1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : M33 10 // Version : 1 11 // Bus type : apb 12 // Description : TEAL registers accessible through the debug interface 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_M33_H 15 #define _HARDWARE_REGS_M33_H 16 // ============================================================================= 17 // Register : M33_ITM_STIM0 18 // Description : Provides the interface for generating Instrumentation packets 19 #define M33_ITM_STIM0_OFFSET _u(0x00000000) 20 #define M33_ITM_STIM0_BITS _u(0xffffffff) 21 #define M33_ITM_STIM0_RESET _u(0x00000000) 22 // ----------------------------------------------------------------------------- 23 // Field : M33_ITM_STIM0_STIMULUS 24 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 25 // Instrumentation packet. The size of write access determines the 26 // type of Instrumentation packet generated. 27 #define M33_ITM_STIM0_STIMULUS_RESET _u(0x00000000) 28 #define M33_ITM_STIM0_STIMULUS_BITS _u(0xffffffff) 29 #define M33_ITM_STIM0_STIMULUS_MSB _u(31) 30 #define M33_ITM_STIM0_STIMULUS_LSB _u(0) 31 #define M33_ITM_STIM0_STIMULUS_ACCESS "RW" 32 // ============================================================================= 33 // Register : M33_ITM_STIM1 34 // Description : Provides the interface for generating Instrumentation packets 35 #define M33_ITM_STIM1_OFFSET _u(0x00000004) 36 #define M33_ITM_STIM1_BITS _u(0xffffffff) 37 #define M33_ITM_STIM1_RESET _u(0x00000000) 38 // ----------------------------------------------------------------------------- 39 // Field : M33_ITM_STIM1_STIMULUS 40 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 41 // Instrumentation packet. The size of write access determines the 42 // type of Instrumentation packet generated. 43 #define M33_ITM_STIM1_STIMULUS_RESET _u(0x00000000) 44 #define M33_ITM_STIM1_STIMULUS_BITS _u(0xffffffff) 45 #define M33_ITM_STIM1_STIMULUS_MSB _u(31) 46 #define M33_ITM_STIM1_STIMULUS_LSB _u(0) 47 #define M33_ITM_STIM1_STIMULUS_ACCESS "RW" 48 // ============================================================================= 49 // Register : M33_ITM_STIM2 50 // Description : Provides the interface for generating Instrumentation packets 51 #define M33_ITM_STIM2_OFFSET _u(0x00000008) 52 #define M33_ITM_STIM2_BITS _u(0xffffffff) 53 #define M33_ITM_STIM2_RESET _u(0x00000000) 54 // ----------------------------------------------------------------------------- 55 // Field : M33_ITM_STIM2_STIMULUS 56 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 57 // Instrumentation packet. The size of write access determines the 58 // type of Instrumentation packet generated. 59 #define M33_ITM_STIM2_STIMULUS_RESET _u(0x00000000) 60 #define M33_ITM_STIM2_STIMULUS_BITS _u(0xffffffff) 61 #define M33_ITM_STIM2_STIMULUS_MSB _u(31) 62 #define M33_ITM_STIM2_STIMULUS_LSB _u(0) 63 #define M33_ITM_STIM2_STIMULUS_ACCESS "RW" 64 // ============================================================================= 65 // Register : M33_ITM_STIM3 66 // Description : Provides the interface for generating Instrumentation packets 67 #define M33_ITM_STIM3_OFFSET _u(0x0000000c) 68 #define M33_ITM_STIM3_BITS _u(0xffffffff) 69 #define M33_ITM_STIM3_RESET _u(0x00000000) 70 // ----------------------------------------------------------------------------- 71 // Field : M33_ITM_STIM3_STIMULUS 72 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 73 // Instrumentation packet. The size of write access determines the 74 // type of Instrumentation packet generated. 75 #define M33_ITM_STIM3_STIMULUS_RESET _u(0x00000000) 76 #define M33_ITM_STIM3_STIMULUS_BITS _u(0xffffffff) 77 #define M33_ITM_STIM3_STIMULUS_MSB _u(31) 78 #define M33_ITM_STIM3_STIMULUS_LSB _u(0) 79 #define M33_ITM_STIM3_STIMULUS_ACCESS "RW" 80 // ============================================================================= 81 // Register : M33_ITM_STIM4 82 // Description : Provides the interface for generating Instrumentation packets 83 #define M33_ITM_STIM4_OFFSET _u(0x00000010) 84 #define M33_ITM_STIM4_BITS _u(0xffffffff) 85 #define M33_ITM_STIM4_RESET _u(0x00000000) 86 // ----------------------------------------------------------------------------- 87 // Field : M33_ITM_STIM4_STIMULUS 88 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 89 // Instrumentation packet. The size of write access determines the 90 // type of Instrumentation packet generated. 91 #define M33_ITM_STIM4_STIMULUS_RESET _u(0x00000000) 92 #define M33_ITM_STIM4_STIMULUS_BITS _u(0xffffffff) 93 #define M33_ITM_STIM4_STIMULUS_MSB _u(31) 94 #define M33_ITM_STIM4_STIMULUS_LSB _u(0) 95 #define M33_ITM_STIM4_STIMULUS_ACCESS "RW" 96 // ============================================================================= 97 // Register : M33_ITM_STIM5 98 // Description : Provides the interface for generating Instrumentation packets 99 #define M33_ITM_STIM5_OFFSET _u(0x00000014) 100 #define M33_ITM_STIM5_BITS _u(0xffffffff) 101 #define M33_ITM_STIM5_RESET _u(0x00000000) 102 // ----------------------------------------------------------------------------- 103 // Field : M33_ITM_STIM5_STIMULUS 104 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 105 // Instrumentation packet. The size of write access determines the 106 // type of Instrumentation packet generated. 107 #define M33_ITM_STIM5_STIMULUS_RESET _u(0x00000000) 108 #define M33_ITM_STIM5_STIMULUS_BITS _u(0xffffffff) 109 #define M33_ITM_STIM5_STIMULUS_MSB _u(31) 110 #define M33_ITM_STIM5_STIMULUS_LSB _u(0) 111 #define M33_ITM_STIM5_STIMULUS_ACCESS "RW" 112 // ============================================================================= 113 // Register : M33_ITM_STIM6 114 // Description : Provides the interface for generating Instrumentation packets 115 #define M33_ITM_STIM6_OFFSET _u(0x00000018) 116 #define M33_ITM_STIM6_BITS _u(0xffffffff) 117 #define M33_ITM_STIM6_RESET _u(0x00000000) 118 // ----------------------------------------------------------------------------- 119 // Field : M33_ITM_STIM6_STIMULUS 120 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 121 // Instrumentation packet. The size of write access determines the 122 // type of Instrumentation packet generated. 123 #define M33_ITM_STIM6_STIMULUS_RESET _u(0x00000000) 124 #define M33_ITM_STIM6_STIMULUS_BITS _u(0xffffffff) 125 #define M33_ITM_STIM6_STIMULUS_MSB _u(31) 126 #define M33_ITM_STIM6_STIMULUS_LSB _u(0) 127 #define M33_ITM_STIM6_STIMULUS_ACCESS "RW" 128 // ============================================================================= 129 // Register : M33_ITM_STIM7 130 // Description : Provides the interface for generating Instrumentation packets 131 #define M33_ITM_STIM7_OFFSET _u(0x0000001c) 132 #define M33_ITM_STIM7_BITS _u(0xffffffff) 133 #define M33_ITM_STIM7_RESET _u(0x00000000) 134 // ----------------------------------------------------------------------------- 135 // Field : M33_ITM_STIM7_STIMULUS 136 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 137 // Instrumentation packet. The size of write access determines the 138 // type of Instrumentation packet generated. 139 #define M33_ITM_STIM7_STIMULUS_RESET _u(0x00000000) 140 #define M33_ITM_STIM7_STIMULUS_BITS _u(0xffffffff) 141 #define M33_ITM_STIM7_STIMULUS_MSB _u(31) 142 #define M33_ITM_STIM7_STIMULUS_LSB _u(0) 143 #define M33_ITM_STIM7_STIMULUS_ACCESS "RW" 144 // ============================================================================= 145 // Register : M33_ITM_STIM8 146 // Description : Provides the interface for generating Instrumentation packets 147 #define M33_ITM_STIM8_OFFSET _u(0x00000020) 148 #define M33_ITM_STIM8_BITS _u(0xffffffff) 149 #define M33_ITM_STIM8_RESET _u(0x00000000) 150 // ----------------------------------------------------------------------------- 151 // Field : M33_ITM_STIM8_STIMULUS 152 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 153 // Instrumentation packet. The size of write access determines the 154 // type of Instrumentation packet generated. 155 #define M33_ITM_STIM8_STIMULUS_RESET _u(0x00000000) 156 #define M33_ITM_STIM8_STIMULUS_BITS _u(0xffffffff) 157 #define M33_ITM_STIM8_STIMULUS_MSB _u(31) 158 #define M33_ITM_STIM8_STIMULUS_LSB _u(0) 159 #define M33_ITM_STIM8_STIMULUS_ACCESS "RW" 160 // ============================================================================= 161 // Register : M33_ITM_STIM9 162 // Description : Provides the interface for generating Instrumentation packets 163 #define M33_ITM_STIM9_OFFSET _u(0x00000024) 164 #define M33_ITM_STIM9_BITS _u(0xffffffff) 165 #define M33_ITM_STIM9_RESET _u(0x00000000) 166 // ----------------------------------------------------------------------------- 167 // Field : M33_ITM_STIM9_STIMULUS 168 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 169 // Instrumentation packet. The size of write access determines the 170 // type of Instrumentation packet generated. 171 #define M33_ITM_STIM9_STIMULUS_RESET _u(0x00000000) 172 #define M33_ITM_STIM9_STIMULUS_BITS _u(0xffffffff) 173 #define M33_ITM_STIM9_STIMULUS_MSB _u(31) 174 #define M33_ITM_STIM9_STIMULUS_LSB _u(0) 175 #define M33_ITM_STIM9_STIMULUS_ACCESS "RW" 176 // ============================================================================= 177 // Register : M33_ITM_STIM10 178 // Description : Provides the interface for generating Instrumentation packets 179 #define M33_ITM_STIM10_OFFSET _u(0x00000028) 180 #define M33_ITM_STIM10_BITS _u(0xffffffff) 181 #define M33_ITM_STIM10_RESET _u(0x00000000) 182 // ----------------------------------------------------------------------------- 183 // Field : M33_ITM_STIM10_STIMULUS 184 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 185 // Instrumentation packet. The size of write access determines the 186 // type of Instrumentation packet generated. 187 #define M33_ITM_STIM10_STIMULUS_RESET _u(0x00000000) 188 #define M33_ITM_STIM10_STIMULUS_BITS _u(0xffffffff) 189 #define M33_ITM_STIM10_STIMULUS_MSB _u(31) 190 #define M33_ITM_STIM10_STIMULUS_LSB _u(0) 191 #define M33_ITM_STIM10_STIMULUS_ACCESS "RW" 192 // ============================================================================= 193 // Register : M33_ITM_STIM11 194 // Description : Provides the interface for generating Instrumentation packets 195 #define M33_ITM_STIM11_OFFSET _u(0x0000002c) 196 #define M33_ITM_STIM11_BITS _u(0xffffffff) 197 #define M33_ITM_STIM11_RESET _u(0x00000000) 198 // ----------------------------------------------------------------------------- 199 // Field : M33_ITM_STIM11_STIMULUS 200 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 201 // Instrumentation packet. The size of write access determines the 202 // type of Instrumentation packet generated. 203 #define M33_ITM_STIM11_STIMULUS_RESET _u(0x00000000) 204 #define M33_ITM_STIM11_STIMULUS_BITS _u(0xffffffff) 205 #define M33_ITM_STIM11_STIMULUS_MSB _u(31) 206 #define M33_ITM_STIM11_STIMULUS_LSB _u(0) 207 #define M33_ITM_STIM11_STIMULUS_ACCESS "RW" 208 // ============================================================================= 209 // Register : M33_ITM_STIM12 210 // Description : Provides the interface for generating Instrumentation packets 211 #define M33_ITM_STIM12_OFFSET _u(0x00000030) 212 #define M33_ITM_STIM12_BITS _u(0xffffffff) 213 #define M33_ITM_STIM12_RESET _u(0x00000000) 214 // ----------------------------------------------------------------------------- 215 // Field : M33_ITM_STIM12_STIMULUS 216 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 217 // Instrumentation packet. The size of write access determines the 218 // type of Instrumentation packet generated. 219 #define M33_ITM_STIM12_STIMULUS_RESET _u(0x00000000) 220 #define M33_ITM_STIM12_STIMULUS_BITS _u(0xffffffff) 221 #define M33_ITM_STIM12_STIMULUS_MSB _u(31) 222 #define M33_ITM_STIM12_STIMULUS_LSB _u(0) 223 #define M33_ITM_STIM12_STIMULUS_ACCESS "RW" 224 // ============================================================================= 225 // Register : M33_ITM_STIM13 226 // Description : Provides the interface for generating Instrumentation packets 227 #define M33_ITM_STIM13_OFFSET _u(0x00000034) 228 #define M33_ITM_STIM13_BITS _u(0xffffffff) 229 #define M33_ITM_STIM13_RESET _u(0x00000000) 230 // ----------------------------------------------------------------------------- 231 // Field : M33_ITM_STIM13_STIMULUS 232 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 233 // Instrumentation packet. The size of write access determines the 234 // type of Instrumentation packet generated. 235 #define M33_ITM_STIM13_STIMULUS_RESET _u(0x00000000) 236 #define M33_ITM_STIM13_STIMULUS_BITS _u(0xffffffff) 237 #define M33_ITM_STIM13_STIMULUS_MSB _u(31) 238 #define M33_ITM_STIM13_STIMULUS_LSB _u(0) 239 #define M33_ITM_STIM13_STIMULUS_ACCESS "RW" 240 // ============================================================================= 241 // Register : M33_ITM_STIM14 242 // Description : Provides the interface for generating Instrumentation packets 243 #define M33_ITM_STIM14_OFFSET _u(0x00000038) 244 #define M33_ITM_STIM14_BITS _u(0xffffffff) 245 #define M33_ITM_STIM14_RESET _u(0x00000000) 246 // ----------------------------------------------------------------------------- 247 // Field : M33_ITM_STIM14_STIMULUS 248 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 249 // Instrumentation packet. The size of write access determines the 250 // type of Instrumentation packet generated. 251 #define M33_ITM_STIM14_STIMULUS_RESET _u(0x00000000) 252 #define M33_ITM_STIM14_STIMULUS_BITS _u(0xffffffff) 253 #define M33_ITM_STIM14_STIMULUS_MSB _u(31) 254 #define M33_ITM_STIM14_STIMULUS_LSB _u(0) 255 #define M33_ITM_STIM14_STIMULUS_ACCESS "RW" 256 // ============================================================================= 257 // Register : M33_ITM_STIM15 258 // Description : Provides the interface for generating Instrumentation packets 259 #define M33_ITM_STIM15_OFFSET _u(0x0000003c) 260 #define M33_ITM_STIM15_BITS _u(0xffffffff) 261 #define M33_ITM_STIM15_RESET _u(0x00000000) 262 // ----------------------------------------------------------------------------- 263 // Field : M33_ITM_STIM15_STIMULUS 264 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 265 // Instrumentation packet. The size of write access determines the 266 // type of Instrumentation packet generated. 267 #define M33_ITM_STIM15_STIMULUS_RESET _u(0x00000000) 268 #define M33_ITM_STIM15_STIMULUS_BITS _u(0xffffffff) 269 #define M33_ITM_STIM15_STIMULUS_MSB _u(31) 270 #define M33_ITM_STIM15_STIMULUS_LSB _u(0) 271 #define M33_ITM_STIM15_STIMULUS_ACCESS "RW" 272 // ============================================================================= 273 // Register : M33_ITM_STIM16 274 // Description : Provides the interface for generating Instrumentation packets 275 #define M33_ITM_STIM16_OFFSET _u(0x00000040) 276 #define M33_ITM_STIM16_BITS _u(0xffffffff) 277 #define M33_ITM_STIM16_RESET _u(0x00000000) 278 // ----------------------------------------------------------------------------- 279 // Field : M33_ITM_STIM16_STIMULUS 280 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 281 // Instrumentation packet. The size of write access determines the 282 // type of Instrumentation packet generated. 283 #define M33_ITM_STIM16_STIMULUS_RESET _u(0x00000000) 284 #define M33_ITM_STIM16_STIMULUS_BITS _u(0xffffffff) 285 #define M33_ITM_STIM16_STIMULUS_MSB _u(31) 286 #define M33_ITM_STIM16_STIMULUS_LSB _u(0) 287 #define M33_ITM_STIM16_STIMULUS_ACCESS "RW" 288 // ============================================================================= 289 // Register : M33_ITM_STIM17 290 // Description : Provides the interface for generating Instrumentation packets 291 #define M33_ITM_STIM17_OFFSET _u(0x00000044) 292 #define M33_ITM_STIM17_BITS _u(0xffffffff) 293 #define M33_ITM_STIM17_RESET _u(0x00000000) 294 // ----------------------------------------------------------------------------- 295 // Field : M33_ITM_STIM17_STIMULUS 296 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 297 // Instrumentation packet. The size of write access determines the 298 // type of Instrumentation packet generated. 299 #define M33_ITM_STIM17_STIMULUS_RESET _u(0x00000000) 300 #define M33_ITM_STIM17_STIMULUS_BITS _u(0xffffffff) 301 #define M33_ITM_STIM17_STIMULUS_MSB _u(31) 302 #define M33_ITM_STIM17_STIMULUS_LSB _u(0) 303 #define M33_ITM_STIM17_STIMULUS_ACCESS "RW" 304 // ============================================================================= 305 // Register : M33_ITM_STIM18 306 // Description : Provides the interface for generating Instrumentation packets 307 #define M33_ITM_STIM18_OFFSET _u(0x00000048) 308 #define M33_ITM_STIM18_BITS _u(0xffffffff) 309 #define M33_ITM_STIM18_RESET _u(0x00000000) 310 // ----------------------------------------------------------------------------- 311 // Field : M33_ITM_STIM18_STIMULUS 312 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 313 // Instrumentation packet. The size of write access determines the 314 // type of Instrumentation packet generated. 315 #define M33_ITM_STIM18_STIMULUS_RESET _u(0x00000000) 316 #define M33_ITM_STIM18_STIMULUS_BITS _u(0xffffffff) 317 #define M33_ITM_STIM18_STIMULUS_MSB _u(31) 318 #define M33_ITM_STIM18_STIMULUS_LSB _u(0) 319 #define M33_ITM_STIM18_STIMULUS_ACCESS "RW" 320 // ============================================================================= 321 // Register : M33_ITM_STIM19 322 // Description : Provides the interface for generating Instrumentation packets 323 #define M33_ITM_STIM19_OFFSET _u(0x0000004c) 324 #define M33_ITM_STIM19_BITS _u(0xffffffff) 325 #define M33_ITM_STIM19_RESET _u(0x00000000) 326 // ----------------------------------------------------------------------------- 327 // Field : M33_ITM_STIM19_STIMULUS 328 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 329 // Instrumentation packet. The size of write access determines the 330 // type of Instrumentation packet generated. 331 #define M33_ITM_STIM19_STIMULUS_RESET _u(0x00000000) 332 #define M33_ITM_STIM19_STIMULUS_BITS _u(0xffffffff) 333 #define M33_ITM_STIM19_STIMULUS_MSB _u(31) 334 #define M33_ITM_STIM19_STIMULUS_LSB _u(0) 335 #define M33_ITM_STIM19_STIMULUS_ACCESS "RW" 336 // ============================================================================= 337 // Register : M33_ITM_STIM20 338 // Description : Provides the interface for generating Instrumentation packets 339 #define M33_ITM_STIM20_OFFSET _u(0x00000050) 340 #define M33_ITM_STIM20_BITS _u(0xffffffff) 341 #define M33_ITM_STIM20_RESET _u(0x00000000) 342 // ----------------------------------------------------------------------------- 343 // Field : M33_ITM_STIM20_STIMULUS 344 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 345 // Instrumentation packet. The size of write access determines the 346 // type of Instrumentation packet generated. 347 #define M33_ITM_STIM20_STIMULUS_RESET _u(0x00000000) 348 #define M33_ITM_STIM20_STIMULUS_BITS _u(0xffffffff) 349 #define M33_ITM_STIM20_STIMULUS_MSB _u(31) 350 #define M33_ITM_STIM20_STIMULUS_LSB _u(0) 351 #define M33_ITM_STIM20_STIMULUS_ACCESS "RW" 352 // ============================================================================= 353 // Register : M33_ITM_STIM21 354 // Description : Provides the interface for generating Instrumentation packets 355 #define M33_ITM_STIM21_OFFSET _u(0x00000054) 356 #define M33_ITM_STIM21_BITS _u(0xffffffff) 357 #define M33_ITM_STIM21_RESET _u(0x00000000) 358 // ----------------------------------------------------------------------------- 359 // Field : M33_ITM_STIM21_STIMULUS 360 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 361 // Instrumentation packet. The size of write access determines the 362 // type of Instrumentation packet generated. 363 #define M33_ITM_STIM21_STIMULUS_RESET _u(0x00000000) 364 #define M33_ITM_STIM21_STIMULUS_BITS _u(0xffffffff) 365 #define M33_ITM_STIM21_STIMULUS_MSB _u(31) 366 #define M33_ITM_STIM21_STIMULUS_LSB _u(0) 367 #define M33_ITM_STIM21_STIMULUS_ACCESS "RW" 368 // ============================================================================= 369 // Register : M33_ITM_STIM22 370 // Description : Provides the interface for generating Instrumentation packets 371 #define M33_ITM_STIM22_OFFSET _u(0x00000058) 372 #define M33_ITM_STIM22_BITS _u(0xffffffff) 373 #define M33_ITM_STIM22_RESET _u(0x00000000) 374 // ----------------------------------------------------------------------------- 375 // Field : M33_ITM_STIM22_STIMULUS 376 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 377 // Instrumentation packet. The size of write access determines the 378 // type of Instrumentation packet generated. 379 #define M33_ITM_STIM22_STIMULUS_RESET _u(0x00000000) 380 #define M33_ITM_STIM22_STIMULUS_BITS _u(0xffffffff) 381 #define M33_ITM_STIM22_STIMULUS_MSB _u(31) 382 #define M33_ITM_STIM22_STIMULUS_LSB _u(0) 383 #define M33_ITM_STIM22_STIMULUS_ACCESS "RW" 384 // ============================================================================= 385 // Register : M33_ITM_STIM23 386 // Description : Provides the interface for generating Instrumentation packets 387 #define M33_ITM_STIM23_OFFSET _u(0x0000005c) 388 #define M33_ITM_STIM23_BITS _u(0xffffffff) 389 #define M33_ITM_STIM23_RESET _u(0x00000000) 390 // ----------------------------------------------------------------------------- 391 // Field : M33_ITM_STIM23_STIMULUS 392 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 393 // Instrumentation packet. The size of write access determines the 394 // type of Instrumentation packet generated. 395 #define M33_ITM_STIM23_STIMULUS_RESET _u(0x00000000) 396 #define M33_ITM_STIM23_STIMULUS_BITS _u(0xffffffff) 397 #define M33_ITM_STIM23_STIMULUS_MSB _u(31) 398 #define M33_ITM_STIM23_STIMULUS_LSB _u(0) 399 #define M33_ITM_STIM23_STIMULUS_ACCESS "RW" 400 // ============================================================================= 401 // Register : M33_ITM_STIM24 402 // Description : Provides the interface for generating Instrumentation packets 403 #define M33_ITM_STIM24_OFFSET _u(0x00000060) 404 #define M33_ITM_STIM24_BITS _u(0xffffffff) 405 #define M33_ITM_STIM24_RESET _u(0x00000000) 406 // ----------------------------------------------------------------------------- 407 // Field : M33_ITM_STIM24_STIMULUS 408 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 409 // Instrumentation packet. The size of write access determines the 410 // type of Instrumentation packet generated. 411 #define M33_ITM_STIM24_STIMULUS_RESET _u(0x00000000) 412 #define M33_ITM_STIM24_STIMULUS_BITS _u(0xffffffff) 413 #define M33_ITM_STIM24_STIMULUS_MSB _u(31) 414 #define M33_ITM_STIM24_STIMULUS_LSB _u(0) 415 #define M33_ITM_STIM24_STIMULUS_ACCESS "RW" 416 // ============================================================================= 417 // Register : M33_ITM_STIM25 418 // Description : Provides the interface for generating Instrumentation packets 419 #define M33_ITM_STIM25_OFFSET _u(0x00000064) 420 #define M33_ITM_STIM25_BITS _u(0xffffffff) 421 #define M33_ITM_STIM25_RESET _u(0x00000000) 422 // ----------------------------------------------------------------------------- 423 // Field : M33_ITM_STIM25_STIMULUS 424 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 425 // Instrumentation packet. The size of write access determines the 426 // type of Instrumentation packet generated. 427 #define M33_ITM_STIM25_STIMULUS_RESET _u(0x00000000) 428 #define M33_ITM_STIM25_STIMULUS_BITS _u(0xffffffff) 429 #define M33_ITM_STIM25_STIMULUS_MSB _u(31) 430 #define M33_ITM_STIM25_STIMULUS_LSB _u(0) 431 #define M33_ITM_STIM25_STIMULUS_ACCESS "RW" 432 // ============================================================================= 433 // Register : M33_ITM_STIM26 434 // Description : Provides the interface for generating Instrumentation packets 435 #define M33_ITM_STIM26_OFFSET _u(0x00000068) 436 #define M33_ITM_STIM26_BITS _u(0xffffffff) 437 #define M33_ITM_STIM26_RESET _u(0x00000000) 438 // ----------------------------------------------------------------------------- 439 // Field : M33_ITM_STIM26_STIMULUS 440 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 441 // Instrumentation packet. The size of write access determines the 442 // type of Instrumentation packet generated. 443 #define M33_ITM_STIM26_STIMULUS_RESET _u(0x00000000) 444 #define M33_ITM_STIM26_STIMULUS_BITS _u(0xffffffff) 445 #define M33_ITM_STIM26_STIMULUS_MSB _u(31) 446 #define M33_ITM_STIM26_STIMULUS_LSB _u(0) 447 #define M33_ITM_STIM26_STIMULUS_ACCESS "RW" 448 // ============================================================================= 449 // Register : M33_ITM_STIM27 450 // Description : Provides the interface for generating Instrumentation packets 451 #define M33_ITM_STIM27_OFFSET _u(0x0000006c) 452 #define M33_ITM_STIM27_BITS _u(0xffffffff) 453 #define M33_ITM_STIM27_RESET _u(0x00000000) 454 // ----------------------------------------------------------------------------- 455 // Field : M33_ITM_STIM27_STIMULUS 456 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 457 // Instrumentation packet. The size of write access determines the 458 // type of Instrumentation packet generated. 459 #define M33_ITM_STIM27_STIMULUS_RESET _u(0x00000000) 460 #define M33_ITM_STIM27_STIMULUS_BITS _u(0xffffffff) 461 #define M33_ITM_STIM27_STIMULUS_MSB _u(31) 462 #define M33_ITM_STIM27_STIMULUS_LSB _u(0) 463 #define M33_ITM_STIM27_STIMULUS_ACCESS "RW" 464 // ============================================================================= 465 // Register : M33_ITM_STIM28 466 // Description : Provides the interface for generating Instrumentation packets 467 #define M33_ITM_STIM28_OFFSET _u(0x00000070) 468 #define M33_ITM_STIM28_BITS _u(0xffffffff) 469 #define M33_ITM_STIM28_RESET _u(0x00000000) 470 // ----------------------------------------------------------------------------- 471 // Field : M33_ITM_STIM28_STIMULUS 472 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 473 // Instrumentation packet. The size of write access determines the 474 // type of Instrumentation packet generated. 475 #define M33_ITM_STIM28_STIMULUS_RESET _u(0x00000000) 476 #define M33_ITM_STIM28_STIMULUS_BITS _u(0xffffffff) 477 #define M33_ITM_STIM28_STIMULUS_MSB _u(31) 478 #define M33_ITM_STIM28_STIMULUS_LSB _u(0) 479 #define M33_ITM_STIM28_STIMULUS_ACCESS "RW" 480 // ============================================================================= 481 // Register : M33_ITM_STIM29 482 // Description : Provides the interface for generating Instrumentation packets 483 #define M33_ITM_STIM29_OFFSET _u(0x00000074) 484 #define M33_ITM_STIM29_BITS _u(0xffffffff) 485 #define M33_ITM_STIM29_RESET _u(0x00000000) 486 // ----------------------------------------------------------------------------- 487 // Field : M33_ITM_STIM29_STIMULUS 488 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 489 // Instrumentation packet. The size of write access determines the 490 // type of Instrumentation packet generated. 491 #define M33_ITM_STIM29_STIMULUS_RESET _u(0x00000000) 492 #define M33_ITM_STIM29_STIMULUS_BITS _u(0xffffffff) 493 #define M33_ITM_STIM29_STIMULUS_MSB _u(31) 494 #define M33_ITM_STIM29_STIMULUS_LSB _u(0) 495 #define M33_ITM_STIM29_STIMULUS_ACCESS "RW" 496 // ============================================================================= 497 // Register : M33_ITM_STIM30 498 // Description : Provides the interface for generating Instrumentation packets 499 #define M33_ITM_STIM30_OFFSET _u(0x00000078) 500 #define M33_ITM_STIM30_BITS _u(0xffffffff) 501 #define M33_ITM_STIM30_RESET _u(0x00000000) 502 // ----------------------------------------------------------------------------- 503 // Field : M33_ITM_STIM30_STIMULUS 504 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 505 // Instrumentation packet. The size of write access determines the 506 // type of Instrumentation packet generated. 507 #define M33_ITM_STIM30_STIMULUS_RESET _u(0x00000000) 508 #define M33_ITM_STIM30_STIMULUS_BITS _u(0xffffffff) 509 #define M33_ITM_STIM30_STIMULUS_MSB _u(31) 510 #define M33_ITM_STIM30_STIMULUS_LSB _u(0) 511 #define M33_ITM_STIM30_STIMULUS_ACCESS "RW" 512 // ============================================================================= 513 // Register : M33_ITM_STIM31 514 // Description : Provides the interface for generating Instrumentation packets 515 #define M33_ITM_STIM31_OFFSET _u(0x0000007c) 516 #define M33_ITM_STIM31_BITS _u(0xffffffff) 517 #define M33_ITM_STIM31_RESET _u(0x00000000) 518 // ----------------------------------------------------------------------------- 519 // Field : M33_ITM_STIM31_STIMULUS 520 // Description : Data to write to the Stimulus Port FIFO, for forwarding as an 521 // Instrumentation packet. The size of write access determines the 522 // type of Instrumentation packet generated. 523 #define M33_ITM_STIM31_STIMULUS_RESET _u(0x00000000) 524 #define M33_ITM_STIM31_STIMULUS_BITS _u(0xffffffff) 525 #define M33_ITM_STIM31_STIMULUS_MSB _u(31) 526 #define M33_ITM_STIM31_STIMULUS_LSB _u(0) 527 #define M33_ITM_STIM31_STIMULUS_ACCESS "RW" 528 // ============================================================================= 529 // Register : M33_ITM_TER0 530 // Description : Provide an individual enable bit for each ITM_STIM register 531 #define M33_ITM_TER0_OFFSET _u(0x00000e00) 532 #define M33_ITM_TER0_BITS _u(0xffffffff) 533 #define M33_ITM_TER0_RESET _u(0x00000000) 534 // ----------------------------------------------------------------------------- 535 // Field : M33_ITM_TER0_STIMENA 536 // Description : For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + 537 // m) is enabled 538 #define M33_ITM_TER0_STIMENA_RESET _u(0x00000000) 539 #define M33_ITM_TER0_STIMENA_BITS _u(0xffffffff) 540 #define M33_ITM_TER0_STIMENA_MSB _u(31) 541 #define M33_ITM_TER0_STIMENA_LSB _u(0) 542 #define M33_ITM_TER0_STIMENA_ACCESS "RW" 543 // ============================================================================= 544 // Register : M33_ITM_TPR 545 // Description : Controls which stimulus ports can be accessed by unprivileged 546 // code 547 #define M33_ITM_TPR_OFFSET _u(0x00000e40) 548 #define M33_ITM_TPR_BITS _u(0x0000000f) 549 #define M33_ITM_TPR_RESET _u(0x00000000) 550 // ----------------------------------------------------------------------------- 551 // Field : M33_ITM_TPR_PRIVMASK 552 // Description : Bit mask to enable tracing on ITM stimulus ports 553 #define M33_ITM_TPR_PRIVMASK_RESET _u(0x0) 554 #define M33_ITM_TPR_PRIVMASK_BITS _u(0x0000000f) 555 #define M33_ITM_TPR_PRIVMASK_MSB _u(3) 556 #define M33_ITM_TPR_PRIVMASK_LSB _u(0) 557 #define M33_ITM_TPR_PRIVMASK_ACCESS "RW" 558 // ============================================================================= 559 // Register : M33_ITM_TCR 560 // Description : Configures and controls transfers through the ITM interface 561 #define M33_ITM_TCR_OFFSET _u(0x00000e80) 562 #define M33_ITM_TCR_BITS _u(0x00ff0f3f) 563 #define M33_ITM_TCR_RESET _u(0x00000000) 564 // ----------------------------------------------------------------------------- 565 // Field : M33_ITM_TCR_BUSY 566 // Description : Indicates whether the ITM is currently processing events 567 #define M33_ITM_TCR_BUSY_RESET _u(0x0) 568 #define M33_ITM_TCR_BUSY_BITS _u(0x00800000) 569 #define M33_ITM_TCR_BUSY_MSB _u(23) 570 #define M33_ITM_TCR_BUSY_LSB _u(23) 571 #define M33_ITM_TCR_BUSY_ACCESS "RO" 572 // ----------------------------------------------------------------------------- 573 // Field : M33_ITM_TCR_TRACEBUSID 574 // Description : Identifier for multi-source trace stream formatting. If multi- 575 // source trace is in use, the debugger must write a unique non- 576 // zero trace ID value to this field 577 #define M33_ITM_TCR_TRACEBUSID_RESET _u(0x00) 578 #define M33_ITM_TCR_TRACEBUSID_BITS _u(0x007f0000) 579 #define M33_ITM_TCR_TRACEBUSID_MSB _u(22) 580 #define M33_ITM_TCR_TRACEBUSID_LSB _u(16) 581 #define M33_ITM_TCR_TRACEBUSID_ACCESS "RW" 582 // ----------------------------------------------------------------------------- 583 // Field : M33_ITM_TCR_GTSFREQ 584 // Description : Defines how often the ITM generates a global timestamp, based 585 // on the global timestamp clock frequency, or disables generation 586 // of global timestamps 587 #define M33_ITM_TCR_GTSFREQ_RESET _u(0x0) 588 #define M33_ITM_TCR_GTSFREQ_BITS _u(0x00000c00) 589 #define M33_ITM_TCR_GTSFREQ_MSB _u(11) 590 #define M33_ITM_TCR_GTSFREQ_LSB _u(10) 591 #define M33_ITM_TCR_GTSFREQ_ACCESS "RW" 592 // ----------------------------------------------------------------------------- 593 // Field : M33_ITM_TCR_TSPRESCALE 594 // Description : Local timestamp prescaler, used with the trace packet reference 595 // clock 596 #define M33_ITM_TCR_TSPRESCALE_RESET _u(0x0) 597 #define M33_ITM_TCR_TSPRESCALE_BITS _u(0x00000300) 598 #define M33_ITM_TCR_TSPRESCALE_MSB _u(9) 599 #define M33_ITM_TCR_TSPRESCALE_LSB _u(8) 600 #define M33_ITM_TCR_TSPRESCALE_ACCESS "RW" 601 // ----------------------------------------------------------------------------- 602 // Field : M33_ITM_TCR_STALLENA 603 // Description : Stall the PE to guarantee delivery of Data Trace packets. 604 #define M33_ITM_TCR_STALLENA_RESET _u(0x0) 605 #define M33_ITM_TCR_STALLENA_BITS _u(0x00000020) 606 #define M33_ITM_TCR_STALLENA_MSB _u(5) 607 #define M33_ITM_TCR_STALLENA_LSB _u(5) 608 #define M33_ITM_TCR_STALLENA_ACCESS "RW" 609 // ----------------------------------------------------------------------------- 610 // Field : M33_ITM_TCR_SWOENA 611 // Description : Enables asynchronous clocking of the timestamp counter 612 #define M33_ITM_TCR_SWOENA_RESET _u(0x0) 613 #define M33_ITM_TCR_SWOENA_BITS _u(0x00000010) 614 #define M33_ITM_TCR_SWOENA_MSB _u(4) 615 #define M33_ITM_TCR_SWOENA_LSB _u(4) 616 #define M33_ITM_TCR_SWOENA_ACCESS "RW" 617 // ----------------------------------------------------------------------------- 618 // Field : M33_ITM_TCR_TXENA 619 // Description : Enables forwarding of hardware event packet from the DWT unit 620 // to the ITM for output to the TPIU 621 #define M33_ITM_TCR_TXENA_RESET _u(0x0) 622 #define M33_ITM_TCR_TXENA_BITS _u(0x00000008) 623 #define M33_ITM_TCR_TXENA_MSB _u(3) 624 #define M33_ITM_TCR_TXENA_LSB _u(3) 625 #define M33_ITM_TCR_TXENA_ACCESS "RW" 626 // ----------------------------------------------------------------------------- 627 // Field : M33_ITM_TCR_SYNCENA 628 // Description : Enables Synchronization packet transmission for a synchronous 629 // TPIU 630 #define M33_ITM_TCR_SYNCENA_RESET _u(0x0) 631 #define M33_ITM_TCR_SYNCENA_BITS _u(0x00000004) 632 #define M33_ITM_TCR_SYNCENA_MSB _u(2) 633 #define M33_ITM_TCR_SYNCENA_LSB _u(2) 634 #define M33_ITM_TCR_SYNCENA_ACCESS "RW" 635 // ----------------------------------------------------------------------------- 636 // Field : M33_ITM_TCR_TSENA 637 // Description : Enables Local timestamp generation 638 #define M33_ITM_TCR_TSENA_RESET _u(0x0) 639 #define M33_ITM_TCR_TSENA_BITS _u(0x00000002) 640 #define M33_ITM_TCR_TSENA_MSB _u(1) 641 #define M33_ITM_TCR_TSENA_LSB _u(1) 642 #define M33_ITM_TCR_TSENA_ACCESS "RW" 643 // ----------------------------------------------------------------------------- 644 // Field : M33_ITM_TCR_ITMENA 645 // Description : Enables the ITM 646 #define M33_ITM_TCR_ITMENA_RESET _u(0x0) 647 #define M33_ITM_TCR_ITMENA_BITS _u(0x00000001) 648 #define M33_ITM_TCR_ITMENA_MSB _u(0) 649 #define M33_ITM_TCR_ITMENA_LSB _u(0) 650 #define M33_ITM_TCR_ITMENA_ACCESS "RW" 651 // ============================================================================= 652 // Register : M33_INT_ATREADY 653 // Description : Integration Mode: Read ATB Ready 654 #define M33_INT_ATREADY_OFFSET _u(0x00000ef0) 655 #define M33_INT_ATREADY_BITS _u(0x00000003) 656 #define M33_INT_ATREADY_RESET _u(0x00000000) 657 // ----------------------------------------------------------------------------- 658 // Field : M33_INT_ATREADY_AFVALID 659 // Description : A read of this bit returns the value of AFVALID 660 #define M33_INT_ATREADY_AFVALID_RESET _u(0x0) 661 #define M33_INT_ATREADY_AFVALID_BITS _u(0x00000002) 662 #define M33_INT_ATREADY_AFVALID_MSB _u(1) 663 #define M33_INT_ATREADY_AFVALID_LSB _u(1) 664 #define M33_INT_ATREADY_AFVALID_ACCESS "RO" 665 // ----------------------------------------------------------------------------- 666 // Field : M33_INT_ATREADY_ATREADY 667 // Description : A read of this bit returns the value of ATREADY 668 #define M33_INT_ATREADY_ATREADY_RESET _u(0x0) 669 #define M33_INT_ATREADY_ATREADY_BITS _u(0x00000001) 670 #define M33_INT_ATREADY_ATREADY_MSB _u(0) 671 #define M33_INT_ATREADY_ATREADY_LSB _u(0) 672 #define M33_INT_ATREADY_ATREADY_ACCESS "RO" 673 // ============================================================================= 674 // Register : M33_INT_ATVALID 675 // Description : Integration Mode: Write ATB Valid 676 #define M33_INT_ATVALID_OFFSET _u(0x00000ef8) 677 #define M33_INT_ATVALID_BITS _u(0x00000003) 678 #define M33_INT_ATVALID_RESET _u(0x00000000) 679 // ----------------------------------------------------------------------------- 680 // Field : M33_INT_ATVALID_AFREADY 681 // Description : A write to this bit gives the value of AFREADY 682 #define M33_INT_ATVALID_AFREADY_RESET _u(0x0) 683 #define M33_INT_ATVALID_AFREADY_BITS _u(0x00000002) 684 #define M33_INT_ATVALID_AFREADY_MSB _u(1) 685 #define M33_INT_ATVALID_AFREADY_LSB _u(1) 686 #define M33_INT_ATVALID_AFREADY_ACCESS "RW" 687 // ----------------------------------------------------------------------------- 688 // Field : M33_INT_ATVALID_ATREADY 689 // Description : A write to this bit gives the value of ATVALID 690 #define M33_INT_ATVALID_ATREADY_RESET _u(0x0) 691 #define M33_INT_ATVALID_ATREADY_BITS _u(0x00000001) 692 #define M33_INT_ATVALID_ATREADY_MSB _u(0) 693 #define M33_INT_ATVALID_ATREADY_LSB _u(0) 694 #define M33_INT_ATVALID_ATREADY_ACCESS "RW" 695 // ============================================================================= 696 // Register : M33_ITM_ITCTRL 697 // Description : Integration Mode Control Register 698 #define M33_ITM_ITCTRL_OFFSET _u(0x00000f00) 699 #define M33_ITM_ITCTRL_BITS _u(0x00000001) 700 #define M33_ITM_ITCTRL_RESET _u(0x00000000) 701 // ----------------------------------------------------------------------------- 702 // Field : M33_ITM_ITCTRL_IME 703 // Description : Integration mode enable bit - The possible values are: 0 - The 704 // trace unit is not in integration mode. 1 - The trace unit is in 705 // integration mode. This mode enables: A debug agent to perform 706 // topology detection. SoC test software to perform integration 707 // testing. 708 #define M33_ITM_ITCTRL_IME_RESET _u(0x0) 709 #define M33_ITM_ITCTRL_IME_BITS _u(0x00000001) 710 #define M33_ITM_ITCTRL_IME_MSB _u(0) 711 #define M33_ITM_ITCTRL_IME_LSB _u(0) 712 #define M33_ITM_ITCTRL_IME_ACCESS "RW" 713 // ============================================================================= 714 // Register : M33_ITM_DEVARCH 715 // Description : Provides CoreSight discovery information for the ITM 716 #define M33_ITM_DEVARCH_OFFSET _u(0x00000fbc) 717 #define M33_ITM_DEVARCH_BITS _u(0xffffffff) 718 #define M33_ITM_DEVARCH_RESET _u(0x47701a01) 719 // ----------------------------------------------------------------------------- 720 // Field : M33_ITM_DEVARCH_ARCHITECT 721 // Description : Defines the architect of the component. Bits [31:28] are the 722 // JEP106 continuation code (JEP106 bank ID, minus 1) and bits 723 // [27:21] are the JEP106 ID code. 724 #define M33_ITM_DEVARCH_ARCHITECT_RESET _u(0x23b) 725 #define M33_ITM_DEVARCH_ARCHITECT_BITS _u(0xffe00000) 726 #define M33_ITM_DEVARCH_ARCHITECT_MSB _u(31) 727 #define M33_ITM_DEVARCH_ARCHITECT_LSB _u(21) 728 #define M33_ITM_DEVARCH_ARCHITECT_ACCESS "RO" 729 // ----------------------------------------------------------------------------- 730 // Field : M33_ITM_DEVARCH_PRESENT 731 // Description : Defines that the DEVARCH register is present 732 #define M33_ITM_DEVARCH_PRESENT_RESET _u(0x1) 733 #define M33_ITM_DEVARCH_PRESENT_BITS _u(0x00100000) 734 #define M33_ITM_DEVARCH_PRESENT_MSB _u(20) 735 #define M33_ITM_DEVARCH_PRESENT_LSB _u(20) 736 #define M33_ITM_DEVARCH_PRESENT_ACCESS "RO" 737 // ----------------------------------------------------------------------------- 738 // Field : M33_ITM_DEVARCH_REVISION 739 // Description : Defines the architecture revision of the component 740 #define M33_ITM_DEVARCH_REVISION_RESET _u(0x0) 741 #define M33_ITM_DEVARCH_REVISION_BITS _u(0x000f0000) 742 #define M33_ITM_DEVARCH_REVISION_MSB _u(19) 743 #define M33_ITM_DEVARCH_REVISION_LSB _u(16) 744 #define M33_ITM_DEVARCH_REVISION_ACCESS "RO" 745 // ----------------------------------------------------------------------------- 746 // Field : M33_ITM_DEVARCH_ARCHVER 747 // Description : Defines the architecture version of the component 748 #define M33_ITM_DEVARCH_ARCHVER_RESET _u(0x1) 749 #define M33_ITM_DEVARCH_ARCHVER_BITS _u(0x0000f000) 750 #define M33_ITM_DEVARCH_ARCHVER_MSB _u(15) 751 #define M33_ITM_DEVARCH_ARCHVER_LSB _u(12) 752 #define M33_ITM_DEVARCH_ARCHVER_ACCESS "RO" 753 // ----------------------------------------------------------------------------- 754 // Field : M33_ITM_DEVARCH_ARCHPART 755 // Description : Defines the architecture of the component 756 #define M33_ITM_DEVARCH_ARCHPART_RESET _u(0xa01) 757 #define M33_ITM_DEVARCH_ARCHPART_BITS _u(0x00000fff) 758 #define M33_ITM_DEVARCH_ARCHPART_MSB _u(11) 759 #define M33_ITM_DEVARCH_ARCHPART_LSB _u(0) 760 #define M33_ITM_DEVARCH_ARCHPART_ACCESS "RO" 761 // ============================================================================= 762 // Register : M33_ITM_DEVTYPE 763 // Description : Provides CoreSight discovery information for the ITM 764 #define M33_ITM_DEVTYPE_OFFSET _u(0x00000fcc) 765 #define M33_ITM_DEVTYPE_BITS _u(0x000000ff) 766 #define M33_ITM_DEVTYPE_RESET _u(0x00000043) 767 // ----------------------------------------------------------------------------- 768 // Field : M33_ITM_DEVTYPE_SUB 769 // Description : Component sub-type 770 #define M33_ITM_DEVTYPE_SUB_RESET _u(0x4) 771 #define M33_ITM_DEVTYPE_SUB_BITS _u(0x000000f0) 772 #define M33_ITM_DEVTYPE_SUB_MSB _u(7) 773 #define M33_ITM_DEVTYPE_SUB_LSB _u(4) 774 #define M33_ITM_DEVTYPE_SUB_ACCESS "RO" 775 // ----------------------------------------------------------------------------- 776 // Field : M33_ITM_DEVTYPE_MAJOR 777 // Description : Component major type 778 #define M33_ITM_DEVTYPE_MAJOR_RESET _u(0x3) 779 #define M33_ITM_DEVTYPE_MAJOR_BITS _u(0x0000000f) 780 #define M33_ITM_DEVTYPE_MAJOR_MSB _u(3) 781 #define M33_ITM_DEVTYPE_MAJOR_LSB _u(0) 782 #define M33_ITM_DEVTYPE_MAJOR_ACCESS "RO" 783 // ============================================================================= 784 // Register : M33_ITM_PIDR4 785 // Description : Provides CoreSight discovery information for the ITM 786 #define M33_ITM_PIDR4_OFFSET _u(0x00000fd0) 787 #define M33_ITM_PIDR4_BITS _u(0x000000ff) 788 #define M33_ITM_PIDR4_RESET _u(0x00000004) 789 // ----------------------------------------------------------------------------- 790 // Field : M33_ITM_PIDR4_SIZE 791 // Description : See CoreSight Architecture Specification 792 #define M33_ITM_PIDR4_SIZE_RESET _u(0x0) 793 #define M33_ITM_PIDR4_SIZE_BITS _u(0x000000f0) 794 #define M33_ITM_PIDR4_SIZE_MSB _u(7) 795 #define M33_ITM_PIDR4_SIZE_LSB _u(4) 796 #define M33_ITM_PIDR4_SIZE_ACCESS "RO" 797 // ----------------------------------------------------------------------------- 798 // Field : M33_ITM_PIDR4_DES_2 799 // Description : See CoreSight Architecture Specification 800 #define M33_ITM_PIDR4_DES_2_RESET _u(0x4) 801 #define M33_ITM_PIDR4_DES_2_BITS _u(0x0000000f) 802 #define M33_ITM_PIDR4_DES_2_MSB _u(3) 803 #define M33_ITM_PIDR4_DES_2_LSB _u(0) 804 #define M33_ITM_PIDR4_DES_2_ACCESS "RO" 805 // ============================================================================= 806 // Register : M33_ITM_PIDR5 807 // Description : Provides CoreSight discovery information for the ITM 808 #define M33_ITM_PIDR5_OFFSET _u(0x00000fd4) 809 #define M33_ITM_PIDR5_BITS _u(0x00000000) 810 #define M33_ITM_PIDR5_RESET _u(0x00000000) 811 #define M33_ITM_PIDR5_MSB _u(31) 812 #define M33_ITM_PIDR5_LSB _u(0) 813 #define M33_ITM_PIDR5_ACCESS "RW" 814 // ============================================================================= 815 // Register : M33_ITM_PIDR6 816 // Description : Provides CoreSight discovery information for the ITM 817 #define M33_ITM_PIDR6_OFFSET _u(0x00000fd8) 818 #define M33_ITM_PIDR6_BITS _u(0x00000000) 819 #define M33_ITM_PIDR6_RESET _u(0x00000000) 820 #define M33_ITM_PIDR6_MSB _u(31) 821 #define M33_ITM_PIDR6_LSB _u(0) 822 #define M33_ITM_PIDR6_ACCESS "RW" 823 // ============================================================================= 824 // Register : M33_ITM_PIDR7 825 // Description : Provides CoreSight discovery information for the ITM 826 #define M33_ITM_PIDR7_OFFSET _u(0x00000fdc) 827 #define M33_ITM_PIDR7_BITS _u(0x00000000) 828 #define M33_ITM_PIDR7_RESET _u(0x00000000) 829 #define M33_ITM_PIDR7_MSB _u(31) 830 #define M33_ITM_PIDR7_LSB _u(0) 831 #define M33_ITM_PIDR7_ACCESS "RW" 832 // ============================================================================= 833 // Register : M33_ITM_PIDR0 834 // Description : Provides CoreSight discovery information for the ITM 835 #define M33_ITM_PIDR0_OFFSET _u(0x00000fe0) 836 #define M33_ITM_PIDR0_BITS _u(0x000000ff) 837 #define M33_ITM_PIDR0_RESET _u(0x00000021) 838 // ----------------------------------------------------------------------------- 839 // Field : M33_ITM_PIDR0_PART_0 840 // Description : See CoreSight Architecture Specification 841 #define M33_ITM_PIDR0_PART_0_RESET _u(0x21) 842 #define M33_ITM_PIDR0_PART_0_BITS _u(0x000000ff) 843 #define M33_ITM_PIDR0_PART_0_MSB _u(7) 844 #define M33_ITM_PIDR0_PART_0_LSB _u(0) 845 #define M33_ITM_PIDR0_PART_0_ACCESS "RO" 846 // ============================================================================= 847 // Register : M33_ITM_PIDR1 848 // Description : Provides CoreSight discovery information for the ITM 849 #define M33_ITM_PIDR1_OFFSET _u(0x00000fe4) 850 #define M33_ITM_PIDR1_BITS _u(0x000000ff) 851 #define M33_ITM_PIDR1_RESET _u(0x000000bd) 852 // ----------------------------------------------------------------------------- 853 // Field : M33_ITM_PIDR1_DES_0 854 // Description : See CoreSight Architecture Specification 855 #define M33_ITM_PIDR1_DES_0_RESET _u(0xb) 856 #define M33_ITM_PIDR1_DES_0_BITS _u(0x000000f0) 857 #define M33_ITM_PIDR1_DES_0_MSB _u(7) 858 #define M33_ITM_PIDR1_DES_0_LSB _u(4) 859 #define M33_ITM_PIDR1_DES_0_ACCESS "RO" 860 // ----------------------------------------------------------------------------- 861 // Field : M33_ITM_PIDR1_PART_1 862 // Description : See CoreSight Architecture Specification 863 #define M33_ITM_PIDR1_PART_1_RESET _u(0xd) 864 #define M33_ITM_PIDR1_PART_1_BITS _u(0x0000000f) 865 #define M33_ITM_PIDR1_PART_1_MSB _u(3) 866 #define M33_ITM_PIDR1_PART_1_LSB _u(0) 867 #define M33_ITM_PIDR1_PART_1_ACCESS "RO" 868 // ============================================================================= 869 // Register : M33_ITM_PIDR2 870 // Description : Provides CoreSight discovery information for the ITM 871 #define M33_ITM_PIDR2_OFFSET _u(0x00000fe8) 872 #define M33_ITM_PIDR2_BITS _u(0x000000ff) 873 #define M33_ITM_PIDR2_RESET _u(0x0000000b) 874 // ----------------------------------------------------------------------------- 875 // Field : M33_ITM_PIDR2_REVISION 876 // Description : See CoreSight Architecture Specification 877 #define M33_ITM_PIDR2_REVISION_RESET _u(0x0) 878 #define M33_ITM_PIDR2_REVISION_BITS _u(0x000000f0) 879 #define M33_ITM_PIDR2_REVISION_MSB _u(7) 880 #define M33_ITM_PIDR2_REVISION_LSB _u(4) 881 #define M33_ITM_PIDR2_REVISION_ACCESS "RO" 882 // ----------------------------------------------------------------------------- 883 // Field : M33_ITM_PIDR2_JEDEC 884 // Description : See CoreSight Architecture Specification 885 #define M33_ITM_PIDR2_JEDEC_RESET _u(0x1) 886 #define M33_ITM_PIDR2_JEDEC_BITS _u(0x00000008) 887 #define M33_ITM_PIDR2_JEDEC_MSB _u(3) 888 #define M33_ITM_PIDR2_JEDEC_LSB _u(3) 889 #define M33_ITM_PIDR2_JEDEC_ACCESS "RO" 890 // ----------------------------------------------------------------------------- 891 // Field : M33_ITM_PIDR2_DES_1 892 // Description : See CoreSight Architecture Specification 893 #define M33_ITM_PIDR2_DES_1_RESET _u(0x3) 894 #define M33_ITM_PIDR2_DES_1_BITS _u(0x00000007) 895 #define M33_ITM_PIDR2_DES_1_MSB _u(2) 896 #define M33_ITM_PIDR2_DES_1_LSB _u(0) 897 #define M33_ITM_PIDR2_DES_1_ACCESS "RO" 898 // ============================================================================= 899 // Register : M33_ITM_PIDR3 900 // Description : Provides CoreSight discovery information for the ITM 901 #define M33_ITM_PIDR3_OFFSET _u(0x00000fec) 902 #define M33_ITM_PIDR3_BITS _u(0x000000ff) 903 #define M33_ITM_PIDR3_RESET _u(0x00000000) 904 // ----------------------------------------------------------------------------- 905 // Field : M33_ITM_PIDR3_REVAND 906 // Description : See CoreSight Architecture Specification 907 #define M33_ITM_PIDR3_REVAND_RESET _u(0x0) 908 #define M33_ITM_PIDR3_REVAND_BITS _u(0x000000f0) 909 #define M33_ITM_PIDR3_REVAND_MSB _u(7) 910 #define M33_ITM_PIDR3_REVAND_LSB _u(4) 911 #define M33_ITM_PIDR3_REVAND_ACCESS "RO" 912 // ----------------------------------------------------------------------------- 913 // Field : M33_ITM_PIDR3_CMOD 914 // Description : See CoreSight Architecture Specification 915 #define M33_ITM_PIDR3_CMOD_RESET _u(0x0) 916 #define M33_ITM_PIDR3_CMOD_BITS _u(0x0000000f) 917 #define M33_ITM_PIDR3_CMOD_MSB _u(3) 918 #define M33_ITM_PIDR3_CMOD_LSB _u(0) 919 #define M33_ITM_PIDR3_CMOD_ACCESS "RO" 920 // ============================================================================= 921 // Register : M33_ITM_CIDR0 922 // Description : Provides CoreSight discovery information for the ITM 923 #define M33_ITM_CIDR0_OFFSET _u(0x00000ff0) 924 #define M33_ITM_CIDR0_BITS _u(0x000000ff) 925 #define M33_ITM_CIDR0_RESET _u(0x0000000d) 926 // ----------------------------------------------------------------------------- 927 // Field : M33_ITM_CIDR0_PRMBL_0 928 // Description : See CoreSight Architecture Specification 929 #define M33_ITM_CIDR0_PRMBL_0_RESET _u(0x0d) 930 #define M33_ITM_CIDR0_PRMBL_0_BITS _u(0x000000ff) 931 #define M33_ITM_CIDR0_PRMBL_0_MSB _u(7) 932 #define M33_ITM_CIDR0_PRMBL_0_LSB _u(0) 933 #define M33_ITM_CIDR0_PRMBL_0_ACCESS "RO" 934 // ============================================================================= 935 // Register : M33_ITM_CIDR1 936 // Description : Provides CoreSight discovery information for the ITM 937 #define M33_ITM_CIDR1_OFFSET _u(0x00000ff4) 938 #define M33_ITM_CIDR1_BITS _u(0x000000ff) 939 #define M33_ITM_CIDR1_RESET _u(0x00000090) 940 // ----------------------------------------------------------------------------- 941 // Field : M33_ITM_CIDR1_CLASS 942 // Description : See CoreSight Architecture Specification 943 #define M33_ITM_CIDR1_CLASS_RESET _u(0x9) 944 #define M33_ITM_CIDR1_CLASS_BITS _u(0x000000f0) 945 #define M33_ITM_CIDR1_CLASS_MSB _u(7) 946 #define M33_ITM_CIDR1_CLASS_LSB _u(4) 947 #define M33_ITM_CIDR1_CLASS_ACCESS "RO" 948 // ----------------------------------------------------------------------------- 949 // Field : M33_ITM_CIDR1_PRMBL_1 950 // Description : See CoreSight Architecture Specification 951 #define M33_ITM_CIDR1_PRMBL_1_RESET _u(0x0) 952 #define M33_ITM_CIDR1_PRMBL_1_BITS _u(0x0000000f) 953 #define M33_ITM_CIDR1_PRMBL_1_MSB _u(3) 954 #define M33_ITM_CIDR1_PRMBL_1_LSB _u(0) 955 #define M33_ITM_CIDR1_PRMBL_1_ACCESS "RO" 956 // ============================================================================= 957 // Register : M33_ITM_CIDR2 958 // Description : Provides CoreSight discovery information for the ITM 959 #define M33_ITM_CIDR2_OFFSET _u(0x00000ff8) 960 #define M33_ITM_CIDR2_BITS _u(0x000000ff) 961 #define M33_ITM_CIDR2_RESET _u(0x00000005) 962 // ----------------------------------------------------------------------------- 963 // Field : M33_ITM_CIDR2_PRMBL_2 964 // Description : See CoreSight Architecture Specification 965 #define M33_ITM_CIDR2_PRMBL_2_RESET _u(0x05) 966 #define M33_ITM_CIDR2_PRMBL_2_BITS _u(0x000000ff) 967 #define M33_ITM_CIDR2_PRMBL_2_MSB _u(7) 968 #define M33_ITM_CIDR2_PRMBL_2_LSB _u(0) 969 #define M33_ITM_CIDR2_PRMBL_2_ACCESS "RO" 970 // ============================================================================= 971 // Register : M33_ITM_CIDR3 972 // Description : Provides CoreSight discovery information for the ITM 973 #define M33_ITM_CIDR3_OFFSET _u(0x00000ffc) 974 #define M33_ITM_CIDR3_BITS _u(0x000000ff) 975 #define M33_ITM_CIDR3_RESET _u(0x000000b1) 976 // ----------------------------------------------------------------------------- 977 // Field : M33_ITM_CIDR3_PRMBL_3 978 // Description : See CoreSight Architecture Specification 979 #define M33_ITM_CIDR3_PRMBL_3_RESET _u(0xb1) 980 #define M33_ITM_CIDR3_PRMBL_3_BITS _u(0x000000ff) 981 #define M33_ITM_CIDR3_PRMBL_3_MSB _u(7) 982 #define M33_ITM_CIDR3_PRMBL_3_LSB _u(0) 983 #define M33_ITM_CIDR3_PRMBL_3_ACCESS "RO" 984 // ============================================================================= 985 // Register : M33_DWT_CTRL 986 // Description : Provides configuration and status information for the DWT unit, 987 // and used to control features of the unit 988 #define M33_DWT_CTRL_OFFSET _u(0x00001000) 989 #define M33_DWT_CTRL_BITS _u(0xffff1fff) 990 #define M33_DWT_CTRL_RESET _u(0x73741824) 991 // ----------------------------------------------------------------------------- 992 // Field : M33_DWT_CTRL_NUMCOMP 993 // Description : Number of DWT comparators implemented 994 #define M33_DWT_CTRL_NUMCOMP_RESET _u(0x7) 995 #define M33_DWT_CTRL_NUMCOMP_BITS _u(0xf0000000) 996 #define M33_DWT_CTRL_NUMCOMP_MSB _u(31) 997 #define M33_DWT_CTRL_NUMCOMP_LSB _u(28) 998 #define M33_DWT_CTRL_NUMCOMP_ACCESS "RO" 999 // ----------------------------------------------------------------------------- 1000 // Field : M33_DWT_CTRL_NOTRCPKT 1001 // Description : Indicates whether the implementation does not support trace 1002 #define M33_DWT_CTRL_NOTRCPKT_RESET _u(0x0) 1003 #define M33_DWT_CTRL_NOTRCPKT_BITS _u(0x08000000) 1004 #define M33_DWT_CTRL_NOTRCPKT_MSB _u(27) 1005 #define M33_DWT_CTRL_NOTRCPKT_LSB _u(27) 1006 #define M33_DWT_CTRL_NOTRCPKT_ACCESS "RO" 1007 // ----------------------------------------------------------------------------- 1008 // Field : M33_DWT_CTRL_NOEXTTRIG 1009 // Description : Reserved, RAZ 1010 #define M33_DWT_CTRL_NOEXTTRIG_RESET _u(0x0) 1011 #define M33_DWT_CTRL_NOEXTTRIG_BITS _u(0x04000000) 1012 #define M33_DWT_CTRL_NOEXTTRIG_MSB _u(26) 1013 #define M33_DWT_CTRL_NOEXTTRIG_LSB _u(26) 1014 #define M33_DWT_CTRL_NOEXTTRIG_ACCESS "RO" 1015 // ----------------------------------------------------------------------------- 1016 // Field : M33_DWT_CTRL_NOCYCCNT 1017 // Description : Indicates whether the implementation does not include a cycle 1018 // counter 1019 #define M33_DWT_CTRL_NOCYCCNT_RESET _u(0x1) 1020 #define M33_DWT_CTRL_NOCYCCNT_BITS _u(0x02000000) 1021 #define M33_DWT_CTRL_NOCYCCNT_MSB _u(25) 1022 #define M33_DWT_CTRL_NOCYCCNT_LSB _u(25) 1023 #define M33_DWT_CTRL_NOCYCCNT_ACCESS "RO" 1024 // ----------------------------------------------------------------------------- 1025 // Field : M33_DWT_CTRL_NOPRFCNT 1026 // Description : Indicates whether the implementation does not include the 1027 // profiling counters 1028 #define M33_DWT_CTRL_NOPRFCNT_RESET _u(0x1) 1029 #define M33_DWT_CTRL_NOPRFCNT_BITS _u(0x01000000) 1030 #define M33_DWT_CTRL_NOPRFCNT_MSB _u(24) 1031 #define M33_DWT_CTRL_NOPRFCNT_LSB _u(24) 1032 #define M33_DWT_CTRL_NOPRFCNT_ACCESS "RO" 1033 // ----------------------------------------------------------------------------- 1034 // Field : M33_DWT_CTRL_CYCDISS 1035 // Description : Controls whether the cycle counter is disabled in Secure state 1036 #define M33_DWT_CTRL_CYCDISS_RESET _u(0x0) 1037 #define M33_DWT_CTRL_CYCDISS_BITS _u(0x00800000) 1038 #define M33_DWT_CTRL_CYCDISS_MSB _u(23) 1039 #define M33_DWT_CTRL_CYCDISS_LSB _u(23) 1040 #define M33_DWT_CTRL_CYCDISS_ACCESS "RW" 1041 // ----------------------------------------------------------------------------- 1042 // Field : M33_DWT_CTRL_CYCEVTENA 1043 // Description : Enables Event Counter packet generation on POSTCNT underflow 1044 #define M33_DWT_CTRL_CYCEVTENA_RESET _u(0x1) 1045 #define M33_DWT_CTRL_CYCEVTENA_BITS _u(0x00400000) 1046 #define M33_DWT_CTRL_CYCEVTENA_MSB _u(22) 1047 #define M33_DWT_CTRL_CYCEVTENA_LSB _u(22) 1048 #define M33_DWT_CTRL_CYCEVTENA_ACCESS "RW" 1049 // ----------------------------------------------------------------------------- 1050 // Field : M33_DWT_CTRL_FOLDEVTENA 1051 // Description : Enables DWT_FOLDCNT counter 1052 #define M33_DWT_CTRL_FOLDEVTENA_RESET _u(0x1) 1053 #define M33_DWT_CTRL_FOLDEVTENA_BITS _u(0x00200000) 1054 #define M33_DWT_CTRL_FOLDEVTENA_MSB _u(21) 1055 #define M33_DWT_CTRL_FOLDEVTENA_LSB _u(21) 1056 #define M33_DWT_CTRL_FOLDEVTENA_ACCESS "RW" 1057 // ----------------------------------------------------------------------------- 1058 // Field : M33_DWT_CTRL_LSUEVTENA 1059 // Description : Enables DWT_LSUCNT counter 1060 #define M33_DWT_CTRL_LSUEVTENA_RESET _u(0x1) 1061 #define M33_DWT_CTRL_LSUEVTENA_BITS _u(0x00100000) 1062 #define M33_DWT_CTRL_LSUEVTENA_MSB _u(20) 1063 #define M33_DWT_CTRL_LSUEVTENA_LSB _u(20) 1064 #define M33_DWT_CTRL_LSUEVTENA_ACCESS "RW" 1065 // ----------------------------------------------------------------------------- 1066 // Field : M33_DWT_CTRL_SLEEPEVTENA 1067 // Description : Enable DWT_SLEEPCNT counter 1068 #define M33_DWT_CTRL_SLEEPEVTENA_RESET _u(0x0) 1069 #define M33_DWT_CTRL_SLEEPEVTENA_BITS _u(0x00080000) 1070 #define M33_DWT_CTRL_SLEEPEVTENA_MSB _u(19) 1071 #define M33_DWT_CTRL_SLEEPEVTENA_LSB _u(19) 1072 #define M33_DWT_CTRL_SLEEPEVTENA_ACCESS "RW" 1073 // ----------------------------------------------------------------------------- 1074 // Field : M33_DWT_CTRL_EXCEVTENA 1075 // Description : Enables DWT_EXCCNT counter 1076 #define M33_DWT_CTRL_EXCEVTENA_RESET _u(0x1) 1077 #define M33_DWT_CTRL_EXCEVTENA_BITS _u(0x00040000) 1078 #define M33_DWT_CTRL_EXCEVTENA_MSB _u(18) 1079 #define M33_DWT_CTRL_EXCEVTENA_LSB _u(18) 1080 #define M33_DWT_CTRL_EXCEVTENA_ACCESS "RW" 1081 // ----------------------------------------------------------------------------- 1082 // Field : M33_DWT_CTRL_CPIEVTENA 1083 // Description : Enables DWT_CPICNT counter 1084 #define M33_DWT_CTRL_CPIEVTENA_RESET _u(0x0) 1085 #define M33_DWT_CTRL_CPIEVTENA_BITS _u(0x00020000) 1086 #define M33_DWT_CTRL_CPIEVTENA_MSB _u(17) 1087 #define M33_DWT_CTRL_CPIEVTENA_LSB _u(17) 1088 #define M33_DWT_CTRL_CPIEVTENA_ACCESS "RW" 1089 // ----------------------------------------------------------------------------- 1090 // Field : M33_DWT_CTRL_EXTTRCENA 1091 // Description : Enables generation of Exception Trace packets 1092 #define M33_DWT_CTRL_EXTTRCENA_RESET _u(0x0) 1093 #define M33_DWT_CTRL_EXTTRCENA_BITS _u(0x00010000) 1094 #define M33_DWT_CTRL_EXTTRCENA_MSB _u(16) 1095 #define M33_DWT_CTRL_EXTTRCENA_LSB _u(16) 1096 #define M33_DWT_CTRL_EXTTRCENA_ACCESS "RW" 1097 // ----------------------------------------------------------------------------- 1098 // Field : M33_DWT_CTRL_PCSAMPLENA 1099 // Description : Enables use of POSTCNT counter as a timer for Periodic PC 1100 // Sample packet generation 1101 #define M33_DWT_CTRL_PCSAMPLENA_RESET _u(0x1) 1102 #define M33_DWT_CTRL_PCSAMPLENA_BITS _u(0x00001000) 1103 #define M33_DWT_CTRL_PCSAMPLENA_MSB _u(12) 1104 #define M33_DWT_CTRL_PCSAMPLENA_LSB _u(12) 1105 #define M33_DWT_CTRL_PCSAMPLENA_ACCESS "RW" 1106 // ----------------------------------------------------------------------------- 1107 // Field : M33_DWT_CTRL_SYNCTAP 1108 // Description : Selects the position of the synchronization packet counter tap 1109 // on the CYCCNT counter. This determines the Synchronization 1110 // packet rate 1111 #define M33_DWT_CTRL_SYNCTAP_RESET _u(0x2) 1112 #define M33_DWT_CTRL_SYNCTAP_BITS _u(0x00000c00) 1113 #define M33_DWT_CTRL_SYNCTAP_MSB _u(11) 1114 #define M33_DWT_CTRL_SYNCTAP_LSB _u(10) 1115 #define M33_DWT_CTRL_SYNCTAP_ACCESS "RW" 1116 // ----------------------------------------------------------------------------- 1117 // Field : M33_DWT_CTRL_CYCTAP 1118 // Description : Selects the position of the POSTCNT tap on the CYCCNT counter 1119 #define M33_DWT_CTRL_CYCTAP_RESET _u(0x0) 1120 #define M33_DWT_CTRL_CYCTAP_BITS _u(0x00000200) 1121 #define M33_DWT_CTRL_CYCTAP_MSB _u(9) 1122 #define M33_DWT_CTRL_CYCTAP_LSB _u(9) 1123 #define M33_DWT_CTRL_CYCTAP_ACCESS "RW" 1124 // ----------------------------------------------------------------------------- 1125 // Field : M33_DWT_CTRL_POSTINIT 1126 // Description : Initial value for the POSTCNT counter 1127 #define M33_DWT_CTRL_POSTINIT_RESET _u(0x1) 1128 #define M33_DWT_CTRL_POSTINIT_BITS _u(0x000001e0) 1129 #define M33_DWT_CTRL_POSTINIT_MSB _u(8) 1130 #define M33_DWT_CTRL_POSTINIT_LSB _u(5) 1131 #define M33_DWT_CTRL_POSTINIT_ACCESS "RW" 1132 // ----------------------------------------------------------------------------- 1133 // Field : M33_DWT_CTRL_POSTPRESET 1134 // Description : Reload value for the POSTCNT counter 1135 #define M33_DWT_CTRL_POSTPRESET_RESET _u(0x2) 1136 #define M33_DWT_CTRL_POSTPRESET_BITS _u(0x0000001e) 1137 #define M33_DWT_CTRL_POSTPRESET_MSB _u(4) 1138 #define M33_DWT_CTRL_POSTPRESET_LSB _u(1) 1139 #define M33_DWT_CTRL_POSTPRESET_ACCESS "RW" 1140 // ----------------------------------------------------------------------------- 1141 // Field : M33_DWT_CTRL_CYCCNTENA 1142 // Description : Enables CYCCNT 1143 #define M33_DWT_CTRL_CYCCNTENA_RESET _u(0x0) 1144 #define M33_DWT_CTRL_CYCCNTENA_BITS _u(0x00000001) 1145 #define M33_DWT_CTRL_CYCCNTENA_MSB _u(0) 1146 #define M33_DWT_CTRL_CYCCNTENA_LSB _u(0) 1147 #define M33_DWT_CTRL_CYCCNTENA_ACCESS "RW" 1148 // ============================================================================= 1149 // Register : M33_DWT_CYCCNT 1150 // Description : Shows or sets the value of the processor cycle counter, CYCCNT 1151 #define M33_DWT_CYCCNT_OFFSET _u(0x00001004) 1152 #define M33_DWT_CYCCNT_BITS _u(0xffffffff) 1153 #define M33_DWT_CYCCNT_RESET _u(0x00000000) 1154 // ----------------------------------------------------------------------------- 1155 // Field : M33_DWT_CYCCNT_CYCCNT 1156 // Description : Increments one on each processor clock cycle when 1157 // DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, 1158 // CYCCNT wraps to zero 1159 #define M33_DWT_CYCCNT_CYCCNT_RESET _u(0x00000000) 1160 #define M33_DWT_CYCCNT_CYCCNT_BITS _u(0xffffffff) 1161 #define M33_DWT_CYCCNT_CYCCNT_MSB _u(31) 1162 #define M33_DWT_CYCCNT_CYCCNT_LSB _u(0) 1163 #define M33_DWT_CYCCNT_CYCCNT_ACCESS "RW" 1164 // ============================================================================= 1165 // Register : M33_DWT_EXCCNT 1166 // Description : Counts the total cycles spent in exception processing 1167 #define M33_DWT_EXCCNT_OFFSET _u(0x0000100c) 1168 #define M33_DWT_EXCCNT_BITS _u(0x000000ff) 1169 #define M33_DWT_EXCCNT_RESET _u(0x00000000) 1170 // ----------------------------------------------------------------------------- 1171 // Field : M33_DWT_EXCCNT_EXCCNT 1172 // Description : Counts one on each cycle when all of the following are true: - 1173 // DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction 1174 // is executed, see DWT_CPICNT. - An exception-entry or exception- 1175 // exit related operation is in progress. - Either 1176 // SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the 1177 // operation is set to Non-secure and NoninvasiveDebugAllowed() == 1178 // TRUE. 1179 #define M33_DWT_EXCCNT_EXCCNT_RESET _u(0x00) 1180 #define M33_DWT_EXCCNT_EXCCNT_BITS _u(0x000000ff) 1181 #define M33_DWT_EXCCNT_EXCCNT_MSB _u(7) 1182 #define M33_DWT_EXCCNT_EXCCNT_LSB _u(0) 1183 #define M33_DWT_EXCCNT_EXCCNT_ACCESS "RW" 1184 // ============================================================================= 1185 // Register : M33_DWT_LSUCNT 1186 // Description : Increments on the additional cycles required to execute all 1187 // load or store instructions 1188 #define M33_DWT_LSUCNT_OFFSET _u(0x00001014) 1189 #define M33_DWT_LSUCNT_BITS _u(0x000000ff) 1190 #define M33_DWT_LSUCNT_RESET _u(0x00000000) 1191 // ----------------------------------------------------------------------------- 1192 // Field : M33_DWT_LSUCNT_LSUCNT 1193 // Description : Counts one on each cycle when all of the following are true: - 1194 // DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction 1195 // is executed, see DWT_CPICNT. - No exception-entry or exception- 1196 // exit operation is in progress, see DWT_EXCCNT. - A load-store 1197 // operation is in progress. - Either 1198 // SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the 1199 // operation is set to Non-secure and NoninvasiveDebugAllowed() == 1200 // TRUE. 1201 #define M33_DWT_LSUCNT_LSUCNT_RESET _u(0x00) 1202 #define M33_DWT_LSUCNT_LSUCNT_BITS _u(0x000000ff) 1203 #define M33_DWT_LSUCNT_LSUCNT_MSB _u(7) 1204 #define M33_DWT_LSUCNT_LSUCNT_LSB _u(0) 1205 #define M33_DWT_LSUCNT_LSUCNT_ACCESS "RW" 1206 // ============================================================================= 1207 // Register : M33_DWT_FOLDCNT 1208 // Description : Increments on the additional cycles required to execute all 1209 // load or store instructions 1210 #define M33_DWT_FOLDCNT_OFFSET _u(0x00001018) 1211 #define M33_DWT_FOLDCNT_BITS _u(0x000000ff) 1212 #define M33_DWT_FOLDCNT_RESET _u(0x00000000) 1213 // ----------------------------------------------------------------------------- 1214 // Field : M33_DWT_FOLDCNT_FOLDCNT 1215 // Description : Counts on each cycle when all of the following are true: - 1216 // DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two 1217 // instructions are executed, see DWT_CPICNT. - Either 1218 // SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non- 1219 // secure state and NoninvasiveDebugAllowed() == TRUE. The counter 1220 // is incremented by the number of instructions executed, minus 1221 // one 1222 #define M33_DWT_FOLDCNT_FOLDCNT_RESET _u(0x00) 1223 #define M33_DWT_FOLDCNT_FOLDCNT_BITS _u(0x000000ff) 1224 #define M33_DWT_FOLDCNT_FOLDCNT_MSB _u(7) 1225 #define M33_DWT_FOLDCNT_FOLDCNT_LSB _u(0) 1226 #define M33_DWT_FOLDCNT_FOLDCNT_ACCESS "RW" 1227 // ============================================================================= 1228 // Register : M33_DWT_COMP0 1229 // Description : Provides a reference value for use by watchpoint comparator 0 1230 #define M33_DWT_COMP0_OFFSET _u(0x00001020) 1231 #define M33_DWT_COMP0_BITS _u(0xffffffff) 1232 #define M33_DWT_COMP0_RESET _u(0x00000000) 1233 #define M33_DWT_COMP0_MSB _u(31) 1234 #define M33_DWT_COMP0_LSB _u(0) 1235 #define M33_DWT_COMP0_ACCESS "RW" 1236 // ============================================================================= 1237 // Register : M33_DWT_FUNCTION0 1238 // Description : Controls the operation of watchpoint comparator 0 1239 #define M33_DWT_FUNCTION0_OFFSET _u(0x00001028) 1240 #define M33_DWT_FUNCTION0_BITS _u(0xf9000c3f) 1241 #define M33_DWT_FUNCTION0_RESET _u(0x58000000) 1242 // ----------------------------------------------------------------------------- 1243 // Field : M33_DWT_FUNCTION0_ID 1244 // Description : Identifies the capabilities for MATCH for comparator *n 1245 #define M33_DWT_FUNCTION0_ID_RESET _u(0x0b) 1246 #define M33_DWT_FUNCTION0_ID_BITS _u(0xf8000000) 1247 #define M33_DWT_FUNCTION0_ID_MSB _u(31) 1248 #define M33_DWT_FUNCTION0_ID_LSB _u(27) 1249 #define M33_DWT_FUNCTION0_ID_ACCESS "RO" 1250 // ----------------------------------------------------------------------------- 1251 // Field : M33_DWT_FUNCTION0_MATCHED 1252 // Description : Set to 1 when the comparator matches 1253 #define M33_DWT_FUNCTION0_MATCHED_RESET _u(0x0) 1254 #define M33_DWT_FUNCTION0_MATCHED_BITS _u(0x01000000) 1255 #define M33_DWT_FUNCTION0_MATCHED_MSB _u(24) 1256 #define M33_DWT_FUNCTION0_MATCHED_LSB _u(24) 1257 #define M33_DWT_FUNCTION0_MATCHED_ACCESS "RO" 1258 // ----------------------------------------------------------------------------- 1259 // Field : M33_DWT_FUNCTION0_DATAVSIZE 1260 // Description : Defines the size of the object being watched for by Data Value 1261 // and Data Address comparators 1262 #define M33_DWT_FUNCTION0_DATAVSIZE_RESET _u(0x0) 1263 #define M33_DWT_FUNCTION0_DATAVSIZE_BITS _u(0x00000c00) 1264 #define M33_DWT_FUNCTION0_DATAVSIZE_MSB _u(11) 1265 #define M33_DWT_FUNCTION0_DATAVSIZE_LSB _u(10) 1266 #define M33_DWT_FUNCTION0_DATAVSIZE_ACCESS "RW" 1267 // ----------------------------------------------------------------------------- 1268 // Field : M33_DWT_FUNCTION0_ACTION 1269 // Description : Defines the action on a match. This field is ignored and the 1270 // comparator generates no actions if it is disabled by MATCH 1271 #define M33_DWT_FUNCTION0_ACTION_RESET _u(0x0) 1272 #define M33_DWT_FUNCTION0_ACTION_BITS _u(0x00000030) 1273 #define M33_DWT_FUNCTION0_ACTION_MSB _u(5) 1274 #define M33_DWT_FUNCTION0_ACTION_LSB _u(4) 1275 #define M33_DWT_FUNCTION0_ACTION_ACCESS "RW" 1276 // ----------------------------------------------------------------------------- 1277 // Field : M33_DWT_FUNCTION0_MATCH 1278 // Description : Controls the type of match generated by this comparator 1279 #define M33_DWT_FUNCTION0_MATCH_RESET _u(0x0) 1280 #define M33_DWT_FUNCTION0_MATCH_BITS _u(0x0000000f) 1281 #define M33_DWT_FUNCTION0_MATCH_MSB _u(3) 1282 #define M33_DWT_FUNCTION0_MATCH_LSB _u(0) 1283 #define M33_DWT_FUNCTION0_MATCH_ACCESS "RW" 1284 // ============================================================================= 1285 // Register : M33_DWT_COMP1 1286 // Description : Provides a reference value for use by watchpoint comparator 1 1287 #define M33_DWT_COMP1_OFFSET _u(0x00001030) 1288 #define M33_DWT_COMP1_BITS _u(0xffffffff) 1289 #define M33_DWT_COMP1_RESET _u(0x00000000) 1290 #define M33_DWT_COMP1_MSB _u(31) 1291 #define M33_DWT_COMP1_LSB _u(0) 1292 #define M33_DWT_COMP1_ACCESS "RW" 1293 // ============================================================================= 1294 // Register : M33_DWT_FUNCTION1 1295 // Description : Controls the operation of watchpoint comparator 1 1296 #define M33_DWT_FUNCTION1_OFFSET _u(0x00001038) 1297 #define M33_DWT_FUNCTION1_BITS _u(0xf9000c3f) 1298 #define M33_DWT_FUNCTION1_RESET _u(0x89000828) 1299 // ----------------------------------------------------------------------------- 1300 // Field : M33_DWT_FUNCTION1_ID 1301 // Description : Identifies the capabilities for MATCH for comparator *n 1302 #define M33_DWT_FUNCTION1_ID_RESET _u(0x11) 1303 #define M33_DWT_FUNCTION1_ID_BITS _u(0xf8000000) 1304 #define M33_DWT_FUNCTION1_ID_MSB _u(31) 1305 #define M33_DWT_FUNCTION1_ID_LSB _u(27) 1306 #define M33_DWT_FUNCTION1_ID_ACCESS "RO" 1307 // ----------------------------------------------------------------------------- 1308 // Field : M33_DWT_FUNCTION1_MATCHED 1309 // Description : Set to 1 when the comparator matches 1310 #define M33_DWT_FUNCTION1_MATCHED_RESET _u(0x1) 1311 #define M33_DWT_FUNCTION1_MATCHED_BITS _u(0x01000000) 1312 #define M33_DWT_FUNCTION1_MATCHED_MSB _u(24) 1313 #define M33_DWT_FUNCTION1_MATCHED_LSB _u(24) 1314 #define M33_DWT_FUNCTION1_MATCHED_ACCESS "RO" 1315 // ----------------------------------------------------------------------------- 1316 // Field : M33_DWT_FUNCTION1_DATAVSIZE 1317 // Description : Defines the size of the object being watched for by Data Value 1318 // and Data Address comparators 1319 #define M33_DWT_FUNCTION1_DATAVSIZE_RESET _u(0x2) 1320 #define M33_DWT_FUNCTION1_DATAVSIZE_BITS _u(0x00000c00) 1321 #define M33_DWT_FUNCTION1_DATAVSIZE_MSB _u(11) 1322 #define M33_DWT_FUNCTION1_DATAVSIZE_LSB _u(10) 1323 #define M33_DWT_FUNCTION1_DATAVSIZE_ACCESS "RW" 1324 // ----------------------------------------------------------------------------- 1325 // Field : M33_DWT_FUNCTION1_ACTION 1326 // Description : Defines the action on a match. This field is ignored and the 1327 // comparator generates no actions if it is disabled by MATCH 1328 #define M33_DWT_FUNCTION1_ACTION_RESET _u(0x2) 1329 #define M33_DWT_FUNCTION1_ACTION_BITS _u(0x00000030) 1330 #define M33_DWT_FUNCTION1_ACTION_MSB _u(5) 1331 #define M33_DWT_FUNCTION1_ACTION_LSB _u(4) 1332 #define M33_DWT_FUNCTION1_ACTION_ACCESS "RW" 1333 // ----------------------------------------------------------------------------- 1334 // Field : M33_DWT_FUNCTION1_MATCH 1335 // Description : Controls the type of match generated by this comparator 1336 #define M33_DWT_FUNCTION1_MATCH_RESET _u(0x8) 1337 #define M33_DWT_FUNCTION1_MATCH_BITS _u(0x0000000f) 1338 #define M33_DWT_FUNCTION1_MATCH_MSB _u(3) 1339 #define M33_DWT_FUNCTION1_MATCH_LSB _u(0) 1340 #define M33_DWT_FUNCTION1_MATCH_ACCESS "RW" 1341 // ============================================================================= 1342 // Register : M33_DWT_COMP2 1343 // Description : Provides a reference value for use by watchpoint comparator 2 1344 #define M33_DWT_COMP2_OFFSET _u(0x00001040) 1345 #define M33_DWT_COMP2_BITS _u(0xffffffff) 1346 #define M33_DWT_COMP2_RESET _u(0x00000000) 1347 #define M33_DWT_COMP2_MSB _u(31) 1348 #define M33_DWT_COMP2_LSB _u(0) 1349 #define M33_DWT_COMP2_ACCESS "RW" 1350 // ============================================================================= 1351 // Register : M33_DWT_FUNCTION2 1352 // Description : Controls the operation of watchpoint comparator 2 1353 #define M33_DWT_FUNCTION2_OFFSET _u(0x00001048) 1354 #define M33_DWT_FUNCTION2_BITS _u(0xf9000c3f) 1355 #define M33_DWT_FUNCTION2_RESET _u(0x50000000) 1356 // ----------------------------------------------------------------------------- 1357 // Field : M33_DWT_FUNCTION2_ID 1358 // Description : Identifies the capabilities for MATCH for comparator *n 1359 #define M33_DWT_FUNCTION2_ID_RESET _u(0x0a) 1360 #define M33_DWT_FUNCTION2_ID_BITS _u(0xf8000000) 1361 #define M33_DWT_FUNCTION2_ID_MSB _u(31) 1362 #define M33_DWT_FUNCTION2_ID_LSB _u(27) 1363 #define M33_DWT_FUNCTION2_ID_ACCESS "RO" 1364 // ----------------------------------------------------------------------------- 1365 // Field : M33_DWT_FUNCTION2_MATCHED 1366 // Description : Set to 1 when the comparator matches 1367 #define M33_DWT_FUNCTION2_MATCHED_RESET _u(0x0) 1368 #define M33_DWT_FUNCTION2_MATCHED_BITS _u(0x01000000) 1369 #define M33_DWT_FUNCTION2_MATCHED_MSB _u(24) 1370 #define M33_DWT_FUNCTION2_MATCHED_LSB _u(24) 1371 #define M33_DWT_FUNCTION2_MATCHED_ACCESS "RO" 1372 // ----------------------------------------------------------------------------- 1373 // Field : M33_DWT_FUNCTION2_DATAVSIZE 1374 // Description : Defines the size of the object being watched for by Data Value 1375 // and Data Address comparators 1376 #define M33_DWT_FUNCTION2_DATAVSIZE_RESET _u(0x0) 1377 #define M33_DWT_FUNCTION2_DATAVSIZE_BITS _u(0x00000c00) 1378 #define M33_DWT_FUNCTION2_DATAVSIZE_MSB _u(11) 1379 #define M33_DWT_FUNCTION2_DATAVSIZE_LSB _u(10) 1380 #define M33_DWT_FUNCTION2_DATAVSIZE_ACCESS "RW" 1381 // ----------------------------------------------------------------------------- 1382 // Field : M33_DWT_FUNCTION2_ACTION 1383 // Description : Defines the action on a match. This field is ignored and the 1384 // comparator generates no actions if it is disabled by MATCH 1385 #define M33_DWT_FUNCTION2_ACTION_RESET _u(0x0) 1386 #define M33_DWT_FUNCTION2_ACTION_BITS _u(0x00000030) 1387 #define M33_DWT_FUNCTION2_ACTION_MSB _u(5) 1388 #define M33_DWT_FUNCTION2_ACTION_LSB _u(4) 1389 #define M33_DWT_FUNCTION2_ACTION_ACCESS "RW" 1390 // ----------------------------------------------------------------------------- 1391 // Field : M33_DWT_FUNCTION2_MATCH 1392 // Description : Controls the type of match generated by this comparator 1393 #define M33_DWT_FUNCTION2_MATCH_RESET _u(0x0) 1394 #define M33_DWT_FUNCTION2_MATCH_BITS _u(0x0000000f) 1395 #define M33_DWT_FUNCTION2_MATCH_MSB _u(3) 1396 #define M33_DWT_FUNCTION2_MATCH_LSB _u(0) 1397 #define M33_DWT_FUNCTION2_MATCH_ACCESS "RW" 1398 // ============================================================================= 1399 // Register : M33_DWT_COMP3 1400 // Description : Provides a reference value for use by watchpoint comparator 3 1401 #define M33_DWT_COMP3_OFFSET _u(0x00001050) 1402 #define M33_DWT_COMP3_BITS _u(0xffffffff) 1403 #define M33_DWT_COMP3_RESET _u(0x00000000) 1404 #define M33_DWT_COMP3_MSB _u(31) 1405 #define M33_DWT_COMP3_LSB _u(0) 1406 #define M33_DWT_COMP3_ACCESS "RW" 1407 // ============================================================================= 1408 // Register : M33_DWT_FUNCTION3 1409 // Description : Controls the operation of watchpoint comparator 3 1410 #define M33_DWT_FUNCTION3_OFFSET _u(0x00001058) 1411 #define M33_DWT_FUNCTION3_BITS _u(0xf9000c3f) 1412 #define M33_DWT_FUNCTION3_RESET _u(0x20000800) 1413 // ----------------------------------------------------------------------------- 1414 // Field : M33_DWT_FUNCTION3_ID 1415 // Description : Identifies the capabilities for MATCH for comparator *n 1416 #define M33_DWT_FUNCTION3_ID_RESET _u(0x04) 1417 #define M33_DWT_FUNCTION3_ID_BITS _u(0xf8000000) 1418 #define M33_DWT_FUNCTION3_ID_MSB _u(31) 1419 #define M33_DWT_FUNCTION3_ID_LSB _u(27) 1420 #define M33_DWT_FUNCTION3_ID_ACCESS "RO" 1421 // ----------------------------------------------------------------------------- 1422 // Field : M33_DWT_FUNCTION3_MATCHED 1423 // Description : Set to 1 when the comparator matches 1424 #define M33_DWT_FUNCTION3_MATCHED_RESET _u(0x0) 1425 #define M33_DWT_FUNCTION3_MATCHED_BITS _u(0x01000000) 1426 #define M33_DWT_FUNCTION3_MATCHED_MSB _u(24) 1427 #define M33_DWT_FUNCTION3_MATCHED_LSB _u(24) 1428 #define M33_DWT_FUNCTION3_MATCHED_ACCESS "RO" 1429 // ----------------------------------------------------------------------------- 1430 // Field : M33_DWT_FUNCTION3_DATAVSIZE 1431 // Description : Defines the size of the object being watched for by Data Value 1432 // and Data Address comparators 1433 #define M33_DWT_FUNCTION3_DATAVSIZE_RESET _u(0x2) 1434 #define M33_DWT_FUNCTION3_DATAVSIZE_BITS _u(0x00000c00) 1435 #define M33_DWT_FUNCTION3_DATAVSIZE_MSB _u(11) 1436 #define M33_DWT_FUNCTION3_DATAVSIZE_LSB _u(10) 1437 #define M33_DWT_FUNCTION3_DATAVSIZE_ACCESS "RW" 1438 // ----------------------------------------------------------------------------- 1439 // Field : M33_DWT_FUNCTION3_ACTION 1440 // Description : Defines the action on a match. This field is ignored and the 1441 // comparator generates no actions if it is disabled by MATCH 1442 #define M33_DWT_FUNCTION3_ACTION_RESET _u(0x0) 1443 #define M33_DWT_FUNCTION3_ACTION_BITS _u(0x00000030) 1444 #define M33_DWT_FUNCTION3_ACTION_MSB _u(5) 1445 #define M33_DWT_FUNCTION3_ACTION_LSB _u(4) 1446 #define M33_DWT_FUNCTION3_ACTION_ACCESS "RW" 1447 // ----------------------------------------------------------------------------- 1448 // Field : M33_DWT_FUNCTION3_MATCH 1449 // Description : Controls the type of match generated by this comparator 1450 #define M33_DWT_FUNCTION3_MATCH_RESET _u(0x0) 1451 #define M33_DWT_FUNCTION3_MATCH_BITS _u(0x0000000f) 1452 #define M33_DWT_FUNCTION3_MATCH_MSB _u(3) 1453 #define M33_DWT_FUNCTION3_MATCH_LSB _u(0) 1454 #define M33_DWT_FUNCTION3_MATCH_ACCESS "RW" 1455 // ============================================================================= 1456 // Register : M33_DWT_DEVARCH 1457 // Description : Provides CoreSight discovery information for the DWT 1458 #define M33_DWT_DEVARCH_OFFSET _u(0x00001fbc) 1459 #define M33_DWT_DEVARCH_BITS _u(0xffffffff) 1460 #define M33_DWT_DEVARCH_RESET _u(0x47701a02) 1461 // ----------------------------------------------------------------------------- 1462 // Field : M33_DWT_DEVARCH_ARCHITECT 1463 // Description : Defines the architect of the component. Bits [31:28] are the 1464 // JEP106 continuation code (JEP106 bank ID, minus 1) and bits 1465 // [27:21] are the JEP106 ID code. 1466 #define M33_DWT_DEVARCH_ARCHITECT_RESET _u(0x23b) 1467 #define M33_DWT_DEVARCH_ARCHITECT_BITS _u(0xffe00000) 1468 #define M33_DWT_DEVARCH_ARCHITECT_MSB _u(31) 1469 #define M33_DWT_DEVARCH_ARCHITECT_LSB _u(21) 1470 #define M33_DWT_DEVARCH_ARCHITECT_ACCESS "RO" 1471 // ----------------------------------------------------------------------------- 1472 // Field : M33_DWT_DEVARCH_PRESENT 1473 // Description : Defines that the DEVARCH register is present 1474 #define M33_DWT_DEVARCH_PRESENT_RESET _u(0x1) 1475 #define M33_DWT_DEVARCH_PRESENT_BITS _u(0x00100000) 1476 #define M33_DWT_DEVARCH_PRESENT_MSB _u(20) 1477 #define M33_DWT_DEVARCH_PRESENT_LSB _u(20) 1478 #define M33_DWT_DEVARCH_PRESENT_ACCESS "RO" 1479 // ----------------------------------------------------------------------------- 1480 // Field : M33_DWT_DEVARCH_REVISION 1481 // Description : Defines the architecture revision of the component 1482 #define M33_DWT_DEVARCH_REVISION_RESET _u(0x0) 1483 #define M33_DWT_DEVARCH_REVISION_BITS _u(0x000f0000) 1484 #define M33_DWT_DEVARCH_REVISION_MSB _u(19) 1485 #define M33_DWT_DEVARCH_REVISION_LSB _u(16) 1486 #define M33_DWT_DEVARCH_REVISION_ACCESS "RO" 1487 // ----------------------------------------------------------------------------- 1488 // Field : M33_DWT_DEVARCH_ARCHVER 1489 // Description : Defines the architecture version of the component 1490 #define M33_DWT_DEVARCH_ARCHVER_RESET _u(0x1) 1491 #define M33_DWT_DEVARCH_ARCHVER_BITS _u(0x0000f000) 1492 #define M33_DWT_DEVARCH_ARCHVER_MSB _u(15) 1493 #define M33_DWT_DEVARCH_ARCHVER_LSB _u(12) 1494 #define M33_DWT_DEVARCH_ARCHVER_ACCESS "RO" 1495 // ----------------------------------------------------------------------------- 1496 // Field : M33_DWT_DEVARCH_ARCHPART 1497 // Description : Defines the architecture of the component 1498 #define M33_DWT_DEVARCH_ARCHPART_RESET _u(0xa02) 1499 #define M33_DWT_DEVARCH_ARCHPART_BITS _u(0x00000fff) 1500 #define M33_DWT_DEVARCH_ARCHPART_MSB _u(11) 1501 #define M33_DWT_DEVARCH_ARCHPART_LSB _u(0) 1502 #define M33_DWT_DEVARCH_ARCHPART_ACCESS "RO" 1503 // ============================================================================= 1504 // Register : M33_DWT_DEVTYPE 1505 // Description : Provides CoreSight discovery information for the DWT 1506 #define M33_DWT_DEVTYPE_OFFSET _u(0x00001fcc) 1507 #define M33_DWT_DEVTYPE_BITS _u(0x000000ff) 1508 #define M33_DWT_DEVTYPE_RESET _u(0x00000000) 1509 // ----------------------------------------------------------------------------- 1510 // Field : M33_DWT_DEVTYPE_SUB 1511 // Description : Component sub-type 1512 #define M33_DWT_DEVTYPE_SUB_RESET _u(0x0) 1513 #define M33_DWT_DEVTYPE_SUB_BITS _u(0x000000f0) 1514 #define M33_DWT_DEVTYPE_SUB_MSB _u(7) 1515 #define M33_DWT_DEVTYPE_SUB_LSB _u(4) 1516 #define M33_DWT_DEVTYPE_SUB_ACCESS "RO" 1517 // ----------------------------------------------------------------------------- 1518 // Field : M33_DWT_DEVTYPE_MAJOR 1519 // Description : Component major type 1520 #define M33_DWT_DEVTYPE_MAJOR_RESET _u(0x0) 1521 #define M33_DWT_DEVTYPE_MAJOR_BITS _u(0x0000000f) 1522 #define M33_DWT_DEVTYPE_MAJOR_MSB _u(3) 1523 #define M33_DWT_DEVTYPE_MAJOR_LSB _u(0) 1524 #define M33_DWT_DEVTYPE_MAJOR_ACCESS "RO" 1525 // ============================================================================= 1526 // Register : M33_DWT_PIDR4 1527 // Description : Provides CoreSight discovery information for the DWT 1528 #define M33_DWT_PIDR4_OFFSET _u(0x00001fd0) 1529 #define M33_DWT_PIDR4_BITS _u(0x000000ff) 1530 #define M33_DWT_PIDR4_RESET _u(0x00000004) 1531 // ----------------------------------------------------------------------------- 1532 // Field : M33_DWT_PIDR4_SIZE 1533 // Description : See CoreSight Architecture Specification 1534 #define M33_DWT_PIDR4_SIZE_RESET _u(0x0) 1535 #define M33_DWT_PIDR4_SIZE_BITS _u(0x000000f0) 1536 #define M33_DWT_PIDR4_SIZE_MSB _u(7) 1537 #define M33_DWT_PIDR4_SIZE_LSB _u(4) 1538 #define M33_DWT_PIDR4_SIZE_ACCESS "RO" 1539 // ----------------------------------------------------------------------------- 1540 // Field : M33_DWT_PIDR4_DES_2 1541 // Description : See CoreSight Architecture Specification 1542 #define M33_DWT_PIDR4_DES_2_RESET _u(0x4) 1543 #define M33_DWT_PIDR4_DES_2_BITS _u(0x0000000f) 1544 #define M33_DWT_PIDR4_DES_2_MSB _u(3) 1545 #define M33_DWT_PIDR4_DES_2_LSB _u(0) 1546 #define M33_DWT_PIDR4_DES_2_ACCESS "RO" 1547 // ============================================================================= 1548 // Register : M33_DWT_PIDR5 1549 // Description : Provides CoreSight discovery information for the DWT 1550 #define M33_DWT_PIDR5_OFFSET _u(0x00001fd4) 1551 #define M33_DWT_PIDR5_BITS _u(0x00000000) 1552 #define M33_DWT_PIDR5_RESET _u(0x00000000) 1553 #define M33_DWT_PIDR5_MSB _u(31) 1554 #define M33_DWT_PIDR5_LSB _u(0) 1555 #define M33_DWT_PIDR5_ACCESS "RW" 1556 // ============================================================================= 1557 // Register : M33_DWT_PIDR6 1558 // Description : Provides CoreSight discovery information for the DWT 1559 #define M33_DWT_PIDR6_OFFSET _u(0x00001fd8) 1560 #define M33_DWT_PIDR6_BITS _u(0x00000000) 1561 #define M33_DWT_PIDR6_RESET _u(0x00000000) 1562 #define M33_DWT_PIDR6_MSB _u(31) 1563 #define M33_DWT_PIDR6_LSB _u(0) 1564 #define M33_DWT_PIDR6_ACCESS "RW" 1565 // ============================================================================= 1566 // Register : M33_DWT_PIDR7 1567 // Description : Provides CoreSight discovery information for the DWT 1568 #define M33_DWT_PIDR7_OFFSET _u(0x00001fdc) 1569 #define M33_DWT_PIDR7_BITS _u(0x00000000) 1570 #define M33_DWT_PIDR7_RESET _u(0x00000000) 1571 #define M33_DWT_PIDR7_MSB _u(31) 1572 #define M33_DWT_PIDR7_LSB _u(0) 1573 #define M33_DWT_PIDR7_ACCESS "RW" 1574 // ============================================================================= 1575 // Register : M33_DWT_PIDR0 1576 // Description : Provides CoreSight discovery information for the DWT 1577 #define M33_DWT_PIDR0_OFFSET _u(0x00001fe0) 1578 #define M33_DWT_PIDR0_BITS _u(0x000000ff) 1579 #define M33_DWT_PIDR0_RESET _u(0x00000021) 1580 // ----------------------------------------------------------------------------- 1581 // Field : M33_DWT_PIDR0_PART_0 1582 // Description : See CoreSight Architecture Specification 1583 #define M33_DWT_PIDR0_PART_0_RESET _u(0x21) 1584 #define M33_DWT_PIDR0_PART_0_BITS _u(0x000000ff) 1585 #define M33_DWT_PIDR0_PART_0_MSB _u(7) 1586 #define M33_DWT_PIDR0_PART_0_LSB _u(0) 1587 #define M33_DWT_PIDR0_PART_0_ACCESS "RO" 1588 // ============================================================================= 1589 // Register : M33_DWT_PIDR1 1590 // Description : Provides CoreSight discovery information for the DWT 1591 #define M33_DWT_PIDR1_OFFSET _u(0x00001fe4) 1592 #define M33_DWT_PIDR1_BITS _u(0x000000ff) 1593 #define M33_DWT_PIDR1_RESET _u(0x000000bd) 1594 // ----------------------------------------------------------------------------- 1595 // Field : M33_DWT_PIDR1_DES_0 1596 // Description : See CoreSight Architecture Specification 1597 #define M33_DWT_PIDR1_DES_0_RESET _u(0xb) 1598 #define M33_DWT_PIDR1_DES_0_BITS _u(0x000000f0) 1599 #define M33_DWT_PIDR1_DES_0_MSB _u(7) 1600 #define M33_DWT_PIDR1_DES_0_LSB _u(4) 1601 #define M33_DWT_PIDR1_DES_0_ACCESS "RO" 1602 // ----------------------------------------------------------------------------- 1603 // Field : M33_DWT_PIDR1_PART_1 1604 // Description : See CoreSight Architecture Specification 1605 #define M33_DWT_PIDR1_PART_1_RESET _u(0xd) 1606 #define M33_DWT_PIDR1_PART_1_BITS _u(0x0000000f) 1607 #define M33_DWT_PIDR1_PART_1_MSB _u(3) 1608 #define M33_DWT_PIDR1_PART_1_LSB _u(0) 1609 #define M33_DWT_PIDR1_PART_1_ACCESS "RO" 1610 // ============================================================================= 1611 // Register : M33_DWT_PIDR2 1612 // Description : Provides CoreSight discovery information for the DWT 1613 #define M33_DWT_PIDR2_OFFSET _u(0x00001fe8) 1614 #define M33_DWT_PIDR2_BITS _u(0x000000ff) 1615 #define M33_DWT_PIDR2_RESET _u(0x0000000b) 1616 // ----------------------------------------------------------------------------- 1617 // Field : M33_DWT_PIDR2_REVISION 1618 // Description : See CoreSight Architecture Specification 1619 #define M33_DWT_PIDR2_REVISION_RESET _u(0x0) 1620 #define M33_DWT_PIDR2_REVISION_BITS _u(0x000000f0) 1621 #define M33_DWT_PIDR2_REVISION_MSB _u(7) 1622 #define M33_DWT_PIDR2_REVISION_LSB _u(4) 1623 #define M33_DWT_PIDR2_REVISION_ACCESS "RO" 1624 // ----------------------------------------------------------------------------- 1625 // Field : M33_DWT_PIDR2_JEDEC 1626 // Description : See CoreSight Architecture Specification 1627 #define M33_DWT_PIDR2_JEDEC_RESET _u(0x1) 1628 #define M33_DWT_PIDR2_JEDEC_BITS _u(0x00000008) 1629 #define M33_DWT_PIDR2_JEDEC_MSB _u(3) 1630 #define M33_DWT_PIDR2_JEDEC_LSB _u(3) 1631 #define M33_DWT_PIDR2_JEDEC_ACCESS "RO" 1632 // ----------------------------------------------------------------------------- 1633 // Field : M33_DWT_PIDR2_DES_1 1634 // Description : See CoreSight Architecture Specification 1635 #define M33_DWT_PIDR2_DES_1_RESET _u(0x3) 1636 #define M33_DWT_PIDR2_DES_1_BITS _u(0x00000007) 1637 #define M33_DWT_PIDR2_DES_1_MSB _u(2) 1638 #define M33_DWT_PIDR2_DES_1_LSB _u(0) 1639 #define M33_DWT_PIDR2_DES_1_ACCESS "RO" 1640 // ============================================================================= 1641 // Register : M33_DWT_PIDR3 1642 // Description : Provides CoreSight discovery information for the DWT 1643 #define M33_DWT_PIDR3_OFFSET _u(0x00001fec) 1644 #define M33_DWT_PIDR3_BITS _u(0x000000ff) 1645 #define M33_DWT_PIDR3_RESET _u(0x00000000) 1646 // ----------------------------------------------------------------------------- 1647 // Field : M33_DWT_PIDR3_REVAND 1648 // Description : See CoreSight Architecture Specification 1649 #define M33_DWT_PIDR3_REVAND_RESET _u(0x0) 1650 #define M33_DWT_PIDR3_REVAND_BITS _u(0x000000f0) 1651 #define M33_DWT_PIDR3_REVAND_MSB _u(7) 1652 #define M33_DWT_PIDR3_REVAND_LSB _u(4) 1653 #define M33_DWT_PIDR3_REVAND_ACCESS "RO" 1654 // ----------------------------------------------------------------------------- 1655 // Field : M33_DWT_PIDR3_CMOD 1656 // Description : See CoreSight Architecture Specification 1657 #define M33_DWT_PIDR3_CMOD_RESET _u(0x0) 1658 #define M33_DWT_PIDR3_CMOD_BITS _u(0x0000000f) 1659 #define M33_DWT_PIDR3_CMOD_MSB _u(3) 1660 #define M33_DWT_PIDR3_CMOD_LSB _u(0) 1661 #define M33_DWT_PIDR3_CMOD_ACCESS "RO" 1662 // ============================================================================= 1663 // Register : M33_DWT_CIDR0 1664 // Description : Provides CoreSight discovery information for the DWT 1665 #define M33_DWT_CIDR0_OFFSET _u(0x00001ff0) 1666 #define M33_DWT_CIDR0_BITS _u(0x000000ff) 1667 #define M33_DWT_CIDR0_RESET _u(0x0000000d) 1668 // ----------------------------------------------------------------------------- 1669 // Field : M33_DWT_CIDR0_PRMBL_0 1670 // Description : See CoreSight Architecture Specification 1671 #define M33_DWT_CIDR0_PRMBL_0_RESET _u(0x0d) 1672 #define M33_DWT_CIDR0_PRMBL_0_BITS _u(0x000000ff) 1673 #define M33_DWT_CIDR0_PRMBL_0_MSB _u(7) 1674 #define M33_DWT_CIDR0_PRMBL_0_LSB _u(0) 1675 #define M33_DWT_CIDR0_PRMBL_0_ACCESS "RO" 1676 // ============================================================================= 1677 // Register : M33_DWT_CIDR1 1678 // Description : Provides CoreSight discovery information for the DWT 1679 #define M33_DWT_CIDR1_OFFSET _u(0x00001ff4) 1680 #define M33_DWT_CIDR1_BITS _u(0x000000ff) 1681 #define M33_DWT_CIDR1_RESET _u(0x00000090) 1682 // ----------------------------------------------------------------------------- 1683 // Field : M33_DWT_CIDR1_CLASS 1684 // Description : See CoreSight Architecture Specification 1685 #define M33_DWT_CIDR1_CLASS_RESET _u(0x9) 1686 #define M33_DWT_CIDR1_CLASS_BITS _u(0x000000f0) 1687 #define M33_DWT_CIDR1_CLASS_MSB _u(7) 1688 #define M33_DWT_CIDR1_CLASS_LSB _u(4) 1689 #define M33_DWT_CIDR1_CLASS_ACCESS "RO" 1690 // ----------------------------------------------------------------------------- 1691 // Field : M33_DWT_CIDR1_PRMBL_1 1692 // Description : See CoreSight Architecture Specification 1693 #define M33_DWT_CIDR1_PRMBL_1_RESET _u(0x0) 1694 #define M33_DWT_CIDR1_PRMBL_1_BITS _u(0x0000000f) 1695 #define M33_DWT_CIDR1_PRMBL_1_MSB _u(3) 1696 #define M33_DWT_CIDR1_PRMBL_1_LSB _u(0) 1697 #define M33_DWT_CIDR1_PRMBL_1_ACCESS "RO" 1698 // ============================================================================= 1699 // Register : M33_DWT_CIDR2 1700 // Description : Provides CoreSight discovery information for the DWT 1701 #define M33_DWT_CIDR2_OFFSET _u(0x00001ff8) 1702 #define M33_DWT_CIDR2_BITS _u(0x000000ff) 1703 #define M33_DWT_CIDR2_RESET _u(0x00000005) 1704 // ----------------------------------------------------------------------------- 1705 // Field : M33_DWT_CIDR2_PRMBL_2 1706 // Description : See CoreSight Architecture Specification 1707 #define M33_DWT_CIDR2_PRMBL_2_RESET _u(0x05) 1708 #define M33_DWT_CIDR2_PRMBL_2_BITS _u(0x000000ff) 1709 #define M33_DWT_CIDR2_PRMBL_2_MSB _u(7) 1710 #define M33_DWT_CIDR2_PRMBL_2_LSB _u(0) 1711 #define M33_DWT_CIDR2_PRMBL_2_ACCESS "RO" 1712 // ============================================================================= 1713 // Register : M33_DWT_CIDR3 1714 // Description : Provides CoreSight discovery information for the DWT 1715 #define M33_DWT_CIDR3_OFFSET _u(0x00001ffc) 1716 #define M33_DWT_CIDR3_BITS _u(0x000000ff) 1717 #define M33_DWT_CIDR3_RESET _u(0x000000b1) 1718 // ----------------------------------------------------------------------------- 1719 // Field : M33_DWT_CIDR3_PRMBL_3 1720 // Description : See CoreSight Architecture Specification 1721 #define M33_DWT_CIDR3_PRMBL_3_RESET _u(0xb1) 1722 #define M33_DWT_CIDR3_PRMBL_3_BITS _u(0x000000ff) 1723 #define M33_DWT_CIDR3_PRMBL_3_MSB _u(7) 1724 #define M33_DWT_CIDR3_PRMBL_3_LSB _u(0) 1725 #define M33_DWT_CIDR3_PRMBL_3_ACCESS "RO" 1726 // ============================================================================= 1727 // Register : M33_FP_CTRL 1728 // Description : Provides FPB implementation information, and the global enable 1729 // for the FPB unit 1730 #define M33_FP_CTRL_OFFSET _u(0x00002000) 1731 #define M33_FP_CTRL_BITS _u(0xf0007ff3) 1732 #define M33_FP_CTRL_RESET _u(0x60005580) 1733 // ----------------------------------------------------------------------------- 1734 // Field : M33_FP_CTRL_REV 1735 // Description : Flash Patch and Breakpoint Unit architecture revision 1736 #define M33_FP_CTRL_REV_RESET _u(0x6) 1737 #define M33_FP_CTRL_REV_BITS _u(0xf0000000) 1738 #define M33_FP_CTRL_REV_MSB _u(31) 1739 #define M33_FP_CTRL_REV_LSB _u(28) 1740 #define M33_FP_CTRL_REV_ACCESS "RO" 1741 // ----------------------------------------------------------------------------- 1742 // Field : M33_FP_CTRL_NUM_CODE_14_12_ 1743 // Description : Indicates the number of implemented instruction address 1744 // comparators. Zero indicates no Instruction Address comparators 1745 // are implemented. The Instruction Address comparators are 1746 // numbered from 0 to NUM_CODE - 1 1747 #define M33_FP_CTRL_NUM_CODE_14_12__RESET _u(0x5) 1748 #define M33_FP_CTRL_NUM_CODE_14_12__BITS _u(0x00007000) 1749 #define M33_FP_CTRL_NUM_CODE_14_12__MSB _u(14) 1750 #define M33_FP_CTRL_NUM_CODE_14_12__LSB _u(12) 1751 #define M33_FP_CTRL_NUM_CODE_14_12__ACCESS "RO" 1752 // ----------------------------------------------------------------------------- 1753 // Field : M33_FP_CTRL_NUM_LIT 1754 // Description : Indicates the number of implemented literal address 1755 // comparators. The Literal Address comparators are numbered from 1756 // NUM_CODE to NUM_CODE + NUM_LIT - 1 1757 #define M33_FP_CTRL_NUM_LIT_RESET _u(0x5) 1758 #define M33_FP_CTRL_NUM_LIT_BITS _u(0x00000f00) 1759 #define M33_FP_CTRL_NUM_LIT_MSB _u(11) 1760 #define M33_FP_CTRL_NUM_LIT_LSB _u(8) 1761 #define M33_FP_CTRL_NUM_LIT_ACCESS "RO" 1762 // ----------------------------------------------------------------------------- 1763 // Field : M33_FP_CTRL_NUM_CODE_7_4_ 1764 // Description : Indicates the number of implemented instruction address 1765 // comparators. Zero indicates no Instruction Address comparators 1766 // are implemented. The Instruction Address comparators are 1767 // numbered from 0 to NUM_CODE - 1 1768 #define M33_FP_CTRL_NUM_CODE_7_4__RESET _u(0x8) 1769 #define M33_FP_CTRL_NUM_CODE_7_4__BITS _u(0x000000f0) 1770 #define M33_FP_CTRL_NUM_CODE_7_4__MSB _u(7) 1771 #define M33_FP_CTRL_NUM_CODE_7_4__LSB _u(4) 1772 #define M33_FP_CTRL_NUM_CODE_7_4__ACCESS "RO" 1773 // ----------------------------------------------------------------------------- 1774 // Field : M33_FP_CTRL_KEY 1775 // Description : Writes to the FP_CTRL are ignored unless KEY is concurrently 1776 // written to one 1777 #define M33_FP_CTRL_KEY_RESET _u(0x0) 1778 #define M33_FP_CTRL_KEY_BITS _u(0x00000002) 1779 #define M33_FP_CTRL_KEY_MSB _u(1) 1780 #define M33_FP_CTRL_KEY_LSB _u(1) 1781 #define M33_FP_CTRL_KEY_ACCESS "RW" 1782 // ----------------------------------------------------------------------------- 1783 // Field : M33_FP_CTRL_ENABLE 1784 // Description : Enables the FPB 1785 #define M33_FP_CTRL_ENABLE_RESET _u(0x0) 1786 #define M33_FP_CTRL_ENABLE_BITS _u(0x00000001) 1787 #define M33_FP_CTRL_ENABLE_MSB _u(0) 1788 #define M33_FP_CTRL_ENABLE_LSB _u(0) 1789 #define M33_FP_CTRL_ENABLE_ACCESS "RW" 1790 // ============================================================================= 1791 // Register : M33_FP_REMAP 1792 // Description : Indicates whether the implementation supports Flash Patch remap 1793 // and, if it does, holds the target address for remap 1794 #define M33_FP_REMAP_OFFSET _u(0x00002004) 1795 #define M33_FP_REMAP_BITS _u(0x3fffffe0) 1796 #define M33_FP_REMAP_RESET _u(0x00000000) 1797 // ----------------------------------------------------------------------------- 1798 // Field : M33_FP_REMAP_RMPSPT 1799 // Description : Indicates whether the FPB unit supports the Flash Patch remap 1800 // function 1801 #define M33_FP_REMAP_RMPSPT_RESET _u(0x0) 1802 #define M33_FP_REMAP_RMPSPT_BITS _u(0x20000000) 1803 #define M33_FP_REMAP_RMPSPT_MSB _u(29) 1804 #define M33_FP_REMAP_RMPSPT_LSB _u(29) 1805 #define M33_FP_REMAP_RMPSPT_ACCESS "RO" 1806 // ----------------------------------------------------------------------------- 1807 // Field : M33_FP_REMAP_REMAP 1808 // Description : Holds the bits[28:5] of the Flash Patch remap address 1809 #define M33_FP_REMAP_REMAP_RESET _u(0x000000) 1810 #define M33_FP_REMAP_REMAP_BITS _u(0x1fffffe0) 1811 #define M33_FP_REMAP_REMAP_MSB _u(28) 1812 #define M33_FP_REMAP_REMAP_LSB _u(5) 1813 #define M33_FP_REMAP_REMAP_ACCESS "RO" 1814 // ============================================================================= 1815 // Register : M33_FP_COMP0 1816 // Description : Holds an address for comparison. The effect of the match 1817 // depends on the configuration of the FPB and whether the 1818 // comparator is an instruction address comparator or a literal 1819 // address comparator 1820 #define M33_FP_COMP0_OFFSET _u(0x00002008) 1821 #define M33_FP_COMP0_BITS _u(0x00000001) 1822 #define M33_FP_COMP0_RESET _u(0x00000000) 1823 // ----------------------------------------------------------------------------- 1824 // Field : M33_FP_COMP0_BE 1825 // Description : Selects between flashpatch and breakpoint functionality 1826 #define M33_FP_COMP0_BE_RESET _u(0x0) 1827 #define M33_FP_COMP0_BE_BITS _u(0x00000001) 1828 #define M33_FP_COMP0_BE_MSB _u(0) 1829 #define M33_FP_COMP0_BE_LSB _u(0) 1830 #define M33_FP_COMP0_BE_ACCESS "RW" 1831 // ============================================================================= 1832 // Register : M33_FP_COMP1 1833 // Description : Holds an address for comparison. The effect of the match 1834 // depends on the configuration of the FPB and whether the 1835 // comparator is an instruction address comparator or a literal 1836 // address comparator 1837 #define M33_FP_COMP1_OFFSET _u(0x0000200c) 1838 #define M33_FP_COMP1_BITS _u(0x00000001) 1839 #define M33_FP_COMP1_RESET _u(0x00000000) 1840 // ----------------------------------------------------------------------------- 1841 // Field : M33_FP_COMP1_BE 1842 // Description : Selects between flashpatch and breakpoint functionality 1843 #define M33_FP_COMP1_BE_RESET _u(0x0) 1844 #define M33_FP_COMP1_BE_BITS _u(0x00000001) 1845 #define M33_FP_COMP1_BE_MSB _u(0) 1846 #define M33_FP_COMP1_BE_LSB _u(0) 1847 #define M33_FP_COMP1_BE_ACCESS "RW" 1848 // ============================================================================= 1849 // Register : M33_FP_COMP2 1850 // Description : Holds an address for comparison. The effect of the match 1851 // depends on the configuration of the FPB and whether the 1852 // comparator is an instruction address comparator or a literal 1853 // address comparator 1854 #define M33_FP_COMP2_OFFSET _u(0x00002010) 1855 #define M33_FP_COMP2_BITS _u(0x00000001) 1856 #define M33_FP_COMP2_RESET _u(0x00000000) 1857 // ----------------------------------------------------------------------------- 1858 // Field : M33_FP_COMP2_BE 1859 // Description : Selects between flashpatch and breakpoint functionality 1860 #define M33_FP_COMP2_BE_RESET _u(0x0) 1861 #define M33_FP_COMP2_BE_BITS _u(0x00000001) 1862 #define M33_FP_COMP2_BE_MSB _u(0) 1863 #define M33_FP_COMP2_BE_LSB _u(0) 1864 #define M33_FP_COMP2_BE_ACCESS "RW" 1865 // ============================================================================= 1866 // Register : M33_FP_COMP3 1867 // Description : Holds an address for comparison. The effect of the match 1868 // depends on the configuration of the FPB and whether the 1869 // comparator is an instruction address comparator or a literal 1870 // address comparator 1871 #define M33_FP_COMP3_OFFSET _u(0x00002014) 1872 #define M33_FP_COMP3_BITS _u(0x00000001) 1873 #define M33_FP_COMP3_RESET _u(0x00000000) 1874 // ----------------------------------------------------------------------------- 1875 // Field : M33_FP_COMP3_BE 1876 // Description : Selects between flashpatch and breakpoint functionality 1877 #define M33_FP_COMP3_BE_RESET _u(0x0) 1878 #define M33_FP_COMP3_BE_BITS _u(0x00000001) 1879 #define M33_FP_COMP3_BE_MSB _u(0) 1880 #define M33_FP_COMP3_BE_LSB _u(0) 1881 #define M33_FP_COMP3_BE_ACCESS "RW" 1882 // ============================================================================= 1883 // Register : M33_FP_COMP4 1884 // Description : Holds an address for comparison. The effect of the match 1885 // depends on the configuration of the FPB and whether the 1886 // comparator is an instruction address comparator or a literal 1887 // address comparator 1888 #define M33_FP_COMP4_OFFSET _u(0x00002018) 1889 #define M33_FP_COMP4_BITS _u(0x00000001) 1890 #define M33_FP_COMP4_RESET _u(0x00000000) 1891 // ----------------------------------------------------------------------------- 1892 // Field : M33_FP_COMP4_BE 1893 // Description : Selects between flashpatch and breakpoint functionality 1894 #define M33_FP_COMP4_BE_RESET _u(0x0) 1895 #define M33_FP_COMP4_BE_BITS _u(0x00000001) 1896 #define M33_FP_COMP4_BE_MSB _u(0) 1897 #define M33_FP_COMP4_BE_LSB _u(0) 1898 #define M33_FP_COMP4_BE_ACCESS "RW" 1899 // ============================================================================= 1900 // Register : M33_FP_COMP5 1901 // Description : Holds an address for comparison. The effect of the match 1902 // depends on the configuration of the FPB and whether the 1903 // comparator is an instruction address comparator or a literal 1904 // address comparator 1905 #define M33_FP_COMP5_OFFSET _u(0x0000201c) 1906 #define M33_FP_COMP5_BITS _u(0x00000001) 1907 #define M33_FP_COMP5_RESET _u(0x00000000) 1908 // ----------------------------------------------------------------------------- 1909 // Field : M33_FP_COMP5_BE 1910 // Description : Selects between flashpatch and breakpoint functionality 1911 #define M33_FP_COMP5_BE_RESET _u(0x0) 1912 #define M33_FP_COMP5_BE_BITS _u(0x00000001) 1913 #define M33_FP_COMP5_BE_MSB _u(0) 1914 #define M33_FP_COMP5_BE_LSB _u(0) 1915 #define M33_FP_COMP5_BE_ACCESS "RW" 1916 // ============================================================================= 1917 // Register : M33_FP_COMP6 1918 // Description : Holds an address for comparison. The effect of the match 1919 // depends on the configuration of the FPB and whether the 1920 // comparator is an instruction address comparator or a literal 1921 // address comparator 1922 #define M33_FP_COMP6_OFFSET _u(0x00002020) 1923 #define M33_FP_COMP6_BITS _u(0x00000001) 1924 #define M33_FP_COMP6_RESET _u(0x00000000) 1925 // ----------------------------------------------------------------------------- 1926 // Field : M33_FP_COMP6_BE 1927 // Description : Selects between flashpatch and breakpoint functionality 1928 #define M33_FP_COMP6_BE_RESET _u(0x0) 1929 #define M33_FP_COMP6_BE_BITS _u(0x00000001) 1930 #define M33_FP_COMP6_BE_MSB _u(0) 1931 #define M33_FP_COMP6_BE_LSB _u(0) 1932 #define M33_FP_COMP6_BE_ACCESS "RW" 1933 // ============================================================================= 1934 // Register : M33_FP_COMP7 1935 // Description : Holds an address for comparison. The effect of the match 1936 // depends on the configuration of the FPB and whether the 1937 // comparator is an instruction address comparator or a literal 1938 // address comparator 1939 #define M33_FP_COMP7_OFFSET _u(0x00002024) 1940 #define M33_FP_COMP7_BITS _u(0x00000001) 1941 #define M33_FP_COMP7_RESET _u(0x00000000) 1942 // ----------------------------------------------------------------------------- 1943 // Field : M33_FP_COMP7_BE 1944 // Description : Selects between flashpatch and breakpoint functionality 1945 #define M33_FP_COMP7_BE_RESET _u(0x0) 1946 #define M33_FP_COMP7_BE_BITS _u(0x00000001) 1947 #define M33_FP_COMP7_BE_MSB _u(0) 1948 #define M33_FP_COMP7_BE_LSB _u(0) 1949 #define M33_FP_COMP7_BE_ACCESS "RW" 1950 // ============================================================================= 1951 // Register : M33_FP_DEVARCH 1952 // Description : Provides CoreSight discovery information for the FPB 1953 #define M33_FP_DEVARCH_OFFSET _u(0x00002fbc) 1954 #define M33_FP_DEVARCH_BITS _u(0xffffffff) 1955 #define M33_FP_DEVARCH_RESET _u(0x47701a03) 1956 // ----------------------------------------------------------------------------- 1957 // Field : M33_FP_DEVARCH_ARCHITECT 1958 // Description : Defines the architect of the component. Bits [31:28] are the 1959 // JEP106 continuation code (JEP106 bank ID, minus 1) and bits 1960 // [27:21] are the JEP106 ID code. 1961 #define M33_FP_DEVARCH_ARCHITECT_RESET _u(0x23b) 1962 #define M33_FP_DEVARCH_ARCHITECT_BITS _u(0xffe00000) 1963 #define M33_FP_DEVARCH_ARCHITECT_MSB _u(31) 1964 #define M33_FP_DEVARCH_ARCHITECT_LSB _u(21) 1965 #define M33_FP_DEVARCH_ARCHITECT_ACCESS "RO" 1966 // ----------------------------------------------------------------------------- 1967 // Field : M33_FP_DEVARCH_PRESENT 1968 // Description : Defines that the DEVARCH register is present 1969 #define M33_FP_DEVARCH_PRESENT_RESET _u(0x1) 1970 #define M33_FP_DEVARCH_PRESENT_BITS _u(0x00100000) 1971 #define M33_FP_DEVARCH_PRESENT_MSB _u(20) 1972 #define M33_FP_DEVARCH_PRESENT_LSB _u(20) 1973 #define M33_FP_DEVARCH_PRESENT_ACCESS "RO" 1974 // ----------------------------------------------------------------------------- 1975 // Field : M33_FP_DEVARCH_REVISION 1976 // Description : Defines the architecture revision of the component 1977 #define M33_FP_DEVARCH_REVISION_RESET _u(0x0) 1978 #define M33_FP_DEVARCH_REVISION_BITS _u(0x000f0000) 1979 #define M33_FP_DEVARCH_REVISION_MSB _u(19) 1980 #define M33_FP_DEVARCH_REVISION_LSB _u(16) 1981 #define M33_FP_DEVARCH_REVISION_ACCESS "RO" 1982 // ----------------------------------------------------------------------------- 1983 // Field : M33_FP_DEVARCH_ARCHVER 1984 // Description : Defines the architecture version of the component 1985 #define M33_FP_DEVARCH_ARCHVER_RESET _u(0x1) 1986 #define M33_FP_DEVARCH_ARCHVER_BITS _u(0x0000f000) 1987 #define M33_FP_DEVARCH_ARCHVER_MSB _u(15) 1988 #define M33_FP_DEVARCH_ARCHVER_LSB _u(12) 1989 #define M33_FP_DEVARCH_ARCHVER_ACCESS "RO" 1990 // ----------------------------------------------------------------------------- 1991 // Field : M33_FP_DEVARCH_ARCHPART 1992 // Description : Defines the architecture of the component 1993 #define M33_FP_DEVARCH_ARCHPART_RESET _u(0xa03) 1994 #define M33_FP_DEVARCH_ARCHPART_BITS _u(0x00000fff) 1995 #define M33_FP_DEVARCH_ARCHPART_MSB _u(11) 1996 #define M33_FP_DEVARCH_ARCHPART_LSB _u(0) 1997 #define M33_FP_DEVARCH_ARCHPART_ACCESS "RO" 1998 // ============================================================================= 1999 // Register : M33_FP_DEVTYPE 2000 // Description : Provides CoreSight discovery information for the FPB 2001 #define M33_FP_DEVTYPE_OFFSET _u(0x00002fcc) 2002 #define M33_FP_DEVTYPE_BITS _u(0x000000ff) 2003 #define M33_FP_DEVTYPE_RESET _u(0x00000000) 2004 // ----------------------------------------------------------------------------- 2005 // Field : M33_FP_DEVTYPE_SUB 2006 // Description : Component sub-type 2007 #define M33_FP_DEVTYPE_SUB_RESET _u(0x0) 2008 #define M33_FP_DEVTYPE_SUB_BITS _u(0x000000f0) 2009 #define M33_FP_DEVTYPE_SUB_MSB _u(7) 2010 #define M33_FP_DEVTYPE_SUB_LSB _u(4) 2011 #define M33_FP_DEVTYPE_SUB_ACCESS "RO" 2012 // ----------------------------------------------------------------------------- 2013 // Field : M33_FP_DEVTYPE_MAJOR 2014 // Description : Component major type 2015 #define M33_FP_DEVTYPE_MAJOR_RESET _u(0x0) 2016 #define M33_FP_DEVTYPE_MAJOR_BITS _u(0x0000000f) 2017 #define M33_FP_DEVTYPE_MAJOR_MSB _u(3) 2018 #define M33_FP_DEVTYPE_MAJOR_LSB _u(0) 2019 #define M33_FP_DEVTYPE_MAJOR_ACCESS "RO" 2020 // ============================================================================= 2021 // Register : M33_FP_PIDR4 2022 // Description : Provides CoreSight discovery information for the FP 2023 #define M33_FP_PIDR4_OFFSET _u(0x00002fd0) 2024 #define M33_FP_PIDR4_BITS _u(0x000000ff) 2025 #define M33_FP_PIDR4_RESET _u(0x00000004) 2026 // ----------------------------------------------------------------------------- 2027 // Field : M33_FP_PIDR4_SIZE 2028 // Description : See CoreSight Architecture Specification 2029 #define M33_FP_PIDR4_SIZE_RESET _u(0x0) 2030 #define M33_FP_PIDR4_SIZE_BITS _u(0x000000f0) 2031 #define M33_FP_PIDR4_SIZE_MSB _u(7) 2032 #define M33_FP_PIDR4_SIZE_LSB _u(4) 2033 #define M33_FP_PIDR4_SIZE_ACCESS "RO" 2034 // ----------------------------------------------------------------------------- 2035 // Field : M33_FP_PIDR4_DES_2 2036 // Description : See CoreSight Architecture Specification 2037 #define M33_FP_PIDR4_DES_2_RESET _u(0x4) 2038 #define M33_FP_PIDR4_DES_2_BITS _u(0x0000000f) 2039 #define M33_FP_PIDR4_DES_2_MSB _u(3) 2040 #define M33_FP_PIDR4_DES_2_LSB _u(0) 2041 #define M33_FP_PIDR4_DES_2_ACCESS "RO" 2042 // ============================================================================= 2043 // Register : M33_FP_PIDR5 2044 // Description : Provides CoreSight discovery information for the FP 2045 #define M33_FP_PIDR5_OFFSET _u(0x00002fd4) 2046 #define M33_FP_PIDR5_BITS _u(0x00000000) 2047 #define M33_FP_PIDR5_RESET _u(0x00000000) 2048 #define M33_FP_PIDR5_MSB _u(31) 2049 #define M33_FP_PIDR5_LSB _u(0) 2050 #define M33_FP_PIDR5_ACCESS "RW" 2051 // ============================================================================= 2052 // Register : M33_FP_PIDR6 2053 // Description : Provides CoreSight discovery information for the FP 2054 #define M33_FP_PIDR6_OFFSET _u(0x00002fd8) 2055 #define M33_FP_PIDR6_BITS _u(0x00000000) 2056 #define M33_FP_PIDR6_RESET _u(0x00000000) 2057 #define M33_FP_PIDR6_MSB _u(31) 2058 #define M33_FP_PIDR6_LSB _u(0) 2059 #define M33_FP_PIDR6_ACCESS "RW" 2060 // ============================================================================= 2061 // Register : M33_FP_PIDR7 2062 // Description : Provides CoreSight discovery information for the FP 2063 #define M33_FP_PIDR7_OFFSET _u(0x00002fdc) 2064 #define M33_FP_PIDR7_BITS _u(0x00000000) 2065 #define M33_FP_PIDR7_RESET _u(0x00000000) 2066 #define M33_FP_PIDR7_MSB _u(31) 2067 #define M33_FP_PIDR7_LSB _u(0) 2068 #define M33_FP_PIDR7_ACCESS "RW" 2069 // ============================================================================= 2070 // Register : M33_FP_PIDR0 2071 // Description : Provides CoreSight discovery information for the FP 2072 #define M33_FP_PIDR0_OFFSET _u(0x00002fe0) 2073 #define M33_FP_PIDR0_BITS _u(0x000000ff) 2074 #define M33_FP_PIDR0_RESET _u(0x00000021) 2075 // ----------------------------------------------------------------------------- 2076 // Field : M33_FP_PIDR0_PART_0 2077 // Description : See CoreSight Architecture Specification 2078 #define M33_FP_PIDR0_PART_0_RESET _u(0x21) 2079 #define M33_FP_PIDR0_PART_0_BITS _u(0x000000ff) 2080 #define M33_FP_PIDR0_PART_0_MSB _u(7) 2081 #define M33_FP_PIDR0_PART_0_LSB _u(0) 2082 #define M33_FP_PIDR0_PART_0_ACCESS "RO" 2083 // ============================================================================= 2084 // Register : M33_FP_PIDR1 2085 // Description : Provides CoreSight discovery information for the FP 2086 #define M33_FP_PIDR1_OFFSET _u(0x00002fe4) 2087 #define M33_FP_PIDR1_BITS _u(0x000000ff) 2088 #define M33_FP_PIDR1_RESET _u(0x000000bd) 2089 // ----------------------------------------------------------------------------- 2090 // Field : M33_FP_PIDR1_DES_0 2091 // Description : See CoreSight Architecture Specification 2092 #define M33_FP_PIDR1_DES_0_RESET _u(0xb) 2093 #define M33_FP_PIDR1_DES_0_BITS _u(0x000000f0) 2094 #define M33_FP_PIDR1_DES_0_MSB _u(7) 2095 #define M33_FP_PIDR1_DES_0_LSB _u(4) 2096 #define M33_FP_PIDR1_DES_0_ACCESS "RO" 2097 // ----------------------------------------------------------------------------- 2098 // Field : M33_FP_PIDR1_PART_1 2099 // Description : See CoreSight Architecture Specification 2100 #define M33_FP_PIDR1_PART_1_RESET _u(0xd) 2101 #define M33_FP_PIDR1_PART_1_BITS _u(0x0000000f) 2102 #define M33_FP_PIDR1_PART_1_MSB _u(3) 2103 #define M33_FP_PIDR1_PART_1_LSB _u(0) 2104 #define M33_FP_PIDR1_PART_1_ACCESS "RO" 2105 // ============================================================================= 2106 // Register : M33_FP_PIDR2 2107 // Description : Provides CoreSight discovery information for the FP 2108 #define M33_FP_PIDR2_OFFSET _u(0x00002fe8) 2109 #define M33_FP_PIDR2_BITS _u(0x000000ff) 2110 #define M33_FP_PIDR2_RESET _u(0x0000000b) 2111 // ----------------------------------------------------------------------------- 2112 // Field : M33_FP_PIDR2_REVISION 2113 // Description : See CoreSight Architecture Specification 2114 #define M33_FP_PIDR2_REVISION_RESET _u(0x0) 2115 #define M33_FP_PIDR2_REVISION_BITS _u(0x000000f0) 2116 #define M33_FP_PIDR2_REVISION_MSB _u(7) 2117 #define M33_FP_PIDR2_REVISION_LSB _u(4) 2118 #define M33_FP_PIDR2_REVISION_ACCESS "RO" 2119 // ----------------------------------------------------------------------------- 2120 // Field : M33_FP_PIDR2_JEDEC 2121 // Description : See CoreSight Architecture Specification 2122 #define M33_FP_PIDR2_JEDEC_RESET _u(0x1) 2123 #define M33_FP_PIDR2_JEDEC_BITS _u(0x00000008) 2124 #define M33_FP_PIDR2_JEDEC_MSB _u(3) 2125 #define M33_FP_PIDR2_JEDEC_LSB _u(3) 2126 #define M33_FP_PIDR2_JEDEC_ACCESS "RO" 2127 // ----------------------------------------------------------------------------- 2128 // Field : M33_FP_PIDR2_DES_1 2129 // Description : See CoreSight Architecture Specification 2130 #define M33_FP_PIDR2_DES_1_RESET _u(0x3) 2131 #define M33_FP_PIDR2_DES_1_BITS _u(0x00000007) 2132 #define M33_FP_PIDR2_DES_1_MSB _u(2) 2133 #define M33_FP_PIDR2_DES_1_LSB _u(0) 2134 #define M33_FP_PIDR2_DES_1_ACCESS "RO" 2135 // ============================================================================= 2136 // Register : M33_FP_PIDR3 2137 // Description : Provides CoreSight discovery information for the FP 2138 #define M33_FP_PIDR3_OFFSET _u(0x00002fec) 2139 #define M33_FP_PIDR3_BITS _u(0x000000ff) 2140 #define M33_FP_PIDR3_RESET _u(0x00000000) 2141 // ----------------------------------------------------------------------------- 2142 // Field : M33_FP_PIDR3_REVAND 2143 // Description : See CoreSight Architecture Specification 2144 #define M33_FP_PIDR3_REVAND_RESET _u(0x0) 2145 #define M33_FP_PIDR3_REVAND_BITS _u(0x000000f0) 2146 #define M33_FP_PIDR3_REVAND_MSB _u(7) 2147 #define M33_FP_PIDR3_REVAND_LSB _u(4) 2148 #define M33_FP_PIDR3_REVAND_ACCESS "RO" 2149 // ----------------------------------------------------------------------------- 2150 // Field : M33_FP_PIDR3_CMOD 2151 // Description : See CoreSight Architecture Specification 2152 #define M33_FP_PIDR3_CMOD_RESET _u(0x0) 2153 #define M33_FP_PIDR3_CMOD_BITS _u(0x0000000f) 2154 #define M33_FP_PIDR3_CMOD_MSB _u(3) 2155 #define M33_FP_PIDR3_CMOD_LSB _u(0) 2156 #define M33_FP_PIDR3_CMOD_ACCESS "RO" 2157 // ============================================================================= 2158 // Register : M33_FP_CIDR0 2159 // Description : Provides CoreSight discovery information for the FP 2160 #define M33_FP_CIDR0_OFFSET _u(0x00002ff0) 2161 #define M33_FP_CIDR0_BITS _u(0x000000ff) 2162 #define M33_FP_CIDR0_RESET _u(0x0000000d) 2163 // ----------------------------------------------------------------------------- 2164 // Field : M33_FP_CIDR0_PRMBL_0 2165 // Description : See CoreSight Architecture Specification 2166 #define M33_FP_CIDR0_PRMBL_0_RESET _u(0x0d) 2167 #define M33_FP_CIDR0_PRMBL_0_BITS _u(0x000000ff) 2168 #define M33_FP_CIDR0_PRMBL_0_MSB _u(7) 2169 #define M33_FP_CIDR0_PRMBL_0_LSB _u(0) 2170 #define M33_FP_CIDR0_PRMBL_0_ACCESS "RO" 2171 // ============================================================================= 2172 // Register : M33_FP_CIDR1 2173 // Description : Provides CoreSight discovery information for the FP 2174 #define M33_FP_CIDR1_OFFSET _u(0x00002ff4) 2175 #define M33_FP_CIDR1_BITS _u(0x000000ff) 2176 #define M33_FP_CIDR1_RESET _u(0x00000090) 2177 // ----------------------------------------------------------------------------- 2178 // Field : M33_FP_CIDR1_CLASS 2179 // Description : See CoreSight Architecture Specification 2180 #define M33_FP_CIDR1_CLASS_RESET _u(0x9) 2181 #define M33_FP_CIDR1_CLASS_BITS _u(0x000000f0) 2182 #define M33_FP_CIDR1_CLASS_MSB _u(7) 2183 #define M33_FP_CIDR1_CLASS_LSB _u(4) 2184 #define M33_FP_CIDR1_CLASS_ACCESS "RO" 2185 // ----------------------------------------------------------------------------- 2186 // Field : M33_FP_CIDR1_PRMBL_1 2187 // Description : See CoreSight Architecture Specification 2188 #define M33_FP_CIDR1_PRMBL_1_RESET _u(0x0) 2189 #define M33_FP_CIDR1_PRMBL_1_BITS _u(0x0000000f) 2190 #define M33_FP_CIDR1_PRMBL_1_MSB _u(3) 2191 #define M33_FP_CIDR1_PRMBL_1_LSB _u(0) 2192 #define M33_FP_CIDR1_PRMBL_1_ACCESS "RO" 2193 // ============================================================================= 2194 // Register : M33_FP_CIDR2 2195 // Description : Provides CoreSight discovery information for the FP 2196 #define M33_FP_CIDR2_OFFSET _u(0x00002ff8) 2197 #define M33_FP_CIDR2_BITS _u(0x000000ff) 2198 #define M33_FP_CIDR2_RESET _u(0x00000005) 2199 // ----------------------------------------------------------------------------- 2200 // Field : M33_FP_CIDR2_PRMBL_2 2201 // Description : See CoreSight Architecture Specification 2202 #define M33_FP_CIDR2_PRMBL_2_RESET _u(0x05) 2203 #define M33_FP_CIDR2_PRMBL_2_BITS _u(0x000000ff) 2204 #define M33_FP_CIDR2_PRMBL_2_MSB _u(7) 2205 #define M33_FP_CIDR2_PRMBL_2_LSB _u(0) 2206 #define M33_FP_CIDR2_PRMBL_2_ACCESS "RO" 2207 // ============================================================================= 2208 // Register : M33_FP_CIDR3 2209 // Description : Provides CoreSight discovery information for the FP 2210 #define M33_FP_CIDR3_OFFSET _u(0x00002ffc) 2211 #define M33_FP_CIDR3_BITS _u(0x000000ff) 2212 #define M33_FP_CIDR3_RESET _u(0x000000b1) 2213 // ----------------------------------------------------------------------------- 2214 // Field : M33_FP_CIDR3_PRMBL_3 2215 // Description : See CoreSight Architecture Specification 2216 #define M33_FP_CIDR3_PRMBL_3_RESET _u(0xb1) 2217 #define M33_FP_CIDR3_PRMBL_3_BITS _u(0x000000ff) 2218 #define M33_FP_CIDR3_PRMBL_3_MSB _u(7) 2219 #define M33_FP_CIDR3_PRMBL_3_LSB _u(0) 2220 #define M33_FP_CIDR3_PRMBL_3_ACCESS "RO" 2221 // ============================================================================= 2222 // Register : M33_ICTR 2223 // Description : Provides information about the interrupt controller 2224 #define M33_ICTR_OFFSET _u(0x0000e004) 2225 #define M33_ICTR_BITS _u(0x0000000f) 2226 #define M33_ICTR_RESET _u(0x00000001) 2227 // ----------------------------------------------------------------------------- 2228 // Field : M33_ICTR_INTLINESNUM 2229 // Description : Indicates the number of the highest implemented register in 2230 // each of the NVIC control register sets, or in the case of 2231 // NVIC_IPR*n, 4×INTLINESNUM 2232 #define M33_ICTR_INTLINESNUM_RESET _u(0x1) 2233 #define M33_ICTR_INTLINESNUM_BITS _u(0x0000000f) 2234 #define M33_ICTR_INTLINESNUM_MSB _u(3) 2235 #define M33_ICTR_INTLINESNUM_LSB _u(0) 2236 #define M33_ICTR_INTLINESNUM_ACCESS "RO" 2237 // ============================================================================= 2238 // Register : M33_ACTLR 2239 // Description : Provides IMPLEMENTATION DEFINED configuration and control 2240 // options 2241 #define M33_ACTLR_OFFSET _u(0x0000e008) 2242 #define M33_ACTLR_BITS _u(0x20001605) 2243 #define M33_ACTLR_RESET _u(0x00000000) 2244 // ----------------------------------------------------------------------------- 2245 // Field : M33_ACTLR_EXTEXCLALL 2246 // Description : External Exclusives Allowed with no MPU 2247 #define M33_ACTLR_EXTEXCLALL_RESET _u(0x0) 2248 #define M33_ACTLR_EXTEXCLALL_BITS _u(0x20000000) 2249 #define M33_ACTLR_EXTEXCLALL_MSB _u(29) 2250 #define M33_ACTLR_EXTEXCLALL_LSB _u(29) 2251 #define M33_ACTLR_EXTEXCLALL_ACCESS "RW" 2252 // ----------------------------------------------------------------------------- 2253 // Field : M33_ACTLR_DISITMATBFLUSH 2254 // Description : Disable ATB Flush 2255 #define M33_ACTLR_DISITMATBFLUSH_RESET _u(0x0) 2256 #define M33_ACTLR_DISITMATBFLUSH_BITS _u(0x00001000) 2257 #define M33_ACTLR_DISITMATBFLUSH_MSB _u(12) 2258 #define M33_ACTLR_DISITMATBFLUSH_LSB _u(12) 2259 #define M33_ACTLR_DISITMATBFLUSH_ACCESS "RW" 2260 // ----------------------------------------------------------------------------- 2261 // Field : M33_ACTLR_FPEXCODIS 2262 // Description : Disable FPU exception outputs 2263 #define M33_ACTLR_FPEXCODIS_RESET _u(0x0) 2264 #define M33_ACTLR_FPEXCODIS_BITS _u(0x00000400) 2265 #define M33_ACTLR_FPEXCODIS_MSB _u(10) 2266 #define M33_ACTLR_FPEXCODIS_LSB _u(10) 2267 #define M33_ACTLR_FPEXCODIS_ACCESS "RW" 2268 // ----------------------------------------------------------------------------- 2269 // Field : M33_ACTLR_DISOOFP 2270 // Description : Disable out-of-order FP instruction completion 2271 #define M33_ACTLR_DISOOFP_RESET _u(0x0) 2272 #define M33_ACTLR_DISOOFP_BITS _u(0x00000200) 2273 #define M33_ACTLR_DISOOFP_MSB _u(9) 2274 #define M33_ACTLR_DISOOFP_LSB _u(9) 2275 #define M33_ACTLR_DISOOFP_ACCESS "RW" 2276 // ----------------------------------------------------------------------------- 2277 // Field : M33_ACTLR_DISFOLD 2278 // Description : Disable dual-issue. 2279 #define M33_ACTLR_DISFOLD_RESET _u(0x0) 2280 #define M33_ACTLR_DISFOLD_BITS _u(0x00000004) 2281 #define M33_ACTLR_DISFOLD_MSB _u(2) 2282 #define M33_ACTLR_DISFOLD_LSB _u(2) 2283 #define M33_ACTLR_DISFOLD_ACCESS "RW" 2284 // ----------------------------------------------------------------------------- 2285 // Field : M33_ACTLR_DISMCYCINT 2286 // Description : Disable dual-issue. 2287 #define M33_ACTLR_DISMCYCINT_RESET _u(0x0) 2288 #define M33_ACTLR_DISMCYCINT_BITS _u(0x00000001) 2289 #define M33_ACTLR_DISMCYCINT_MSB _u(0) 2290 #define M33_ACTLR_DISMCYCINT_LSB _u(0) 2291 #define M33_ACTLR_DISMCYCINT_ACCESS "RW" 2292 // ============================================================================= 2293 // Register : M33_SYST_CSR 2294 // Description : Use the SysTick Control and Status Register to enable the 2295 // SysTick features. 2296 #define M33_SYST_CSR_OFFSET _u(0x0000e010) 2297 #define M33_SYST_CSR_BITS _u(0x00010007) 2298 #define M33_SYST_CSR_RESET _u(0x00000000) 2299 // ----------------------------------------------------------------------------- 2300 // Field : M33_SYST_CSR_COUNTFLAG 2301 // Description : Returns 1 if timer counted to 0 since last time this was read. 2302 // Clears on read by application or debugger. 2303 #define M33_SYST_CSR_COUNTFLAG_RESET _u(0x0) 2304 #define M33_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) 2305 #define M33_SYST_CSR_COUNTFLAG_MSB _u(16) 2306 #define M33_SYST_CSR_COUNTFLAG_LSB _u(16) 2307 #define M33_SYST_CSR_COUNTFLAG_ACCESS "RO" 2308 // ----------------------------------------------------------------------------- 2309 // Field : M33_SYST_CSR_CLKSOURCE 2310 // Description : SysTick clock source. Always reads as one if SYST_CALIB reports 2311 // NOREF. 2312 // Selects the SysTick timer clock source: 2313 // 0 = External reference clock. 2314 // 1 = Processor clock. 2315 #define M33_SYST_CSR_CLKSOURCE_RESET _u(0x0) 2316 #define M33_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) 2317 #define M33_SYST_CSR_CLKSOURCE_MSB _u(2) 2318 #define M33_SYST_CSR_CLKSOURCE_LSB _u(2) 2319 #define M33_SYST_CSR_CLKSOURCE_ACCESS "RW" 2320 // ----------------------------------------------------------------------------- 2321 // Field : M33_SYST_CSR_TICKINT 2322 // Description : Enables SysTick exception request: 2323 // 0 = Counting down to zero does not assert the SysTick exception 2324 // request. 2325 // 1 = Counting down to zero to asserts the SysTick exception 2326 // request. 2327 #define M33_SYST_CSR_TICKINT_RESET _u(0x0) 2328 #define M33_SYST_CSR_TICKINT_BITS _u(0x00000002) 2329 #define M33_SYST_CSR_TICKINT_MSB _u(1) 2330 #define M33_SYST_CSR_TICKINT_LSB _u(1) 2331 #define M33_SYST_CSR_TICKINT_ACCESS "RW" 2332 // ----------------------------------------------------------------------------- 2333 // Field : M33_SYST_CSR_ENABLE 2334 // Description : Enable SysTick counter: 2335 // 0 = Counter disabled. 2336 // 1 = Counter enabled. 2337 #define M33_SYST_CSR_ENABLE_RESET _u(0x0) 2338 #define M33_SYST_CSR_ENABLE_BITS _u(0x00000001) 2339 #define M33_SYST_CSR_ENABLE_MSB _u(0) 2340 #define M33_SYST_CSR_ENABLE_LSB _u(0) 2341 #define M33_SYST_CSR_ENABLE_ACCESS "RW" 2342 // ============================================================================= 2343 // Register : M33_SYST_RVR 2344 // Description : Use the SysTick Reload Value Register to specify the start 2345 // value to load into the current value register when the counter 2346 // reaches 0. It can be any value between 0 and 0x00FFFFFF. A 2347 // start value of 0 is possible, but has no effect because the 2348 // SysTick interrupt and COUNTFLAG are activated when counting 2349 // from 1 to 0. The reset value of this register is UNKNOWN. 2350 // To generate a multi-shot timer with a period of N processor 2351 // clock cycles, use a RELOAD value of N-1. For example, if the 2352 // SysTick interrupt is required every 100 clock pulses, set 2353 // RELOAD to 99. 2354 #define M33_SYST_RVR_OFFSET _u(0x0000e014) 2355 #define M33_SYST_RVR_BITS _u(0x00ffffff) 2356 #define M33_SYST_RVR_RESET _u(0x00000000) 2357 // ----------------------------------------------------------------------------- 2358 // Field : M33_SYST_RVR_RELOAD 2359 // Description : Value to load into the SysTick Current Value Register when the 2360 // counter reaches 0. 2361 #define M33_SYST_RVR_RELOAD_RESET _u(0x000000) 2362 #define M33_SYST_RVR_RELOAD_BITS _u(0x00ffffff) 2363 #define M33_SYST_RVR_RELOAD_MSB _u(23) 2364 #define M33_SYST_RVR_RELOAD_LSB _u(0) 2365 #define M33_SYST_RVR_RELOAD_ACCESS "RW" 2366 // ============================================================================= 2367 // Register : M33_SYST_CVR 2368 // Description : Use the SysTick Current Value Register to find the current 2369 // value in the register. The reset value of this register is 2370 // UNKNOWN. 2371 #define M33_SYST_CVR_OFFSET _u(0x0000e018) 2372 #define M33_SYST_CVR_BITS _u(0x00ffffff) 2373 #define M33_SYST_CVR_RESET _u(0x00000000) 2374 // ----------------------------------------------------------------------------- 2375 // Field : M33_SYST_CVR_CURRENT 2376 // Description : Reads return the current value of the SysTick counter. This 2377 // register is write-clear. Writing to it with any value clears 2378 // the register to 0. Clearing this register also clears the 2379 // COUNTFLAG bit of the SysTick Control and Status Register. 2380 #define M33_SYST_CVR_CURRENT_RESET _u(0x000000) 2381 #define M33_SYST_CVR_CURRENT_BITS _u(0x00ffffff) 2382 #define M33_SYST_CVR_CURRENT_MSB _u(23) 2383 #define M33_SYST_CVR_CURRENT_LSB _u(0) 2384 #define M33_SYST_CVR_CURRENT_ACCESS "RW" 2385 // ============================================================================= 2386 // Register : M33_SYST_CALIB 2387 // Description : Use the SysTick Calibration Value Register to enable software 2388 // to scale to any required speed using divide and multiply. 2389 #define M33_SYST_CALIB_OFFSET _u(0x0000e01c) 2390 #define M33_SYST_CALIB_BITS _u(0xc0ffffff) 2391 #define M33_SYST_CALIB_RESET _u(0x00000000) 2392 // ----------------------------------------------------------------------------- 2393 // Field : M33_SYST_CALIB_NOREF 2394 // Description : If reads as 1, the Reference clock is not provided - the 2395 // CLKSOURCE bit of the SysTick Control and Status register will 2396 // be forced to 1 and cannot be cleared to 0. 2397 #define M33_SYST_CALIB_NOREF_RESET _u(0x0) 2398 #define M33_SYST_CALIB_NOREF_BITS _u(0x80000000) 2399 #define M33_SYST_CALIB_NOREF_MSB _u(31) 2400 #define M33_SYST_CALIB_NOREF_LSB _u(31) 2401 #define M33_SYST_CALIB_NOREF_ACCESS "RO" 2402 // ----------------------------------------------------------------------------- 2403 // Field : M33_SYST_CALIB_SKEW 2404 // Description : If reads as 1, the calibration value for 10ms is inexact (due 2405 // to clock frequency). 2406 #define M33_SYST_CALIB_SKEW_RESET _u(0x0) 2407 #define M33_SYST_CALIB_SKEW_BITS _u(0x40000000) 2408 #define M33_SYST_CALIB_SKEW_MSB _u(30) 2409 #define M33_SYST_CALIB_SKEW_LSB _u(30) 2410 #define M33_SYST_CALIB_SKEW_ACCESS "RO" 2411 // ----------------------------------------------------------------------------- 2412 // Field : M33_SYST_CALIB_TENMS 2413 // Description : An optional Reload value to be used for 10ms (100Hz) timing, 2414 // subject to system clock skew errors. If the value reads as 0, 2415 // the calibration value is not known. 2416 #define M33_SYST_CALIB_TENMS_RESET _u(0x000000) 2417 #define M33_SYST_CALIB_TENMS_BITS _u(0x00ffffff) 2418 #define M33_SYST_CALIB_TENMS_MSB _u(23) 2419 #define M33_SYST_CALIB_TENMS_LSB _u(0) 2420 #define M33_SYST_CALIB_TENMS_ACCESS "RO" 2421 // ============================================================================= 2422 // Register : M33_NVIC_ISER0 2423 // Description : Enables or reads the enabled state of each group of 32 2424 // interrupts 2425 #define M33_NVIC_ISER0_OFFSET _u(0x0000e100) 2426 #define M33_NVIC_ISER0_BITS _u(0xffffffff) 2427 #define M33_NVIC_ISER0_RESET _u(0x00000000) 2428 // ----------------------------------------------------------------------------- 2429 // Field : M33_NVIC_ISER0_SETENA 2430 // Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n 2431 // + m is enabled 2432 #define M33_NVIC_ISER0_SETENA_RESET _u(0x00000000) 2433 #define M33_NVIC_ISER0_SETENA_BITS _u(0xffffffff) 2434 #define M33_NVIC_ISER0_SETENA_MSB _u(31) 2435 #define M33_NVIC_ISER0_SETENA_LSB _u(0) 2436 #define M33_NVIC_ISER0_SETENA_ACCESS "RW" 2437 // ============================================================================= 2438 // Register : M33_NVIC_ISER1 2439 // Description : Enables or reads the enabled state of each group of 32 2440 // interrupts 2441 #define M33_NVIC_ISER1_OFFSET _u(0x0000e104) 2442 #define M33_NVIC_ISER1_BITS _u(0xffffffff) 2443 #define M33_NVIC_ISER1_RESET _u(0x00000000) 2444 // ----------------------------------------------------------------------------- 2445 // Field : M33_NVIC_ISER1_SETENA 2446 // Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n 2447 // + m is enabled 2448 #define M33_NVIC_ISER1_SETENA_RESET _u(0x00000000) 2449 #define M33_NVIC_ISER1_SETENA_BITS _u(0xffffffff) 2450 #define M33_NVIC_ISER1_SETENA_MSB _u(31) 2451 #define M33_NVIC_ISER1_SETENA_LSB _u(0) 2452 #define M33_NVIC_ISER1_SETENA_ACCESS "RW" 2453 // ============================================================================= 2454 // Register : M33_NVIC_ICER0 2455 // Description : Clears or reads the enabled state of each group of 32 2456 // interrupts 2457 #define M33_NVIC_ICER0_OFFSET _u(0x0000e180) 2458 #define M33_NVIC_ICER0_BITS _u(0xffffffff) 2459 #define M33_NVIC_ICER0_RESET _u(0x00000000) 2460 // ----------------------------------------------------------------------------- 2461 // Field : M33_NVIC_ICER0_CLRENA 2462 // Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n 2463 // + m is enabled 2464 #define M33_NVIC_ICER0_CLRENA_RESET _u(0x00000000) 2465 #define M33_NVIC_ICER0_CLRENA_BITS _u(0xffffffff) 2466 #define M33_NVIC_ICER0_CLRENA_MSB _u(31) 2467 #define M33_NVIC_ICER0_CLRENA_LSB _u(0) 2468 #define M33_NVIC_ICER0_CLRENA_ACCESS "RW" 2469 // ============================================================================= 2470 // Register : M33_NVIC_ICER1 2471 // Description : Clears or reads the enabled state of each group of 32 2472 // interrupts 2473 #define M33_NVIC_ICER1_OFFSET _u(0x0000e184) 2474 #define M33_NVIC_ICER1_BITS _u(0xffffffff) 2475 #define M33_NVIC_ICER1_RESET _u(0x00000000) 2476 // ----------------------------------------------------------------------------- 2477 // Field : M33_NVIC_ICER1_CLRENA 2478 // Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n 2479 // + m is enabled 2480 #define M33_NVIC_ICER1_CLRENA_RESET _u(0x00000000) 2481 #define M33_NVIC_ICER1_CLRENA_BITS _u(0xffffffff) 2482 #define M33_NVIC_ICER1_CLRENA_MSB _u(31) 2483 #define M33_NVIC_ICER1_CLRENA_LSB _u(0) 2484 #define M33_NVIC_ICER1_CLRENA_ACCESS "RW" 2485 // ============================================================================= 2486 // Register : M33_NVIC_ISPR0 2487 // Description : Enables or reads the pending state of each group of 32 2488 // interrupts 2489 #define M33_NVIC_ISPR0_OFFSET _u(0x0000e200) 2490 #define M33_NVIC_ISPR0_BITS _u(0xffffffff) 2491 #define M33_NVIC_ISPR0_RESET _u(0x00000000) 2492 // ----------------------------------------------------------------------------- 2493 // Field : M33_NVIC_ISPR0_SETPEND 2494 // Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n 2495 // + m is pending 2496 #define M33_NVIC_ISPR0_SETPEND_RESET _u(0x00000000) 2497 #define M33_NVIC_ISPR0_SETPEND_BITS _u(0xffffffff) 2498 #define M33_NVIC_ISPR0_SETPEND_MSB _u(31) 2499 #define M33_NVIC_ISPR0_SETPEND_LSB _u(0) 2500 #define M33_NVIC_ISPR0_SETPEND_ACCESS "RW" 2501 // ============================================================================= 2502 // Register : M33_NVIC_ISPR1 2503 // Description : Enables or reads the pending state of each group of 32 2504 // interrupts 2505 #define M33_NVIC_ISPR1_OFFSET _u(0x0000e204) 2506 #define M33_NVIC_ISPR1_BITS _u(0xffffffff) 2507 #define M33_NVIC_ISPR1_RESET _u(0x00000000) 2508 // ----------------------------------------------------------------------------- 2509 // Field : M33_NVIC_ISPR1_SETPEND 2510 // Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n 2511 // + m is pending 2512 #define M33_NVIC_ISPR1_SETPEND_RESET _u(0x00000000) 2513 #define M33_NVIC_ISPR1_SETPEND_BITS _u(0xffffffff) 2514 #define M33_NVIC_ISPR1_SETPEND_MSB _u(31) 2515 #define M33_NVIC_ISPR1_SETPEND_LSB _u(0) 2516 #define M33_NVIC_ISPR1_SETPEND_ACCESS "RW" 2517 // ============================================================================= 2518 // Register : M33_NVIC_ICPR0 2519 // Description : Clears or reads the pending state of each group of 32 2520 // interrupts 2521 #define M33_NVIC_ICPR0_OFFSET _u(0x0000e280) 2522 #define M33_NVIC_ICPR0_BITS _u(0xffffffff) 2523 #define M33_NVIC_ICPR0_RESET _u(0x00000000) 2524 // ----------------------------------------------------------------------------- 2525 // Field : M33_NVIC_ICPR0_CLRPEND 2526 // Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n 2527 // + m is pending 2528 #define M33_NVIC_ICPR0_CLRPEND_RESET _u(0x00000000) 2529 #define M33_NVIC_ICPR0_CLRPEND_BITS _u(0xffffffff) 2530 #define M33_NVIC_ICPR0_CLRPEND_MSB _u(31) 2531 #define M33_NVIC_ICPR0_CLRPEND_LSB _u(0) 2532 #define M33_NVIC_ICPR0_CLRPEND_ACCESS "RW" 2533 // ============================================================================= 2534 // Register : M33_NVIC_ICPR1 2535 // Description : Clears or reads the pending state of each group of 32 2536 // interrupts 2537 #define M33_NVIC_ICPR1_OFFSET _u(0x0000e284) 2538 #define M33_NVIC_ICPR1_BITS _u(0xffffffff) 2539 #define M33_NVIC_ICPR1_RESET _u(0x00000000) 2540 // ----------------------------------------------------------------------------- 2541 // Field : M33_NVIC_ICPR1_CLRPEND 2542 // Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n 2543 // + m is pending 2544 #define M33_NVIC_ICPR1_CLRPEND_RESET _u(0x00000000) 2545 #define M33_NVIC_ICPR1_CLRPEND_BITS _u(0xffffffff) 2546 #define M33_NVIC_ICPR1_CLRPEND_MSB _u(31) 2547 #define M33_NVIC_ICPR1_CLRPEND_LSB _u(0) 2548 #define M33_NVIC_ICPR1_CLRPEND_ACCESS "RW" 2549 // ============================================================================= 2550 // Register : M33_NVIC_IABR0 2551 // Description : For each group of 32 interrupts, shows the active state of each 2552 // interrupt 2553 #define M33_NVIC_IABR0_OFFSET _u(0x0000e300) 2554 #define M33_NVIC_IABR0_BITS _u(0xffffffff) 2555 #define M33_NVIC_IABR0_RESET _u(0x00000000) 2556 // ----------------------------------------------------------------------------- 2557 // Field : M33_NVIC_IABR0_ACTIVE 2558 // Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for 2559 // interrupt 32*n+m 2560 #define M33_NVIC_IABR0_ACTIVE_RESET _u(0x00000000) 2561 #define M33_NVIC_IABR0_ACTIVE_BITS _u(0xffffffff) 2562 #define M33_NVIC_IABR0_ACTIVE_MSB _u(31) 2563 #define M33_NVIC_IABR0_ACTIVE_LSB _u(0) 2564 #define M33_NVIC_IABR0_ACTIVE_ACCESS "RW" 2565 // ============================================================================= 2566 // Register : M33_NVIC_IABR1 2567 // Description : For each group of 32 interrupts, shows the active state of each 2568 // interrupt 2569 #define M33_NVIC_IABR1_OFFSET _u(0x0000e304) 2570 #define M33_NVIC_IABR1_BITS _u(0xffffffff) 2571 #define M33_NVIC_IABR1_RESET _u(0x00000000) 2572 // ----------------------------------------------------------------------------- 2573 // Field : M33_NVIC_IABR1_ACTIVE 2574 // Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for 2575 // interrupt 32*n+m 2576 #define M33_NVIC_IABR1_ACTIVE_RESET _u(0x00000000) 2577 #define M33_NVIC_IABR1_ACTIVE_BITS _u(0xffffffff) 2578 #define M33_NVIC_IABR1_ACTIVE_MSB _u(31) 2579 #define M33_NVIC_IABR1_ACTIVE_LSB _u(0) 2580 #define M33_NVIC_IABR1_ACTIVE_ACCESS "RW" 2581 // ============================================================================= 2582 // Register : M33_NVIC_ITNS0 2583 // Description : For each group of 32 interrupts, determines whether each 2584 // interrupt targets Non-secure or Secure state 2585 #define M33_NVIC_ITNS0_OFFSET _u(0x0000e380) 2586 #define M33_NVIC_ITNS0_BITS _u(0xffffffff) 2587 #define M33_NVIC_ITNS0_RESET _u(0x00000000) 2588 // ----------------------------------------------------------------------------- 2589 // Field : M33_NVIC_ITNS0_ITNS 2590 // Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state 2591 // for interrupt 32*n+m 2592 #define M33_NVIC_ITNS0_ITNS_RESET _u(0x00000000) 2593 #define M33_NVIC_ITNS0_ITNS_BITS _u(0xffffffff) 2594 #define M33_NVIC_ITNS0_ITNS_MSB _u(31) 2595 #define M33_NVIC_ITNS0_ITNS_LSB _u(0) 2596 #define M33_NVIC_ITNS0_ITNS_ACCESS "RW" 2597 // ============================================================================= 2598 // Register : M33_NVIC_ITNS1 2599 // Description : For each group of 32 interrupts, determines whether each 2600 // interrupt targets Non-secure or Secure state 2601 #define M33_NVIC_ITNS1_OFFSET _u(0x0000e384) 2602 #define M33_NVIC_ITNS1_BITS _u(0xffffffff) 2603 #define M33_NVIC_ITNS1_RESET _u(0x00000000) 2604 // ----------------------------------------------------------------------------- 2605 // Field : M33_NVIC_ITNS1_ITNS 2606 // Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state 2607 // for interrupt 32*n+m 2608 #define M33_NVIC_ITNS1_ITNS_RESET _u(0x00000000) 2609 #define M33_NVIC_ITNS1_ITNS_BITS _u(0xffffffff) 2610 #define M33_NVIC_ITNS1_ITNS_MSB _u(31) 2611 #define M33_NVIC_ITNS1_ITNS_LSB _u(0) 2612 #define M33_NVIC_ITNS1_ITNS_ACCESS "RW" 2613 // ============================================================================= 2614 // Register : M33_NVIC_IPR0 2615 // Description : Sets or reads interrupt priorities 2616 #define M33_NVIC_IPR0_OFFSET _u(0x0000e400) 2617 #define M33_NVIC_IPR0_BITS _u(0xf0f0f0f0) 2618 #define M33_NVIC_IPR0_RESET _u(0x00000000) 2619 // ----------------------------------------------------------------------------- 2620 // Field : M33_NVIC_IPR0_PRI_N3 2621 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2622 // or RES0 if the PE does not implement this interrupt 2623 #define M33_NVIC_IPR0_PRI_N3_RESET _u(0x0) 2624 #define M33_NVIC_IPR0_PRI_N3_BITS _u(0xf0000000) 2625 #define M33_NVIC_IPR0_PRI_N3_MSB _u(31) 2626 #define M33_NVIC_IPR0_PRI_N3_LSB _u(28) 2627 #define M33_NVIC_IPR0_PRI_N3_ACCESS "RW" 2628 // ----------------------------------------------------------------------------- 2629 // Field : M33_NVIC_IPR0_PRI_N2 2630 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2631 // or RES0 if the PE does not implement this interrupt 2632 #define M33_NVIC_IPR0_PRI_N2_RESET _u(0x0) 2633 #define M33_NVIC_IPR0_PRI_N2_BITS _u(0x00f00000) 2634 #define M33_NVIC_IPR0_PRI_N2_MSB _u(23) 2635 #define M33_NVIC_IPR0_PRI_N2_LSB _u(20) 2636 #define M33_NVIC_IPR0_PRI_N2_ACCESS "RW" 2637 // ----------------------------------------------------------------------------- 2638 // Field : M33_NVIC_IPR0_PRI_N1 2639 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2640 // or RES0 if the PE does not implement this interrupt 2641 #define M33_NVIC_IPR0_PRI_N1_RESET _u(0x0) 2642 #define M33_NVIC_IPR0_PRI_N1_BITS _u(0x0000f000) 2643 #define M33_NVIC_IPR0_PRI_N1_MSB _u(15) 2644 #define M33_NVIC_IPR0_PRI_N1_LSB _u(12) 2645 #define M33_NVIC_IPR0_PRI_N1_ACCESS "RW" 2646 // ----------------------------------------------------------------------------- 2647 // Field : M33_NVIC_IPR0_PRI_N0 2648 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2649 // or RES0 if the PE does not implement this interrupt 2650 #define M33_NVIC_IPR0_PRI_N0_RESET _u(0x0) 2651 #define M33_NVIC_IPR0_PRI_N0_BITS _u(0x000000f0) 2652 #define M33_NVIC_IPR0_PRI_N0_MSB _u(7) 2653 #define M33_NVIC_IPR0_PRI_N0_LSB _u(4) 2654 #define M33_NVIC_IPR0_PRI_N0_ACCESS "RW" 2655 // ============================================================================= 2656 // Register : M33_NVIC_IPR1 2657 // Description : Sets or reads interrupt priorities 2658 #define M33_NVIC_IPR1_OFFSET _u(0x0000e404) 2659 #define M33_NVIC_IPR1_BITS _u(0xf0f0f0f0) 2660 #define M33_NVIC_IPR1_RESET _u(0x00000000) 2661 // ----------------------------------------------------------------------------- 2662 // Field : M33_NVIC_IPR1_PRI_N3 2663 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2664 // or RES0 if the PE does not implement this interrupt 2665 #define M33_NVIC_IPR1_PRI_N3_RESET _u(0x0) 2666 #define M33_NVIC_IPR1_PRI_N3_BITS _u(0xf0000000) 2667 #define M33_NVIC_IPR1_PRI_N3_MSB _u(31) 2668 #define M33_NVIC_IPR1_PRI_N3_LSB _u(28) 2669 #define M33_NVIC_IPR1_PRI_N3_ACCESS "RW" 2670 // ----------------------------------------------------------------------------- 2671 // Field : M33_NVIC_IPR1_PRI_N2 2672 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2673 // or RES0 if the PE does not implement this interrupt 2674 #define M33_NVIC_IPR1_PRI_N2_RESET _u(0x0) 2675 #define M33_NVIC_IPR1_PRI_N2_BITS _u(0x00f00000) 2676 #define M33_NVIC_IPR1_PRI_N2_MSB _u(23) 2677 #define M33_NVIC_IPR1_PRI_N2_LSB _u(20) 2678 #define M33_NVIC_IPR1_PRI_N2_ACCESS "RW" 2679 // ----------------------------------------------------------------------------- 2680 // Field : M33_NVIC_IPR1_PRI_N1 2681 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2682 // or RES0 if the PE does not implement this interrupt 2683 #define M33_NVIC_IPR1_PRI_N1_RESET _u(0x0) 2684 #define M33_NVIC_IPR1_PRI_N1_BITS _u(0x0000f000) 2685 #define M33_NVIC_IPR1_PRI_N1_MSB _u(15) 2686 #define M33_NVIC_IPR1_PRI_N1_LSB _u(12) 2687 #define M33_NVIC_IPR1_PRI_N1_ACCESS "RW" 2688 // ----------------------------------------------------------------------------- 2689 // Field : M33_NVIC_IPR1_PRI_N0 2690 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2691 // or RES0 if the PE does not implement this interrupt 2692 #define M33_NVIC_IPR1_PRI_N0_RESET _u(0x0) 2693 #define M33_NVIC_IPR1_PRI_N0_BITS _u(0x000000f0) 2694 #define M33_NVIC_IPR1_PRI_N0_MSB _u(7) 2695 #define M33_NVIC_IPR1_PRI_N0_LSB _u(4) 2696 #define M33_NVIC_IPR1_PRI_N0_ACCESS "RW" 2697 // ============================================================================= 2698 // Register : M33_NVIC_IPR2 2699 // Description : Sets or reads interrupt priorities 2700 #define M33_NVIC_IPR2_OFFSET _u(0x0000e408) 2701 #define M33_NVIC_IPR2_BITS _u(0xf0f0f0f0) 2702 #define M33_NVIC_IPR2_RESET _u(0x00000000) 2703 // ----------------------------------------------------------------------------- 2704 // Field : M33_NVIC_IPR2_PRI_N3 2705 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2706 // or RES0 if the PE does not implement this interrupt 2707 #define M33_NVIC_IPR2_PRI_N3_RESET _u(0x0) 2708 #define M33_NVIC_IPR2_PRI_N3_BITS _u(0xf0000000) 2709 #define M33_NVIC_IPR2_PRI_N3_MSB _u(31) 2710 #define M33_NVIC_IPR2_PRI_N3_LSB _u(28) 2711 #define M33_NVIC_IPR2_PRI_N3_ACCESS "RW" 2712 // ----------------------------------------------------------------------------- 2713 // Field : M33_NVIC_IPR2_PRI_N2 2714 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2715 // or RES0 if the PE does not implement this interrupt 2716 #define M33_NVIC_IPR2_PRI_N2_RESET _u(0x0) 2717 #define M33_NVIC_IPR2_PRI_N2_BITS _u(0x00f00000) 2718 #define M33_NVIC_IPR2_PRI_N2_MSB _u(23) 2719 #define M33_NVIC_IPR2_PRI_N2_LSB _u(20) 2720 #define M33_NVIC_IPR2_PRI_N2_ACCESS "RW" 2721 // ----------------------------------------------------------------------------- 2722 // Field : M33_NVIC_IPR2_PRI_N1 2723 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2724 // or RES0 if the PE does not implement this interrupt 2725 #define M33_NVIC_IPR2_PRI_N1_RESET _u(0x0) 2726 #define M33_NVIC_IPR2_PRI_N1_BITS _u(0x0000f000) 2727 #define M33_NVIC_IPR2_PRI_N1_MSB _u(15) 2728 #define M33_NVIC_IPR2_PRI_N1_LSB _u(12) 2729 #define M33_NVIC_IPR2_PRI_N1_ACCESS "RW" 2730 // ----------------------------------------------------------------------------- 2731 // Field : M33_NVIC_IPR2_PRI_N0 2732 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2733 // or RES0 if the PE does not implement this interrupt 2734 #define M33_NVIC_IPR2_PRI_N0_RESET _u(0x0) 2735 #define M33_NVIC_IPR2_PRI_N0_BITS _u(0x000000f0) 2736 #define M33_NVIC_IPR2_PRI_N0_MSB _u(7) 2737 #define M33_NVIC_IPR2_PRI_N0_LSB _u(4) 2738 #define M33_NVIC_IPR2_PRI_N0_ACCESS "RW" 2739 // ============================================================================= 2740 // Register : M33_NVIC_IPR3 2741 // Description : Sets or reads interrupt priorities 2742 #define M33_NVIC_IPR3_OFFSET _u(0x0000e40c) 2743 #define M33_NVIC_IPR3_BITS _u(0xf0f0f0f0) 2744 #define M33_NVIC_IPR3_RESET _u(0x00000000) 2745 // ----------------------------------------------------------------------------- 2746 // Field : M33_NVIC_IPR3_PRI_N3 2747 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2748 // or RES0 if the PE does not implement this interrupt 2749 #define M33_NVIC_IPR3_PRI_N3_RESET _u(0x0) 2750 #define M33_NVIC_IPR3_PRI_N3_BITS _u(0xf0000000) 2751 #define M33_NVIC_IPR3_PRI_N3_MSB _u(31) 2752 #define M33_NVIC_IPR3_PRI_N3_LSB _u(28) 2753 #define M33_NVIC_IPR3_PRI_N3_ACCESS "RW" 2754 // ----------------------------------------------------------------------------- 2755 // Field : M33_NVIC_IPR3_PRI_N2 2756 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2757 // or RES0 if the PE does not implement this interrupt 2758 #define M33_NVIC_IPR3_PRI_N2_RESET _u(0x0) 2759 #define M33_NVIC_IPR3_PRI_N2_BITS _u(0x00f00000) 2760 #define M33_NVIC_IPR3_PRI_N2_MSB _u(23) 2761 #define M33_NVIC_IPR3_PRI_N2_LSB _u(20) 2762 #define M33_NVIC_IPR3_PRI_N2_ACCESS "RW" 2763 // ----------------------------------------------------------------------------- 2764 // Field : M33_NVIC_IPR3_PRI_N1 2765 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2766 // or RES0 if the PE does not implement this interrupt 2767 #define M33_NVIC_IPR3_PRI_N1_RESET _u(0x0) 2768 #define M33_NVIC_IPR3_PRI_N1_BITS _u(0x0000f000) 2769 #define M33_NVIC_IPR3_PRI_N1_MSB _u(15) 2770 #define M33_NVIC_IPR3_PRI_N1_LSB _u(12) 2771 #define M33_NVIC_IPR3_PRI_N1_ACCESS "RW" 2772 // ----------------------------------------------------------------------------- 2773 // Field : M33_NVIC_IPR3_PRI_N0 2774 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2775 // or RES0 if the PE does not implement this interrupt 2776 #define M33_NVIC_IPR3_PRI_N0_RESET _u(0x0) 2777 #define M33_NVIC_IPR3_PRI_N0_BITS _u(0x000000f0) 2778 #define M33_NVIC_IPR3_PRI_N0_MSB _u(7) 2779 #define M33_NVIC_IPR3_PRI_N0_LSB _u(4) 2780 #define M33_NVIC_IPR3_PRI_N0_ACCESS "RW" 2781 // ============================================================================= 2782 // Register : M33_NVIC_IPR4 2783 // Description : Sets or reads interrupt priorities 2784 #define M33_NVIC_IPR4_OFFSET _u(0x0000e410) 2785 #define M33_NVIC_IPR4_BITS _u(0xf0f0f0f0) 2786 #define M33_NVIC_IPR4_RESET _u(0x00000000) 2787 // ----------------------------------------------------------------------------- 2788 // Field : M33_NVIC_IPR4_PRI_N3 2789 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2790 // or RES0 if the PE does not implement this interrupt 2791 #define M33_NVIC_IPR4_PRI_N3_RESET _u(0x0) 2792 #define M33_NVIC_IPR4_PRI_N3_BITS _u(0xf0000000) 2793 #define M33_NVIC_IPR4_PRI_N3_MSB _u(31) 2794 #define M33_NVIC_IPR4_PRI_N3_LSB _u(28) 2795 #define M33_NVIC_IPR4_PRI_N3_ACCESS "RW" 2796 // ----------------------------------------------------------------------------- 2797 // Field : M33_NVIC_IPR4_PRI_N2 2798 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2799 // or RES0 if the PE does not implement this interrupt 2800 #define M33_NVIC_IPR4_PRI_N2_RESET _u(0x0) 2801 #define M33_NVIC_IPR4_PRI_N2_BITS _u(0x00f00000) 2802 #define M33_NVIC_IPR4_PRI_N2_MSB _u(23) 2803 #define M33_NVIC_IPR4_PRI_N2_LSB _u(20) 2804 #define M33_NVIC_IPR4_PRI_N2_ACCESS "RW" 2805 // ----------------------------------------------------------------------------- 2806 // Field : M33_NVIC_IPR4_PRI_N1 2807 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2808 // or RES0 if the PE does not implement this interrupt 2809 #define M33_NVIC_IPR4_PRI_N1_RESET _u(0x0) 2810 #define M33_NVIC_IPR4_PRI_N1_BITS _u(0x0000f000) 2811 #define M33_NVIC_IPR4_PRI_N1_MSB _u(15) 2812 #define M33_NVIC_IPR4_PRI_N1_LSB _u(12) 2813 #define M33_NVIC_IPR4_PRI_N1_ACCESS "RW" 2814 // ----------------------------------------------------------------------------- 2815 // Field : M33_NVIC_IPR4_PRI_N0 2816 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2817 // or RES0 if the PE does not implement this interrupt 2818 #define M33_NVIC_IPR4_PRI_N0_RESET _u(0x0) 2819 #define M33_NVIC_IPR4_PRI_N0_BITS _u(0x000000f0) 2820 #define M33_NVIC_IPR4_PRI_N0_MSB _u(7) 2821 #define M33_NVIC_IPR4_PRI_N0_LSB _u(4) 2822 #define M33_NVIC_IPR4_PRI_N0_ACCESS "RW" 2823 // ============================================================================= 2824 // Register : M33_NVIC_IPR5 2825 // Description : Sets or reads interrupt priorities 2826 #define M33_NVIC_IPR5_OFFSET _u(0x0000e414) 2827 #define M33_NVIC_IPR5_BITS _u(0xf0f0f0f0) 2828 #define M33_NVIC_IPR5_RESET _u(0x00000000) 2829 // ----------------------------------------------------------------------------- 2830 // Field : M33_NVIC_IPR5_PRI_N3 2831 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2832 // or RES0 if the PE does not implement this interrupt 2833 #define M33_NVIC_IPR5_PRI_N3_RESET _u(0x0) 2834 #define M33_NVIC_IPR5_PRI_N3_BITS _u(0xf0000000) 2835 #define M33_NVIC_IPR5_PRI_N3_MSB _u(31) 2836 #define M33_NVIC_IPR5_PRI_N3_LSB _u(28) 2837 #define M33_NVIC_IPR5_PRI_N3_ACCESS "RW" 2838 // ----------------------------------------------------------------------------- 2839 // Field : M33_NVIC_IPR5_PRI_N2 2840 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2841 // or RES0 if the PE does not implement this interrupt 2842 #define M33_NVIC_IPR5_PRI_N2_RESET _u(0x0) 2843 #define M33_NVIC_IPR5_PRI_N2_BITS _u(0x00f00000) 2844 #define M33_NVIC_IPR5_PRI_N2_MSB _u(23) 2845 #define M33_NVIC_IPR5_PRI_N2_LSB _u(20) 2846 #define M33_NVIC_IPR5_PRI_N2_ACCESS "RW" 2847 // ----------------------------------------------------------------------------- 2848 // Field : M33_NVIC_IPR5_PRI_N1 2849 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2850 // or RES0 if the PE does not implement this interrupt 2851 #define M33_NVIC_IPR5_PRI_N1_RESET _u(0x0) 2852 #define M33_NVIC_IPR5_PRI_N1_BITS _u(0x0000f000) 2853 #define M33_NVIC_IPR5_PRI_N1_MSB _u(15) 2854 #define M33_NVIC_IPR5_PRI_N1_LSB _u(12) 2855 #define M33_NVIC_IPR5_PRI_N1_ACCESS "RW" 2856 // ----------------------------------------------------------------------------- 2857 // Field : M33_NVIC_IPR5_PRI_N0 2858 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2859 // or RES0 if the PE does not implement this interrupt 2860 #define M33_NVIC_IPR5_PRI_N0_RESET _u(0x0) 2861 #define M33_NVIC_IPR5_PRI_N0_BITS _u(0x000000f0) 2862 #define M33_NVIC_IPR5_PRI_N0_MSB _u(7) 2863 #define M33_NVIC_IPR5_PRI_N0_LSB _u(4) 2864 #define M33_NVIC_IPR5_PRI_N0_ACCESS "RW" 2865 // ============================================================================= 2866 // Register : M33_NVIC_IPR6 2867 // Description : Sets or reads interrupt priorities 2868 #define M33_NVIC_IPR6_OFFSET _u(0x0000e418) 2869 #define M33_NVIC_IPR6_BITS _u(0xf0f0f0f0) 2870 #define M33_NVIC_IPR6_RESET _u(0x00000000) 2871 // ----------------------------------------------------------------------------- 2872 // Field : M33_NVIC_IPR6_PRI_N3 2873 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2874 // or RES0 if the PE does not implement this interrupt 2875 #define M33_NVIC_IPR6_PRI_N3_RESET _u(0x0) 2876 #define M33_NVIC_IPR6_PRI_N3_BITS _u(0xf0000000) 2877 #define M33_NVIC_IPR6_PRI_N3_MSB _u(31) 2878 #define M33_NVIC_IPR6_PRI_N3_LSB _u(28) 2879 #define M33_NVIC_IPR6_PRI_N3_ACCESS "RW" 2880 // ----------------------------------------------------------------------------- 2881 // Field : M33_NVIC_IPR6_PRI_N2 2882 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2883 // or RES0 if the PE does not implement this interrupt 2884 #define M33_NVIC_IPR6_PRI_N2_RESET _u(0x0) 2885 #define M33_NVIC_IPR6_PRI_N2_BITS _u(0x00f00000) 2886 #define M33_NVIC_IPR6_PRI_N2_MSB _u(23) 2887 #define M33_NVIC_IPR6_PRI_N2_LSB _u(20) 2888 #define M33_NVIC_IPR6_PRI_N2_ACCESS "RW" 2889 // ----------------------------------------------------------------------------- 2890 // Field : M33_NVIC_IPR6_PRI_N1 2891 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2892 // or RES0 if the PE does not implement this interrupt 2893 #define M33_NVIC_IPR6_PRI_N1_RESET _u(0x0) 2894 #define M33_NVIC_IPR6_PRI_N1_BITS _u(0x0000f000) 2895 #define M33_NVIC_IPR6_PRI_N1_MSB _u(15) 2896 #define M33_NVIC_IPR6_PRI_N1_LSB _u(12) 2897 #define M33_NVIC_IPR6_PRI_N1_ACCESS "RW" 2898 // ----------------------------------------------------------------------------- 2899 // Field : M33_NVIC_IPR6_PRI_N0 2900 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2901 // or RES0 if the PE does not implement this interrupt 2902 #define M33_NVIC_IPR6_PRI_N0_RESET _u(0x0) 2903 #define M33_NVIC_IPR6_PRI_N0_BITS _u(0x000000f0) 2904 #define M33_NVIC_IPR6_PRI_N0_MSB _u(7) 2905 #define M33_NVIC_IPR6_PRI_N0_LSB _u(4) 2906 #define M33_NVIC_IPR6_PRI_N0_ACCESS "RW" 2907 // ============================================================================= 2908 // Register : M33_NVIC_IPR7 2909 // Description : Sets or reads interrupt priorities 2910 #define M33_NVIC_IPR7_OFFSET _u(0x0000e41c) 2911 #define M33_NVIC_IPR7_BITS _u(0xf0f0f0f0) 2912 #define M33_NVIC_IPR7_RESET _u(0x00000000) 2913 // ----------------------------------------------------------------------------- 2914 // Field : M33_NVIC_IPR7_PRI_N3 2915 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2916 // or RES0 if the PE does not implement this interrupt 2917 #define M33_NVIC_IPR7_PRI_N3_RESET _u(0x0) 2918 #define M33_NVIC_IPR7_PRI_N3_BITS _u(0xf0000000) 2919 #define M33_NVIC_IPR7_PRI_N3_MSB _u(31) 2920 #define M33_NVIC_IPR7_PRI_N3_LSB _u(28) 2921 #define M33_NVIC_IPR7_PRI_N3_ACCESS "RW" 2922 // ----------------------------------------------------------------------------- 2923 // Field : M33_NVIC_IPR7_PRI_N2 2924 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2925 // or RES0 if the PE does not implement this interrupt 2926 #define M33_NVIC_IPR7_PRI_N2_RESET _u(0x0) 2927 #define M33_NVIC_IPR7_PRI_N2_BITS _u(0x00f00000) 2928 #define M33_NVIC_IPR7_PRI_N2_MSB _u(23) 2929 #define M33_NVIC_IPR7_PRI_N2_LSB _u(20) 2930 #define M33_NVIC_IPR7_PRI_N2_ACCESS "RW" 2931 // ----------------------------------------------------------------------------- 2932 // Field : M33_NVIC_IPR7_PRI_N1 2933 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2934 // or RES0 if the PE does not implement this interrupt 2935 #define M33_NVIC_IPR7_PRI_N1_RESET _u(0x0) 2936 #define M33_NVIC_IPR7_PRI_N1_BITS _u(0x0000f000) 2937 #define M33_NVIC_IPR7_PRI_N1_MSB _u(15) 2938 #define M33_NVIC_IPR7_PRI_N1_LSB _u(12) 2939 #define M33_NVIC_IPR7_PRI_N1_ACCESS "RW" 2940 // ----------------------------------------------------------------------------- 2941 // Field : M33_NVIC_IPR7_PRI_N0 2942 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2943 // or RES0 if the PE does not implement this interrupt 2944 #define M33_NVIC_IPR7_PRI_N0_RESET _u(0x0) 2945 #define M33_NVIC_IPR7_PRI_N0_BITS _u(0x000000f0) 2946 #define M33_NVIC_IPR7_PRI_N0_MSB _u(7) 2947 #define M33_NVIC_IPR7_PRI_N0_LSB _u(4) 2948 #define M33_NVIC_IPR7_PRI_N0_ACCESS "RW" 2949 // ============================================================================= 2950 // Register : M33_NVIC_IPR8 2951 // Description : Sets or reads interrupt priorities 2952 #define M33_NVIC_IPR8_OFFSET _u(0x0000e420) 2953 #define M33_NVIC_IPR8_BITS _u(0xf0f0f0f0) 2954 #define M33_NVIC_IPR8_RESET _u(0x00000000) 2955 // ----------------------------------------------------------------------------- 2956 // Field : M33_NVIC_IPR8_PRI_N3 2957 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 2958 // or RES0 if the PE does not implement this interrupt 2959 #define M33_NVIC_IPR8_PRI_N3_RESET _u(0x0) 2960 #define M33_NVIC_IPR8_PRI_N3_BITS _u(0xf0000000) 2961 #define M33_NVIC_IPR8_PRI_N3_MSB _u(31) 2962 #define M33_NVIC_IPR8_PRI_N3_LSB _u(28) 2963 #define M33_NVIC_IPR8_PRI_N3_ACCESS "RW" 2964 // ----------------------------------------------------------------------------- 2965 // Field : M33_NVIC_IPR8_PRI_N2 2966 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 2967 // or RES0 if the PE does not implement this interrupt 2968 #define M33_NVIC_IPR8_PRI_N2_RESET _u(0x0) 2969 #define M33_NVIC_IPR8_PRI_N2_BITS _u(0x00f00000) 2970 #define M33_NVIC_IPR8_PRI_N2_MSB _u(23) 2971 #define M33_NVIC_IPR8_PRI_N2_LSB _u(20) 2972 #define M33_NVIC_IPR8_PRI_N2_ACCESS "RW" 2973 // ----------------------------------------------------------------------------- 2974 // Field : M33_NVIC_IPR8_PRI_N1 2975 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 2976 // or RES0 if the PE does not implement this interrupt 2977 #define M33_NVIC_IPR8_PRI_N1_RESET _u(0x0) 2978 #define M33_NVIC_IPR8_PRI_N1_BITS _u(0x0000f000) 2979 #define M33_NVIC_IPR8_PRI_N1_MSB _u(15) 2980 #define M33_NVIC_IPR8_PRI_N1_LSB _u(12) 2981 #define M33_NVIC_IPR8_PRI_N1_ACCESS "RW" 2982 // ----------------------------------------------------------------------------- 2983 // Field : M33_NVIC_IPR8_PRI_N0 2984 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 2985 // or RES0 if the PE does not implement this interrupt 2986 #define M33_NVIC_IPR8_PRI_N0_RESET _u(0x0) 2987 #define M33_NVIC_IPR8_PRI_N0_BITS _u(0x000000f0) 2988 #define M33_NVIC_IPR8_PRI_N0_MSB _u(7) 2989 #define M33_NVIC_IPR8_PRI_N0_LSB _u(4) 2990 #define M33_NVIC_IPR8_PRI_N0_ACCESS "RW" 2991 // ============================================================================= 2992 // Register : M33_NVIC_IPR9 2993 // Description : Sets or reads interrupt priorities 2994 #define M33_NVIC_IPR9_OFFSET _u(0x0000e424) 2995 #define M33_NVIC_IPR9_BITS _u(0xf0f0f0f0) 2996 #define M33_NVIC_IPR9_RESET _u(0x00000000) 2997 // ----------------------------------------------------------------------------- 2998 // Field : M33_NVIC_IPR9_PRI_N3 2999 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3000 // or RES0 if the PE does not implement this interrupt 3001 #define M33_NVIC_IPR9_PRI_N3_RESET _u(0x0) 3002 #define M33_NVIC_IPR9_PRI_N3_BITS _u(0xf0000000) 3003 #define M33_NVIC_IPR9_PRI_N3_MSB _u(31) 3004 #define M33_NVIC_IPR9_PRI_N3_LSB _u(28) 3005 #define M33_NVIC_IPR9_PRI_N3_ACCESS "RW" 3006 // ----------------------------------------------------------------------------- 3007 // Field : M33_NVIC_IPR9_PRI_N2 3008 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3009 // or RES0 if the PE does not implement this interrupt 3010 #define M33_NVIC_IPR9_PRI_N2_RESET _u(0x0) 3011 #define M33_NVIC_IPR9_PRI_N2_BITS _u(0x00f00000) 3012 #define M33_NVIC_IPR9_PRI_N2_MSB _u(23) 3013 #define M33_NVIC_IPR9_PRI_N2_LSB _u(20) 3014 #define M33_NVIC_IPR9_PRI_N2_ACCESS "RW" 3015 // ----------------------------------------------------------------------------- 3016 // Field : M33_NVIC_IPR9_PRI_N1 3017 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3018 // or RES0 if the PE does not implement this interrupt 3019 #define M33_NVIC_IPR9_PRI_N1_RESET _u(0x0) 3020 #define M33_NVIC_IPR9_PRI_N1_BITS _u(0x0000f000) 3021 #define M33_NVIC_IPR9_PRI_N1_MSB _u(15) 3022 #define M33_NVIC_IPR9_PRI_N1_LSB _u(12) 3023 #define M33_NVIC_IPR9_PRI_N1_ACCESS "RW" 3024 // ----------------------------------------------------------------------------- 3025 // Field : M33_NVIC_IPR9_PRI_N0 3026 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3027 // or RES0 if the PE does not implement this interrupt 3028 #define M33_NVIC_IPR9_PRI_N0_RESET _u(0x0) 3029 #define M33_NVIC_IPR9_PRI_N0_BITS _u(0x000000f0) 3030 #define M33_NVIC_IPR9_PRI_N0_MSB _u(7) 3031 #define M33_NVIC_IPR9_PRI_N0_LSB _u(4) 3032 #define M33_NVIC_IPR9_PRI_N0_ACCESS "RW" 3033 // ============================================================================= 3034 // Register : M33_NVIC_IPR10 3035 // Description : Sets or reads interrupt priorities 3036 #define M33_NVIC_IPR10_OFFSET _u(0x0000e428) 3037 #define M33_NVIC_IPR10_BITS _u(0xf0f0f0f0) 3038 #define M33_NVIC_IPR10_RESET _u(0x00000000) 3039 // ----------------------------------------------------------------------------- 3040 // Field : M33_NVIC_IPR10_PRI_N3 3041 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3042 // or RES0 if the PE does not implement this interrupt 3043 #define M33_NVIC_IPR10_PRI_N3_RESET _u(0x0) 3044 #define M33_NVIC_IPR10_PRI_N3_BITS _u(0xf0000000) 3045 #define M33_NVIC_IPR10_PRI_N3_MSB _u(31) 3046 #define M33_NVIC_IPR10_PRI_N3_LSB _u(28) 3047 #define M33_NVIC_IPR10_PRI_N3_ACCESS "RW" 3048 // ----------------------------------------------------------------------------- 3049 // Field : M33_NVIC_IPR10_PRI_N2 3050 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3051 // or RES0 if the PE does not implement this interrupt 3052 #define M33_NVIC_IPR10_PRI_N2_RESET _u(0x0) 3053 #define M33_NVIC_IPR10_PRI_N2_BITS _u(0x00f00000) 3054 #define M33_NVIC_IPR10_PRI_N2_MSB _u(23) 3055 #define M33_NVIC_IPR10_PRI_N2_LSB _u(20) 3056 #define M33_NVIC_IPR10_PRI_N2_ACCESS "RW" 3057 // ----------------------------------------------------------------------------- 3058 // Field : M33_NVIC_IPR10_PRI_N1 3059 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3060 // or RES0 if the PE does not implement this interrupt 3061 #define M33_NVIC_IPR10_PRI_N1_RESET _u(0x0) 3062 #define M33_NVIC_IPR10_PRI_N1_BITS _u(0x0000f000) 3063 #define M33_NVIC_IPR10_PRI_N1_MSB _u(15) 3064 #define M33_NVIC_IPR10_PRI_N1_LSB _u(12) 3065 #define M33_NVIC_IPR10_PRI_N1_ACCESS "RW" 3066 // ----------------------------------------------------------------------------- 3067 // Field : M33_NVIC_IPR10_PRI_N0 3068 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3069 // or RES0 if the PE does not implement this interrupt 3070 #define M33_NVIC_IPR10_PRI_N0_RESET _u(0x0) 3071 #define M33_NVIC_IPR10_PRI_N0_BITS _u(0x000000f0) 3072 #define M33_NVIC_IPR10_PRI_N0_MSB _u(7) 3073 #define M33_NVIC_IPR10_PRI_N0_LSB _u(4) 3074 #define M33_NVIC_IPR10_PRI_N0_ACCESS "RW" 3075 // ============================================================================= 3076 // Register : M33_NVIC_IPR11 3077 // Description : Sets or reads interrupt priorities 3078 #define M33_NVIC_IPR11_OFFSET _u(0x0000e42c) 3079 #define M33_NVIC_IPR11_BITS _u(0xf0f0f0f0) 3080 #define M33_NVIC_IPR11_RESET _u(0x00000000) 3081 // ----------------------------------------------------------------------------- 3082 // Field : M33_NVIC_IPR11_PRI_N3 3083 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3084 // or RES0 if the PE does not implement this interrupt 3085 #define M33_NVIC_IPR11_PRI_N3_RESET _u(0x0) 3086 #define M33_NVIC_IPR11_PRI_N3_BITS _u(0xf0000000) 3087 #define M33_NVIC_IPR11_PRI_N3_MSB _u(31) 3088 #define M33_NVIC_IPR11_PRI_N3_LSB _u(28) 3089 #define M33_NVIC_IPR11_PRI_N3_ACCESS "RW" 3090 // ----------------------------------------------------------------------------- 3091 // Field : M33_NVIC_IPR11_PRI_N2 3092 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3093 // or RES0 if the PE does not implement this interrupt 3094 #define M33_NVIC_IPR11_PRI_N2_RESET _u(0x0) 3095 #define M33_NVIC_IPR11_PRI_N2_BITS _u(0x00f00000) 3096 #define M33_NVIC_IPR11_PRI_N2_MSB _u(23) 3097 #define M33_NVIC_IPR11_PRI_N2_LSB _u(20) 3098 #define M33_NVIC_IPR11_PRI_N2_ACCESS "RW" 3099 // ----------------------------------------------------------------------------- 3100 // Field : M33_NVIC_IPR11_PRI_N1 3101 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3102 // or RES0 if the PE does not implement this interrupt 3103 #define M33_NVIC_IPR11_PRI_N1_RESET _u(0x0) 3104 #define M33_NVIC_IPR11_PRI_N1_BITS _u(0x0000f000) 3105 #define M33_NVIC_IPR11_PRI_N1_MSB _u(15) 3106 #define M33_NVIC_IPR11_PRI_N1_LSB _u(12) 3107 #define M33_NVIC_IPR11_PRI_N1_ACCESS "RW" 3108 // ----------------------------------------------------------------------------- 3109 // Field : M33_NVIC_IPR11_PRI_N0 3110 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3111 // or RES0 if the PE does not implement this interrupt 3112 #define M33_NVIC_IPR11_PRI_N0_RESET _u(0x0) 3113 #define M33_NVIC_IPR11_PRI_N0_BITS _u(0x000000f0) 3114 #define M33_NVIC_IPR11_PRI_N0_MSB _u(7) 3115 #define M33_NVIC_IPR11_PRI_N0_LSB _u(4) 3116 #define M33_NVIC_IPR11_PRI_N0_ACCESS "RW" 3117 // ============================================================================= 3118 // Register : M33_NVIC_IPR12 3119 // Description : Sets or reads interrupt priorities 3120 #define M33_NVIC_IPR12_OFFSET _u(0x0000e430) 3121 #define M33_NVIC_IPR12_BITS _u(0xf0f0f0f0) 3122 #define M33_NVIC_IPR12_RESET _u(0x00000000) 3123 // ----------------------------------------------------------------------------- 3124 // Field : M33_NVIC_IPR12_PRI_N3 3125 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3126 // or RES0 if the PE does not implement this interrupt 3127 #define M33_NVIC_IPR12_PRI_N3_RESET _u(0x0) 3128 #define M33_NVIC_IPR12_PRI_N3_BITS _u(0xf0000000) 3129 #define M33_NVIC_IPR12_PRI_N3_MSB _u(31) 3130 #define M33_NVIC_IPR12_PRI_N3_LSB _u(28) 3131 #define M33_NVIC_IPR12_PRI_N3_ACCESS "RW" 3132 // ----------------------------------------------------------------------------- 3133 // Field : M33_NVIC_IPR12_PRI_N2 3134 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3135 // or RES0 if the PE does not implement this interrupt 3136 #define M33_NVIC_IPR12_PRI_N2_RESET _u(0x0) 3137 #define M33_NVIC_IPR12_PRI_N2_BITS _u(0x00f00000) 3138 #define M33_NVIC_IPR12_PRI_N2_MSB _u(23) 3139 #define M33_NVIC_IPR12_PRI_N2_LSB _u(20) 3140 #define M33_NVIC_IPR12_PRI_N2_ACCESS "RW" 3141 // ----------------------------------------------------------------------------- 3142 // Field : M33_NVIC_IPR12_PRI_N1 3143 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3144 // or RES0 if the PE does not implement this interrupt 3145 #define M33_NVIC_IPR12_PRI_N1_RESET _u(0x0) 3146 #define M33_NVIC_IPR12_PRI_N1_BITS _u(0x0000f000) 3147 #define M33_NVIC_IPR12_PRI_N1_MSB _u(15) 3148 #define M33_NVIC_IPR12_PRI_N1_LSB _u(12) 3149 #define M33_NVIC_IPR12_PRI_N1_ACCESS "RW" 3150 // ----------------------------------------------------------------------------- 3151 // Field : M33_NVIC_IPR12_PRI_N0 3152 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3153 // or RES0 if the PE does not implement this interrupt 3154 #define M33_NVIC_IPR12_PRI_N0_RESET _u(0x0) 3155 #define M33_NVIC_IPR12_PRI_N0_BITS _u(0x000000f0) 3156 #define M33_NVIC_IPR12_PRI_N0_MSB _u(7) 3157 #define M33_NVIC_IPR12_PRI_N0_LSB _u(4) 3158 #define M33_NVIC_IPR12_PRI_N0_ACCESS "RW" 3159 // ============================================================================= 3160 // Register : M33_NVIC_IPR13 3161 // Description : Sets or reads interrupt priorities 3162 #define M33_NVIC_IPR13_OFFSET _u(0x0000e434) 3163 #define M33_NVIC_IPR13_BITS _u(0xf0f0f0f0) 3164 #define M33_NVIC_IPR13_RESET _u(0x00000000) 3165 // ----------------------------------------------------------------------------- 3166 // Field : M33_NVIC_IPR13_PRI_N3 3167 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3168 // or RES0 if the PE does not implement this interrupt 3169 #define M33_NVIC_IPR13_PRI_N3_RESET _u(0x0) 3170 #define M33_NVIC_IPR13_PRI_N3_BITS _u(0xf0000000) 3171 #define M33_NVIC_IPR13_PRI_N3_MSB _u(31) 3172 #define M33_NVIC_IPR13_PRI_N3_LSB _u(28) 3173 #define M33_NVIC_IPR13_PRI_N3_ACCESS "RW" 3174 // ----------------------------------------------------------------------------- 3175 // Field : M33_NVIC_IPR13_PRI_N2 3176 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3177 // or RES0 if the PE does not implement this interrupt 3178 #define M33_NVIC_IPR13_PRI_N2_RESET _u(0x0) 3179 #define M33_NVIC_IPR13_PRI_N2_BITS _u(0x00f00000) 3180 #define M33_NVIC_IPR13_PRI_N2_MSB _u(23) 3181 #define M33_NVIC_IPR13_PRI_N2_LSB _u(20) 3182 #define M33_NVIC_IPR13_PRI_N2_ACCESS "RW" 3183 // ----------------------------------------------------------------------------- 3184 // Field : M33_NVIC_IPR13_PRI_N1 3185 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3186 // or RES0 if the PE does not implement this interrupt 3187 #define M33_NVIC_IPR13_PRI_N1_RESET _u(0x0) 3188 #define M33_NVIC_IPR13_PRI_N1_BITS _u(0x0000f000) 3189 #define M33_NVIC_IPR13_PRI_N1_MSB _u(15) 3190 #define M33_NVIC_IPR13_PRI_N1_LSB _u(12) 3191 #define M33_NVIC_IPR13_PRI_N1_ACCESS "RW" 3192 // ----------------------------------------------------------------------------- 3193 // Field : M33_NVIC_IPR13_PRI_N0 3194 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3195 // or RES0 if the PE does not implement this interrupt 3196 #define M33_NVIC_IPR13_PRI_N0_RESET _u(0x0) 3197 #define M33_NVIC_IPR13_PRI_N0_BITS _u(0x000000f0) 3198 #define M33_NVIC_IPR13_PRI_N0_MSB _u(7) 3199 #define M33_NVIC_IPR13_PRI_N0_LSB _u(4) 3200 #define M33_NVIC_IPR13_PRI_N0_ACCESS "RW" 3201 // ============================================================================= 3202 // Register : M33_NVIC_IPR14 3203 // Description : Sets or reads interrupt priorities 3204 #define M33_NVIC_IPR14_OFFSET _u(0x0000e438) 3205 #define M33_NVIC_IPR14_BITS _u(0xf0f0f0f0) 3206 #define M33_NVIC_IPR14_RESET _u(0x00000000) 3207 // ----------------------------------------------------------------------------- 3208 // Field : M33_NVIC_IPR14_PRI_N3 3209 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3210 // or RES0 if the PE does not implement this interrupt 3211 #define M33_NVIC_IPR14_PRI_N3_RESET _u(0x0) 3212 #define M33_NVIC_IPR14_PRI_N3_BITS _u(0xf0000000) 3213 #define M33_NVIC_IPR14_PRI_N3_MSB _u(31) 3214 #define M33_NVIC_IPR14_PRI_N3_LSB _u(28) 3215 #define M33_NVIC_IPR14_PRI_N3_ACCESS "RW" 3216 // ----------------------------------------------------------------------------- 3217 // Field : M33_NVIC_IPR14_PRI_N2 3218 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3219 // or RES0 if the PE does not implement this interrupt 3220 #define M33_NVIC_IPR14_PRI_N2_RESET _u(0x0) 3221 #define M33_NVIC_IPR14_PRI_N2_BITS _u(0x00f00000) 3222 #define M33_NVIC_IPR14_PRI_N2_MSB _u(23) 3223 #define M33_NVIC_IPR14_PRI_N2_LSB _u(20) 3224 #define M33_NVIC_IPR14_PRI_N2_ACCESS "RW" 3225 // ----------------------------------------------------------------------------- 3226 // Field : M33_NVIC_IPR14_PRI_N1 3227 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3228 // or RES0 if the PE does not implement this interrupt 3229 #define M33_NVIC_IPR14_PRI_N1_RESET _u(0x0) 3230 #define M33_NVIC_IPR14_PRI_N1_BITS _u(0x0000f000) 3231 #define M33_NVIC_IPR14_PRI_N1_MSB _u(15) 3232 #define M33_NVIC_IPR14_PRI_N1_LSB _u(12) 3233 #define M33_NVIC_IPR14_PRI_N1_ACCESS "RW" 3234 // ----------------------------------------------------------------------------- 3235 // Field : M33_NVIC_IPR14_PRI_N0 3236 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3237 // or RES0 if the PE does not implement this interrupt 3238 #define M33_NVIC_IPR14_PRI_N0_RESET _u(0x0) 3239 #define M33_NVIC_IPR14_PRI_N0_BITS _u(0x000000f0) 3240 #define M33_NVIC_IPR14_PRI_N0_MSB _u(7) 3241 #define M33_NVIC_IPR14_PRI_N0_LSB _u(4) 3242 #define M33_NVIC_IPR14_PRI_N0_ACCESS "RW" 3243 // ============================================================================= 3244 // Register : M33_NVIC_IPR15 3245 // Description : Sets or reads interrupt priorities 3246 #define M33_NVIC_IPR15_OFFSET _u(0x0000e43c) 3247 #define M33_NVIC_IPR15_BITS _u(0xf0f0f0f0) 3248 #define M33_NVIC_IPR15_RESET _u(0x00000000) 3249 // ----------------------------------------------------------------------------- 3250 // Field : M33_NVIC_IPR15_PRI_N3 3251 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, 3252 // or RES0 if the PE does not implement this interrupt 3253 #define M33_NVIC_IPR15_PRI_N3_RESET _u(0x0) 3254 #define M33_NVIC_IPR15_PRI_N3_BITS _u(0xf0000000) 3255 #define M33_NVIC_IPR15_PRI_N3_MSB _u(31) 3256 #define M33_NVIC_IPR15_PRI_N3_LSB _u(28) 3257 #define M33_NVIC_IPR15_PRI_N3_ACCESS "RW" 3258 // ----------------------------------------------------------------------------- 3259 // Field : M33_NVIC_IPR15_PRI_N2 3260 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, 3261 // or RES0 if the PE does not implement this interrupt 3262 #define M33_NVIC_IPR15_PRI_N2_RESET _u(0x0) 3263 #define M33_NVIC_IPR15_PRI_N2_BITS _u(0x00f00000) 3264 #define M33_NVIC_IPR15_PRI_N2_MSB _u(23) 3265 #define M33_NVIC_IPR15_PRI_N2_LSB _u(20) 3266 #define M33_NVIC_IPR15_PRI_N2_ACCESS "RW" 3267 // ----------------------------------------------------------------------------- 3268 // Field : M33_NVIC_IPR15_PRI_N1 3269 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, 3270 // or RES0 if the PE does not implement this interrupt 3271 #define M33_NVIC_IPR15_PRI_N1_RESET _u(0x0) 3272 #define M33_NVIC_IPR15_PRI_N1_BITS _u(0x0000f000) 3273 #define M33_NVIC_IPR15_PRI_N1_MSB _u(15) 3274 #define M33_NVIC_IPR15_PRI_N1_LSB _u(12) 3275 #define M33_NVIC_IPR15_PRI_N1_ACCESS "RW" 3276 // ----------------------------------------------------------------------------- 3277 // Field : M33_NVIC_IPR15_PRI_N0 3278 // Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, 3279 // or RES0 if the PE does not implement this interrupt 3280 #define M33_NVIC_IPR15_PRI_N0_RESET _u(0x0) 3281 #define M33_NVIC_IPR15_PRI_N0_BITS _u(0x000000f0) 3282 #define M33_NVIC_IPR15_PRI_N0_MSB _u(7) 3283 #define M33_NVIC_IPR15_PRI_N0_LSB _u(4) 3284 #define M33_NVIC_IPR15_PRI_N0_ACCESS "RW" 3285 // ============================================================================= 3286 // Register : M33_CPUID 3287 // Description : Provides identification information for the PE, including an 3288 // implementer code for the device and a device ID number 3289 #define M33_CPUID_OFFSET _u(0x0000ed00) 3290 #define M33_CPUID_BITS _u(0xffffffff) 3291 #define M33_CPUID_RESET _u(0x411fd210) 3292 // ----------------------------------------------------------------------------- 3293 // Field : M33_CPUID_IMPLEMENTER 3294 // Description : This field must hold an implementer code that has been assigned 3295 // by ARM 3296 #define M33_CPUID_IMPLEMENTER_RESET _u(0x41) 3297 #define M33_CPUID_IMPLEMENTER_BITS _u(0xff000000) 3298 #define M33_CPUID_IMPLEMENTER_MSB _u(31) 3299 #define M33_CPUID_IMPLEMENTER_LSB _u(24) 3300 #define M33_CPUID_IMPLEMENTER_ACCESS "RO" 3301 // ----------------------------------------------------------------------------- 3302 // Field : M33_CPUID_VARIANT 3303 // Description : IMPLEMENTATION DEFINED variant number. Typically, this field is 3304 // used to distinguish between different product variants, or 3305 // major revisions of a product 3306 #define M33_CPUID_VARIANT_RESET _u(0x1) 3307 #define M33_CPUID_VARIANT_BITS _u(0x00f00000) 3308 #define M33_CPUID_VARIANT_MSB _u(23) 3309 #define M33_CPUID_VARIANT_LSB _u(20) 3310 #define M33_CPUID_VARIANT_ACCESS "RO" 3311 // ----------------------------------------------------------------------------- 3312 // Field : M33_CPUID_ARCHITECTURE 3313 // Description : Defines the Architecture implemented by the PE 3314 #define M33_CPUID_ARCHITECTURE_RESET _u(0xf) 3315 #define M33_CPUID_ARCHITECTURE_BITS _u(0x000f0000) 3316 #define M33_CPUID_ARCHITECTURE_MSB _u(19) 3317 #define M33_CPUID_ARCHITECTURE_LSB _u(16) 3318 #define M33_CPUID_ARCHITECTURE_ACCESS "RO" 3319 // ----------------------------------------------------------------------------- 3320 // Field : M33_CPUID_PARTNO 3321 // Description : IMPLEMENTATION DEFINED primary part number for the device 3322 #define M33_CPUID_PARTNO_RESET _u(0xd21) 3323 #define M33_CPUID_PARTNO_BITS _u(0x0000fff0) 3324 #define M33_CPUID_PARTNO_MSB _u(15) 3325 #define M33_CPUID_PARTNO_LSB _u(4) 3326 #define M33_CPUID_PARTNO_ACCESS "RO" 3327 // ----------------------------------------------------------------------------- 3328 // Field : M33_CPUID_REVISION 3329 // Description : IMPLEMENTATION DEFINED revision number for the device 3330 #define M33_CPUID_REVISION_RESET _u(0x0) 3331 #define M33_CPUID_REVISION_BITS _u(0x0000000f) 3332 #define M33_CPUID_REVISION_MSB _u(3) 3333 #define M33_CPUID_REVISION_LSB _u(0) 3334 #define M33_CPUID_REVISION_ACCESS "RO" 3335 // ============================================================================= 3336 // Register : M33_ICSR 3337 // Description : Controls and provides status information for NMI, PendSV, 3338 // SysTick and interrupts 3339 #define M33_ICSR_OFFSET _u(0x0000ed04) 3340 #define M33_ICSR_BITS _u(0xdfdff9ff) 3341 #define M33_ICSR_RESET _u(0x00000000) 3342 // ----------------------------------------------------------------------------- 3343 // Field : M33_ICSR_PENDNMISET 3344 // Description : Indicates whether the NMI exception is pending 3345 #define M33_ICSR_PENDNMISET_RESET _u(0x0) 3346 #define M33_ICSR_PENDNMISET_BITS _u(0x80000000) 3347 #define M33_ICSR_PENDNMISET_MSB _u(31) 3348 #define M33_ICSR_PENDNMISET_LSB _u(31) 3349 #define M33_ICSR_PENDNMISET_ACCESS "RO" 3350 // ----------------------------------------------------------------------------- 3351 // Field : M33_ICSR_PENDNMICLR 3352 // Description : Allows the NMI exception pend state to be cleared 3353 #define M33_ICSR_PENDNMICLR_RESET _u(0x0) 3354 #define M33_ICSR_PENDNMICLR_BITS _u(0x40000000) 3355 #define M33_ICSR_PENDNMICLR_MSB _u(30) 3356 #define M33_ICSR_PENDNMICLR_LSB _u(30) 3357 #define M33_ICSR_PENDNMICLR_ACCESS "RW" 3358 // ----------------------------------------------------------------------------- 3359 // Field : M33_ICSR_PENDSVSET 3360 // Description : Indicates whether the PendSV `FTSSS exception is pending 3361 #define M33_ICSR_PENDSVSET_RESET _u(0x0) 3362 #define M33_ICSR_PENDSVSET_BITS _u(0x10000000) 3363 #define M33_ICSR_PENDSVSET_MSB _u(28) 3364 #define M33_ICSR_PENDSVSET_LSB _u(28) 3365 #define M33_ICSR_PENDSVSET_ACCESS "RO" 3366 // ----------------------------------------------------------------------------- 3367 // Field : M33_ICSR_PENDSVCLR 3368 // Description : Allows the PendSV exception pend state to be cleared `FTSSS 3369 #define M33_ICSR_PENDSVCLR_RESET _u(0x0) 3370 #define M33_ICSR_PENDSVCLR_BITS _u(0x08000000) 3371 #define M33_ICSR_PENDSVCLR_MSB _u(27) 3372 #define M33_ICSR_PENDSVCLR_LSB _u(27) 3373 #define M33_ICSR_PENDSVCLR_ACCESS "RW" 3374 // ----------------------------------------------------------------------------- 3375 // Field : M33_ICSR_PENDSTSET 3376 // Description : Indicates whether the SysTick `FTSSS exception is pending 3377 #define M33_ICSR_PENDSTSET_RESET _u(0x0) 3378 #define M33_ICSR_PENDSTSET_BITS _u(0x04000000) 3379 #define M33_ICSR_PENDSTSET_MSB _u(26) 3380 #define M33_ICSR_PENDSTSET_LSB _u(26) 3381 #define M33_ICSR_PENDSTSET_ACCESS "RO" 3382 // ----------------------------------------------------------------------------- 3383 // Field : M33_ICSR_PENDSTCLR 3384 // Description : Allows the SysTick exception pend state to be cleared `FTSSS 3385 #define M33_ICSR_PENDSTCLR_RESET _u(0x0) 3386 #define M33_ICSR_PENDSTCLR_BITS _u(0x02000000) 3387 #define M33_ICSR_PENDSTCLR_MSB _u(25) 3388 #define M33_ICSR_PENDSTCLR_LSB _u(25) 3389 #define M33_ICSR_PENDSTCLR_ACCESS "RW" 3390 // ----------------------------------------------------------------------------- 3391 // Field : M33_ICSR_STTNS 3392 // Description : Controls whether in a single SysTick implementation, the 3393 // SysTick is Secure or Non-secure 3394 #define M33_ICSR_STTNS_RESET _u(0x0) 3395 #define M33_ICSR_STTNS_BITS _u(0x01000000) 3396 #define M33_ICSR_STTNS_MSB _u(24) 3397 #define M33_ICSR_STTNS_LSB _u(24) 3398 #define M33_ICSR_STTNS_ACCESS "RW" 3399 // ----------------------------------------------------------------------------- 3400 // Field : M33_ICSR_ISRPREEMPT 3401 // Description : Indicates whether a pending exception will be serviced on exit 3402 // from debug halt state 3403 #define M33_ICSR_ISRPREEMPT_RESET _u(0x0) 3404 #define M33_ICSR_ISRPREEMPT_BITS _u(0x00800000) 3405 #define M33_ICSR_ISRPREEMPT_MSB _u(23) 3406 #define M33_ICSR_ISRPREEMPT_LSB _u(23) 3407 #define M33_ICSR_ISRPREEMPT_ACCESS "RO" 3408 // ----------------------------------------------------------------------------- 3409 // Field : M33_ICSR_ISRPENDING 3410 // Description : Indicates whether an external interrupt, generated by the NVIC, 3411 // is pending 3412 #define M33_ICSR_ISRPENDING_RESET _u(0x0) 3413 #define M33_ICSR_ISRPENDING_BITS _u(0x00400000) 3414 #define M33_ICSR_ISRPENDING_MSB _u(22) 3415 #define M33_ICSR_ISRPENDING_LSB _u(22) 3416 #define M33_ICSR_ISRPENDING_ACCESS "RO" 3417 // ----------------------------------------------------------------------------- 3418 // Field : M33_ICSR_VECTPENDING 3419 // Description : The exception number of the highest priority pending and 3420 // enabled interrupt 3421 #define M33_ICSR_VECTPENDING_RESET _u(0x000) 3422 #define M33_ICSR_VECTPENDING_BITS _u(0x001ff000) 3423 #define M33_ICSR_VECTPENDING_MSB _u(20) 3424 #define M33_ICSR_VECTPENDING_LSB _u(12) 3425 #define M33_ICSR_VECTPENDING_ACCESS "RO" 3426 // ----------------------------------------------------------------------------- 3427 // Field : M33_ICSR_RETTOBASE 3428 // Description : In Handler mode, indicates whether there is more than one 3429 // active exception 3430 #define M33_ICSR_RETTOBASE_RESET _u(0x0) 3431 #define M33_ICSR_RETTOBASE_BITS _u(0x00000800) 3432 #define M33_ICSR_RETTOBASE_MSB _u(11) 3433 #define M33_ICSR_RETTOBASE_LSB _u(11) 3434 #define M33_ICSR_RETTOBASE_ACCESS "RO" 3435 // ----------------------------------------------------------------------------- 3436 // Field : M33_ICSR_VECTACTIVE 3437 // Description : The exception number of the current executing exception 3438 #define M33_ICSR_VECTACTIVE_RESET _u(0x000) 3439 #define M33_ICSR_VECTACTIVE_BITS _u(0x000001ff) 3440 #define M33_ICSR_VECTACTIVE_MSB _u(8) 3441 #define M33_ICSR_VECTACTIVE_LSB _u(0) 3442 #define M33_ICSR_VECTACTIVE_ACCESS "RO" 3443 // ============================================================================= 3444 // Register : M33_VTOR 3445 // Description : The VTOR indicates the offset of the vector table base address 3446 // from memory address 0x00000000. 3447 #define M33_VTOR_OFFSET _u(0x0000ed08) 3448 #define M33_VTOR_BITS _u(0xffffff80) 3449 #define M33_VTOR_RESET _u(0x00000000) 3450 // ----------------------------------------------------------------------------- 3451 // Field : M33_VTOR_TBLOFF 3452 // Description : Vector table base offset field. It contains bits[31:7] of the 3453 // offset of the table base from the bottom of the memory map. 3454 #define M33_VTOR_TBLOFF_RESET _u(0x0000000) 3455 #define M33_VTOR_TBLOFF_BITS _u(0xffffff80) 3456 #define M33_VTOR_TBLOFF_MSB _u(31) 3457 #define M33_VTOR_TBLOFF_LSB _u(7) 3458 #define M33_VTOR_TBLOFF_ACCESS "RW" 3459 // ============================================================================= 3460 // Register : M33_AIRCR 3461 // Description : Use the Application Interrupt and Reset Control Register to: 3462 // determine data endianness, clear all active state information 3463 // from debug halt mode, request a system reset. 3464 #define M33_AIRCR_OFFSET _u(0x0000ed0c) 3465 #define M33_AIRCR_BITS _u(0xffffe70e) 3466 #define M33_AIRCR_RESET _u(0x00000000) 3467 // ----------------------------------------------------------------------------- 3468 // Field : M33_AIRCR_VECTKEY 3469 // Description : Register key: 3470 // Reads as Unknown 3471 // On writes, write 0x05FA to VECTKEY, otherwise the write is 3472 // ignored. 3473 #define M33_AIRCR_VECTKEY_RESET _u(0x0000) 3474 #define M33_AIRCR_VECTKEY_BITS _u(0xffff0000) 3475 #define M33_AIRCR_VECTKEY_MSB _u(31) 3476 #define M33_AIRCR_VECTKEY_LSB _u(16) 3477 #define M33_AIRCR_VECTKEY_ACCESS "RW" 3478 // ----------------------------------------------------------------------------- 3479 // Field : M33_AIRCR_ENDIANESS 3480 // Description : Data endianness implemented: 3481 // 0 = Little-endian. 3482 #define M33_AIRCR_ENDIANESS_RESET _u(0x0) 3483 #define M33_AIRCR_ENDIANESS_BITS _u(0x00008000) 3484 #define M33_AIRCR_ENDIANESS_MSB _u(15) 3485 #define M33_AIRCR_ENDIANESS_LSB _u(15) 3486 #define M33_AIRCR_ENDIANESS_ACCESS "RO" 3487 // ----------------------------------------------------------------------------- 3488 // Field : M33_AIRCR_PRIS 3489 // Description : Prioritize Secure exceptions. The value of this bit defines 3490 // whether Secure exception priority boosting is enabled. 3491 // 0 Priority ranges of Secure and Non-secure exceptions are 3492 // identical. 3493 // 1 Non-secure exceptions are de-prioritized. 3494 #define M33_AIRCR_PRIS_RESET _u(0x0) 3495 #define M33_AIRCR_PRIS_BITS _u(0x00004000) 3496 #define M33_AIRCR_PRIS_MSB _u(14) 3497 #define M33_AIRCR_PRIS_LSB _u(14) 3498 #define M33_AIRCR_PRIS_ACCESS "RW" 3499 // ----------------------------------------------------------------------------- 3500 // Field : M33_AIRCR_BFHFNMINS 3501 // Description : BusFault, HardFault, and NMI Non-secure enable. 3502 // 0 BusFault, HardFault, and NMI are Secure. 3503 // 1 BusFault and NMI are Non-secure and exceptions can target 3504 // Non-secure HardFault. 3505 #define M33_AIRCR_BFHFNMINS_RESET _u(0x0) 3506 #define M33_AIRCR_BFHFNMINS_BITS _u(0x00002000) 3507 #define M33_AIRCR_BFHFNMINS_MSB _u(13) 3508 #define M33_AIRCR_BFHFNMINS_LSB _u(13) 3509 #define M33_AIRCR_BFHFNMINS_ACCESS "RW" 3510 // ----------------------------------------------------------------------------- 3511 // Field : M33_AIRCR_PRIGROUP 3512 // Description : Interrupt priority grouping field. This field determines the 3513 // split of group priority from subpriority. 3514 // See https://developer.arm.com/documentation/100235/0004/the- 3515 // cortex-m33-peripherals/system-control-block/application- 3516 // interrupt-and-reset-control-register?lang=en 3517 #define M33_AIRCR_PRIGROUP_RESET _u(0x0) 3518 #define M33_AIRCR_PRIGROUP_BITS _u(0x00000700) 3519 #define M33_AIRCR_PRIGROUP_MSB _u(10) 3520 #define M33_AIRCR_PRIGROUP_LSB _u(8) 3521 #define M33_AIRCR_PRIGROUP_ACCESS "RW" 3522 // ----------------------------------------------------------------------------- 3523 // Field : M33_AIRCR_SYSRESETREQS 3524 // Description : System reset request, Secure state only. 3525 // 0 SYSRESETREQ functionality is available to both Security 3526 // states. 3527 // 1 SYSRESETREQ functionality is only available to Secure state. 3528 #define M33_AIRCR_SYSRESETREQS_RESET _u(0x0) 3529 #define M33_AIRCR_SYSRESETREQS_BITS _u(0x00000008) 3530 #define M33_AIRCR_SYSRESETREQS_MSB _u(3) 3531 #define M33_AIRCR_SYSRESETREQS_LSB _u(3) 3532 #define M33_AIRCR_SYSRESETREQS_ACCESS "RW" 3533 // ----------------------------------------------------------------------------- 3534 // Field : M33_AIRCR_SYSRESETREQ 3535 // Description : Writing 1 to this bit causes the SYSRESETREQ signal to the 3536 // outer system to be asserted to request a reset. The intention 3537 // is to force a large system reset of all major components except 3538 // for debug. The C_HALT bit in the DHCSR is cleared as a result 3539 // of the system reset requested. The debugger does not lose 3540 // contact with the device. 3541 #define M33_AIRCR_SYSRESETREQ_RESET _u(0x0) 3542 #define M33_AIRCR_SYSRESETREQ_BITS _u(0x00000004) 3543 #define M33_AIRCR_SYSRESETREQ_MSB _u(2) 3544 #define M33_AIRCR_SYSRESETREQ_LSB _u(2) 3545 #define M33_AIRCR_SYSRESETREQ_ACCESS "RW" 3546 // ----------------------------------------------------------------------------- 3547 // Field : M33_AIRCR_VECTCLRACTIVE 3548 // Description : Clears all active state information for fixed and configurable 3549 // exceptions. This bit: is self-clearing, can only be set by the 3550 // DAP when the core is halted. When set: clears all active 3551 // exception status of the processor, forces a return to Thread 3552 // mode, forces an IPSR of 0. A debugger must re-initialize the 3553 // stack. 3554 #define M33_AIRCR_VECTCLRACTIVE_RESET _u(0x0) 3555 #define M33_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) 3556 #define M33_AIRCR_VECTCLRACTIVE_MSB _u(1) 3557 #define M33_AIRCR_VECTCLRACTIVE_LSB _u(1) 3558 #define M33_AIRCR_VECTCLRACTIVE_ACCESS "RW" 3559 // ============================================================================= 3560 // Register : M33_SCR 3561 // Description : System Control Register. Use the System Control Register for 3562 // power-management functions: signal to the system when the 3563 // processor can enter a low power state, control how the 3564 // processor enters and exits low power states. 3565 #define M33_SCR_OFFSET _u(0x0000ed10) 3566 #define M33_SCR_BITS _u(0x0000001e) 3567 #define M33_SCR_RESET _u(0x00000000) 3568 // ----------------------------------------------------------------------------- 3569 // Field : M33_SCR_SEVONPEND 3570 // Description : Send Event on Pending bit: 3571 // 0 = Only enabled interrupts or events can wakeup the processor, 3572 // disabled interrupts are excluded. 3573 // 1 = Enabled events and all interrupts, including disabled 3574 // interrupts, can wakeup the processor. 3575 // When an event or interrupt becomes pending, the event signal 3576 // wakes up the processor from WFE. If the 3577 // processor is not waiting for an event, the event is registered 3578 // and affects the next WFE. 3579 // The processor also wakes up on execution of an SEV instruction 3580 // or an external event. 3581 #define M33_SCR_SEVONPEND_RESET _u(0x0) 3582 #define M33_SCR_SEVONPEND_BITS _u(0x00000010) 3583 #define M33_SCR_SEVONPEND_MSB _u(4) 3584 #define M33_SCR_SEVONPEND_LSB _u(4) 3585 #define M33_SCR_SEVONPEND_ACCESS "RW" 3586 // ----------------------------------------------------------------------------- 3587 // Field : M33_SCR_SLEEPDEEPS 3588 // Description : 0 SLEEPDEEP is available to both security states 3589 // 1 SLEEPDEEP is only available to Secure state 3590 #define M33_SCR_SLEEPDEEPS_RESET _u(0x0) 3591 #define M33_SCR_SLEEPDEEPS_BITS _u(0x00000008) 3592 #define M33_SCR_SLEEPDEEPS_MSB _u(3) 3593 #define M33_SCR_SLEEPDEEPS_LSB _u(3) 3594 #define M33_SCR_SLEEPDEEPS_ACCESS "RW" 3595 // ----------------------------------------------------------------------------- 3596 // Field : M33_SCR_SLEEPDEEP 3597 // Description : Controls whether the processor uses sleep or deep sleep as its 3598 // low power mode: 3599 // 0 = Sleep. 3600 // 1 = Deep sleep. 3601 #define M33_SCR_SLEEPDEEP_RESET _u(0x0) 3602 #define M33_SCR_SLEEPDEEP_BITS _u(0x00000004) 3603 #define M33_SCR_SLEEPDEEP_MSB _u(2) 3604 #define M33_SCR_SLEEPDEEP_LSB _u(2) 3605 #define M33_SCR_SLEEPDEEP_ACCESS "RW" 3606 // ----------------------------------------------------------------------------- 3607 // Field : M33_SCR_SLEEPONEXIT 3608 // Description : Indicates sleep-on-exit when returning from Handler mode to 3609 // Thread mode: 3610 // 0 = Do not sleep when returning to Thread mode. 3611 // 1 = Enter sleep, or deep sleep, on return from an ISR to Thread 3612 // mode. 3613 // Setting this bit to 1 enables an interrupt driven application 3614 // to avoid returning to an empty main application. 3615 #define M33_SCR_SLEEPONEXIT_RESET _u(0x0) 3616 #define M33_SCR_SLEEPONEXIT_BITS _u(0x00000002) 3617 #define M33_SCR_SLEEPONEXIT_MSB _u(1) 3618 #define M33_SCR_SLEEPONEXIT_LSB _u(1) 3619 #define M33_SCR_SLEEPONEXIT_ACCESS "RW" 3620 // ============================================================================= 3621 // Register : M33_CCR 3622 // Description : Sets or returns configuration and control data 3623 #define M33_CCR_OFFSET _u(0x0000ed14) 3624 #define M33_CCR_BITS _u(0x0007071b) 3625 #define M33_CCR_RESET _u(0x00000201) 3626 // ----------------------------------------------------------------------------- 3627 // Field : M33_CCR_BP 3628 // Description : Enables program flow prediction `FTSSS 3629 #define M33_CCR_BP_RESET _u(0x0) 3630 #define M33_CCR_BP_BITS _u(0x00040000) 3631 #define M33_CCR_BP_MSB _u(18) 3632 #define M33_CCR_BP_LSB _u(18) 3633 #define M33_CCR_BP_ACCESS "RO" 3634 // ----------------------------------------------------------------------------- 3635 // Field : M33_CCR_IC 3636 // Description : This is a global enable bit for instruction caches in the 3637 // selected Security state 3638 #define M33_CCR_IC_RESET _u(0x0) 3639 #define M33_CCR_IC_BITS _u(0x00020000) 3640 #define M33_CCR_IC_MSB _u(17) 3641 #define M33_CCR_IC_LSB _u(17) 3642 #define M33_CCR_IC_ACCESS "RO" 3643 // ----------------------------------------------------------------------------- 3644 // Field : M33_CCR_DC 3645 // Description : Enables data caching of all data accesses to Normal memory 3646 // `FTSSS 3647 #define M33_CCR_DC_RESET _u(0x0) 3648 #define M33_CCR_DC_BITS _u(0x00010000) 3649 #define M33_CCR_DC_MSB _u(16) 3650 #define M33_CCR_DC_LSB _u(16) 3651 #define M33_CCR_DC_ACCESS "RO" 3652 // ----------------------------------------------------------------------------- 3653 // Field : M33_CCR_STKOFHFNMIGN 3654 // Description : Controls the effect of a stack limit violation while executing 3655 // at a requested priority less than 0 3656 #define M33_CCR_STKOFHFNMIGN_RESET _u(0x0) 3657 #define M33_CCR_STKOFHFNMIGN_BITS _u(0x00000400) 3658 #define M33_CCR_STKOFHFNMIGN_MSB _u(10) 3659 #define M33_CCR_STKOFHFNMIGN_LSB _u(10) 3660 #define M33_CCR_STKOFHFNMIGN_ACCESS "RW" 3661 // ----------------------------------------------------------------------------- 3662 // Field : M33_CCR_RES1 3663 // Description : Reserved, RES1 3664 #define M33_CCR_RES1_RESET _u(0x1) 3665 #define M33_CCR_RES1_BITS _u(0x00000200) 3666 #define M33_CCR_RES1_MSB _u(9) 3667 #define M33_CCR_RES1_LSB _u(9) 3668 #define M33_CCR_RES1_ACCESS "RO" 3669 // ----------------------------------------------------------------------------- 3670 // Field : M33_CCR_BFHFNMIGN 3671 // Description : Determines the effect of precise BusFaults on handlers running 3672 // at a requested priority less than 0 3673 #define M33_CCR_BFHFNMIGN_RESET _u(0x0) 3674 #define M33_CCR_BFHFNMIGN_BITS _u(0x00000100) 3675 #define M33_CCR_BFHFNMIGN_MSB _u(8) 3676 #define M33_CCR_BFHFNMIGN_LSB _u(8) 3677 #define M33_CCR_BFHFNMIGN_ACCESS "RW" 3678 // ----------------------------------------------------------------------------- 3679 // Field : M33_CCR_DIV_0_TRP 3680 // Description : Controls the generation of a DIVBYZERO UsageFault when 3681 // attempting to perform integer division by zero 3682 #define M33_CCR_DIV_0_TRP_RESET _u(0x0) 3683 #define M33_CCR_DIV_0_TRP_BITS _u(0x00000010) 3684 #define M33_CCR_DIV_0_TRP_MSB _u(4) 3685 #define M33_CCR_DIV_0_TRP_LSB _u(4) 3686 #define M33_CCR_DIV_0_TRP_ACCESS "RW" 3687 // ----------------------------------------------------------------------------- 3688 // Field : M33_CCR_UNALIGN_TRP 3689 // Description : Controls the trapping of unaligned word or halfword accesses 3690 #define M33_CCR_UNALIGN_TRP_RESET _u(0x0) 3691 #define M33_CCR_UNALIGN_TRP_BITS _u(0x00000008) 3692 #define M33_CCR_UNALIGN_TRP_MSB _u(3) 3693 #define M33_CCR_UNALIGN_TRP_LSB _u(3) 3694 #define M33_CCR_UNALIGN_TRP_ACCESS "RW" 3695 // ----------------------------------------------------------------------------- 3696 // Field : M33_CCR_USERSETMPEND 3697 // Description : Determines whether unprivileged accesses are permitted to pend 3698 // interrupts via the STIR 3699 #define M33_CCR_USERSETMPEND_RESET _u(0x0) 3700 #define M33_CCR_USERSETMPEND_BITS _u(0x00000002) 3701 #define M33_CCR_USERSETMPEND_MSB _u(1) 3702 #define M33_CCR_USERSETMPEND_LSB _u(1) 3703 #define M33_CCR_USERSETMPEND_ACCESS "RW" 3704 // ----------------------------------------------------------------------------- 3705 // Field : M33_CCR_RES1_1 3706 // Description : Reserved, RES1 3707 #define M33_CCR_RES1_1_RESET _u(0x1) 3708 #define M33_CCR_RES1_1_BITS _u(0x00000001) 3709 #define M33_CCR_RES1_1_MSB _u(0) 3710 #define M33_CCR_RES1_1_LSB _u(0) 3711 #define M33_CCR_RES1_1_ACCESS "RO" 3712 // ============================================================================= 3713 // Register : M33_SHPR1 3714 // Description : Sets or returns priority for system handlers 4 - 7 3715 #define M33_SHPR1_OFFSET _u(0x0000ed18) 3716 #define M33_SHPR1_BITS _u(0xe0e0e0e0) 3717 #define M33_SHPR1_RESET _u(0x00000000) 3718 // ----------------------------------------------------------------------------- 3719 // Field : M33_SHPR1_PRI_7_3 3720 // Description : Priority of system handler 7, SecureFault 3721 #define M33_SHPR1_PRI_7_3_RESET _u(0x0) 3722 #define M33_SHPR1_PRI_7_3_BITS _u(0xe0000000) 3723 #define M33_SHPR1_PRI_7_3_MSB _u(31) 3724 #define M33_SHPR1_PRI_7_3_LSB _u(29) 3725 #define M33_SHPR1_PRI_7_3_ACCESS "RW" 3726 // ----------------------------------------------------------------------------- 3727 // Field : M33_SHPR1_PRI_6_3 3728 // Description : Priority of system handler 6, SecureFault 3729 #define M33_SHPR1_PRI_6_3_RESET _u(0x0) 3730 #define M33_SHPR1_PRI_6_3_BITS _u(0x00e00000) 3731 #define M33_SHPR1_PRI_6_3_MSB _u(23) 3732 #define M33_SHPR1_PRI_6_3_LSB _u(21) 3733 #define M33_SHPR1_PRI_6_3_ACCESS "RW" 3734 // ----------------------------------------------------------------------------- 3735 // Field : M33_SHPR1_PRI_5_3 3736 // Description : Priority of system handler 5, SecureFault 3737 #define M33_SHPR1_PRI_5_3_RESET _u(0x0) 3738 #define M33_SHPR1_PRI_5_3_BITS _u(0x0000e000) 3739 #define M33_SHPR1_PRI_5_3_MSB _u(15) 3740 #define M33_SHPR1_PRI_5_3_LSB _u(13) 3741 #define M33_SHPR1_PRI_5_3_ACCESS "RW" 3742 // ----------------------------------------------------------------------------- 3743 // Field : M33_SHPR1_PRI_4_3 3744 // Description : Priority of system handler 4, SecureFault 3745 #define M33_SHPR1_PRI_4_3_RESET _u(0x0) 3746 #define M33_SHPR1_PRI_4_3_BITS _u(0x000000e0) 3747 #define M33_SHPR1_PRI_4_3_MSB _u(7) 3748 #define M33_SHPR1_PRI_4_3_LSB _u(5) 3749 #define M33_SHPR1_PRI_4_3_ACCESS "RW" 3750 // ============================================================================= 3751 // Register : M33_SHPR2 3752 // Description : Sets or returns priority for system handlers 8 - 11 3753 #define M33_SHPR2_OFFSET _u(0x0000ed1c) 3754 #define M33_SHPR2_BITS _u(0xe0ffffff) 3755 #define M33_SHPR2_RESET _u(0x00000000) 3756 // ----------------------------------------------------------------------------- 3757 // Field : M33_SHPR2_PRI_11_3 3758 // Description : Priority of system handler 11, SecureFault 3759 #define M33_SHPR2_PRI_11_3_RESET _u(0x0) 3760 #define M33_SHPR2_PRI_11_3_BITS _u(0xe0000000) 3761 #define M33_SHPR2_PRI_11_3_MSB _u(31) 3762 #define M33_SHPR2_PRI_11_3_LSB _u(29) 3763 #define M33_SHPR2_PRI_11_3_ACCESS "RW" 3764 // ----------------------------------------------------------------------------- 3765 // Field : M33_SHPR2_PRI_10 3766 // Description : Reserved, RES0 3767 #define M33_SHPR2_PRI_10_RESET _u(0x00) 3768 #define M33_SHPR2_PRI_10_BITS _u(0x00ff0000) 3769 #define M33_SHPR2_PRI_10_MSB _u(23) 3770 #define M33_SHPR2_PRI_10_LSB _u(16) 3771 #define M33_SHPR2_PRI_10_ACCESS "RO" 3772 // ----------------------------------------------------------------------------- 3773 // Field : M33_SHPR2_PRI_9 3774 // Description : Reserved, RES0 3775 #define M33_SHPR2_PRI_9_RESET _u(0x00) 3776 #define M33_SHPR2_PRI_9_BITS _u(0x0000ff00) 3777 #define M33_SHPR2_PRI_9_MSB _u(15) 3778 #define M33_SHPR2_PRI_9_LSB _u(8) 3779 #define M33_SHPR2_PRI_9_ACCESS "RO" 3780 // ----------------------------------------------------------------------------- 3781 // Field : M33_SHPR2_PRI_8 3782 // Description : Reserved, RES0 3783 #define M33_SHPR2_PRI_8_RESET _u(0x00) 3784 #define M33_SHPR2_PRI_8_BITS _u(0x000000ff) 3785 #define M33_SHPR2_PRI_8_MSB _u(7) 3786 #define M33_SHPR2_PRI_8_LSB _u(0) 3787 #define M33_SHPR2_PRI_8_ACCESS "RO" 3788 // ============================================================================= 3789 // Register : M33_SHPR3 3790 // Description : Sets or returns priority for system handlers 12 - 15 3791 #define M33_SHPR3_OFFSET _u(0x0000ed20) 3792 #define M33_SHPR3_BITS _u(0xe0e0ffe0) 3793 #define M33_SHPR3_RESET _u(0x00000000) 3794 // ----------------------------------------------------------------------------- 3795 // Field : M33_SHPR3_PRI_15_3 3796 // Description : Priority of system handler 15, SecureFault 3797 #define M33_SHPR3_PRI_15_3_RESET _u(0x0) 3798 #define M33_SHPR3_PRI_15_3_BITS _u(0xe0000000) 3799 #define M33_SHPR3_PRI_15_3_MSB _u(31) 3800 #define M33_SHPR3_PRI_15_3_LSB _u(29) 3801 #define M33_SHPR3_PRI_15_3_ACCESS "RW" 3802 // ----------------------------------------------------------------------------- 3803 // Field : M33_SHPR3_PRI_14_3 3804 // Description : Priority of system handler 14, SecureFault 3805 #define M33_SHPR3_PRI_14_3_RESET _u(0x0) 3806 #define M33_SHPR3_PRI_14_3_BITS _u(0x00e00000) 3807 #define M33_SHPR3_PRI_14_3_MSB _u(23) 3808 #define M33_SHPR3_PRI_14_3_LSB _u(21) 3809 #define M33_SHPR3_PRI_14_3_ACCESS "RW" 3810 // ----------------------------------------------------------------------------- 3811 // Field : M33_SHPR3_PRI_13 3812 // Description : Reserved, RES0 3813 #define M33_SHPR3_PRI_13_RESET _u(0x00) 3814 #define M33_SHPR3_PRI_13_BITS _u(0x0000ff00) 3815 #define M33_SHPR3_PRI_13_MSB _u(15) 3816 #define M33_SHPR3_PRI_13_LSB _u(8) 3817 #define M33_SHPR3_PRI_13_ACCESS "RO" 3818 // ----------------------------------------------------------------------------- 3819 // Field : M33_SHPR3_PRI_12_3 3820 // Description : Priority of system handler 12, SecureFault 3821 #define M33_SHPR3_PRI_12_3_RESET _u(0x0) 3822 #define M33_SHPR3_PRI_12_3_BITS _u(0x000000e0) 3823 #define M33_SHPR3_PRI_12_3_MSB _u(7) 3824 #define M33_SHPR3_PRI_12_3_LSB _u(5) 3825 #define M33_SHPR3_PRI_12_3_ACCESS "RW" 3826 // ============================================================================= 3827 // Register : M33_SHCSR 3828 // Description : Provides access to the active and pending status of system 3829 // exceptions 3830 #define M33_SHCSR_OFFSET _u(0x0000ed24) 3831 #define M33_SHCSR_BITS _u(0x003ffdbf) 3832 #define M33_SHCSR_RESET _u(0x00000000) 3833 // ----------------------------------------------------------------------------- 3834 // Field : M33_SHCSR_HARDFAULTPENDED 3835 // Description : `IAAMO the pending state of the HardFault exception `CTTSSS 3836 #define M33_SHCSR_HARDFAULTPENDED_RESET _u(0x0) 3837 #define M33_SHCSR_HARDFAULTPENDED_BITS _u(0x00200000) 3838 #define M33_SHCSR_HARDFAULTPENDED_MSB _u(21) 3839 #define M33_SHCSR_HARDFAULTPENDED_LSB _u(21) 3840 #define M33_SHCSR_HARDFAULTPENDED_ACCESS "RW" 3841 // ----------------------------------------------------------------------------- 3842 // Field : M33_SHCSR_SECUREFAULTPENDED 3843 // Description : `IAAMO the pending state of the SecureFault exception 3844 #define M33_SHCSR_SECUREFAULTPENDED_RESET _u(0x0) 3845 #define M33_SHCSR_SECUREFAULTPENDED_BITS _u(0x00100000) 3846 #define M33_SHCSR_SECUREFAULTPENDED_MSB _u(20) 3847 #define M33_SHCSR_SECUREFAULTPENDED_LSB _u(20) 3848 #define M33_SHCSR_SECUREFAULTPENDED_ACCESS "RW" 3849 // ----------------------------------------------------------------------------- 3850 // Field : M33_SHCSR_SECUREFAULTENA 3851 // Description : `DW the SecureFault exception is enabled 3852 #define M33_SHCSR_SECUREFAULTENA_RESET _u(0x0) 3853 #define M33_SHCSR_SECUREFAULTENA_BITS _u(0x00080000) 3854 #define M33_SHCSR_SECUREFAULTENA_MSB _u(19) 3855 #define M33_SHCSR_SECUREFAULTENA_LSB _u(19) 3856 #define M33_SHCSR_SECUREFAULTENA_ACCESS "RW" 3857 // ----------------------------------------------------------------------------- 3858 // Field : M33_SHCSR_USGFAULTENA 3859 // Description : `DW the UsageFault exception is enabled `FTSSS 3860 #define M33_SHCSR_USGFAULTENA_RESET _u(0x0) 3861 #define M33_SHCSR_USGFAULTENA_BITS _u(0x00040000) 3862 #define M33_SHCSR_USGFAULTENA_MSB _u(18) 3863 #define M33_SHCSR_USGFAULTENA_LSB _u(18) 3864 #define M33_SHCSR_USGFAULTENA_ACCESS "RW" 3865 // ----------------------------------------------------------------------------- 3866 // Field : M33_SHCSR_BUSFAULTENA 3867 // Description : `DW the BusFault exception is enabled 3868 #define M33_SHCSR_BUSFAULTENA_RESET _u(0x0) 3869 #define M33_SHCSR_BUSFAULTENA_BITS _u(0x00020000) 3870 #define M33_SHCSR_BUSFAULTENA_MSB _u(17) 3871 #define M33_SHCSR_BUSFAULTENA_LSB _u(17) 3872 #define M33_SHCSR_BUSFAULTENA_ACCESS "RW" 3873 // ----------------------------------------------------------------------------- 3874 // Field : M33_SHCSR_MEMFAULTENA 3875 // Description : `DW the MemManage exception is enabled `FTSSS 3876 #define M33_SHCSR_MEMFAULTENA_RESET _u(0x0) 3877 #define M33_SHCSR_MEMFAULTENA_BITS _u(0x00010000) 3878 #define M33_SHCSR_MEMFAULTENA_MSB _u(16) 3879 #define M33_SHCSR_MEMFAULTENA_LSB _u(16) 3880 #define M33_SHCSR_MEMFAULTENA_ACCESS "RW" 3881 // ----------------------------------------------------------------------------- 3882 // Field : M33_SHCSR_SVCALLPENDED 3883 // Description : `IAAMO the pending state of the SVCall exception `FTSSS 3884 #define M33_SHCSR_SVCALLPENDED_RESET _u(0x0) 3885 #define M33_SHCSR_SVCALLPENDED_BITS _u(0x00008000) 3886 #define M33_SHCSR_SVCALLPENDED_MSB _u(15) 3887 #define M33_SHCSR_SVCALLPENDED_LSB _u(15) 3888 #define M33_SHCSR_SVCALLPENDED_ACCESS "RW" 3889 // ----------------------------------------------------------------------------- 3890 // Field : M33_SHCSR_BUSFAULTPENDED 3891 // Description : `IAAMO the pending state of the BusFault exception 3892 #define M33_SHCSR_BUSFAULTPENDED_RESET _u(0x0) 3893 #define M33_SHCSR_BUSFAULTPENDED_BITS _u(0x00004000) 3894 #define M33_SHCSR_BUSFAULTPENDED_MSB _u(14) 3895 #define M33_SHCSR_BUSFAULTPENDED_LSB _u(14) 3896 #define M33_SHCSR_BUSFAULTPENDED_ACCESS "RW" 3897 // ----------------------------------------------------------------------------- 3898 // Field : M33_SHCSR_MEMFAULTPENDED 3899 // Description : `IAAMO the pending state of the MemManage exception `FTSSS 3900 #define M33_SHCSR_MEMFAULTPENDED_RESET _u(0x0) 3901 #define M33_SHCSR_MEMFAULTPENDED_BITS _u(0x00002000) 3902 #define M33_SHCSR_MEMFAULTPENDED_MSB _u(13) 3903 #define M33_SHCSR_MEMFAULTPENDED_LSB _u(13) 3904 #define M33_SHCSR_MEMFAULTPENDED_ACCESS "RW" 3905 // ----------------------------------------------------------------------------- 3906 // Field : M33_SHCSR_USGFAULTPENDED 3907 // Description : The UsageFault exception is banked between Security states, 3908 // `IAAMO the pending state of the UsageFault exception `FTSSS 3909 #define M33_SHCSR_USGFAULTPENDED_RESET _u(0x0) 3910 #define M33_SHCSR_USGFAULTPENDED_BITS _u(0x00001000) 3911 #define M33_SHCSR_USGFAULTPENDED_MSB _u(12) 3912 #define M33_SHCSR_USGFAULTPENDED_LSB _u(12) 3913 #define M33_SHCSR_USGFAULTPENDED_ACCESS "RW" 3914 // ----------------------------------------------------------------------------- 3915 // Field : M33_SHCSR_SYSTICKACT 3916 // Description : `IAAMO the active state of the SysTick exception `FTSSS 3917 #define M33_SHCSR_SYSTICKACT_RESET _u(0x0) 3918 #define M33_SHCSR_SYSTICKACT_BITS _u(0x00000800) 3919 #define M33_SHCSR_SYSTICKACT_MSB _u(11) 3920 #define M33_SHCSR_SYSTICKACT_LSB _u(11) 3921 #define M33_SHCSR_SYSTICKACT_ACCESS "RW" 3922 // ----------------------------------------------------------------------------- 3923 // Field : M33_SHCSR_PENDSVACT 3924 // Description : `IAAMO the active state of the PendSV exception `FTSSS 3925 #define M33_SHCSR_PENDSVACT_RESET _u(0x0) 3926 #define M33_SHCSR_PENDSVACT_BITS _u(0x00000400) 3927 #define M33_SHCSR_PENDSVACT_MSB _u(10) 3928 #define M33_SHCSR_PENDSVACT_LSB _u(10) 3929 #define M33_SHCSR_PENDSVACT_ACCESS "RW" 3930 // ----------------------------------------------------------------------------- 3931 // Field : M33_SHCSR_MONITORACT 3932 // Description : `IAAMO the active state of the DebugMonitor exception 3933 #define M33_SHCSR_MONITORACT_RESET _u(0x0) 3934 #define M33_SHCSR_MONITORACT_BITS _u(0x00000100) 3935 #define M33_SHCSR_MONITORACT_MSB _u(8) 3936 #define M33_SHCSR_MONITORACT_LSB _u(8) 3937 #define M33_SHCSR_MONITORACT_ACCESS "RW" 3938 // ----------------------------------------------------------------------------- 3939 // Field : M33_SHCSR_SVCALLACT 3940 // Description : `IAAMO the active state of the SVCall exception `FTSSS 3941 #define M33_SHCSR_SVCALLACT_RESET _u(0x0) 3942 #define M33_SHCSR_SVCALLACT_BITS _u(0x00000080) 3943 #define M33_SHCSR_SVCALLACT_MSB _u(7) 3944 #define M33_SHCSR_SVCALLACT_LSB _u(7) 3945 #define M33_SHCSR_SVCALLACT_ACCESS "RW" 3946 // ----------------------------------------------------------------------------- 3947 // Field : M33_SHCSR_NMIACT 3948 // Description : `IAAMO the active state of the NMI exception 3949 #define M33_SHCSR_NMIACT_RESET _u(0x0) 3950 #define M33_SHCSR_NMIACT_BITS _u(0x00000020) 3951 #define M33_SHCSR_NMIACT_MSB _u(5) 3952 #define M33_SHCSR_NMIACT_LSB _u(5) 3953 #define M33_SHCSR_NMIACT_ACCESS "RW" 3954 // ----------------------------------------------------------------------------- 3955 // Field : M33_SHCSR_SECUREFAULTACT 3956 // Description : `IAAMO the active state of the SecureFault exception 3957 #define M33_SHCSR_SECUREFAULTACT_RESET _u(0x0) 3958 #define M33_SHCSR_SECUREFAULTACT_BITS _u(0x00000010) 3959 #define M33_SHCSR_SECUREFAULTACT_MSB _u(4) 3960 #define M33_SHCSR_SECUREFAULTACT_LSB _u(4) 3961 #define M33_SHCSR_SECUREFAULTACT_ACCESS "RW" 3962 // ----------------------------------------------------------------------------- 3963 // Field : M33_SHCSR_USGFAULTACT 3964 // Description : `IAAMO the active state of the UsageFault exception `FTSSS 3965 #define M33_SHCSR_USGFAULTACT_RESET _u(0x0) 3966 #define M33_SHCSR_USGFAULTACT_BITS _u(0x00000008) 3967 #define M33_SHCSR_USGFAULTACT_MSB _u(3) 3968 #define M33_SHCSR_USGFAULTACT_LSB _u(3) 3969 #define M33_SHCSR_USGFAULTACT_ACCESS "RW" 3970 // ----------------------------------------------------------------------------- 3971 // Field : M33_SHCSR_HARDFAULTACT 3972 // Description : Indicates and allows limited modification of the active state 3973 // of the HardFault exception `FTSSS 3974 #define M33_SHCSR_HARDFAULTACT_RESET _u(0x0) 3975 #define M33_SHCSR_HARDFAULTACT_BITS _u(0x00000004) 3976 #define M33_SHCSR_HARDFAULTACT_MSB _u(2) 3977 #define M33_SHCSR_HARDFAULTACT_LSB _u(2) 3978 #define M33_SHCSR_HARDFAULTACT_ACCESS "RW" 3979 // ----------------------------------------------------------------------------- 3980 // Field : M33_SHCSR_BUSFAULTACT 3981 // Description : `IAAMO the active state of the BusFault exception 3982 #define M33_SHCSR_BUSFAULTACT_RESET _u(0x0) 3983 #define M33_SHCSR_BUSFAULTACT_BITS _u(0x00000002) 3984 #define M33_SHCSR_BUSFAULTACT_MSB _u(1) 3985 #define M33_SHCSR_BUSFAULTACT_LSB _u(1) 3986 #define M33_SHCSR_BUSFAULTACT_ACCESS "RW" 3987 // ----------------------------------------------------------------------------- 3988 // Field : M33_SHCSR_MEMFAULTACT 3989 // Description : `IAAMO the active state of the MemManage exception `FTSSS 3990 #define M33_SHCSR_MEMFAULTACT_RESET _u(0x0) 3991 #define M33_SHCSR_MEMFAULTACT_BITS _u(0x00000001) 3992 #define M33_SHCSR_MEMFAULTACT_MSB _u(0) 3993 #define M33_SHCSR_MEMFAULTACT_LSB _u(0) 3994 #define M33_SHCSR_MEMFAULTACT_ACCESS "RW" 3995 // ============================================================================= 3996 // Register : M33_CFSR 3997 // Description : Contains the three Configurable Fault Status Registers. 3998 // 3999 // 31:16 UFSR: Provides information on UsageFault exceptions 4000 // 4001 // 15:8 BFSR: Provides information on BusFault exceptions 4002 // 4003 // 7:0 MMFSR: Provides information on MemManage exceptions 4004 #define M33_CFSR_OFFSET _u(0x0000ed28) 4005 #define M33_CFSR_BITS _u(0x031fbfff) 4006 #define M33_CFSR_RESET _u(0x00000000) 4007 // ----------------------------------------------------------------------------- 4008 // Field : M33_CFSR_UFSR_DIVBYZERO 4009 // Description : Sticky flag indicating whether an integer division by zero 4010 // error has occurred 4011 #define M33_CFSR_UFSR_DIVBYZERO_RESET _u(0x0) 4012 #define M33_CFSR_UFSR_DIVBYZERO_BITS _u(0x02000000) 4013 #define M33_CFSR_UFSR_DIVBYZERO_MSB _u(25) 4014 #define M33_CFSR_UFSR_DIVBYZERO_LSB _u(25) 4015 #define M33_CFSR_UFSR_DIVBYZERO_ACCESS "RW" 4016 // ----------------------------------------------------------------------------- 4017 // Field : M33_CFSR_UFSR_UNALIGNED 4018 // Description : Sticky flag indicating whether an unaligned access error has 4019 // occurred 4020 #define M33_CFSR_UFSR_UNALIGNED_RESET _u(0x0) 4021 #define M33_CFSR_UFSR_UNALIGNED_BITS _u(0x01000000) 4022 #define M33_CFSR_UFSR_UNALIGNED_MSB _u(24) 4023 #define M33_CFSR_UFSR_UNALIGNED_LSB _u(24) 4024 #define M33_CFSR_UFSR_UNALIGNED_ACCESS "RW" 4025 // ----------------------------------------------------------------------------- 4026 // Field : M33_CFSR_UFSR_STKOF 4027 // Description : Sticky flag indicating whether a stack overflow error has 4028 // occurred 4029 #define M33_CFSR_UFSR_STKOF_RESET _u(0x0) 4030 #define M33_CFSR_UFSR_STKOF_BITS _u(0x00100000) 4031 #define M33_CFSR_UFSR_STKOF_MSB _u(20) 4032 #define M33_CFSR_UFSR_STKOF_LSB _u(20) 4033 #define M33_CFSR_UFSR_STKOF_ACCESS "RW" 4034 // ----------------------------------------------------------------------------- 4035 // Field : M33_CFSR_UFSR_NOCP 4036 // Description : Sticky flag indicating whether a coprocessor disabled or not 4037 // present error has occurred 4038 #define M33_CFSR_UFSR_NOCP_RESET _u(0x0) 4039 #define M33_CFSR_UFSR_NOCP_BITS _u(0x00080000) 4040 #define M33_CFSR_UFSR_NOCP_MSB _u(19) 4041 #define M33_CFSR_UFSR_NOCP_LSB _u(19) 4042 #define M33_CFSR_UFSR_NOCP_ACCESS "RW" 4043 // ----------------------------------------------------------------------------- 4044 // Field : M33_CFSR_UFSR_INVPC 4045 // Description : Sticky flag indicating whether an integrity check error has 4046 // occurred 4047 #define M33_CFSR_UFSR_INVPC_RESET _u(0x0) 4048 #define M33_CFSR_UFSR_INVPC_BITS _u(0x00040000) 4049 #define M33_CFSR_UFSR_INVPC_MSB _u(18) 4050 #define M33_CFSR_UFSR_INVPC_LSB _u(18) 4051 #define M33_CFSR_UFSR_INVPC_ACCESS "RW" 4052 // ----------------------------------------------------------------------------- 4053 // Field : M33_CFSR_UFSR_INVSTATE 4054 // Description : Sticky flag indicating whether an EPSR.T or EPSR.IT validity 4055 // error has occurred 4056 #define M33_CFSR_UFSR_INVSTATE_RESET _u(0x0) 4057 #define M33_CFSR_UFSR_INVSTATE_BITS _u(0x00020000) 4058 #define M33_CFSR_UFSR_INVSTATE_MSB _u(17) 4059 #define M33_CFSR_UFSR_INVSTATE_LSB _u(17) 4060 #define M33_CFSR_UFSR_INVSTATE_ACCESS "RW" 4061 // ----------------------------------------------------------------------------- 4062 // Field : M33_CFSR_UFSR_UNDEFINSTR 4063 // Description : Sticky flag indicating whether an undefined instruction error 4064 // has occurred 4065 #define M33_CFSR_UFSR_UNDEFINSTR_RESET _u(0x0) 4066 #define M33_CFSR_UFSR_UNDEFINSTR_BITS _u(0x00010000) 4067 #define M33_CFSR_UFSR_UNDEFINSTR_MSB _u(16) 4068 #define M33_CFSR_UFSR_UNDEFINSTR_LSB _u(16) 4069 #define M33_CFSR_UFSR_UNDEFINSTR_ACCESS "RW" 4070 // ----------------------------------------------------------------------------- 4071 // Field : M33_CFSR_BFSR_BFARVALID 4072 // Description : Indicates validity of the contents of the BFAR register 4073 #define M33_CFSR_BFSR_BFARVALID_RESET _u(0x0) 4074 #define M33_CFSR_BFSR_BFARVALID_BITS _u(0x00008000) 4075 #define M33_CFSR_BFSR_BFARVALID_MSB _u(15) 4076 #define M33_CFSR_BFSR_BFARVALID_LSB _u(15) 4077 #define M33_CFSR_BFSR_BFARVALID_ACCESS "RW" 4078 // ----------------------------------------------------------------------------- 4079 // Field : M33_CFSR_BFSR_LSPERR 4080 // Description : Records whether a BusFault occurred during FP lazy state 4081 // preservation 4082 #define M33_CFSR_BFSR_LSPERR_RESET _u(0x0) 4083 #define M33_CFSR_BFSR_LSPERR_BITS _u(0x00002000) 4084 #define M33_CFSR_BFSR_LSPERR_MSB _u(13) 4085 #define M33_CFSR_BFSR_LSPERR_LSB _u(13) 4086 #define M33_CFSR_BFSR_LSPERR_ACCESS "RW" 4087 // ----------------------------------------------------------------------------- 4088 // Field : M33_CFSR_BFSR_STKERR 4089 // Description : Records whether a derived BusFault occurred during exception 4090 // entry stacking 4091 #define M33_CFSR_BFSR_STKERR_RESET _u(0x0) 4092 #define M33_CFSR_BFSR_STKERR_BITS _u(0x00001000) 4093 #define M33_CFSR_BFSR_STKERR_MSB _u(12) 4094 #define M33_CFSR_BFSR_STKERR_LSB _u(12) 4095 #define M33_CFSR_BFSR_STKERR_ACCESS "RW" 4096 // ----------------------------------------------------------------------------- 4097 // Field : M33_CFSR_BFSR_UNSTKERR 4098 // Description : Records whether a derived BusFault occurred during exception 4099 // return unstacking 4100 #define M33_CFSR_BFSR_UNSTKERR_RESET _u(0x0) 4101 #define M33_CFSR_BFSR_UNSTKERR_BITS _u(0x00000800) 4102 #define M33_CFSR_BFSR_UNSTKERR_MSB _u(11) 4103 #define M33_CFSR_BFSR_UNSTKERR_LSB _u(11) 4104 #define M33_CFSR_BFSR_UNSTKERR_ACCESS "RW" 4105 // ----------------------------------------------------------------------------- 4106 // Field : M33_CFSR_BFSR_IMPRECISERR 4107 // Description : Records whether an imprecise data access error has occurred 4108 #define M33_CFSR_BFSR_IMPRECISERR_RESET _u(0x0) 4109 #define M33_CFSR_BFSR_IMPRECISERR_BITS _u(0x00000400) 4110 #define M33_CFSR_BFSR_IMPRECISERR_MSB _u(10) 4111 #define M33_CFSR_BFSR_IMPRECISERR_LSB _u(10) 4112 #define M33_CFSR_BFSR_IMPRECISERR_ACCESS "RW" 4113 // ----------------------------------------------------------------------------- 4114 // Field : M33_CFSR_BFSR_PRECISERR 4115 // Description : Records whether a precise data access error has occurred 4116 #define M33_CFSR_BFSR_PRECISERR_RESET _u(0x0) 4117 #define M33_CFSR_BFSR_PRECISERR_BITS _u(0x00000200) 4118 #define M33_CFSR_BFSR_PRECISERR_MSB _u(9) 4119 #define M33_CFSR_BFSR_PRECISERR_LSB _u(9) 4120 #define M33_CFSR_BFSR_PRECISERR_ACCESS "RW" 4121 // ----------------------------------------------------------------------------- 4122 // Field : M33_CFSR_BFSR_IBUSERR 4123 // Description : Records whether a BusFault on an instruction prefetch has 4124 // occurred 4125 #define M33_CFSR_BFSR_IBUSERR_RESET _u(0x0) 4126 #define M33_CFSR_BFSR_IBUSERR_BITS _u(0x00000100) 4127 #define M33_CFSR_BFSR_IBUSERR_MSB _u(8) 4128 #define M33_CFSR_BFSR_IBUSERR_LSB _u(8) 4129 #define M33_CFSR_BFSR_IBUSERR_ACCESS "RW" 4130 // ----------------------------------------------------------------------------- 4131 // Field : M33_CFSR_MMFSR 4132 // Description : Provides information on MemManage exceptions 4133 #define M33_CFSR_MMFSR_RESET _u(0x00) 4134 #define M33_CFSR_MMFSR_BITS _u(0x000000ff) 4135 #define M33_CFSR_MMFSR_MSB _u(7) 4136 #define M33_CFSR_MMFSR_LSB _u(0) 4137 #define M33_CFSR_MMFSR_ACCESS "RW" 4138 // ============================================================================= 4139 // Register : M33_HFSR 4140 // Description : Shows the cause of any HardFaults 4141 #define M33_HFSR_OFFSET _u(0x0000ed2c) 4142 #define M33_HFSR_BITS _u(0xc0000002) 4143 #define M33_HFSR_RESET _u(0x00000000) 4144 // ----------------------------------------------------------------------------- 4145 // Field : M33_HFSR_DEBUGEVT 4146 // Description : Indicates when a Debug event has occurred 4147 #define M33_HFSR_DEBUGEVT_RESET _u(0x0) 4148 #define M33_HFSR_DEBUGEVT_BITS _u(0x80000000) 4149 #define M33_HFSR_DEBUGEVT_MSB _u(31) 4150 #define M33_HFSR_DEBUGEVT_LSB _u(31) 4151 #define M33_HFSR_DEBUGEVT_ACCESS "RW" 4152 // ----------------------------------------------------------------------------- 4153 // Field : M33_HFSR_FORCED 4154 // Description : Indicates that a fault with configurable priority has been 4155 // escalated to a HardFault exception, because it could not be 4156 // made active, because of priority, or because it was disabled 4157 #define M33_HFSR_FORCED_RESET _u(0x0) 4158 #define M33_HFSR_FORCED_BITS _u(0x40000000) 4159 #define M33_HFSR_FORCED_MSB _u(30) 4160 #define M33_HFSR_FORCED_LSB _u(30) 4161 #define M33_HFSR_FORCED_ACCESS "RW" 4162 // ----------------------------------------------------------------------------- 4163 // Field : M33_HFSR_VECTTBL 4164 // Description : Indicates when a fault has occurred because of a vector table 4165 // read error on exception processing 4166 #define M33_HFSR_VECTTBL_RESET _u(0x0) 4167 #define M33_HFSR_VECTTBL_BITS _u(0x00000002) 4168 #define M33_HFSR_VECTTBL_MSB _u(1) 4169 #define M33_HFSR_VECTTBL_LSB _u(1) 4170 #define M33_HFSR_VECTTBL_ACCESS "RW" 4171 // ============================================================================= 4172 // Register : M33_DFSR 4173 // Description : Shows which debug event occurred 4174 #define M33_DFSR_OFFSET _u(0x0000ed30) 4175 #define M33_DFSR_BITS _u(0x0000001f) 4176 #define M33_DFSR_RESET _u(0x00000000) 4177 // ----------------------------------------------------------------------------- 4178 // Field : M33_DFSR_EXTERNAL 4179 // Description : Sticky flag indicating whether an External debug request debug 4180 // event has occurred 4181 #define M33_DFSR_EXTERNAL_RESET _u(0x0) 4182 #define M33_DFSR_EXTERNAL_BITS _u(0x00000010) 4183 #define M33_DFSR_EXTERNAL_MSB _u(4) 4184 #define M33_DFSR_EXTERNAL_LSB _u(4) 4185 #define M33_DFSR_EXTERNAL_ACCESS "RW" 4186 // ----------------------------------------------------------------------------- 4187 // Field : M33_DFSR_VCATCH 4188 // Description : Sticky flag indicating whether a Vector catch debug event has 4189 // occurred 4190 #define M33_DFSR_VCATCH_RESET _u(0x0) 4191 #define M33_DFSR_VCATCH_BITS _u(0x00000008) 4192 #define M33_DFSR_VCATCH_MSB _u(3) 4193 #define M33_DFSR_VCATCH_LSB _u(3) 4194 #define M33_DFSR_VCATCH_ACCESS "RW" 4195 // ----------------------------------------------------------------------------- 4196 // Field : M33_DFSR_DWTTRAP 4197 // Description : Sticky flag indicating whether a Watchpoint debug event has 4198 // occurred 4199 #define M33_DFSR_DWTTRAP_RESET _u(0x0) 4200 #define M33_DFSR_DWTTRAP_BITS _u(0x00000004) 4201 #define M33_DFSR_DWTTRAP_MSB _u(2) 4202 #define M33_DFSR_DWTTRAP_LSB _u(2) 4203 #define M33_DFSR_DWTTRAP_ACCESS "RW" 4204 // ----------------------------------------------------------------------------- 4205 // Field : M33_DFSR_BKPT 4206 // Description : Sticky flag indicating whether a Breakpoint debug event has 4207 // occurred 4208 #define M33_DFSR_BKPT_RESET _u(0x0) 4209 #define M33_DFSR_BKPT_BITS _u(0x00000002) 4210 #define M33_DFSR_BKPT_MSB _u(1) 4211 #define M33_DFSR_BKPT_LSB _u(1) 4212 #define M33_DFSR_BKPT_ACCESS "RW" 4213 // ----------------------------------------------------------------------------- 4214 // Field : M33_DFSR_HALTED 4215 // Description : Sticky flag indicating that a Halt request debug event or Step 4216 // debug event has occurred 4217 #define M33_DFSR_HALTED_RESET _u(0x0) 4218 #define M33_DFSR_HALTED_BITS _u(0x00000001) 4219 #define M33_DFSR_HALTED_MSB _u(0) 4220 #define M33_DFSR_HALTED_LSB _u(0) 4221 #define M33_DFSR_HALTED_ACCESS "RW" 4222 // ============================================================================= 4223 // Register : M33_MMFAR 4224 // Description : Shows the address of the memory location that caused an MPU 4225 // fault 4226 #define M33_MMFAR_OFFSET _u(0x0000ed34) 4227 #define M33_MMFAR_BITS _u(0xffffffff) 4228 #define M33_MMFAR_RESET _u(0x00000000) 4229 // ----------------------------------------------------------------------------- 4230 // Field : M33_MMFAR_ADDRESS 4231 // Description : This register is updated with the address of a location that 4232 // produced a MemManage fault. The MMFSR shows the cause of the 4233 // fault, and whether this field is valid. This field is valid 4234 // only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN 4235 #define M33_MMFAR_ADDRESS_RESET _u(0x00000000) 4236 #define M33_MMFAR_ADDRESS_BITS _u(0xffffffff) 4237 #define M33_MMFAR_ADDRESS_MSB _u(31) 4238 #define M33_MMFAR_ADDRESS_LSB _u(0) 4239 #define M33_MMFAR_ADDRESS_ACCESS "RW" 4240 // ============================================================================= 4241 // Register : M33_BFAR 4242 // Description : Shows the address associated with a precise data access 4243 // BusFault 4244 #define M33_BFAR_OFFSET _u(0x0000ed38) 4245 #define M33_BFAR_BITS _u(0xffffffff) 4246 #define M33_BFAR_RESET _u(0x00000000) 4247 // ----------------------------------------------------------------------------- 4248 // Field : M33_BFAR_ADDRESS 4249 // Description : This register is updated with the address of a location that 4250 // produced a BusFault. The BFSR shows the reason for the fault. 4251 // This field is valid only when BFSR.BFARVALID is set, otherwise 4252 // it is UNKNOWN 4253 #define M33_BFAR_ADDRESS_RESET _u(0x00000000) 4254 #define M33_BFAR_ADDRESS_BITS _u(0xffffffff) 4255 #define M33_BFAR_ADDRESS_MSB _u(31) 4256 #define M33_BFAR_ADDRESS_LSB _u(0) 4257 #define M33_BFAR_ADDRESS_ACCESS "RW" 4258 // ============================================================================= 4259 // Register : M33_ID_PFR0 4260 // Description : Gives top-level information about the instruction set supported 4261 // by the PE 4262 #define M33_ID_PFR0_OFFSET _u(0x0000ed40) 4263 #define M33_ID_PFR0_BITS _u(0x000000ff) 4264 #define M33_ID_PFR0_RESET _u(0x00000030) 4265 // ----------------------------------------------------------------------------- 4266 // Field : M33_ID_PFR0_STATE1 4267 // Description : T32 instruction set support 4268 #define M33_ID_PFR0_STATE1_RESET _u(0x3) 4269 #define M33_ID_PFR0_STATE1_BITS _u(0x000000f0) 4270 #define M33_ID_PFR0_STATE1_MSB _u(7) 4271 #define M33_ID_PFR0_STATE1_LSB _u(4) 4272 #define M33_ID_PFR0_STATE1_ACCESS "RO" 4273 // ----------------------------------------------------------------------------- 4274 // Field : M33_ID_PFR0_STATE0 4275 // Description : A32 instruction set support 4276 #define M33_ID_PFR0_STATE0_RESET _u(0x0) 4277 #define M33_ID_PFR0_STATE0_BITS _u(0x0000000f) 4278 #define M33_ID_PFR0_STATE0_MSB _u(3) 4279 #define M33_ID_PFR0_STATE0_LSB _u(0) 4280 #define M33_ID_PFR0_STATE0_ACCESS "RO" 4281 // ============================================================================= 4282 // Register : M33_ID_PFR1 4283 // Description : Gives information about the programmers' model and Extensions 4284 // support 4285 #define M33_ID_PFR1_OFFSET _u(0x0000ed44) 4286 #define M33_ID_PFR1_BITS _u(0x00000ff0) 4287 #define M33_ID_PFR1_RESET _u(0x00000520) 4288 // ----------------------------------------------------------------------------- 4289 // Field : M33_ID_PFR1_MPROGMOD 4290 // Description : Identifies support for the M-Profile programmers' model support 4291 #define M33_ID_PFR1_MPROGMOD_RESET _u(0x5) 4292 #define M33_ID_PFR1_MPROGMOD_BITS _u(0x00000f00) 4293 #define M33_ID_PFR1_MPROGMOD_MSB _u(11) 4294 #define M33_ID_PFR1_MPROGMOD_LSB _u(8) 4295 #define M33_ID_PFR1_MPROGMOD_ACCESS "RO" 4296 // ----------------------------------------------------------------------------- 4297 // Field : M33_ID_PFR1_SECURITY 4298 // Description : Identifies whether the Security Extension is implemented 4299 #define M33_ID_PFR1_SECURITY_RESET _u(0x2) 4300 #define M33_ID_PFR1_SECURITY_BITS _u(0x000000f0) 4301 #define M33_ID_PFR1_SECURITY_MSB _u(7) 4302 #define M33_ID_PFR1_SECURITY_LSB _u(4) 4303 #define M33_ID_PFR1_SECURITY_ACCESS "RO" 4304 // ============================================================================= 4305 // Register : M33_ID_DFR0 4306 // Description : Provides top level information about the debug system 4307 #define M33_ID_DFR0_OFFSET _u(0x0000ed48) 4308 #define M33_ID_DFR0_BITS _u(0x00f00000) 4309 #define M33_ID_DFR0_RESET _u(0x00200000) 4310 // ----------------------------------------------------------------------------- 4311 // Field : M33_ID_DFR0_MPROFDBG 4312 // Description : Indicates the supported M-profile debug architecture 4313 #define M33_ID_DFR0_MPROFDBG_RESET _u(0x2) 4314 #define M33_ID_DFR0_MPROFDBG_BITS _u(0x00f00000) 4315 #define M33_ID_DFR0_MPROFDBG_MSB _u(23) 4316 #define M33_ID_DFR0_MPROFDBG_LSB _u(20) 4317 #define M33_ID_DFR0_MPROFDBG_ACCESS "RO" 4318 // ============================================================================= 4319 // Register : M33_ID_AFR0 4320 // Description : Provides information about the IMPLEMENTATION DEFINED features 4321 // of the PE 4322 #define M33_ID_AFR0_OFFSET _u(0x0000ed4c) 4323 #define M33_ID_AFR0_BITS _u(0x0000ffff) 4324 #define M33_ID_AFR0_RESET _u(0x00000000) 4325 // ----------------------------------------------------------------------------- 4326 // Field : M33_ID_AFR0_IMPDEF3 4327 // Description : IMPLEMENTATION DEFINED meaning 4328 #define M33_ID_AFR0_IMPDEF3_RESET _u(0x0) 4329 #define M33_ID_AFR0_IMPDEF3_BITS _u(0x0000f000) 4330 #define M33_ID_AFR0_IMPDEF3_MSB _u(15) 4331 #define M33_ID_AFR0_IMPDEF3_LSB _u(12) 4332 #define M33_ID_AFR0_IMPDEF3_ACCESS "RO" 4333 // ----------------------------------------------------------------------------- 4334 // Field : M33_ID_AFR0_IMPDEF2 4335 // Description : IMPLEMENTATION DEFINED meaning 4336 #define M33_ID_AFR0_IMPDEF2_RESET _u(0x0) 4337 #define M33_ID_AFR0_IMPDEF2_BITS _u(0x00000f00) 4338 #define M33_ID_AFR0_IMPDEF2_MSB _u(11) 4339 #define M33_ID_AFR0_IMPDEF2_LSB _u(8) 4340 #define M33_ID_AFR0_IMPDEF2_ACCESS "RO" 4341 // ----------------------------------------------------------------------------- 4342 // Field : M33_ID_AFR0_IMPDEF1 4343 // Description : IMPLEMENTATION DEFINED meaning 4344 #define M33_ID_AFR0_IMPDEF1_RESET _u(0x0) 4345 #define M33_ID_AFR0_IMPDEF1_BITS _u(0x000000f0) 4346 #define M33_ID_AFR0_IMPDEF1_MSB _u(7) 4347 #define M33_ID_AFR0_IMPDEF1_LSB _u(4) 4348 #define M33_ID_AFR0_IMPDEF1_ACCESS "RO" 4349 // ----------------------------------------------------------------------------- 4350 // Field : M33_ID_AFR0_IMPDEF0 4351 // Description : IMPLEMENTATION DEFINED meaning 4352 #define M33_ID_AFR0_IMPDEF0_RESET _u(0x0) 4353 #define M33_ID_AFR0_IMPDEF0_BITS _u(0x0000000f) 4354 #define M33_ID_AFR0_IMPDEF0_MSB _u(3) 4355 #define M33_ID_AFR0_IMPDEF0_LSB _u(0) 4356 #define M33_ID_AFR0_IMPDEF0_ACCESS "RO" 4357 // ============================================================================= 4358 // Register : M33_ID_MMFR0 4359 // Description : Provides information about the implemented memory model and 4360 // memory management support 4361 #define M33_ID_MMFR0_OFFSET _u(0x0000ed50) 4362 #define M33_ID_MMFR0_BITS _u(0x00fffff0) 4363 #define M33_ID_MMFR0_RESET _u(0x00101f40) 4364 // ----------------------------------------------------------------------------- 4365 // Field : M33_ID_MMFR0_AUXREG 4366 // Description : Indicates support for Auxiliary Control Registers 4367 #define M33_ID_MMFR0_AUXREG_RESET _u(0x1) 4368 #define M33_ID_MMFR0_AUXREG_BITS _u(0x00f00000) 4369 #define M33_ID_MMFR0_AUXREG_MSB _u(23) 4370 #define M33_ID_MMFR0_AUXREG_LSB _u(20) 4371 #define M33_ID_MMFR0_AUXREG_ACCESS "RO" 4372 // ----------------------------------------------------------------------------- 4373 // Field : M33_ID_MMFR0_TCM 4374 // Description : Indicates support for tightly coupled memories (TCMs) 4375 #define M33_ID_MMFR0_TCM_RESET _u(0x0) 4376 #define M33_ID_MMFR0_TCM_BITS _u(0x000f0000) 4377 #define M33_ID_MMFR0_TCM_MSB _u(19) 4378 #define M33_ID_MMFR0_TCM_LSB _u(16) 4379 #define M33_ID_MMFR0_TCM_ACCESS "RO" 4380 // ----------------------------------------------------------------------------- 4381 // Field : M33_ID_MMFR0_SHARELVL 4382 // Description : Indicates the number of shareability levels implemented 4383 #define M33_ID_MMFR0_SHARELVL_RESET _u(0x1) 4384 #define M33_ID_MMFR0_SHARELVL_BITS _u(0x0000f000) 4385 #define M33_ID_MMFR0_SHARELVL_MSB _u(15) 4386 #define M33_ID_MMFR0_SHARELVL_LSB _u(12) 4387 #define M33_ID_MMFR0_SHARELVL_ACCESS "RO" 4388 // ----------------------------------------------------------------------------- 4389 // Field : M33_ID_MMFR0_OUTERSHR 4390 // Description : Indicates the outermost shareability domain implemented 4391 #define M33_ID_MMFR0_OUTERSHR_RESET _u(0xf) 4392 #define M33_ID_MMFR0_OUTERSHR_BITS _u(0x00000f00) 4393 #define M33_ID_MMFR0_OUTERSHR_MSB _u(11) 4394 #define M33_ID_MMFR0_OUTERSHR_LSB _u(8) 4395 #define M33_ID_MMFR0_OUTERSHR_ACCESS "RO" 4396 // ----------------------------------------------------------------------------- 4397 // Field : M33_ID_MMFR0_PMSA 4398 // Description : Indicates support for the protected memory system architecture 4399 // (PMSA) 4400 #define M33_ID_MMFR0_PMSA_RESET _u(0x4) 4401 #define M33_ID_MMFR0_PMSA_BITS _u(0x000000f0) 4402 #define M33_ID_MMFR0_PMSA_MSB _u(7) 4403 #define M33_ID_MMFR0_PMSA_LSB _u(4) 4404 #define M33_ID_MMFR0_PMSA_ACCESS "RO" 4405 // ============================================================================= 4406 // Register : M33_ID_MMFR1 4407 // Description : Provides information about the implemented memory model and 4408 // memory management support 4409 #define M33_ID_MMFR1_OFFSET _u(0x0000ed54) 4410 #define M33_ID_MMFR1_BITS _u(0x00000000) 4411 #define M33_ID_MMFR1_RESET _u(0x00000000) 4412 #define M33_ID_MMFR1_MSB _u(31) 4413 #define M33_ID_MMFR1_LSB _u(0) 4414 #define M33_ID_MMFR1_ACCESS "RW" 4415 // ============================================================================= 4416 // Register : M33_ID_MMFR2 4417 // Description : Provides information about the implemented memory model and 4418 // memory management support 4419 #define M33_ID_MMFR2_OFFSET _u(0x0000ed58) 4420 #define M33_ID_MMFR2_BITS _u(0x0f000000) 4421 #define M33_ID_MMFR2_RESET _u(0x01000000) 4422 // ----------------------------------------------------------------------------- 4423 // Field : M33_ID_MMFR2_WFISTALL 4424 // Description : Indicates the support for Wait For Interrupt (WFI) stalling 4425 #define M33_ID_MMFR2_WFISTALL_RESET _u(0x1) 4426 #define M33_ID_MMFR2_WFISTALL_BITS _u(0x0f000000) 4427 #define M33_ID_MMFR2_WFISTALL_MSB _u(27) 4428 #define M33_ID_MMFR2_WFISTALL_LSB _u(24) 4429 #define M33_ID_MMFR2_WFISTALL_ACCESS "RO" 4430 // ============================================================================= 4431 // Register : M33_ID_MMFR3 4432 // Description : Provides information about the implemented memory model and 4433 // memory management support 4434 #define M33_ID_MMFR3_OFFSET _u(0x0000ed5c) 4435 #define M33_ID_MMFR3_BITS _u(0x00000fff) 4436 #define M33_ID_MMFR3_RESET _u(0x00000000) 4437 // ----------------------------------------------------------------------------- 4438 // Field : M33_ID_MMFR3_BPMAINT 4439 // Description : Indicates the supported branch predictor maintenance 4440 #define M33_ID_MMFR3_BPMAINT_RESET _u(0x0) 4441 #define M33_ID_MMFR3_BPMAINT_BITS _u(0x00000f00) 4442 #define M33_ID_MMFR3_BPMAINT_MSB _u(11) 4443 #define M33_ID_MMFR3_BPMAINT_LSB _u(8) 4444 #define M33_ID_MMFR3_BPMAINT_ACCESS "RO" 4445 // ----------------------------------------------------------------------------- 4446 // Field : M33_ID_MMFR3_CMAINTSW 4447 // Description : Indicates the supported cache maintenance operations by set/way 4448 #define M33_ID_MMFR3_CMAINTSW_RESET _u(0x0) 4449 #define M33_ID_MMFR3_CMAINTSW_BITS _u(0x000000f0) 4450 #define M33_ID_MMFR3_CMAINTSW_MSB _u(7) 4451 #define M33_ID_MMFR3_CMAINTSW_LSB _u(4) 4452 #define M33_ID_MMFR3_CMAINTSW_ACCESS "RO" 4453 // ----------------------------------------------------------------------------- 4454 // Field : M33_ID_MMFR3_CMAINTVA 4455 // Description : Indicates the supported cache maintenance operations by address 4456 #define M33_ID_MMFR3_CMAINTVA_RESET _u(0x0) 4457 #define M33_ID_MMFR3_CMAINTVA_BITS _u(0x0000000f) 4458 #define M33_ID_MMFR3_CMAINTVA_MSB _u(3) 4459 #define M33_ID_MMFR3_CMAINTVA_LSB _u(0) 4460 #define M33_ID_MMFR3_CMAINTVA_ACCESS "RO" 4461 // ============================================================================= 4462 // Register : M33_ID_ISAR0 4463 // Description : Provides information about the instruction set implemented by 4464 // the PE 4465 #define M33_ID_ISAR0_OFFSET _u(0x0000ed60) 4466 #define M33_ID_ISAR0_BITS _u(0x0ffffff0) 4467 #define M33_ID_ISAR0_RESET _u(0x08092300) 4468 // ----------------------------------------------------------------------------- 4469 // Field : M33_ID_ISAR0_DIVIDE 4470 // Description : Indicates the supported Divide instructions 4471 #define M33_ID_ISAR0_DIVIDE_RESET _u(0x8) 4472 #define M33_ID_ISAR0_DIVIDE_BITS _u(0x0f000000) 4473 #define M33_ID_ISAR0_DIVIDE_MSB _u(27) 4474 #define M33_ID_ISAR0_DIVIDE_LSB _u(24) 4475 #define M33_ID_ISAR0_DIVIDE_ACCESS "RO" 4476 // ----------------------------------------------------------------------------- 4477 // Field : M33_ID_ISAR0_DEBUG 4478 // Description : Indicates the implemented Debug instructions 4479 #define M33_ID_ISAR0_DEBUG_RESET _u(0x0) 4480 #define M33_ID_ISAR0_DEBUG_BITS _u(0x00f00000) 4481 #define M33_ID_ISAR0_DEBUG_MSB _u(23) 4482 #define M33_ID_ISAR0_DEBUG_LSB _u(20) 4483 #define M33_ID_ISAR0_DEBUG_ACCESS "RO" 4484 // ----------------------------------------------------------------------------- 4485 // Field : M33_ID_ISAR0_COPROC 4486 // Description : Indicates the supported Coprocessor instructions 4487 #define M33_ID_ISAR0_COPROC_RESET _u(0x9) 4488 #define M33_ID_ISAR0_COPROC_BITS _u(0x000f0000) 4489 #define M33_ID_ISAR0_COPROC_MSB _u(19) 4490 #define M33_ID_ISAR0_COPROC_LSB _u(16) 4491 #define M33_ID_ISAR0_COPROC_ACCESS "RO" 4492 // ----------------------------------------------------------------------------- 4493 // Field : M33_ID_ISAR0_CMPBRANCH 4494 // Description : Indicates the supported combined Compare and Branch 4495 // instructions 4496 #define M33_ID_ISAR0_CMPBRANCH_RESET _u(0x2) 4497 #define M33_ID_ISAR0_CMPBRANCH_BITS _u(0x0000f000) 4498 #define M33_ID_ISAR0_CMPBRANCH_MSB _u(15) 4499 #define M33_ID_ISAR0_CMPBRANCH_LSB _u(12) 4500 #define M33_ID_ISAR0_CMPBRANCH_ACCESS "RO" 4501 // ----------------------------------------------------------------------------- 4502 // Field : M33_ID_ISAR0_BITFIELD 4503 // Description : Indicates the supported bit field instructions 4504 #define M33_ID_ISAR0_BITFIELD_RESET _u(0x3) 4505 #define M33_ID_ISAR0_BITFIELD_BITS _u(0x00000f00) 4506 #define M33_ID_ISAR0_BITFIELD_MSB _u(11) 4507 #define M33_ID_ISAR0_BITFIELD_LSB _u(8) 4508 #define M33_ID_ISAR0_BITFIELD_ACCESS "RO" 4509 // ----------------------------------------------------------------------------- 4510 // Field : M33_ID_ISAR0_BITCOUNT 4511 // Description : Indicates the supported bit count instructions 4512 #define M33_ID_ISAR0_BITCOUNT_RESET _u(0x0) 4513 #define M33_ID_ISAR0_BITCOUNT_BITS _u(0x000000f0) 4514 #define M33_ID_ISAR0_BITCOUNT_MSB _u(7) 4515 #define M33_ID_ISAR0_BITCOUNT_LSB _u(4) 4516 #define M33_ID_ISAR0_BITCOUNT_ACCESS "RO" 4517 // ============================================================================= 4518 // Register : M33_ID_ISAR1 4519 // Description : Provides information about the instruction set implemented by 4520 // the PE 4521 #define M33_ID_ISAR1_OFFSET _u(0x0000ed64) 4522 #define M33_ID_ISAR1_BITS _u(0x0ffff000) 4523 #define M33_ID_ISAR1_RESET _u(0x05725000) 4524 // ----------------------------------------------------------------------------- 4525 // Field : M33_ID_ISAR1_INTERWORK 4526 // Description : Indicates the implemented Interworking instructions 4527 #define M33_ID_ISAR1_INTERWORK_RESET _u(0x5) 4528 #define M33_ID_ISAR1_INTERWORK_BITS _u(0x0f000000) 4529 #define M33_ID_ISAR1_INTERWORK_MSB _u(27) 4530 #define M33_ID_ISAR1_INTERWORK_LSB _u(24) 4531 #define M33_ID_ISAR1_INTERWORK_ACCESS "RO" 4532 // ----------------------------------------------------------------------------- 4533 // Field : M33_ID_ISAR1_IMMEDIATE 4534 // Description : Indicates the implemented for data-processing instructions with 4535 // long immediates 4536 #define M33_ID_ISAR1_IMMEDIATE_RESET _u(0x7) 4537 #define M33_ID_ISAR1_IMMEDIATE_BITS _u(0x00f00000) 4538 #define M33_ID_ISAR1_IMMEDIATE_MSB _u(23) 4539 #define M33_ID_ISAR1_IMMEDIATE_LSB _u(20) 4540 #define M33_ID_ISAR1_IMMEDIATE_ACCESS "RO" 4541 // ----------------------------------------------------------------------------- 4542 // Field : M33_ID_ISAR1_IFTHEN 4543 // Description : Indicates the implemented If-Then instructions 4544 #define M33_ID_ISAR1_IFTHEN_RESET _u(0x2) 4545 #define M33_ID_ISAR1_IFTHEN_BITS _u(0x000f0000) 4546 #define M33_ID_ISAR1_IFTHEN_MSB _u(19) 4547 #define M33_ID_ISAR1_IFTHEN_LSB _u(16) 4548 #define M33_ID_ISAR1_IFTHEN_ACCESS "RO" 4549 // ----------------------------------------------------------------------------- 4550 // Field : M33_ID_ISAR1_EXTEND 4551 // Description : Indicates the implemented Extend instructions 4552 #define M33_ID_ISAR1_EXTEND_RESET _u(0x5) 4553 #define M33_ID_ISAR1_EXTEND_BITS _u(0x0000f000) 4554 #define M33_ID_ISAR1_EXTEND_MSB _u(15) 4555 #define M33_ID_ISAR1_EXTEND_LSB _u(12) 4556 #define M33_ID_ISAR1_EXTEND_ACCESS "RO" 4557 // ============================================================================= 4558 // Register : M33_ID_ISAR2 4559 // Description : Provides information about the instruction set implemented by 4560 // the PE 4561 #define M33_ID_ISAR2_OFFSET _u(0x0000ed68) 4562 #define M33_ID_ISAR2_BITS _u(0xf0ffffff) 4563 #define M33_ID_ISAR2_RESET _u(0x30173426) 4564 // ----------------------------------------------------------------------------- 4565 // Field : M33_ID_ISAR2_REVERSAL 4566 // Description : Indicates the implemented Reversal instructions 4567 #define M33_ID_ISAR2_REVERSAL_RESET _u(0x3) 4568 #define M33_ID_ISAR2_REVERSAL_BITS _u(0xf0000000) 4569 #define M33_ID_ISAR2_REVERSAL_MSB _u(31) 4570 #define M33_ID_ISAR2_REVERSAL_LSB _u(28) 4571 #define M33_ID_ISAR2_REVERSAL_ACCESS "RO" 4572 // ----------------------------------------------------------------------------- 4573 // Field : M33_ID_ISAR2_MULTU 4574 // Description : Indicates the implemented advanced unsigned Multiply 4575 // instructions 4576 #define M33_ID_ISAR2_MULTU_RESET _u(0x1) 4577 #define M33_ID_ISAR2_MULTU_BITS _u(0x00f00000) 4578 #define M33_ID_ISAR2_MULTU_MSB _u(23) 4579 #define M33_ID_ISAR2_MULTU_LSB _u(20) 4580 #define M33_ID_ISAR2_MULTU_ACCESS "RO" 4581 // ----------------------------------------------------------------------------- 4582 // Field : M33_ID_ISAR2_MULTS 4583 // Description : Indicates the implemented advanced signed Multiply instructions 4584 #define M33_ID_ISAR2_MULTS_RESET _u(0x7) 4585 #define M33_ID_ISAR2_MULTS_BITS _u(0x000f0000) 4586 #define M33_ID_ISAR2_MULTS_MSB _u(19) 4587 #define M33_ID_ISAR2_MULTS_LSB _u(16) 4588 #define M33_ID_ISAR2_MULTS_ACCESS "RO" 4589 // ----------------------------------------------------------------------------- 4590 // Field : M33_ID_ISAR2_MULT 4591 // Description : Indicates the implemented additional Multiply instructions 4592 #define M33_ID_ISAR2_MULT_RESET _u(0x3) 4593 #define M33_ID_ISAR2_MULT_BITS _u(0x0000f000) 4594 #define M33_ID_ISAR2_MULT_MSB _u(15) 4595 #define M33_ID_ISAR2_MULT_LSB _u(12) 4596 #define M33_ID_ISAR2_MULT_ACCESS "RO" 4597 // ----------------------------------------------------------------------------- 4598 // Field : M33_ID_ISAR2_MULTIACCESSINT 4599 // Description : Indicates the support for interruptible multi-access 4600 // instructions 4601 #define M33_ID_ISAR2_MULTIACCESSINT_RESET _u(0x4) 4602 #define M33_ID_ISAR2_MULTIACCESSINT_BITS _u(0x00000f00) 4603 #define M33_ID_ISAR2_MULTIACCESSINT_MSB _u(11) 4604 #define M33_ID_ISAR2_MULTIACCESSINT_LSB _u(8) 4605 #define M33_ID_ISAR2_MULTIACCESSINT_ACCESS "RO" 4606 // ----------------------------------------------------------------------------- 4607 // Field : M33_ID_ISAR2_MEMHINT 4608 // Description : Indicates the implemented Memory Hint instructions 4609 #define M33_ID_ISAR2_MEMHINT_RESET _u(0x2) 4610 #define M33_ID_ISAR2_MEMHINT_BITS _u(0x000000f0) 4611 #define M33_ID_ISAR2_MEMHINT_MSB _u(7) 4612 #define M33_ID_ISAR2_MEMHINT_LSB _u(4) 4613 #define M33_ID_ISAR2_MEMHINT_ACCESS "RO" 4614 // ----------------------------------------------------------------------------- 4615 // Field : M33_ID_ISAR2_LOADSTORE 4616 // Description : Indicates the implemented additional load/store instructions 4617 #define M33_ID_ISAR2_LOADSTORE_RESET _u(0x6) 4618 #define M33_ID_ISAR2_LOADSTORE_BITS _u(0x0000000f) 4619 #define M33_ID_ISAR2_LOADSTORE_MSB _u(3) 4620 #define M33_ID_ISAR2_LOADSTORE_LSB _u(0) 4621 #define M33_ID_ISAR2_LOADSTORE_ACCESS "RO" 4622 // ============================================================================= 4623 // Register : M33_ID_ISAR3 4624 // Description : Provides information about the instruction set implemented by 4625 // the PE 4626 #define M33_ID_ISAR3_OFFSET _u(0x0000ed6c) 4627 #define M33_ID_ISAR3_BITS _u(0x0fffffff) 4628 #define M33_ID_ISAR3_RESET _u(0x07895729) 4629 // ----------------------------------------------------------------------------- 4630 // Field : M33_ID_ISAR3_TRUENOP 4631 // Description : Indicates the implemented true NOP instructions 4632 #define M33_ID_ISAR3_TRUENOP_RESET _u(0x7) 4633 #define M33_ID_ISAR3_TRUENOP_BITS _u(0x0f000000) 4634 #define M33_ID_ISAR3_TRUENOP_MSB _u(27) 4635 #define M33_ID_ISAR3_TRUENOP_LSB _u(24) 4636 #define M33_ID_ISAR3_TRUENOP_ACCESS "RO" 4637 // ----------------------------------------------------------------------------- 4638 // Field : M33_ID_ISAR3_T32COPY 4639 // Description : Indicates the support for T32 non flag-setting MOV instructions 4640 #define M33_ID_ISAR3_T32COPY_RESET _u(0x8) 4641 #define M33_ID_ISAR3_T32COPY_BITS _u(0x00f00000) 4642 #define M33_ID_ISAR3_T32COPY_MSB _u(23) 4643 #define M33_ID_ISAR3_T32COPY_LSB _u(20) 4644 #define M33_ID_ISAR3_T32COPY_ACCESS "RO" 4645 // ----------------------------------------------------------------------------- 4646 // Field : M33_ID_ISAR3_TABBRANCH 4647 // Description : Indicates the implemented Table Branch instructions 4648 #define M33_ID_ISAR3_TABBRANCH_RESET _u(0x9) 4649 #define M33_ID_ISAR3_TABBRANCH_BITS _u(0x000f0000) 4650 #define M33_ID_ISAR3_TABBRANCH_MSB _u(19) 4651 #define M33_ID_ISAR3_TABBRANCH_LSB _u(16) 4652 #define M33_ID_ISAR3_TABBRANCH_ACCESS "RO" 4653 // ----------------------------------------------------------------------------- 4654 // Field : M33_ID_ISAR3_SYNCHPRIM 4655 // Description : Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate 4656 // the implemented Synchronization Primitive instructions 4657 #define M33_ID_ISAR3_SYNCHPRIM_RESET _u(0x5) 4658 #define M33_ID_ISAR3_SYNCHPRIM_BITS _u(0x0000f000) 4659 #define M33_ID_ISAR3_SYNCHPRIM_MSB _u(15) 4660 #define M33_ID_ISAR3_SYNCHPRIM_LSB _u(12) 4661 #define M33_ID_ISAR3_SYNCHPRIM_ACCESS "RO" 4662 // ----------------------------------------------------------------------------- 4663 // Field : M33_ID_ISAR3_SVC 4664 // Description : Indicates the implemented SVC instructions 4665 #define M33_ID_ISAR3_SVC_RESET _u(0x7) 4666 #define M33_ID_ISAR3_SVC_BITS _u(0x00000f00) 4667 #define M33_ID_ISAR3_SVC_MSB _u(11) 4668 #define M33_ID_ISAR3_SVC_LSB _u(8) 4669 #define M33_ID_ISAR3_SVC_ACCESS "RO" 4670 // ----------------------------------------------------------------------------- 4671 // Field : M33_ID_ISAR3_SIMD 4672 // Description : Indicates the implemented SIMD instructions 4673 #define M33_ID_ISAR3_SIMD_RESET _u(0x2) 4674 #define M33_ID_ISAR3_SIMD_BITS _u(0x000000f0) 4675 #define M33_ID_ISAR3_SIMD_MSB _u(7) 4676 #define M33_ID_ISAR3_SIMD_LSB _u(4) 4677 #define M33_ID_ISAR3_SIMD_ACCESS "RO" 4678 // ----------------------------------------------------------------------------- 4679 // Field : M33_ID_ISAR3_SATURATE 4680 // Description : Indicates the implemented saturating instructions 4681 #define M33_ID_ISAR3_SATURATE_RESET _u(0x9) 4682 #define M33_ID_ISAR3_SATURATE_BITS _u(0x0000000f) 4683 #define M33_ID_ISAR3_SATURATE_MSB _u(3) 4684 #define M33_ID_ISAR3_SATURATE_LSB _u(0) 4685 #define M33_ID_ISAR3_SATURATE_ACCESS "RO" 4686 // ============================================================================= 4687 // Register : M33_ID_ISAR4 4688 // Description : Provides information about the instruction set implemented by 4689 // the PE 4690 #define M33_ID_ISAR4_OFFSET _u(0x0000ed70) 4691 #define M33_ID_ISAR4_BITS _u(0x0fff0fff) 4692 #define M33_ID_ISAR4_RESET _u(0x01310132) 4693 // ----------------------------------------------------------------------------- 4694 // Field : M33_ID_ISAR4_PSR_M 4695 // Description : Indicates the implemented M profile instructions to modify the 4696 // PSRs 4697 #define M33_ID_ISAR4_PSR_M_RESET _u(0x1) 4698 #define M33_ID_ISAR4_PSR_M_BITS _u(0x0f000000) 4699 #define M33_ID_ISAR4_PSR_M_MSB _u(27) 4700 #define M33_ID_ISAR4_PSR_M_LSB _u(24) 4701 #define M33_ID_ISAR4_PSR_M_ACCESS "RO" 4702 // ----------------------------------------------------------------------------- 4703 // Field : M33_ID_ISAR4_SYNCPRIM_FRAC 4704 // Description : Used in conjunction with ID_ISAR3.SynchPrim to indicate the 4705 // implemented Synchronization Primitive instructions 4706 #define M33_ID_ISAR4_SYNCPRIM_FRAC_RESET _u(0x3) 4707 #define M33_ID_ISAR4_SYNCPRIM_FRAC_BITS _u(0x00f00000) 4708 #define M33_ID_ISAR4_SYNCPRIM_FRAC_MSB _u(23) 4709 #define M33_ID_ISAR4_SYNCPRIM_FRAC_LSB _u(20) 4710 #define M33_ID_ISAR4_SYNCPRIM_FRAC_ACCESS "RO" 4711 // ----------------------------------------------------------------------------- 4712 // Field : M33_ID_ISAR4_BARRIER 4713 // Description : Indicates the implemented Barrier instructions 4714 #define M33_ID_ISAR4_BARRIER_RESET _u(0x1) 4715 #define M33_ID_ISAR4_BARRIER_BITS _u(0x000f0000) 4716 #define M33_ID_ISAR4_BARRIER_MSB _u(19) 4717 #define M33_ID_ISAR4_BARRIER_LSB _u(16) 4718 #define M33_ID_ISAR4_BARRIER_ACCESS "RO" 4719 // ----------------------------------------------------------------------------- 4720 // Field : M33_ID_ISAR4_WRITEBACK 4721 // Description : Indicates the support for writeback addressing modes 4722 #define M33_ID_ISAR4_WRITEBACK_RESET _u(0x1) 4723 #define M33_ID_ISAR4_WRITEBACK_BITS _u(0x00000f00) 4724 #define M33_ID_ISAR4_WRITEBACK_MSB _u(11) 4725 #define M33_ID_ISAR4_WRITEBACK_LSB _u(8) 4726 #define M33_ID_ISAR4_WRITEBACK_ACCESS "RO" 4727 // ----------------------------------------------------------------------------- 4728 // Field : M33_ID_ISAR4_WITHSHIFTS 4729 // Description : Indicates the support for writeback addressing modes 4730 #define M33_ID_ISAR4_WITHSHIFTS_RESET _u(0x3) 4731 #define M33_ID_ISAR4_WITHSHIFTS_BITS _u(0x000000f0) 4732 #define M33_ID_ISAR4_WITHSHIFTS_MSB _u(7) 4733 #define M33_ID_ISAR4_WITHSHIFTS_LSB _u(4) 4734 #define M33_ID_ISAR4_WITHSHIFTS_ACCESS "RO" 4735 // ----------------------------------------------------------------------------- 4736 // Field : M33_ID_ISAR4_UNPRIV 4737 // Description : Indicates the implemented unprivileged instructions 4738 #define M33_ID_ISAR4_UNPRIV_RESET _u(0x2) 4739 #define M33_ID_ISAR4_UNPRIV_BITS _u(0x0000000f) 4740 #define M33_ID_ISAR4_UNPRIV_MSB _u(3) 4741 #define M33_ID_ISAR4_UNPRIV_LSB _u(0) 4742 #define M33_ID_ISAR4_UNPRIV_ACCESS "RO" 4743 // ============================================================================= 4744 // Register : M33_ID_ISAR5 4745 // Description : Provides information about the instruction set implemented by 4746 // the PE 4747 #define M33_ID_ISAR5_OFFSET _u(0x0000ed74) 4748 #define M33_ID_ISAR5_BITS _u(0x00000000) 4749 #define M33_ID_ISAR5_RESET _u(0x00000000) 4750 #define M33_ID_ISAR5_MSB _u(31) 4751 #define M33_ID_ISAR5_LSB _u(0) 4752 #define M33_ID_ISAR5_ACCESS "RW" 4753 // ============================================================================= 4754 // Register : M33_CTR 4755 // Description : Provides information about the architecture of the caches. CTR 4756 // is RES0 if CLIDR is zero. 4757 #define M33_CTR_OFFSET _u(0x0000ed7c) 4758 #define M33_CTR_BITS _u(0x8fffc00f) 4759 #define M33_CTR_RESET _u(0x8000c000) 4760 // ----------------------------------------------------------------------------- 4761 // Field : M33_CTR_RES1 4762 // Description : Reserved, RES1 4763 #define M33_CTR_RES1_RESET _u(0x1) 4764 #define M33_CTR_RES1_BITS _u(0x80000000) 4765 #define M33_CTR_RES1_MSB _u(31) 4766 #define M33_CTR_RES1_LSB _u(31) 4767 #define M33_CTR_RES1_ACCESS "RO" 4768 // ----------------------------------------------------------------------------- 4769 // Field : M33_CTR_CWG 4770 // Description : Log2 of the number of words of the maximum size of memory that 4771 // can be overwritten as a result of the eviction of a cache entry 4772 // that has had a memory location in it modified 4773 #define M33_CTR_CWG_RESET _u(0x0) 4774 #define M33_CTR_CWG_BITS _u(0x0f000000) 4775 #define M33_CTR_CWG_MSB _u(27) 4776 #define M33_CTR_CWG_LSB _u(24) 4777 #define M33_CTR_CWG_ACCESS "RO" 4778 // ----------------------------------------------------------------------------- 4779 // Field : M33_CTR_ERG 4780 // Description : Log2 of the number of words of the maximum size of the 4781 // reservation granule that has been implemented for the Load- 4782 // Exclusive and Store-Exclusive instructions 4783 #define M33_CTR_ERG_RESET _u(0x0) 4784 #define M33_CTR_ERG_BITS _u(0x00f00000) 4785 #define M33_CTR_ERG_MSB _u(23) 4786 #define M33_CTR_ERG_LSB _u(20) 4787 #define M33_CTR_ERG_ACCESS "RO" 4788 // ----------------------------------------------------------------------------- 4789 // Field : M33_CTR_DMINLINE 4790 // Description : Log2 of the number of words in the smallest cache line of all 4791 // the data caches and unified caches that are controlled by the 4792 // PE 4793 #define M33_CTR_DMINLINE_RESET _u(0x0) 4794 #define M33_CTR_DMINLINE_BITS _u(0x000f0000) 4795 #define M33_CTR_DMINLINE_MSB _u(19) 4796 #define M33_CTR_DMINLINE_LSB _u(16) 4797 #define M33_CTR_DMINLINE_ACCESS "RO" 4798 // ----------------------------------------------------------------------------- 4799 // Field : M33_CTR_RES1_1 4800 // Description : Reserved, RES1 4801 #define M33_CTR_RES1_1_RESET _u(0x3) 4802 #define M33_CTR_RES1_1_BITS _u(0x0000c000) 4803 #define M33_CTR_RES1_1_MSB _u(15) 4804 #define M33_CTR_RES1_1_LSB _u(14) 4805 #define M33_CTR_RES1_1_ACCESS "RO" 4806 // ----------------------------------------------------------------------------- 4807 // Field : M33_CTR_IMINLINE 4808 // Description : Log2 of the number of words in the smallest cache line of all 4809 // the instruction caches that are controlled by the PE 4810 #define M33_CTR_IMINLINE_RESET _u(0x0) 4811 #define M33_CTR_IMINLINE_BITS _u(0x0000000f) 4812 #define M33_CTR_IMINLINE_MSB _u(3) 4813 #define M33_CTR_IMINLINE_LSB _u(0) 4814 #define M33_CTR_IMINLINE_ACCESS "RO" 4815 // ============================================================================= 4816 // Register : M33_CPACR 4817 // Description : Specifies the access privileges for coprocessors and the FP 4818 // Extension 4819 #define M33_CPACR_OFFSET _u(0x0000ed88) 4820 #define M33_CPACR_BITS _u(0x00f0ffff) 4821 #define M33_CPACR_RESET _u(0x00000000) 4822 // ----------------------------------------------------------------------------- 4823 // Field : M33_CPACR_CP11 4824 // Description : The value in this field is ignored. If the implementation does 4825 // not include the FP Extension, this field is RAZ/WI. If the 4826 // value of this bit is not programmed to the same value as the 4827 // CP10 field, then the value is UNKNOWN 4828 #define M33_CPACR_CP11_RESET _u(0x0) 4829 #define M33_CPACR_CP11_BITS _u(0x00c00000) 4830 #define M33_CPACR_CP11_MSB _u(23) 4831 #define M33_CPACR_CP11_LSB _u(22) 4832 #define M33_CPACR_CP11_ACCESS "RW" 4833 // ----------------------------------------------------------------------------- 4834 // Field : M33_CPACR_CP10 4835 // Description : Defines the access rights for the floating-point functionality 4836 #define M33_CPACR_CP10_RESET _u(0x0) 4837 #define M33_CPACR_CP10_BITS _u(0x00300000) 4838 #define M33_CPACR_CP10_MSB _u(21) 4839 #define M33_CPACR_CP10_LSB _u(20) 4840 #define M33_CPACR_CP10_ACCESS "RW" 4841 // ----------------------------------------------------------------------------- 4842 // Field : M33_CPACR_CP7 4843 // Description : Controls access privileges for coprocessor 7 4844 #define M33_CPACR_CP7_RESET _u(0x0) 4845 #define M33_CPACR_CP7_BITS _u(0x0000c000) 4846 #define M33_CPACR_CP7_MSB _u(15) 4847 #define M33_CPACR_CP7_LSB _u(14) 4848 #define M33_CPACR_CP7_ACCESS "RW" 4849 // ----------------------------------------------------------------------------- 4850 // Field : M33_CPACR_CP6 4851 // Description : Controls access privileges for coprocessor 6 4852 #define M33_CPACR_CP6_RESET _u(0x0) 4853 #define M33_CPACR_CP6_BITS _u(0x00003000) 4854 #define M33_CPACR_CP6_MSB _u(13) 4855 #define M33_CPACR_CP6_LSB _u(12) 4856 #define M33_CPACR_CP6_ACCESS "RW" 4857 // ----------------------------------------------------------------------------- 4858 // Field : M33_CPACR_CP5 4859 // Description : Controls access privileges for coprocessor 5 4860 #define M33_CPACR_CP5_RESET _u(0x0) 4861 #define M33_CPACR_CP5_BITS _u(0x00000c00) 4862 #define M33_CPACR_CP5_MSB _u(11) 4863 #define M33_CPACR_CP5_LSB _u(10) 4864 #define M33_CPACR_CP5_ACCESS "RW" 4865 // ----------------------------------------------------------------------------- 4866 // Field : M33_CPACR_CP4 4867 // Description : Controls access privileges for coprocessor 4 4868 #define M33_CPACR_CP4_RESET _u(0x0) 4869 #define M33_CPACR_CP4_BITS _u(0x00000300) 4870 #define M33_CPACR_CP4_MSB _u(9) 4871 #define M33_CPACR_CP4_LSB _u(8) 4872 #define M33_CPACR_CP4_ACCESS "RW" 4873 // ----------------------------------------------------------------------------- 4874 // Field : M33_CPACR_CP3 4875 // Description : Controls access privileges for coprocessor 3 4876 #define M33_CPACR_CP3_RESET _u(0x0) 4877 #define M33_CPACR_CP3_BITS _u(0x000000c0) 4878 #define M33_CPACR_CP3_MSB _u(7) 4879 #define M33_CPACR_CP3_LSB _u(6) 4880 #define M33_CPACR_CP3_ACCESS "RW" 4881 // ----------------------------------------------------------------------------- 4882 // Field : M33_CPACR_CP2 4883 // Description : Controls access privileges for coprocessor 2 4884 #define M33_CPACR_CP2_RESET _u(0x0) 4885 #define M33_CPACR_CP2_BITS _u(0x00000030) 4886 #define M33_CPACR_CP2_MSB _u(5) 4887 #define M33_CPACR_CP2_LSB _u(4) 4888 #define M33_CPACR_CP2_ACCESS "RW" 4889 // ----------------------------------------------------------------------------- 4890 // Field : M33_CPACR_CP1 4891 // Description : Controls access privileges for coprocessor 1 4892 #define M33_CPACR_CP1_RESET _u(0x0) 4893 #define M33_CPACR_CP1_BITS _u(0x0000000c) 4894 #define M33_CPACR_CP1_MSB _u(3) 4895 #define M33_CPACR_CP1_LSB _u(2) 4896 #define M33_CPACR_CP1_ACCESS "RW" 4897 // ----------------------------------------------------------------------------- 4898 // Field : M33_CPACR_CP0 4899 // Description : Controls access privileges for coprocessor 0 4900 #define M33_CPACR_CP0_RESET _u(0x0) 4901 #define M33_CPACR_CP0_BITS _u(0x00000003) 4902 #define M33_CPACR_CP0_MSB _u(1) 4903 #define M33_CPACR_CP0_LSB _u(0) 4904 #define M33_CPACR_CP0_ACCESS "RW" 4905 // ============================================================================= 4906 // Register : M33_NSACR 4907 // Description : Defines the Non-secure access permissions for both the FP 4908 // Extension and coprocessors CP0 to CP7 4909 #define M33_NSACR_OFFSET _u(0x0000ed8c) 4910 #define M33_NSACR_BITS _u(0x00000cff) 4911 #define M33_NSACR_RESET _u(0x00000000) 4912 // ----------------------------------------------------------------------------- 4913 // Field : M33_NSACR_CP11 4914 // Description : Enables Non-secure access to the Floating-point Extension 4915 #define M33_NSACR_CP11_RESET _u(0x0) 4916 #define M33_NSACR_CP11_BITS _u(0x00000800) 4917 #define M33_NSACR_CP11_MSB _u(11) 4918 #define M33_NSACR_CP11_LSB _u(11) 4919 #define M33_NSACR_CP11_ACCESS "RW" 4920 // ----------------------------------------------------------------------------- 4921 // Field : M33_NSACR_CP10 4922 // Description : Enables Non-secure access to the Floating-point Extension 4923 #define M33_NSACR_CP10_RESET _u(0x0) 4924 #define M33_NSACR_CP10_BITS _u(0x00000400) 4925 #define M33_NSACR_CP10_MSB _u(10) 4926 #define M33_NSACR_CP10_LSB _u(10) 4927 #define M33_NSACR_CP10_ACCESS "RW" 4928 // ----------------------------------------------------------------------------- 4929 // Field : M33_NSACR_CP7 4930 // Description : Enables Non-secure access to coprocessor CP7 4931 #define M33_NSACR_CP7_RESET _u(0x0) 4932 #define M33_NSACR_CP7_BITS _u(0x00000080) 4933 #define M33_NSACR_CP7_MSB _u(7) 4934 #define M33_NSACR_CP7_LSB _u(7) 4935 #define M33_NSACR_CP7_ACCESS "RW" 4936 // ----------------------------------------------------------------------------- 4937 // Field : M33_NSACR_CP6 4938 // Description : Enables Non-secure access to coprocessor CP6 4939 #define M33_NSACR_CP6_RESET _u(0x0) 4940 #define M33_NSACR_CP6_BITS _u(0x00000040) 4941 #define M33_NSACR_CP6_MSB _u(6) 4942 #define M33_NSACR_CP6_LSB _u(6) 4943 #define M33_NSACR_CP6_ACCESS "RW" 4944 // ----------------------------------------------------------------------------- 4945 // Field : M33_NSACR_CP5 4946 // Description : Enables Non-secure access to coprocessor CP5 4947 #define M33_NSACR_CP5_RESET _u(0x0) 4948 #define M33_NSACR_CP5_BITS _u(0x00000020) 4949 #define M33_NSACR_CP5_MSB _u(5) 4950 #define M33_NSACR_CP5_LSB _u(5) 4951 #define M33_NSACR_CP5_ACCESS "RW" 4952 // ----------------------------------------------------------------------------- 4953 // Field : M33_NSACR_CP4 4954 // Description : Enables Non-secure access to coprocessor CP4 4955 #define M33_NSACR_CP4_RESET _u(0x0) 4956 #define M33_NSACR_CP4_BITS _u(0x00000010) 4957 #define M33_NSACR_CP4_MSB _u(4) 4958 #define M33_NSACR_CP4_LSB _u(4) 4959 #define M33_NSACR_CP4_ACCESS "RW" 4960 // ----------------------------------------------------------------------------- 4961 // Field : M33_NSACR_CP3 4962 // Description : Enables Non-secure access to coprocessor CP3 4963 #define M33_NSACR_CP3_RESET _u(0x0) 4964 #define M33_NSACR_CP3_BITS _u(0x00000008) 4965 #define M33_NSACR_CP3_MSB _u(3) 4966 #define M33_NSACR_CP3_LSB _u(3) 4967 #define M33_NSACR_CP3_ACCESS "RW" 4968 // ----------------------------------------------------------------------------- 4969 // Field : M33_NSACR_CP2 4970 // Description : Enables Non-secure access to coprocessor CP2 4971 #define M33_NSACR_CP2_RESET _u(0x0) 4972 #define M33_NSACR_CP2_BITS _u(0x00000004) 4973 #define M33_NSACR_CP2_MSB _u(2) 4974 #define M33_NSACR_CP2_LSB _u(2) 4975 #define M33_NSACR_CP2_ACCESS "RW" 4976 // ----------------------------------------------------------------------------- 4977 // Field : M33_NSACR_CP1 4978 // Description : Enables Non-secure access to coprocessor CP1 4979 #define M33_NSACR_CP1_RESET _u(0x0) 4980 #define M33_NSACR_CP1_BITS _u(0x00000002) 4981 #define M33_NSACR_CP1_MSB _u(1) 4982 #define M33_NSACR_CP1_LSB _u(1) 4983 #define M33_NSACR_CP1_ACCESS "RW" 4984 // ----------------------------------------------------------------------------- 4985 // Field : M33_NSACR_CP0 4986 // Description : Enables Non-secure access to coprocessor CP0 4987 #define M33_NSACR_CP0_RESET _u(0x0) 4988 #define M33_NSACR_CP0_BITS _u(0x00000001) 4989 #define M33_NSACR_CP0_MSB _u(0) 4990 #define M33_NSACR_CP0_LSB _u(0) 4991 #define M33_NSACR_CP0_ACCESS "RW" 4992 // ============================================================================= 4993 // Register : M33_MPU_TYPE 4994 // Description : The MPU Type Register indicates how many regions the MPU `FTSSS 4995 // supports 4996 #define M33_MPU_TYPE_OFFSET _u(0x0000ed90) 4997 #define M33_MPU_TYPE_BITS _u(0x0000ff01) 4998 #define M33_MPU_TYPE_RESET _u(0x00000800) 4999 // ----------------------------------------------------------------------------- 5000 // Field : M33_MPU_TYPE_DREGION 5001 // Description : Number of regions supported by the MPU 5002 #define M33_MPU_TYPE_DREGION_RESET _u(0x08) 5003 #define M33_MPU_TYPE_DREGION_BITS _u(0x0000ff00) 5004 #define M33_MPU_TYPE_DREGION_MSB _u(15) 5005 #define M33_MPU_TYPE_DREGION_LSB _u(8) 5006 #define M33_MPU_TYPE_DREGION_ACCESS "RO" 5007 // ----------------------------------------------------------------------------- 5008 // Field : M33_MPU_TYPE_SEPARATE 5009 // Description : Indicates support for separate instructions and data address 5010 // regions 5011 #define M33_MPU_TYPE_SEPARATE_RESET _u(0x0) 5012 #define M33_MPU_TYPE_SEPARATE_BITS _u(0x00000001) 5013 #define M33_MPU_TYPE_SEPARATE_MSB _u(0) 5014 #define M33_MPU_TYPE_SEPARATE_LSB _u(0) 5015 #define M33_MPU_TYPE_SEPARATE_ACCESS "RO" 5016 // ============================================================================= 5017 // Register : M33_MPU_CTRL 5018 // Description : Enables the MPU and, when the MPU is enabled, controls whether 5019 // the default memory map is enabled as a background region for 5020 // privileged accesses, and whether the MPU is enabled for 5021 // HardFaults, NMIs, and exception handlers when FAULTMASK is set 5022 // to 1 5023 #define M33_MPU_CTRL_OFFSET _u(0x0000ed94) 5024 #define M33_MPU_CTRL_BITS _u(0x00000007) 5025 #define M33_MPU_CTRL_RESET _u(0x00000000) 5026 // ----------------------------------------------------------------------------- 5027 // Field : M33_MPU_CTRL_PRIVDEFENA 5028 // Description : Controls whether the default memory map is enabled for 5029 // privileged software 5030 #define M33_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) 5031 #define M33_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) 5032 #define M33_MPU_CTRL_PRIVDEFENA_MSB _u(2) 5033 #define M33_MPU_CTRL_PRIVDEFENA_LSB _u(2) 5034 #define M33_MPU_CTRL_PRIVDEFENA_ACCESS "RW" 5035 // ----------------------------------------------------------------------------- 5036 // Field : M33_MPU_CTRL_HFNMIENA 5037 // Description : Controls whether handlers executing with priority less than 0 5038 // access memory with the MPU enabled or disabled. This applies to 5039 // HardFaults, NMIs, and exception handlers when FAULTMASK is set 5040 // to 1 5041 #define M33_MPU_CTRL_HFNMIENA_RESET _u(0x0) 5042 #define M33_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) 5043 #define M33_MPU_CTRL_HFNMIENA_MSB _u(1) 5044 #define M33_MPU_CTRL_HFNMIENA_LSB _u(1) 5045 #define M33_MPU_CTRL_HFNMIENA_ACCESS "RW" 5046 // ----------------------------------------------------------------------------- 5047 // Field : M33_MPU_CTRL_ENABLE 5048 // Description : Enables the MPU 5049 #define M33_MPU_CTRL_ENABLE_RESET _u(0x0) 5050 #define M33_MPU_CTRL_ENABLE_BITS _u(0x00000001) 5051 #define M33_MPU_CTRL_ENABLE_MSB _u(0) 5052 #define M33_MPU_CTRL_ENABLE_LSB _u(0) 5053 #define M33_MPU_CTRL_ENABLE_ACCESS "RW" 5054 // ============================================================================= 5055 // Register : M33_MPU_RNR 5056 // Description : Selects the region currently accessed by MPU_RBAR and MPU_RLAR 5057 #define M33_MPU_RNR_OFFSET _u(0x0000ed98) 5058 #define M33_MPU_RNR_BITS _u(0x00000007) 5059 #define M33_MPU_RNR_RESET _u(0x00000000) 5060 // ----------------------------------------------------------------------------- 5061 // Field : M33_MPU_RNR_REGION 5062 // Description : Indicates the memory region accessed by MPU_RBAR and MPU_RLAR 5063 #define M33_MPU_RNR_REGION_RESET _u(0x0) 5064 #define M33_MPU_RNR_REGION_BITS _u(0x00000007) 5065 #define M33_MPU_RNR_REGION_MSB _u(2) 5066 #define M33_MPU_RNR_REGION_LSB _u(0) 5067 #define M33_MPU_RNR_REGION_ACCESS "RW" 5068 // ============================================================================= 5069 // Register : M33_MPU_RBAR 5070 // Description : Provides indirect read and write access to the base address of 5071 // the currently selected MPU region `FTSSS 5072 #define M33_MPU_RBAR_OFFSET _u(0x0000ed9c) 5073 #define M33_MPU_RBAR_BITS _u(0xffffffff) 5074 #define M33_MPU_RBAR_RESET _u(0x00000000) 5075 // ----------------------------------------------------------------------------- 5076 // Field : M33_MPU_RBAR_BASE 5077 // Description : Contains bits [31:5] of the lower inclusive limit of the 5078 // selected MPU memory region. This value is zero extended to 5079 // provide the base address to be checked against 5080 #define M33_MPU_RBAR_BASE_RESET _u(0x0000000) 5081 #define M33_MPU_RBAR_BASE_BITS _u(0xffffffe0) 5082 #define M33_MPU_RBAR_BASE_MSB _u(31) 5083 #define M33_MPU_RBAR_BASE_LSB _u(5) 5084 #define M33_MPU_RBAR_BASE_ACCESS "RW" 5085 // ----------------------------------------------------------------------------- 5086 // Field : M33_MPU_RBAR_SH 5087 // Description : Defines the Shareability domain of this region for Normal 5088 // memory 5089 #define M33_MPU_RBAR_SH_RESET _u(0x0) 5090 #define M33_MPU_RBAR_SH_BITS _u(0x00000018) 5091 #define M33_MPU_RBAR_SH_MSB _u(4) 5092 #define M33_MPU_RBAR_SH_LSB _u(3) 5093 #define M33_MPU_RBAR_SH_ACCESS "RW" 5094 // ----------------------------------------------------------------------------- 5095 // Field : M33_MPU_RBAR_AP 5096 // Description : Defines the access permissions for this region 5097 #define M33_MPU_RBAR_AP_RESET _u(0x0) 5098 #define M33_MPU_RBAR_AP_BITS _u(0x00000006) 5099 #define M33_MPU_RBAR_AP_MSB _u(2) 5100 #define M33_MPU_RBAR_AP_LSB _u(1) 5101 #define M33_MPU_RBAR_AP_ACCESS "RW" 5102 // ----------------------------------------------------------------------------- 5103 // Field : M33_MPU_RBAR_XN 5104 // Description : Defines whether code can be executed from this region 5105 #define M33_MPU_RBAR_XN_RESET _u(0x0) 5106 #define M33_MPU_RBAR_XN_BITS _u(0x00000001) 5107 #define M33_MPU_RBAR_XN_MSB _u(0) 5108 #define M33_MPU_RBAR_XN_LSB _u(0) 5109 #define M33_MPU_RBAR_XN_ACCESS "RW" 5110 // ============================================================================= 5111 // Register : M33_MPU_RLAR 5112 // Description : Provides indirect read and write access to the limit address of 5113 // the currently selected MPU region `FTSSS 5114 #define M33_MPU_RLAR_OFFSET _u(0x0000eda0) 5115 #define M33_MPU_RLAR_BITS _u(0xffffffef) 5116 #define M33_MPU_RLAR_RESET _u(0x00000000) 5117 // ----------------------------------------------------------------------------- 5118 // Field : M33_MPU_RLAR_LIMIT 5119 // Description : Contains bits [31:5] of the upper inclusive limit of the 5120 // selected MPU memory region. This value is postfixed with 0x1F 5121 // to provide the limit address to be checked against 5122 #define M33_MPU_RLAR_LIMIT_RESET _u(0x0000000) 5123 #define M33_MPU_RLAR_LIMIT_BITS _u(0xffffffe0) 5124 #define M33_MPU_RLAR_LIMIT_MSB _u(31) 5125 #define M33_MPU_RLAR_LIMIT_LSB _u(5) 5126 #define M33_MPU_RLAR_LIMIT_ACCESS "RW" 5127 // ----------------------------------------------------------------------------- 5128 // Field : M33_MPU_RLAR_ATTRINDX 5129 // Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 5130 // fields 5131 #define M33_MPU_RLAR_ATTRINDX_RESET _u(0x0) 5132 #define M33_MPU_RLAR_ATTRINDX_BITS _u(0x0000000e) 5133 #define M33_MPU_RLAR_ATTRINDX_MSB _u(3) 5134 #define M33_MPU_RLAR_ATTRINDX_LSB _u(1) 5135 #define M33_MPU_RLAR_ATTRINDX_ACCESS "RW" 5136 // ----------------------------------------------------------------------------- 5137 // Field : M33_MPU_RLAR_EN 5138 // Description : Region enable 5139 #define M33_MPU_RLAR_EN_RESET _u(0x0) 5140 #define M33_MPU_RLAR_EN_BITS _u(0x00000001) 5141 #define M33_MPU_RLAR_EN_MSB _u(0) 5142 #define M33_MPU_RLAR_EN_LSB _u(0) 5143 #define M33_MPU_RLAR_EN_ACCESS "RW" 5144 // ============================================================================= 5145 // Register : M33_MPU_RBAR_A1 5146 // Description : Provides indirect read and write access to the base address of 5147 // the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS 5148 #define M33_MPU_RBAR_A1_OFFSET _u(0x0000eda4) 5149 #define M33_MPU_RBAR_A1_BITS _u(0xffffffff) 5150 #define M33_MPU_RBAR_A1_RESET _u(0x00000000) 5151 // ----------------------------------------------------------------------------- 5152 // Field : M33_MPU_RBAR_A1_BASE 5153 // Description : Contains bits [31:5] of the lower inclusive limit of the 5154 // selected MPU memory region. This value is zero extended to 5155 // provide the base address to be checked against 5156 #define M33_MPU_RBAR_A1_BASE_RESET _u(0x0000000) 5157 #define M33_MPU_RBAR_A1_BASE_BITS _u(0xffffffe0) 5158 #define M33_MPU_RBAR_A1_BASE_MSB _u(31) 5159 #define M33_MPU_RBAR_A1_BASE_LSB _u(5) 5160 #define M33_MPU_RBAR_A1_BASE_ACCESS "RW" 5161 // ----------------------------------------------------------------------------- 5162 // Field : M33_MPU_RBAR_A1_SH 5163 // Description : Defines the Shareability domain of this region for Normal 5164 // memory 5165 #define M33_MPU_RBAR_A1_SH_RESET _u(0x0) 5166 #define M33_MPU_RBAR_A1_SH_BITS _u(0x00000018) 5167 #define M33_MPU_RBAR_A1_SH_MSB _u(4) 5168 #define M33_MPU_RBAR_A1_SH_LSB _u(3) 5169 #define M33_MPU_RBAR_A1_SH_ACCESS "RW" 5170 // ----------------------------------------------------------------------------- 5171 // Field : M33_MPU_RBAR_A1_AP 5172 // Description : Defines the access permissions for this region 5173 #define M33_MPU_RBAR_A1_AP_RESET _u(0x0) 5174 #define M33_MPU_RBAR_A1_AP_BITS _u(0x00000006) 5175 #define M33_MPU_RBAR_A1_AP_MSB _u(2) 5176 #define M33_MPU_RBAR_A1_AP_LSB _u(1) 5177 #define M33_MPU_RBAR_A1_AP_ACCESS "RW" 5178 // ----------------------------------------------------------------------------- 5179 // Field : M33_MPU_RBAR_A1_XN 5180 // Description : Defines whether code can be executed from this region 5181 #define M33_MPU_RBAR_A1_XN_RESET _u(0x0) 5182 #define M33_MPU_RBAR_A1_XN_BITS _u(0x00000001) 5183 #define M33_MPU_RBAR_A1_XN_MSB _u(0) 5184 #define M33_MPU_RBAR_A1_XN_LSB _u(0) 5185 #define M33_MPU_RBAR_A1_XN_ACCESS "RW" 5186 // ============================================================================= 5187 // Register : M33_MPU_RLAR_A1 5188 // Description : Provides indirect read and write access to the limit address of 5189 // the currently selected MPU region selected by 5190 // MPU_RNR[7:2]:(1[1:0]) `FTSSS 5191 #define M33_MPU_RLAR_A1_OFFSET _u(0x0000eda8) 5192 #define M33_MPU_RLAR_A1_BITS _u(0xffffffef) 5193 #define M33_MPU_RLAR_A1_RESET _u(0x00000000) 5194 // ----------------------------------------------------------------------------- 5195 // Field : M33_MPU_RLAR_A1_LIMIT 5196 // Description : Contains bits [31:5] of the upper inclusive limit of the 5197 // selected MPU memory region. This value is postfixed with 0x1F 5198 // to provide the limit address to be checked against 5199 #define M33_MPU_RLAR_A1_LIMIT_RESET _u(0x0000000) 5200 #define M33_MPU_RLAR_A1_LIMIT_BITS _u(0xffffffe0) 5201 #define M33_MPU_RLAR_A1_LIMIT_MSB _u(31) 5202 #define M33_MPU_RLAR_A1_LIMIT_LSB _u(5) 5203 #define M33_MPU_RLAR_A1_LIMIT_ACCESS "RW" 5204 // ----------------------------------------------------------------------------- 5205 // Field : M33_MPU_RLAR_A1_ATTRINDX 5206 // Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 5207 // fields 5208 #define M33_MPU_RLAR_A1_ATTRINDX_RESET _u(0x0) 5209 #define M33_MPU_RLAR_A1_ATTRINDX_BITS _u(0x0000000e) 5210 #define M33_MPU_RLAR_A1_ATTRINDX_MSB _u(3) 5211 #define M33_MPU_RLAR_A1_ATTRINDX_LSB _u(1) 5212 #define M33_MPU_RLAR_A1_ATTRINDX_ACCESS "RW" 5213 // ----------------------------------------------------------------------------- 5214 // Field : M33_MPU_RLAR_A1_EN 5215 // Description : Region enable 5216 #define M33_MPU_RLAR_A1_EN_RESET _u(0x0) 5217 #define M33_MPU_RLAR_A1_EN_BITS _u(0x00000001) 5218 #define M33_MPU_RLAR_A1_EN_MSB _u(0) 5219 #define M33_MPU_RLAR_A1_EN_LSB _u(0) 5220 #define M33_MPU_RLAR_A1_EN_ACCESS "RW" 5221 // ============================================================================= 5222 // Register : M33_MPU_RBAR_A2 5223 // Description : Provides indirect read and write access to the base address of 5224 // the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS 5225 #define M33_MPU_RBAR_A2_OFFSET _u(0x0000edac) 5226 #define M33_MPU_RBAR_A2_BITS _u(0xffffffff) 5227 #define M33_MPU_RBAR_A2_RESET _u(0x00000000) 5228 // ----------------------------------------------------------------------------- 5229 // Field : M33_MPU_RBAR_A2_BASE 5230 // Description : Contains bits [31:5] of the lower inclusive limit of the 5231 // selected MPU memory region. This value is zero extended to 5232 // provide the base address to be checked against 5233 #define M33_MPU_RBAR_A2_BASE_RESET _u(0x0000000) 5234 #define M33_MPU_RBAR_A2_BASE_BITS _u(0xffffffe0) 5235 #define M33_MPU_RBAR_A2_BASE_MSB _u(31) 5236 #define M33_MPU_RBAR_A2_BASE_LSB _u(5) 5237 #define M33_MPU_RBAR_A2_BASE_ACCESS "RW" 5238 // ----------------------------------------------------------------------------- 5239 // Field : M33_MPU_RBAR_A2_SH 5240 // Description : Defines the Shareability domain of this region for Normal 5241 // memory 5242 #define M33_MPU_RBAR_A2_SH_RESET _u(0x0) 5243 #define M33_MPU_RBAR_A2_SH_BITS _u(0x00000018) 5244 #define M33_MPU_RBAR_A2_SH_MSB _u(4) 5245 #define M33_MPU_RBAR_A2_SH_LSB _u(3) 5246 #define M33_MPU_RBAR_A2_SH_ACCESS "RW" 5247 // ----------------------------------------------------------------------------- 5248 // Field : M33_MPU_RBAR_A2_AP 5249 // Description : Defines the access permissions for this region 5250 #define M33_MPU_RBAR_A2_AP_RESET _u(0x0) 5251 #define M33_MPU_RBAR_A2_AP_BITS _u(0x00000006) 5252 #define M33_MPU_RBAR_A2_AP_MSB _u(2) 5253 #define M33_MPU_RBAR_A2_AP_LSB _u(1) 5254 #define M33_MPU_RBAR_A2_AP_ACCESS "RW" 5255 // ----------------------------------------------------------------------------- 5256 // Field : M33_MPU_RBAR_A2_XN 5257 // Description : Defines whether code can be executed from this region 5258 #define M33_MPU_RBAR_A2_XN_RESET _u(0x0) 5259 #define M33_MPU_RBAR_A2_XN_BITS _u(0x00000001) 5260 #define M33_MPU_RBAR_A2_XN_MSB _u(0) 5261 #define M33_MPU_RBAR_A2_XN_LSB _u(0) 5262 #define M33_MPU_RBAR_A2_XN_ACCESS "RW" 5263 // ============================================================================= 5264 // Register : M33_MPU_RLAR_A2 5265 // Description : Provides indirect read and write access to the limit address of 5266 // the currently selected MPU region selected by 5267 // MPU_RNR[7:2]:(2[1:0]) `FTSSS 5268 #define M33_MPU_RLAR_A2_OFFSET _u(0x0000edb0) 5269 #define M33_MPU_RLAR_A2_BITS _u(0xffffffef) 5270 #define M33_MPU_RLAR_A2_RESET _u(0x00000000) 5271 // ----------------------------------------------------------------------------- 5272 // Field : M33_MPU_RLAR_A2_LIMIT 5273 // Description : Contains bits [31:5] of the upper inclusive limit of the 5274 // selected MPU memory region. This value is postfixed with 0x1F 5275 // to provide the limit address to be checked against 5276 #define M33_MPU_RLAR_A2_LIMIT_RESET _u(0x0000000) 5277 #define M33_MPU_RLAR_A2_LIMIT_BITS _u(0xffffffe0) 5278 #define M33_MPU_RLAR_A2_LIMIT_MSB _u(31) 5279 #define M33_MPU_RLAR_A2_LIMIT_LSB _u(5) 5280 #define M33_MPU_RLAR_A2_LIMIT_ACCESS "RW" 5281 // ----------------------------------------------------------------------------- 5282 // Field : M33_MPU_RLAR_A2_ATTRINDX 5283 // Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 5284 // fields 5285 #define M33_MPU_RLAR_A2_ATTRINDX_RESET _u(0x0) 5286 #define M33_MPU_RLAR_A2_ATTRINDX_BITS _u(0x0000000e) 5287 #define M33_MPU_RLAR_A2_ATTRINDX_MSB _u(3) 5288 #define M33_MPU_RLAR_A2_ATTRINDX_LSB _u(1) 5289 #define M33_MPU_RLAR_A2_ATTRINDX_ACCESS "RW" 5290 // ----------------------------------------------------------------------------- 5291 // Field : M33_MPU_RLAR_A2_EN 5292 // Description : Region enable 5293 #define M33_MPU_RLAR_A2_EN_RESET _u(0x0) 5294 #define M33_MPU_RLAR_A2_EN_BITS _u(0x00000001) 5295 #define M33_MPU_RLAR_A2_EN_MSB _u(0) 5296 #define M33_MPU_RLAR_A2_EN_LSB _u(0) 5297 #define M33_MPU_RLAR_A2_EN_ACCESS "RW" 5298 // ============================================================================= 5299 // Register : M33_MPU_RBAR_A3 5300 // Description : Provides indirect read and write access to the base address of 5301 // the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS 5302 #define M33_MPU_RBAR_A3_OFFSET _u(0x0000edb4) 5303 #define M33_MPU_RBAR_A3_BITS _u(0xffffffff) 5304 #define M33_MPU_RBAR_A3_RESET _u(0x00000000) 5305 // ----------------------------------------------------------------------------- 5306 // Field : M33_MPU_RBAR_A3_BASE 5307 // Description : Contains bits [31:5] of the lower inclusive limit of the 5308 // selected MPU memory region. This value is zero extended to 5309 // provide the base address to be checked against 5310 #define M33_MPU_RBAR_A3_BASE_RESET _u(0x0000000) 5311 #define M33_MPU_RBAR_A3_BASE_BITS _u(0xffffffe0) 5312 #define M33_MPU_RBAR_A3_BASE_MSB _u(31) 5313 #define M33_MPU_RBAR_A3_BASE_LSB _u(5) 5314 #define M33_MPU_RBAR_A3_BASE_ACCESS "RW" 5315 // ----------------------------------------------------------------------------- 5316 // Field : M33_MPU_RBAR_A3_SH 5317 // Description : Defines the Shareability domain of this region for Normal 5318 // memory 5319 #define M33_MPU_RBAR_A3_SH_RESET _u(0x0) 5320 #define M33_MPU_RBAR_A3_SH_BITS _u(0x00000018) 5321 #define M33_MPU_RBAR_A3_SH_MSB _u(4) 5322 #define M33_MPU_RBAR_A3_SH_LSB _u(3) 5323 #define M33_MPU_RBAR_A3_SH_ACCESS "RW" 5324 // ----------------------------------------------------------------------------- 5325 // Field : M33_MPU_RBAR_A3_AP 5326 // Description : Defines the access permissions for this region 5327 #define M33_MPU_RBAR_A3_AP_RESET _u(0x0) 5328 #define M33_MPU_RBAR_A3_AP_BITS _u(0x00000006) 5329 #define M33_MPU_RBAR_A3_AP_MSB _u(2) 5330 #define M33_MPU_RBAR_A3_AP_LSB _u(1) 5331 #define M33_MPU_RBAR_A3_AP_ACCESS "RW" 5332 // ----------------------------------------------------------------------------- 5333 // Field : M33_MPU_RBAR_A3_XN 5334 // Description : Defines whether code can be executed from this region 5335 #define M33_MPU_RBAR_A3_XN_RESET _u(0x0) 5336 #define M33_MPU_RBAR_A3_XN_BITS _u(0x00000001) 5337 #define M33_MPU_RBAR_A3_XN_MSB _u(0) 5338 #define M33_MPU_RBAR_A3_XN_LSB _u(0) 5339 #define M33_MPU_RBAR_A3_XN_ACCESS "RW" 5340 // ============================================================================= 5341 // Register : M33_MPU_RLAR_A3 5342 // Description : Provides indirect read and write access to the limit address of 5343 // the currently selected MPU region selected by 5344 // MPU_RNR[7:2]:(3[1:0]) `FTSSS 5345 #define M33_MPU_RLAR_A3_OFFSET _u(0x0000edb8) 5346 #define M33_MPU_RLAR_A3_BITS _u(0xffffffef) 5347 #define M33_MPU_RLAR_A3_RESET _u(0x00000000) 5348 // ----------------------------------------------------------------------------- 5349 // Field : M33_MPU_RLAR_A3_LIMIT 5350 // Description : Contains bits [31:5] of the upper inclusive limit of the 5351 // selected MPU memory region. This value is postfixed with 0x1F 5352 // to provide the limit address to be checked against 5353 #define M33_MPU_RLAR_A3_LIMIT_RESET _u(0x0000000) 5354 #define M33_MPU_RLAR_A3_LIMIT_BITS _u(0xffffffe0) 5355 #define M33_MPU_RLAR_A3_LIMIT_MSB _u(31) 5356 #define M33_MPU_RLAR_A3_LIMIT_LSB _u(5) 5357 #define M33_MPU_RLAR_A3_LIMIT_ACCESS "RW" 5358 // ----------------------------------------------------------------------------- 5359 // Field : M33_MPU_RLAR_A3_ATTRINDX 5360 // Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 5361 // fields 5362 #define M33_MPU_RLAR_A3_ATTRINDX_RESET _u(0x0) 5363 #define M33_MPU_RLAR_A3_ATTRINDX_BITS _u(0x0000000e) 5364 #define M33_MPU_RLAR_A3_ATTRINDX_MSB _u(3) 5365 #define M33_MPU_RLAR_A3_ATTRINDX_LSB _u(1) 5366 #define M33_MPU_RLAR_A3_ATTRINDX_ACCESS "RW" 5367 // ----------------------------------------------------------------------------- 5368 // Field : M33_MPU_RLAR_A3_EN 5369 // Description : Region enable 5370 #define M33_MPU_RLAR_A3_EN_RESET _u(0x0) 5371 #define M33_MPU_RLAR_A3_EN_BITS _u(0x00000001) 5372 #define M33_MPU_RLAR_A3_EN_MSB _u(0) 5373 #define M33_MPU_RLAR_A3_EN_LSB _u(0) 5374 #define M33_MPU_RLAR_A3_EN_ACCESS "RW" 5375 // ============================================================================= 5376 // Register : M33_MPU_MAIR0 5377 // Description : Along with MPU_MAIR1, provides the memory attribute encodings 5378 // corresponding to the AttrIndex values 5379 #define M33_MPU_MAIR0_OFFSET _u(0x0000edc0) 5380 #define M33_MPU_MAIR0_BITS _u(0xffffffff) 5381 #define M33_MPU_MAIR0_RESET _u(0x00000000) 5382 // ----------------------------------------------------------------------------- 5383 // Field : M33_MPU_MAIR0_ATTR3 5384 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5385 // 3 5386 #define M33_MPU_MAIR0_ATTR3_RESET _u(0x00) 5387 #define M33_MPU_MAIR0_ATTR3_BITS _u(0xff000000) 5388 #define M33_MPU_MAIR0_ATTR3_MSB _u(31) 5389 #define M33_MPU_MAIR0_ATTR3_LSB _u(24) 5390 #define M33_MPU_MAIR0_ATTR3_ACCESS "RW" 5391 // ----------------------------------------------------------------------------- 5392 // Field : M33_MPU_MAIR0_ATTR2 5393 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5394 // 2 5395 #define M33_MPU_MAIR0_ATTR2_RESET _u(0x00) 5396 #define M33_MPU_MAIR0_ATTR2_BITS _u(0x00ff0000) 5397 #define M33_MPU_MAIR0_ATTR2_MSB _u(23) 5398 #define M33_MPU_MAIR0_ATTR2_LSB _u(16) 5399 #define M33_MPU_MAIR0_ATTR2_ACCESS "RW" 5400 // ----------------------------------------------------------------------------- 5401 // Field : M33_MPU_MAIR0_ATTR1 5402 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5403 // 1 5404 #define M33_MPU_MAIR0_ATTR1_RESET _u(0x00) 5405 #define M33_MPU_MAIR0_ATTR1_BITS _u(0x0000ff00) 5406 #define M33_MPU_MAIR0_ATTR1_MSB _u(15) 5407 #define M33_MPU_MAIR0_ATTR1_LSB _u(8) 5408 #define M33_MPU_MAIR0_ATTR1_ACCESS "RW" 5409 // ----------------------------------------------------------------------------- 5410 // Field : M33_MPU_MAIR0_ATTR0 5411 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5412 // 0 5413 #define M33_MPU_MAIR0_ATTR0_RESET _u(0x00) 5414 #define M33_MPU_MAIR0_ATTR0_BITS _u(0x000000ff) 5415 #define M33_MPU_MAIR0_ATTR0_MSB _u(7) 5416 #define M33_MPU_MAIR0_ATTR0_LSB _u(0) 5417 #define M33_MPU_MAIR0_ATTR0_ACCESS "RW" 5418 // ============================================================================= 5419 // Register : M33_MPU_MAIR1 5420 // Description : Along with MPU_MAIR0, provides the memory attribute encodings 5421 // corresponding to the AttrIndex values 5422 #define M33_MPU_MAIR1_OFFSET _u(0x0000edc4) 5423 #define M33_MPU_MAIR1_BITS _u(0xffffffff) 5424 #define M33_MPU_MAIR1_RESET _u(0x00000000) 5425 // ----------------------------------------------------------------------------- 5426 // Field : M33_MPU_MAIR1_ATTR7 5427 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5428 // 7 5429 #define M33_MPU_MAIR1_ATTR7_RESET _u(0x00) 5430 #define M33_MPU_MAIR1_ATTR7_BITS _u(0xff000000) 5431 #define M33_MPU_MAIR1_ATTR7_MSB _u(31) 5432 #define M33_MPU_MAIR1_ATTR7_LSB _u(24) 5433 #define M33_MPU_MAIR1_ATTR7_ACCESS "RW" 5434 // ----------------------------------------------------------------------------- 5435 // Field : M33_MPU_MAIR1_ATTR6 5436 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5437 // 6 5438 #define M33_MPU_MAIR1_ATTR6_RESET _u(0x00) 5439 #define M33_MPU_MAIR1_ATTR6_BITS _u(0x00ff0000) 5440 #define M33_MPU_MAIR1_ATTR6_MSB _u(23) 5441 #define M33_MPU_MAIR1_ATTR6_LSB _u(16) 5442 #define M33_MPU_MAIR1_ATTR6_ACCESS "RW" 5443 // ----------------------------------------------------------------------------- 5444 // Field : M33_MPU_MAIR1_ATTR5 5445 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5446 // 5 5447 #define M33_MPU_MAIR1_ATTR5_RESET _u(0x00) 5448 #define M33_MPU_MAIR1_ATTR5_BITS _u(0x0000ff00) 5449 #define M33_MPU_MAIR1_ATTR5_MSB _u(15) 5450 #define M33_MPU_MAIR1_ATTR5_LSB _u(8) 5451 #define M33_MPU_MAIR1_ATTR5_ACCESS "RW" 5452 // ----------------------------------------------------------------------------- 5453 // Field : M33_MPU_MAIR1_ATTR4 5454 // Description : Memory attribute encoding for MPU regions with an AttrIndex of 5455 // 4 5456 #define M33_MPU_MAIR1_ATTR4_RESET _u(0x00) 5457 #define M33_MPU_MAIR1_ATTR4_BITS _u(0x000000ff) 5458 #define M33_MPU_MAIR1_ATTR4_MSB _u(7) 5459 #define M33_MPU_MAIR1_ATTR4_LSB _u(0) 5460 #define M33_MPU_MAIR1_ATTR4_ACCESS "RW" 5461 // ============================================================================= 5462 // Register : M33_SAU_CTRL 5463 // Description : Allows enabling of the Security Attribution Unit 5464 #define M33_SAU_CTRL_OFFSET _u(0x0000edd0) 5465 #define M33_SAU_CTRL_BITS _u(0x00000003) 5466 #define M33_SAU_CTRL_RESET _u(0x00000000) 5467 // ----------------------------------------------------------------------------- 5468 // Field : M33_SAU_CTRL_ALLNS 5469 // Description : When SAU_CTRL.ENABLE is 0 this bit controls if the memory is 5470 // marked as Non-secure or Secure 5471 #define M33_SAU_CTRL_ALLNS_RESET _u(0x0) 5472 #define M33_SAU_CTRL_ALLNS_BITS _u(0x00000002) 5473 #define M33_SAU_CTRL_ALLNS_MSB _u(1) 5474 #define M33_SAU_CTRL_ALLNS_LSB _u(1) 5475 #define M33_SAU_CTRL_ALLNS_ACCESS "RW" 5476 // ----------------------------------------------------------------------------- 5477 // Field : M33_SAU_CTRL_ENABLE 5478 // Description : Enables the SAU 5479 #define M33_SAU_CTRL_ENABLE_RESET _u(0x0) 5480 #define M33_SAU_CTRL_ENABLE_BITS _u(0x00000001) 5481 #define M33_SAU_CTRL_ENABLE_MSB _u(0) 5482 #define M33_SAU_CTRL_ENABLE_LSB _u(0) 5483 #define M33_SAU_CTRL_ENABLE_ACCESS "RW" 5484 // ============================================================================= 5485 // Register : M33_SAU_TYPE 5486 // Description : Indicates the number of regions implemented by the Security 5487 // Attribution Unit 5488 #define M33_SAU_TYPE_OFFSET _u(0x0000edd4) 5489 #define M33_SAU_TYPE_BITS _u(0x000000ff) 5490 #define M33_SAU_TYPE_RESET _u(0x00000008) 5491 // ----------------------------------------------------------------------------- 5492 // Field : M33_SAU_TYPE_SREGION 5493 // Description : The number of implemented SAU regions 5494 #define M33_SAU_TYPE_SREGION_RESET _u(0x08) 5495 #define M33_SAU_TYPE_SREGION_BITS _u(0x000000ff) 5496 #define M33_SAU_TYPE_SREGION_MSB _u(7) 5497 #define M33_SAU_TYPE_SREGION_LSB _u(0) 5498 #define M33_SAU_TYPE_SREGION_ACCESS "RO" 5499 // ============================================================================= 5500 // Register : M33_SAU_RNR 5501 // Description : Selects the region currently accessed by SAU_RBAR and SAU_RLAR 5502 #define M33_SAU_RNR_OFFSET _u(0x0000edd8) 5503 #define M33_SAU_RNR_BITS _u(0x000000ff) 5504 #define M33_SAU_RNR_RESET _u(0x00000000) 5505 // ----------------------------------------------------------------------------- 5506 // Field : M33_SAU_RNR_REGION 5507 // Description : Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR 5508 #define M33_SAU_RNR_REGION_RESET _u(0x00) 5509 #define M33_SAU_RNR_REGION_BITS _u(0x000000ff) 5510 #define M33_SAU_RNR_REGION_MSB _u(7) 5511 #define M33_SAU_RNR_REGION_LSB _u(0) 5512 #define M33_SAU_RNR_REGION_ACCESS "RW" 5513 // ============================================================================= 5514 // Register : M33_SAU_RBAR 5515 // Description : Provides indirect read and write access to the base address of 5516 // the currently selected SAU region 5517 #define M33_SAU_RBAR_OFFSET _u(0x0000eddc) 5518 #define M33_SAU_RBAR_BITS _u(0xffffffe0) 5519 #define M33_SAU_RBAR_RESET _u(0x00000000) 5520 // ----------------------------------------------------------------------------- 5521 // Field : M33_SAU_RBAR_BADDR 5522 // Description : Holds bits [31:5] of the base address for the selected SAU 5523 // region 5524 #define M33_SAU_RBAR_BADDR_RESET _u(0x0000000) 5525 #define M33_SAU_RBAR_BADDR_BITS _u(0xffffffe0) 5526 #define M33_SAU_RBAR_BADDR_MSB _u(31) 5527 #define M33_SAU_RBAR_BADDR_LSB _u(5) 5528 #define M33_SAU_RBAR_BADDR_ACCESS "RW" 5529 // ============================================================================= 5530 // Register : M33_SAU_RLAR 5531 // Description : Provides indirect read and write access to the limit address of 5532 // the currently selected SAU region 5533 #define M33_SAU_RLAR_OFFSET _u(0x0000ede0) 5534 #define M33_SAU_RLAR_BITS _u(0xffffffe3) 5535 #define M33_SAU_RLAR_RESET _u(0x00000000) 5536 // ----------------------------------------------------------------------------- 5537 // Field : M33_SAU_RLAR_LADDR 5538 // Description : Holds bits [31:5] of the limit address for the selected SAU 5539 // region 5540 #define M33_SAU_RLAR_LADDR_RESET _u(0x0000000) 5541 #define M33_SAU_RLAR_LADDR_BITS _u(0xffffffe0) 5542 #define M33_SAU_RLAR_LADDR_MSB _u(31) 5543 #define M33_SAU_RLAR_LADDR_LSB _u(5) 5544 #define M33_SAU_RLAR_LADDR_ACCESS "RW" 5545 // ----------------------------------------------------------------------------- 5546 // Field : M33_SAU_RLAR_NSC 5547 // Description : Controls whether Non-secure state is permitted to execute an SG 5548 // instruction from this region 5549 #define M33_SAU_RLAR_NSC_RESET _u(0x0) 5550 #define M33_SAU_RLAR_NSC_BITS _u(0x00000002) 5551 #define M33_SAU_RLAR_NSC_MSB _u(1) 5552 #define M33_SAU_RLAR_NSC_LSB _u(1) 5553 #define M33_SAU_RLAR_NSC_ACCESS "RW" 5554 // ----------------------------------------------------------------------------- 5555 // Field : M33_SAU_RLAR_ENABLE 5556 // Description : SAU region enable 5557 #define M33_SAU_RLAR_ENABLE_RESET _u(0x0) 5558 #define M33_SAU_RLAR_ENABLE_BITS _u(0x00000001) 5559 #define M33_SAU_RLAR_ENABLE_MSB _u(0) 5560 #define M33_SAU_RLAR_ENABLE_LSB _u(0) 5561 #define M33_SAU_RLAR_ENABLE_ACCESS "RW" 5562 // ============================================================================= 5563 // Register : M33_SFSR 5564 // Description : Provides information about any security related faults 5565 #define M33_SFSR_OFFSET _u(0x0000ede4) 5566 #define M33_SFSR_BITS _u(0x000000ff) 5567 #define M33_SFSR_RESET _u(0x00000000) 5568 // ----------------------------------------------------------------------------- 5569 // Field : M33_SFSR_LSERR 5570 // Description : Sticky flag indicating that an error occurred during lazy state 5571 // activation or deactivation 5572 #define M33_SFSR_LSERR_RESET _u(0x0) 5573 #define M33_SFSR_LSERR_BITS _u(0x00000080) 5574 #define M33_SFSR_LSERR_MSB _u(7) 5575 #define M33_SFSR_LSERR_LSB _u(7) 5576 #define M33_SFSR_LSERR_ACCESS "RW" 5577 // ----------------------------------------------------------------------------- 5578 // Field : M33_SFSR_SFARVALID 5579 // Description : This bit is set when the SFAR register contains a valid value. 5580 // As with similar fields, such as BFSR.BFARVALID and 5581 // MMFSR.MMARVALID, this bit can be cleared by other exceptions, 5582 // such as BusFault 5583 #define M33_SFSR_SFARVALID_RESET _u(0x0) 5584 #define M33_SFSR_SFARVALID_BITS _u(0x00000040) 5585 #define M33_SFSR_SFARVALID_MSB _u(6) 5586 #define M33_SFSR_SFARVALID_LSB _u(6) 5587 #define M33_SFSR_SFARVALID_ACCESS "RW" 5588 // ----------------------------------------------------------------------------- 5589 // Field : M33_SFSR_LSPERR 5590 // Description : Stick flag indicating that an SAU or IDAU violation occurred 5591 // during the lazy preservation of floating-point state 5592 #define M33_SFSR_LSPERR_RESET _u(0x0) 5593 #define M33_SFSR_LSPERR_BITS _u(0x00000020) 5594 #define M33_SFSR_LSPERR_MSB _u(5) 5595 #define M33_SFSR_LSPERR_LSB _u(5) 5596 #define M33_SFSR_LSPERR_ACCESS "RW" 5597 // ----------------------------------------------------------------------------- 5598 // Field : M33_SFSR_INVTRAN 5599 // Description : Sticky flag indicating that an exception was raised due to a 5600 // branch that was not flagged as being domain crossing causing a 5601 // transition from Secure to Non-secure memory 5602 #define M33_SFSR_INVTRAN_RESET _u(0x0) 5603 #define M33_SFSR_INVTRAN_BITS _u(0x00000010) 5604 #define M33_SFSR_INVTRAN_MSB _u(4) 5605 #define M33_SFSR_INVTRAN_LSB _u(4) 5606 #define M33_SFSR_INVTRAN_ACCESS "RW" 5607 // ----------------------------------------------------------------------------- 5608 // Field : M33_SFSR_AUVIOL 5609 // Description : Sticky flag indicating that an attempt was made to access parts 5610 // of the address space that are marked as Secure with NS-Req for 5611 // the transaction set to Non-secure. This bit is not set if the 5612 // violation occurred during lazy state preservation. See LSPERR 5613 #define M33_SFSR_AUVIOL_RESET _u(0x0) 5614 #define M33_SFSR_AUVIOL_BITS _u(0x00000008) 5615 #define M33_SFSR_AUVIOL_MSB _u(3) 5616 #define M33_SFSR_AUVIOL_LSB _u(3) 5617 #define M33_SFSR_AUVIOL_ACCESS "RW" 5618 // ----------------------------------------------------------------------------- 5619 // Field : M33_SFSR_INVER 5620 // Description : This can be caused by EXC_RETURN.DCRS being set to 0 when 5621 // returning from an exception in the Non-secure state, or by 5622 // EXC_RETURN.ES being set to 1 when returning from an exception 5623 // in the Non-secure state 5624 #define M33_SFSR_INVER_RESET _u(0x0) 5625 #define M33_SFSR_INVER_BITS _u(0x00000004) 5626 #define M33_SFSR_INVER_MSB _u(2) 5627 #define M33_SFSR_INVER_LSB _u(2) 5628 #define M33_SFSR_INVER_ACCESS "RW" 5629 // ----------------------------------------------------------------------------- 5630 // Field : M33_SFSR_INVIS 5631 // Description : This bit is set if the integrity signature in an exception 5632 // stack frame is found to be invalid during the unstacking 5633 // operation 5634 #define M33_SFSR_INVIS_RESET _u(0x0) 5635 #define M33_SFSR_INVIS_BITS _u(0x00000002) 5636 #define M33_SFSR_INVIS_MSB _u(1) 5637 #define M33_SFSR_INVIS_LSB _u(1) 5638 #define M33_SFSR_INVIS_ACCESS "RW" 5639 // ----------------------------------------------------------------------------- 5640 // Field : M33_SFSR_INVEP 5641 // Description : This bit is set if a function call from the Non-secure state or 5642 // exception targets a non-SG instruction in the Secure state. 5643 // This bit is also set if the target address is a SG instruction, 5644 // but there is no matching SAU/IDAU region with the NSC flag set 5645 #define M33_SFSR_INVEP_RESET _u(0x0) 5646 #define M33_SFSR_INVEP_BITS _u(0x00000001) 5647 #define M33_SFSR_INVEP_MSB _u(0) 5648 #define M33_SFSR_INVEP_LSB _u(0) 5649 #define M33_SFSR_INVEP_ACCESS "RW" 5650 // ============================================================================= 5651 // Register : M33_SFAR 5652 // Description : Shows the address of the memory location that caused a Security 5653 // violation 5654 #define M33_SFAR_OFFSET _u(0x0000ede8) 5655 #define M33_SFAR_BITS _u(0xffffffff) 5656 #define M33_SFAR_RESET _u(0x00000000) 5657 // ----------------------------------------------------------------------------- 5658 // Field : M33_SFAR_ADDRESS 5659 // Description : The address of an access that caused a attribution unit 5660 // violation. This field is only valid when SFSR.SFARVALID is set. 5661 // This allows the actual flip flops associated with this register 5662 // to be shared with other fault address registers. If an 5663 // implementation chooses to share the storage in this way, care 5664 // must be taken to not leak Secure address information to the 5665 // Non-secure state. One way of achieving this is to share the 5666 // SFAR register with the MMFAR_S register, which is not 5667 // accessible to the Non-secure state 5668 #define M33_SFAR_ADDRESS_RESET _u(0x00000000) 5669 #define M33_SFAR_ADDRESS_BITS _u(0xffffffff) 5670 #define M33_SFAR_ADDRESS_MSB _u(31) 5671 #define M33_SFAR_ADDRESS_LSB _u(0) 5672 #define M33_SFAR_ADDRESS_ACCESS "RW" 5673 // ============================================================================= 5674 // Register : M33_DHCSR 5675 // Description : Controls halting debug 5676 #define M33_DHCSR_OFFSET _u(0x0000edf0) 5677 #define M33_DHCSR_BITS _u(0x071f002f) 5678 #define M33_DHCSR_RESET _u(0x00000000) 5679 // ----------------------------------------------------------------------------- 5680 // Field : M33_DHCSR_S_RESTART_ST 5681 // Description : Indicates the PE has processed a request to clear DHCSR.C_HALT 5682 // to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT 5683 // from 1 to 0, or an External Restart Request 5684 #define M33_DHCSR_S_RESTART_ST_RESET _u(0x0) 5685 #define M33_DHCSR_S_RESTART_ST_BITS _u(0x04000000) 5686 #define M33_DHCSR_S_RESTART_ST_MSB _u(26) 5687 #define M33_DHCSR_S_RESTART_ST_LSB _u(26) 5688 #define M33_DHCSR_S_RESTART_ST_ACCESS "RO" 5689 // ----------------------------------------------------------------------------- 5690 // Field : M33_DHCSR_S_RESET_ST 5691 // Description : Indicates whether the PE has been reset since the last read of 5692 // the DHCSR 5693 #define M33_DHCSR_S_RESET_ST_RESET _u(0x0) 5694 #define M33_DHCSR_S_RESET_ST_BITS _u(0x02000000) 5695 #define M33_DHCSR_S_RESET_ST_MSB _u(25) 5696 #define M33_DHCSR_S_RESET_ST_LSB _u(25) 5697 #define M33_DHCSR_S_RESET_ST_ACCESS "RO" 5698 // ----------------------------------------------------------------------------- 5699 // Field : M33_DHCSR_S_RETIRE_ST 5700 // Description : Set to 1 every time the PE retires one of more instructions 5701 #define M33_DHCSR_S_RETIRE_ST_RESET _u(0x0) 5702 #define M33_DHCSR_S_RETIRE_ST_BITS _u(0x01000000) 5703 #define M33_DHCSR_S_RETIRE_ST_MSB _u(24) 5704 #define M33_DHCSR_S_RETIRE_ST_LSB _u(24) 5705 #define M33_DHCSR_S_RETIRE_ST_ACCESS "RO" 5706 // ----------------------------------------------------------------------------- 5707 // Field : M33_DHCSR_S_SDE 5708 // Description : Indicates whether Secure invasive debug is allowed 5709 #define M33_DHCSR_S_SDE_RESET _u(0x0) 5710 #define M33_DHCSR_S_SDE_BITS _u(0x00100000) 5711 #define M33_DHCSR_S_SDE_MSB _u(20) 5712 #define M33_DHCSR_S_SDE_LSB _u(20) 5713 #define M33_DHCSR_S_SDE_ACCESS "RO" 5714 // ----------------------------------------------------------------------------- 5715 // Field : M33_DHCSR_S_LOCKUP 5716 // Description : Indicates whether the PE is in Lockup state 5717 #define M33_DHCSR_S_LOCKUP_RESET _u(0x0) 5718 #define M33_DHCSR_S_LOCKUP_BITS _u(0x00080000) 5719 #define M33_DHCSR_S_LOCKUP_MSB _u(19) 5720 #define M33_DHCSR_S_LOCKUP_LSB _u(19) 5721 #define M33_DHCSR_S_LOCKUP_ACCESS "RO" 5722 // ----------------------------------------------------------------------------- 5723 // Field : M33_DHCSR_S_SLEEP 5724 // Description : Indicates whether the PE is sleeping 5725 #define M33_DHCSR_S_SLEEP_RESET _u(0x0) 5726 #define M33_DHCSR_S_SLEEP_BITS _u(0x00040000) 5727 #define M33_DHCSR_S_SLEEP_MSB _u(18) 5728 #define M33_DHCSR_S_SLEEP_LSB _u(18) 5729 #define M33_DHCSR_S_SLEEP_ACCESS "RO" 5730 // ----------------------------------------------------------------------------- 5731 // Field : M33_DHCSR_S_HALT 5732 // Description : Indicates whether the PE is in Debug state 5733 #define M33_DHCSR_S_HALT_RESET _u(0x0) 5734 #define M33_DHCSR_S_HALT_BITS _u(0x00020000) 5735 #define M33_DHCSR_S_HALT_MSB _u(17) 5736 #define M33_DHCSR_S_HALT_LSB _u(17) 5737 #define M33_DHCSR_S_HALT_ACCESS "RO" 5738 // ----------------------------------------------------------------------------- 5739 // Field : M33_DHCSR_S_REGRDY 5740 // Description : Handshake flag to transfers through the DCRDR 5741 #define M33_DHCSR_S_REGRDY_RESET _u(0x0) 5742 #define M33_DHCSR_S_REGRDY_BITS _u(0x00010000) 5743 #define M33_DHCSR_S_REGRDY_MSB _u(16) 5744 #define M33_DHCSR_S_REGRDY_LSB _u(16) 5745 #define M33_DHCSR_S_REGRDY_ACCESS "RO" 5746 // ----------------------------------------------------------------------------- 5747 // Field : M33_DHCSR_C_SNAPSTALL 5748 // Description : Allow imprecise entry to Debug state 5749 #define M33_DHCSR_C_SNAPSTALL_RESET _u(0x0) 5750 #define M33_DHCSR_C_SNAPSTALL_BITS _u(0x00000020) 5751 #define M33_DHCSR_C_SNAPSTALL_MSB _u(5) 5752 #define M33_DHCSR_C_SNAPSTALL_LSB _u(5) 5753 #define M33_DHCSR_C_SNAPSTALL_ACCESS "RW" 5754 // ----------------------------------------------------------------------------- 5755 // Field : M33_DHCSR_C_MASKINTS 5756 // Description : When debug is enabled, the debugger can write to this bit to 5757 // mask PendSV, SysTick and external configurable interrupts 5758 #define M33_DHCSR_C_MASKINTS_RESET _u(0x0) 5759 #define M33_DHCSR_C_MASKINTS_BITS _u(0x00000008) 5760 #define M33_DHCSR_C_MASKINTS_MSB _u(3) 5761 #define M33_DHCSR_C_MASKINTS_LSB _u(3) 5762 #define M33_DHCSR_C_MASKINTS_ACCESS "RW" 5763 // ----------------------------------------------------------------------------- 5764 // Field : M33_DHCSR_C_STEP 5765 // Description : Enable single instruction step 5766 #define M33_DHCSR_C_STEP_RESET _u(0x0) 5767 #define M33_DHCSR_C_STEP_BITS _u(0x00000004) 5768 #define M33_DHCSR_C_STEP_MSB _u(2) 5769 #define M33_DHCSR_C_STEP_LSB _u(2) 5770 #define M33_DHCSR_C_STEP_ACCESS "RW" 5771 // ----------------------------------------------------------------------------- 5772 // Field : M33_DHCSR_C_HALT 5773 // Description : PE enter Debug state halt request 5774 #define M33_DHCSR_C_HALT_RESET _u(0x0) 5775 #define M33_DHCSR_C_HALT_BITS _u(0x00000002) 5776 #define M33_DHCSR_C_HALT_MSB _u(1) 5777 #define M33_DHCSR_C_HALT_LSB _u(1) 5778 #define M33_DHCSR_C_HALT_ACCESS "RW" 5779 // ----------------------------------------------------------------------------- 5780 // Field : M33_DHCSR_C_DEBUGEN 5781 // Description : Enable Halting debug 5782 #define M33_DHCSR_C_DEBUGEN_RESET _u(0x0) 5783 #define M33_DHCSR_C_DEBUGEN_BITS _u(0x00000001) 5784 #define M33_DHCSR_C_DEBUGEN_MSB _u(0) 5785 #define M33_DHCSR_C_DEBUGEN_LSB _u(0) 5786 #define M33_DHCSR_C_DEBUGEN_ACCESS "RW" 5787 // ============================================================================= 5788 // Register : M33_DCRSR 5789 // Description : With the DCRDR, provides debug access to the general-purpose 5790 // registers, special-purpose registers, and the FP extension 5791 // registers. A write to the DCRSR specifies the register to 5792 // transfer, whether the transfer is a read or write, and starts 5793 // the transfer 5794 #define M33_DCRSR_OFFSET _u(0x0000edf4) 5795 #define M33_DCRSR_BITS _u(0x0001007f) 5796 #define M33_DCRSR_RESET _u(0x00000000) 5797 // ----------------------------------------------------------------------------- 5798 // Field : M33_DCRSR_REGWNR 5799 // Description : Specifies the access type for the transfer 5800 #define M33_DCRSR_REGWNR_RESET _u(0x0) 5801 #define M33_DCRSR_REGWNR_BITS _u(0x00010000) 5802 #define M33_DCRSR_REGWNR_MSB _u(16) 5803 #define M33_DCRSR_REGWNR_LSB _u(16) 5804 #define M33_DCRSR_REGWNR_ACCESS "RW" 5805 // ----------------------------------------------------------------------------- 5806 // Field : M33_DCRSR_REGSEL 5807 // Description : Specifies the general-purpose register, special-purpose 5808 // register, or FP register to transfer 5809 #define M33_DCRSR_REGSEL_RESET _u(0x00) 5810 #define M33_DCRSR_REGSEL_BITS _u(0x0000007f) 5811 #define M33_DCRSR_REGSEL_MSB _u(6) 5812 #define M33_DCRSR_REGSEL_LSB _u(0) 5813 #define M33_DCRSR_REGSEL_ACCESS "RW" 5814 // ============================================================================= 5815 // Register : M33_DCRDR 5816 // Description : With the DCRSR, provides debug access to the general-purpose 5817 // registers, special-purpose registers, and the FP Extension 5818 // registers. If the Main Extension is implemented, it can also be 5819 // used for message passing between an external debugger and a 5820 // debug agent running on the PE 5821 #define M33_DCRDR_OFFSET _u(0x0000edf8) 5822 #define M33_DCRDR_BITS _u(0xffffffff) 5823 #define M33_DCRDR_RESET _u(0x00000000) 5824 // ----------------------------------------------------------------------------- 5825 // Field : M33_DCRDR_DBGTMP 5826 // Description : Provides debug access for reading and writing the general- 5827 // purpose registers, special-purpose registers, and Floating- 5828 // point Extension registers 5829 #define M33_DCRDR_DBGTMP_RESET _u(0x00000000) 5830 #define M33_DCRDR_DBGTMP_BITS _u(0xffffffff) 5831 #define M33_DCRDR_DBGTMP_MSB _u(31) 5832 #define M33_DCRDR_DBGTMP_LSB _u(0) 5833 #define M33_DCRDR_DBGTMP_ACCESS "RW" 5834 // ============================================================================= 5835 // Register : M33_DEMCR 5836 // Description : Manages vector catch behavior and DebugMonitor handling when 5837 // debugging 5838 #define M33_DEMCR_OFFSET _u(0x0000edfc) 5839 #define M33_DEMCR_BITS _u(0x011f0ff1) 5840 #define M33_DEMCR_RESET _u(0x00000000) 5841 // ----------------------------------------------------------------------------- 5842 // Field : M33_DEMCR_TRCENA 5843 // Description : Global enable for all DWT and ITM features 5844 #define M33_DEMCR_TRCENA_RESET _u(0x0) 5845 #define M33_DEMCR_TRCENA_BITS _u(0x01000000) 5846 #define M33_DEMCR_TRCENA_MSB _u(24) 5847 #define M33_DEMCR_TRCENA_LSB _u(24) 5848 #define M33_DEMCR_TRCENA_ACCESS "RW" 5849 // ----------------------------------------------------------------------------- 5850 // Field : M33_DEMCR_SDME 5851 // Description : Indicates whether the DebugMonitor targets the Secure or the 5852 // Non-secure state and whether debug events are allowed in Secure 5853 // state 5854 #define M33_DEMCR_SDME_RESET _u(0x0) 5855 #define M33_DEMCR_SDME_BITS _u(0x00100000) 5856 #define M33_DEMCR_SDME_MSB _u(20) 5857 #define M33_DEMCR_SDME_LSB _u(20) 5858 #define M33_DEMCR_SDME_ACCESS "RO" 5859 // ----------------------------------------------------------------------------- 5860 // Field : M33_DEMCR_MON_REQ 5861 // Description : DebugMonitor semaphore bit 5862 #define M33_DEMCR_MON_REQ_RESET _u(0x0) 5863 #define M33_DEMCR_MON_REQ_BITS _u(0x00080000) 5864 #define M33_DEMCR_MON_REQ_MSB _u(19) 5865 #define M33_DEMCR_MON_REQ_LSB _u(19) 5866 #define M33_DEMCR_MON_REQ_ACCESS "RW" 5867 // ----------------------------------------------------------------------------- 5868 // Field : M33_DEMCR_MON_STEP 5869 // Description : Enable DebugMonitor stepping 5870 #define M33_DEMCR_MON_STEP_RESET _u(0x0) 5871 #define M33_DEMCR_MON_STEP_BITS _u(0x00040000) 5872 #define M33_DEMCR_MON_STEP_MSB _u(18) 5873 #define M33_DEMCR_MON_STEP_LSB _u(18) 5874 #define M33_DEMCR_MON_STEP_ACCESS "RW" 5875 // ----------------------------------------------------------------------------- 5876 // Field : M33_DEMCR_MON_PEND 5877 // Description : Sets or clears the pending state of the DebugMonitor exception 5878 #define M33_DEMCR_MON_PEND_RESET _u(0x0) 5879 #define M33_DEMCR_MON_PEND_BITS _u(0x00020000) 5880 #define M33_DEMCR_MON_PEND_MSB _u(17) 5881 #define M33_DEMCR_MON_PEND_LSB _u(17) 5882 #define M33_DEMCR_MON_PEND_ACCESS "RW" 5883 // ----------------------------------------------------------------------------- 5884 // Field : M33_DEMCR_MON_EN 5885 // Description : Enable the DebugMonitor exception 5886 #define M33_DEMCR_MON_EN_RESET _u(0x0) 5887 #define M33_DEMCR_MON_EN_BITS _u(0x00010000) 5888 #define M33_DEMCR_MON_EN_MSB _u(16) 5889 #define M33_DEMCR_MON_EN_LSB _u(16) 5890 #define M33_DEMCR_MON_EN_ACCESS "RW" 5891 // ----------------------------------------------------------------------------- 5892 // Field : M33_DEMCR_VC_SFERR 5893 // Description : SecureFault exception halting debug vector catch enable 5894 #define M33_DEMCR_VC_SFERR_RESET _u(0x0) 5895 #define M33_DEMCR_VC_SFERR_BITS _u(0x00000800) 5896 #define M33_DEMCR_VC_SFERR_MSB _u(11) 5897 #define M33_DEMCR_VC_SFERR_LSB _u(11) 5898 #define M33_DEMCR_VC_SFERR_ACCESS "RW" 5899 // ----------------------------------------------------------------------------- 5900 // Field : M33_DEMCR_VC_HARDERR 5901 // Description : HardFault exception halting debug vector catch enable 5902 #define M33_DEMCR_VC_HARDERR_RESET _u(0x0) 5903 #define M33_DEMCR_VC_HARDERR_BITS _u(0x00000400) 5904 #define M33_DEMCR_VC_HARDERR_MSB _u(10) 5905 #define M33_DEMCR_VC_HARDERR_LSB _u(10) 5906 #define M33_DEMCR_VC_HARDERR_ACCESS "RW" 5907 // ----------------------------------------------------------------------------- 5908 // Field : M33_DEMCR_VC_INTERR 5909 // Description : Enable halting debug vector catch for faults during exception 5910 // entry and return 5911 #define M33_DEMCR_VC_INTERR_RESET _u(0x0) 5912 #define M33_DEMCR_VC_INTERR_BITS _u(0x00000200) 5913 #define M33_DEMCR_VC_INTERR_MSB _u(9) 5914 #define M33_DEMCR_VC_INTERR_LSB _u(9) 5915 #define M33_DEMCR_VC_INTERR_ACCESS "RW" 5916 // ----------------------------------------------------------------------------- 5917 // Field : M33_DEMCR_VC_BUSERR 5918 // Description : BusFault exception halting debug vector catch enable 5919 #define M33_DEMCR_VC_BUSERR_RESET _u(0x0) 5920 #define M33_DEMCR_VC_BUSERR_BITS _u(0x00000100) 5921 #define M33_DEMCR_VC_BUSERR_MSB _u(8) 5922 #define M33_DEMCR_VC_BUSERR_LSB _u(8) 5923 #define M33_DEMCR_VC_BUSERR_ACCESS "RW" 5924 // ----------------------------------------------------------------------------- 5925 // Field : M33_DEMCR_VC_STATERR 5926 // Description : Enable halting debug trap on a UsageFault exception caused by a 5927 // state information error, for example an Undefined Instruction 5928 // exception 5929 #define M33_DEMCR_VC_STATERR_RESET _u(0x0) 5930 #define M33_DEMCR_VC_STATERR_BITS _u(0x00000080) 5931 #define M33_DEMCR_VC_STATERR_MSB _u(7) 5932 #define M33_DEMCR_VC_STATERR_LSB _u(7) 5933 #define M33_DEMCR_VC_STATERR_ACCESS "RW" 5934 // ----------------------------------------------------------------------------- 5935 // Field : M33_DEMCR_VC_CHKERR 5936 // Description : Enable halting debug trap on a UsageFault exception caused by a 5937 // checking error, for example an alignment check error 5938 #define M33_DEMCR_VC_CHKERR_RESET _u(0x0) 5939 #define M33_DEMCR_VC_CHKERR_BITS _u(0x00000040) 5940 #define M33_DEMCR_VC_CHKERR_MSB _u(6) 5941 #define M33_DEMCR_VC_CHKERR_LSB _u(6) 5942 #define M33_DEMCR_VC_CHKERR_ACCESS "RW" 5943 // ----------------------------------------------------------------------------- 5944 // Field : M33_DEMCR_VC_NOCPERR 5945 // Description : Enable halting debug trap on a UsageFault caused by an access 5946 // to a coprocessor 5947 #define M33_DEMCR_VC_NOCPERR_RESET _u(0x0) 5948 #define M33_DEMCR_VC_NOCPERR_BITS _u(0x00000020) 5949 #define M33_DEMCR_VC_NOCPERR_MSB _u(5) 5950 #define M33_DEMCR_VC_NOCPERR_LSB _u(5) 5951 #define M33_DEMCR_VC_NOCPERR_ACCESS "RW" 5952 // ----------------------------------------------------------------------------- 5953 // Field : M33_DEMCR_VC_MMERR 5954 // Description : Enable halting debug trap on a MemManage exception 5955 #define M33_DEMCR_VC_MMERR_RESET _u(0x0) 5956 #define M33_DEMCR_VC_MMERR_BITS _u(0x00000010) 5957 #define M33_DEMCR_VC_MMERR_MSB _u(4) 5958 #define M33_DEMCR_VC_MMERR_LSB _u(4) 5959 #define M33_DEMCR_VC_MMERR_ACCESS "RW" 5960 // ----------------------------------------------------------------------------- 5961 // Field : M33_DEMCR_VC_CORERESET 5962 // Description : Enable Reset Vector Catch. This causes a warm reset to halt a 5963 // running system 5964 #define M33_DEMCR_VC_CORERESET_RESET _u(0x0) 5965 #define M33_DEMCR_VC_CORERESET_BITS _u(0x00000001) 5966 #define M33_DEMCR_VC_CORERESET_MSB _u(0) 5967 #define M33_DEMCR_VC_CORERESET_LSB _u(0) 5968 #define M33_DEMCR_VC_CORERESET_ACCESS "RW" 5969 // ============================================================================= 5970 // Register : M33_DSCSR 5971 // Description : Provides control and status information for Secure debug 5972 #define M33_DSCSR_OFFSET _u(0x0000ee08) 5973 #define M33_DSCSR_BITS _u(0x00030003) 5974 #define M33_DSCSR_RESET _u(0x00000000) 5975 // ----------------------------------------------------------------------------- 5976 // Field : M33_DSCSR_CDSKEY 5977 // Description : Writes to the CDS bit are ignored unless CDSKEY is concurrently 5978 // written to zero 5979 #define M33_DSCSR_CDSKEY_RESET _u(0x0) 5980 #define M33_DSCSR_CDSKEY_BITS _u(0x00020000) 5981 #define M33_DSCSR_CDSKEY_MSB _u(17) 5982 #define M33_DSCSR_CDSKEY_LSB _u(17) 5983 #define M33_DSCSR_CDSKEY_ACCESS "RW" 5984 // ----------------------------------------------------------------------------- 5985 // Field : M33_DSCSR_CDS 5986 // Description : This field indicates the current Security state of the 5987 // processor 5988 #define M33_DSCSR_CDS_RESET _u(0x0) 5989 #define M33_DSCSR_CDS_BITS _u(0x00010000) 5990 #define M33_DSCSR_CDS_MSB _u(16) 5991 #define M33_DSCSR_CDS_LSB _u(16) 5992 #define M33_DSCSR_CDS_ACCESS "RW" 5993 // ----------------------------------------------------------------------------- 5994 // Field : M33_DSCSR_SBRSEL 5995 // Description : If SBRSELEN is 1 this bit selects whether the Non-secure or the 5996 // Secure version of the memory-mapped Banked registers are 5997 // accessible to the debugger 5998 #define M33_DSCSR_SBRSEL_RESET _u(0x0) 5999 #define M33_DSCSR_SBRSEL_BITS _u(0x00000002) 6000 #define M33_DSCSR_SBRSEL_MSB _u(1) 6001 #define M33_DSCSR_SBRSEL_LSB _u(1) 6002 #define M33_DSCSR_SBRSEL_ACCESS "RW" 6003 // ----------------------------------------------------------------------------- 6004 // Field : M33_DSCSR_SBRSELEN 6005 // Description : Controls whether the SBRSEL field or the current Security state 6006 // of the processor selects which version of the memory-mapped 6007 // Banked registers are accessed to the debugger 6008 #define M33_DSCSR_SBRSELEN_RESET _u(0x0) 6009 #define M33_DSCSR_SBRSELEN_BITS _u(0x00000001) 6010 #define M33_DSCSR_SBRSELEN_MSB _u(0) 6011 #define M33_DSCSR_SBRSELEN_LSB _u(0) 6012 #define M33_DSCSR_SBRSELEN_ACCESS "RW" 6013 // ============================================================================= 6014 // Register : M33_STIR 6015 // Description : Provides a mechanism for software to generate an interrupt 6016 #define M33_STIR_OFFSET _u(0x0000ef00) 6017 #define M33_STIR_BITS _u(0x000001ff) 6018 #define M33_STIR_RESET _u(0x00000000) 6019 // ----------------------------------------------------------------------------- 6020 // Field : M33_STIR_INTID 6021 // Description : Indicates the interrupt to be pended. The value written is 6022 // (ExceptionNumber - 16) 6023 #define M33_STIR_INTID_RESET _u(0x000) 6024 #define M33_STIR_INTID_BITS _u(0x000001ff) 6025 #define M33_STIR_INTID_MSB _u(8) 6026 #define M33_STIR_INTID_LSB _u(0) 6027 #define M33_STIR_INTID_ACCESS "RW" 6028 // ============================================================================= 6029 // Register : M33_FPCCR 6030 // Description : Holds control data for the Floating-point extension 6031 #define M33_FPCCR_OFFSET _u(0x0000ef34) 6032 #define M33_FPCCR_BITS _u(0xfc0007ff) 6033 #define M33_FPCCR_RESET _u(0x20000472) 6034 // ----------------------------------------------------------------------------- 6035 // Field : M33_FPCCR_ASPEN 6036 // Description : When this bit is set to 1, execution of a floating-point 6037 // instruction sets the CONTROL.FPCA bit to 1 6038 #define M33_FPCCR_ASPEN_RESET _u(0x0) 6039 #define M33_FPCCR_ASPEN_BITS _u(0x80000000) 6040 #define M33_FPCCR_ASPEN_MSB _u(31) 6041 #define M33_FPCCR_ASPEN_LSB _u(31) 6042 #define M33_FPCCR_ASPEN_ACCESS "RW" 6043 // ----------------------------------------------------------------------------- 6044 // Field : M33_FPCCR_LSPEN 6045 // Description : Enables lazy context save of floating-point state 6046 #define M33_FPCCR_LSPEN_RESET _u(0x0) 6047 #define M33_FPCCR_LSPEN_BITS _u(0x40000000) 6048 #define M33_FPCCR_LSPEN_MSB _u(30) 6049 #define M33_FPCCR_LSPEN_LSB _u(30) 6050 #define M33_FPCCR_LSPEN_ACCESS "RW" 6051 // ----------------------------------------------------------------------------- 6052 // Field : M33_FPCCR_LSPENS 6053 // Description : This bit controls whether the LSPEN bit is writeable from the 6054 // Non-secure state 6055 #define M33_FPCCR_LSPENS_RESET _u(0x1) 6056 #define M33_FPCCR_LSPENS_BITS _u(0x20000000) 6057 #define M33_FPCCR_LSPENS_MSB _u(29) 6058 #define M33_FPCCR_LSPENS_LSB _u(29) 6059 #define M33_FPCCR_LSPENS_ACCESS "RW" 6060 // ----------------------------------------------------------------------------- 6061 // Field : M33_FPCCR_CLRONRET 6062 // Description : Clear floating-point caller saved registers on exception return 6063 #define M33_FPCCR_CLRONRET_RESET _u(0x0) 6064 #define M33_FPCCR_CLRONRET_BITS _u(0x10000000) 6065 #define M33_FPCCR_CLRONRET_MSB _u(28) 6066 #define M33_FPCCR_CLRONRET_LSB _u(28) 6067 #define M33_FPCCR_CLRONRET_ACCESS "RW" 6068 // ----------------------------------------------------------------------------- 6069 // Field : M33_FPCCR_CLRONRETS 6070 // Description : This bit controls whether the CLRONRET bit is writeable from 6071 // the Non-secure state 6072 #define M33_FPCCR_CLRONRETS_RESET _u(0x0) 6073 #define M33_FPCCR_CLRONRETS_BITS _u(0x08000000) 6074 #define M33_FPCCR_CLRONRETS_MSB _u(27) 6075 #define M33_FPCCR_CLRONRETS_LSB _u(27) 6076 #define M33_FPCCR_CLRONRETS_ACCESS "RW" 6077 // ----------------------------------------------------------------------------- 6078 // Field : M33_FPCCR_TS 6079 // Description : Treat floating-point registers as Secure enable 6080 #define M33_FPCCR_TS_RESET _u(0x0) 6081 #define M33_FPCCR_TS_BITS _u(0x04000000) 6082 #define M33_FPCCR_TS_MSB _u(26) 6083 #define M33_FPCCR_TS_LSB _u(26) 6084 #define M33_FPCCR_TS_ACCESS "RW" 6085 // ----------------------------------------------------------------------------- 6086 // Field : M33_FPCCR_UFRDY 6087 // Description : Indicates whether the software executing when the PE allocated 6088 // the floating-point stack frame was able to set the UsageFault 6089 // exception to pending 6090 #define M33_FPCCR_UFRDY_RESET _u(0x1) 6091 #define M33_FPCCR_UFRDY_BITS _u(0x00000400) 6092 #define M33_FPCCR_UFRDY_MSB _u(10) 6093 #define M33_FPCCR_UFRDY_LSB _u(10) 6094 #define M33_FPCCR_UFRDY_ACCESS "RW" 6095 // ----------------------------------------------------------------------------- 6096 // Field : M33_FPCCR_SPLIMVIOL 6097 // Description : This bit is banked between the Security states and indicates 6098 // whether the floating-point context violates the stack pointer 6099 // limit that was active when lazy state preservation was 6100 // activated. SPLIMVIOL modifies the lazy floating-point state 6101 // preservation behavior 6102 #define M33_FPCCR_SPLIMVIOL_RESET _u(0x0) 6103 #define M33_FPCCR_SPLIMVIOL_BITS _u(0x00000200) 6104 #define M33_FPCCR_SPLIMVIOL_MSB _u(9) 6105 #define M33_FPCCR_SPLIMVIOL_LSB _u(9) 6106 #define M33_FPCCR_SPLIMVIOL_ACCESS "RW" 6107 // ----------------------------------------------------------------------------- 6108 // Field : M33_FPCCR_MONRDY 6109 // Description : Indicates whether the software executing when the PE allocated 6110 // the floating-point stack frame was able to set the DebugMonitor 6111 // exception to pending 6112 #define M33_FPCCR_MONRDY_RESET _u(0x0) 6113 #define M33_FPCCR_MONRDY_BITS _u(0x00000100) 6114 #define M33_FPCCR_MONRDY_MSB _u(8) 6115 #define M33_FPCCR_MONRDY_LSB _u(8) 6116 #define M33_FPCCR_MONRDY_ACCESS "RW" 6117 // ----------------------------------------------------------------------------- 6118 // Field : M33_FPCCR_SFRDY 6119 // Description : Indicates whether the software executing when the PE allocated 6120 // the floating-point stack frame was able to set the SecureFault 6121 // exception to pending. This bit is only present in the Secure 6122 // version of the register, and behaves as RAZ/WI when accessed 6123 // from the Non-secure state 6124 #define M33_FPCCR_SFRDY_RESET _u(0x0) 6125 #define M33_FPCCR_SFRDY_BITS _u(0x00000080) 6126 #define M33_FPCCR_SFRDY_MSB _u(7) 6127 #define M33_FPCCR_SFRDY_LSB _u(7) 6128 #define M33_FPCCR_SFRDY_ACCESS "RW" 6129 // ----------------------------------------------------------------------------- 6130 // Field : M33_FPCCR_BFRDY 6131 // Description : Indicates whether the software executing when the PE allocated 6132 // the floating-point stack frame was able to set the BusFault 6133 // exception to pending 6134 #define M33_FPCCR_BFRDY_RESET _u(0x1) 6135 #define M33_FPCCR_BFRDY_BITS _u(0x00000040) 6136 #define M33_FPCCR_BFRDY_MSB _u(6) 6137 #define M33_FPCCR_BFRDY_LSB _u(6) 6138 #define M33_FPCCR_BFRDY_ACCESS "RW" 6139 // ----------------------------------------------------------------------------- 6140 // Field : M33_FPCCR_MMRDY 6141 // Description : Indicates whether the software executing when the PE allocated 6142 // the floating-point stack frame was able to set the MemManage 6143 // exception to pending 6144 #define M33_FPCCR_MMRDY_RESET _u(0x1) 6145 #define M33_FPCCR_MMRDY_BITS _u(0x00000020) 6146 #define M33_FPCCR_MMRDY_MSB _u(5) 6147 #define M33_FPCCR_MMRDY_LSB _u(5) 6148 #define M33_FPCCR_MMRDY_ACCESS "RW" 6149 // ----------------------------------------------------------------------------- 6150 // Field : M33_FPCCR_HFRDY 6151 // Description : Indicates whether the software executing when the PE allocated 6152 // the floating-point stack frame was able to set the HardFault 6153 // exception to pending 6154 #define M33_FPCCR_HFRDY_RESET _u(0x1) 6155 #define M33_FPCCR_HFRDY_BITS _u(0x00000010) 6156 #define M33_FPCCR_HFRDY_MSB _u(4) 6157 #define M33_FPCCR_HFRDY_LSB _u(4) 6158 #define M33_FPCCR_HFRDY_ACCESS "RW" 6159 // ----------------------------------------------------------------------------- 6160 // Field : M33_FPCCR_THREAD 6161 // Description : Indicates the PE mode when it allocated the floating-point 6162 // stack frame 6163 #define M33_FPCCR_THREAD_RESET _u(0x0) 6164 #define M33_FPCCR_THREAD_BITS _u(0x00000008) 6165 #define M33_FPCCR_THREAD_MSB _u(3) 6166 #define M33_FPCCR_THREAD_LSB _u(3) 6167 #define M33_FPCCR_THREAD_ACCESS "RW" 6168 // ----------------------------------------------------------------------------- 6169 // Field : M33_FPCCR_S 6170 // Description : Security status of the floating-point context. This bit is only 6171 // present in the Secure version of the register, and behaves as 6172 // RAZ/WI when accessed from the Non-secure state. This bit is 6173 // updated whenever lazy state preservation is activated, or when 6174 // a floating-point instruction is executed 6175 #define M33_FPCCR_S_RESET _u(0x0) 6176 #define M33_FPCCR_S_BITS _u(0x00000004) 6177 #define M33_FPCCR_S_MSB _u(2) 6178 #define M33_FPCCR_S_LSB _u(2) 6179 #define M33_FPCCR_S_ACCESS "RW" 6180 // ----------------------------------------------------------------------------- 6181 // Field : M33_FPCCR_USER 6182 // Description : Indicates the privilege level of the software executing when 6183 // the PE allocated the floating-point stack frame 6184 #define M33_FPCCR_USER_RESET _u(0x1) 6185 #define M33_FPCCR_USER_BITS _u(0x00000002) 6186 #define M33_FPCCR_USER_MSB _u(1) 6187 #define M33_FPCCR_USER_LSB _u(1) 6188 #define M33_FPCCR_USER_ACCESS "RW" 6189 // ----------------------------------------------------------------------------- 6190 // Field : M33_FPCCR_LSPACT 6191 // Description : Indicates whether lazy preservation of the floating-point state 6192 // is active 6193 #define M33_FPCCR_LSPACT_RESET _u(0x0) 6194 #define M33_FPCCR_LSPACT_BITS _u(0x00000001) 6195 #define M33_FPCCR_LSPACT_MSB _u(0) 6196 #define M33_FPCCR_LSPACT_LSB _u(0) 6197 #define M33_FPCCR_LSPACT_ACCESS "RW" 6198 // ============================================================================= 6199 // Register : M33_FPCAR 6200 // Description : Holds the location of the unpopulated floating-point register 6201 // space allocated on an exception stack frame 6202 #define M33_FPCAR_OFFSET _u(0x0000ef38) 6203 #define M33_FPCAR_BITS _u(0xfffffff8) 6204 #define M33_FPCAR_RESET _u(0x00000000) 6205 // ----------------------------------------------------------------------------- 6206 // Field : M33_FPCAR_ADDRESS 6207 // Description : The location of the unpopulated floating-point register space 6208 // allocated on an exception stack frame 6209 #define M33_FPCAR_ADDRESS_RESET _u(0x00000000) 6210 #define M33_FPCAR_ADDRESS_BITS _u(0xfffffff8) 6211 #define M33_FPCAR_ADDRESS_MSB _u(31) 6212 #define M33_FPCAR_ADDRESS_LSB _u(3) 6213 #define M33_FPCAR_ADDRESS_ACCESS "RW" 6214 // ============================================================================= 6215 // Register : M33_FPDSCR 6216 // Description : Holds the default values for the floating-point status control 6217 // data that the PE assigns to the FPSCR when it creates a new 6218 // floating-point context 6219 #define M33_FPDSCR_OFFSET _u(0x0000ef3c) 6220 #define M33_FPDSCR_BITS _u(0x07c00000) 6221 #define M33_FPDSCR_RESET _u(0x00000000) 6222 // ----------------------------------------------------------------------------- 6223 // Field : M33_FPDSCR_AHP 6224 // Description : Default value for FPSCR.AHP 6225 #define M33_FPDSCR_AHP_RESET _u(0x0) 6226 #define M33_FPDSCR_AHP_BITS _u(0x04000000) 6227 #define M33_FPDSCR_AHP_MSB _u(26) 6228 #define M33_FPDSCR_AHP_LSB _u(26) 6229 #define M33_FPDSCR_AHP_ACCESS "RW" 6230 // ----------------------------------------------------------------------------- 6231 // Field : M33_FPDSCR_DN 6232 // Description : Default value for FPSCR.DN 6233 #define M33_FPDSCR_DN_RESET _u(0x0) 6234 #define M33_FPDSCR_DN_BITS _u(0x02000000) 6235 #define M33_FPDSCR_DN_MSB _u(25) 6236 #define M33_FPDSCR_DN_LSB _u(25) 6237 #define M33_FPDSCR_DN_ACCESS "RW" 6238 // ----------------------------------------------------------------------------- 6239 // Field : M33_FPDSCR_FZ 6240 // Description : Default value for FPSCR.FZ 6241 #define M33_FPDSCR_FZ_RESET _u(0x0) 6242 #define M33_FPDSCR_FZ_BITS _u(0x01000000) 6243 #define M33_FPDSCR_FZ_MSB _u(24) 6244 #define M33_FPDSCR_FZ_LSB _u(24) 6245 #define M33_FPDSCR_FZ_ACCESS "RW" 6246 // ----------------------------------------------------------------------------- 6247 // Field : M33_FPDSCR_RMODE 6248 // Description : Default value for FPSCR.RMode 6249 #define M33_FPDSCR_RMODE_RESET _u(0x0) 6250 #define M33_FPDSCR_RMODE_BITS _u(0x00c00000) 6251 #define M33_FPDSCR_RMODE_MSB _u(23) 6252 #define M33_FPDSCR_RMODE_LSB _u(22) 6253 #define M33_FPDSCR_RMODE_ACCESS "RW" 6254 // ============================================================================= 6255 // Register : M33_MVFR0 6256 // Description : Describes the features provided by the Floating-point Extension 6257 #define M33_MVFR0_OFFSET _u(0x0000ef40) 6258 #define M33_MVFR0_BITS _u(0xf0ff0fff) 6259 #define M33_MVFR0_RESET _u(0x60540601) 6260 // ----------------------------------------------------------------------------- 6261 // Field : M33_MVFR0_FPROUND 6262 // Description : Indicates the rounding modes supported by the FP Extension 6263 #define M33_MVFR0_FPROUND_RESET _u(0x6) 6264 #define M33_MVFR0_FPROUND_BITS _u(0xf0000000) 6265 #define M33_MVFR0_FPROUND_MSB _u(31) 6266 #define M33_MVFR0_FPROUND_LSB _u(28) 6267 #define M33_MVFR0_FPROUND_ACCESS "RO" 6268 // ----------------------------------------------------------------------------- 6269 // Field : M33_MVFR0_FPSQRT 6270 // Description : Indicates the support for FP square root operations 6271 #define M33_MVFR0_FPSQRT_RESET _u(0x5) 6272 #define M33_MVFR0_FPSQRT_BITS _u(0x00f00000) 6273 #define M33_MVFR0_FPSQRT_MSB _u(23) 6274 #define M33_MVFR0_FPSQRT_LSB _u(20) 6275 #define M33_MVFR0_FPSQRT_ACCESS "RO" 6276 // ----------------------------------------------------------------------------- 6277 // Field : M33_MVFR0_FPDIVIDE 6278 // Description : Indicates the support for FP divide operations 6279 #define M33_MVFR0_FPDIVIDE_RESET _u(0x4) 6280 #define M33_MVFR0_FPDIVIDE_BITS _u(0x000f0000) 6281 #define M33_MVFR0_FPDIVIDE_MSB _u(19) 6282 #define M33_MVFR0_FPDIVIDE_LSB _u(16) 6283 #define M33_MVFR0_FPDIVIDE_ACCESS "RO" 6284 // ----------------------------------------------------------------------------- 6285 // Field : M33_MVFR0_FPDP 6286 // Description : Indicates support for FP double-precision operations 6287 #define M33_MVFR0_FPDP_RESET _u(0x6) 6288 #define M33_MVFR0_FPDP_BITS _u(0x00000f00) 6289 #define M33_MVFR0_FPDP_MSB _u(11) 6290 #define M33_MVFR0_FPDP_LSB _u(8) 6291 #define M33_MVFR0_FPDP_ACCESS "RO" 6292 // ----------------------------------------------------------------------------- 6293 // Field : M33_MVFR0_FPSP 6294 // Description : Indicates support for FP single-precision operations 6295 #define M33_MVFR0_FPSP_RESET _u(0x0) 6296 #define M33_MVFR0_FPSP_BITS _u(0x000000f0) 6297 #define M33_MVFR0_FPSP_MSB _u(7) 6298 #define M33_MVFR0_FPSP_LSB _u(4) 6299 #define M33_MVFR0_FPSP_ACCESS "RO" 6300 // ----------------------------------------------------------------------------- 6301 // Field : M33_MVFR0_SIMDREG 6302 // Description : Indicates size of FP register file 6303 #define M33_MVFR0_SIMDREG_RESET _u(0x1) 6304 #define M33_MVFR0_SIMDREG_BITS _u(0x0000000f) 6305 #define M33_MVFR0_SIMDREG_MSB _u(3) 6306 #define M33_MVFR0_SIMDREG_LSB _u(0) 6307 #define M33_MVFR0_SIMDREG_ACCESS "RO" 6308 // ============================================================================= 6309 // Register : M33_MVFR1 6310 // Description : Describes the features provided by the Floating-point Extension 6311 #define M33_MVFR1_OFFSET _u(0x0000ef44) 6312 #define M33_MVFR1_BITS _u(0xff0000ff) 6313 #define M33_MVFR1_RESET _u(0x85000089) 6314 // ----------------------------------------------------------------------------- 6315 // Field : M33_MVFR1_FMAC 6316 // Description : Indicates whether the FP Extension implements the fused 6317 // multiply accumulate instructions 6318 #define M33_MVFR1_FMAC_RESET _u(0x8) 6319 #define M33_MVFR1_FMAC_BITS _u(0xf0000000) 6320 #define M33_MVFR1_FMAC_MSB _u(31) 6321 #define M33_MVFR1_FMAC_LSB _u(28) 6322 #define M33_MVFR1_FMAC_ACCESS "RO" 6323 // ----------------------------------------------------------------------------- 6324 // Field : M33_MVFR1_FPHP 6325 // Description : Indicates whether the FP Extension implements half-precision FP 6326 // conversion instructions 6327 #define M33_MVFR1_FPHP_RESET _u(0x5) 6328 #define M33_MVFR1_FPHP_BITS _u(0x0f000000) 6329 #define M33_MVFR1_FPHP_MSB _u(27) 6330 #define M33_MVFR1_FPHP_LSB _u(24) 6331 #define M33_MVFR1_FPHP_ACCESS "RO" 6332 // ----------------------------------------------------------------------------- 6333 // Field : M33_MVFR1_FPDNAN 6334 // Description : Indicates whether the FP hardware implementation supports NaN 6335 // propagation 6336 #define M33_MVFR1_FPDNAN_RESET _u(0x8) 6337 #define M33_MVFR1_FPDNAN_BITS _u(0x000000f0) 6338 #define M33_MVFR1_FPDNAN_MSB _u(7) 6339 #define M33_MVFR1_FPDNAN_LSB _u(4) 6340 #define M33_MVFR1_FPDNAN_ACCESS "RO" 6341 // ----------------------------------------------------------------------------- 6342 // Field : M33_MVFR1_FPFTZ 6343 // Description : Indicates whether subnormals are always flushed-to-zero 6344 #define M33_MVFR1_FPFTZ_RESET _u(0x9) 6345 #define M33_MVFR1_FPFTZ_BITS _u(0x0000000f) 6346 #define M33_MVFR1_FPFTZ_MSB _u(3) 6347 #define M33_MVFR1_FPFTZ_LSB _u(0) 6348 #define M33_MVFR1_FPFTZ_ACCESS "RO" 6349 // ============================================================================= 6350 // Register : M33_MVFR2 6351 // Description : Describes the features provided by the Floating-point Extension 6352 #define M33_MVFR2_OFFSET _u(0x0000ef48) 6353 #define M33_MVFR2_BITS _u(0x000000f0) 6354 #define M33_MVFR2_RESET _u(0x00000060) 6355 // ----------------------------------------------------------------------------- 6356 // Field : M33_MVFR2_FPMISC 6357 // Description : Indicates support for miscellaneous FP features 6358 #define M33_MVFR2_FPMISC_RESET _u(0x6) 6359 #define M33_MVFR2_FPMISC_BITS _u(0x000000f0) 6360 #define M33_MVFR2_FPMISC_MSB _u(7) 6361 #define M33_MVFR2_FPMISC_LSB _u(4) 6362 #define M33_MVFR2_FPMISC_ACCESS "RO" 6363 // ============================================================================= 6364 // Register : M33_DDEVARCH 6365 // Description : Provides CoreSight discovery information for the SCS 6366 #define M33_DDEVARCH_OFFSET _u(0x0000efbc) 6367 #define M33_DDEVARCH_BITS _u(0xffffffff) 6368 #define M33_DDEVARCH_RESET _u(0x47702a04) 6369 // ----------------------------------------------------------------------------- 6370 // Field : M33_DDEVARCH_ARCHITECT 6371 // Description : Defines the architect of the component. Bits [31:28] are the 6372 // JEP106 continuation code (JEP106 bank ID, minus 1) and bits 6373 // [27:21] are the JEP106 ID code. 6374 #define M33_DDEVARCH_ARCHITECT_RESET _u(0x23b) 6375 #define M33_DDEVARCH_ARCHITECT_BITS _u(0xffe00000) 6376 #define M33_DDEVARCH_ARCHITECT_MSB _u(31) 6377 #define M33_DDEVARCH_ARCHITECT_LSB _u(21) 6378 #define M33_DDEVARCH_ARCHITECT_ACCESS "RO" 6379 // ----------------------------------------------------------------------------- 6380 // Field : M33_DDEVARCH_PRESENT 6381 // Description : Defines that the DEVARCH register is present 6382 #define M33_DDEVARCH_PRESENT_RESET _u(0x1) 6383 #define M33_DDEVARCH_PRESENT_BITS _u(0x00100000) 6384 #define M33_DDEVARCH_PRESENT_MSB _u(20) 6385 #define M33_DDEVARCH_PRESENT_LSB _u(20) 6386 #define M33_DDEVARCH_PRESENT_ACCESS "RO" 6387 // ----------------------------------------------------------------------------- 6388 // Field : M33_DDEVARCH_REVISION 6389 // Description : Defines the architecture revision of the component 6390 #define M33_DDEVARCH_REVISION_RESET _u(0x0) 6391 #define M33_DDEVARCH_REVISION_BITS _u(0x000f0000) 6392 #define M33_DDEVARCH_REVISION_MSB _u(19) 6393 #define M33_DDEVARCH_REVISION_LSB _u(16) 6394 #define M33_DDEVARCH_REVISION_ACCESS "RO" 6395 // ----------------------------------------------------------------------------- 6396 // Field : M33_DDEVARCH_ARCHVER 6397 // Description : Defines the architecture version of the component 6398 #define M33_DDEVARCH_ARCHVER_RESET _u(0x2) 6399 #define M33_DDEVARCH_ARCHVER_BITS _u(0x0000f000) 6400 #define M33_DDEVARCH_ARCHVER_MSB _u(15) 6401 #define M33_DDEVARCH_ARCHVER_LSB _u(12) 6402 #define M33_DDEVARCH_ARCHVER_ACCESS "RO" 6403 // ----------------------------------------------------------------------------- 6404 // Field : M33_DDEVARCH_ARCHPART 6405 // Description : Defines the architecture of the component 6406 #define M33_DDEVARCH_ARCHPART_RESET _u(0xa04) 6407 #define M33_DDEVARCH_ARCHPART_BITS _u(0x00000fff) 6408 #define M33_DDEVARCH_ARCHPART_MSB _u(11) 6409 #define M33_DDEVARCH_ARCHPART_LSB _u(0) 6410 #define M33_DDEVARCH_ARCHPART_ACCESS "RO" 6411 // ============================================================================= 6412 // Register : M33_DDEVTYPE 6413 // Description : Provides CoreSight discovery information for the SCS 6414 #define M33_DDEVTYPE_OFFSET _u(0x0000efcc) 6415 #define M33_DDEVTYPE_BITS _u(0x000000ff) 6416 #define M33_DDEVTYPE_RESET _u(0x00000000) 6417 // ----------------------------------------------------------------------------- 6418 // Field : M33_DDEVTYPE_SUB 6419 // Description : Component sub-type 6420 #define M33_DDEVTYPE_SUB_RESET _u(0x0) 6421 #define M33_DDEVTYPE_SUB_BITS _u(0x000000f0) 6422 #define M33_DDEVTYPE_SUB_MSB _u(7) 6423 #define M33_DDEVTYPE_SUB_LSB _u(4) 6424 #define M33_DDEVTYPE_SUB_ACCESS "RO" 6425 // ----------------------------------------------------------------------------- 6426 // Field : M33_DDEVTYPE_MAJOR 6427 // Description : CoreSight major type 6428 #define M33_DDEVTYPE_MAJOR_RESET _u(0x0) 6429 #define M33_DDEVTYPE_MAJOR_BITS _u(0x0000000f) 6430 #define M33_DDEVTYPE_MAJOR_MSB _u(3) 6431 #define M33_DDEVTYPE_MAJOR_LSB _u(0) 6432 #define M33_DDEVTYPE_MAJOR_ACCESS "RO" 6433 // ============================================================================= 6434 // Register : M33_DPIDR4 6435 // Description : Provides CoreSight discovery information for the SCS 6436 #define M33_DPIDR4_OFFSET _u(0x0000efd0) 6437 #define M33_DPIDR4_BITS _u(0x000000ff) 6438 #define M33_DPIDR4_RESET _u(0x00000004) 6439 // ----------------------------------------------------------------------------- 6440 // Field : M33_DPIDR4_SIZE 6441 // Description : See CoreSight Architecture Specification 6442 #define M33_DPIDR4_SIZE_RESET _u(0x0) 6443 #define M33_DPIDR4_SIZE_BITS _u(0x000000f0) 6444 #define M33_DPIDR4_SIZE_MSB _u(7) 6445 #define M33_DPIDR4_SIZE_LSB _u(4) 6446 #define M33_DPIDR4_SIZE_ACCESS "RO" 6447 // ----------------------------------------------------------------------------- 6448 // Field : M33_DPIDR4_DES_2 6449 // Description : See CoreSight Architecture Specification 6450 #define M33_DPIDR4_DES_2_RESET _u(0x4) 6451 #define M33_DPIDR4_DES_2_BITS _u(0x0000000f) 6452 #define M33_DPIDR4_DES_2_MSB _u(3) 6453 #define M33_DPIDR4_DES_2_LSB _u(0) 6454 #define M33_DPIDR4_DES_2_ACCESS "RO" 6455 // ============================================================================= 6456 // Register : M33_DPIDR5 6457 // Description : Provides CoreSight discovery information for the SCS 6458 #define M33_DPIDR5_OFFSET _u(0x0000efd4) 6459 #define M33_DPIDR5_BITS _u(0x00000000) 6460 #define M33_DPIDR5_RESET _u(0x00000000) 6461 #define M33_DPIDR5_MSB _u(31) 6462 #define M33_DPIDR5_LSB _u(0) 6463 #define M33_DPIDR5_ACCESS "RW" 6464 // ============================================================================= 6465 // Register : M33_DPIDR6 6466 // Description : Provides CoreSight discovery information for the SCS 6467 #define M33_DPIDR6_OFFSET _u(0x0000efd8) 6468 #define M33_DPIDR6_BITS _u(0x00000000) 6469 #define M33_DPIDR6_RESET _u(0x00000000) 6470 #define M33_DPIDR6_MSB _u(31) 6471 #define M33_DPIDR6_LSB _u(0) 6472 #define M33_DPIDR6_ACCESS "RW" 6473 // ============================================================================= 6474 // Register : M33_DPIDR7 6475 // Description : Provides CoreSight discovery information for the SCS 6476 #define M33_DPIDR7_OFFSET _u(0x0000efdc) 6477 #define M33_DPIDR7_BITS _u(0x00000000) 6478 #define M33_DPIDR7_RESET _u(0x00000000) 6479 #define M33_DPIDR7_MSB _u(31) 6480 #define M33_DPIDR7_LSB _u(0) 6481 #define M33_DPIDR7_ACCESS "RW" 6482 // ============================================================================= 6483 // Register : M33_DPIDR0 6484 // Description : Provides CoreSight discovery information for the SCS 6485 #define M33_DPIDR0_OFFSET _u(0x0000efe0) 6486 #define M33_DPIDR0_BITS _u(0x000000ff) 6487 #define M33_DPIDR0_RESET _u(0x00000021) 6488 // ----------------------------------------------------------------------------- 6489 // Field : M33_DPIDR0_PART_0 6490 // Description : See CoreSight Architecture Specification 6491 #define M33_DPIDR0_PART_0_RESET _u(0x21) 6492 #define M33_DPIDR0_PART_0_BITS _u(0x000000ff) 6493 #define M33_DPIDR0_PART_0_MSB _u(7) 6494 #define M33_DPIDR0_PART_0_LSB _u(0) 6495 #define M33_DPIDR0_PART_0_ACCESS "RO" 6496 // ============================================================================= 6497 // Register : M33_DPIDR1 6498 // Description : Provides CoreSight discovery information for the SCS 6499 #define M33_DPIDR1_OFFSET _u(0x0000efe4) 6500 #define M33_DPIDR1_BITS _u(0x000000ff) 6501 #define M33_DPIDR1_RESET _u(0x000000bd) 6502 // ----------------------------------------------------------------------------- 6503 // Field : M33_DPIDR1_DES_0 6504 // Description : See CoreSight Architecture Specification 6505 #define M33_DPIDR1_DES_0_RESET _u(0xb) 6506 #define M33_DPIDR1_DES_0_BITS _u(0x000000f0) 6507 #define M33_DPIDR1_DES_0_MSB _u(7) 6508 #define M33_DPIDR1_DES_0_LSB _u(4) 6509 #define M33_DPIDR1_DES_0_ACCESS "RO" 6510 // ----------------------------------------------------------------------------- 6511 // Field : M33_DPIDR1_PART_1 6512 // Description : See CoreSight Architecture Specification 6513 #define M33_DPIDR1_PART_1_RESET _u(0xd) 6514 #define M33_DPIDR1_PART_1_BITS _u(0x0000000f) 6515 #define M33_DPIDR1_PART_1_MSB _u(3) 6516 #define M33_DPIDR1_PART_1_LSB _u(0) 6517 #define M33_DPIDR1_PART_1_ACCESS "RO" 6518 // ============================================================================= 6519 // Register : M33_DPIDR2 6520 // Description : Provides CoreSight discovery information for the SCS 6521 #define M33_DPIDR2_OFFSET _u(0x0000efe8) 6522 #define M33_DPIDR2_BITS _u(0x000000ff) 6523 #define M33_DPIDR2_RESET _u(0x0000000b) 6524 // ----------------------------------------------------------------------------- 6525 // Field : M33_DPIDR2_REVISION 6526 // Description : See CoreSight Architecture Specification 6527 #define M33_DPIDR2_REVISION_RESET _u(0x0) 6528 #define M33_DPIDR2_REVISION_BITS _u(0x000000f0) 6529 #define M33_DPIDR2_REVISION_MSB _u(7) 6530 #define M33_DPIDR2_REVISION_LSB _u(4) 6531 #define M33_DPIDR2_REVISION_ACCESS "RO" 6532 // ----------------------------------------------------------------------------- 6533 // Field : M33_DPIDR2_JEDEC 6534 // Description : See CoreSight Architecture Specification 6535 #define M33_DPIDR2_JEDEC_RESET _u(0x1) 6536 #define M33_DPIDR2_JEDEC_BITS _u(0x00000008) 6537 #define M33_DPIDR2_JEDEC_MSB _u(3) 6538 #define M33_DPIDR2_JEDEC_LSB _u(3) 6539 #define M33_DPIDR2_JEDEC_ACCESS "RO" 6540 // ----------------------------------------------------------------------------- 6541 // Field : M33_DPIDR2_DES_1 6542 // Description : See CoreSight Architecture Specification 6543 #define M33_DPIDR2_DES_1_RESET _u(0x3) 6544 #define M33_DPIDR2_DES_1_BITS _u(0x00000007) 6545 #define M33_DPIDR2_DES_1_MSB _u(2) 6546 #define M33_DPIDR2_DES_1_LSB _u(0) 6547 #define M33_DPIDR2_DES_1_ACCESS "RO" 6548 // ============================================================================= 6549 // Register : M33_DPIDR3 6550 // Description : Provides CoreSight discovery information for the SCS 6551 #define M33_DPIDR3_OFFSET _u(0x0000efec) 6552 #define M33_DPIDR3_BITS _u(0x000000ff) 6553 #define M33_DPIDR3_RESET _u(0x00000000) 6554 // ----------------------------------------------------------------------------- 6555 // Field : M33_DPIDR3_REVAND 6556 // Description : See CoreSight Architecture Specification 6557 #define M33_DPIDR3_REVAND_RESET _u(0x0) 6558 #define M33_DPIDR3_REVAND_BITS _u(0x000000f0) 6559 #define M33_DPIDR3_REVAND_MSB _u(7) 6560 #define M33_DPIDR3_REVAND_LSB _u(4) 6561 #define M33_DPIDR3_REVAND_ACCESS "RO" 6562 // ----------------------------------------------------------------------------- 6563 // Field : M33_DPIDR3_CMOD 6564 // Description : See CoreSight Architecture Specification 6565 #define M33_DPIDR3_CMOD_RESET _u(0x0) 6566 #define M33_DPIDR3_CMOD_BITS _u(0x0000000f) 6567 #define M33_DPIDR3_CMOD_MSB _u(3) 6568 #define M33_DPIDR3_CMOD_LSB _u(0) 6569 #define M33_DPIDR3_CMOD_ACCESS "RO" 6570 // ============================================================================= 6571 // Register : M33_DCIDR0 6572 // Description : Provides CoreSight discovery information for the SCS 6573 #define M33_DCIDR0_OFFSET _u(0x0000eff0) 6574 #define M33_DCIDR0_BITS _u(0x000000ff) 6575 #define M33_DCIDR0_RESET _u(0x0000000d) 6576 // ----------------------------------------------------------------------------- 6577 // Field : M33_DCIDR0_PRMBL_0 6578 // Description : See CoreSight Architecture Specification 6579 #define M33_DCIDR0_PRMBL_0_RESET _u(0x0d) 6580 #define M33_DCIDR0_PRMBL_0_BITS _u(0x000000ff) 6581 #define M33_DCIDR0_PRMBL_0_MSB _u(7) 6582 #define M33_DCIDR0_PRMBL_0_LSB _u(0) 6583 #define M33_DCIDR0_PRMBL_0_ACCESS "RO" 6584 // ============================================================================= 6585 // Register : M33_DCIDR1 6586 // Description : Provides CoreSight discovery information for the SCS 6587 #define M33_DCIDR1_OFFSET _u(0x0000eff4) 6588 #define M33_DCIDR1_BITS _u(0x000000ff) 6589 #define M33_DCIDR1_RESET _u(0x00000090) 6590 // ----------------------------------------------------------------------------- 6591 // Field : M33_DCIDR1_CLASS 6592 // Description : See CoreSight Architecture Specification 6593 #define M33_DCIDR1_CLASS_RESET _u(0x9) 6594 #define M33_DCIDR1_CLASS_BITS _u(0x000000f0) 6595 #define M33_DCIDR1_CLASS_MSB _u(7) 6596 #define M33_DCIDR1_CLASS_LSB _u(4) 6597 #define M33_DCIDR1_CLASS_ACCESS "RO" 6598 // ----------------------------------------------------------------------------- 6599 // Field : M33_DCIDR1_PRMBL_1 6600 // Description : See CoreSight Architecture Specification 6601 #define M33_DCIDR1_PRMBL_1_RESET _u(0x0) 6602 #define M33_DCIDR1_PRMBL_1_BITS _u(0x0000000f) 6603 #define M33_DCIDR1_PRMBL_1_MSB _u(3) 6604 #define M33_DCIDR1_PRMBL_1_LSB _u(0) 6605 #define M33_DCIDR1_PRMBL_1_ACCESS "RO" 6606 // ============================================================================= 6607 // Register : M33_DCIDR2 6608 // Description : Provides CoreSight discovery information for the SCS 6609 #define M33_DCIDR2_OFFSET _u(0x0000eff8) 6610 #define M33_DCIDR2_BITS _u(0x000000ff) 6611 #define M33_DCIDR2_RESET _u(0x00000005) 6612 // ----------------------------------------------------------------------------- 6613 // Field : M33_DCIDR2_PRMBL_2 6614 // Description : See CoreSight Architecture Specification 6615 #define M33_DCIDR2_PRMBL_2_RESET _u(0x05) 6616 #define M33_DCIDR2_PRMBL_2_BITS _u(0x000000ff) 6617 #define M33_DCIDR2_PRMBL_2_MSB _u(7) 6618 #define M33_DCIDR2_PRMBL_2_LSB _u(0) 6619 #define M33_DCIDR2_PRMBL_2_ACCESS "RO" 6620 // ============================================================================= 6621 // Register : M33_DCIDR3 6622 // Description : Provides CoreSight discovery information for the SCS 6623 #define M33_DCIDR3_OFFSET _u(0x0000effc) 6624 #define M33_DCIDR3_BITS _u(0x000000ff) 6625 #define M33_DCIDR3_RESET _u(0x000000b1) 6626 // ----------------------------------------------------------------------------- 6627 // Field : M33_DCIDR3_PRMBL_3 6628 // Description : See CoreSight Architecture Specification 6629 #define M33_DCIDR3_PRMBL_3_RESET _u(0xb1) 6630 #define M33_DCIDR3_PRMBL_3_BITS _u(0x000000ff) 6631 #define M33_DCIDR3_PRMBL_3_MSB _u(7) 6632 #define M33_DCIDR3_PRMBL_3_LSB _u(0) 6633 #define M33_DCIDR3_PRMBL_3_ACCESS "RO" 6634 // ============================================================================= 6635 // Register : M33_TRCPRGCTLR 6636 // Description : Programming Control Register 6637 #define M33_TRCPRGCTLR_OFFSET _u(0x00041004) 6638 #define M33_TRCPRGCTLR_BITS _u(0x00000001) 6639 #define M33_TRCPRGCTLR_RESET _u(0x00000000) 6640 // ----------------------------------------------------------------------------- 6641 // Field : M33_TRCPRGCTLR_EN 6642 // Description : Trace Unit Enable 6643 #define M33_TRCPRGCTLR_EN_RESET _u(0x0) 6644 #define M33_TRCPRGCTLR_EN_BITS _u(0x00000001) 6645 #define M33_TRCPRGCTLR_EN_MSB _u(0) 6646 #define M33_TRCPRGCTLR_EN_LSB _u(0) 6647 #define M33_TRCPRGCTLR_EN_ACCESS "RW" 6648 // ============================================================================= 6649 // Register : M33_TRCSTATR 6650 // Description : The TRCSTATR indicates the ETM-Teal status 6651 #define M33_TRCSTATR_OFFSET _u(0x0004100c) 6652 #define M33_TRCSTATR_BITS _u(0x00000003) 6653 #define M33_TRCSTATR_RESET _u(0x00000000) 6654 // ----------------------------------------------------------------------------- 6655 // Field : M33_TRCSTATR_PMSTABLE 6656 // Description : Indicates whether the ETM-Teal registers are stable and can be 6657 // read 6658 #define M33_TRCSTATR_PMSTABLE_RESET _u(0x0) 6659 #define M33_TRCSTATR_PMSTABLE_BITS _u(0x00000002) 6660 #define M33_TRCSTATR_PMSTABLE_MSB _u(1) 6661 #define M33_TRCSTATR_PMSTABLE_LSB _u(1) 6662 #define M33_TRCSTATR_PMSTABLE_ACCESS "RO" 6663 // ----------------------------------------------------------------------------- 6664 // Field : M33_TRCSTATR_IDLE 6665 // Description : Indicates that the trace unit is inactive 6666 #define M33_TRCSTATR_IDLE_RESET _u(0x0) 6667 #define M33_TRCSTATR_IDLE_BITS _u(0x00000001) 6668 #define M33_TRCSTATR_IDLE_MSB _u(0) 6669 #define M33_TRCSTATR_IDLE_LSB _u(0) 6670 #define M33_TRCSTATR_IDLE_ACCESS "RO" 6671 // ============================================================================= 6672 // Register : M33_TRCCONFIGR 6673 // Description : The TRCCONFIGR sets the basic tracing options for the trace 6674 // unit 6675 #define M33_TRCCONFIGR_OFFSET _u(0x00041010) 6676 #define M33_TRCCONFIGR_BITS _u(0x00001ff8) 6677 #define M33_TRCCONFIGR_RESET _u(0x00000000) 6678 // ----------------------------------------------------------------------------- 6679 // Field : M33_TRCCONFIGR_RS 6680 // Description : Return stack enable 6681 #define M33_TRCCONFIGR_RS_RESET _u(0x0) 6682 #define M33_TRCCONFIGR_RS_BITS _u(0x00001000) 6683 #define M33_TRCCONFIGR_RS_MSB _u(12) 6684 #define M33_TRCCONFIGR_RS_LSB _u(12) 6685 #define M33_TRCCONFIGR_RS_ACCESS "RW" 6686 // ----------------------------------------------------------------------------- 6687 // Field : M33_TRCCONFIGR_TS 6688 // Description : Global timestamp tracing 6689 #define M33_TRCCONFIGR_TS_RESET _u(0x0) 6690 #define M33_TRCCONFIGR_TS_BITS _u(0x00000800) 6691 #define M33_TRCCONFIGR_TS_MSB _u(11) 6692 #define M33_TRCCONFIGR_TS_LSB _u(11) 6693 #define M33_TRCCONFIGR_TS_ACCESS "RW" 6694 // ----------------------------------------------------------------------------- 6695 // Field : M33_TRCCONFIGR_COND 6696 // Description : Conditional instruction tracing 6697 #define M33_TRCCONFIGR_COND_RESET _u(0x00) 6698 #define M33_TRCCONFIGR_COND_BITS _u(0x000007e0) 6699 #define M33_TRCCONFIGR_COND_MSB _u(10) 6700 #define M33_TRCCONFIGR_COND_LSB _u(5) 6701 #define M33_TRCCONFIGR_COND_ACCESS "RW" 6702 // ----------------------------------------------------------------------------- 6703 // Field : M33_TRCCONFIGR_CCI 6704 // Description : Cycle counting in instruction trace 6705 #define M33_TRCCONFIGR_CCI_RESET _u(0x0) 6706 #define M33_TRCCONFIGR_CCI_BITS _u(0x00000010) 6707 #define M33_TRCCONFIGR_CCI_MSB _u(4) 6708 #define M33_TRCCONFIGR_CCI_LSB _u(4) 6709 #define M33_TRCCONFIGR_CCI_ACCESS "RW" 6710 // ----------------------------------------------------------------------------- 6711 // Field : M33_TRCCONFIGR_BB 6712 // Description : Branch broadcast mode 6713 #define M33_TRCCONFIGR_BB_RESET _u(0x0) 6714 #define M33_TRCCONFIGR_BB_BITS _u(0x00000008) 6715 #define M33_TRCCONFIGR_BB_MSB _u(3) 6716 #define M33_TRCCONFIGR_BB_LSB _u(3) 6717 #define M33_TRCCONFIGR_BB_ACCESS "RW" 6718 // ============================================================================= 6719 // Register : M33_TRCEVENTCTL0R 6720 // Description : The TRCEVENTCTL0R controls the tracing of events in the trace 6721 // stream. The events also drive the ETM-Teal external outputs. 6722 #define M33_TRCEVENTCTL0R_OFFSET _u(0x00041020) 6723 #define M33_TRCEVENTCTL0R_BITS _u(0x00008787) 6724 #define M33_TRCEVENTCTL0R_RESET _u(0x00000000) 6725 // ----------------------------------------------------------------------------- 6726 // Field : M33_TRCEVENTCTL0R_TYPE1 6727 // Description : Selects the resource type for event 1 6728 #define M33_TRCEVENTCTL0R_TYPE1_RESET _u(0x0) 6729 #define M33_TRCEVENTCTL0R_TYPE1_BITS _u(0x00008000) 6730 #define M33_TRCEVENTCTL0R_TYPE1_MSB _u(15) 6731 #define M33_TRCEVENTCTL0R_TYPE1_LSB _u(15) 6732 #define M33_TRCEVENTCTL0R_TYPE1_ACCESS "RW" 6733 // ----------------------------------------------------------------------------- 6734 // Field : M33_TRCEVENTCTL0R_SEL1 6735 // Description : Selects the resource number, based on the value of TYPE1: When 6736 // TYPE1 is 0, selects a single selected resource from 0-15 6737 // defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean 6738 // combined resource pair from 0-7 defined by SEL1[2:0] 6739 #define M33_TRCEVENTCTL0R_SEL1_RESET _u(0x0) 6740 #define M33_TRCEVENTCTL0R_SEL1_BITS _u(0x00000700) 6741 #define M33_TRCEVENTCTL0R_SEL1_MSB _u(10) 6742 #define M33_TRCEVENTCTL0R_SEL1_LSB _u(8) 6743 #define M33_TRCEVENTCTL0R_SEL1_ACCESS "RW" 6744 // ----------------------------------------------------------------------------- 6745 // Field : M33_TRCEVENTCTL0R_TYPE0 6746 // Description : Selects the resource type for event 0 6747 #define M33_TRCEVENTCTL0R_TYPE0_RESET _u(0x0) 6748 #define M33_TRCEVENTCTL0R_TYPE0_BITS _u(0x00000080) 6749 #define M33_TRCEVENTCTL0R_TYPE0_MSB _u(7) 6750 #define M33_TRCEVENTCTL0R_TYPE0_LSB _u(7) 6751 #define M33_TRCEVENTCTL0R_TYPE0_ACCESS "RW" 6752 // ----------------------------------------------------------------------------- 6753 // Field : M33_TRCEVENTCTL0R_SEL0 6754 // Description : Selects the resource number, based on the value of TYPE0: When 6755 // TYPE1 is 0, selects a single selected resource from 0-15 6756 // defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean 6757 // combined resource pair from 0-7 defined by SEL0[2:0] 6758 #define M33_TRCEVENTCTL0R_SEL0_RESET _u(0x0) 6759 #define M33_TRCEVENTCTL0R_SEL0_BITS _u(0x00000007) 6760 #define M33_TRCEVENTCTL0R_SEL0_MSB _u(2) 6761 #define M33_TRCEVENTCTL0R_SEL0_LSB _u(0) 6762 #define M33_TRCEVENTCTL0R_SEL0_ACCESS "RW" 6763 // ============================================================================= 6764 // Register : M33_TRCEVENTCTL1R 6765 // Description : The TRCEVENTCTL1R controls how the events selected by 6766 // TRCEVENTCTL0R behave 6767 #define M33_TRCEVENTCTL1R_OFFSET _u(0x00041024) 6768 #define M33_TRCEVENTCTL1R_BITS _u(0x00001803) 6769 #define M33_TRCEVENTCTL1R_RESET _u(0x00000000) 6770 // ----------------------------------------------------------------------------- 6771 // Field : M33_TRCEVENTCTL1R_LPOVERRIDE 6772 // Description : Low power state behavior override 6773 #define M33_TRCEVENTCTL1R_LPOVERRIDE_RESET _u(0x0) 6774 #define M33_TRCEVENTCTL1R_LPOVERRIDE_BITS _u(0x00001000) 6775 #define M33_TRCEVENTCTL1R_LPOVERRIDE_MSB _u(12) 6776 #define M33_TRCEVENTCTL1R_LPOVERRIDE_LSB _u(12) 6777 #define M33_TRCEVENTCTL1R_LPOVERRIDE_ACCESS "RW" 6778 // ----------------------------------------------------------------------------- 6779 // Field : M33_TRCEVENTCTL1R_ATB 6780 // Description : ATB enabled 6781 #define M33_TRCEVENTCTL1R_ATB_RESET _u(0x0) 6782 #define M33_TRCEVENTCTL1R_ATB_BITS _u(0x00000800) 6783 #define M33_TRCEVENTCTL1R_ATB_MSB _u(11) 6784 #define M33_TRCEVENTCTL1R_ATB_LSB _u(11) 6785 #define M33_TRCEVENTCTL1R_ATB_ACCESS "RW" 6786 // ----------------------------------------------------------------------------- 6787 // Field : M33_TRCEVENTCTL1R_INSTEN1 6788 // Description : One bit per event, to enable generation of an event element in 6789 // the instruction trace stream when the selected event occurs 6790 #define M33_TRCEVENTCTL1R_INSTEN1_RESET _u(0x0) 6791 #define M33_TRCEVENTCTL1R_INSTEN1_BITS _u(0x00000002) 6792 #define M33_TRCEVENTCTL1R_INSTEN1_MSB _u(1) 6793 #define M33_TRCEVENTCTL1R_INSTEN1_LSB _u(1) 6794 #define M33_TRCEVENTCTL1R_INSTEN1_ACCESS "RW" 6795 // ----------------------------------------------------------------------------- 6796 // Field : M33_TRCEVENTCTL1R_INSTEN0 6797 // Description : One bit per event, to enable generation of an event element in 6798 // the instruction trace stream when the selected event occurs 6799 #define M33_TRCEVENTCTL1R_INSTEN0_RESET _u(0x0) 6800 #define M33_TRCEVENTCTL1R_INSTEN0_BITS _u(0x00000001) 6801 #define M33_TRCEVENTCTL1R_INSTEN0_MSB _u(0) 6802 #define M33_TRCEVENTCTL1R_INSTEN0_LSB _u(0) 6803 #define M33_TRCEVENTCTL1R_INSTEN0_ACCESS "RW" 6804 // ============================================================================= 6805 // Register : M33_TRCSTALLCTLR 6806 // Description : The TRCSTALLCTLR enables ETM-Teal to stall the processor if the 6807 // ETM-Teal FIFO goes over the programmed level to minimize risk 6808 // of overflow 6809 #define M33_TRCSTALLCTLR_OFFSET _u(0x0004102c) 6810 #define M33_TRCSTALLCTLR_BITS _u(0x0000050c) 6811 #define M33_TRCSTALLCTLR_RESET _u(0x00000000) 6812 // ----------------------------------------------------------------------------- 6813 // Field : M33_TRCSTALLCTLR_INSTPRIORITY 6814 // Description : Reserved, RES0 6815 #define M33_TRCSTALLCTLR_INSTPRIORITY_RESET _u(0x0) 6816 #define M33_TRCSTALLCTLR_INSTPRIORITY_BITS _u(0x00000400) 6817 #define M33_TRCSTALLCTLR_INSTPRIORITY_MSB _u(10) 6818 #define M33_TRCSTALLCTLR_INSTPRIORITY_LSB _u(10) 6819 #define M33_TRCSTALLCTLR_INSTPRIORITY_ACCESS "RO" 6820 // ----------------------------------------------------------------------------- 6821 // Field : M33_TRCSTALLCTLR_ISTALL 6822 // Description : Stall processor based on instruction trace buffer space 6823 #define M33_TRCSTALLCTLR_ISTALL_RESET _u(0x0) 6824 #define M33_TRCSTALLCTLR_ISTALL_BITS _u(0x00000100) 6825 #define M33_TRCSTALLCTLR_ISTALL_MSB _u(8) 6826 #define M33_TRCSTALLCTLR_ISTALL_LSB _u(8) 6827 #define M33_TRCSTALLCTLR_ISTALL_ACCESS "RW" 6828 // ----------------------------------------------------------------------------- 6829 // Field : M33_TRCSTALLCTLR_LEVEL 6830 // Description : Threshold at which stalling becomes active. This provides four 6831 // levels. This level can be varied to optimize the level of 6832 // invasion caused by stalling, balanced against the risk of a 6833 // FIFO overflow 6834 #define M33_TRCSTALLCTLR_LEVEL_RESET _u(0x0) 6835 #define M33_TRCSTALLCTLR_LEVEL_BITS _u(0x0000000c) 6836 #define M33_TRCSTALLCTLR_LEVEL_MSB _u(3) 6837 #define M33_TRCSTALLCTLR_LEVEL_LSB _u(2) 6838 #define M33_TRCSTALLCTLR_LEVEL_ACCESS "RW" 6839 // ============================================================================= 6840 // Register : M33_TRCTSCTLR 6841 // Description : The TRCTSCTLR controls the insertion of global timestamps into 6842 // the trace stream. A timestamp is always inserted into the 6843 // instruction trace stream 6844 #define M33_TRCTSCTLR_OFFSET _u(0x00041030) 6845 #define M33_TRCTSCTLR_BITS _u(0x00000083) 6846 #define M33_TRCTSCTLR_RESET _u(0x00000000) 6847 // ----------------------------------------------------------------------------- 6848 // Field : M33_TRCTSCTLR_TYPE0 6849 // Description : Selects the resource type for event 0 6850 #define M33_TRCTSCTLR_TYPE0_RESET _u(0x0) 6851 #define M33_TRCTSCTLR_TYPE0_BITS _u(0x00000080) 6852 #define M33_TRCTSCTLR_TYPE0_MSB _u(7) 6853 #define M33_TRCTSCTLR_TYPE0_LSB _u(7) 6854 #define M33_TRCTSCTLR_TYPE0_ACCESS "RW" 6855 // ----------------------------------------------------------------------------- 6856 // Field : M33_TRCTSCTLR_SEL0 6857 // Description : Selects the resource number, based on the value of TYPE0: When 6858 // TYPE1 is 0, selects a single selected resource from 0-15 6859 // defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean 6860 // combined resource pair from 0-7 defined by SEL0[2:0] 6861 #define M33_TRCTSCTLR_SEL0_RESET _u(0x0) 6862 #define M33_TRCTSCTLR_SEL0_BITS _u(0x00000003) 6863 #define M33_TRCTSCTLR_SEL0_MSB _u(1) 6864 #define M33_TRCTSCTLR_SEL0_LSB _u(0) 6865 #define M33_TRCTSCTLR_SEL0_ACCESS "RW" 6866 // ============================================================================= 6867 // Register : M33_TRCSYNCPR 6868 // Description : The TRCSYNCPR specifies the period of trace synchronization of 6869 // the trace streams. TRCSYNCPR defines a number of bytes of trace 6870 // between requests for trace synchronization. This value is 6871 // always a power of two 6872 #define M33_TRCSYNCPR_OFFSET _u(0x00041034) 6873 #define M33_TRCSYNCPR_BITS _u(0x0000001f) 6874 #define M33_TRCSYNCPR_RESET _u(0x0000000a) 6875 // ----------------------------------------------------------------------------- 6876 // Field : M33_TRCSYNCPR_PERIOD 6877 // Description : Defines the number of bytes of trace between trace 6878 // synchronization requests as a total of the number of bytes 6879 // generated by the instruction stream. The number of bytes is 2N 6880 // where N is the value of this field: - A value of zero disables 6881 // these periodic trace synchronization requests, but does not 6882 // disable other trace synchronization requests. - The minimum 6883 // value that can be programmed, other than zero, is 8, providing 6884 // a minimum trace synchronization period of 256 bytes. - The 6885 // maximum value is 20, providing a maximum trace synchronization 6886 // period of 2^20 bytes 6887 #define M33_TRCSYNCPR_PERIOD_RESET _u(0x0a) 6888 #define M33_TRCSYNCPR_PERIOD_BITS _u(0x0000001f) 6889 #define M33_TRCSYNCPR_PERIOD_MSB _u(4) 6890 #define M33_TRCSYNCPR_PERIOD_LSB _u(0) 6891 #define M33_TRCSYNCPR_PERIOD_ACCESS "RO" 6892 // ============================================================================= 6893 // Register : M33_TRCCCCTLR 6894 // Description : The TRCCCCTLR sets the threshold value for instruction trace 6895 // cycle counting. The threshold represents the minimum interval 6896 // between cycle count trace packets 6897 #define M33_TRCCCCTLR_OFFSET _u(0x00041038) 6898 #define M33_TRCCCCTLR_BITS _u(0x00000fff) 6899 #define M33_TRCCCCTLR_RESET _u(0x00000000) 6900 // ----------------------------------------------------------------------------- 6901 // Field : M33_TRCCCCTLR_THRESHOLD 6902 // Description : Instruction trace cycle count threshold 6903 #define M33_TRCCCCTLR_THRESHOLD_RESET _u(0x000) 6904 #define M33_TRCCCCTLR_THRESHOLD_BITS _u(0x00000fff) 6905 #define M33_TRCCCCTLR_THRESHOLD_MSB _u(11) 6906 #define M33_TRCCCCTLR_THRESHOLD_LSB _u(0) 6907 #define M33_TRCCCCTLR_THRESHOLD_ACCESS "RW" 6908 // ============================================================================= 6909 // Register : M33_TRCVICTLR 6910 // Description : The TRCVICTLR controls instruction trace filtering 6911 #define M33_TRCVICTLR_OFFSET _u(0x00041080) 6912 #define M33_TRCVICTLR_BITS _u(0x00090e83) 6913 #define M33_TRCVICTLR_RESET _u(0x00000000) 6914 // ----------------------------------------------------------------------------- 6915 // Field : M33_TRCVICTLR_EXLEVEL_S3 6916 // Description : In Secure state, each bit controls whether instruction tracing 6917 // is enabled for the corresponding exception level 6918 #define M33_TRCVICTLR_EXLEVEL_S3_RESET _u(0x0) 6919 #define M33_TRCVICTLR_EXLEVEL_S3_BITS _u(0x00080000) 6920 #define M33_TRCVICTLR_EXLEVEL_S3_MSB _u(19) 6921 #define M33_TRCVICTLR_EXLEVEL_S3_LSB _u(19) 6922 #define M33_TRCVICTLR_EXLEVEL_S3_ACCESS "RW" 6923 // ----------------------------------------------------------------------------- 6924 // Field : M33_TRCVICTLR_EXLEVEL_S0 6925 // Description : In Secure state, each bit controls whether instruction tracing 6926 // is enabled for the corresponding exception level 6927 #define M33_TRCVICTLR_EXLEVEL_S0_RESET _u(0x0) 6928 #define M33_TRCVICTLR_EXLEVEL_S0_BITS _u(0x00010000) 6929 #define M33_TRCVICTLR_EXLEVEL_S0_MSB _u(16) 6930 #define M33_TRCVICTLR_EXLEVEL_S0_LSB _u(16) 6931 #define M33_TRCVICTLR_EXLEVEL_S0_ACCESS "RW" 6932 // ----------------------------------------------------------------------------- 6933 // Field : M33_TRCVICTLR_TRCERR 6934 // Description : Selects whether a system error exception must always be traced 6935 #define M33_TRCVICTLR_TRCERR_RESET _u(0x0) 6936 #define M33_TRCVICTLR_TRCERR_BITS _u(0x00000800) 6937 #define M33_TRCVICTLR_TRCERR_MSB _u(11) 6938 #define M33_TRCVICTLR_TRCERR_LSB _u(11) 6939 #define M33_TRCVICTLR_TRCERR_ACCESS "RW" 6940 // ----------------------------------------------------------------------------- 6941 // Field : M33_TRCVICTLR_TRCRESET 6942 // Description : Selects whether a reset exception must always be traced 6943 #define M33_TRCVICTLR_TRCRESET_RESET _u(0x0) 6944 #define M33_TRCVICTLR_TRCRESET_BITS _u(0x00000400) 6945 #define M33_TRCVICTLR_TRCRESET_MSB _u(10) 6946 #define M33_TRCVICTLR_TRCRESET_LSB _u(10) 6947 #define M33_TRCVICTLR_TRCRESET_ACCESS "RW" 6948 // ----------------------------------------------------------------------------- 6949 // Field : M33_TRCVICTLR_SSSTATUS 6950 // Description : Indicates the current status of the start/stop logic 6951 #define M33_TRCVICTLR_SSSTATUS_RESET _u(0x0) 6952 #define M33_TRCVICTLR_SSSTATUS_BITS _u(0x00000200) 6953 #define M33_TRCVICTLR_SSSTATUS_MSB _u(9) 6954 #define M33_TRCVICTLR_SSSTATUS_LSB _u(9) 6955 #define M33_TRCVICTLR_SSSTATUS_ACCESS "RW" 6956 // ----------------------------------------------------------------------------- 6957 // Field : M33_TRCVICTLR_TYPE0 6958 // Description : Selects the resource type for event 0 6959 #define M33_TRCVICTLR_TYPE0_RESET _u(0x0) 6960 #define M33_TRCVICTLR_TYPE0_BITS _u(0x00000080) 6961 #define M33_TRCVICTLR_TYPE0_MSB _u(7) 6962 #define M33_TRCVICTLR_TYPE0_LSB _u(7) 6963 #define M33_TRCVICTLR_TYPE0_ACCESS "RW" 6964 // ----------------------------------------------------------------------------- 6965 // Field : M33_TRCVICTLR_SEL0 6966 // Description : Selects the resource number, based on the value of TYPE0: When 6967 // TYPE1 is 0, selects a single selected resource from 0-15 6968 // defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean 6969 // combined resource pair from 0-7 defined by SEL0[2:0] 6970 #define M33_TRCVICTLR_SEL0_RESET _u(0x0) 6971 #define M33_TRCVICTLR_SEL0_BITS _u(0x00000003) 6972 #define M33_TRCVICTLR_SEL0_MSB _u(1) 6973 #define M33_TRCVICTLR_SEL0_LSB _u(0) 6974 #define M33_TRCVICTLR_SEL0_ACCESS "RW" 6975 // ============================================================================= 6976 // Register : M33_TRCCNTRLDVR0 6977 // Description : The TRCCNTRLDVR defines the reload value for the reduced 6978 // function counter 6979 #define M33_TRCCNTRLDVR0_OFFSET _u(0x00041140) 6980 #define M33_TRCCNTRLDVR0_BITS _u(0x0000ffff) 6981 #define M33_TRCCNTRLDVR0_RESET _u(0x00000000) 6982 // ----------------------------------------------------------------------------- 6983 // Field : M33_TRCCNTRLDVR0_VALUE 6984 // Description : Defines the reload value for the counter. This value is loaded 6985 // into the counter each time the reload event occurs 6986 #define M33_TRCCNTRLDVR0_VALUE_RESET _u(0x0000) 6987 #define M33_TRCCNTRLDVR0_VALUE_BITS _u(0x0000ffff) 6988 #define M33_TRCCNTRLDVR0_VALUE_MSB _u(15) 6989 #define M33_TRCCNTRLDVR0_VALUE_LSB _u(0) 6990 #define M33_TRCCNTRLDVR0_VALUE_ACCESS "RW" 6991 // ============================================================================= 6992 // Register : M33_TRCIDR8 6993 // Description : TRCIDR8 6994 #define M33_TRCIDR8_OFFSET _u(0x00041180) 6995 #define M33_TRCIDR8_BITS _u(0xffffffff) 6996 #define M33_TRCIDR8_RESET _u(0x00000000) 6997 // ----------------------------------------------------------------------------- 6998 // Field : M33_TRCIDR8_MAXSPEC 6999 // Description : reads as `ImpDef 7000 #define M33_TRCIDR8_MAXSPEC_RESET _u(0x00000000) 7001 #define M33_TRCIDR8_MAXSPEC_BITS _u(0xffffffff) 7002 #define M33_TRCIDR8_MAXSPEC_MSB _u(31) 7003 #define M33_TRCIDR8_MAXSPEC_LSB _u(0) 7004 #define M33_TRCIDR8_MAXSPEC_ACCESS "RO" 7005 // ============================================================================= 7006 // Register : M33_TRCIDR9 7007 // Description : TRCIDR9 7008 #define M33_TRCIDR9_OFFSET _u(0x00041184) 7009 #define M33_TRCIDR9_BITS _u(0xffffffff) 7010 #define M33_TRCIDR9_RESET _u(0x00000000) 7011 // ----------------------------------------------------------------------------- 7012 // Field : M33_TRCIDR9_NUMP0KEY 7013 // Description : reads as `ImpDef 7014 #define M33_TRCIDR9_NUMP0KEY_RESET _u(0x00000000) 7015 #define M33_TRCIDR9_NUMP0KEY_BITS _u(0xffffffff) 7016 #define M33_TRCIDR9_NUMP0KEY_MSB _u(31) 7017 #define M33_TRCIDR9_NUMP0KEY_LSB _u(0) 7018 #define M33_TRCIDR9_NUMP0KEY_ACCESS "RO" 7019 // ============================================================================= 7020 // Register : M33_TRCIDR10 7021 // Description : TRCIDR10 7022 #define M33_TRCIDR10_OFFSET _u(0x00041188) 7023 #define M33_TRCIDR10_BITS _u(0xffffffff) 7024 #define M33_TRCIDR10_RESET _u(0x00000000) 7025 // ----------------------------------------------------------------------------- 7026 // Field : M33_TRCIDR10_NUMP1KEY 7027 // Description : reads as `ImpDef 7028 #define M33_TRCIDR10_NUMP1KEY_RESET _u(0x00000000) 7029 #define M33_TRCIDR10_NUMP1KEY_BITS _u(0xffffffff) 7030 #define M33_TRCIDR10_NUMP1KEY_MSB _u(31) 7031 #define M33_TRCIDR10_NUMP1KEY_LSB _u(0) 7032 #define M33_TRCIDR10_NUMP1KEY_ACCESS "RO" 7033 // ============================================================================= 7034 // Register : M33_TRCIDR11 7035 // Description : TRCIDR11 7036 #define M33_TRCIDR11_OFFSET _u(0x0004118c) 7037 #define M33_TRCIDR11_BITS _u(0xffffffff) 7038 #define M33_TRCIDR11_RESET _u(0x00000000) 7039 // ----------------------------------------------------------------------------- 7040 // Field : M33_TRCIDR11_NUMP1SPC 7041 // Description : reads as `ImpDef 7042 #define M33_TRCIDR11_NUMP1SPC_RESET _u(0x00000000) 7043 #define M33_TRCIDR11_NUMP1SPC_BITS _u(0xffffffff) 7044 #define M33_TRCIDR11_NUMP1SPC_MSB _u(31) 7045 #define M33_TRCIDR11_NUMP1SPC_LSB _u(0) 7046 #define M33_TRCIDR11_NUMP1SPC_ACCESS "RO" 7047 // ============================================================================= 7048 // Register : M33_TRCIDR12 7049 // Description : TRCIDR12 7050 #define M33_TRCIDR12_OFFSET _u(0x00041190) 7051 #define M33_TRCIDR12_BITS _u(0xffffffff) 7052 #define M33_TRCIDR12_RESET _u(0x00000001) 7053 // ----------------------------------------------------------------------------- 7054 // Field : M33_TRCIDR12_NUMCONDKEY 7055 // Description : reads as `ImpDef 7056 #define M33_TRCIDR12_NUMCONDKEY_RESET _u(0x00000001) 7057 #define M33_TRCIDR12_NUMCONDKEY_BITS _u(0xffffffff) 7058 #define M33_TRCIDR12_NUMCONDKEY_MSB _u(31) 7059 #define M33_TRCIDR12_NUMCONDKEY_LSB _u(0) 7060 #define M33_TRCIDR12_NUMCONDKEY_ACCESS "RO" 7061 // ============================================================================= 7062 // Register : M33_TRCIDR13 7063 // Description : TRCIDR13 7064 #define M33_TRCIDR13_OFFSET _u(0x00041194) 7065 #define M33_TRCIDR13_BITS _u(0xffffffff) 7066 #define M33_TRCIDR13_RESET _u(0x00000000) 7067 // ----------------------------------------------------------------------------- 7068 // Field : M33_TRCIDR13_NUMCONDSPC 7069 // Description : reads as `ImpDef 7070 #define M33_TRCIDR13_NUMCONDSPC_RESET _u(0x00000000) 7071 #define M33_TRCIDR13_NUMCONDSPC_BITS _u(0xffffffff) 7072 #define M33_TRCIDR13_NUMCONDSPC_MSB _u(31) 7073 #define M33_TRCIDR13_NUMCONDSPC_LSB _u(0) 7074 #define M33_TRCIDR13_NUMCONDSPC_ACCESS "RO" 7075 // ============================================================================= 7076 // Register : M33_TRCIMSPEC 7077 // Description : The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC 7078 // features, and enables any features that are provided 7079 #define M33_TRCIMSPEC_OFFSET _u(0x000411c0) 7080 #define M33_TRCIMSPEC_BITS _u(0x0000000f) 7081 #define M33_TRCIMSPEC_RESET _u(0x00000000) 7082 // ----------------------------------------------------------------------------- 7083 // Field : M33_TRCIMSPEC_SUPPORT 7084 // Description : Reserved, RES0 7085 #define M33_TRCIMSPEC_SUPPORT_RESET _u(0x0) 7086 #define M33_TRCIMSPEC_SUPPORT_BITS _u(0x0000000f) 7087 #define M33_TRCIMSPEC_SUPPORT_MSB _u(3) 7088 #define M33_TRCIMSPEC_SUPPORT_LSB _u(0) 7089 #define M33_TRCIMSPEC_SUPPORT_ACCESS "RO" 7090 // ============================================================================= 7091 // Register : M33_TRCIDR0 7092 // Description : TRCIDR0 7093 #define M33_TRCIDR0_OFFSET _u(0x000411e0) 7094 #define M33_TRCIDR0_BITS _u(0x3f03feff) 7095 #define M33_TRCIDR0_RESET _u(0x280006e1) 7096 // ----------------------------------------------------------------------------- 7097 // Field : M33_TRCIDR0_COMMOPT 7098 // Description : reads as `ImpDef 7099 #define M33_TRCIDR0_COMMOPT_RESET _u(0x1) 7100 #define M33_TRCIDR0_COMMOPT_BITS _u(0x20000000) 7101 #define M33_TRCIDR0_COMMOPT_MSB _u(29) 7102 #define M33_TRCIDR0_COMMOPT_LSB _u(29) 7103 #define M33_TRCIDR0_COMMOPT_ACCESS "RO" 7104 // ----------------------------------------------------------------------------- 7105 // Field : M33_TRCIDR0_TSSIZE 7106 // Description : reads as `ImpDef 7107 #define M33_TRCIDR0_TSSIZE_RESET _u(0x08) 7108 #define M33_TRCIDR0_TSSIZE_BITS _u(0x1f000000) 7109 #define M33_TRCIDR0_TSSIZE_MSB _u(28) 7110 #define M33_TRCIDR0_TSSIZE_LSB _u(24) 7111 #define M33_TRCIDR0_TSSIZE_ACCESS "RO" 7112 // ----------------------------------------------------------------------------- 7113 // Field : M33_TRCIDR0_TRCEXDATA 7114 // Description : reads as `ImpDef 7115 #define M33_TRCIDR0_TRCEXDATA_RESET _u(0x0) 7116 #define M33_TRCIDR0_TRCEXDATA_BITS _u(0x00020000) 7117 #define M33_TRCIDR0_TRCEXDATA_MSB _u(17) 7118 #define M33_TRCIDR0_TRCEXDATA_LSB _u(17) 7119 #define M33_TRCIDR0_TRCEXDATA_ACCESS "RO" 7120 // ----------------------------------------------------------------------------- 7121 // Field : M33_TRCIDR0_QSUPP 7122 // Description : reads as `ImpDef 7123 #define M33_TRCIDR0_QSUPP_RESET _u(0x0) 7124 #define M33_TRCIDR0_QSUPP_BITS _u(0x00018000) 7125 #define M33_TRCIDR0_QSUPP_MSB _u(16) 7126 #define M33_TRCIDR0_QSUPP_LSB _u(15) 7127 #define M33_TRCIDR0_QSUPP_ACCESS "RO" 7128 // ----------------------------------------------------------------------------- 7129 // Field : M33_TRCIDR0_QFILT 7130 // Description : reads as `ImpDef 7131 #define M33_TRCIDR0_QFILT_RESET _u(0x0) 7132 #define M33_TRCIDR0_QFILT_BITS _u(0x00004000) 7133 #define M33_TRCIDR0_QFILT_MSB _u(14) 7134 #define M33_TRCIDR0_QFILT_LSB _u(14) 7135 #define M33_TRCIDR0_QFILT_ACCESS "RO" 7136 // ----------------------------------------------------------------------------- 7137 // Field : M33_TRCIDR0_CONDTYPE 7138 // Description : reads as `ImpDef 7139 #define M33_TRCIDR0_CONDTYPE_RESET _u(0x0) 7140 #define M33_TRCIDR0_CONDTYPE_BITS _u(0x00003000) 7141 #define M33_TRCIDR0_CONDTYPE_MSB _u(13) 7142 #define M33_TRCIDR0_CONDTYPE_LSB _u(12) 7143 #define M33_TRCIDR0_CONDTYPE_ACCESS "RO" 7144 // ----------------------------------------------------------------------------- 7145 // Field : M33_TRCIDR0_NUMEVENT 7146 // Description : reads as `ImpDef 7147 #define M33_TRCIDR0_NUMEVENT_RESET _u(0x1) 7148 #define M33_TRCIDR0_NUMEVENT_BITS _u(0x00000c00) 7149 #define M33_TRCIDR0_NUMEVENT_MSB _u(11) 7150 #define M33_TRCIDR0_NUMEVENT_LSB _u(10) 7151 #define M33_TRCIDR0_NUMEVENT_ACCESS "RO" 7152 // ----------------------------------------------------------------------------- 7153 // Field : M33_TRCIDR0_RETSTACK 7154 // Description : reads as `ImpDef 7155 #define M33_TRCIDR0_RETSTACK_RESET _u(0x1) 7156 #define M33_TRCIDR0_RETSTACK_BITS _u(0x00000200) 7157 #define M33_TRCIDR0_RETSTACK_MSB _u(9) 7158 #define M33_TRCIDR0_RETSTACK_LSB _u(9) 7159 #define M33_TRCIDR0_RETSTACK_ACCESS "RO" 7160 // ----------------------------------------------------------------------------- 7161 // Field : M33_TRCIDR0_TRCCCI 7162 // Description : reads as `ImpDef 7163 #define M33_TRCIDR0_TRCCCI_RESET _u(0x1) 7164 #define M33_TRCIDR0_TRCCCI_BITS _u(0x00000080) 7165 #define M33_TRCIDR0_TRCCCI_MSB _u(7) 7166 #define M33_TRCIDR0_TRCCCI_LSB _u(7) 7167 #define M33_TRCIDR0_TRCCCI_ACCESS "RO" 7168 // ----------------------------------------------------------------------------- 7169 // Field : M33_TRCIDR0_TRCCOND 7170 // Description : reads as `ImpDef 7171 #define M33_TRCIDR0_TRCCOND_RESET _u(0x1) 7172 #define M33_TRCIDR0_TRCCOND_BITS _u(0x00000040) 7173 #define M33_TRCIDR0_TRCCOND_MSB _u(6) 7174 #define M33_TRCIDR0_TRCCOND_LSB _u(6) 7175 #define M33_TRCIDR0_TRCCOND_ACCESS "RO" 7176 // ----------------------------------------------------------------------------- 7177 // Field : M33_TRCIDR0_TRCBB 7178 // Description : reads as `ImpDef 7179 #define M33_TRCIDR0_TRCBB_RESET _u(0x1) 7180 #define M33_TRCIDR0_TRCBB_BITS _u(0x00000020) 7181 #define M33_TRCIDR0_TRCBB_MSB _u(5) 7182 #define M33_TRCIDR0_TRCBB_LSB _u(5) 7183 #define M33_TRCIDR0_TRCBB_ACCESS "RO" 7184 // ----------------------------------------------------------------------------- 7185 // Field : M33_TRCIDR0_TRCDATA 7186 // Description : reads as `ImpDef 7187 #define M33_TRCIDR0_TRCDATA_RESET _u(0x0) 7188 #define M33_TRCIDR0_TRCDATA_BITS _u(0x00000018) 7189 #define M33_TRCIDR0_TRCDATA_MSB _u(4) 7190 #define M33_TRCIDR0_TRCDATA_LSB _u(3) 7191 #define M33_TRCIDR0_TRCDATA_ACCESS "RO" 7192 // ----------------------------------------------------------------------------- 7193 // Field : M33_TRCIDR0_INSTP0 7194 // Description : reads as `ImpDef 7195 #define M33_TRCIDR0_INSTP0_RESET _u(0x0) 7196 #define M33_TRCIDR0_INSTP0_BITS _u(0x00000006) 7197 #define M33_TRCIDR0_INSTP0_MSB _u(2) 7198 #define M33_TRCIDR0_INSTP0_LSB _u(1) 7199 #define M33_TRCIDR0_INSTP0_ACCESS "RO" 7200 // ----------------------------------------------------------------------------- 7201 // Field : M33_TRCIDR0_RES1 7202 // Description : Reserved, RES1 7203 #define M33_TRCIDR0_RES1_RESET _u(0x1) 7204 #define M33_TRCIDR0_RES1_BITS _u(0x00000001) 7205 #define M33_TRCIDR0_RES1_MSB _u(0) 7206 #define M33_TRCIDR0_RES1_LSB _u(0) 7207 #define M33_TRCIDR0_RES1_ACCESS "RO" 7208 // ============================================================================= 7209 // Register : M33_TRCIDR1 7210 // Description : TRCIDR1 7211 #define M33_TRCIDR1_OFFSET _u(0x000411e4) 7212 #define M33_TRCIDR1_BITS _u(0xff00ffff) 7213 #define M33_TRCIDR1_RESET _u(0x4100f421) 7214 // ----------------------------------------------------------------------------- 7215 // Field : M33_TRCIDR1_DESIGNER 7216 // Description : reads as `ImpDef 7217 #define M33_TRCIDR1_DESIGNER_RESET _u(0x41) 7218 #define M33_TRCIDR1_DESIGNER_BITS _u(0xff000000) 7219 #define M33_TRCIDR1_DESIGNER_MSB _u(31) 7220 #define M33_TRCIDR1_DESIGNER_LSB _u(24) 7221 #define M33_TRCIDR1_DESIGNER_ACCESS "RO" 7222 // ----------------------------------------------------------------------------- 7223 // Field : M33_TRCIDR1_RES1 7224 // Description : Reserved, RES1 7225 #define M33_TRCIDR1_RES1_RESET _u(0xf) 7226 #define M33_TRCIDR1_RES1_BITS _u(0x0000f000) 7227 #define M33_TRCIDR1_RES1_MSB _u(15) 7228 #define M33_TRCIDR1_RES1_LSB _u(12) 7229 #define M33_TRCIDR1_RES1_ACCESS "RO" 7230 // ----------------------------------------------------------------------------- 7231 // Field : M33_TRCIDR1_TRCARCHMAJ 7232 // Description : reads as 0b0100 7233 #define M33_TRCIDR1_TRCARCHMAJ_RESET _u(0x4) 7234 #define M33_TRCIDR1_TRCARCHMAJ_BITS _u(0x00000f00) 7235 #define M33_TRCIDR1_TRCARCHMAJ_MSB _u(11) 7236 #define M33_TRCIDR1_TRCARCHMAJ_LSB _u(8) 7237 #define M33_TRCIDR1_TRCARCHMAJ_ACCESS "RO" 7238 // ----------------------------------------------------------------------------- 7239 // Field : M33_TRCIDR1_TRCARCHMIN 7240 // Description : reads as 0b0000 7241 #define M33_TRCIDR1_TRCARCHMIN_RESET _u(0x2) 7242 #define M33_TRCIDR1_TRCARCHMIN_BITS _u(0x000000f0) 7243 #define M33_TRCIDR1_TRCARCHMIN_MSB _u(7) 7244 #define M33_TRCIDR1_TRCARCHMIN_LSB _u(4) 7245 #define M33_TRCIDR1_TRCARCHMIN_ACCESS "RO" 7246 // ----------------------------------------------------------------------------- 7247 // Field : M33_TRCIDR1_REVISION 7248 // Description : reads as `ImpDef 7249 #define M33_TRCIDR1_REVISION_RESET _u(0x1) 7250 #define M33_TRCIDR1_REVISION_BITS _u(0x0000000f) 7251 #define M33_TRCIDR1_REVISION_MSB _u(3) 7252 #define M33_TRCIDR1_REVISION_LSB _u(0) 7253 #define M33_TRCIDR1_REVISION_ACCESS "RO" 7254 // ============================================================================= 7255 // Register : M33_TRCIDR2 7256 // Description : TRCIDR2 7257 #define M33_TRCIDR2_OFFSET _u(0x000411e8) 7258 #define M33_TRCIDR2_BITS _u(0x1fffffff) 7259 #define M33_TRCIDR2_RESET _u(0x00000004) 7260 // ----------------------------------------------------------------------------- 7261 // Field : M33_TRCIDR2_CCSIZE 7262 // Description : reads as `ImpDef 7263 #define M33_TRCIDR2_CCSIZE_RESET _u(0x0) 7264 #define M33_TRCIDR2_CCSIZE_BITS _u(0x1e000000) 7265 #define M33_TRCIDR2_CCSIZE_MSB _u(28) 7266 #define M33_TRCIDR2_CCSIZE_LSB _u(25) 7267 #define M33_TRCIDR2_CCSIZE_ACCESS "RO" 7268 // ----------------------------------------------------------------------------- 7269 // Field : M33_TRCIDR2_DVSIZE 7270 // Description : reads as `ImpDef 7271 #define M33_TRCIDR2_DVSIZE_RESET _u(0x00) 7272 #define M33_TRCIDR2_DVSIZE_BITS _u(0x01f00000) 7273 #define M33_TRCIDR2_DVSIZE_MSB _u(24) 7274 #define M33_TRCIDR2_DVSIZE_LSB _u(20) 7275 #define M33_TRCIDR2_DVSIZE_ACCESS "RO" 7276 // ----------------------------------------------------------------------------- 7277 // Field : M33_TRCIDR2_DASIZE 7278 // Description : reads as `ImpDef 7279 #define M33_TRCIDR2_DASIZE_RESET _u(0x00) 7280 #define M33_TRCIDR2_DASIZE_BITS _u(0x000f8000) 7281 #define M33_TRCIDR2_DASIZE_MSB _u(19) 7282 #define M33_TRCIDR2_DASIZE_LSB _u(15) 7283 #define M33_TRCIDR2_DASIZE_ACCESS "RO" 7284 // ----------------------------------------------------------------------------- 7285 // Field : M33_TRCIDR2_VMIDSIZE 7286 // Description : reads as `ImpDef 7287 #define M33_TRCIDR2_VMIDSIZE_RESET _u(0x00) 7288 #define M33_TRCIDR2_VMIDSIZE_BITS _u(0x00007c00) 7289 #define M33_TRCIDR2_VMIDSIZE_MSB _u(14) 7290 #define M33_TRCIDR2_VMIDSIZE_LSB _u(10) 7291 #define M33_TRCIDR2_VMIDSIZE_ACCESS "RO" 7292 // ----------------------------------------------------------------------------- 7293 // Field : M33_TRCIDR2_CIDSIZE 7294 // Description : reads as `ImpDef 7295 #define M33_TRCIDR2_CIDSIZE_RESET _u(0x00) 7296 #define M33_TRCIDR2_CIDSIZE_BITS _u(0x000003e0) 7297 #define M33_TRCIDR2_CIDSIZE_MSB _u(9) 7298 #define M33_TRCIDR2_CIDSIZE_LSB _u(5) 7299 #define M33_TRCIDR2_CIDSIZE_ACCESS "RO" 7300 // ----------------------------------------------------------------------------- 7301 // Field : M33_TRCIDR2_IASIZE 7302 // Description : reads as `ImpDef 7303 #define M33_TRCIDR2_IASIZE_RESET _u(0x04) 7304 #define M33_TRCIDR2_IASIZE_BITS _u(0x0000001f) 7305 #define M33_TRCIDR2_IASIZE_MSB _u(4) 7306 #define M33_TRCIDR2_IASIZE_LSB _u(0) 7307 #define M33_TRCIDR2_IASIZE_ACCESS "RO" 7308 // ============================================================================= 7309 // Register : M33_TRCIDR3 7310 // Description : TRCIDR3 7311 #define M33_TRCIDR3_OFFSET _u(0x000411ec) 7312 #define M33_TRCIDR3_BITS _u(0xffff0fff) 7313 #define M33_TRCIDR3_RESET _u(0x0f090004) 7314 // ----------------------------------------------------------------------------- 7315 // Field : M33_TRCIDR3_NOOVERFLOW 7316 // Description : reads as `ImpDef 7317 #define M33_TRCIDR3_NOOVERFLOW_RESET _u(0x0) 7318 #define M33_TRCIDR3_NOOVERFLOW_BITS _u(0x80000000) 7319 #define M33_TRCIDR3_NOOVERFLOW_MSB _u(31) 7320 #define M33_TRCIDR3_NOOVERFLOW_LSB _u(31) 7321 #define M33_TRCIDR3_NOOVERFLOW_ACCESS "RO" 7322 // ----------------------------------------------------------------------------- 7323 // Field : M33_TRCIDR3_NUMPROC 7324 // Description : reads as `ImpDef 7325 #define M33_TRCIDR3_NUMPROC_RESET _u(0x0) 7326 #define M33_TRCIDR3_NUMPROC_BITS _u(0x70000000) 7327 #define M33_TRCIDR3_NUMPROC_MSB _u(30) 7328 #define M33_TRCIDR3_NUMPROC_LSB _u(28) 7329 #define M33_TRCIDR3_NUMPROC_ACCESS "RO" 7330 // ----------------------------------------------------------------------------- 7331 // Field : M33_TRCIDR3_SYSSTALL 7332 // Description : reads as `ImpDef 7333 #define M33_TRCIDR3_SYSSTALL_RESET _u(0x1) 7334 #define M33_TRCIDR3_SYSSTALL_BITS _u(0x08000000) 7335 #define M33_TRCIDR3_SYSSTALL_MSB _u(27) 7336 #define M33_TRCIDR3_SYSSTALL_LSB _u(27) 7337 #define M33_TRCIDR3_SYSSTALL_ACCESS "RO" 7338 // ----------------------------------------------------------------------------- 7339 // Field : M33_TRCIDR3_STALLCTL 7340 // Description : reads as `ImpDef 7341 #define M33_TRCIDR3_STALLCTL_RESET _u(0x1) 7342 #define M33_TRCIDR3_STALLCTL_BITS _u(0x04000000) 7343 #define M33_TRCIDR3_STALLCTL_MSB _u(26) 7344 #define M33_TRCIDR3_STALLCTL_LSB _u(26) 7345 #define M33_TRCIDR3_STALLCTL_ACCESS "RO" 7346 // ----------------------------------------------------------------------------- 7347 // Field : M33_TRCIDR3_SYNCPR 7348 // Description : reads as `ImpDef 7349 #define M33_TRCIDR3_SYNCPR_RESET _u(0x1) 7350 #define M33_TRCIDR3_SYNCPR_BITS _u(0x02000000) 7351 #define M33_TRCIDR3_SYNCPR_MSB _u(25) 7352 #define M33_TRCIDR3_SYNCPR_LSB _u(25) 7353 #define M33_TRCIDR3_SYNCPR_ACCESS "RO" 7354 // ----------------------------------------------------------------------------- 7355 // Field : M33_TRCIDR3_TRCERR 7356 // Description : reads as `ImpDef 7357 #define M33_TRCIDR3_TRCERR_RESET _u(0x1) 7358 #define M33_TRCIDR3_TRCERR_BITS _u(0x01000000) 7359 #define M33_TRCIDR3_TRCERR_MSB _u(24) 7360 #define M33_TRCIDR3_TRCERR_LSB _u(24) 7361 #define M33_TRCIDR3_TRCERR_ACCESS "RO" 7362 // ----------------------------------------------------------------------------- 7363 // Field : M33_TRCIDR3_EXLEVEL_NS 7364 // Description : reads as `ImpDef 7365 #define M33_TRCIDR3_EXLEVEL_NS_RESET _u(0x0) 7366 #define M33_TRCIDR3_EXLEVEL_NS_BITS _u(0x00f00000) 7367 #define M33_TRCIDR3_EXLEVEL_NS_MSB _u(23) 7368 #define M33_TRCIDR3_EXLEVEL_NS_LSB _u(20) 7369 #define M33_TRCIDR3_EXLEVEL_NS_ACCESS "RO" 7370 // ----------------------------------------------------------------------------- 7371 // Field : M33_TRCIDR3_EXLEVEL_S 7372 // Description : reads as `ImpDef 7373 #define M33_TRCIDR3_EXLEVEL_S_RESET _u(0x9) 7374 #define M33_TRCIDR3_EXLEVEL_S_BITS _u(0x000f0000) 7375 #define M33_TRCIDR3_EXLEVEL_S_MSB _u(19) 7376 #define M33_TRCIDR3_EXLEVEL_S_LSB _u(16) 7377 #define M33_TRCIDR3_EXLEVEL_S_ACCESS "RO" 7378 // ----------------------------------------------------------------------------- 7379 // Field : M33_TRCIDR3_CCITMIN 7380 // Description : reads as `ImpDef 7381 #define M33_TRCIDR3_CCITMIN_RESET _u(0x004) 7382 #define M33_TRCIDR3_CCITMIN_BITS _u(0x00000fff) 7383 #define M33_TRCIDR3_CCITMIN_MSB _u(11) 7384 #define M33_TRCIDR3_CCITMIN_LSB _u(0) 7385 #define M33_TRCIDR3_CCITMIN_ACCESS "RO" 7386 // ============================================================================= 7387 // Register : M33_TRCIDR4 7388 // Description : TRCIDR4 7389 #define M33_TRCIDR4_OFFSET _u(0x000411f0) 7390 #define M33_TRCIDR4_BITS _u(0xfffff1ff) 7391 #define M33_TRCIDR4_RESET _u(0x00114000) 7392 // ----------------------------------------------------------------------------- 7393 // Field : M33_TRCIDR4_NUMVMIDC 7394 // Description : reads as `ImpDef 7395 #define M33_TRCIDR4_NUMVMIDC_RESET _u(0x0) 7396 #define M33_TRCIDR4_NUMVMIDC_BITS _u(0xf0000000) 7397 #define M33_TRCIDR4_NUMVMIDC_MSB _u(31) 7398 #define M33_TRCIDR4_NUMVMIDC_LSB _u(28) 7399 #define M33_TRCIDR4_NUMVMIDC_ACCESS "RO" 7400 // ----------------------------------------------------------------------------- 7401 // Field : M33_TRCIDR4_NUMCIDC 7402 // Description : reads as `ImpDef 7403 #define M33_TRCIDR4_NUMCIDC_RESET _u(0x0) 7404 #define M33_TRCIDR4_NUMCIDC_BITS _u(0x0f000000) 7405 #define M33_TRCIDR4_NUMCIDC_MSB _u(27) 7406 #define M33_TRCIDR4_NUMCIDC_LSB _u(24) 7407 #define M33_TRCIDR4_NUMCIDC_ACCESS "RO" 7408 // ----------------------------------------------------------------------------- 7409 // Field : M33_TRCIDR4_NUMSSCC 7410 // Description : reads as `ImpDef 7411 #define M33_TRCIDR4_NUMSSCC_RESET _u(0x1) 7412 #define M33_TRCIDR4_NUMSSCC_BITS _u(0x00f00000) 7413 #define M33_TRCIDR4_NUMSSCC_MSB _u(23) 7414 #define M33_TRCIDR4_NUMSSCC_LSB _u(20) 7415 #define M33_TRCIDR4_NUMSSCC_ACCESS "RO" 7416 // ----------------------------------------------------------------------------- 7417 // Field : M33_TRCIDR4_NUMRSPAIR 7418 // Description : reads as `ImpDef 7419 #define M33_TRCIDR4_NUMRSPAIR_RESET _u(0x1) 7420 #define M33_TRCIDR4_NUMRSPAIR_BITS _u(0x000f0000) 7421 #define M33_TRCIDR4_NUMRSPAIR_MSB _u(19) 7422 #define M33_TRCIDR4_NUMRSPAIR_LSB _u(16) 7423 #define M33_TRCIDR4_NUMRSPAIR_ACCESS "RO" 7424 // ----------------------------------------------------------------------------- 7425 // Field : M33_TRCIDR4_NUMPC 7426 // Description : reads as `ImpDef 7427 #define M33_TRCIDR4_NUMPC_RESET _u(0x4) 7428 #define M33_TRCIDR4_NUMPC_BITS _u(0x0000f000) 7429 #define M33_TRCIDR4_NUMPC_MSB _u(15) 7430 #define M33_TRCIDR4_NUMPC_LSB _u(12) 7431 #define M33_TRCIDR4_NUMPC_ACCESS "RO" 7432 // ----------------------------------------------------------------------------- 7433 // Field : M33_TRCIDR4_SUPPDAC 7434 // Description : reads as `ImpDef 7435 #define M33_TRCIDR4_SUPPDAC_RESET _u(0x0) 7436 #define M33_TRCIDR4_SUPPDAC_BITS _u(0x00000100) 7437 #define M33_TRCIDR4_SUPPDAC_MSB _u(8) 7438 #define M33_TRCIDR4_SUPPDAC_LSB _u(8) 7439 #define M33_TRCIDR4_SUPPDAC_ACCESS "RO" 7440 // ----------------------------------------------------------------------------- 7441 // Field : M33_TRCIDR4_NUMDVC 7442 // Description : reads as `ImpDef 7443 #define M33_TRCIDR4_NUMDVC_RESET _u(0x0) 7444 #define M33_TRCIDR4_NUMDVC_BITS _u(0x000000f0) 7445 #define M33_TRCIDR4_NUMDVC_MSB _u(7) 7446 #define M33_TRCIDR4_NUMDVC_LSB _u(4) 7447 #define M33_TRCIDR4_NUMDVC_ACCESS "RO" 7448 // ----------------------------------------------------------------------------- 7449 // Field : M33_TRCIDR4_NUMACPAIRS 7450 // Description : reads as `ImpDef 7451 #define M33_TRCIDR4_NUMACPAIRS_RESET _u(0x0) 7452 #define M33_TRCIDR4_NUMACPAIRS_BITS _u(0x0000000f) 7453 #define M33_TRCIDR4_NUMACPAIRS_MSB _u(3) 7454 #define M33_TRCIDR4_NUMACPAIRS_LSB _u(0) 7455 #define M33_TRCIDR4_NUMACPAIRS_ACCESS "RO" 7456 // ============================================================================= 7457 // Register : M33_TRCIDR5 7458 // Description : TRCIDR5 7459 #define M33_TRCIDR5_OFFSET _u(0x000411f4) 7460 #define M33_TRCIDR5_BITS _u(0xfeff0fff) 7461 #define M33_TRCIDR5_RESET _u(0x90c70004) 7462 // ----------------------------------------------------------------------------- 7463 // Field : M33_TRCIDR5_REDFUNCNTR 7464 // Description : reads as `ImpDef 7465 #define M33_TRCIDR5_REDFUNCNTR_RESET _u(0x1) 7466 #define M33_TRCIDR5_REDFUNCNTR_BITS _u(0x80000000) 7467 #define M33_TRCIDR5_REDFUNCNTR_MSB _u(31) 7468 #define M33_TRCIDR5_REDFUNCNTR_LSB _u(31) 7469 #define M33_TRCIDR5_REDFUNCNTR_ACCESS "RO" 7470 // ----------------------------------------------------------------------------- 7471 // Field : M33_TRCIDR5_NUMCNTR 7472 // Description : reads as `ImpDef 7473 #define M33_TRCIDR5_NUMCNTR_RESET _u(0x1) 7474 #define M33_TRCIDR5_NUMCNTR_BITS _u(0x70000000) 7475 #define M33_TRCIDR5_NUMCNTR_MSB _u(30) 7476 #define M33_TRCIDR5_NUMCNTR_LSB _u(28) 7477 #define M33_TRCIDR5_NUMCNTR_ACCESS "RO" 7478 // ----------------------------------------------------------------------------- 7479 // Field : M33_TRCIDR5_NUMSEQSTATE 7480 // Description : reads as `ImpDef 7481 #define M33_TRCIDR5_NUMSEQSTATE_RESET _u(0x0) 7482 #define M33_TRCIDR5_NUMSEQSTATE_BITS _u(0x0e000000) 7483 #define M33_TRCIDR5_NUMSEQSTATE_MSB _u(27) 7484 #define M33_TRCIDR5_NUMSEQSTATE_LSB _u(25) 7485 #define M33_TRCIDR5_NUMSEQSTATE_ACCESS "RO" 7486 // ----------------------------------------------------------------------------- 7487 // Field : M33_TRCIDR5_LPOVERRIDE 7488 // Description : reads as `ImpDef 7489 #define M33_TRCIDR5_LPOVERRIDE_RESET _u(0x1) 7490 #define M33_TRCIDR5_LPOVERRIDE_BITS _u(0x00800000) 7491 #define M33_TRCIDR5_LPOVERRIDE_MSB _u(23) 7492 #define M33_TRCIDR5_LPOVERRIDE_LSB _u(23) 7493 #define M33_TRCIDR5_LPOVERRIDE_ACCESS "RO" 7494 // ----------------------------------------------------------------------------- 7495 // Field : M33_TRCIDR5_ATBTRIG 7496 // Description : reads as `ImpDef 7497 #define M33_TRCIDR5_ATBTRIG_RESET _u(0x1) 7498 #define M33_TRCIDR5_ATBTRIG_BITS _u(0x00400000) 7499 #define M33_TRCIDR5_ATBTRIG_MSB _u(22) 7500 #define M33_TRCIDR5_ATBTRIG_LSB _u(22) 7501 #define M33_TRCIDR5_ATBTRIG_ACCESS "RO" 7502 // ----------------------------------------------------------------------------- 7503 // Field : M33_TRCIDR5_TRACEIDSIZE 7504 // Description : reads as 0x07 7505 #define M33_TRCIDR5_TRACEIDSIZE_RESET _u(0x07) 7506 #define M33_TRCIDR5_TRACEIDSIZE_BITS _u(0x003f0000) 7507 #define M33_TRCIDR5_TRACEIDSIZE_MSB _u(21) 7508 #define M33_TRCIDR5_TRACEIDSIZE_LSB _u(16) 7509 #define M33_TRCIDR5_TRACEIDSIZE_ACCESS "RO" 7510 // ----------------------------------------------------------------------------- 7511 // Field : M33_TRCIDR5_NUMEXTINSEL 7512 // Description : reads as `ImpDef 7513 #define M33_TRCIDR5_NUMEXTINSEL_RESET _u(0x0) 7514 #define M33_TRCIDR5_NUMEXTINSEL_BITS _u(0x00000e00) 7515 #define M33_TRCIDR5_NUMEXTINSEL_MSB _u(11) 7516 #define M33_TRCIDR5_NUMEXTINSEL_LSB _u(9) 7517 #define M33_TRCIDR5_NUMEXTINSEL_ACCESS "RO" 7518 // ----------------------------------------------------------------------------- 7519 // Field : M33_TRCIDR5_NUMEXTIN 7520 // Description : reads as `ImpDef 7521 #define M33_TRCIDR5_NUMEXTIN_RESET _u(0x004) 7522 #define M33_TRCIDR5_NUMEXTIN_BITS _u(0x000001ff) 7523 #define M33_TRCIDR5_NUMEXTIN_MSB _u(8) 7524 #define M33_TRCIDR5_NUMEXTIN_LSB _u(0) 7525 #define M33_TRCIDR5_NUMEXTIN_ACCESS "RO" 7526 // ============================================================================= 7527 // Register : M33_TRCIDR6 7528 // Description : TRCIDR6 7529 #define M33_TRCIDR6_OFFSET _u(0x000411f8) 7530 #define M33_TRCIDR6_BITS _u(0x00000000) 7531 #define M33_TRCIDR6_RESET _u(0x00000000) 7532 #define M33_TRCIDR6_MSB _u(31) 7533 #define M33_TRCIDR6_LSB _u(0) 7534 #define M33_TRCIDR6_ACCESS "RW" 7535 // ============================================================================= 7536 // Register : M33_TRCIDR7 7537 // Description : TRCIDR7 7538 #define M33_TRCIDR7_OFFSET _u(0x000411fc) 7539 #define M33_TRCIDR7_BITS _u(0x00000000) 7540 #define M33_TRCIDR7_RESET _u(0x00000000) 7541 #define M33_TRCIDR7_MSB _u(31) 7542 #define M33_TRCIDR7_LSB _u(0) 7543 #define M33_TRCIDR7_ACCESS "RW" 7544 // ============================================================================= 7545 // Register : M33_TRCRSCTLR2 7546 // Description : The TRCRSCTLR controls the trace resources 7547 #define M33_TRCRSCTLR2_OFFSET _u(0x00041208) 7548 #define M33_TRCRSCTLR2_BITS _u(0x003700ff) 7549 #define M33_TRCRSCTLR2_RESET _u(0x00000000) 7550 // ----------------------------------------------------------------------------- 7551 // Field : M33_TRCRSCTLR2_PAIRINV 7552 // Description : Inverts the result of a combined pair of resources. This bit 7553 // is only implemented on the lower register for a pair of 7554 // resource selectors 7555 #define M33_TRCRSCTLR2_PAIRINV_RESET _u(0x0) 7556 #define M33_TRCRSCTLR2_PAIRINV_BITS _u(0x00200000) 7557 #define M33_TRCRSCTLR2_PAIRINV_MSB _u(21) 7558 #define M33_TRCRSCTLR2_PAIRINV_LSB _u(21) 7559 #define M33_TRCRSCTLR2_PAIRINV_ACCESS "RW" 7560 // ----------------------------------------------------------------------------- 7561 // Field : M33_TRCRSCTLR2_INV 7562 // Description : Inverts the selected resources 7563 #define M33_TRCRSCTLR2_INV_RESET _u(0x0) 7564 #define M33_TRCRSCTLR2_INV_BITS _u(0x00100000) 7565 #define M33_TRCRSCTLR2_INV_MSB _u(20) 7566 #define M33_TRCRSCTLR2_INV_LSB _u(20) 7567 #define M33_TRCRSCTLR2_INV_ACCESS "RW" 7568 // ----------------------------------------------------------------------------- 7569 // Field : M33_TRCRSCTLR2_GROUP 7570 // Description : Selects a group of resource 7571 #define M33_TRCRSCTLR2_GROUP_RESET _u(0x0) 7572 #define M33_TRCRSCTLR2_GROUP_BITS _u(0x00070000) 7573 #define M33_TRCRSCTLR2_GROUP_MSB _u(18) 7574 #define M33_TRCRSCTLR2_GROUP_LSB _u(16) 7575 #define M33_TRCRSCTLR2_GROUP_ACCESS "RW" 7576 // ----------------------------------------------------------------------------- 7577 // Field : M33_TRCRSCTLR2_SELECT 7578 // Description : Selects one or more resources from the wanted group. One bit is 7579 // provided per resource from the group 7580 #define M33_TRCRSCTLR2_SELECT_RESET _u(0x00) 7581 #define M33_TRCRSCTLR2_SELECT_BITS _u(0x000000ff) 7582 #define M33_TRCRSCTLR2_SELECT_MSB _u(7) 7583 #define M33_TRCRSCTLR2_SELECT_LSB _u(0) 7584 #define M33_TRCRSCTLR2_SELECT_ACCESS "RW" 7585 // ============================================================================= 7586 // Register : M33_TRCRSCTLR3 7587 // Description : The TRCRSCTLR controls the trace resources 7588 #define M33_TRCRSCTLR3_OFFSET _u(0x0004120c) 7589 #define M33_TRCRSCTLR3_BITS _u(0x003700ff) 7590 #define M33_TRCRSCTLR3_RESET _u(0x00000000) 7591 // ----------------------------------------------------------------------------- 7592 // Field : M33_TRCRSCTLR3_PAIRINV 7593 // Description : Inverts the result of a combined pair of resources. This bit 7594 // is only implemented on the lower register for a pair of 7595 // resource selectors 7596 #define M33_TRCRSCTLR3_PAIRINV_RESET _u(0x0) 7597 #define M33_TRCRSCTLR3_PAIRINV_BITS _u(0x00200000) 7598 #define M33_TRCRSCTLR3_PAIRINV_MSB _u(21) 7599 #define M33_TRCRSCTLR3_PAIRINV_LSB _u(21) 7600 #define M33_TRCRSCTLR3_PAIRINV_ACCESS "RW" 7601 // ----------------------------------------------------------------------------- 7602 // Field : M33_TRCRSCTLR3_INV 7603 // Description : Inverts the selected resources 7604 #define M33_TRCRSCTLR3_INV_RESET _u(0x0) 7605 #define M33_TRCRSCTLR3_INV_BITS _u(0x00100000) 7606 #define M33_TRCRSCTLR3_INV_MSB _u(20) 7607 #define M33_TRCRSCTLR3_INV_LSB _u(20) 7608 #define M33_TRCRSCTLR3_INV_ACCESS "RW" 7609 // ----------------------------------------------------------------------------- 7610 // Field : M33_TRCRSCTLR3_GROUP 7611 // Description : Selects a group of resource 7612 #define M33_TRCRSCTLR3_GROUP_RESET _u(0x0) 7613 #define M33_TRCRSCTLR3_GROUP_BITS _u(0x00070000) 7614 #define M33_TRCRSCTLR3_GROUP_MSB _u(18) 7615 #define M33_TRCRSCTLR3_GROUP_LSB _u(16) 7616 #define M33_TRCRSCTLR3_GROUP_ACCESS "RW" 7617 // ----------------------------------------------------------------------------- 7618 // Field : M33_TRCRSCTLR3_SELECT 7619 // Description : Selects one or more resources from the wanted group. One bit is 7620 // provided per resource from the group 7621 #define M33_TRCRSCTLR3_SELECT_RESET _u(0x00) 7622 #define M33_TRCRSCTLR3_SELECT_BITS _u(0x000000ff) 7623 #define M33_TRCRSCTLR3_SELECT_MSB _u(7) 7624 #define M33_TRCRSCTLR3_SELECT_LSB _u(0) 7625 #define M33_TRCRSCTLR3_SELECT_ACCESS "RW" 7626 // ============================================================================= 7627 // Register : M33_TRCSSCSR 7628 // Description : Controls the corresponding single-shot comparator resource 7629 #define M33_TRCSSCSR_OFFSET _u(0x000412a0) 7630 #define M33_TRCSSCSR_BITS _u(0x8000000f) 7631 #define M33_TRCSSCSR_RESET _u(0x00000000) 7632 // ----------------------------------------------------------------------------- 7633 // Field : M33_TRCSSCSR_STATUS 7634 // Description : Single-shot status bit. Indicates if any of the comparators, 7635 // that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched 7636 #define M33_TRCSSCSR_STATUS_RESET _u(0x0) 7637 #define M33_TRCSSCSR_STATUS_BITS _u(0x80000000) 7638 #define M33_TRCSSCSR_STATUS_MSB _u(31) 7639 #define M33_TRCSSCSR_STATUS_LSB _u(31) 7640 #define M33_TRCSSCSR_STATUS_ACCESS "RW" 7641 // ----------------------------------------------------------------------------- 7642 // Field : M33_TRCSSCSR_PC 7643 // Description : Reserved, RES1 7644 #define M33_TRCSSCSR_PC_RESET _u(0x0) 7645 #define M33_TRCSSCSR_PC_BITS _u(0x00000008) 7646 #define M33_TRCSSCSR_PC_MSB _u(3) 7647 #define M33_TRCSSCSR_PC_LSB _u(3) 7648 #define M33_TRCSSCSR_PC_ACCESS "RO" 7649 // ----------------------------------------------------------------------------- 7650 // Field : M33_TRCSSCSR_DV 7651 // Description : Reserved, RES0 7652 #define M33_TRCSSCSR_DV_RESET _u(0x0) 7653 #define M33_TRCSSCSR_DV_BITS _u(0x00000004) 7654 #define M33_TRCSSCSR_DV_MSB _u(2) 7655 #define M33_TRCSSCSR_DV_LSB _u(2) 7656 #define M33_TRCSSCSR_DV_ACCESS "RO" 7657 // ----------------------------------------------------------------------------- 7658 // Field : M33_TRCSSCSR_DA 7659 // Description : Reserved, RES0 7660 #define M33_TRCSSCSR_DA_RESET _u(0x0) 7661 #define M33_TRCSSCSR_DA_BITS _u(0x00000002) 7662 #define M33_TRCSSCSR_DA_MSB _u(1) 7663 #define M33_TRCSSCSR_DA_LSB _u(1) 7664 #define M33_TRCSSCSR_DA_ACCESS "RO" 7665 // ----------------------------------------------------------------------------- 7666 // Field : M33_TRCSSCSR_INST 7667 // Description : Reserved, RES0 7668 #define M33_TRCSSCSR_INST_RESET _u(0x0) 7669 #define M33_TRCSSCSR_INST_BITS _u(0x00000001) 7670 #define M33_TRCSSCSR_INST_MSB _u(0) 7671 #define M33_TRCSSCSR_INST_LSB _u(0) 7672 #define M33_TRCSSCSR_INST_ACCESS "RO" 7673 // ============================================================================= 7674 // Register : M33_TRCSSPCICR 7675 // Description : Selects the PE comparator inputs for Single-shot control 7676 #define M33_TRCSSPCICR_OFFSET _u(0x000412c0) 7677 #define M33_TRCSSPCICR_BITS _u(0x0000000f) 7678 #define M33_TRCSSPCICR_RESET _u(0x00000000) 7679 // ----------------------------------------------------------------------------- 7680 // Field : M33_TRCSSPCICR_PC 7681 // Description : Selects one or more PE comparator inputs for Single-shot 7682 // control. TRCIDR4.NUMPC defines the size of the PC field. 1 7683 // bit is provided for each implemented PE comparator input. For 7684 // example, if bit[1] == 1 this selects PE comparator input 1 for 7685 // Single-shot control 7686 #define M33_TRCSSPCICR_PC_RESET _u(0x0) 7687 #define M33_TRCSSPCICR_PC_BITS _u(0x0000000f) 7688 #define M33_TRCSSPCICR_PC_MSB _u(3) 7689 #define M33_TRCSSPCICR_PC_LSB _u(0) 7690 #define M33_TRCSSPCICR_PC_ACCESS "RW" 7691 // ============================================================================= 7692 // Register : M33_TRCPDCR 7693 // Description : Requests the system to provide power to the trace unit 7694 #define M33_TRCPDCR_OFFSET _u(0x00041310) 7695 #define M33_TRCPDCR_BITS _u(0x00000008) 7696 #define M33_TRCPDCR_RESET _u(0x00000000) 7697 // ----------------------------------------------------------------------------- 7698 // Field : M33_TRCPDCR_PU 7699 // Description : Powerup request bit: 7700 #define M33_TRCPDCR_PU_RESET _u(0x0) 7701 #define M33_TRCPDCR_PU_BITS _u(0x00000008) 7702 #define M33_TRCPDCR_PU_MSB _u(3) 7703 #define M33_TRCPDCR_PU_LSB _u(3) 7704 #define M33_TRCPDCR_PU_ACCESS "RW" 7705 // ============================================================================= 7706 // Register : M33_TRCPDSR 7707 // Description : Returns the following information about the trace unit: - OS 7708 // Lock status. - Core power domain status. - Power interruption 7709 // status 7710 #define M33_TRCPDSR_OFFSET _u(0x00041314) 7711 #define M33_TRCPDSR_BITS _u(0x00000023) 7712 #define M33_TRCPDSR_RESET _u(0x00000003) 7713 // ----------------------------------------------------------------------------- 7714 // Field : M33_TRCPDSR_OSLK 7715 // Description : OS Lock status bit: 7716 #define M33_TRCPDSR_OSLK_RESET _u(0x0) 7717 #define M33_TRCPDSR_OSLK_BITS _u(0x00000020) 7718 #define M33_TRCPDSR_OSLK_MSB _u(5) 7719 #define M33_TRCPDSR_OSLK_LSB _u(5) 7720 #define M33_TRCPDSR_OSLK_ACCESS "RO" 7721 // ----------------------------------------------------------------------------- 7722 // Field : M33_TRCPDSR_STICKYPD 7723 // Description : Sticky powerdown status bit. Indicates whether the trace 7724 // register state is valid: 7725 #define M33_TRCPDSR_STICKYPD_RESET _u(0x1) 7726 #define M33_TRCPDSR_STICKYPD_BITS _u(0x00000002) 7727 #define M33_TRCPDSR_STICKYPD_MSB _u(1) 7728 #define M33_TRCPDSR_STICKYPD_LSB _u(1) 7729 #define M33_TRCPDSR_STICKYPD_ACCESS "RO" 7730 // ----------------------------------------------------------------------------- 7731 // Field : M33_TRCPDSR_POWER 7732 // Description : Power status bit: 7733 #define M33_TRCPDSR_POWER_RESET _u(0x1) 7734 #define M33_TRCPDSR_POWER_BITS _u(0x00000001) 7735 #define M33_TRCPDSR_POWER_MSB _u(0) 7736 #define M33_TRCPDSR_POWER_LSB _u(0) 7737 #define M33_TRCPDSR_POWER_ACCESS "RO" 7738 // ============================================================================= 7739 // Register : M33_TRCITATBIDR 7740 // Description : Trace Integration ATB Identification Register 7741 #define M33_TRCITATBIDR_OFFSET _u(0x00041ee4) 7742 #define M33_TRCITATBIDR_BITS _u(0x0000007f) 7743 #define M33_TRCITATBIDR_RESET _u(0x00000000) 7744 // ----------------------------------------------------------------------------- 7745 // Field : M33_TRCITATBIDR_ID 7746 // Description : Trace ID 7747 #define M33_TRCITATBIDR_ID_RESET _u(0x00) 7748 #define M33_TRCITATBIDR_ID_BITS _u(0x0000007f) 7749 #define M33_TRCITATBIDR_ID_MSB _u(6) 7750 #define M33_TRCITATBIDR_ID_LSB _u(0) 7751 #define M33_TRCITATBIDR_ID_ACCESS "RW" 7752 // ============================================================================= 7753 // Register : M33_TRCITIATBINR 7754 // Description : Trace Integration Instruction ATB In Register 7755 #define M33_TRCITIATBINR_OFFSET _u(0x00041ef4) 7756 #define M33_TRCITIATBINR_BITS _u(0x00000003) 7757 #define M33_TRCITIATBINR_RESET _u(0x00000000) 7758 // ----------------------------------------------------------------------------- 7759 // Field : M33_TRCITIATBINR_AFVALIDM 7760 // Description : Integration Mode instruction AFVALIDM in 7761 #define M33_TRCITIATBINR_AFVALIDM_RESET _u(0x0) 7762 #define M33_TRCITIATBINR_AFVALIDM_BITS _u(0x00000002) 7763 #define M33_TRCITIATBINR_AFVALIDM_MSB _u(1) 7764 #define M33_TRCITIATBINR_AFVALIDM_LSB _u(1) 7765 #define M33_TRCITIATBINR_AFVALIDM_ACCESS "RW" 7766 // ----------------------------------------------------------------------------- 7767 // Field : M33_TRCITIATBINR_ATREADYM 7768 // Description : Integration Mode instruction ATREADYM in 7769 #define M33_TRCITIATBINR_ATREADYM_RESET _u(0x0) 7770 #define M33_TRCITIATBINR_ATREADYM_BITS _u(0x00000001) 7771 #define M33_TRCITIATBINR_ATREADYM_MSB _u(0) 7772 #define M33_TRCITIATBINR_ATREADYM_LSB _u(0) 7773 #define M33_TRCITIATBINR_ATREADYM_ACCESS "RW" 7774 // ============================================================================= 7775 // Register : M33_TRCITIATBOUTR 7776 // Description : Trace Integration Instruction ATB Out Register 7777 #define M33_TRCITIATBOUTR_OFFSET _u(0x00041efc) 7778 #define M33_TRCITIATBOUTR_BITS _u(0x00000003) 7779 #define M33_TRCITIATBOUTR_RESET _u(0x00000000) 7780 // ----------------------------------------------------------------------------- 7781 // Field : M33_TRCITIATBOUTR_AFREADY 7782 // Description : Integration Mode instruction AFREADY out 7783 #define M33_TRCITIATBOUTR_AFREADY_RESET _u(0x0) 7784 #define M33_TRCITIATBOUTR_AFREADY_BITS _u(0x00000002) 7785 #define M33_TRCITIATBOUTR_AFREADY_MSB _u(1) 7786 #define M33_TRCITIATBOUTR_AFREADY_LSB _u(1) 7787 #define M33_TRCITIATBOUTR_AFREADY_ACCESS "RW" 7788 // ----------------------------------------------------------------------------- 7789 // Field : M33_TRCITIATBOUTR_ATVALID 7790 // Description : Integration Mode instruction ATVALID out 7791 #define M33_TRCITIATBOUTR_ATVALID_RESET _u(0x0) 7792 #define M33_TRCITIATBOUTR_ATVALID_BITS _u(0x00000001) 7793 #define M33_TRCITIATBOUTR_ATVALID_MSB _u(0) 7794 #define M33_TRCITIATBOUTR_ATVALID_LSB _u(0) 7795 #define M33_TRCITIATBOUTR_ATVALID_ACCESS "RW" 7796 // ============================================================================= 7797 // Register : M33_TRCCLAIMSET 7798 // Description : Claim Tag Set Register 7799 #define M33_TRCCLAIMSET_OFFSET _u(0x00041fa0) 7800 #define M33_TRCCLAIMSET_BITS _u(0x0000000f) 7801 #define M33_TRCCLAIMSET_RESET _u(0x0000000f) 7802 // ----------------------------------------------------------------------------- 7803 // Field : M33_TRCCLAIMSET_SET3 7804 // Description : When a write to one of these bits occurs, with the value: 7805 #define M33_TRCCLAIMSET_SET3_RESET _u(0x1) 7806 #define M33_TRCCLAIMSET_SET3_BITS _u(0x00000008) 7807 #define M33_TRCCLAIMSET_SET3_MSB _u(3) 7808 #define M33_TRCCLAIMSET_SET3_LSB _u(3) 7809 #define M33_TRCCLAIMSET_SET3_ACCESS "RW" 7810 // ----------------------------------------------------------------------------- 7811 // Field : M33_TRCCLAIMSET_SET2 7812 // Description : When a write to one of these bits occurs, with the value: 7813 #define M33_TRCCLAIMSET_SET2_RESET _u(0x1) 7814 #define M33_TRCCLAIMSET_SET2_BITS _u(0x00000004) 7815 #define M33_TRCCLAIMSET_SET2_MSB _u(2) 7816 #define M33_TRCCLAIMSET_SET2_LSB _u(2) 7817 #define M33_TRCCLAIMSET_SET2_ACCESS "RW" 7818 // ----------------------------------------------------------------------------- 7819 // Field : M33_TRCCLAIMSET_SET1 7820 // Description : When a write to one of these bits occurs, with the value: 7821 #define M33_TRCCLAIMSET_SET1_RESET _u(0x1) 7822 #define M33_TRCCLAIMSET_SET1_BITS _u(0x00000002) 7823 #define M33_TRCCLAIMSET_SET1_MSB _u(1) 7824 #define M33_TRCCLAIMSET_SET1_LSB _u(1) 7825 #define M33_TRCCLAIMSET_SET1_ACCESS "RW" 7826 // ----------------------------------------------------------------------------- 7827 // Field : M33_TRCCLAIMSET_SET0 7828 // Description : When a write to one of these bits occurs, with the value: 7829 #define M33_TRCCLAIMSET_SET0_RESET _u(0x1) 7830 #define M33_TRCCLAIMSET_SET0_BITS _u(0x00000001) 7831 #define M33_TRCCLAIMSET_SET0_MSB _u(0) 7832 #define M33_TRCCLAIMSET_SET0_LSB _u(0) 7833 #define M33_TRCCLAIMSET_SET0_ACCESS "RW" 7834 // ============================================================================= 7835 // Register : M33_TRCCLAIMCLR 7836 // Description : Claim Tag Clear Register 7837 #define M33_TRCCLAIMCLR_OFFSET _u(0x00041fa4) 7838 #define M33_TRCCLAIMCLR_BITS _u(0x0000000f) 7839 #define M33_TRCCLAIMCLR_RESET _u(0x00000000) 7840 // ----------------------------------------------------------------------------- 7841 // Field : M33_TRCCLAIMCLR_CLR3 7842 // Description : When a write to one of these bits occurs, with the value: 7843 #define M33_TRCCLAIMCLR_CLR3_RESET _u(0x0) 7844 #define M33_TRCCLAIMCLR_CLR3_BITS _u(0x00000008) 7845 #define M33_TRCCLAIMCLR_CLR3_MSB _u(3) 7846 #define M33_TRCCLAIMCLR_CLR3_LSB _u(3) 7847 #define M33_TRCCLAIMCLR_CLR3_ACCESS "RW" 7848 // ----------------------------------------------------------------------------- 7849 // Field : M33_TRCCLAIMCLR_CLR2 7850 // Description : When a write to one of these bits occurs, with the value: 7851 #define M33_TRCCLAIMCLR_CLR2_RESET _u(0x0) 7852 #define M33_TRCCLAIMCLR_CLR2_BITS _u(0x00000004) 7853 #define M33_TRCCLAIMCLR_CLR2_MSB _u(2) 7854 #define M33_TRCCLAIMCLR_CLR2_LSB _u(2) 7855 #define M33_TRCCLAIMCLR_CLR2_ACCESS "RW" 7856 // ----------------------------------------------------------------------------- 7857 // Field : M33_TRCCLAIMCLR_CLR1 7858 // Description : When a write to one of these bits occurs, with the value: 7859 #define M33_TRCCLAIMCLR_CLR1_RESET _u(0x0) 7860 #define M33_TRCCLAIMCLR_CLR1_BITS _u(0x00000002) 7861 #define M33_TRCCLAIMCLR_CLR1_MSB _u(1) 7862 #define M33_TRCCLAIMCLR_CLR1_LSB _u(1) 7863 #define M33_TRCCLAIMCLR_CLR1_ACCESS "RW" 7864 // ----------------------------------------------------------------------------- 7865 // Field : M33_TRCCLAIMCLR_CLR0 7866 // Description : When a write to one of these bits occurs, with the value: 7867 #define M33_TRCCLAIMCLR_CLR0_RESET _u(0x0) 7868 #define M33_TRCCLAIMCLR_CLR0_BITS _u(0x00000001) 7869 #define M33_TRCCLAIMCLR_CLR0_MSB _u(0) 7870 #define M33_TRCCLAIMCLR_CLR0_LSB _u(0) 7871 #define M33_TRCCLAIMCLR_CLR0_ACCESS "RW" 7872 // ============================================================================= 7873 // Register : M33_TRCAUTHSTATUS 7874 // Description : Returns the level of tracing that the trace unit can support 7875 #define M33_TRCAUTHSTATUS_OFFSET _u(0x00041fb8) 7876 #define M33_TRCAUTHSTATUS_BITS _u(0x000000ff) 7877 #define M33_TRCAUTHSTATUS_RESET _u(0x00000000) 7878 // ----------------------------------------------------------------------------- 7879 // Field : M33_TRCAUTHSTATUS_SNID 7880 // Description : Indicates whether the system enables the trace unit to support 7881 // Secure non-invasive debug: 7882 #define M33_TRCAUTHSTATUS_SNID_RESET _u(0x0) 7883 #define M33_TRCAUTHSTATUS_SNID_BITS _u(0x000000c0) 7884 #define M33_TRCAUTHSTATUS_SNID_MSB _u(7) 7885 #define M33_TRCAUTHSTATUS_SNID_LSB _u(6) 7886 #define M33_TRCAUTHSTATUS_SNID_ACCESS "RO" 7887 // ----------------------------------------------------------------------------- 7888 // Field : M33_TRCAUTHSTATUS_SID 7889 // Description : Indicates whether the trace unit supports Secure invasive 7890 // debug: 7891 #define M33_TRCAUTHSTATUS_SID_RESET _u(0x0) 7892 #define M33_TRCAUTHSTATUS_SID_BITS _u(0x00000030) 7893 #define M33_TRCAUTHSTATUS_SID_MSB _u(5) 7894 #define M33_TRCAUTHSTATUS_SID_LSB _u(4) 7895 #define M33_TRCAUTHSTATUS_SID_ACCESS "RO" 7896 // ----------------------------------------------------------------------------- 7897 // Field : M33_TRCAUTHSTATUS_NSNID 7898 // Description : Indicates whether the system enables the trace unit to support 7899 // Non-secure non-invasive debug: 7900 #define M33_TRCAUTHSTATUS_NSNID_RESET _u(0x0) 7901 #define M33_TRCAUTHSTATUS_NSNID_BITS _u(0x0000000c) 7902 #define M33_TRCAUTHSTATUS_NSNID_MSB _u(3) 7903 #define M33_TRCAUTHSTATUS_NSNID_LSB _u(2) 7904 #define M33_TRCAUTHSTATUS_NSNID_ACCESS "RO" 7905 // ----------------------------------------------------------------------------- 7906 // Field : M33_TRCAUTHSTATUS_NSID 7907 // Description : Indicates whether the trace unit supports Non-secure invasive 7908 // debug: 7909 #define M33_TRCAUTHSTATUS_NSID_RESET _u(0x0) 7910 #define M33_TRCAUTHSTATUS_NSID_BITS _u(0x00000003) 7911 #define M33_TRCAUTHSTATUS_NSID_MSB _u(1) 7912 #define M33_TRCAUTHSTATUS_NSID_LSB _u(0) 7913 #define M33_TRCAUTHSTATUS_NSID_ACCESS "RO" 7914 // ============================================================================= 7915 // Register : M33_TRCDEVARCH 7916 // Description : TRCDEVARCH 7917 #define M33_TRCDEVARCH_OFFSET _u(0x00041fbc) 7918 #define M33_TRCDEVARCH_BITS _u(0xffffffff) 7919 #define M33_TRCDEVARCH_RESET _u(0x47724a13) 7920 // ----------------------------------------------------------------------------- 7921 // Field : M33_TRCDEVARCH_ARCHITECT 7922 // Description : reads as 0b01000111011 7923 #define M33_TRCDEVARCH_ARCHITECT_RESET _u(0x23b) 7924 #define M33_TRCDEVARCH_ARCHITECT_BITS _u(0xffe00000) 7925 #define M33_TRCDEVARCH_ARCHITECT_MSB _u(31) 7926 #define M33_TRCDEVARCH_ARCHITECT_LSB _u(21) 7927 #define M33_TRCDEVARCH_ARCHITECT_ACCESS "RO" 7928 // ----------------------------------------------------------------------------- 7929 // Field : M33_TRCDEVARCH_PRESENT 7930 // Description : reads as 0b1 7931 #define M33_TRCDEVARCH_PRESENT_RESET _u(0x1) 7932 #define M33_TRCDEVARCH_PRESENT_BITS _u(0x00100000) 7933 #define M33_TRCDEVARCH_PRESENT_MSB _u(20) 7934 #define M33_TRCDEVARCH_PRESENT_LSB _u(20) 7935 #define M33_TRCDEVARCH_PRESENT_ACCESS "RO" 7936 // ----------------------------------------------------------------------------- 7937 // Field : M33_TRCDEVARCH_REVISION 7938 // Description : reads as 0b0000 7939 #define M33_TRCDEVARCH_REVISION_RESET _u(0x2) 7940 #define M33_TRCDEVARCH_REVISION_BITS _u(0x000f0000) 7941 #define M33_TRCDEVARCH_REVISION_MSB _u(19) 7942 #define M33_TRCDEVARCH_REVISION_LSB _u(16) 7943 #define M33_TRCDEVARCH_REVISION_ACCESS "RO" 7944 // ----------------------------------------------------------------------------- 7945 // Field : M33_TRCDEVARCH_ARCHID 7946 // Description : reads as 0b0100101000010011 7947 #define M33_TRCDEVARCH_ARCHID_RESET _u(0x4a13) 7948 #define M33_TRCDEVARCH_ARCHID_BITS _u(0x0000ffff) 7949 #define M33_TRCDEVARCH_ARCHID_MSB _u(15) 7950 #define M33_TRCDEVARCH_ARCHID_LSB _u(0) 7951 #define M33_TRCDEVARCH_ARCHID_ACCESS "RO" 7952 // ============================================================================= 7953 // Register : M33_TRCDEVID 7954 // Description : TRCDEVID 7955 #define M33_TRCDEVID_OFFSET _u(0x00041fc8) 7956 #define M33_TRCDEVID_BITS _u(0x00000000) 7957 #define M33_TRCDEVID_RESET _u(0x00000000) 7958 #define M33_TRCDEVID_MSB _u(31) 7959 #define M33_TRCDEVID_LSB _u(0) 7960 #define M33_TRCDEVID_ACCESS "RW" 7961 // ============================================================================= 7962 // Register : M33_TRCDEVTYPE 7963 // Description : TRCDEVTYPE 7964 #define M33_TRCDEVTYPE_OFFSET _u(0x00041fcc) 7965 #define M33_TRCDEVTYPE_BITS _u(0x000000ff) 7966 #define M33_TRCDEVTYPE_RESET _u(0x00000013) 7967 // ----------------------------------------------------------------------------- 7968 // Field : M33_TRCDEVTYPE_SUB 7969 // Description : reads as 0b0001 7970 #define M33_TRCDEVTYPE_SUB_RESET _u(0x1) 7971 #define M33_TRCDEVTYPE_SUB_BITS _u(0x000000f0) 7972 #define M33_TRCDEVTYPE_SUB_MSB _u(7) 7973 #define M33_TRCDEVTYPE_SUB_LSB _u(4) 7974 #define M33_TRCDEVTYPE_SUB_ACCESS "RO" 7975 // ----------------------------------------------------------------------------- 7976 // Field : M33_TRCDEVTYPE_MAJOR 7977 // Description : reads as 0b0011 7978 #define M33_TRCDEVTYPE_MAJOR_RESET _u(0x3) 7979 #define M33_TRCDEVTYPE_MAJOR_BITS _u(0x0000000f) 7980 #define M33_TRCDEVTYPE_MAJOR_MSB _u(3) 7981 #define M33_TRCDEVTYPE_MAJOR_LSB _u(0) 7982 #define M33_TRCDEVTYPE_MAJOR_ACCESS "RO" 7983 // ============================================================================= 7984 // Register : M33_TRCPIDR4 7985 // Description : TRCPIDR4 7986 #define M33_TRCPIDR4_OFFSET _u(0x00041fd0) 7987 #define M33_TRCPIDR4_BITS _u(0x000000ff) 7988 #define M33_TRCPIDR4_RESET _u(0x00000004) 7989 // ----------------------------------------------------------------------------- 7990 // Field : M33_TRCPIDR4_SIZE 7991 // Description : reads as `ImpDef 7992 #define M33_TRCPIDR4_SIZE_RESET _u(0x0) 7993 #define M33_TRCPIDR4_SIZE_BITS _u(0x000000f0) 7994 #define M33_TRCPIDR4_SIZE_MSB _u(7) 7995 #define M33_TRCPIDR4_SIZE_LSB _u(4) 7996 #define M33_TRCPIDR4_SIZE_ACCESS "RO" 7997 // ----------------------------------------------------------------------------- 7998 // Field : M33_TRCPIDR4_DES_2 7999 // Description : reads as `ImpDef 8000 #define M33_TRCPIDR4_DES_2_RESET _u(0x4) 8001 #define M33_TRCPIDR4_DES_2_BITS _u(0x0000000f) 8002 #define M33_TRCPIDR4_DES_2_MSB _u(3) 8003 #define M33_TRCPIDR4_DES_2_LSB _u(0) 8004 #define M33_TRCPIDR4_DES_2_ACCESS "RO" 8005 // ============================================================================= 8006 // Register : M33_TRCPIDR5 8007 // Description : TRCPIDR5 8008 #define M33_TRCPIDR5_OFFSET _u(0x00041fd4) 8009 #define M33_TRCPIDR5_BITS _u(0x00000000) 8010 #define M33_TRCPIDR5_RESET _u(0x00000000) 8011 #define M33_TRCPIDR5_MSB _u(31) 8012 #define M33_TRCPIDR5_LSB _u(0) 8013 #define M33_TRCPIDR5_ACCESS "RW" 8014 // ============================================================================= 8015 // Register : M33_TRCPIDR6 8016 // Description : TRCPIDR6 8017 #define M33_TRCPIDR6_OFFSET _u(0x00041fd8) 8018 #define M33_TRCPIDR6_BITS _u(0x00000000) 8019 #define M33_TRCPIDR6_RESET _u(0x00000000) 8020 #define M33_TRCPIDR6_MSB _u(31) 8021 #define M33_TRCPIDR6_LSB _u(0) 8022 #define M33_TRCPIDR6_ACCESS "RW" 8023 // ============================================================================= 8024 // Register : M33_TRCPIDR7 8025 // Description : TRCPIDR7 8026 #define M33_TRCPIDR7_OFFSET _u(0x00041fdc) 8027 #define M33_TRCPIDR7_BITS _u(0x00000000) 8028 #define M33_TRCPIDR7_RESET _u(0x00000000) 8029 #define M33_TRCPIDR7_MSB _u(31) 8030 #define M33_TRCPIDR7_LSB _u(0) 8031 #define M33_TRCPIDR7_ACCESS "RW" 8032 // ============================================================================= 8033 // Register : M33_TRCPIDR0 8034 // Description : TRCPIDR0 8035 #define M33_TRCPIDR0_OFFSET _u(0x00041fe0) 8036 #define M33_TRCPIDR0_BITS _u(0x000000ff) 8037 #define M33_TRCPIDR0_RESET _u(0x00000021) 8038 // ----------------------------------------------------------------------------- 8039 // Field : M33_TRCPIDR0_PART_0 8040 // Description : reads as `ImpDef 8041 #define M33_TRCPIDR0_PART_0_RESET _u(0x21) 8042 #define M33_TRCPIDR0_PART_0_BITS _u(0x000000ff) 8043 #define M33_TRCPIDR0_PART_0_MSB _u(7) 8044 #define M33_TRCPIDR0_PART_0_LSB _u(0) 8045 #define M33_TRCPIDR0_PART_0_ACCESS "RO" 8046 // ============================================================================= 8047 // Register : M33_TRCPIDR1 8048 // Description : TRCPIDR1 8049 #define M33_TRCPIDR1_OFFSET _u(0x00041fe4) 8050 #define M33_TRCPIDR1_BITS _u(0x000000ff) 8051 #define M33_TRCPIDR1_RESET _u(0x000000bd) 8052 // ----------------------------------------------------------------------------- 8053 // Field : M33_TRCPIDR1_DES_0 8054 // Description : reads as `ImpDef 8055 #define M33_TRCPIDR1_DES_0_RESET _u(0xb) 8056 #define M33_TRCPIDR1_DES_0_BITS _u(0x000000f0) 8057 #define M33_TRCPIDR1_DES_0_MSB _u(7) 8058 #define M33_TRCPIDR1_DES_0_LSB _u(4) 8059 #define M33_TRCPIDR1_DES_0_ACCESS "RO" 8060 // ----------------------------------------------------------------------------- 8061 // Field : M33_TRCPIDR1_PART_0 8062 // Description : reads as `ImpDef 8063 #define M33_TRCPIDR1_PART_0_RESET _u(0xd) 8064 #define M33_TRCPIDR1_PART_0_BITS _u(0x0000000f) 8065 #define M33_TRCPIDR1_PART_0_MSB _u(3) 8066 #define M33_TRCPIDR1_PART_0_LSB _u(0) 8067 #define M33_TRCPIDR1_PART_0_ACCESS "RO" 8068 // ============================================================================= 8069 // Register : M33_TRCPIDR2 8070 // Description : TRCPIDR2 8071 #define M33_TRCPIDR2_OFFSET _u(0x00041fe8) 8072 #define M33_TRCPIDR2_BITS _u(0x000000ff) 8073 #define M33_TRCPIDR2_RESET _u(0x0000002b) 8074 // ----------------------------------------------------------------------------- 8075 // Field : M33_TRCPIDR2_REVISION 8076 // Description : reads as `ImpDef 8077 #define M33_TRCPIDR2_REVISION_RESET _u(0x2) 8078 #define M33_TRCPIDR2_REVISION_BITS _u(0x000000f0) 8079 #define M33_TRCPIDR2_REVISION_MSB _u(7) 8080 #define M33_TRCPIDR2_REVISION_LSB _u(4) 8081 #define M33_TRCPIDR2_REVISION_ACCESS "RO" 8082 // ----------------------------------------------------------------------------- 8083 // Field : M33_TRCPIDR2_JEDEC 8084 // Description : reads as 0b1 8085 #define M33_TRCPIDR2_JEDEC_RESET _u(0x1) 8086 #define M33_TRCPIDR2_JEDEC_BITS _u(0x00000008) 8087 #define M33_TRCPIDR2_JEDEC_MSB _u(3) 8088 #define M33_TRCPIDR2_JEDEC_LSB _u(3) 8089 #define M33_TRCPIDR2_JEDEC_ACCESS "RO" 8090 // ----------------------------------------------------------------------------- 8091 // Field : M33_TRCPIDR2_DES_0 8092 // Description : reads as `ImpDef 8093 #define M33_TRCPIDR2_DES_0_RESET _u(0x3) 8094 #define M33_TRCPIDR2_DES_0_BITS _u(0x00000007) 8095 #define M33_TRCPIDR2_DES_0_MSB _u(2) 8096 #define M33_TRCPIDR2_DES_0_LSB _u(0) 8097 #define M33_TRCPIDR2_DES_0_ACCESS "RO" 8098 // ============================================================================= 8099 // Register : M33_TRCPIDR3 8100 // Description : TRCPIDR3 8101 #define M33_TRCPIDR3_OFFSET _u(0x00041fec) 8102 #define M33_TRCPIDR3_BITS _u(0x000000ff) 8103 #define M33_TRCPIDR3_RESET _u(0x00000000) 8104 // ----------------------------------------------------------------------------- 8105 // Field : M33_TRCPIDR3_REVAND 8106 // Description : reads as `ImpDef 8107 #define M33_TRCPIDR3_REVAND_RESET _u(0x0) 8108 #define M33_TRCPIDR3_REVAND_BITS _u(0x000000f0) 8109 #define M33_TRCPIDR3_REVAND_MSB _u(7) 8110 #define M33_TRCPIDR3_REVAND_LSB _u(4) 8111 #define M33_TRCPIDR3_REVAND_ACCESS "RO" 8112 // ----------------------------------------------------------------------------- 8113 // Field : M33_TRCPIDR3_CMOD 8114 // Description : reads as `ImpDef 8115 #define M33_TRCPIDR3_CMOD_RESET _u(0x0) 8116 #define M33_TRCPIDR3_CMOD_BITS _u(0x0000000f) 8117 #define M33_TRCPIDR3_CMOD_MSB _u(3) 8118 #define M33_TRCPIDR3_CMOD_LSB _u(0) 8119 #define M33_TRCPIDR3_CMOD_ACCESS "RO" 8120 // ============================================================================= 8121 // Register : M33_TRCCIDR0 8122 // Description : TRCCIDR0 8123 #define M33_TRCCIDR0_OFFSET _u(0x00041ff0) 8124 #define M33_TRCCIDR0_BITS _u(0x000000ff) 8125 #define M33_TRCCIDR0_RESET _u(0x0000000d) 8126 // ----------------------------------------------------------------------------- 8127 // Field : M33_TRCCIDR0_PRMBL_0 8128 // Description : reads as 0b00001101 8129 #define M33_TRCCIDR0_PRMBL_0_RESET _u(0x0d) 8130 #define M33_TRCCIDR0_PRMBL_0_BITS _u(0x000000ff) 8131 #define M33_TRCCIDR0_PRMBL_0_MSB _u(7) 8132 #define M33_TRCCIDR0_PRMBL_0_LSB _u(0) 8133 #define M33_TRCCIDR0_PRMBL_0_ACCESS "RO" 8134 // ============================================================================= 8135 // Register : M33_TRCCIDR1 8136 // Description : TRCCIDR1 8137 #define M33_TRCCIDR1_OFFSET _u(0x00041ff4) 8138 #define M33_TRCCIDR1_BITS _u(0x000000ff) 8139 #define M33_TRCCIDR1_RESET _u(0x00000090) 8140 // ----------------------------------------------------------------------------- 8141 // Field : M33_TRCCIDR1_CLASS 8142 // Description : reads as 0b1001 8143 #define M33_TRCCIDR1_CLASS_RESET _u(0x9) 8144 #define M33_TRCCIDR1_CLASS_BITS _u(0x000000f0) 8145 #define M33_TRCCIDR1_CLASS_MSB _u(7) 8146 #define M33_TRCCIDR1_CLASS_LSB _u(4) 8147 #define M33_TRCCIDR1_CLASS_ACCESS "RO" 8148 // ----------------------------------------------------------------------------- 8149 // Field : M33_TRCCIDR1_PRMBL_1 8150 // Description : reads as 0b0000 8151 #define M33_TRCCIDR1_PRMBL_1_RESET _u(0x0) 8152 #define M33_TRCCIDR1_PRMBL_1_BITS _u(0x0000000f) 8153 #define M33_TRCCIDR1_PRMBL_1_MSB _u(3) 8154 #define M33_TRCCIDR1_PRMBL_1_LSB _u(0) 8155 #define M33_TRCCIDR1_PRMBL_1_ACCESS "RO" 8156 // ============================================================================= 8157 // Register : M33_TRCCIDR2 8158 // Description : TRCCIDR2 8159 #define M33_TRCCIDR2_OFFSET _u(0x00041ff8) 8160 #define M33_TRCCIDR2_BITS _u(0x000000ff) 8161 #define M33_TRCCIDR2_RESET _u(0x00000005) 8162 // ----------------------------------------------------------------------------- 8163 // Field : M33_TRCCIDR2_PRMBL_2 8164 // Description : reads as 0b00000101 8165 #define M33_TRCCIDR2_PRMBL_2_RESET _u(0x05) 8166 #define M33_TRCCIDR2_PRMBL_2_BITS _u(0x000000ff) 8167 #define M33_TRCCIDR2_PRMBL_2_MSB _u(7) 8168 #define M33_TRCCIDR2_PRMBL_2_LSB _u(0) 8169 #define M33_TRCCIDR2_PRMBL_2_ACCESS "RO" 8170 // ============================================================================= 8171 // Register : M33_TRCCIDR3 8172 // Description : TRCCIDR3 8173 #define M33_TRCCIDR3_OFFSET _u(0x00041ffc) 8174 #define M33_TRCCIDR3_BITS _u(0x000000ff) 8175 #define M33_TRCCIDR3_RESET _u(0x000000b1) 8176 // ----------------------------------------------------------------------------- 8177 // Field : M33_TRCCIDR3_PRMBL_3 8178 // Description : reads as 0b10110001 8179 #define M33_TRCCIDR3_PRMBL_3_RESET _u(0xb1) 8180 #define M33_TRCCIDR3_PRMBL_3_BITS _u(0x000000ff) 8181 #define M33_TRCCIDR3_PRMBL_3_MSB _u(7) 8182 #define M33_TRCCIDR3_PRMBL_3_LSB _u(0) 8183 #define M33_TRCCIDR3_PRMBL_3_ACCESS "RO" 8184 // ============================================================================= 8185 // Register : M33_CTICONTROL 8186 // Description : CTI Control Register 8187 #define M33_CTICONTROL_OFFSET _u(0x00042000) 8188 #define M33_CTICONTROL_BITS _u(0x00000001) 8189 #define M33_CTICONTROL_RESET _u(0x00000000) 8190 // ----------------------------------------------------------------------------- 8191 // Field : M33_CTICONTROL_GLBEN 8192 // Description : Enables or disables the CTI 8193 #define M33_CTICONTROL_GLBEN_RESET _u(0x0) 8194 #define M33_CTICONTROL_GLBEN_BITS _u(0x00000001) 8195 #define M33_CTICONTROL_GLBEN_MSB _u(0) 8196 #define M33_CTICONTROL_GLBEN_LSB _u(0) 8197 #define M33_CTICONTROL_GLBEN_ACCESS "RW" 8198 // ============================================================================= 8199 // Register : M33_CTIINTACK 8200 // Description : CTI Interrupt Acknowledge Register 8201 #define M33_CTIINTACK_OFFSET _u(0x00042010) 8202 #define M33_CTIINTACK_BITS _u(0x000000ff) 8203 #define M33_CTIINTACK_RESET _u(0x00000000) 8204 // ----------------------------------------------------------------------------- 8205 // Field : M33_CTIINTACK_INTACK 8206 // Description : Acknowledges the corresponding ctitrigout output. There is one 8207 // bit of the register for each ctitrigout output. When a 1 is 8208 // written to a bit in this register, the corresponding ctitrigout 8209 // is acknowledged, causing it to be cleared. 8210 #define M33_CTIINTACK_INTACK_RESET _u(0x00) 8211 #define M33_CTIINTACK_INTACK_BITS _u(0x000000ff) 8212 #define M33_CTIINTACK_INTACK_MSB _u(7) 8213 #define M33_CTIINTACK_INTACK_LSB _u(0) 8214 #define M33_CTIINTACK_INTACK_ACCESS "RW" 8215 // ============================================================================= 8216 // Register : M33_CTIAPPSET 8217 // Description : CTI Application Trigger Set Register 8218 #define M33_CTIAPPSET_OFFSET _u(0x00042014) 8219 #define M33_CTIAPPSET_BITS _u(0x0000000f) 8220 #define M33_CTIAPPSET_RESET _u(0x00000000) 8221 // ----------------------------------------------------------------------------- 8222 // Field : M33_CTIAPPSET_APPSET 8223 // Description : Setting a bit HIGH generates a channel event for the selected 8224 // channel. There is one bit of the register for each channel 8225 #define M33_CTIAPPSET_APPSET_RESET _u(0x0) 8226 #define M33_CTIAPPSET_APPSET_BITS _u(0x0000000f) 8227 #define M33_CTIAPPSET_APPSET_MSB _u(3) 8228 #define M33_CTIAPPSET_APPSET_LSB _u(0) 8229 #define M33_CTIAPPSET_APPSET_ACCESS "RW" 8230 // ============================================================================= 8231 // Register : M33_CTIAPPCLEAR 8232 // Description : CTI Application Trigger Clear Register 8233 #define M33_CTIAPPCLEAR_OFFSET _u(0x00042018) 8234 #define M33_CTIAPPCLEAR_BITS _u(0x0000000f) 8235 #define M33_CTIAPPCLEAR_RESET _u(0x00000000) 8236 // ----------------------------------------------------------------------------- 8237 // Field : M33_CTIAPPCLEAR_APPCLEAR 8238 // Description : Sets the corresponding bits in the CTIAPPSET to 0. There is one 8239 // bit of the register for each channel. 8240 #define M33_CTIAPPCLEAR_APPCLEAR_RESET _u(0x0) 8241 #define M33_CTIAPPCLEAR_APPCLEAR_BITS _u(0x0000000f) 8242 #define M33_CTIAPPCLEAR_APPCLEAR_MSB _u(3) 8243 #define M33_CTIAPPCLEAR_APPCLEAR_LSB _u(0) 8244 #define M33_CTIAPPCLEAR_APPCLEAR_ACCESS "RW" 8245 // ============================================================================= 8246 // Register : M33_CTIAPPPULSE 8247 // Description : CTI Application Pulse Register 8248 #define M33_CTIAPPPULSE_OFFSET _u(0x0004201c) 8249 #define M33_CTIAPPPULSE_BITS _u(0x0000000f) 8250 #define M33_CTIAPPPULSE_RESET _u(0x00000000) 8251 // ----------------------------------------------------------------------------- 8252 // Field : M33_CTIAPPPULSE_APPULSE 8253 // Description : Setting a bit HIGH generates a channel event pulse for the 8254 // selected channel. There is one bit of the register for each 8255 // channel. 8256 #define M33_CTIAPPPULSE_APPULSE_RESET _u(0x0) 8257 #define M33_CTIAPPPULSE_APPULSE_BITS _u(0x0000000f) 8258 #define M33_CTIAPPPULSE_APPULSE_MSB _u(3) 8259 #define M33_CTIAPPPULSE_APPULSE_LSB _u(0) 8260 #define M33_CTIAPPPULSE_APPULSE_ACCESS "RW" 8261 // ============================================================================= 8262 // Register : M33_CTIINEN0 8263 // Description : CTI Trigger to Channel Enable Registers 8264 #define M33_CTIINEN0_OFFSET _u(0x00042020) 8265 #define M33_CTIINEN0_BITS _u(0x0000000f) 8266 #define M33_CTIINEN0_RESET _u(0x00000000) 8267 // ----------------------------------------------------------------------------- 8268 // Field : M33_CTIINEN0_TRIGINEN 8269 // Description : Enables a cross trigger event to the corresponding channel when 8270 // a ctitrigin input is activated. There is one bit of the field 8271 // for each of the four channels 8272 #define M33_CTIINEN0_TRIGINEN_RESET _u(0x0) 8273 #define M33_CTIINEN0_TRIGINEN_BITS _u(0x0000000f) 8274 #define M33_CTIINEN0_TRIGINEN_MSB _u(3) 8275 #define M33_CTIINEN0_TRIGINEN_LSB _u(0) 8276 #define M33_CTIINEN0_TRIGINEN_ACCESS "RW" 8277 // ============================================================================= 8278 // Register : M33_CTIINEN1 8279 // Description : CTI Trigger to Channel Enable Registers 8280 #define M33_CTIINEN1_OFFSET _u(0x00042024) 8281 #define M33_CTIINEN1_BITS _u(0x0000000f) 8282 #define M33_CTIINEN1_RESET _u(0x00000000) 8283 // ----------------------------------------------------------------------------- 8284 // Field : M33_CTIINEN1_TRIGINEN 8285 // Description : Enables a cross trigger event to the corresponding channel when 8286 // a ctitrigin input is activated. There is one bit of the field 8287 // for each of the four channels 8288 #define M33_CTIINEN1_TRIGINEN_RESET _u(0x0) 8289 #define M33_CTIINEN1_TRIGINEN_BITS _u(0x0000000f) 8290 #define M33_CTIINEN1_TRIGINEN_MSB _u(3) 8291 #define M33_CTIINEN1_TRIGINEN_LSB _u(0) 8292 #define M33_CTIINEN1_TRIGINEN_ACCESS "RW" 8293 // ============================================================================= 8294 // Register : M33_CTIINEN2 8295 // Description : CTI Trigger to Channel Enable Registers 8296 #define M33_CTIINEN2_OFFSET _u(0x00042028) 8297 #define M33_CTIINEN2_BITS _u(0x0000000f) 8298 #define M33_CTIINEN2_RESET _u(0x00000000) 8299 // ----------------------------------------------------------------------------- 8300 // Field : M33_CTIINEN2_TRIGINEN 8301 // Description : Enables a cross trigger event to the corresponding channel when 8302 // a ctitrigin input is activated. There is one bit of the field 8303 // for each of the four channels 8304 #define M33_CTIINEN2_TRIGINEN_RESET _u(0x0) 8305 #define M33_CTIINEN2_TRIGINEN_BITS _u(0x0000000f) 8306 #define M33_CTIINEN2_TRIGINEN_MSB _u(3) 8307 #define M33_CTIINEN2_TRIGINEN_LSB _u(0) 8308 #define M33_CTIINEN2_TRIGINEN_ACCESS "RW" 8309 // ============================================================================= 8310 // Register : M33_CTIINEN3 8311 // Description : CTI Trigger to Channel Enable Registers 8312 #define M33_CTIINEN3_OFFSET _u(0x0004202c) 8313 #define M33_CTIINEN3_BITS _u(0x0000000f) 8314 #define M33_CTIINEN3_RESET _u(0x00000000) 8315 // ----------------------------------------------------------------------------- 8316 // Field : M33_CTIINEN3_TRIGINEN 8317 // Description : Enables a cross trigger event to the corresponding channel when 8318 // a ctitrigin input is activated. There is one bit of the field 8319 // for each of the four channels 8320 #define M33_CTIINEN3_TRIGINEN_RESET _u(0x0) 8321 #define M33_CTIINEN3_TRIGINEN_BITS _u(0x0000000f) 8322 #define M33_CTIINEN3_TRIGINEN_MSB _u(3) 8323 #define M33_CTIINEN3_TRIGINEN_LSB _u(0) 8324 #define M33_CTIINEN3_TRIGINEN_ACCESS "RW" 8325 // ============================================================================= 8326 // Register : M33_CTIINEN4 8327 // Description : CTI Trigger to Channel Enable Registers 8328 #define M33_CTIINEN4_OFFSET _u(0x00042030) 8329 #define M33_CTIINEN4_BITS _u(0x0000000f) 8330 #define M33_CTIINEN4_RESET _u(0x00000000) 8331 // ----------------------------------------------------------------------------- 8332 // Field : M33_CTIINEN4_TRIGINEN 8333 // Description : Enables a cross trigger event to the corresponding channel when 8334 // a ctitrigin input is activated. There is one bit of the field 8335 // for each of the four channels 8336 #define M33_CTIINEN4_TRIGINEN_RESET _u(0x0) 8337 #define M33_CTIINEN4_TRIGINEN_BITS _u(0x0000000f) 8338 #define M33_CTIINEN4_TRIGINEN_MSB _u(3) 8339 #define M33_CTIINEN4_TRIGINEN_LSB _u(0) 8340 #define M33_CTIINEN4_TRIGINEN_ACCESS "RW" 8341 // ============================================================================= 8342 // Register : M33_CTIINEN5 8343 // Description : CTI Trigger to Channel Enable Registers 8344 #define M33_CTIINEN5_OFFSET _u(0x00042034) 8345 #define M33_CTIINEN5_BITS _u(0x0000000f) 8346 #define M33_CTIINEN5_RESET _u(0x00000000) 8347 // ----------------------------------------------------------------------------- 8348 // Field : M33_CTIINEN5_TRIGINEN 8349 // Description : Enables a cross trigger event to the corresponding channel when 8350 // a ctitrigin input is activated. There is one bit of the field 8351 // for each of the four channels 8352 #define M33_CTIINEN5_TRIGINEN_RESET _u(0x0) 8353 #define M33_CTIINEN5_TRIGINEN_BITS _u(0x0000000f) 8354 #define M33_CTIINEN5_TRIGINEN_MSB _u(3) 8355 #define M33_CTIINEN5_TRIGINEN_LSB _u(0) 8356 #define M33_CTIINEN5_TRIGINEN_ACCESS "RW" 8357 // ============================================================================= 8358 // Register : M33_CTIINEN6 8359 // Description : CTI Trigger to Channel Enable Registers 8360 #define M33_CTIINEN6_OFFSET _u(0x00042038) 8361 #define M33_CTIINEN6_BITS _u(0x0000000f) 8362 #define M33_CTIINEN6_RESET _u(0x00000000) 8363 // ----------------------------------------------------------------------------- 8364 // Field : M33_CTIINEN6_TRIGINEN 8365 // Description : Enables a cross trigger event to the corresponding channel when 8366 // a ctitrigin input is activated. There is one bit of the field 8367 // for each of the four channels 8368 #define M33_CTIINEN6_TRIGINEN_RESET _u(0x0) 8369 #define M33_CTIINEN6_TRIGINEN_BITS _u(0x0000000f) 8370 #define M33_CTIINEN6_TRIGINEN_MSB _u(3) 8371 #define M33_CTIINEN6_TRIGINEN_LSB _u(0) 8372 #define M33_CTIINEN6_TRIGINEN_ACCESS "RW" 8373 // ============================================================================= 8374 // Register : M33_CTIINEN7 8375 // Description : CTI Trigger to Channel Enable Registers 8376 #define M33_CTIINEN7_OFFSET _u(0x0004203c) 8377 #define M33_CTIINEN7_BITS _u(0x0000000f) 8378 #define M33_CTIINEN7_RESET _u(0x00000000) 8379 // ----------------------------------------------------------------------------- 8380 // Field : M33_CTIINEN7_TRIGINEN 8381 // Description : Enables a cross trigger event to the corresponding channel when 8382 // a ctitrigin input is activated. There is one bit of the field 8383 // for each of the four channels 8384 #define M33_CTIINEN7_TRIGINEN_RESET _u(0x0) 8385 #define M33_CTIINEN7_TRIGINEN_BITS _u(0x0000000f) 8386 #define M33_CTIINEN7_TRIGINEN_MSB _u(3) 8387 #define M33_CTIINEN7_TRIGINEN_LSB _u(0) 8388 #define M33_CTIINEN7_TRIGINEN_ACCESS "RW" 8389 // ============================================================================= 8390 // Register : M33_CTIOUTEN0 8391 // Description : CTI Trigger to Channel Enable Registers 8392 #define M33_CTIOUTEN0_OFFSET _u(0x000420a0) 8393 #define M33_CTIOUTEN0_BITS _u(0x0000000f) 8394 #define M33_CTIOUTEN0_RESET _u(0x00000000) 8395 // ----------------------------------------------------------------------------- 8396 // Field : M33_CTIOUTEN0_TRIGOUTEN 8397 // Description : Enables a cross trigger event to ctitrigout when the 8398 // corresponding channel is activated. There is one bit of the 8399 // field for each of the four channels. 8400 #define M33_CTIOUTEN0_TRIGOUTEN_RESET _u(0x0) 8401 #define M33_CTIOUTEN0_TRIGOUTEN_BITS _u(0x0000000f) 8402 #define M33_CTIOUTEN0_TRIGOUTEN_MSB _u(3) 8403 #define M33_CTIOUTEN0_TRIGOUTEN_LSB _u(0) 8404 #define M33_CTIOUTEN0_TRIGOUTEN_ACCESS "RW" 8405 // ============================================================================= 8406 // Register : M33_CTIOUTEN1 8407 // Description : CTI Trigger to Channel Enable Registers 8408 #define M33_CTIOUTEN1_OFFSET _u(0x000420a4) 8409 #define M33_CTIOUTEN1_BITS _u(0x0000000f) 8410 #define M33_CTIOUTEN1_RESET _u(0x00000000) 8411 // ----------------------------------------------------------------------------- 8412 // Field : M33_CTIOUTEN1_TRIGOUTEN 8413 // Description : Enables a cross trigger event to ctitrigout when the 8414 // corresponding channel is activated. There is one bit of the 8415 // field for each of the four channels. 8416 #define M33_CTIOUTEN1_TRIGOUTEN_RESET _u(0x0) 8417 #define M33_CTIOUTEN1_TRIGOUTEN_BITS _u(0x0000000f) 8418 #define M33_CTIOUTEN1_TRIGOUTEN_MSB _u(3) 8419 #define M33_CTIOUTEN1_TRIGOUTEN_LSB _u(0) 8420 #define M33_CTIOUTEN1_TRIGOUTEN_ACCESS "RW" 8421 // ============================================================================= 8422 // Register : M33_CTIOUTEN2 8423 // Description : CTI Trigger to Channel Enable Registers 8424 #define M33_CTIOUTEN2_OFFSET _u(0x000420a8) 8425 #define M33_CTIOUTEN2_BITS _u(0x0000000f) 8426 #define M33_CTIOUTEN2_RESET _u(0x00000000) 8427 // ----------------------------------------------------------------------------- 8428 // Field : M33_CTIOUTEN2_TRIGOUTEN 8429 // Description : Enables a cross trigger event to ctitrigout when the 8430 // corresponding channel is activated. There is one bit of the 8431 // field for each of the four channels. 8432 #define M33_CTIOUTEN2_TRIGOUTEN_RESET _u(0x0) 8433 #define M33_CTIOUTEN2_TRIGOUTEN_BITS _u(0x0000000f) 8434 #define M33_CTIOUTEN2_TRIGOUTEN_MSB _u(3) 8435 #define M33_CTIOUTEN2_TRIGOUTEN_LSB _u(0) 8436 #define M33_CTIOUTEN2_TRIGOUTEN_ACCESS "RW" 8437 // ============================================================================= 8438 // Register : M33_CTIOUTEN3 8439 // Description : CTI Trigger to Channel Enable Registers 8440 #define M33_CTIOUTEN3_OFFSET _u(0x000420ac) 8441 #define M33_CTIOUTEN3_BITS _u(0x0000000f) 8442 #define M33_CTIOUTEN3_RESET _u(0x00000000) 8443 // ----------------------------------------------------------------------------- 8444 // Field : M33_CTIOUTEN3_TRIGOUTEN 8445 // Description : Enables a cross trigger event to ctitrigout when the 8446 // corresponding channel is activated. There is one bit of the 8447 // field for each of the four channels. 8448 #define M33_CTIOUTEN3_TRIGOUTEN_RESET _u(0x0) 8449 #define M33_CTIOUTEN3_TRIGOUTEN_BITS _u(0x0000000f) 8450 #define M33_CTIOUTEN3_TRIGOUTEN_MSB _u(3) 8451 #define M33_CTIOUTEN3_TRIGOUTEN_LSB _u(0) 8452 #define M33_CTIOUTEN3_TRIGOUTEN_ACCESS "RW" 8453 // ============================================================================= 8454 // Register : M33_CTIOUTEN4 8455 // Description : CTI Trigger to Channel Enable Registers 8456 #define M33_CTIOUTEN4_OFFSET _u(0x000420b0) 8457 #define M33_CTIOUTEN4_BITS _u(0x0000000f) 8458 #define M33_CTIOUTEN4_RESET _u(0x00000000) 8459 // ----------------------------------------------------------------------------- 8460 // Field : M33_CTIOUTEN4_TRIGOUTEN 8461 // Description : Enables a cross trigger event to ctitrigout when the 8462 // corresponding channel is activated. There is one bit of the 8463 // field for each of the four channels. 8464 #define M33_CTIOUTEN4_TRIGOUTEN_RESET _u(0x0) 8465 #define M33_CTIOUTEN4_TRIGOUTEN_BITS _u(0x0000000f) 8466 #define M33_CTIOUTEN4_TRIGOUTEN_MSB _u(3) 8467 #define M33_CTIOUTEN4_TRIGOUTEN_LSB _u(0) 8468 #define M33_CTIOUTEN4_TRIGOUTEN_ACCESS "RW" 8469 // ============================================================================= 8470 // Register : M33_CTIOUTEN5 8471 // Description : CTI Trigger to Channel Enable Registers 8472 #define M33_CTIOUTEN5_OFFSET _u(0x000420b4) 8473 #define M33_CTIOUTEN5_BITS _u(0x0000000f) 8474 #define M33_CTIOUTEN5_RESET _u(0x00000000) 8475 // ----------------------------------------------------------------------------- 8476 // Field : M33_CTIOUTEN5_TRIGOUTEN 8477 // Description : Enables a cross trigger event to ctitrigout when the 8478 // corresponding channel is activated. There is one bit of the 8479 // field for each of the four channels. 8480 #define M33_CTIOUTEN5_TRIGOUTEN_RESET _u(0x0) 8481 #define M33_CTIOUTEN5_TRIGOUTEN_BITS _u(0x0000000f) 8482 #define M33_CTIOUTEN5_TRIGOUTEN_MSB _u(3) 8483 #define M33_CTIOUTEN5_TRIGOUTEN_LSB _u(0) 8484 #define M33_CTIOUTEN5_TRIGOUTEN_ACCESS "RW" 8485 // ============================================================================= 8486 // Register : M33_CTIOUTEN6 8487 // Description : CTI Trigger to Channel Enable Registers 8488 #define M33_CTIOUTEN6_OFFSET _u(0x000420b8) 8489 #define M33_CTIOUTEN6_BITS _u(0x0000000f) 8490 #define M33_CTIOUTEN6_RESET _u(0x00000000) 8491 // ----------------------------------------------------------------------------- 8492 // Field : M33_CTIOUTEN6_TRIGOUTEN 8493 // Description : Enables a cross trigger event to ctitrigout when the 8494 // corresponding channel is activated. There is one bit of the 8495 // field for each of the four channels. 8496 #define M33_CTIOUTEN6_TRIGOUTEN_RESET _u(0x0) 8497 #define M33_CTIOUTEN6_TRIGOUTEN_BITS _u(0x0000000f) 8498 #define M33_CTIOUTEN6_TRIGOUTEN_MSB _u(3) 8499 #define M33_CTIOUTEN6_TRIGOUTEN_LSB _u(0) 8500 #define M33_CTIOUTEN6_TRIGOUTEN_ACCESS "RW" 8501 // ============================================================================= 8502 // Register : M33_CTIOUTEN7 8503 // Description : CTI Trigger to Channel Enable Registers 8504 #define M33_CTIOUTEN7_OFFSET _u(0x000420bc) 8505 #define M33_CTIOUTEN7_BITS _u(0x0000000f) 8506 #define M33_CTIOUTEN7_RESET _u(0x00000000) 8507 // ----------------------------------------------------------------------------- 8508 // Field : M33_CTIOUTEN7_TRIGOUTEN 8509 // Description : Enables a cross trigger event to ctitrigout when the 8510 // corresponding channel is activated. There is one bit of the 8511 // field for each of the four channels. 8512 #define M33_CTIOUTEN7_TRIGOUTEN_RESET _u(0x0) 8513 #define M33_CTIOUTEN7_TRIGOUTEN_BITS _u(0x0000000f) 8514 #define M33_CTIOUTEN7_TRIGOUTEN_MSB _u(3) 8515 #define M33_CTIOUTEN7_TRIGOUTEN_LSB _u(0) 8516 #define M33_CTIOUTEN7_TRIGOUTEN_ACCESS "RW" 8517 // ============================================================================= 8518 // Register : M33_CTITRIGINSTATUS 8519 // Description : CTI Trigger to Channel Enable Registers 8520 #define M33_CTITRIGINSTATUS_OFFSET _u(0x00042130) 8521 #define M33_CTITRIGINSTATUS_BITS _u(0x000000ff) 8522 #define M33_CTITRIGINSTATUS_RESET _u(0x00000000) 8523 // ----------------------------------------------------------------------------- 8524 // Field : M33_CTITRIGINSTATUS_TRIGINSTATUS 8525 // Description : Shows the status of the ctitrigin inputs. There is one bit of 8526 // the field for each trigger input.Because the register provides 8527 // a view of the raw ctitrigin inputs, the reset value is UNKNOWN. 8528 #define M33_CTITRIGINSTATUS_TRIGINSTATUS_RESET _u(0x00) 8529 #define M33_CTITRIGINSTATUS_TRIGINSTATUS_BITS _u(0x000000ff) 8530 #define M33_CTITRIGINSTATUS_TRIGINSTATUS_MSB _u(7) 8531 #define M33_CTITRIGINSTATUS_TRIGINSTATUS_LSB _u(0) 8532 #define M33_CTITRIGINSTATUS_TRIGINSTATUS_ACCESS "RO" 8533 // ============================================================================= 8534 // Register : M33_CTITRIGOUTSTATUS 8535 // Description : CTI Trigger In Status Register 8536 #define M33_CTITRIGOUTSTATUS_OFFSET _u(0x00042134) 8537 #define M33_CTITRIGOUTSTATUS_BITS _u(0x000000ff) 8538 #define M33_CTITRIGOUTSTATUS_RESET _u(0x00000000) 8539 // ----------------------------------------------------------------------------- 8540 // Field : M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS 8541 // Description : Shows the status of the ctitrigout outputs. There is one bit of 8542 // the field for each trigger output. 8543 #define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_RESET _u(0x00) 8544 #define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_BITS _u(0x000000ff) 8545 #define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_MSB _u(7) 8546 #define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_LSB _u(0) 8547 #define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_ACCESS "RO" 8548 // ============================================================================= 8549 // Register : M33_CTICHINSTATUS 8550 // Description : CTI Channel In Status Register 8551 #define M33_CTICHINSTATUS_OFFSET _u(0x00042138) 8552 #define M33_CTICHINSTATUS_BITS _u(0x0000000f) 8553 #define M33_CTICHINSTATUS_RESET _u(0x00000000) 8554 // ----------------------------------------------------------------------------- 8555 // Field : M33_CTICHINSTATUS_CTICHOUTSTATUS 8556 // Description : Shows the status of the ctichout outputs. There is one bit of 8557 // the field for each channel output 8558 #define M33_CTICHINSTATUS_CTICHOUTSTATUS_RESET _u(0x0) 8559 #define M33_CTICHINSTATUS_CTICHOUTSTATUS_BITS _u(0x0000000f) 8560 #define M33_CTICHINSTATUS_CTICHOUTSTATUS_MSB _u(3) 8561 #define M33_CTICHINSTATUS_CTICHOUTSTATUS_LSB _u(0) 8562 #define M33_CTICHINSTATUS_CTICHOUTSTATUS_ACCESS "RO" 8563 // ============================================================================= 8564 // Register : M33_CTIGATE 8565 // Description : Enable CTI Channel Gate register 8566 #define M33_CTIGATE_OFFSET _u(0x00042140) 8567 #define M33_CTIGATE_BITS _u(0x0000000f) 8568 #define M33_CTIGATE_RESET _u(0x0000000f) 8569 // ----------------------------------------------------------------------------- 8570 // Field : M33_CTIGATE_CTIGATEEN3 8571 // Description : Enable ctichout3. Set to 0 to disable channel propagation. 8572 #define M33_CTIGATE_CTIGATEEN3_RESET _u(0x1) 8573 #define M33_CTIGATE_CTIGATEEN3_BITS _u(0x00000008) 8574 #define M33_CTIGATE_CTIGATEEN3_MSB _u(3) 8575 #define M33_CTIGATE_CTIGATEEN3_LSB _u(3) 8576 #define M33_CTIGATE_CTIGATEEN3_ACCESS "RW" 8577 // ----------------------------------------------------------------------------- 8578 // Field : M33_CTIGATE_CTIGATEEN2 8579 // Description : Enable ctichout2. Set to 0 to disable channel propagation. 8580 #define M33_CTIGATE_CTIGATEEN2_RESET _u(0x1) 8581 #define M33_CTIGATE_CTIGATEEN2_BITS _u(0x00000004) 8582 #define M33_CTIGATE_CTIGATEEN2_MSB _u(2) 8583 #define M33_CTIGATE_CTIGATEEN2_LSB _u(2) 8584 #define M33_CTIGATE_CTIGATEEN2_ACCESS "RW" 8585 // ----------------------------------------------------------------------------- 8586 // Field : M33_CTIGATE_CTIGATEEN1 8587 // Description : Enable ctichout1. Set to 0 to disable channel propagation. 8588 #define M33_CTIGATE_CTIGATEEN1_RESET _u(0x1) 8589 #define M33_CTIGATE_CTIGATEEN1_BITS _u(0x00000002) 8590 #define M33_CTIGATE_CTIGATEEN1_MSB _u(1) 8591 #define M33_CTIGATE_CTIGATEEN1_LSB _u(1) 8592 #define M33_CTIGATE_CTIGATEEN1_ACCESS "RW" 8593 // ----------------------------------------------------------------------------- 8594 // Field : M33_CTIGATE_CTIGATEEN0 8595 // Description : Enable ctichout0. Set to 0 to disable channel propagation. 8596 #define M33_CTIGATE_CTIGATEEN0_RESET _u(0x1) 8597 #define M33_CTIGATE_CTIGATEEN0_BITS _u(0x00000001) 8598 #define M33_CTIGATE_CTIGATEEN0_MSB _u(0) 8599 #define M33_CTIGATE_CTIGATEEN0_LSB _u(0) 8600 #define M33_CTIGATE_CTIGATEEN0_ACCESS "RW" 8601 // ============================================================================= 8602 // Register : M33_ASICCTL 8603 // Description : External Multiplexer Control register 8604 #define M33_ASICCTL_OFFSET _u(0x00042144) 8605 #define M33_ASICCTL_BITS _u(0x00000000) 8606 #define M33_ASICCTL_RESET _u(0x00000000) 8607 #define M33_ASICCTL_MSB _u(31) 8608 #define M33_ASICCTL_LSB _u(0) 8609 #define M33_ASICCTL_ACCESS "RW" 8610 // ============================================================================= 8611 // Register : M33_ITCHOUT 8612 // Description : Integration Test Channel Output register 8613 #define M33_ITCHOUT_OFFSET _u(0x00042ee4) 8614 #define M33_ITCHOUT_BITS _u(0x0000000f) 8615 #define M33_ITCHOUT_RESET _u(0x00000000) 8616 // ----------------------------------------------------------------------------- 8617 // Field : M33_ITCHOUT_CTCHOUT 8618 // Description : Sets the value of the ctichout outputs 8619 #define M33_ITCHOUT_CTCHOUT_RESET _u(0x0) 8620 #define M33_ITCHOUT_CTCHOUT_BITS _u(0x0000000f) 8621 #define M33_ITCHOUT_CTCHOUT_MSB _u(3) 8622 #define M33_ITCHOUT_CTCHOUT_LSB _u(0) 8623 #define M33_ITCHOUT_CTCHOUT_ACCESS "RW" 8624 // ============================================================================= 8625 // Register : M33_ITTRIGOUT 8626 // Description : Integration Test Trigger Output register 8627 #define M33_ITTRIGOUT_OFFSET _u(0x00042ee8) 8628 #define M33_ITTRIGOUT_BITS _u(0x000000ff) 8629 #define M33_ITTRIGOUT_RESET _u(0x00000000) 8630 // ----------------------------------------------------------------------------- 8631 // Field : M33_ITTRIGOUT_CTTRIGOUT 8632 // Description : Sets the value of the ctitrigout outputs 8633 #define M33_ITTRIGOUT_CTTRIGOUT_RESET _u(0x00) 8634 #define M33_ITTRIGOUT_CTTRIGOUT_BITS _u(0x000000ff) 8635 #define M33_ITTRIGOUT_CTTRIGOUT_MSB _u(7) 8636 #define M33_ITTRIGOUT_CTTRIGOUT_LSB _u(0) 8637 #define M33_ITTRIGOUT_CTTRIGOUT_ACCESS "RW" 8638 // ============================================================================= 8639 // Register : M33_ITCHIN 8640 // Description : Integration Test Channel Input register 8641 #define M33_ITCHIN_OFFSET _u(0x00042ef4) 8642 #define M33_ITCHIN_BITS _u(0x0000000f) 8643 #define M33_ITCHIN_RESET _u(0x00000000) 8644 // ----------------------------------------------------------------------------- 8645 // Field : M33_ITCHIN_CTCHIN 8646 // Description : Reads the value of the ctichin inputs. 8647 #define M33_ITCHIN_CTCHIN_RESET _u(0x0) 8648 #define M33_ITCHIN_CTCHIN_BITS _u(0x0000000f) 8649 #define M33_ITCHIN_CTCHIN_MSB _u(3) 8650 #define M33_ITCHIN_CTCHIN_LSB _u(0) 8651 #define M33_ITCHIN_CTCHIN_ACCESS "RO" 8652 // ============================================================================= 8653 // Register : M33_ITCTRL 8654 // Description : Integration Mode Control register 8655 #define M33_ITCTRL_OFFSET _u(0x00042f00) 8656 #define M33_ITCTRL_BITS _u(0x00000001) 8657 #define M33_ITCTRL_RESET _u(0x00000000) 8658 // ----------------------------------------------------------------------------- 8659 // Field : M33_ITCTRL_IME 8660 // Description : Integration Mode Enable 8661 #define M33_ITCTRL_IME_RESET _u(0x0) 8662 #define M33_ITCTRL_IME_BITS _u(0x00000001) 8663 #define M33_ITCTRL_IME_MSB _u(0) 8664 #define M33_ITCTRL_IME_LSB _u(0) 8665 #define M33_ITCTRL_IME_ACCESS "RW" 8666 // ============================================================================= 8667 // Register : M33_DEVARCH 8668 // Description : Device Architecture register 8669 #define M33_DEVARCH_OFFSET _u(0x00042fbc) 8670 #define M33_DEVARCH_BITS _u(0xffffffff) 8671 #define M33_DEVARCH_RESET _u(0x47701a14) 8672 // ----------------------------------------------------------------------------- 8673 // Field : M33_DEVARCH_ARCHITECT 8674 // Description : Indicates the component architect 8675 #define M33_DEVARCH_ARCHITECT_RESET _u(0x23b) 8676 #define M33_DEVARCH_ARCHITECT_BITS _u(0xffe00000) 8677 #define M33_DEVARCH_ARCHITECT_MSB _u(31) 8678 #define M33_DEVARCH_ARCHITECT_LSB _u(21) 8679 #define M33_DEVARCH_ARCHITECT_ACCESS "RO" 8680 // ----------------------------------------------------------------------------- 8681 // Field : M33_DEVARCH_PRESENT 8682 // Description : Indicates whether the DEVARCH register is present 8683 #define M33_DEVARCH_PRESENT_RESET _u(0x1) 8684 #define M33_DEVARCH_PRESENT_BITS _u(0x00100000) 8685 #define M33_DEVARCH_PRESENT_MSB _u(20) 8686 #define M33_DEVARCH_PRESENT_LSB _u(20) 8687 #define M33_DEVARCH_PRESENT_ACCESS "RO" 8688 // ----------------------------------------------------------------------------- 8689 // Field : M33_DEVARCH_REVISION 8690 // Description : Indicates the architecture revision 8691 #define M33_DEVARCH_REVISION_RESET _u(0x0) 8692 #define M33_DEVARCH_REVISION_BITS _u(0x000f0000) 8693 #define M33_DEVARCH_REVISION_MSB _u(19) 8694 #define M33_DEVARCH_REVISION_LSB _u(16) 8695 #define M33_DEVARCH_REVISION_ACCESS "RO" 8696 // ----------------------------------------------------------------------------- 8697 // Field : M33_DEVARCH_ARCHID 8698 // Description : Indicates the component 8699 #define M33_DEVARCH_ARCHID_RESET _u(0x1a14) 8700 #define M33_DEVARCH_ARCHID_BITS _u(0x0000ffff) 8701 #define M33_DEVARCH_ARCHID_MSB _u(15) 8702 #define M33_DEVARCH_ARCHID_LSB _u(0) 8703 #define M33_DEVARCH_ARCHID_ACCESS "RO" 8704 // ============================================================================= 8705 // Register : M33_DEVID 8706 // Description : Device Configuration register 8707 #define M33_DEVID_OFFSET _u(0x00042fc8) 8708 #define M33_DEVID_BITS _u(0x000fff1f) 8709 #define M33_DEVID_RESET _u(0x00040800) 8710 // ----------------------------------------------------------------------------- 8711 // Field : M33_DEVID_NUMCH 8712 // Description : Number of ECT channels available 8713 #define M33_DEVID_NUMCH_RESET _u(0x4) 8714 #define M33_DEVID_NUMCH_BITS _u(0x000f0000) 8715 #define M33_DEVID_NUMCH_MSB _u(19) 8716 #define M33_DEVID_NUMCH_LSB _u(16) 8717 #define M33_DEVID_NUMCH_ACCESS "RO" 8718 // ----------------------------------------------------------------------------- 8719 // Field : M33_DEVID_NUMTRIG 8720 // Description : Number of ECT triggers available. 8721 #define M33_DEVID_NUMTRIG_RESET _u(0x08) 8722 #define M33_DEVID_NUMTRIG_BITS _u(0x0000ff00) 8723 #define M33_DEVID_NUMTRIG_MSB _u(15) 8724 #define M33_DEVID_NUMTRIG_LSB _u(8) 8725 #define M33_DEVID_NUMTRIG_ACCESS "RO" 8726 // ----------------------------------------------------------------------------- 8727 // Field : M33_DEVID_EXTMUXNUM 8728 // Description : Indicates the number of multiplexers available on Trigger 8729 // Inputs and Trigger Outputs that are using asicctl. The default 8730 // value of 0b00000 indicates that no multiplexing is present. 8731 // This value of this bit depends on the Verilog define EXTMUXNUM 8732 // that you must change accordingly. 8733 #define M33_DEVID_EXTMUXNUM_RESET _u(0x00) 8734 #define M33_DEVID_EXTMUXNUM_BITS _u(0x0000001f) 8735 #define M33_DEVID_EXTMUXNUM_MSB _u(4) 8736 #define M33_DEVID_EXTMUXNUM_LSB _u(0) 8737 #define M33_DEVID_EXTMUXNUM_ACCESS "RO" 8738 // ============================================================================= 8739 // Register : M33_DEVTYPE 8740 // Description : Device Type Identifier register 8741 #define M33_DEVTYPE_OFFSET _u(0x00042fcc) 8742 #define M33_DEVTYPE_BITS _u(0x000000ff) 8743 #define M33_DEVTYPE_RESET _u(0x00000014) 8744 // ----------------------------------------------------------------------------- 8745 // Field : M33_DEVTYPE_SUB 8746 // Description : Sub-classification of the type of the debug component as 8747 // specified in the ARM Architecture Specification within the 8748 // major classification as specified in the MAJOR field. 8749 #define M33_DEVTYPE_SUB_RESET _u(0x1) 8750 #define M33_DEVTYPE_SUB_BITS _u(0x000000f0) 8751 #define M33_DEVTYPE_SUB_MSB _u(7) 8752 #define M33_DEVTYPE_SUB_LSB _u(4) 8753 #define M33_DEVTYPE_SUB_ACCESS "RO" 8754 // ----------------------------------------------------------------------------- 8755 // Field : M33_DEVTYPE_MAJOR 8756 // Description : Major classification of the type of the debug component as 8757 // specified in the ARM Architecture Specification for this debug 8758 // and trace component. 8759 #define M33_DEVTYPE_MAJOR_RESET _u(0x4) 8760 #define M33_DEVTYPE_MAJOR_BITS _u(0x0000000f) 8761 #define M33_DEVTYPE_MAJOR_MSB _u(3) 8762 #define M33_DEVTYPE_MAJOR_LSB _u(0) 8763 #define M33_DEVTYPE_MAJOR_ACCESS "RO" 8764 // ============================================================================= 8765 // Register : M33_PIDR4 8766 // Description : CoreSight Peripheral ID4 8767 #define M33_PIDR4_OFFSET _u(0x00042fd0) 8768 #define M33_PIDR4_BITS _u(0x000000ff) 8769 #define M33_PIDR4_RESET _u(0x00000004) 8770 // ----------------------------------------------------------------------------- 8771 // Field : M33_PIDR4_SIZE 8772 // Description : Always 0b0000. Indicates that the device only occupies 4KB of 8773 // memory 8774 #define M33_PIDR4_SIZE_RESET _u(0x0) 8775 #define M33_PIDR4_SIZE_BITS _u(0x000000f0) 8776 #define M33_PIDR4_SIZE_MSB _u(7) 8777 #define M33_PIDR4_SIZE_LSB _u(4) 8778 #define M33_PIDR4_SIZE_ACCESS "RO" 8779 // ----------------------------------------------------------------------------- 8780 // Field : M33_PIDR4_DES_2 8781 // Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify 8782 // the designer of the component. 8783 #define M33_PIDR4_DES_2_RESET _u(0x4) 8784 #define M33_PIDR4_DES_2_BITS _u(0x0000000f) 8785 #define M33_PIDR4_DES_2_MSB _u(3) 8786 #define M33_PIDR4_DES_2_LSB _u(0) 8787 #define M33_PIDR4_DES_2_ACCESS "RO" 8788 // ============================================================================= 8789 // Register : M33_PIDR5 8790 // Description : CoreSight Peripheral ID5 8791 #define M33_PIDR5_OFFSET _u(0x00042fd4) 8792 #define M33_PIDR5_BITS _u(0x00000000) 8793 #define M33_PIDR5_RESET _u(0x00000000) 8794 #define M33_PIDR5_MSB _u(31) 8795 #define M33_PIDR5_LSB _u(0) 8796 #define M33_PIDR5_ACCESS "RW" 8797 // ============================================================================= 8798 // Register : M33_PIDR6 8799 // Description : CoreSight Peripheral ID6 8800 #define M33_PIDR6_OFFSET _u(0x00042fd8) 8801 #define M33_PIDR6_BITS _u(0x00000000) 8802 #define M33_PIDR6_RESET _u(0x00000000) 8803 #define M33_PIDR6_MSB _u(31) 8804 #define M33_PIDR6_LSB _u(0) 8805 #define M33_PIDR6_ACCESS "RW" 8806 // ============================================================================= 8807 // Register : M33_PIDR7 8808 // Description : CoreSight Peripheral ID7 8809 #define M33_PIDR7_OFFSET _u(0x00042fdc) 8810 #define M33_PIDR7_BITS _u(0x00000000) 8811 #define M33_PIDR7_RESET _u(0x00000000) 8812 #define M33_PIDR7_MSB _u(31) 8813 #define M33_PIDR7_LSB _u(0) 8814 #define M33_PIDR7_ACCESS "RW" 8815 // ============================================================================= 8816 // Register : M33_PIDR0 8817 // Description : CoreSight Peripheral ID0 8818 #define M33_PIDR0_OFFSET _u(0x00042fe0) 8819 #define M33_PIDR0_BITS _u(0x000000ff) 8820 #define M33_PIDR0_RESET _u(0x00000021) 8821 // ----------------------------------------------------------------------------- 8822 // Field : M33_PIDR0_PART_0 8823 // Description : Bits[7:0] of the 12-bit part number of the component. The 8824 // designer of the component assigns this part number. 8825 #define M33_PIDR0_PART_0_RESET _u(0x21) 8826 #define M33_PIDR0_PART_0_BITS _u(0x000000ff) 8827 #define M33_PIDR0_PART_0_MSB _u(7) 8828 #define M33_PIDR0_PART_0_LSB _u(0) 8829 #define M33_PIDR0_PART_0_ACCESS "RO" 8830 // ============================================================================= 8831 // Register : M33_PIDR1 8832 // Description : CoreSight Peripheral ID1 8833 #define M33_PIDR1_OFFSET _u(0x00042fe4) 8834 #define M33_PIDR1_BITS _u(0x000000ff) 8835 #define M33_PIDR1_RESET _u(0x000000bd) 8836 // ----------------------------------------------------------------------------- 8837 // Field : M33_PIDR1_DES_0 8838 // Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify 8839 // the designer of the component. 8840 #define M33_PIDR1_DES_0_RESET _u(0xb) 8841 #define M33_PIDR1_DES_0_BITS _u(0x000000f0) 8842 #define M33_PIDR1_DES_0_MSB _u(7) 8843 #define M33_PIDR1_DES_0_LSB _u(4) 8844 #define M33_PIDR1_DES_0_ACCESS "RO" 8845 // ----------------------------------------------------------------------------- 8846 // Field : M33_PIDR1_PART_1 8847 // Description : Bits[11:8] of the 12-bit part number of the component. The 8848 // designer of the component assigns this part number. 8849 #define M33_PIDR1_PART_1_RESET _u(0xd) 8850 #define M33_PIDR1_PART_1_BITS _u(0x0000000f) 8851 #define M33_PIDR1_PART_1_MSB _u(3) 8852 #define M33_PIDR1_PART_1_LSB _u(0) 8853 #define M33_PIDR1_PART_1_ACCESS "RO" 8854 // ============================================================================= 8855 // Register : M33_PIDR2 8856 // Description : CoreSight Peripheral ID2 8857 #define M33_PIDR2_OFFSET _u(0x00042fe8) 8858 #define M33_PIDR2_BITS _u(0x000000ff) 8859 #define M33_PIDR2_RESET _u(0x0000000b) 8860 // ----------------------------------------------------------------------------- 8861 // Field : M33_PIDR2_REVISION 8862 // Description : This device is at r1p0 8863 #define M33_PIDR2_REVISION_RESET _u(0x0) 8864 #define M33_PIDR2_REVISION_BITS _u(0x000000f0) 8865 #define M33_PIDR2_REVISION_MSB _u(7) 8866 #define M33_PIDR2_REVISION_LSB _u(4) 8867 #define M33_PIDR2_REVISION_ACCESS "RO" 8868 // ----------------------------------------------------------------------------- 8869 // Field : M33_PIDR2_JEDEC 8870 // Description : Always 1. Indicates that the JEDEC-assigned designer ID is 8871 // used. 8872 #define M33_PIDR2_JEDEC_RESET _u(0x1) 8873 #define M33_PIDR2_JEDEC_BITS _u(0x00000008) 8874 #define M33_PIDR2_JEDEC_MSB _u(3) 8875 #define M33_PIDR2_JEDEC_LSB _u(3) 8876 #define M33_PIDR2_JEDEC_ACCESS "RO" 8877 // ----------------------------------------------------------------------------- 8878 // Field : M33_PIDR2_DES_1 8879 // Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify 8880 // the designer of the component. 8881 #define M33_PIDR2_DES_1_RESET _u(0x3) 8882 #define M33_PIDR2_DES_1_BITS _u(0x00000007) 8883 #define M33_PIDR2_DES_1_MSB _u(2) 8884 #define M33_PIDR2_DES_1_LSB _u(0) 8885 #define M33_PIDR2_DES_1_ACCESS "RO" 8886 // ============================================================================= 8887 // Register : M33_PIDR3 8888 // Description : CoreSight Peripheral ID3 8889 #define M33_PIDR3_OFFSET _u(0x00042fec) 8890 #define M33_PIDR3_BITS _u(0x000000ff) 8891 #define M33_PIDR3_RESET _u(0x00000000) 8892 // ----------------------------------------------------------------------------- 8893 // Field : M33_PIDR3_REVAND 8894 // Description : Indicates minor errata fixes specific to the revision of the 8895 // component being used, for example metal fixes after 8896 // implementation. In most cases, this field is 0b0000. ARM 8897 // recommends that the component designers ensure that a metal fix 8898 // can change this field if required, for example, by driving it 8899 // from registers that reset to 0b0000. 8900 #define M33_PIDR3_REVAND_RESET _u(0x0) 8901 #define M33_PIDR3_REVAND_BITS _u(0x000000f0) 8902 #define M33_PIDR3_REVAND_MSB _u(7) 8903 #define M33_PIDR3_REVAND_LSB _u(4) 8904 #define M33_PIDR3_REVAND_ACCESS "RO" 8905 // ----------------------------------------------------------------------------- 8906 // Field : M33_PIDR3_CMOD 8907 // Description : Customer Modified. Indicates whether the customer has modified 8908 // the behavior of the component. In most cases, this field is 8909 // 0b0000. Customers change this value when they make authorized 8910 // modifications to this component. 8911 #define M33_PIDR3_CMOD_RESET _u(0x0) 8912 #define M33_PIDR3_CMOD_BITS _u(0x0000000f) 8913 #define M33_PIDR3_CMOD_MSB _u(3) 8914 #define M33_PIDR3_CMOD_LSB _u(0) 8915 #define M33_PIDR3_CMOD_ACCESS "RO" 8916 // ============================================================================= 8917 // Register : M33_CIDR0 8918 // Description : CoreSight Component ID0 8919 #define M33_CIDR0_OFFSET _u(0x00042ff0) 8920 #define M33_CIDR0_BITS _u(0x000000ff) 8921 #define M33_CIDR0_RESET _u(0x0000000d) 8922 // ----------------------------------------------------------------------------- 8923 // Field : M33_CIDR0_PRMBL_0 8924 // Description : Preamble[0]. Contains bits[7:0] of the component identification 8925 // code 8926 #define M33_CIDR0_PRMBL_0_RESET _u(0x0d) 8927 #define M33_CIDR0_PRMBL_0_BITS _u(0x000000ff) 8928 #define M33_CIDR0_PRMBL_0_MSB _u(7) 8929 #define M33_CIDR0_PRMBL_0_LSB _u(0) 8930 #define M33_CIDR0_PRMBL_0_ACCESS "RO" 8931 // ============================================================================= 8932 // Register : M33_CIDR1 8933 // Description : CoreSight Component ID1 8934 #define M33_CIDR1_OFFSET _u(0x00042ff4) 8935 #define M33_CIDR1_BITS _u(0x000000ff) 8936 #define M33_CIDR1_RESET _u(0x00000090) 8937 // ----------------------------------------------------------------------------- 8938 // Field : M33_CIDR1_CLASS 8939 // Description : Class of the component, for example, whether the component is a 8940 // ROM table or a generic CoreSight component. Contains 8941 // bits[15:12] of the component identification code. 8942 #define M33_CIDR1_CLASS_RESET _u(0x9) 8943 #define M33_CIDR1_CLASS_BITS _u(0x000000f0) 8944 #define M33_CIDR1_CLASS_MSB _u(7) 8945 #define M33_CIDR1_CLASS_LSB _u(4) 8946 #define M33_CIDR1_CLASS_ACCESS "RO" 8947 // ----------------------------------------------------------------------------- 8948 // Field : M33_CIDR1_PRMBL_1 8949 // Description : Preamble[1]. Contains bits[11:8] of the component 8950 // identification code. 8951 #define M33_CIDR1_PRMBL_1_RESET _u(0x0) 8952 #define M33_CIDR1_PRMBL_1_BITS _u(0x0000000f) 8953 #define M33_CIDR1_PRMBL_1_MSB _u(3) 8954 #define M33_CIDR1_PRMBL_1_LSB _u(0) 8955 #define M33_CIDR1_PRMBL_1_ACCESS "RO" 8956 // ============================================================================= 8957 // Register : M33_CIDR2 8958 // Description : CoreSight Component ID2 8959 #define M33_CIDR2_OFFSET _u(0x00042ff8) 8960 #define M33_CIDR2_BITS _u(0x000000ff) 8961 #define M33_CIDR2_RESET _u(0x00000005) 8962 // ----------------------------------------------------------------------------- 8963 // Field : M33_CIDR2_PRMBL_2 8964 // Description : Preamble[2]. Contains bits[23:16] of the component 8965 // identification code. 8966 #define M33_CIDR2_PRMBL_2_RESET _u(0x05) 8967 #define M33_CIDR2_PRMBL_2_BITS _u(0x000000ff) 8968 #define M33_CIDR2_PRMBL_2_MSB _u(7) 8969 #define M33_CIDR2_PRMBL_2_LSB _u(0) 8970 #define M33_CIDR2_PRMBL_2_ACCESS "RO" 8971 // ============================================================================= 8972 // Register : M33_CIDR3 8973 // Description : CoreSight Component ID3 8974 #define M33_CIDR3_OFFSET _u(0x00042ffc) 8975 #define M33_CIDR3_BITS _u(0x000000ff) 8976 #define M33_CIDR3_RESET _u(0x000000b1) 8977 // ----------------------------------------------------------------------------- 8978 // Field : M33_CIDR3_PRMBL_3 8979 // Description : Preamble[3]. Contains bits[31:24] of the component 8980 // identification code. 8981 #define M33_CIDR3_PRMBL_3_RESET _u(0xb1) 8982 #define M33_CIDR3_PRMBL_3_BITS _u(0x000000ff) 8983 #define M33_CIDR3_PRMBL_3_MSB _u(7) 8984 #define M33_CIDR3_PRMBL_3_LSB _u(0) 8985 #define M33_CIDR3_PRMBL_3_ACCESS "RO" 8986 // ============================================================================= 8987 #endif // _HARDWARE_REGS_M33_H 8988 8989