1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : M0PLUS 10 // Version : 1 11 // Bus type : ahbl 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_M0PLUS_H 14 #define _HARDWARE_REGS_M0PLUS_H 15 // ============================================================================= 16 // Register : M0PLUS_SYST_CSR 17 // Description : Use the SysTick Control and Status Register to enable the 18 // SysTick features. 19 #define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010) 20 #define M0PLUS_SYST_CSR_BITS _u(0x00010007) 21 #define M0PLUS_SYST_CSR_RESET _u(0x00000000) 22 // ----------------------------------------------------------------------------- 23 // Field : M0PLUS_SYST_CSR_COUNTFLAG 24 // Description : Returns 1 if timer counted to 0 since last time this was read. 25 // Clears on read by application or debugger. 26 #define M0PLUS_SYST_CSR_COUNTFLAG_RESET _u(0x0) 27 #define M0PLUS_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) 28 #define M0PLUS_SYST_CSR_COUNTFLAG_MSB _u(16) 29 #define M0PLUS_SYST_CSR_COUNTFLAG_LSB _u(16) 30 #define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" 31 // ----------------------------------------------------------------------------- 32 // Field : M0PLUS_SYST_CSR_CLKSOURCE 33 // Description : SysTick clock source. Always reads as one if SYST_CALIB reports 34 // NOREF. 35 // Selects the SysTick timer clock source: 36 // 0 = External reference clock. 37 // 1 = Processor clock. 38 #define M0PLUS_SYST_CSR_CLKSOURCE_RESET _u(0x0) 39 #define M0PLUS_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) 40 #define M0PLUS_SYST_CSR_CLKSOURCE_MSB _u(2) 41 #define M0PLUS_SYST_CSR_CLKSOURCE_LSB _u(2) 42 #define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" 43 // ----------------------------------------------------------------------------- 44 // Field : M0PLUS_SYST_CSR_TICKINT 45 // Description : Enables SysTick exception request: 46 // 0 = Counting down to zero does not assert the SysTick exception 47 // request. 48 // 1 = Counting down to zero to asserts the SysTick exception 49 // request. 50 #define M0PLUS_SYST_CSR_TICKINT_RESET _u(0x0) 51 #define M0PLUS_SYST_CSR_TICKINT_BITS _u(0x00000002) 52 #define M0PLUS_SYST_CSR_TICKINT_MSB _u(1) 53 #define M0PLUS_SYST_CSR_TICKINT_LSB _u(1) 54 #define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" 55 // ----------------------------------------------------------------------------- 56 // Field : M0PLUS_SYST_CSR_ENABLE 57 // Description : Enable SysTick counter: 58 // 0 = Counter disabled. 59 // 1 = Counter enabled. 60 #define M0PLUS_SYST_CSR_ENABLE_RESET _u(0x0) 61 #define M0PLUS_SYST_CSR_ENABLE_BITS _u(0x00000001) 62 #define M0PLUS_SYST_CSR_ENABLE_MSB _u(0) 63 #define M0PLUS_SYST_CSR_ENABLE_LSB _u(0) 64 #define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" 65 // ============================================================================= 66 // Register : M0PLUS_SYST_RVR 67 // Description : Use the SysTick Reload Value Register to specify the start 68 // value to load into the current value register when the counter 69 // reaches 0. It can be any value between 0 and 0x00FFFFFF. A 70 // start value of 0 is possible, but has no effect because the 71 // SysTick interrupt and COUNTFLAG are activated when counting 72 // from 1 to 0. The reset value of this register is UNKNOWN. 73 // To generate a multi-shot timer with a period of N processor 74 // clock cycles, use a RELOAD value of N-1. For example, if the 75 // SysTick interrupt is required every 100 clock pulses, set 76 // RELOAD to 99. 77 #define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014) 78 #define M0PLUS_SYST_RVR_BITS _u(0x00ffffff) 79 #define M0PLUS_SYST_RVR_RESET _u(0x00000000) 80 // ----------------------------------------------------------------------------- 81 // Field : M0PLUS_SYST_RVR_RELOAD 82 // Description : Value to load into the SysTick Current Value Register when the 83 // counter reaches 0. 84 #define M0PLUS_SYST_RVR_RELOAD_RESET _u(0x000000) 85 #define M0PLUS_SYST_RVR_RELOAD_BITS _u(0x00ffffff) 86 #define M0PLUS_SYST_RVR_RELOAD_MSB _u(23) 87 #define M0PLUS_SYST_RVR_RELOAD_LSB _u(0) 88 #define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" 89 // ============================================================================= 90 // Register : M0PLUS_SYST_CVR 91 // Description : Use the SysTick Current Value Register to find the current 92 // value in the register. The reset value of this register is 93 // UNKNOWN. 94 #define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018) 95 #define M0PLUS_SYST_CVR_BITS _u(0x00ffffff) 96 #define M0PLUS_SYST_CVR_RESET _u(0x00000000) 97 // ----------------------------------------------------------------------------- 98 // Field : M0PLUS_SYST_CVR_CURRENT 99 // Description : Reads return the current value of the SysTick counter. This 100 // register is write-clear. Writing to it with any value clears 101 // the register to 0. Clearing this register also clears the 102 // COUNTFLAG bit of the SysTick Control and Status Register. 103 #define M0PLUS_SYST_CVR_CURRENT_RESET _u(0x000000) 104 #define M0PLUS_SYST_CVR_CURRENT_BITS _u(0x00ffffff) 105 #define M0PLUS_SYST_CVR_CURRENT_MSB _u(23) 106 #define M0PLUS_SYST_CVR_CURRENT_LSB _u(0) 107 #define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" 108 // ============================================================================= 109 // Register : M0PLUS_SYST_CALIB 110 // Description : Use the SysTick Calibration Value Register to enable software 111 // to scale to any required speed using divide and multiply. 112 #define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c) 113 #define M0PLUS_SYST_CALIB_BITS _u(0xc0ffffff) 114 #define M0PLUS_SYST_CALIB_RESET _u(0x00000000) 115 // ----------------------------------------------------------------------------- 116 // Field : M0PLUS_SYST_CALIB_NOREF 117 // Description : If reads as 1, the Reference clock is not provided - the 118 // CLKSOURCE bit of the SysTick Control and Status register will 119 // be forced to 1 and cannot be cleared to 0. 120 #define M0PLUS_SYST_CALIB_NOREF_RESET _u(0x0) 121 #define M0PLUS_SYST_CALIB_NOREF_BITS _u(0x80000000) 122 #define M0PLUS_SYST_CALIB_NOREF_MSB _u(31) 123 #define M0PLUS_SYST_CALIB_NOREF_LSB _u(31) 124 #define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" 125 // ----------------------------------------------------------------------------- 126 // Field : M0PLUS_SYST_CALIB_SKEW 127 // Description : If reads as 1, the calibration value for 10ms is inexact (due 128 // to clock frequency). 129 #define M0PLUS_SYST_CALIB_SKEW_RESET _u(0x0) 130 #define M0PLUS_SYST_CALIB_SKEW_BITS _u(0x40000000) 131 #define M0PLUS_SYST_CALIB_SKEW_MSB _u(30) 132 #define M0PLUS_SYST_CALIB_SKEW_LSB _u(30) 133 #define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" 134 // ----------------------------------------------------------------------------- 135 // Field : M0PLUS_SYST_CALIB_TENMS 136 // Description : An optional Reload value to be used for 10ms (100Hz) timing, 137 // subject to system clock skew errors. If the value reads as 0, 138 // the calibration value is not known. 139 #define M0PLUS_SYST_CALIB_TENMS_RESET _u(0x000000) 140 #define M0PLUS_SYST_CALIB_TENMS_BITS _u(0x00ffffff) 141 #define M0PLUS_SYST_CALIB_TENMS_MSB _u(23) 142 #define M0PLUS_SYST_CALIB_TENMS_LSB _u(0) 143 #define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" 144 // ============================================================================= 145 // Register : M0PLUS_NVIC_ISER 146 // Description : Use the Interrupt Set-Enable Register to enable interrupts and 147 // determine which interrupts are currently enabled. 148 // If a pending interrupt is enabled, the NVIC activates the 149 // interrupt based on its priority. If an interrupt is not 150 // enabled, asserting its interrupt signal changes the interrupt 151 // state to pending, but the NVIC never activates the interrupt, 152 // regardless of its priority. 153 #define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100) 154 #define M0PLUS_NVIC_ISER_BITS _u(0xffffffff) 155 #define M0PLUS_NVIC_ISER_RESET _u(0x00000000) 156 // ----------------------------------------------------------------------------- 157 // Field : M0PLUS_NVIC_ISER_SETENA 158 // Description : Interrupt set-enable bits. 159 // Write: 160 // 0 = No effect. 161 // 1 = Enable interrupt. 162 // Read: 163 // 0 = Interrupt disabled. 164 // 1 = Interrupt enabled. 165 #define M0PLUS_NVIC_ISER_SETENA_RESET _u(0x00000000) 166 #define M0PLUS_NVIC_ISER_SETENA_BITS _u(0xffffffff) 167 #define M0PLUS_NVIC_ISER_SETENA_MSB _u(31) 168 #define M0PLUS_NVIC_ISER_SETENA_LSB _u(0) 169 #define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" 170 // ============================================================================= 171 // Register : M0PLUS_NVIC_ICER 172 // Description : Use the Interrupt Clear-Enable Registers to disable interrupts 173 // and determine which interrupts are currently enabled. 174 #define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180) 175 #define M0PLUS_NVIC_ICER_BITS _u(0xffffffff) 176 #define M0PLUS_NVIC_ICER_RESET _u(0x00000000) 177 // ----------------------------------------------------------------------------- 178 // Field : M0PLUS_NVIC_ICER_CLRENA 179 // Description : Interrupt clear-enable bits. 180 // Write: 181 // 0 = No effect. 182 // 1 = Disable interrupt. 183 // Read: 184 // 0 = Interrupt disabled. 185 // 1 = Interrupt enabled. 186 #define M0PLUS_NVIC_ICER_CLRENA_RESET _u(0x00000000) 187 #define M0PLUS_NVIC_ICER_CLRENA_BITS _u(0xffffffff) 188 #define M0PLUS_NVIC_ICER_CLRENA_MSB _u(31) 189 #define M0PLUS_NVIC_ICER_CLRENA_LSB _u(0) 190 #define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" 191 // ============================================================================= 192 // Register : M0PLUS_NVIC_ISPR 193 // Description : The NVIC_ISPR forces interrupts into the pending state, and 194 // shows which interrupts are pending. 195 #define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200) 196 #define M0PLUS_NVIC_ISPR_BITS _u(0xffffffff) 197 #define M0PLUS_NVIC_ISPR_RESET _u(0x00000000) 198 // ----------------------------------------------------------------------------- 199 // Field : M0PLUS_NVIC_ISPR_SETPEND 200 // Description : Interrupt set-pending bits. 201 // Write: 202 // 0 = No effect. 203 // 1 = Changes interrupt state to pending. 204 // Read: 205 // 0 = Interrupt is not pending. 206 // 1 = Interrupt is pending. 207 // Note: Writing 1 to the NVIC_ISPR bit corresponding to: 208 // An interrupt that is pending has no effect. 209 // A disabled interrupt sets the state of that interrupt to 210 // pending. 211 #define M0PLUS_NVIC_ISPR_SETPEND_RESET _u(0x00000000) 212 #define M0PLUS_NVIC_ISPR_SETPEND_BITS _u(0xffffffff) 213 #define M0PLUS_NVIC_ISPR_SETPEND_MSB _u(31) 214 #define M0PLUS_NVIC_ISPR_SETPEND_LSB _u(0) 215 #define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" 216 // ============================================================================= 217 // Register : M0PLUS_NVIC_ICPR 218 // Description : Use the Interrupt Clear-Pending Register to clear pending 219 // interrupts and determine which interrupts are currently 220 // pending. 221 #define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280) 222 #define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff) 223 #define M0PLUS_NVIC_ICPR_RESET _u(0x00000000) 224 // ----------------------------------------------------------------------------- 225 // Field : M0PLUS_NVIC_ICPR_CLRPEND 226 // Description : Interrupt clear-pending bits. 227 // Write: 228 // 0 = No effect. 229 // 1 = Removes pending state and interrupt. 230 // Read: 231 // 0 = Interrupt is not pending. 232 // 1 = Interrupt is pending. 233 #define M0PLUS_NVIC_ICPR_CLRPEND_RESET _u(0x00000000) 234 #define M0PLUS_NVIC_ICPR_CLRPEND_BITS _u(0xffffffff) 235 #define M0PLUS_NVIC_ICPR_CLRPEND_MSB _u(31) 236 #define M0PLUS_NVIC_ICPR_CLRPEND_LSB _u(0) 237 #define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" 238 // ============================================================================= 239 // Register : M0PLUS_NVIC_IPR0 240 // Description : Use the Interrupt Priority Registers to assign a priority from 241 // 0 to 3 to each of the available interrupts. 0 is the highest 242 // priority, and 3 is the lowest. 243 // Note: Writing 1 to an NVIC_ICPR bit does not affect the active 244 // state of the corresponding interrupt. 245 // These registers are only word-accessible 246 #define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400) 247 #define M0PLUS_NVIC_IPR0_BITS _u(0xc0c0c0c0) 248 #define M0PLUS_NVIC_IPR0_RESET _u(0x00000000) 249 // ----------------------------------------------------------------------------- 250 // Field : M0PLUS_NVIC_IPR0_IP_3 251 // Description : Priority of interrupt 3 252 #define M0PLUS_NVIC_IPR0_IP_3_RESET _u(0x0) 253 #define M0PLUS_NVIC_IPR0_IP_3_BITS _u(0xc0000000) 254 #define M0PLUS_NVIC_IPR0_IP_3_MSB _u(31) 255 #define M0PLUS_NVIC_IPR0_IP_3_LSB _u(30) 256 #define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" 257 // ----------------------------------------------------------------------------- 258 // Field : M0PLUS_NVIC_IPR0_IP_2 259 // Description : Priority of interrupt 2 260 #define M0PLUS_NVIC_IPR0_IP_2_RESET _u(0x0) 261 #define M0PLUS_NVIC_IPR0_IP_2_BITS _u(0x00c00000) 262 #define M0PLUS_NVIC_IPR0_IP_2_MSB _u(23) 263 #define M0PLUS_NVIC_IPR0_IP_2_LSB _u(22) 264 #define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" 265 // ----------------------------------------------------------------------------- 266 // Field : M0PLUS_NVIC_IPR0_IP_1 267 // Description : Priority of interrupt 1 268 #define M0PLUS_NVIC_IPR0_IP_1_RESET _u(0x0) 269 #define M0PLUS_NVIC_IPR0_IP_1_BITS _u(0x0000c000) 270 #define M0PLUS_NVIC_IPR0_IP_1_MSB _u(15) 271 #define M0PLUS_NVIC_IPR0_IP_1_LSB _u(14) 272 #define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" 273 // ----------------------------------------------------------------------------- 274 // Field : M0PLUS_NVIC_IPR0_IP_0 275 // Description : Priority of interrupt 0 276 #define M0PLUS_NVIC_IPR0_IP_0_RESET _u(0x0) 277 #define M0PLUS_NVIC_IPR0_IP_0_BITS _u(0x000000c0) 278 #define M0PLUS_NVIC_IPR0_IP_0_MSB _u(7) 279 #define M0PLUS_NVIC_IPR0_IP_0_LSB _u(6) 280 #define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" 281 // ============================================================================= 282 // Register : M0PLUS_NVIC_IPR1 283 // Description : Use the Interrupt Priority Registers to assign a priority from 284 // 0 to 3 to each of the available interrupts. 0 is the highest 285 // priority, and 3 is the lowest. 286 #define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404) 287 #define M0PLUS_NVIC_IPR1_BITS _u(0xc0c0c0c0) 288 #define M0PLUS_NVIC_IPR1_RESET _u(0x00000000) 289 // ----------------------------------------------------------------------------- 290 // Field : M0PLUS_NVIC_IPR1_IP_7 291 // Description : Priority of interrupt 7 292 #define M0PLUS_NVIC_IPR1_IP_7_RESET _u(0x0) 293 #define M0PLUS_NVIC_IPR1_IP_7_BITS _u(0xc0000000) 294 #define M0PLUS_NVIC_IPR1_IP_7_MSB _u(31) 295 #define M0PLUS_NVIC_IPR1_IP_7_LSB _u(30) 296 #define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" 297 // ----------------------------------------------------------------------------- 298 // Field : M0PLUS_NVIC_IPR1_IP_6 299 // Description : Priority of interrupt 6 300 #define M0PLUS_NVIC_IPR1_IP_6_RESET _u(0x0) 301 #define M0PLUS_NVIC_IPR1_IP_6_BITS _u(0x00c00000) 302 #define M0PLUS_NVIC_IPR1_IP_6_MSB _u(23) 303 #define M0PLUS_NVIC_IPR1_IP_6_LSB _u(22) 304 #define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" 305 // ----------------------------------------------------------------------------- 306 // Field : M0PLUS_NVIC_IPR1_IP_5 307 // Description : Priority of interrupt 5 308 #define M0PLUS_NVIC_IPR1_IP_5_RESET _u(0x0) 309 #define M0PLUS_NVIC_IPR1_IP_5_BITS _u(0x0000c000) 310 #define M0PLUS_NVIC_IPR1_IP_5_MSB _u(15) 311 #define M0PLUS_NVIC_IPR1_IP_5_LSB _u(14) 312 #define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" 313 // ----------------------------------------------------------------------------- 314 // Field : M0PLUS_NVIC_IPR1_IP_4 315 // Description : Priority of interrupt 4 316 #define M0PLUS_NVIC_IPR1_IP_4_RESET _u(0x0) 317 #define M0PLUS_NVIC_IPR1_IP_4_BITS _u(0x000000c0) 318 #define M0PLUS_NVIC_IPR1_IP_4_MSB _u(7) 319 #define M0PLUS_NVIC_IPR1_IP_4_LSB _u(6) 320 #define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" 321 // ============================================================================= 322 // Register : M0PLUS_NVIC_IPR2 323 // Description : Use the Interrupt Priority Registers to assign a priority from 324 // 0 to 3 to each of the available interrupts. 0 is the highest 325 // priority, and 3 is the lowest. 326 #define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408) 327 #define M0PLUS_NVIC_IPR2_BITS _u(0xc0c0c0c0) 328 #define M0PLUS_NVIC_IPR2_RESET _u(0x00000000) 329 // ----------------------------------------------------------------------------- 330 // Field : M0PLUS_NVIC_IPR2_IP_11 331 // Description : Priority of interrupt 11 332 #define M0PLUS_NVIC_IPR2_IP_11_RESET _u(0x0) 333 #define M0PLUS_NVIC_IPR2_IP_11_BITS _u(0xc0000000) 334 #define M0PLUS_NVIC_IPR2_IP_11_MSB _u(31) 335 #define M0PLUS_NVIC_IPR2_IP_11_LSB _u(30) 336 #define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" 337 // ----------------------------------------------------------------------------- 338 // Field : M0PLUS_NVIC_IPR2_IP_10 339 // Description : Priority of interrupt 10 340 #define M0PLUS_NVIC_IPR2_IP_10_RESET _u(0x0) 341 #define M0PLUS_NVIC_IPR2_IP_10_BITS _u(0x00c00000) 342 #define M0PLUS_NVIC_IPR2_IP_10_MSB _u(23) 343 #define M0PLUS_NVIC_IPR2_IP_10_LSB _u(22) 344 #define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" 345 // ----------------------------------------------------------------------------- 346 // Field : M0PLUS_NVIC_IPR2_IP_9 347 // Description : Priority of interrupt 9 348 #define M0PLUS_NVIC_IPR2_IP_9_RESET _u(0x0) 349 #define M0PLUS_NVIC_IPR2_IP_9_BITS _u(0x0000c000) 350 #define M0PLUS_NVIC_IPR2_IP_9_MSB _u(15) 351 #define M0PLUS_NVIC_IPR2_IP_9_LSB _u(14) 352 #define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" 353 // ----------------------------------------------------------------------------- 354 // Field : M0PLUS_NVIC_IPR2_IP_8 355 // Description : Priority of interrupt 8 356 #define M0PLUS_NVIC_IPR2_IP_8_RESET _u(0x0) 357 #define M0PLUS_NVIC_IPR2_IP_8_BITS _u(0x000000c0) 358 #define M0PLUS_NVIC_IPR2_IP_8_MSB _u(7) 359 #define M0PLUS_NVIC_IPR2_IP_8_LSB _u(6) 360 #define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" 361 // ============================================================================= 362 // Register : M0PLUS_NVIC_IPR3 363 // Description : Use the Interrupt Priority Registers to assign a priority from 364 // 0 to 3 to each of the available interrupts. 0 is the highest 365 // priority, and 3 is the lowest. 366 #define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c) 367 #define M0PLUS_NVIC_IPR3_BITS _u(0xc0c0c0c0) 368 #define M0PLUS_NVIC_IPR3_RESET _u(0x00000000) 369 // ----------------------------------------------------------------------------- 370 // Field : M0PLUS_NVIC_IPR3_IP_15 371 // Description : Priority of interrupt 15 372 #define M0PLUS_NVIC_IPR3_IP_15_RESET _u(0x0) 373 #define M0PLUS_NVIC_IPR3_IP_15_BITS _u(0xc0000000) 374 #define M0PLUS_NVIC_IPR3_IP_15_MSB _u(31) 375 #define M0PLUS_NVIC_IPR3_IP_15_LSB _u(30) 376 #define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" 377 // ----------------------------------------------------------------------------- 378 // Field : M0PLUS_NVIC_IPR3_IP_14 379 // Description : Priority of interrupt 14 380 #define M0PLUS_NVIC_IPR3_IP_14_RESET _u(0x0) 381 #define M0PLUS_NVIC_IPR3_IP_14_BITS _u(0x00c00000) 382 #define M0PLUS_NVIC_IPR3_IP_14_MSB _u(23) 383 #define M0PLUS_NVIC_IPR3_IP_14_LSB _u(22) 384 #define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" 385 // ----------------------------------------------------------------------------- 386 // Field : M0PLUS_NVIC_IPR3_IP_13 387 // Description : Priority of interrupt 13 388 #define M0PLUS_NVIC_IPR3_IP_13_RESET _u(0x0) 389 #define M0PLUS_NVIC_IPR3_IP_13_BITS _u(0x0000c000) 390 #define M0PLUS_NVIC_IPR3_IP_13_MSB _u(15) 391 #define M0PLUS_NVIC_IPR3_IP_13_LSB _u(14) 392 #define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" 393 // ----------------------------------------------------------------------------- 394 // Field : M0PLUS_NVIC_IPR3_IP_12 395 // Description : Priority of interrupt 12 396 #define M0PLUS_NVIC_IPR3_IP_12_RESET _u(0x0) 397 #define M0PLUS_NVIC_IPR3_IP_12_BITS _u(0x000000c0) 398 #define M0PLUS_NVIC_IPR3_IP_12_MSB _u(7) 399 #define M0PLUS_NVIC_IPR3_IP_12_LSB _u(6) 400 #define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" 401 // ============================================================================= 402 // Register : M0PLUS_NVIC_IPR4 403 // Description : Use the Interrupt Priority Registers to assign a priority from 404 // 0 to 3 to each of the available interrupts. 0 is the highest 405 // priority, and 3 is the lowest. 406 #define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410) 407 #define M0PLUS_NVIC_IPR4_BITS _u(0xc0c0c0c0) 408 #define M0PLUS_NVIC_IPR4_RESET _u(0x00000000) 409 // ----------------------------------------------------------------------------- 410 // Field : M0PLUS_NVIC_IPR4_IP_19 411 // Description : Priority of interrupt 19 412 #define M0PLUS_NVIC_IPR4_IP_19_RESET _u(0x0) 413 #define M0PLUS_NVIC_IPR4_IP_19_BITS _u(0xc0000000) 414 #define M0PLUS_NVIC_IPR4_IP_19_MSB _u(31) 415 #define M0PLUS_NVIC_IPR4_IP_19_LSB _u(30) 416 #define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" 417 // ----------------------------------------------------------------------------- 418 // Field : M0PLUS_NVIC_IPR4_IP_18 419 // Description : Priority of interrupt 18 420 #define M0PLUS_NVIC_IPR4_IP_18_RESET _u(0x0) 421 #define M0PLUS_NVIC_IPR4_IP_18_BITS _u(0x00c00000) 422 #define M0PLUS_NVIC_IPR4_IP_18_MSB _u(23) 423 #define M0PLUS_NVIC_IPR4_IP_18_LSB _u(22) 424 #define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" 425 // ----------------------------------------------------------------------------- 426 // Field : M0PLUS_NVIC_IPR4_IP_17 427 // Description : Priority of interrupt 17 428 #define M0PLUS_NVIC_IPR4_IP_17_RESET _u(0x0) 429 #define M0PLUS_NVIC_IPR4_IP_17_BITS _u(0x0000c000) 430 #define M0PLUS_NVIC_IPR4_IP_17_MSB _u(15) 431 #define M0PLUS_NVIC_IPR4_IP_17_LSB _u(14) 432 #define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" 433 // ----------------------------------------------------------------------------- 434 // Field : M0PLUS_NVIC_IPR4_IP_16 435 // Description : Priority of interrupt 16 436 #define M0PLUS_NVIC_IPR4_IP_16_RESET _u(0x0) 437 #define M0PLUS_NVIC_IPR4_IP_16_BITS _u(0x000000c0) 438 #define M0PLUS_NVIC_IPR4_IP_16_MSB _u(7) 439 #define M0PLUS_NVIC_IPR4_IP_16_LSB _u(6) 440 #define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" 441 // ============================================================================= 442 // Register : M0PLUS_NVIC_IPR5 443 // Description : Use the Interrupt Priority Registers to assign a priority from 444 // 0 to 3 to each of the available interrupts. 0 is the highest 445 // priority, and 3 is the lowest. 446 #define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414) 447 #define M0PLUS_NVIC_IPR5_BITS _u(0xc0c0c0c0) 448 #define M0PLUS_NVIC_IPR5_RESET _u(0x00000000) 449 // ----------------------------------------------------------------------------- 450 // Field : M0PLUS_NVIC_IPR5_IP_23 451 // Description : Priority of interrupt 23 452 #define M0PLUS_NVIC_IPR5_IP_23_RESET _u(0x0) 453 #define M0PLUS_NVIC_IPR5_IP_23_BITS _u(0xc0000000) 454 #define M0PLUS_NVIC_IPR5_IP_23_MSB _u(31) 455 #define M0PLUS_NVIC_IPR5_IP_23_LSB _u(30) 456 #define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" 457 // ----------------------------------------------------------------------------- 458 // Field : M0PLUS_NVIC_IPR5_IP_22 459 // Description : Priority of interrupt 22 460 #define M0PLUS_NVIC_IPR5_IP_22_RESET _u(0x0) 461 #define M0PLUS_NVIC_IPR5_IP_22_BITS _u(0x00c00000) 462 #define M0PLUS_NVIC_IPR5_IP_22_MSB _u(23) 463 #define M0PLUS_NVIC_IPR5_IP_22_LSB _u(22) 464 #define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" 465 // ----------------------------------------------------------------------------- 466 // Field : M0PLUS_NVIC_IPR5_IP_21 467 // Description : Priority of interrupt 21 468 #define M0PLUS_NVIC_IPR5_IP_21_RESET _u(0x0) 469 #define M0PLUS_NVIC_IPR5_IP_21_BITS _u(0x0000c000) 470 #define M0PLUS_NVIC_IPR5_IP_21_MSB _u(15) 471 #define M0PLUS_NVIC_IPR5_IP_21_LSB _u(14) 472 #define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" 473 // ----------------------------------------------------------------------------- 474 // Field : M0PLUS_NVIC_IPR5_IP_20 475 // Description : Priority of interrupt 20 476 #define M0PLUS_NVIC_IPR5_IP_20_RESET _u(0x0) 477 #define M0PLUS_NVIC_IPR5_IP_20_BITS _u(0x000000c0) 478 #define M0PLUS_NVIC_IPR5_IP_20_MSB _u(7) 479 #define M0PLUS_NVIC_IPR5_IP_20_LSB _u(6) 480 #define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" 481 // ============================================================================= 482 // Register : M0PLUS_NVIC_IPR6 483 // Description : Use the Interrupt Priority Registers to assign a priority from 484 // 0 to 3 to each of the available interrupts. 0 is the highest 485 // priority, and 3 is the lowest. 486 #define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418) 487 #define M0PLUS_NVIC_IPR6_BITS _u(0xc0c0c0c0) 488 #define M0PLUS_NVIC_IPR6_RESET _u(0x00000000) 489 // ----------------------------------------------------------------------------- 490 // Field : M0PLUS_NVIC_IPR6_IP_27 491 // Description : Priority of interrupt 27 492 #define M0PLUS_NVIC_IPR6_IP_27_RESET _u(0x0) 493 #define M0PLUS_NVIC_IPR6_IP_27_BITS _u(0xc0000000) 494 #define M0PLUS_NVIC_IPR6_IP_27_MSB _u(31) 495 #define M0PLUS_NVIC_IPR6_IP_27_LSB _u(30) 496 #define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" 497 // ----------------------------------------------------------------------------- 498 // Field : M0PLUS_NVIC_IPR6_IP_26 499 // Description : Priority of interrupt 26 500 #define M0PLUS_NVIC_IPR6_IP_26_RESET _u(0x0) 501 #define M0PLUS_NVIC_IPR6_IP_26_BITS _u(0x00c00000) 502 #define M0PLUS_NVIC_IPR6_IP_26_MSB _u(23) 503 #define M0PLUS_NVIC_IPR6_IP_26_LSB _u(22) 504 #define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" 505 // ----------------------------------------------------------------------------- 506 // Field : M0PLUS_NVIC_IPR6_IP_25 507 // Description : Priority of interrupt 25 508 #define M0PLUS_NVIC_IPR6_IP_25_RESET _u(0x0) 509 #define M0PLUS_NVIC_IPR6_IP_25_BITS _u(0x0000c000) 510 #define M0PLUS_NVIC_IPR6_IP_25_MSB _u(15) 511 #define M0PLUS_NVIC_IPR6_IP_25_LSB _u(14) 512 #define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" 513 // ----------------------------------------------------------------------------- 514 // Field : M0PLUS_NVIC_IPR6_IP_24 515 // Description : Priority of interrupt 24 516 #define M0PLUS_NVIC_IPR6_IP_24_RESET _u(0x0) 517 #define M0PLUS_NVIC_IPR6_IP_24_BITS _u(0x000000c0) 518 #define M0PLUS_NVIC_IPR6_IP_24_MSB _u(7) 519 #define M0PLUS_NVIC_IPR6_IP_24_LSB _u(6) 520 #define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" 521 // ============================================================================= 522 // Register : M0PLUS_NVIC_IPR7 523 // Description : Use the Interrupt Priority Registers to assign a priority from 524 // 0 to 3 to each of the available interrupts. 0 is the highest 525 // priority, and 3 is the lowest. 526 #define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c) 527 #define M0PLUS_NVIC_IPR7_BITS _u(0xc0c0c0c0) 528 #define M0PLUS_NVIC_IPR7_RESET _u(0x00000000) 529 // ----------------------------------------------------------------------------- 530 // Field : M0PLUS_NVIC_IPR7_IP_31 531 // Description : Priority of interrupt 31 532 #define M0PLUS_NVIC_IPR7_IP_31_RESET _u(0x0) 533 #define M0PLUS_NVIC_IPR7_IP_31_BITS _u(0xc0000000) 534 #define M0PLUS_NVIC_IPR7_IP_31_MSB _u(31) 535 #define M0PLUS_NVIC_IPR7_IP_31_LSB _u(30) 536 #define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" 537 // ----------------------------------------------------------------------------- 538 // Field : M0PLUS_NVIC_IPR7_IP_30 539 // Description : Priority of interrupt 30 540 #define M0PLUS_NVIC_IPR7_IP_30_RESET _u(0x0) 541 #define M0PLUS_NVIC_IPR7_IP_30_BITS _u(0x00c00000) 542 #define M0PLUS_NVIC_IPR7_IP_30_MSB _u(23) 543 #define M0PLUS_NVIC_IPR7_IP_30_LSB _u(22) 544 #define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" 545 // ----------------------------------------------------------------------------- 546 // Field : M0PLUS_NVIC_IPR7_IP_29 547 // Description : Priority of interrupt 29 548 #define M0PLUS_NVIC_IPR7_IP_29_RESET _u(0x0) 549 #define M0PLUS_NVIC_IPR7_IP_29_BITS _u(0x0000c000) 550 #define M0PLUS_NVIC_IPR7_IP_29_MSB _u(15) 551 #define M0PLUS_NVIC_IPR7_IP_29_LSB _u(14) 552 #define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" 553 // ----------------------------------------------------------------------------- 554 // Field : M0PLUS_NVIC_IPR7_IP_28 555 // Description : Priority of interrupt 28 556 #define M0PLUS_NVIC_IPR7_IP_28_RESET _u(0x0) 557 #define M0PLUS_NVIC_IPR7_IP_28_BITS _u(0x000000c0) 558 #define M0PLUS_NVIC_IPR7_IP_28_MSB _u(7) 559 #define M0PLUS_NVIC_IPR7_IP_28_LSB _u(6) 560 #define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" 561 // ============================================================================= 562 // Register : M0PLUS_CPUID 563 // Description : Read the CPU ID Base Register to determine: the ID number of 564 // the processor core, the version number of the processor core, 565 // the implementation details of the processor core. 566 #define M0PLUS_CPUID_OFFSET _u(0x0000ed00) 567 #define M0PLUS_CPUID_BITS _u(0xffffffff) 568 #define M0PLUS_CPUID_RESET _u(0x410cc601) 569 // ----------------------------------------------------------------------------- 570 // Field : M0PLUS_CPUID_IMPLEMENTER 571 // Description : Implementor code: 0x41 = ARM 572 #define M0PLUS_CPUID_IMPLEMENTER_RESET _u(0x41) 573 #define M0PLUS_CPUID_IMPLEMENTER_BITS _u(0xff000000) 574 #define M0PLUS_CPUID_IMPLEMENTER_MSB _u(31) 575 #define M0PLUS_CPUID_IMPLEMENTER_LSB _u(24) 576 #define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" 577 // ----------------------------------------------------------------------------- 578 // Field : M0PLUS_CPUID_VARIANT 579 // Description : Major revision number n in the rnpm revision status: 580 // 0x0 = Revision 0. 581 #define M0PLUS_CPUID_VARIANT_RESET _u(0x0) 582 #define M0PLUS_CPUID_VARIANT_BITS _u(0x00f00000) 583 #define M0PLUS_CPUID_VARIANT_MSB _u(23) 584 #define M0PLUS_CPUID_VARIANT_LSB _u(20) 585 #define M0PLUS_CPUID_VARIANT_ACCESS "RO" 586 // ----------------------------------------------------------------------------- 587 // Field : M0PLUS_CPUID_ARCHITECTURE 588 // Description : Constant that defines the architecture of the processor: 589 // 0xC = ARMv6-M architecture. 590 #define M0PLUS_CPUID_ARCHITECTURE_RESET _u(0xc) 591 #define M0PLUS_CPUID_ARCHITECTURE_BITS _u(0x000f0000) 592 #define M0PLUS_CPUID_ARCHITECTURE_MSB _u(19) 593 #define M0PLUS_CPUID_ARCHITECTURE_LSB _u(16) 594 #define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" 595 // ----------------------------------------------------------------------------- 596 // Field : M0PLUS_CPUID_PARTNO 597 // Description : Number of processor within family: 0xC60 = Cortex-M0+ 598 #define M0PLUS_CPUID_PARTNO_RESET _u(0xc60) 599 #define M0PLUS_CPUID_PARTNO_BITS _u(0x0000fff0) 600 #define M0PLUS_CPUID_PARTNO_MSB _u(15) 601 #define M0PLUS_CPUID_PARTNO_LSB _u(4) 602 #define M0PLUS_CPUID_PARTNO_ACCESS "RO" 603 // ----------------------------------------------------------------------------- 604 // Field : M0PLUS_CPUID_REVISION 605 // Description : Minor revision number m in the rnpm revision status: 606 // 0x1 = Patch 1. 607 #define M0PLUS_CPUID_REVISION_RESET _u(0x1) 608 #define M0PLUS_CPUID_REVISION_BITS _u(0x0000000f) 609 #define M0PLUS_CPUID_REVISION_MSB _u(3) 610 #define M0PLUS_CPUID_REVISION_LSB _u(0) 611 #define M0PLUS_CPUID_REVISION_ACCESS "RO" 612 // ============================================================================= 613 // Register : M0PLUS_ICSR 614 // Description : Use the Interrupt Control State Register to set a pending Non- 615 // Maskable Interrupt (NMI), set or clear a pending PendSV, set or 616 // clear a pending SysTick, check for pending exceptions, check 617 // the vector number of the highest priority pended exception, 618 // check the vector number of the active exception. 619 #define M0PLUS_ICSR_OFFSET _u(0x0000ed04) 620 #define M0PLUS_ICSR_BITS _u(0x9edff1ff) 621 #define M0PLUS_ICSR_RESET _u(0x00000000) 622 // ----------------------------------------------------------------------------- 623 // Field : M0PLUS_ICSR_NMIPENDSET 624 // Description : Setting this bit will activate an NMI. Since NMI is the highest 625 // priority exception, it will activate as soon as it is 626 // registered. 627 // NMI set-pending bit. 628 // Write: 629 // 0 = No effect. 630 // 1 = Changes NMI exception state to pending. 631 // Read: 632 // 0 = NMI exception is not pending. 633 // 1 = NMI exception is pending. 634 // Because NMI is the highest-priority exception, normally the 635 // processor enters the NMI 636 // exception handler as soon as it detects a write of 1 to this 637 // bit. Entering the handler then clears 638 // this bit to 0. This means a read of this bit by the NMI 639 // exception handler returns 1 only if the 640 // NMI signal is reasserted while the processor is executing that 641 // handler. 642 #define M0PLUS_ICSR_NMIPENDSET_RESET _u(0x0) 643 #define M0PLUS_ICSR_NMIPENDSET_BITS _u(0x80000000) 644 #define M0PLUS_ICSR_NMIPENDSET_MSB _u(31) 645 #define M0PLUS_ICSR_NMIPENDSET_LSB _u(31) 646 #define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" 647 // ----------------------------------------------------------------------------- 648 // Field : M0PLUS_ICSR_PENDSVSET 649 // Description : PendSV set-pending bit. 650 // Write: 651 // 0 = No effect. 652 // 1 = Changes PendSV exception state to pending. 653 // Read: 654 // 0 = PendSV exception is not pending. 655 // 1 = PendSV exception is pending. 656 // Writing 1 to this bit is the only way to set the PendSV 657 // exception state to pending. 658 #define M0PLUS_ICSR_PENDSVSET_RESET _u(0x0) 659 #define M0PLUS_ICSR_PENDSVSET_BITS _u(0x10000000) 660 #define M0PLUS_ICSR_PENDSVSET_MSB _u(28) 661 #define M0PLUS_ICSR_PENDSVSET_LSB _u(28) 662 #define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" 663 // ----------------------------------------------------------------------------- 664 // Field : M0PLUS_ICSR_PENDSVCLR 665 // Description : PendSV clear-pending bit. 666 // Write: 667 // 0 = No effect. 668 // 1 = Removes the pending state from the PendSV exception. 669 #define M0PLUS_ICSR_PENDSVCLR_RESET _u(0x0) 670 #define M0PLUS_ICSR_PENDSVCLR_BITS _u(0x08000000) 671 #define M0PLUS_ICSR_PENDSVCLR_MSB _u(27) 672 #define M0PLUS_ICSR_PENDSVCLR_LSB _u(27) 673 #define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" 674 // ----------------------------------------------------------------------------- 675 // Field : M0PLUS_ICSR_PENDSTSET 676 // Description : SysTick exception set-pending bit. 677 // Write: 678 // 0 = No effect. 679 // 1 = Changes SysTick exception state to pending. 680 // Read: 681 // 0 = SysTick exception is not pending. 682 // 1 = SysTick exception is pending. 683 #define M0PLUS_ICSR_PENDSTSET_RESET _u(0x0) 684 #define M0PLUS_ICSR_PENDSTSET_BITS _u(0x04000000) 685 #define M0PLUS_ICSR_PENDSTSET_MSB _u(26) 686 #define M0PLUS_ICSR_PENDSTSET_LSB _u(26) 687 #define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" 688 // ----------------------------------------------------------------------------- 689 // Field : M0PLUS_ICSR_PENDSTCLR 690 // Description : SysTick exception clear-pending bit. 691 // Write: 692 // 0 = No effect. 693 // 1 = Removes the pending state from the SysTick exception. 694 // This bit is WO. On a register read its value is Unknown. 695 #define M0PLUS_ICSR_PENDSTCLR_RESET _u(0x0) 696 #define M0PLUS_ICSR_PENDSTCLR_BITS _u(0x02000000) 697 #define M0PLUS_ICSR_PENDSTCLR_MSB _u(25) 698 #define M0PLUS_ICSR_PENDSTCLR_LSB _u(25) 699 #define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" 700 // ----------------------------------------------------------------------------- 701 // Field : M0PLUS_ICSR_ISRPREEMPT 702 // Description : The system can only access this bit when the core is halted. It 703 // indicates that a pending interrupt is to be taken in the next 704 // running cycle. If C_MASKINTS is clear in the Debug Halting 705 // Control and Status Register, the interrupt is serviced. 706 #define M0PLUS_ICSR_ISRPREEMPT_RESET _u(0x0) 707 #define M0PLUS_ICSR_ISRPREEMPT_BITS _u(0x00800000) 708 #define M0PLUS_ICSR_ISRPREEMPT_MSB _u(23) 709 #define M0PLUS_ICSR_ISRPREEMPT_LSB _u(23) 710 #define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" 711 // ----------------------------------------------------------------------------- 712 // Field : M0PLUS_ICSR_ISRPENDING 713 // Description : External interrupt pending flag 714 #define M0PLUS_ICSR_ISRPENDING_RESET _u(0x0) 715 #define M0PLUS_ICSR_ISRPENDING_BITS _u(0x00400000) 716 #define M0PLUS_ICSR_ISRPENDING_MSB _u(22) 717 #define M0PLUS_ICSR_ISRPENDING_LSB _u(22) 718 #define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" 719 // ----------------------------------------------------------------------------- 720 // Field : M0PLUS_ICSR_VECTPENDING 721 // Description : Indicates the exception number for the highest priority pending 722 // exception: 0 = no pending exceptions. Non zero = The pending 723 // state includes the effect of memory-mapped enable and mask 724 // registers. It does not include the PRIMASK special-purpose 725 // register qualifier. 726 #define M0PLUS_ICSR_VECTPENDING_RESET _u(0x000) 727 #define M0PLUS_ICSR_VECTPENDING_BITS _u(0x001ff000) 728 #define M0PLUS_ICSR_VECTPENDING_MSB _u(20) 729 #define M0PLUS_ICSR_VECTPENDING_LSB _u(12) 730 #define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" 731 // ----------------------------------------------------------------------------- 732 // Field : M0PLUS_ICSR_VECTACTIVE 733 // Description : Active exception number field. Reset clears the VECTACTIVE 734 // field. 735 #define M0PLUS_ICSR_VECTACTIVE_RESET _u(0x000) 736 #define M0PLUS_ICSR_VECTACTIVE_BITS _u(0x000001ff) 737 #define M0PLUS_ICSR_VECTACTIVE_MSB _u(8) 738 #define M0PLUS_ICSR_VECTACTIVE_LSB _u(0) 739 #define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" 740 // ============================================================================= 741 // Register : M0PLUS_VTOR 742 // Description : The VTOR holds the vector table offset address. 743 #define M0PLUS_VTOR_OFFSET _u(0x0000ed08) 744 #define M0PLUS_VTOR_BITS _u(0xffffff00) 745 #define M0PLUS_VTOR_RESET _u(0x00000000) 746 // ----------------------------------------------------------------------------- 747 // Field : M0PLUS_VTOR_TBLOFF 748 // Description : Bits [31:8] of the indicate the vector table offset address. 749 #define M0PLUS_VTOR_TBLOFF_RESET _u(0x000000) 750 #define M0PLUS_VTOR_TBLOFF_BITS _u(0xffffff00) 751 #define M0PLUS_VTOR_TBLOFF_MSB _u(31) 752 #define M0PLUS_VTOR_TBLOFF_LSB _u(8) 753 #define M0PLUS_VTOR_TBLOFF_ACCESS "RW" 754 // ============================================================================= 755 // Register : M0PLUS_AIRCR 756 // Description : Use the Application Interrupt and Reset Control Register to: 757 // determine data endianness, clear all active state information 758 // from debug halt mode, request a system reset. 759 #define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c) 760 #define M0PLUS_AIRCR_BITS _u(0xffff8006) 761 #define M0PLUS_AIRCR_RESET _u(0x00000000) 762 // ----------------------------------------------------------------------------- 763 // Field : M0PLUS_AIRCR_VECTKEY 764 // Description : Register key: 765 // Reads as Unknown 766 // On writes, write 0x05FA to VECTKEY, otherwise the write is 767 // ignored. 768 #define M0PLUS_AIRCR_VECTKEY_RESET _u(0x0000) 769 #define M0PLUS_AIRCR_VECTKEY_BITS _u(0xffff0000) 770 #define M0PLUS_AIRCR_VECTKEY_MSB _u(31) 771 #define M0PLUS_AIRCR_VECTKEY_LSB _u(16) 772 #define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" 773 // ----------------------------------------------------------------------------- 774 // Field : M0PLUS_AIRCR_ENDIANESS 775 // Description : Data endianness implemented: 776 // 0 = Little-endian. 777 #define M0PLUS_AIRCR_ENDIANESS_RESET _u(0x0) 778 #define M0PLUS_AIRCR_ENDIANESS_BITS _u(0x00008000) 779 #define M0PLUS_AIRCR_ENDIANESS_MSB _u(15) 780 #define M0PLUS_AIRCR_ENDIANESS_LSB _u(15) 781 #define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" 782 // ----------------------------------------------------------------------------- 783 // Field : M0PLUS_AIRCR_SYSRESETREQ 784 // Description : Writing 1 to this bit causes the SYSRESETREQ signal to the 785 // outer system to be asserted to request a reset. The intention 786 // is to force a large system reset of all major components except 787 // for debug. The C_HALT bit in the DHCSR is cleared as a result 788 // of the system reset requested. The debugger does not lose 789 // contact with the device. 790 #define M0PLUS_AIRCR_SYSRESETREQ_RESET _u(0x0) 791 #define M0PLUS_AIRCR_SYSRESETREQ_BITS _u(0x00000004) 792 #define M0PLUS_AIRCR_SYSRESETREQ_MSB _u(2) 793 #define M0PLUS_AIRCR_SYSRESETREQ_LSB _u(2) 794 #define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" 795 // ----------------------------------------------------------------------------- 796 // Field : M0PLUS_AIRCR_VECTCLRACTIVE 797 // Description : Clears all active state information for fixed and configurable 798 // exceptions. This bit: is self-clearing, can only be set by the 799 // DAP when the core is halted. When set: clears all active 800 // exception status of the processor, forces a return to Thread 801 // mode, forces an IPSR of 0. A debugger must re-initialize the 802 // stack. 803 #define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _u(0x0) 804 #define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) 805 #define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _u(1) 806 #define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _u(1) 807 #define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" 808 // ============================================================================= 809 // Register : M0PLUS_SCR 810 // Description : System Control Register. Use the System Control Register for 811 // power-management functions: signal to the system when the 812 // processor can enter a low power state, control how the 813 // processor enters and exits low power states. 814 #define M0PLUS_SCR_OFFSET _u(0x0000ed10) 815 #define M0PLUS_SCR_BITS _u(0x00000016) 816 #define M0PLUS_SCR_RESET _u(0x00000000) 817 // ----------------------------------------------------------------------------- 818 // Field : M0PLUS_SCR_SEVONPEND 819 // Description : Send Event on Pending bit: 820 // 0 = Only enabled interrupts or events can wakeup the processor, 821 // disabled interrupts are excluded. 822 // 1 = Enabled events and all interrupts, including disabled 823 // interrupts, can wakeup the processor. 824 // When an event or interrupt becomes pending, the event signal 825 // wakes up the processor from WFE. If the 826 // processor is not waiting for an event, the event is registered 827 // and affects the next WFE. 828 // The processor also wakes up on execution of an SEV instruction 829 // or an external event. 830 #define M0PLUS_SCR_SEVONPEND_RESET _u(0x0) 831 #define M0PLUS_SCR_SEVONPEND_BITS _u(0x00000010) 832 #define M0PLUS_SCR_SEVONPEND_MSB _u(4) 833 #define M0PLUS_SCR_SEVONPEND_LSB _u(4) 834 #define M0PLUS_SCR_SEVONPEND_ACCESS "RW" 835 // ----------------------------------------------------------------------------- 836 // Field : M0PLUS_SCR_SLEEPDEEP 837 // Description : Controls whether the processor uses sleep or deep sleep as its 838 // low power mode: 839 // 0 = Sleep. 840 // 1 = Deep sleep. 841 #define M0PLUS_SCR_SLEEPDEEP_RESET _u(0x0) 842 #define M0PLUS_SCR_SLEEPDEEP_BITS _u(0x00000004) 843 #define M0PLUS_SCR_SLEEPDEEP_MSB _u(2) 844 #define M0PLUS_SCR_SLEEPDEEP_LSB _u(2) 845 #define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" 846 // ----------------------------------------------------------------------------- 847 // Field : M0PLUS_SCR_SLEEPONEXIT 848 // Description : Indicates sleep-on-exit when returning from Handler mode to 849 // Thread mode: 850 // 0 = Do not sleep when returning to Thread mode. 851 // 1 = Enter sleep, or deep sleep, on return from an ISR to Thread 852 // mode. 853 // Setting this bit to 1 enables an interrupt driven application 854 // to avoid returning to an empty main application. 855 #define M0PLUS_SCR_SLEEPONEXIT_RESET _u(0x0) 856 #define M0PLUS_SCR_SLEEPONEXIT_BITS _u(0x00000002) 857 #define M0PLUS_SCR_SLEEPONEXIT_MSB _u(1) 858 #define M0PLUS_SCR_SLEEPONEXIT_LSB _u(1) 859 #define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" 860 // ============================================================================= 861 // Register : M0PLUS_CCR 862 // Description : The Configuration and Control Register permanently enables 863 // stack alignment and causes unaligned accesses to result in a 864 // Hard Fault. 865 #define M0PLUS_CCR_OFFSET _u(0x0000ed14) 866 #define M0PLUS_CCR_BITS _u(0x00000208) 867 #define M0PLUS_CCR_RESET _u(0x00000000) 868 // ----------------------------------------------------------------------------- 869 // Field : M0PLUS_CCR_STKALIGN 870 // Description : Always reads as one, indicates 8-byte stack alignment on 871 // exception entry. On exception entry, the processor uses bit[9] 872 // of the stacked PSR to indicate the stack alignment. On return 873 // from the exception it uses this stacked bit to restore the 874 // correct stack alignment. 875 #define M0PLUS_CCR_STKALIGN_RESET _u(0x0) 876 #define M0PLUS_CCR_STKALIGN_BITS _u(0x00000200) 877 #define M0PLUS_CCR_STKALIGN_MSB _u(9) 878 #define M0PLUS_CCR_STKALIGN_LSB _u(9) 879 #define M0PLUS_CCR_STKALIGN_ACCESS "RO" 880 // ----------------------------------------------------------------------------- 881 // Field : M0PLUS_CCR_UNALIGN_TRP 882 // Description : Always reads as one, indicates that all unaligned accesses 883 // generate a HardFault. 884 #define M0PLUS_CCR_UNALIGN_TRP_RESET _u(0x0) 885 #define M0PLUS_CCR_UNALIGN_TRP_BITS _u(0x00000008) 886 #define M0PLUS_CCR_UNALIGN_TRP_MSB _u(3) 887 #define M0PLUS_CCR_UNALIGN_TRP_LSB _u(3) 888 #define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" 889 // ============================================================================= 890 // Register : M0PLUS_SHPR2 891 // Description : System handlers are a special class of exception handler that 892 // can have their priority set to any of the priority levels. Use 893 // the System Handler Priority Register 2 to set the priority of 894 // SVCall. 895 #define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c) 896 #define M0PLUS_SHPR2_BITS _u(0xc0000000) 897 #define M0PLUS_SHPR2_RESET _u(0x00000000) 898 // ----------------------------------------------------------------------------- 899 // Field : M0PLUS_SHPR2_PRI_11 900 // Description : Priority of system handler 11, SVCall 901 #define M0PLUS_SHPR2_PRI_11_RESET _u(0x0) 902 #define M0PLUS_SHPR2_PRI_11_BITS _u(0xc0000000) 903 #define M0PLUS_SHPR2_PRI_11_MSB _u(31) 904 #define M0PLUS_SHPR2_PRI_11_LSB _u(30) 905 #define M0PLUS_SHPR2_PRI_11_ACCESS "RW" 906 // ============================================================================= 907 // Register : M0PLUS_SHPR3 908 // Description : System handlers are a special class of exception handler that 909 // can have their priority set to any of the priority levels. Use 910 // the System Handler Priority Register 3 to set the priority of 911 // PendSV and SysTick. 912 #define M0PLUS_SHPR3_OFFSET _u(0x0000ed20) 913 #define M0PLUS_SHPR3_BITS _u(0xc0c00000) 914 #define M0PLUS_SHPR3_RESET _u(0x00000000) 915 // ----------------------------------------------------------------------------- 916 // Field : M0PLUS_SHPR3_PRI_15 917 // Description : Priority of system handler 15, SysTick 918 #define M0PLUS_SHPR3_PRI_15_RESET _u(0x0) 919 #define M0PLUS_SHPR3_PRI_15_BITS _u(0xc0000000) 920 #define M0PLUS_SHPR3_PRI_15_MSB _u(31) 921 #define M0PLUS_SHPR3_PRI_15_LSB _u(30) 922 #define M0PLUS_SHPR3_PRI_15_ACCESS "RW" 923 // ----------------------------------------------------------------------------- 924 // Field : M0PLUS_SHPR3_PRI_14 925 // Description : Priority of system handler 14, PendSV 926 #define M0PLUS_SHPR3_PRI_14_RESET _u(0x0) 927 #define M0PLUS_SHPR3_PRI_14_BITS _u(0x00c00000) 928 #define M0PLUS_SHPR3_PRI_14_MSB _u(23) 929 #define M0PLUS_SHPR3_PRI_14_LSB _u(22) 930 #define M0PLUS_SHPR3_PRI_14_ACCESS "RW" 931 // ============================================================================= 932 // Register : M0PLUS_SHCSR 933 // Description : Use the System Handler Control and State Register to determine 934 // or clear the pending status of SVCall. 935 #define M0PLUS_SHCSR_OFFSET _u(0x0000ed24) 936 #define M0PLUS_SHCSR_BITS _u(0x00008000) 937 #define M0PLUS_SHCSR_RESET _u(0x00000000) 938 // ----------------------------------------------------------------------------- 939 // Field : M0PLUS_SHCSR_SVCALLPENDED 940 // Description : Reads as 1 if SVCall is Pending. Write 1 to set pending 941 // SVCall, write 0 to clear pending SVCall. 942 #define M0PLUS_SHCSR_SVCALLPENDED_RESET _u(0x0) 943 #define M0PLUS_SHCSR_SVCALLPENDED_BITS _u(0x00008000) 944 #define M0PLUS_SHCSR_SVCALLPENDED_MSB _u(15) 945 #define M0PLUS_SHCSR_SVCALLPENDED_LSB _u(15) 946 #define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" 947 // ============================================================================= 948 // Register : M0PLUS_MPU_TYPE 949 // Description : Read the MPU Type Register to determine if the processor 950 // implements an MPU, and how many regions the MPU supports. 951 #define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90) 952 #define M0PLUS_MPU_TYPE_BITS _u(0x00ffff01) 953 #define M0PLUS_MPU_TYPE_RESET _u(0x00000800) 954 // ----------------------------------------------------------------------------- 955 // Field : M0PLUS_MPU_TYPE_IREGION 956 // Description : Instruction region. Reads as zero as ARMv6-M only supports a 957 // unified MPU. 958 #define M0PLUS_MPU_TYPE_IREGION_RESET _u(0x00) 959 #define M0PLUS_MPU_TYPE_IREGION_BITS _u(0x00ff0000) 960 #define M0PLUS_MPU_TYPE_IREGION_MSB _u(23) 961 #define M0PLUS_MPU_TYPE_IREGION_LSB _u(16) 962 #define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" 963 // ----------------------------------------------------------------------------- 964 // Field : M0PLUS_MPU_TYPE_DREGION 965 // Description : Number of regions supported by the MPU. 966 #define M0PLUS_MPU_TYPE_DREGION_RESET _u(0x08) 967 #define M0PLUS_MPU_TYPE_DREGION_BITS _u(0x0000ff00) 968 #define M0PLUS_MPU_TYPE_DREGION_MSB _u(15) 969 #define M0PLUS_MPU_TYPE_DREGION_LSB _u(8) 970 #define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" 971 // ----------------------------------------------------------------------------- 972 // Field : M0PLUS_MPU_TYPE_SEPARATE 973 // Description : Indicates support for separate instruction and data address 974 // maps. Reads as 0 as ARMv6-M only supports a unified MPU. 975 #define M0PLUS_MPU_TYPE_SEPARATE_RESET _u(0x0) 976 #define M0PLUS_MPU_TYPE_SEPARATE_BITS _u(0x00000001) 977 #define M0PLUS_MPU_TYPE_SEPARATE_MSB _u(0) 978 #define M0PLUS_MPU_TYPE_SEPARATE_LSB _u(0) 979 #define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" 980 // ============================================================================= 981 // Register : M0PLUS_MPU_CTRL 982 // Description : Use the MPU Control Register to enable and disable the MPU, and 983 // to control whether the default memory map is enabled as a 984 // background region for privileged accesses, and whether the MPU 985 // is enabled for HardFaults and NMIs. 986 #define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94) 987 #define M0PLUS_MPU_CTRL_BITS _u(0x00000007) 988 #define M0PLUS_MPU_CTRL_RESET _u(0x00000000) 989 // ----------------------------------------------------------------------------- 990 // Field : M0PLUS_MPU_CTRL_PRIVDEFENA 991 // Description : Controls whether the default memory map is enabled as a 992 // background region for privileged accesses. This bit is ignored 993 // when ENABLE is clear. 994 // 0 = If the MPU is enabled, disables use of the default memory 995 // map. Any memory access to a location not 996 // covered by any enabled region causes a fault. 997 // 1 = If the MPU is enabled, enables use of the default memory 998 // map as a background region for privileged software accesses. 999 // When enabled, the background region acts as if it is region 1000 // number -1. Any region that is defined and enabled has priority 1001 // over this default map. 1002 #define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) 1003 #define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) 1004 #define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _u(2) 1005 #define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _u(2) 1006 #define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" 1007 // ----------------------------------------------------------------------------- 1008 // Field : M0PLUS_MPU_CTRL_HFNMIENA 1009 // Description : Controls the use of the MPU for HardFaults and NMIs. Setting 1010 // this bit when ENABLE is clear results in UNPREDICTABLE 1011 // behaviour. 1012 // When the MPU is enabled: 1013 // 0 = MPU is disabled during HardFault and NMI handlers, 1014 // regardless of the value of the ENABLE bit. 1015 // 1 = the MPU is enabled during HardFault and NMI handlers. 1016 #define M0PLUS_MPU_CTRL_HFNMIENA_RESET _u(0x0) 1017 #define M0PLUS_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) 1018 #define M0PLUS_MPU_CTRL_HFNMIENA_MSB _u(1) 1019 #define M0PLUS_MPU_CTRL_HFNMIENA_LSB _u(1) 1020 #define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" 1021 // ----------------------------------------------------------------------------- 1022 // Field : M0PLUS_MPU_CTRL_ENABLE 1023 // Description : Enables the MPU. If the MPU is disabled, privileged and 1024 // unprivileged accesses use the default memory map. 1025 // 0 = MPU disabled. 1026 // 1 = MPU enabled. 1027 #define M0PLUS_MPU_CTRL_ENABLE_RESET _u(0x0) 1028 #define M0PLUS_MPU_CTRL_ENABLE_BITS _u(0x00000001) 1029 #define M0PLUS_MPU_CTRL_ENABLE_MSB _u(0) 1030 #define M0PLUS_MPU_CTRL_ENABLE_LSB _u(0) 1031 #define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" 1032 // ============================================================================= 1033 // Register : M0PLUS_MPU_RNR 1034 // Description : Use the MPU Region Number Register to select the region 1035 // currently accessed by MPU_RBAR and MPU_RASR. 1036 #define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98) 1037 #define M0PLUS_MPU_RNR_BITS _u(0x0000000f) 1038 #define M0PLUS_MPU_RNR_RESET _u(0x00000000) 1039 // ----------------------------------------------------------------------------- 1040 // Field : M0PLUS_MPU_RNR_REGION 1041 // Description : Indicates the MPU region referenced by the MPU_RBAR and 1042 // MPU_RASR registers. 1043 // The MPU supports 8 memory regions, so the permitted values of 1044 // this field are 0-7. 1045 #define M0PLUS_MPU_RNR_REGION_RESET _u(0x0) 1046 #define M0PLUS_MPU_RNR_REGION_BITS _u(0x0000000f) 1047 #define M0PLUS_MPU_RNR_REGION_MSB _u(3) 1048 #define M0PLUS_MPU_RNR_REGION_LSB _u(0) 1049 #define M0PLUS_MPU_RNR_REGION_ACCESS "RW" 1050 // ============================================================================= 1051 // Register : M0PLUS_MPU_RBAR 1052 // Description : Read the MPU Region Base Address Register to determine the base 1053 // address of the region identified by MPU_RNR. Write to update 1054 // the base address of said region or that of a specified region, 1055 // with whose number MPU_RNR will also be updated. 1056 #define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c) 1057 #define M0PLUS_MPU_RBAR_BITS _u(0xffffff1f) 1058 #define M0PLUS_MPU_RBAR_RESET _u(0x00000000) 1059 // ----------------------------------------------------------------------------- 1060 // Field : M0PLUS_MPU_RBAR_ADDR 1061 // Description : Base address of the region. 1062 #define M0PLUS_MPU_RBAR_ADDR_RESET _u(0x000000) 1063 #define M0PLUS_MPU_RBAR_ADDR_BITS _u(0xffffff00) 1064 #define M0PLUS_MPU_RBAR_ADDR_MSB _u(31) 1065 #define M0PLUS_MPU_RBAR_ADDR_LSB _u(8) 1066 #define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" 1067 // ----------------------------------------------------------------------------- 1068 // Field : M0PLUS_MPU_RBAR_VALID 1069 // Description : On writes, indicates whether the write must update the base 1070 // address of the region identified by the REGION field, updating 1071 // the MPU_RNR to indicate this new region. 1072 // Write: 1073 // 0 = MPU_RNR not changed, and the processor: 1074 // Updates the base address for the region specified in the 1075 // MPU_RNR. 1076 // Ignores the value of the REGION field. 1077 // 1 = The processor: 1078 // Updates the value of the MPU_RNR to the value of the REGION 1079 // field. 1080 // Updates the base address for the region specified in the REGION 1081 // field. 1082 // Always reads as zero. 1083 #define M0PLUS_MPU_RBAR_VALID_RESET _u(0x0) 1084 #define M0PLUS_MPU_RBAR_VALID_BITS _u(0x00000010) 1085 #define M0PLUS_MPU_RBAR_VALID_MSB _u(4) 1086 #define M0PLUS_MPU_RBAR_VALID_LSB _u(4) 1087 #define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" 1088 // ----------------------------------------------------------------------------- 1089 // Field : M0PLUS_MPU_RBAR_REGION 1090 // Description : On writes, specifies the number of the region whose base 1091 // address to update provided VALID is set written as 1. On reads, 1092 // returns bits [3:0] of MPU_RNR. 1093 #define M0PLUS_MPU_RBAR_REGION_RESET _u(0x0) 1094 #define M0PLUS_MPU_RBAR_REGION_BITS _u(0x0000000f) 1095 #define M0PLUS_MPU_RBAR_REGION_MSB _u(3) 1096 #define M0PLUS_MPU_RBAR_REGION_LSB _u(0) 1097 #define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" 1098 // ============================================================================= 1099 // Register : M0PLUS_MPU_RASR 1100 // Description : Use the MPU Region Attribute and Size Register to define the 1101 // size, access behaviour and memory type of the region identified 1102 // by MPU_RNR, and enable that region. 1103 #define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0) 1104 #define M0PLUS_MPU_RASR_BITS _u(0xffffff3f) 1105 #define M0PLUS_MPU_RASR_RESET _u(0x00000000) 1106 // ----------------------------------------------------------------------------- 1107 // Field : M0PLUS_MPU_RASR_ATTRS 1108 // Description : The MPU Region Attribute field. Use to define the region 1109 // attribute control. 1110 // 28 = XN: Instruction access disable bit: 1111 // 0 = Instruction fetches enabled. 1112 // 1 = Instruction fetches disabled. 1113 // 26:24 = AP: Access permission field 1114 // 18 = S: Shareable bit 1115 // 17 = C: Cacheable bit 1116 // 16 = B: Bufferable bit 1117 #define M0PLUS_MPU_RASR_ATTRS_RESET _u(0x0000) 1118 #define M0PLUS_MPU_RASR_ATTRS_BITS _u(0xffff0000) 1119 #define M0PLUS_MPU_RASR_ATTRS_MSB _u(31) 1120 #define M0PLUS_MPU_RASR_ATTRS_LSB _u(16) 1121 #define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" 1122 // ----------------------------------------------------------------------------- 1123 // Field : M0PLUS_MPU_RASR_SRD 1124 // Description : Subregion Disable. For regions of 256 bytes or larger, each bit 1125 // of this field controls whether one of the eight equal 1126 // subregions is enabled. 1127 #define M0PLUS_MPU_RASR_SRD_RESET _u(0x00) 1128 #define M0PLUS_MPU_RASR_SRD_BITS _u(0x0000ff00) 1129 #define M0PLUS_MPU_RASR_SRD_MSB _u(15) 1130 #define M0PLUS_MPU_RASR_SRD_LSB _u(8) 1131 #define M0PLUS_MPU_RASR_SRD_ACCESS "RW" 1132 // ----------------------------------------------------------------------------- 1133 // Field : M0PLUS_MPU_RASR_SIZE 1134 // Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). 1135 // The minimum permitted value is 7 (b00111) = 256Bytes 1136 #define M0PLUS_MPU_RASR_SIZE_RESET _u(0x00) 1137 #define M0PLUS_MPU_RASR_SIZE_BITS _u(0x0000003e) 1138 #define M0PLUS_MPU_RASR_SIZE_MSB _u(5) 1139 #define M0PLUS_MPU_RASR_SIZE_LSB _u(1) 1140 #define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" 1141 // ----------------------------------------------------------------------------- 1142 // Field : M0PLUS_MPU_RASR_ENABLE 1143 // Description : Enables the region. 1144 #define M0PLUS_MPU_RASR_ENABLE_RESET _u(0x0) 1145 #define M0PLUS_MPU_RASR_ENABLE_BITS _u(0x00000001) 1146 #define M0PLUS_MPU_RASR_ENABLE_MSB _u(0) 1147 #define M0PLUS_MPU_RASR_ENABLE_LSB _u(0) 1148 #define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" 1149 // ============================================================================= 1150 #endif // _HARDWARE_REGS_M0PLUS_H 1151 1152