1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : IO_QSPI 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_IO_QSPI_H 14 #define _HARDWARE_REGS_IO_QSPI_H 15 // ============================================================================= 16 // Register : IO_QSPI_USBPHY_DP_STATUS 17 #define IO_QSPI_USBPHY_DP_STATUS_OFFSET _u(0x00000000) 18 #define IO_QSPI_USBPHY_DP_STATUS_BITS _u(0x04022200) 19 #define IO_QSPI_USBPHY_DP_STATUS_RESET _u(0x00000000) 20 // ----------------------------------------------------------------------------- 21 // Field : IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC 22 // Description : interrupt to processors, after override is applied 23 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_RESET _u(0x0) 24 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_BITS _u(0x04000000) 25 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_MSB _u(26) 26 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_LSB _u(26) 27 #define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_ACCESS "RO" 28 // ----------------------------------------------------------------------------- 29 // Field : IO_QSPI_USBPHY_DP_STATUS_INFROMPAD 30 // Description : input signal from pad, before filtering and override are 31 // applied 32 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_RESET _u(0x0) 33 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_BITS _u(0x00020000) 34 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_MSB _u(17) 35 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_LSB _u(17) 36 #define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_ACCESS "RO" 37 // ----------------------------------------------------------------------------- 38 // Field : IO_QSPI_USBPHY_DP_STATUS_OETOPAD 39 // Description : output enable to pad after register override is applied 40 #define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_RESET _u(0x0) 41 #define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_BITS _u(0x00002000) 42 #define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_MSB _u(13) 43 #define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_LSB _u(13) 44 #define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_ACCESS "RO" 45 // ----------------------------------------------------------------------------- 46 // Field : IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD 47 // Description : output signal to pad after register override is applied 48 #define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_RESET _u(0x0) 49 #define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_BITS _u(0x00000200) 50 #define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_MSB _u(9) 51 #define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_LSB _u(9) 52 #define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_ACCESS "RO" 53 // ============================================================================= 54 // Register : IO_QSPI_USBPHY_DP_CTRL 55 #define IO_QSPI_USBPHY_DP_CTRL_OFFSET _u(0x00000004) 56 #define IO_QSPI_USBPHY_DP_CTRL_BITS _u(0x3003f01f) 57 #define IO_QSPI_USBPHY_DP_CTRL_RESET _u(0x0000001f) 58 // ----------------------------------------------------------------------------- 59 // Field : IO_QSPI_USBPHY_DP_CTRL_IRQOVER 60 // 0x0 -> don't invert the interrupt 61 // 0x1 -> invert the interrupt 62 // 0x2 -> drive interrupt low 63 // 0x3 -> drive interrupt high 64 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_RESET _u(0x0) 65 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_BITS _u(0x30000000) 66 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_MSB _u(29) 67 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_LSB _u(28) 68 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_ACCESS "RW" 69 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 70 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 71 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_LOW _u(0x2) 72 #define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 73 // ----------------------------------------------------------------------------- 74 // Field : IO_QSPI_USBPHY_DP_CTRL_INOVER 75 // 0x0 -> don't invert the peri input 76 // 0x1 -> invert the peri input 77 // 0x2 -> drive peri input low 78 // 0x3 -> drive peri input high 79 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_RESET _u(0x0) 80 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_BITS _u(0x00030000) 81 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_MSB _u(17) 82 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_LSB _u(16) 83 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_ACCESS "RW" 84 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_NORMAL _u(0x0) 85 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_INVERT _u(0x1) 86 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_LOW _u(0x2) 87 #define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_HIGH _u(0x3) 88 // ----------------------------------------------------------------------------- 89 // Field : IO_QSPI_USBPHY_DP_CTRL_OEOVER 90 // 0x0 -> drive output enable from peripheral signal selected by funcsel 91 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 92 // 0x2 -> disable output 93 // 0x3 -> enable output 94 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_RESET _u(0x0) 95 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_BITS _u(0x0000c000) 96 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_MSB _u(15) 97 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_LSB _u(14) 98 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_ACCESS "RW" 99 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 100 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_INVERT _u(0x1) 101 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 102 #define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 103 // ----------------------------------------------------------------------------- 104 // Field : IO_QSPI_USBPHY_DP_CTRL_OUTOVER 105 // 0x0 -> drive output from peripheral signal selected by funcsel 106 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 107 // 0x2 -> drive output low 108 // 0x3 -> drive output high 109 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_RESET _u(0x0) 110 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_BITS _u(0x00003000) 111 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_MSB _u(13) 112 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_LSB _u(12) 113 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_ACCESS "RW" 114 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 115 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 116 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_LOW _u(0x2) 117 #define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 118 // ----------------------------------------------------------------------------- 119 // Field : IO_QSPI_USBPHY_DP_CTRL_FUNCSEL 120 // Description : 0-31 -> selects pin function according to the gpio table 121 // 31 == NULL 122 // 0x02 -> uart1_tx 123 // 0x03 -> i2c0_sda 124 // 0x05 -> siob_proc_56 125 // 0x1f -> null 126 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_RESET _u(0x1f) 127 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_BITS _u(0x0000001f) 128 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_MSB _u(4) 129 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_LSB _u(0) 130 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_ACCESS "RW" 131 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) 132 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 133 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_SIOB_PROC_56 _u(0x05) 134 #define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 135 // ============================================================================= 136 // Register : IO_QSPI_USBPHY_DM_STATUS 137 #define IO_QSPI_USBPHY_DM_STATUS_OFFSET _u(0x00000008) 138 #define IO_QSPI_USBPHY_DM_STATUS_BITS _u(0x04022200) 139 #define IO_QSPI_USBPHY_DM_STATUS_RESET _u(0x00000000) 140 // ----------------------------------------------------------------------------- 141 // Field : IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC 142 // Description : interrupt to processors, after override is applied 143 #define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_RESET _u(0x0) 144 #define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_BITS _u(0x04000000) 145 #define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_MSB _u(26) 146 #define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_LSB _u(26) 147 #define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_ACCESS "RO" 148 // ----------------------------------------------------------------------------- 149 // Field : IO_QSPI_USBPHY_DM_STATUS_INFROMPAD 150 // Description : input signal from pad, before filtering and override are 151 // applied 152 #define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_RESET _u(0x0) 153 #define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_BITS _u(0x00020000) 154 #define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_MSB _u(17) 155 #define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_LSB _u(17) 156 #define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_ACCESS "RO" 157 // ----------------------------------------------------------------------------- 158 // Field : IO_QSPI_USBPHY_DM_STATUS_OETOPAD 159 // Description : output enable to pad after register override is applied 160 #define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_RESET _u(0x0) 161 #define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_BITS _u(0x00002000) 162 #define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_MSB _u(13) 163 #define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_LSB _u(13) 164 #define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_ACCESS "RO" 165 // ----------------------------------------------------------------------------- 166 // Field : IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD 167 // Description : output signal to pad after register override is applied 168 #define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_RESET _u(0x0) 169 #define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_BITS _u(0x00000200) 170 #define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_MSB _u(9) 171 #define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_LSB _u(9) 172 #define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_ACCESS "RO" 173 // ============================================================================= 174 // Register : IO_QSPI_USBPHY_DM_CTRL 175 #define IO_QSPI_USBPHY_DM_CTRL_OFFSET _u(0x0000000c) 176 #define IO_QSPI_USBPHY_DM_CTRL_BITS _u(0x3003f01f) 177 #define IO_QSPI_USBPHY_DM_CTRL_RESET _u(0x0000001f) 178 // ----------------------------------------------------------------------------- 179 // Field : IO_QSPI_USBPHY_DM_CTRL_IRQOVER 180 // 0x0 -> don't invert the interrupt 181 // 0x1 -> invert the interrupt 182 // 0x2 -> drive interrupt low 183 // 0x3 -> drive interrupt high 184 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_RESET _u(0x0) 185 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_BITS _u(0x30000000) 186 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_MSB _u(29) 187 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_LSB _u(28) 188 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_ACCESS "RW" 189 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 190 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 191 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_LOW _u(0x2) 192 #define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 193 // ----------------------------------------------------------------------------- 194 // Field : IO_QSPI_USBPHY_DM_CTRL_INOVER 195 // 0x0 -> don't invert the peri input 196 // 0x1 -> invert the peri input 197 // 0x2 -> drive peri input low 198 // 0x3 -> drive peri input high 199 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_RESET _u(0x0) 200 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_BITS _u(0x00030000) 201 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_MSB _u(17) 202 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_LSB _u(16) 203 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_ACCESS "RW" 204 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_NORMAL _u(0x0) 205 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_INVERT _u(0x1) 206 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_LOW _u(0x2) 207 #define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_HIGH _u(0x3) 208 // ----------------------------------------------------------------------------- 209 // Field : IO_QSPI_USBPHY_DM_CTRL_OEOVER 210 // 0x0 -> drive output enable from peripheral signal selected by funcsel 211 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 212 // 0x2 -> disable output 213 // 0x3 -> enable output 214 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_RESET _u(0x0) 215 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_BITS _u(0x0000c000) 216 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_MSB _u(15) 217 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_LSB _u(14) 218 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_ACCESS "RW" 219 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 220 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_INVERT _u(0x1) 221 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 222 #define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 223 // ----------------------------------------------------------------------------- 224 // Field : IO_QSPI_USBPHY_DM_CTRL_OUTOVER 225 // 0x0 -> drive output from peripheral signal selected by funcsel 226 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 227 // 0x2 -> drive output low 228 // 0x3 -> drive output high 229 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_RESET _u(0x0) 230 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_BITS _u(0x00003000) 231 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_MSB _u(13) 232 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_LSB _u(12) 233 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_ACCESS "RW" 234 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 235 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 236 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_LOW _u(0x2) 237 #define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 238 // ----------------------------------------------------------------------------- 239 // Field : IO_QSPI_USBPHY_DM_CTRL_FUNCSEL 240 // Description : 0-31 -> selects pin function according to the gpio table 241 // 31 == NULL 242 // 0x02 -> uart1_rx 243 // 0x03 -> i2c0_scl 244 // 0x05 -> siob_proc_57 245 // 0x1f -> null 246 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_RESET _u(0x1f) 247 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_BITS _u(0x0000001f) 248 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_MSB _u(4) 249 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_LSB _u(0) 250 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_ACCESS "RW" 251 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) 252 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 253 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_SIOB_PROC_57 _u(0x05) 254 #define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 255 // ============================================================================= 256 // Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS 257 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000010) 258 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x04022200) 259 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) 260 // ----------------------------------------------------------------------------- 261 // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC 262 // Description : interrupt to processors, after override is applied 263 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) 264 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) 265 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) 266 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) 267 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" 268 // ----------------------------------------------------------------------------- 269 // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD 270 // Description : input signal from pad, before filtering and override are 271 // applied 272 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) 273 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) 274 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) 275 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) 276 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" 277 // ----------------------------------------------------------------------------- 278 // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD 279 // Description : output enable to pad after register override is applied 280 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) 281 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) 282 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) 283 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) 284 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" 285 // ----------------------------------------------------------------------------- 286 // Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD 287 // Description : output signal to pad after register override is applied 288 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) 289 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) 290 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) 291 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) 292 #define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" 293 // ============================================================================= 294 // Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL 295 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000014) 296 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003f01f) 297 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) 298 // ----------------------------------------------------------------------------- 299 // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER 300 // 0x0 -> don't invert the interrupt 301 // 0x1 -> invert the interrupt 302 // 0x2 -> drive interrupt low 303 // 0x3 -> drive interrupt high 304 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) 305 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) 306 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) 307 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) 308 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" 309 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 310 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 311 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) 312 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 313 // ----------------------------------------------------------------------------- 314 // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER 315 // 0x0 -> don't invert the peri input 316 // 0x1 -> invert the peri input 317 // 0x2 -> drive peri input low 318 // 0x3 -> drive peri input high 319 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) 320 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) 321 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) 322 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) 323 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" 324 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) 325 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) 326 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) 327 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) 328 // ----------------------------------------------------------------------------- 329 // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER 330 // 0x0 -> drive output enable from peripheral signal selected by funcsel 331 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 332 // 0x2 -> disable output 333 // 0x3 -> enable output 334 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) 335 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x0000c000) 336 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(15) 337 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(14) 338 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" 339 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 340 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) 341 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 342 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 343 // ----------------------------------------------------------------------------- 344 // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER 345 // 0x0 -> drive output from peripheral signal selected by funcsel 346 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 347 // 0x2 -> drive output low 348 // 0x3 -> drive output high 349 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) 350 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00003000) 351 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(13) 352 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(12) 353 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" 354 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 355 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 356 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) 357 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 358 // ----------------------------------------------------------------------------- 359 // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL 360 // Description : 0-31 -> selects pin function according to the gpio table 361 // 31 == NULL 362 // 0x00 -> xip_sclk 363 // 0x02 -> uart1_cts 364 // 0x03 -> i2c1_sda 365 // 0x05 -> siob_proc_58 366 // 0x0b -> uart1_tx 367 // 0x1f -> null 368 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) 369 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) 370 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) 371 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) 372 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" 373 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) 374 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) 375 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 376 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIOB_PROC_58 _u(0x05) 377 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) 378 #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 379 // ============================================================================= 380 // Register : IO_QSPI_GPIO_QSPI_SS_STATUS 381 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000018) 382 #define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x04022200) 383 #define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) 384 // ----------------------------------------------------------------------------- 385 // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC 386 // Description : interrupt to processors, after override is applied 387 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) 388 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) 389 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) 390 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) 391 #define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" 392 // ----------------------------------------------------------------------------- 393 // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD 394 // Description : input signal from pad, before filtering and override are 395 // applied 396 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) 397 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) 398 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) 399 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) 400 #define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" 401 // ----------------------------------------------------------------------------- 402 // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD 403 // Description : output enable to pad after register override is applied 404 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) 405 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) 406 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) 407 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) 408 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" 409 // ----------------------------------------------------------------------------- 410 // Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD 411 // Description : output signal to pad after register override is applied 412 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) 413 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) 414 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) 415 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) 416 #define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" 417 // ============================================================================= 418 // Register : IO_QSPI_GPIO_QSPI_SS_CTRL 419 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000001c) 420 #define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003f01f) 421 #define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) 422 // ----------------------------------------------------------------------------- 423 // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER 424 // 0x0 -> don't invert the interrupt 425 // 0x1 -> invert the interrupt 426 // 0x2 -> drive interrupt low 427 // 0x3 -> drive interrupt high 428 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) 429 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) 430 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) 431 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) 432 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" 433 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 434 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 435 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) 436 #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 437 // ----------------------------------------------------------------------------- 438 // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER 439 // 0x0 -> don't invert the peri input 440 // 0x1 -> invert the peri input 441 // 0x2 -> drive peri input low 442 // 0x3 -> drive peri input high 443 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) 444 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) 445 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) 446 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) 447 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" 448 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) 449 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) 450 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) 451 #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) 452 // ----------------------------------------------------------------------------- 453 // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER 454 // 0x0 -> drive output enable from peripheral signal selected by funcsel 455 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 456 // 0x2 -> disable output 457 // 0x3 -> enable output 458 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) 459 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x0000c000) 460 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(15) 461 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(14) 462 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" 463 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 464 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) 465 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 466 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 467 // ----------------------------------------------------------------------------- 468 // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER 469 // 0x0 -> drive output from peripheral signal selected by funcsel 470 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 471 // 0x2 -> drive output low 472 // 0x3 -> drive output high 473 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) 474 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00003000) 475 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(13) 476 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(12) 477 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" 478 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 479 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 480 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) 481 #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 482 // ----------------------------------------------------------------------------- 483 // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL 484 // Description : 0-31 -> selects pin function according to the gpio table 485 // 31 == NULL 486 // 0x00 -> xip_ss_n_0 487 // 0x02 -> uart1_rts 488 // 0x03 -> i2c1_scl 489 // 0x05 -> siob_proc_59 490 // 0x0b -> uart1_rx 491 // 0x1f -> null 492 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) 493 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) 494 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) 495 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) 496 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" 497 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N_0 _u(0x00) 498 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) 499 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 500 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIOB_PROC_59 _u(0x05) 501 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) 502 #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 503 // ============================================================================= 504 // Register : IO_QSPI_GPIO_QSPI_SD0_STATUS 505 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000020) 506 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x04022200) 507 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) 508 // ----------------------------------------------------------------------------- 509 // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC 510 // Description : interrupt to processors, after override is applied 511 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) 512 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) 513 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) 514 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) 515 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" 516 // ----------------------------------------------------------------------------- 517 // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD 518 // Description : input signal from pad, before filtering and override are 519 // applied 520 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) 521 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) 522 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) 523 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) 524 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" 525 // ----------------------------------------------------------------------------- 526 // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD 527 // Description : output enable to pad after register override is applied 528 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) 529 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) 530 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) 531 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) 532 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" 533 // ----------------------------------------------------------------------------- 534 // Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD 535 // Description : output signal to pad after register override is applied 536 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) 537 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) 538 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) 539 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) 540 #define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" 541 // ============================================================================= 542 // Register : IO_QSPI_GPIO_QSPI_SD0_CTRL 543 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000024) 544 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003f01f) 545 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) 546 // ----------------------------------------------------------------------------- 547 // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER 548 // 0x0 -> don't invert the interrupt 549 // 0x1 -> invert the interrupt 550 // 0x2 -> drive interrupt low 551 // 0x3 -> drive interrupt high 552 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) 553 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) 554 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) 555 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) 556 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" 557 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 558 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 559 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) 560 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 561 // ----------------------------------------------------------------------------- 562 // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER 563 // 0x0 -> don't invert the peri input 564 // 0x1 -> invert the peri input 565 // 0x2 -> drive peri input low 566 // 0x3 -> drive peri input high 567 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) 568 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) 569 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) 570 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) 571 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" 572 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) 573 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) 574 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) 575 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) 576 // ----------------------------------------------------------------------------- 577 // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER 578 // 0x0 -> drive output enable from peripheral signal selected by funcsel 579 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 580 // 0x2 -> disable output 581 // 0x3 -> enable output 582 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) 583 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x0000c000) 584 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(15) 585 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(14) 586 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" 587 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 588 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) 589 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 590 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 591 // ----------------------------------------------------------------------------- 592 // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER 593 // 0x0 -> drive output from peripheral signal selected by funcsel 594 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 595 // 0x2 -> drive output low 596 // 0x3 -> drive output high 597 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) 598 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00003000) 599 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(13) 600 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(12) 601 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" 602 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 603 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 604 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) 605 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 606 // ----------------------------------------------------------------------------- 607 // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL 608 // Description : 0-31 -> selects pin function according to the gpio table 609 // 31 == NULL 610 // 0x00 -> xip_sd0 611 // 0x02 -> uart0_tx 612 // 0x03 -> i2c0_sda 613 // 0x05 -> siob_proc_60 614 // 0x1f -> null 615 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) 616 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) 617 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) 618 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) 619 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" 620 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) 621 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) 622 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) 623 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIOB_PROC_60 _u(0x05) 624 #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 625 // ============================================================================= 626 // Register : IO_QSPI_GPIO_QSPI_SD1_STATUS 627 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000028) 628 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x04022200) 629 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) 630 // ----------------------------------------------------------------------------- 631 // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC 632 // Description : interrupt to processors, after override is applied 633 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) 634 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) 635 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) 636 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) 637 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" 638 // ----------------------------------------------------------------------------- 639 // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD 640 // Description : input signal from pad, before filtering and override are 641 // applied 642 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) 643 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) 644 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) 645 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) 646 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" 647 // ----------------------------------------------------------------------------- 648 // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD 649 // Description : output enable to pad after register override is applied 650 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) 651 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) 652 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) 653 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) 654 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" 655 // ----------------------------------------------------------------------------- 656 // Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD 657 // Description : output signal to pad after register override is applied 658 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) 659 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) 660 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) 661 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) 662 #define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" 663 // ============================================================================= 664 // Register : IO_QSPI_GPIO_QSPI_SD1_CTRL 665 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000002c) 666 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003f01f) 667 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) 668 // ----------------------------------------------------------------------------- 669 // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER 670 // 0x0 -> don't invert the interrupt 671 // 0x1 -> invert the interrupt 672 // 0x2 -> drive interrupt low 673 // 0x3 -> drive interrupt high 674 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) 675 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) 676 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) 677 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) 678 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" 679 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 680 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 681 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) 682 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 683 // ----------------------------------------------------------------------------- 684 // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER 685 // 0x0 -> don't invert the peri input 686 // 0x1 -> invert the peri input 687 // 0x2 -> drive peri input low 688 // 0x3 -> drive peri input high 689 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) 690 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) 691 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) 692 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) 693 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" 694 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) 695 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) 696 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) 697 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) 698 // ----------------------------------------------------------------------------- 699 // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER 700 // 0x0 -> drive output enable from peripheral signal selected by funcsel 701 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 702 // 0x2 -> disable output 703 // 0x3 -> enable output 704 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) 705 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x0000c000) 706 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(15) 707 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(14) 708 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" 709 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 710 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) 711 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 712 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 713 // ----------------------------------------------------------------------------- 714 // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER 715 // 0x0 -> drive output from peripheral signal selected by funcsel 716 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 717 // 0x2 -> drive output low 718 // 0x3 -> drive output high 719 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) 720 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00003000) 721 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(13) 722 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(12) 723 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" 724 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 725 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 726 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) 727 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 728 // ----------------------------------------------------------------------------- 729 // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL 730 // Description : 0-31 -> selects pin function according to the gpio table 731 // 31 == NULL 732 // 0x00 -> xip_sd1 733 // 0x02 -> uart0_rx 734 // 0x03 -> i2c0_scl 735 // 0x05 -> siob_proc_61 736 // 0x1f -> null 737 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) 738 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) 739 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) 740 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) 741 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" 742 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) 743 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) 744 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) 745 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIOB_PROC_61 _u(0x05) 746 #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 747 // ============================================================================= 748 // Register : IO_QSPI_GPIO_QSPI_SD2_STATUS 749 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000030) 750 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x04022200) 751 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) 752 // ----------------------------------------------------------------------------- 753 // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC 754 // Description : interrupt to processors, after override is applied 755 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) 756 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) 757 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) 758 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) 759 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" 760 // ----------------------------------------------------------------------------- 761 // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD 762 // Description : input signal from pad, before filtering and override are 763 // applied 764 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) 765 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) 766 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) 767 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) 768 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" 769 // ----------------------------------------------------------------------------- 770 // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD 771 // Description : output enable to pad after register override is applied 772 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) 773 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) 774 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) 775 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) 776 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" 777 // ----------------------------------------------------------------------------- 778 // Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD 779 // Description : output signal to pad after register override is applied 780 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) 781 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) 782 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) 783 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) 784 #define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" 785 // ============================================================================= 786 // Register : IO_QSPI_GPIO_QSPI_SD2_CTRL 787 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000034) 788 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003f01f) 789 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) 790 // ----------------------------------------------------------------------------- 791 // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER 792 // 0x0 -> don't invert the interrupt 793 // 0x1 -> invert the interrupt 794 // 0x2 -> drive interrupt low 795 // 0x3 -> drive interrupt high 796 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) 797 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) 798 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) 799 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) 800 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" 801 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 802 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 803 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) 804 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 805 // ----------------------------------------------------------------------------- 806 // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER 807 // 0x0 -> don't invert the peri input 808 // 0x1 -> invert the peri input 809 // 0x2 -> drive peri input low 810 // 0x3 -> drive peri input high 811 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) 812 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) 813 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) 814 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) 815 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" 816 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) 817 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) 818 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) 819 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) 820 // ----------------------------------------------------------------------------- 821 // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER 822 // 0x0 -> drive output enable from peripheral signal selected by funcsel 823 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 824 // 0x2 -> disable output 825 // 0x3 -> enable output 826 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) 827 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x0000c000) 828 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(15) 829 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(14) 830 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" 831 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 832 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) 833 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 834 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 835 // ----------------------------------------------------------------------------- 836 // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER 837 // 0x0 -> drive output from peripheral signal selected by funcsel 838 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 839 // 0x2 -> drive output low 840 // 0x3 -> drive output high 841 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) 842 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00003000) 843 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(13) 844 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(12) 845 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" 846 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 847 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 848 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) 849 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 850 // ----------------------------------------------------------------------------- 851 // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL 852 // Description : 0-31 -> selects pin function according to the gpio table 853 // 31 == NULL 854 // 0x00 -> xip_sd2 855 // 0x02 -> uart0_cts 856 // 0x03 -> i2c1_sda 857 // 0x05 -> siob_proc_62 858 // 0x0b -> uart0_tx 859 // 0x1f -> null 860 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) 861 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) 862 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) 863 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) 864 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" 865 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) 866 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) 867 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) 868 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIOB_PROC_62 _u(0x05) 869 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) 870 #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 871 // ============================================================================= 872 // Register : IO_QSPI_GPIO_QSPI_SD3_STATUS 873 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000038) 874 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x04022200) 875 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) 876 // ----------------------------------------------------------------------------- 877 // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC 878 // Description : interrupt to processors, after override is applied 879 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) 880 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) 881 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) 882 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) 883 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" 884 // ----------------------------------------------------------------------------- 885 // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD 886 // Description : input signal from pad, before filtering and override are 887 // applied 888 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) 889 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) 890 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) 891 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) 892 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" 893 // ----------------------------------------------------------------------------- 894 // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD 895 // Description : output enable to pad after register override is applied 896 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) 897 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) 898 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) 899 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) 900 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" 901 // ----------------------------------------------------------------------------- 902 // Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD 903 // Description : output signal to pad after register override is applied 904 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) 905 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) 906 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) 907 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) 908 #define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" 909 // ============================================================================= 910 // Register : IO_QSPI_GPIO_QSPI_SD3_CTRL 911 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000003c) 912 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003f01f) 913 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) 914 // ----------------------------------------------------------------------------- 915 // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER 916 // 0x0 -> don't invert the interrupt 917 // 0x1 -> invert the interrupt 918 // 0x2 -> drive interrupt low 919 // 0x3 -> drive interrupt high 920 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) 921 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) 922 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) 923 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) 924 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" 925 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) 926 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) 927 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) 928 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) 929 // ----------------------------------------------------------------------------- 930 // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER 931 // 0x0 -> don't invert the peri input 932 // 0x1 -> invert the peri input 933 // 0x2 -> drive peri input low 934 // 0x3 -> drive peri input high 935 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) 936 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) 937 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) 938 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) 939 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" 940 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) 941 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) 942 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) 943 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) 944 // ----------------------------------------------------------------------------- 945 // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER 946 // 0x0 -> drive output enable from peripheral signal selected by funcsel 947 // 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel 948 // 0x2 -> disable output 949 // 0x3 -> enable output 950 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) 951 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x0000c000) 952 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(15) 953 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(14) 954 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" 955 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) 956 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) 957 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) 958 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) 959 // ----------------------------------------------------------------------------- 960 // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER 961 // 0x0 -> drive output from peripheral signal selected by funcsel 962 // 0x1 -> drive output from inverse of peripheral signal selected by funcsel 963 // 0x2 -> drive output low 964 // 0x3 -> drive output high 965 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) 966 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00003000) 967 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(13) 968 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(12) 969 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" 970 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) 971 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) 972 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) 973 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) 974 // ----------------------------------------------------------------------------- 975 // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL 976 // Description : 0-31 -> selects pin function according to the gpio table 977 // 31 == NULL 978 // 0x00 -> xip_sd3 979 // 0x02 -> uart0_rts 980 // 0x03 -> i2c1_scl 981 // 0x05 -> siob_proc_63 982 // 0x0b -> uart0_rx 983 // 0x1f -> null 984 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) 985 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) 986 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) 987 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) 988 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" 989 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) 990 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) 991 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) 992 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIOB_PROC_63 _u(0x05) 993 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) 994 #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) 995 // ============================================================================= 996 // Register : IO_QSPI_IRQSUMMARY_PROC0_SECURE 997 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET _u(0x00000200) 998 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_BITS _u(0x000000ff) 999 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_RESET _u(0x00000000) 1000 // ----------------------------------------------------------------------------- 1001 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3 1002 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) 1003 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) 1004 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_MSB _u(7) 1005 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_LSB _u(7) 1006 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_ACCESS "RO" 1007 // ----------------------------------------------------------------------------- 1008 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2 1009 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) 1010 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) 1011 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_MSB _u(6) 1012 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_LSB _u(6) 1013 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_ACCESS "RO" 1014 // ----------------------------------------------------------------------------- 1015 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1 1016 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) 1017 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) 1018 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_MSB _u(5) 1019 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_LSB _u(5) 1020 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_ACCESS "RO" 1021 // ----------------------------------------------------------------------------- 1022 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0 1023 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) 1024 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) 1025 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_MSB _u(4) 1026 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_LSB _u(4) 1027 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_ACCESS "RO" 1028 // ----------------------------------------------------------------------------- 1029 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS 1030 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_RESET _u(0x0) 1031 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) 1032 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_MSB _u(3) 1033 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_LSB _u(3) 1034 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_ACCESS "RO" 1035 // ----------------------------------------------------------------------------- 1036 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK 1037 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) 1038 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) 1039 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_MSB _u(2) 1040 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_LSB _u(2) 1041 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" 1042 // ----------------------------------------------------------------------------- 1043 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM 1044 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_RESET _u(0x0) 1045 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_BITS _u(0x00000002) 1046 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_MSB _u(1) 1047 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_LSB _u(1) 1048 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_ACCESS "RO" 1049 // ----------------------------------------------------------------------------- 1050 // Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP 1051 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_RESET _u(0x0) 1052 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_BITS _u(0x00000001) 1053 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_MSB _u(0) 1054 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_LSB _u(0) 1055 #define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_ACCESS "RO" 1056 // ============================================================================= 1057 // Register : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE 1058 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET _u(0x00000204) 1059 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_BITS _u(0x000000ff) 1060 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_RESET _u(0x00000000) 1061 // ----------------------------------------------------------------------------- 1062 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3 1063 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) 1064 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) 1065 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) 1066 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) 1067 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" 1068 // ----------------------------------------------------------------------------- 1069 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2 1070 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) 1071 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) 1072 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) 1073 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) 1074 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" 1075 // ----------------------------------------------------------------------------- 1076 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1 1077 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) 1078 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) 1079 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) 1080 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) 1081 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" 1082 // ----------------------------------------------------------------------------- 1083 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0 1084 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) 1085 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) 1086 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) 1087 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) 1088 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" 1089 // ----------------------------------------------------------------------------- 1090 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS 1091 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) 1092 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) 1093 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_MSB _u(3) 1094 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_LSB _u(3) 1095 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" 1096 // ----------------------------------------------------------------------------- 1097 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK 1098 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) 1099 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) 1100 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) 1101 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) 1102 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" 1103 // ----------------------------------------------------------------------------- 1104 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM 1105 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_RESET _u(0x0) 1106 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_BITS _u(0x00000002) 1107 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_MSB _u(1) 1108 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_LSB _u(1) 1109 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_ACCESS "RO" 1110 // ----------------------------------------------------------------------------- 1111 // Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP 1112 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_RESET _u(0x0) 1113 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_BITS _u(0x00000001) 1114 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_MSB _u(0) 1115 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_LSB _u(0) 1116 #define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_ACCESS "RO" 1117 // ============================================================================= 1118 // Register : IO_QSPI_IRQSUMMARY_PROC1_SECURE 1119 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET _u(0x00000208) 1120 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_BITS _u(0x000000ff) 1121 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_RESET _u(0x00000000) 1122 // ----------------------------------------------------------------------------- 1123 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3 1124 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) 1125 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) 1126 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_MSB _u(7) 1127 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_LSB _u(7) 1128 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_ACCESS "RO" 1129 // ----------------------------------------------------------------------------- 1130 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2 1131 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) 1132 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) 1133 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_MSB _u(6) 1134 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_LSB _u(6) 1135 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_ACCESS "RO" 1136 // ----------------------------------------------------------------------------- 1137 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1 1138 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) 1139 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) 1140 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_MSB _u(5) 1141 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_LSB _u(5) 1142 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_ACCESS "RO" 1143 // ----------------------------------------------------------------------------- 1144 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0 1145 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) 1146 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) 1147 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_MSB _u(4) 1148 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_LSB _u(4) 1149 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_ACCESS "RO" 1150 // ----------------------------------------------------------------------------- 1151 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS 1152 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_RESET _u(0x0) 1153 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) 1154 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_MSB _u(3) 1155 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_LSB _u(3) 1156 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_ACCESS "RO" 1157 // ----------------------------------------------------------------------------- 1158 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK 1159 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) 1160 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) 1161 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_MSB _u(2) 1162 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_LSB _u(2) 1163 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" 1164 // ----------------------------------------------------------------------------- 1165 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM 1166 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_RESET _u(0x0) 1167 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_BITS _u(0x00000002) 1168 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_MSB _u(1) 1169 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_LSB _u(1) 1170 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_ACCESS "RO" 1171 // ----------------------------------------------------------------------------- 1172 // Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP 1173 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_RESET _u(0x0) 1174 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_BITS _u(0x00000001) 1175 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_MSB _u(0) 1176 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_LSB _u(0) 1177 #define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_ACCESS "RO" 1178 // ============================================================================= 1179 // Register : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE 1180 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET _u(0x0000020c) 1181 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_BITS _u(0x000000ff) 1182 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_RESET _u(0x00000000) 1183 // ----------------------------------------------------------------------------- 1184 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3 1185 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) 1186 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) 1187 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) 1188 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) 1189 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" 1190 // ----------------------------------------------------------------------------- 1191 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2 1192 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) 1193 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) 1194 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) 1195 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) 1196 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" 1197 // ----------------------------------------------------------------------------- 1198 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1 1199 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) 1200 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) 1201 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) 1202 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) 1203 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" 1204 // ----------------------------------------------------------------------------- 1205 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0 1206 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) 1207 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) 1208 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) 1209 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) 1210 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" 1211 // ----------------------------------------------------------------------------- 1212 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS 1213 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) 1214 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) 1215 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_MSB _u(3) 1216 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_LSB _u(3) 1217 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" 1218 // ----------------------------------------------------------------------------- 1219 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK 1220 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) 1221 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) 1222 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) 1223 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) 1224 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" 1225 // ----------------------------------------------------------------------------- 1226 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM 1227 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_RESET _u(0x0) 1228 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_BITS _u(0x00000002) 1229 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_MSB _u(1) 1230 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_LSB _u(1) 1231 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_ACCESS "RO" 1232 // ----------------------------------------------------------------------------- 1233 // Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP 1234 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_RESET _u(0x0) 1235 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_BITS _u(0x00000001) 1236 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_MSB _u(0) 1237 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_LSB _u(0) 1238 #define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_ACCESS "RO" 1239 // ============================================================================= 1240 // Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE 1241 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET _u(0x00000210) 1242 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_BITS _u(0x000000ff) 1243 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_RESET _u(0x00000000) 1244 // ----------------------------------------------------------------------------- 1245 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3 1246 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) 1247 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) 1248 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_MSB _u(7) 1249 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_LSB _u(7) 1250 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_ACCESS "RO" 1251 // ----------------------------------------------------------------------------- 1252 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2 1253 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) 1254 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) 1255 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_MSB _u(6) 1256 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_LSB _u(6) 1257 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_ACCESS "RO" 1258 // ----------------------------------------------------------------------------- 1259 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1 1260 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) 1261 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) 1262 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_MSB _u(5) 1263 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_LSB _u(5) 1264 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_ACCESS "RO" 1265 // ----------------------------------------------------------------------------- 1266 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0 1267 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) 1268 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) 1269 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_MSB _u(4) 1270 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_LSB _u(4) 1271 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_ACCESS "RO" 1272 // ----------------------------------------------------------------------------- 1273 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS 1274 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_RESET _u(0x0) 1275 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) 1276 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_MSB _u(3) 1277 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_LSB _u(3) 1278 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_ACCESS "RO" 1279 // ----------------------------------------------------------------------------- 1280 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK 1281 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) 1282 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) 1283 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_MSB _u(2) 1284 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_LSB _u(2) 1285 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" 1286 // ----------------------------------------------------------------------------- 1287 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM 1288 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_RESET _u(0x0) 1289 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_BITS _u(0x00000002) 1290 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_MSB _u(1) 1291 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_LSB _u(1) 1292 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_ACCESS "RO" 1293 // ----------------------------------------------------------------------------- 1294 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP 1295 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_RESET _u(0x0) 1296 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_BITS _u(0x00000001) 1297 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_MSB _u(0) 1298 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_LSB _u(0) 1299 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_ACCESS "RO" 1300 // ============================================================================= 1301 // Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE 1302 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET _u(0x00000214) 1303 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_BITS _u(0x000000ff) 1304 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_RESET _u(0x00000000) 1305 // ----------------------------------------------------------------------------- 1306 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3 1307 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) 1308 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) 1309 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) 1310 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) 1311 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" 1312 // ----------------------------------------------------------------------------- 1313 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2 1314 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) 1315 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) 1316 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) 1317 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) 1318 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" 1319 // ----------------------------------------------------------------------------- 1320 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1 1321 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) 1322 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) 1323 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) 1324 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) 1325 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" 1326 // ----------------------------------------------------------------------------- 1327 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0 1328 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) 1329 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) 1330 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) 1331 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) 1332 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" 1333 // ----------------------------------------------------------------------------- 1334 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS 1335 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) 1336 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) 1337 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_MSB _u(3) 1338 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_LSB _u(3) 1339 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" 1340 // ----------------------------------------------------------------------------- 1341 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK 1342 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) 1343 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) 1344 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) 1345 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) 1346 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" 1347 // ----------------------------------------------------------------------------- 1348 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM 1349 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_RESET _u(0x0) 1350 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_BITS _u(0x00000002) 1351 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_MSB _u(1) 1352 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_LSB _u(1) 1353 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_ACCESS "RO" 1354 // ----------------------------------------------------------------------------- 1355 // Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP 1356 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_RESET _u(0x0) 1357 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_BITS _u(0x00000001) 1358 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_MSB _u(0) 1359 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_LSB _u(0) 1360 #define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_ACCESS "RO" 1361 // ============================================================================= 1362 // Register : IO_QSPI_INTR 1363 // Description : Raw Interrupts 1364 #define IO_QSPI_INTR_OFFSET _u(0x00000218) 1365 #define IO_QSPI_INTR_BITS _u(0xffffffff) 1366 #define IO_QSPI_INTR_RESET _u(0x00000000) 1367 // ----------------------------------------------------------------------------- 1368 // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH 1369 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 1370 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 1371 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 1372 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 1373 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" 1374 // ----------------------------------------------------------------------------- 1375 // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW 1376 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 1377 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 1378 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 1379 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 1380 #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" 1381 // ----------------------------------------------------------------------------- 1382 // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH 1383 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 1384 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 1385 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 1386 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 1387 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" 1388 // ----------------------------------------------------------------------------- 1389 // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW 1390 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 1391 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 1392 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 1393 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 1394 #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" 1395 // ----------------------------------------------------------------------------- 1396 // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH 1397 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 1398 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 1399 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 1400 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 1401 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" 1402 // ----------------------------------------------------------------------------- 1403 // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW 1404 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 1405 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 1406 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 1407 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 1408 #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" 1409 // ----------------------------------------------------------------------------- 1410 // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH 1411 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 1412 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 1413 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 1414 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 1415 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" 1416 // ----------------------------------------------------------------------------- 1417 // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW 1418 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 1419 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 1420 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 1421 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 1422 #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" 1423 // ----------------------------------------------------------------------------- 1424 // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH 1425 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 1426 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 1427 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 1428 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 1429 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" 1430 // ----------------------------------------------------------------------------- 1431 // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW 1432 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 1433 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 1434 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 1435 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 1436 #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" 1437 // ----------------------------------------------------------------------------- 1438 // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH 1439 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 1440 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 1441 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 1442 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 1443 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" 1444 // ----------------------------------------------------------------------------- 1445 // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW 1446 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 1447 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 1448 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 1449 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 1450 #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" 1451 // ----------------------------------------------------------------------------- 1452 // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH 1453 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 1454 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 1455 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 1456 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 1457 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" 1458 // ----------------------------------------------------------------------------- 1459 // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW 1460 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 1461 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 1462 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 1463 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 1464 #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" 1465 // ----------------------------------------------------------------------------- 1466 // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH 1467 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 1468 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 1469 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 1470 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 1471 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" 1472 // ----------------------------------------------------------------------------- 1473 // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW 1474 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 1475 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 1476 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 1477 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 1478 #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" 1479 // ----------------------------------------------------------------------------- 1480 // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH 1481 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 1482 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 1483 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 1484 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 1485 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" 1486 // ----------------------------------------------------------------------------- 1487 // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW 1488 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 1489 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 1490 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 1491 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 1492 #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" 1493 // ----------------------------------------------------------------------------- 1494 // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH 1495 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 1496 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 1497 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 1498 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 1499 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" 1500 // ----------------------------------------------------------------------------- 1501 // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW 1502 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 1503 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 1504 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 1505 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 1506 #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" 1507 // ----------------------------------------------------------------------------- 1508 // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH 1509 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 1510 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 1511 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 1512 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 1513 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" 1514 // ----------------------------------------------------------------------------- 1515 // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW 1516 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 1517 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 1518 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 1519 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 1520 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" 1521 // ----------------------------------------------------------------------------- 1522 // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH 1523 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 1524 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 1525 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 1526 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 1527 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" 1528 // ----------------------------------------------------------------------------- 1529 // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW 1530 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 1531 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 1532 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 1533 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 1534 #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" 1535 // ----------------------------------------------------------------------------- 1536 // Field : IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH 1537 #define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 1538 #define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 1539 #define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_MSB _u(7) 1540 #define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_LSB _u(7) 1541 #define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_ACCESS "WC" 1542 // ----------------------------------------------------------------------------- 1543 // Field : IO_QSPI_INTR_USBPHY_DM_EDGE_LOW 1544 #define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 1545 #define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 1546 #define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_MSB _u(6) 1547 #define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_LSB _u(6) 1548 #define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_ACCESS "WC" 1549 // ----------------------------------------------------------------------------- 1550 // Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH 1551 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 1552 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 1553 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 1554 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 1555 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" 1556 // ----------------------------------------------------------------------------- 1557 // Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW 1558 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 1559 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 1560 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_MSB _u(4) 1561 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_LSB _u(4) 1562 #define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_ACCESS "RO" 1563 // ----------------------------------------------------------------------------- 1564 // Field : IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH 1565 #define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 1566 #define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 1567 #define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_MSB _u(3) 1568 #define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_LSB _u(3) 1569 #define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_ACCESS "WC" 1570 // ----------------------------------------------------------------------------- 1571 // Field : IO_QSPI_INTR_USBPHY_DP_EDGE_LOW 1572 #define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 1573 #define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 1574 #define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_MSB _u(2) 1575 #define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_LSB _u(2) 1576 #define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_ACCESS "WC" 1577 // ----------------------------------------------------------------------------- 1578 // Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH 1579 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 1580 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 1581 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 1582 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 1583 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" 1584 // ----------------------------------------------------------------------------- 1585 // Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW 1586 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 1587 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 1588 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_MSB _u(0) 1589 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_LSB _u(0) 1590 #define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_ACCESS "RO" 1591 // ============================================================================= 1592 // Register : IO_QSPI_PROC0_INTE 1593 // Description : Interrupt Enable for proc0 1594 #define IO_QSPI_PROC0_INTE_OFFSET _u(0x0000021c) 1595 #define IO_QSPI_PROC0_INTE_BITS _u(0xffffffff) 1596 #define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) 1597 // ----------------------------------------------------------------------------- 1598 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH 1599 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 1600 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 1601 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 1602 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 1603 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" 1604 // ----------------------------------------------------------------------------- 1605 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW 1606 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 1607 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 1608 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 1609 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 1610 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" 1611 // ----------------------------------------------------------------------------- 1612 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH 1613 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 1614 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 1615 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 1616 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 1617 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" 1618 // ----------------------------------------------------------------------------- 1619 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW 1620 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 1621 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 1622 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 1623 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 1624 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" 1625 // ----------------------------------------------------------------------------- 1626 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH 1627 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 1628 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 1629 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 1630 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 1631 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" 1632 // ----------------------------------------------------------------------------- 1633 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW 1634 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 1635 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 1636 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 1637 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 1638 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" 1639 // ----------------------------------------------------------------------------- 1640 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH 1641 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 1642 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 1643 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 1644 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 1645 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" 1646 // ----------------------------------------------------------------------------- 1647 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW 1648 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 1649 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 1650 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 1651 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 1652 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" 1653 // ----------------------------------------------------------------------------- 1654 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH 1655 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 1656 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 1657 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 1658 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 1659 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" 1660 // ----------------------------------------------------------------------------- 1661 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW 1662 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 1663 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 1664 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 1665 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 1666 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" 1667 // ----------------------------------------------------------------------------- 1668 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH 1669 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 1670 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 1671 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 1672 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 1673 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" 1674 // ----------------------------------------------------------------------------- 1675 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW 1676 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 1677 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 1678 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 1679 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 1680 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" 1681 // ----------------------------------------------------------------------------- 1682 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH 1683 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 1684 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 1685 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 1686 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 1687 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" 1688 // ----------------------------------------------------------------------------- 1689 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW 1690 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 1691 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 1692 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 1693 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 1694 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" 1695 // ----------------------------------------------------------------------------- 1696 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH 1697 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 1698 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 1699 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 1700 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 1701 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" 1702 // ----------------------------------------------------------------------------- 1703 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW 1704 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 1705 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 1706 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 1707 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 1708 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" 1709 // ----------------------------------------------------------------------------- 1710 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH 1711 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 1712 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 1713 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 1714 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 1715 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" 1716 // ----------------------------------------------------------------------------- 1717 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW 1718 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 1719 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 1720 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 1721 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 1722 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" 1723 // ----------------------------------------------------------------------------- 1724 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH 1725 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 1726 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 1727 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 1728 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 1729 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" 1730 // ----------------------------------------------------------------------------- 1731 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW 1732 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 1733 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 1734 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 1735 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 1736 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" 1737 // ----------------------------------------------------------------------------- 1738 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH 1739 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 1740 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 1741 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 1742 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 1743 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" 1744 // ----------------------------------------------------------------------------- 1745 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW 1746 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 1747 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 1748 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 1749 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 1750 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" 1751 // ----------------------------------------------------------------------------- 1752 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH 1753 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 1754 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 1755 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 1756 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 1757 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" 1758 // ----------------------------------------------------------------------------- 1759 // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW 1760 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 1761 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 1762 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 1763 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 1764 #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" 1765 // ----------------------------------------------------------------------------- 1766 // Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH 1767 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 1768 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 1769 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) 1770 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) 1771 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" 1772 // ----------------------------------------------------------------------------- 1773 // Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW 1774 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 1775 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 1776 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) 1777 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) 1778 #define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" 1779 // ----------------------------------------------------------------------------- 1780 // Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH 1781 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 1782 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 1783 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 1784 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 1785 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" 1786 // ----------------------------------------------------------------------------- 1787 // Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW 1788 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 1789 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 1790 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) 1791 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) 1792 #define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" 1793 // ----------------------------------------------------------------------------- 1794 // Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH 1795 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 1796 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 1797 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) 1798 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) 1799 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" 1800 // ----------------------------------------------------------------------------- 1801 // Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW 1802 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 1803 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 1804 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) 1805 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) 1806 #define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" 1807 // ----------------------------------------------------------------------------- 1808 // Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH 1809 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 1810 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 1811 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 1812 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 1813 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" 1814 // ----------------------------------------------------------------------------- 1815 // Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW 1816 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 1817 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 1818 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) 1819 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) 1820 #define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" 1821 // ============================================================================= 1822 // Register : IO_QSPI_PROC0_INTF 1823 // Description : Interrupt Force for proc0 1824 #define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000220) 1825 #define IO_QSPI_PROC0_INTF_BITS _u(0xffffffff) 1826 #define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) 1827 // ----------------------------------------------------------------------------- 1828 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH 1829 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 1830 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 1831 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 1832 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 1833 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" 1834 // ----------------------------------------------------------------------------- 1835 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW 1836 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 1837 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 1838 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 1839 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 1840 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" 1841 // ----------------------------------------------------------------------------- 1842 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH 1843 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 1844 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 1845 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 1846 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 1847 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" 1848 // ----------------------------------------------------------------------------- 1849 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW 1850 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 1851 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 1852 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 1853 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 1854 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" 1855 // ----------------------------------------------------------------------------- 1856 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH 1857 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 1858 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 1859 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 1860 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 1861 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" 1862 // ----------------------------------------------------------------------------- 1863 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW 1864 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 1865 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 1866 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 1867 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 1868 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" 1869 // ----------------------------------------------------------------------------- 1870 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH 1871 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 1872 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 1873 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 1874 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 1875 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" 1876 // ----------------------------------------------------------------------------- 1877 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW 1878 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 1879 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 1880 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 1881 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 1882 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" 1883 // ----------------------------------------------------------------------------- 1884 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH 1885 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 1886 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 1887 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 1888 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 1889 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" 1890 // ----------------------------------------------------------------------------- 1891 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW 1892 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 1893 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 1894 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 1895 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 1896 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" 1897 // ----------------------------------------------------------------------------- 1898 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH 1899 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 1900 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 1901 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 1902 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 1903 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" 1904 // ----------------------------------------------------------------------------- 1905 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW 1906 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 1907 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 1908 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 1909 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 1910 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" 1911 // ----------------------------------------------------------------------------- 1912 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH 1913 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 1914 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 1915 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 1916 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 1917 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" 1918 // ----------------------------------------------------------------------------- 1919 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW 1920 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 1921 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 1922 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 1923 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 1924 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" 1925 // ----------------------------------------------------------------------------- 1926 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH 1927 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 1928 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 1929 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 1930 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 1931 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" 1932 // ----------------------------------------------------------------------------- 1933 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW 1934 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 1935 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 1936 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 1937 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 1938 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" 1939 // ----------------------------------------------------------------------------- 1940 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH 1941 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 1942 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 1943 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 1944 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 1945 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" 1946 // ----------------------------------------------------------------------------- 1947 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW 1948 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 1949 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 1950 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 1951 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 1952 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" 1953 // ----------------------------------------------------------------------------- 1954 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH 1955 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 1956 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 1957 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 1958 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 1959 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" 1960 // ----------------------------------------------------------------------------- 1961 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW 1962 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 1963 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 1964 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 1965 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 1966 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" 1967 // ----------------------------------------------------------------------------- 1968 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH 1969 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 1970 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 1971 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 1972 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 1973 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" 1974 // ----------------------------------------------------------------------------- 1975 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW 1976 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 1977 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 1978 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 1979 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 1980 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" 1981 // ----------------------------------------------------------------------------- 1982 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH 1983 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 1984 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 1985 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 1986 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 1987 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" 1988 // ----------------------------------------------------------------------------- 1989 // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW 1990 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 1991 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 1992 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 1993 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 1994 #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" 1995 // ----------------------------------------------------------------------------- 1996 // Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH 1997 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 1998 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 1999 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) 2000 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) 2001 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" 2002 // ----------------------------------------------------------------------------- 2003 // Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW 2004 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 2005 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 2006 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) 2007 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) 2008 #define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" 2009 // ----------------------------------------------------------------------------- 2010 // Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH 2011 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 2012 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 2013 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 2014 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 2015 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" 2016 // ----------------------------------------------------------------------------- 2017 // Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW 2018 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 2019 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 2020 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) 2021 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) 2022 #define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" 2023 // ----------------------------------------------------------------------------- 2024 // Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH 2025 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 2026 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 2027 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) 2028 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) 2029 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" 2030 // ----------------------------------------------------------------------------- 2031 // Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW 2032 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 2033 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 2034 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) 2035 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) 2036 #define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" 2037 // ----------------------------------------------------------------------------- 2038 // Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH 2039 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 2040 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 2041 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 2042 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 2043 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" 2044 // ----------------------------------------------------------------------------- 2045 // Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW 2046 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 2047 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 2048 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) 2049 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) 2050 #define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" 2051 // ============================================================================= 2052 // Register : IO_QSPI_PROC0_INTS 2053 // Description : Interrupt status after masking & forcing for proc0 2054 #define IO_QSPI_PROC0_INTS_OFFSET _u(0x00000224) 2055 #define IO_QSPI_PROC0_INTS_BITS _u(0xffffffff) 2056 #define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) 2057 // ----------------------------------------------------------------------------- 2058 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH 2059 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 2060 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 2061 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 2062 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 2063 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" 2064 // ----------------------------------------------------------------------------- 2065 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW 2066 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 2067 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 2068 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 2069 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 2070 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" 2071 // ----------------------------------------------------------------------------- 2072 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH 2073 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 2074 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 2075 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 2076 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 2077 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" 2078 // ----------------------------------------------------------------------------- 2079 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW 2080 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 2081 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 2082 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 2083 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 2084 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" 2085 // ----------------------------------------------------------------------------- 2086 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH 2087 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 2088 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 2089 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 2090 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 2091 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" 2092 // ----------------------------------------------------------------------------- 2093 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW 2094 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 2095 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 2096 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 2097 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 2098 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" 2099 // ----------------------------------------------------------------------------- 2100 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH 2101 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 2102 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 2103 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 2104 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 2105 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" 2106 // ----------------------------------------------------------------------------- 2107 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW 2108 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 2109 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 2110 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 2111 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 2112 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" 2113 // ----------------------------------------------------------------------------- 2114 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH 2115 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 2116 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 2117 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 2118 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 2119 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" 2120 // ----------------------------------------------------------------------------- 2121 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW 2122 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 2123 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 2124 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 2125 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 2126 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" 2127 // ----------------------------------------------------------------------------- 2128 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH 2129 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 2130 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 2131 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 2132 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 2133 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" 2134 // ----------------------------------------------------------------------------- 2135 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW 2136 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 2137 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 2138 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 2139 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 2140 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" 2141 // ----------------------------------------------------------------------------- 2142 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH 2143 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 2144 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 2145 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 2146 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 2147 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" 2148 // ----------------------------------------------------------------------------- 2149 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW 2150 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 2151 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 2152 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 2153 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 2154 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" 2155 // ----------------------------------------------------------------------------- 2156 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH 2157 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 2158 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 2159 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 2160 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 2161 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" 2162 // ----------------------------------------------------------------------------- 2163 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW 2164 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 2165 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 2166 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 2167 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 2168 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" 2169 // ----------------------------------------------------------------------------- 2170 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH 2171 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 2172 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 2173 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 2174 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 2175 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" 2176 // ----------------------------------------------------------------------------- 2177 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW 2178 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 2179 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 2180 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 2181 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 2182 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" 2183 // ----------------------------------------------------------------------------- 2184 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH 2185 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 2186 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 2187 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 2188 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 2189 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" 2190 // ----------------------------------------------------------------------------- 2191 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW 2192 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 2193 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 2194 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 2195 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 2196 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" 2197 // ----------------------------------------------------------------------------- 2198 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH 2199 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 2200 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 2201 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 2202 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 2203 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" 2204 // ----------------------------------------------------------------------------- 2205 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW 2206 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 2207 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 2208 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 2209 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 2210 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" 2211 // ----------------------------------------------------------------------------- 2212 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH 2213 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 2214 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 2215 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 2216 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 2217 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" 2218 // ----------------------------------------------------------------------------- 2219 // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW 2220 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 2221 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 2222 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 2223 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 2224 #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" 2225 // ----------------------------------------------------------------------------- 2226 // Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH 2227 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 2228 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 2229 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) 2230 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) 2231 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" 2232 // ----------------------------------------------------------------------------- 2233 // Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW 2234 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 2235 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 2236 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) 2237 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) 2238 #define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" 2239 // ----------------------------------------------------------------------------- 2240 // Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH 2241 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 2242 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 2243 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 2244 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 2245 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" 2246 // ----------------------------------------------------------------------------- 2247 // Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW 2248 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 2249 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 2250 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) 2251 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) 2252 #define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" 2253 // ----------------------------------------------------------------------------- 2254 // Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH 2255 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 2256 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 2257 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) 2258 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) 2259 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" 2260 // ----------------------------------------------------------------------------- 2261 // Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW 2262 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 2263 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 2264 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) 2265 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) 2266 #define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" 2267 // ----------------------------------------------------------------------------- 2268 // Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH 2269 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 2270 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 2271 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 2272 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 2273 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" 2274 // ----------------------------------------------------------------------------- 2275 // Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW 2276 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 2277 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 2278 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) 2279 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) 2280 #define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" 2281 // ============================================================================= 2282 // Register : IO_QSPI_PROC1_INTE 2283 // Description : Interrupt Enable for proc1 2284 #define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000228) 2285 #define IO_QSPI_PROC1_INTE_BITS _u(0xffffffff) 2286 #define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) 2287 // ----------------------------------------------------------------------------- 2288 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH 2289 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 2290 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 2291 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 2292 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 2293 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" 2294 // ----------------------------------------------------------------------------- 2295 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW 2296 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 2297 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 2298 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 2299 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 2300 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" 2301 // ----------------------------------------------------------------------------- 2302 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH 2303 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 2304 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 2305 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 2306 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 2307 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" 2308 // ----------------------------------------------------------------------------- 2309 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW 2310 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 2311 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 2312 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 2313 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 2314 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" 2315 // ----------------------------------------------------------------------------- 2316 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH 2317 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 2318 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 2319 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 2320 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 2321 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" 2322 // ----------------------------------------------------------------------------- 2323 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW 2324 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 2325 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 2326 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 2327 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 2328 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" 2329 // ----------------------------------------------------------------------------- 2330 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH 2331 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 2332 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 2333 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 2334 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 2335 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" 2336 // ----------------------------------------------------------------------------- 2337 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW 2338 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 2339 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 2340 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 2341 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 2342 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" 2343 // ----------------------------------------------------------------------------- 2344 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH 2345 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 2346 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 2347 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 2348 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 2349 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" 2350 // ----------------------------------------------------------------------------- 2351 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW 2352 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 2353 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 2354 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 2355 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 2356 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" 2357 // ----------------------------------------------------------------------------- 2358 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH 2359 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 2360 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 2361 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 2362 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 2363 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" 2364 // ----------------------------------------------------------------------------- 2365 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW 2366 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 2367 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 2368 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 2369 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 2370 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" 2371 // ----------------------------------------------------------------------------- 2372 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH 2373 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 2374 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 2375 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 2376 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 2377 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" 2378 // ----------------------------------------------------------------------------- 2379 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW 2380 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 2381 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 2382 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 2383 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 2384 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" 2385 // ----------------------------------------------------------------------------- 2386 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH 2387 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 2388 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 2389 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 2390 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 2391 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" 2392 // ----------------------------------------------------------------------------- 2393 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW 2394 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 2395 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 2396 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 2397 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 2398 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" 2399 // ----------------------------------------------------------------------------- 2400 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH 2401 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 2402 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 2403 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 2404 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 2405 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" 2406 // ----------------------------------------------------------------------------- 2407 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW 2408 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 2409 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 2410 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 2411 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 2412 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" 2413 // ----------------------------------------------------------------------------- 2414 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH 2415 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 2416 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 2417 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 2418 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 2419 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" 2420 // ----------------------------------------------------------------------------- 2421 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW 2422 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 2423 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 2424 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 2425 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 2426 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" 2427 // ----------------------------------------------------------------------------- 2428 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH 2429 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 2430 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 2431 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 2432 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 2433 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" 2434 // ----------------------------------------------------------------------------- 2435 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW 2436 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 2437 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 2438 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 2439 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 2440 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" 2441 // ----------------------------------------------------------------------------- 2442 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH 2443 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 2444 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 2445 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 2446 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 2447 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" 2448 // ----------------------------------------------------------------------------- 2449 // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW 2450 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 2451 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 2452 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 2453 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 2454 #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" 2455 // ----------------------------------------------------------------------------- 2456 // Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH 2457 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 2458 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 2459 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) 2460 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) 2461 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" 2462 // ----------------------------------------------------------------------------- 2463 // Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW 2464 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 2465 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 2466 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) 2467 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) 2468 #define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" 2469 // ----------------------------------------------------------------------------- 2470 // Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH 2471 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 2472 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 2473 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 2474 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 2475 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" 2476 // ----------------------------------------------------------------------------- 2477 // Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW 2478 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 2479 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 2480 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) 2481 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) 2482 #define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" 2483 // ----------------------------------------------------------------------------- 2484 // Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH 2485 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 2486 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 2487 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) 2488 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) 2489 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" 2490 // ----------------------------------------------------------------------------- 2491 // Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW 2492 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 2493 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 2494 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) 2495 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) 2496 #define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" 2497 // ----------------------------------------------------------------------------- 2498 // Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH 2499 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 2500 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 2501 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 2502 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 2503 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" 2504 // ----------------------------------------------------------------------------- 2505 // Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW 2506 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 2507 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 2508 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) 2509 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) 2510 #define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" 2511 // ============================================================================= 2512 // Register : IO_QSPI_PROC1_INTF 2513 // Description : Interrupt Force for proc1 2514 #define IO_QSPI_PROC1_INTF_OFFSET _u(0x0000022c) 2515 #define IO_QSPI_PROC1_INTF_BITS _u(0xffffffff) 2516 #define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) 2517 // ----------------------------------------------------------------------------- 2518 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH 2519 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 2520 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 2521 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 2522 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 2523 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" 2524 // ----------------------------------------------------------------------------- 2525 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW 2526 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 2527 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 2528 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 2529 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 2530 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" 2531 // ----------------------------------------------------------------------------- 2532 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH 2533 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 2534 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 2535 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 2536 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 2537 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" 2538 // ----------------------------------------------------------------------------- 2539 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW 2540 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 2541 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 2542 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 2543 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 2544 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" 2545 // ----------------------------------------------------------------------------- 2546 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH 2547 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 2548 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 2549 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 2550 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 2551 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" 2552 // ----------------------------------------------------------------------------- 2553 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW 2554 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 2555 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 2556 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 2557 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 2558 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" 2559 // ----------------------------------------------------------------------------- 2560 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH 2561 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 2562 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 2563 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 2564 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 2565 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" 2566 // ----------------------------------------------------------------------------- 2567 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW 2568 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 2569 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 2570 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 2571 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 2572 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" 2573 // ----------------------------------------------------------------------------- 2574 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH 2575 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 2576 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 2577 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 2578 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 2579 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" 2580 // ----------------------------------------------------------------------------- 2581 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW 2582 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 2583 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 2584 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 2585 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 2586 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" 2587 // ----------------------------------------------------------------------------- 2588 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH 2589 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 2590 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 2591 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 2592 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 2593 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" 2594 // ----------------------------------------------------------------------------- 2595 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW 2596 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 2597 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 2598 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 2599 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 2600 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" 2601 // ----------------------------------------------------------------------------- 2602 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH 2603 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 2604 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 2605 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 2606 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 2607 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" 2608 // ----------------------------------------------------------------------------- 2609 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW 2610 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 2611 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 2612 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 2613 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 2614 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" 2615 // ----------------------------------------------------------------------------- 2616 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH 2617 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 2618 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 2619 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 2620 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 2621 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" 2622 // ----------------------------------------------------------------------------- 2623 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW 2624 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 2625 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 2626 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 2627 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 2628 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" 2629 // ----------------------------------------------------------------------------- 2630 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH 2631 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 2632 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 2633 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 2634 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 2635 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" 2636 // ----------------------------------------------------------------------------- 2637 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW 2638 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 2639 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 2640 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 2641 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 2642 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" 2643 // ----------------------------------------------------------------------------- 2644 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH 2645 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 2646 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 2647 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 2648 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 2649 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" 2650 // ----------------------------------------------------------------------------- 2651 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW 2652 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 2653 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 2654 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 2655 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 2656 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" 2657 // ----------------------------------------------------------------------------- 2658 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH 2659 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 2660 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 2661 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 2662 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 2663 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" 2664 // ----------------------------------------------------------------------------- 2665 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW 2666 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 2667 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 2668 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 2669 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 2670 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" 2671 // ----------------------------------------------------------------------------- 2672 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH 2673 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 2674 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 2675 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 2676 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 2677 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" 2678 // ----------------------------------------------------------------------------- 2679 // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW 2680 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 2681 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 2682 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 2683 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 2684 #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" 2685 // ----------------------------------------------------------------------------- 2686 // Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH 2687 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 2688 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 2689 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) 2690 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) 2691 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" 2692 // ----------------------------------------------------------------------------- 2693 // Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW 2694 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 2695 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 2696 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) 2697 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) 2698 #define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" 2699 // ----------------------------------------------------------------------------- 2700 // Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH 2701 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 2702 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 2703 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 2704 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 2705 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" 2706 // ----------------------------------------------------------------------------- 2707 // Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW 2708 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 2709 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 2710 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) 2711 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) 2712 #define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" 2713 // ----------------------------------------------------------------------------- 2714 // Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH 2715 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 2716 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 2717 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) 2718 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) 2719 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" 2720 // ----------------------------------------------------------------------------- 2721 // Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW 2722 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 2723 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 2724 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) 2725 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) 2726 #define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" 2727 // ----------------------------------------------------------------------------- 2728 // Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH 2729 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 2730 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 2731 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 2732 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 2733 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" 2734 // ----------------------------------------------------------------------------- 2735 // Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW 2736 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 2737 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 2738 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) 2739 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) 2740 #define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" 2741 // ============================================================================= 2742 // Register : IO_QSPI_PROC1_INTS 2743 // Description : Interrupt status after masking & forcing for proc1 2744 #define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000230) 2745 #define IO_QSPI_PROC1_INTS_BITS _u(0xffffffff) 2746 #define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) 2747 // ----------------------------------------------------------------------------- 2748 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH 2749 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 2750 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 2751 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 2752 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 2753 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" 2754 // ----------------------------------------------------------------------------- 2755 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW 2756 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 2757 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 2758 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 2759 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 2760 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" 2761 // ----------------------------------------------------------------------------- 2762 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH 2763 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 2764 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 2765 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 2766 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 2767 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" 2768 // ----------------------------------------------------------------------------- 2769 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW 2770 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 2771 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 2772 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 2773 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 2774 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" 2775 // ----------------------------------------------------------------------------- 2776 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH 2777 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 2778 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 2779 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 2780 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 2781 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" 2782 // ----------------------------------------------------------------------------- 2783 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW 2784 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 2785 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 2786 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 2787 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 2788 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" 2789 // ----------------------------------------------------------------------------- 2790 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH 2791 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 2792 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 2793 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 2794 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 2795 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" 2796 // ----------------------------------------------------------------------------- 2797 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW 2798 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 2799 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 2800 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 2801 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 2802 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" 2803 // ----------------------------------------------------------------------------- 2804 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH 2805 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 2806 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 2807 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 2808 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 2809 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" 2810 // ----------------------------------------------------------------------------- 2811 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW 2812 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 2813 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 2814 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 2815 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 2816 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" 2817 // ----------------------------------------------------------------------------- 2818 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH 2819 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 2820 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 2821 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 2822 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 2823 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" 2824 // ----------------------------------------------------------------------------- 2825 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW 2826 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 2827 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 2828 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 2829 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 2830 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" 2831 // ----------------------------------------------------------------------------- 2832 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH 2833 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 2834 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 2835 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 2836 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 2837 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" 2838 // ----------------------------------------------------------------------------- 2839 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW 2840 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 2841 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 2842 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 2843 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 2844 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" 2845 // ----------------------------------------------------------------------------- 2846 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH 2847 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 2848 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 2849 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 2850 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 2851 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" 2852 // ----------------------------------------------------------------------------- 2853 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW 2854 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 2855 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 2856 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 2857 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 2858 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" 2859 // ----------------------------------------------------------------------------- 2860 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH 2861 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 2862 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 2863 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 2864 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 2865 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" 2866 // ----------------------------------------------------------------------------- 2867 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW 2868 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 2869 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 2870 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 2871 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 2872 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" 2873 // ----------------------------------------------------------------------------- 2874 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH 2875 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 2876 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 2877 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 2878 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 2879 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" 2880 // ----------------------------------------------------------------------------- 2881 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW 2882 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 2883 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 2884 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 2885 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 2886 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" 2887 // ----------------------------------------------------------------------------- 2888 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH 2889 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 2890 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 2891 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 2892 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 2893 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" 2894 // ----------------------------------------------------------------------------- 2895 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW 2896 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 2897 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 2898 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 2899 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 2900 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" 2901 // ----------------------------------------------------------------------------- 2902 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH 2903 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 2904 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 2905 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 2906 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 2907 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" 2908 // ----------------------------------------------------------------------------- 2909 // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW 2910 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 2911 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 2912 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 2913 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 2914 #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" 2915 // ----------------------------------------------------------------------------- 2916 // Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH 2917 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 2918 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 2919 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) 2920 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) 2921 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" 2922 // ----------------------------------------------------------------------------- 2923 // Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW 2924 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 2925 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 2926 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) 2927 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) 2928 #define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" 2929 // ----------------------------------------------------------------------------- 2930 // Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH 2931 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 2932 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 2933 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 2934 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 2935 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" 2936 // ----------------------------------------------------------------------------- 2937 // Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW 2938 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 2939 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 2940 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) 2941 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) 2942 #define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" 2943 // ----------------------------------------------------------------------------- 2944 // Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH 2945 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 2946 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 2947 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) 2948 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) 2949 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" 2950 // ----------------------------------------------------------------------------- 2951 // Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW 2952 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 2953 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 2954 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) 2955 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) 2956 #define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" 2957 // ----------------------------------------------------------------------------- 2958 // Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH 2959 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 2960 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 2961 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 2962 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 2963 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" 2964 // ----------------------------------------------------------------------------- 2965 // Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW 2966 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 2967 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 2968 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) 2969 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) 2970 #define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" 2971 // ============================================================================= 2972 // Register : IO_QSPI_DORMANT_WAKE_INTE 2973 // Description : Interrupt Enable for dormant_wake 2974 #define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x00000234) 2975 #define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0xffffffff) 2976 #define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) 2977 // ----------------------------------------------------------------------------- 2978 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH 2979 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 2980 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 2981 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 2982 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 2983 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" 2984 // ----------------------------------------------------------------------------- 2985 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW 2986 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 2987 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 2988 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 2989 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 2990 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" 2991 // ----------------------------------------------------------------------------- 2992 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH 2993 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 2994 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 2995 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 2996 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 2997 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" 2998 // ----------------------------------------------------------------------------- 2999 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW 3000 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 3001 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 3002 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 3003 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 3004 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" 3005 // ----------------------------------------------------------------------------- 3006 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH 3007 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 3008 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 3009 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 3010 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 3011 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" 3012 // ----------------------------------------------------------------------------- 3013 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW 3014 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 3015 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 3016 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 3017 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 3018 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" 3019 // ----------------------------------------------------------------------------- 3020 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH 3021 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 3022 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 3023 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 3024 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 3025 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" 3026 // ----------------------------------------------------------------------------- 3027 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW 3028 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 3029 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 3030 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 3031 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 3032 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" 3033 // ----------------------------------------------------------------------------- 3034 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH 3035 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 3036 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 3037 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 3038 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 3039 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" 3040 // ----------------------------------------------------------------------------- 3041 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW 3042 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 3043 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 3044 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 3045 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 3046 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" 3047 // ----------------------------------------------------------------------------- 3048 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH 3049 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 3050 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 3051 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 3052 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 3053 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" 3054 // ----------------------------------------------------------------------------- 3055 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW 3056 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 3057 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 3058 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 3059 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 3060 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" 3061 // ----------------------------------------------------------------------------- 3062 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH 3063 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 3064 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 3065 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 3066 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 3067 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" 3068 // ----------------------------------------------------------------------------- 3069 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW 3070 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 3071 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 3072 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 3073 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 3074 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" 3075 // ----------------------------------------------------------------------------- 3076 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH 3077 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 3078 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 3079 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 3080 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 3081 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" 3082 // ----------------------------------------------------------------------------- 3083 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW 3084 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 3085 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 3086 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 3087 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 3088 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" 3089 // ----------------------------------------------------------------------------- 3090 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH 3091 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 3092 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 3093 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 3094 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 3095 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" 3096 // ----------------------------------------------------------------------------- 3097 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW 3098 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 3099 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 3100 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 3101 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 3102 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" 3103 // ----------------------------------------------------------------------------- 3104 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH 3105 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 3106 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 3107 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 3108 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 3109 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" 3110 // ----------------------------------------------------------------------------- 3111 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW 3112 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 3113 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 3114 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 3115 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 3116 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" 3117 // ----------------------------------------------------------------------------- 3118 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH 3119 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 3120 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 3121 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 3122 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 3123 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" 3124 // ----------------------------------------------------------------------------- 3125 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW 3126 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 3127 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 3128 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 3129 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 3130 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" 3131 // ----------------------------------------------------------------------------- 3132 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH 3133 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 3134 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 3135 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 3136 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 3137 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" 3138 // ----------------------------------------------------------------------------- 3139 // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW 3140 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 3141 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 3142 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 3143 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 3144 #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" 3145 // ----------------------------------------------------------------------------- 3146 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH 3147 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 3148 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 3149 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) 3150 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) 3151 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" 3152 // ----------------------------------------------------------------------------- 3153 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW 3154 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 3155 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 3156 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) 3157 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) 3158 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" 3159 // ----------------------------------------------------------------------------- 3160 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH 3161 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 3162 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 3163 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 3164 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 3165 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" 3166 // ----------------------------------------------------------------------------- 3167 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW 3168 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 3169 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 3170 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) 3171 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) 3172 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" 3173 // ----------------------------------------------------------------------------- 3174 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH 3175 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 3176 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 3177 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) 3178 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) 3179 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" 3180 // ----------------------------------------------------------------------------- 3181 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW 3182 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 3183 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 3184 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) 3185 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) 3186 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" 3187 // ----------------------------------------------------------------------------- 3188 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH 3189 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 3190 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 3191 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 3192 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 3193 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" 3194 // ----------------------------------------------------------------------------- 3195 // Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW 3196 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 3197 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 3198 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) 3199 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) 3200 #define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" 3201 // ============================================================================= 3202 // Register : IO_QSPI_DORMANT_WAKE_INTF 3203 // Description : Interrupt Force for dormant_wake 3204 #define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000238) 3205 #define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0xffffffff) 3206 #define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) 3207 // ----------------------------------------------------------------------------- 3208 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH 3209 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 3210 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 3211 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 3212 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 3213 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" 3214 // ----------------------------------------------------------------------------- 3215 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW 3216 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 3217 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 3218 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 3219 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 3220 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" 3221 // ----------------------------------------------------------------------------- 3222 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH 3223 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 3224 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 3225 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 3226 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 3227 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" 3228 // ----------------------------------------------------------------------------- 3229 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW 3230 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 3231 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 3232 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 3233 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 3234 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" 3235 // ----------------------------------------------------------------------------- 3236 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH 3237 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 3238 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 3239 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 3240 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 3241 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" 3242 // ----------------------------------------------------------------------------- 3243 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW 3244 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 3245 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 3246 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 3247 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 3248 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" 3249 // ----------------------------------------------------------------------------- 3250 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH 3251 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 3252 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 3253 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 3254 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 3255 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" 3256 // ----------------------------------------------------------------------------- 3257 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW 3258 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 3259 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 3260 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 3261 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 3262 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" 3263 // ----------------------------------------------------------------------------- 3264 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH 3265 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 3266 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 3267 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 3268 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 3269 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" 3270 // ----------------------------------------------------------------------------- 3271 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW 3272 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 3273 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 3274 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 3275 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 3276 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" 3277 // ----------------------------------------------------------------------------- 3278 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH 3279 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 3280 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 3281 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 3282 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 3283 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" 3284 // ----------------------------------------------------------------------------- 3285 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW 3286 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 3287 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 3288 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 3289 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 3290 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" 3291 // ----------------------------------------------------------------------------- 3292 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH 3293 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 3294 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 3295 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 3296 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 3297 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" 3298 // ----------------------------------------------------------------------------- 3299 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW 3300 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 3301 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 3302 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 3303 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 3304 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" 3305 // ----------------------------------------------------------------------------- 3306 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH 3307 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 3308 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 3309 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 3310 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 3311 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" 3312 // ----------------------------------------------------------------------------- 3313 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW 3314 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 3315 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 3316 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 3317 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 3318 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" 3319 // ----------------------------------------------------------------------------- 3320 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH 3321 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 3322 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 3323 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 3324 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 3325 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" 3326 // ----------------------------------------------------------------------------- 3327 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW 3328 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 3329 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 3330 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 3331 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 3332 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" 3333 // ----------------------------------------------------------------------------- 3334 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH 3335 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 3336 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 3337 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 3338 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 3339 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" 3340 // ----------------------------------------------------------------------------- 3341 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW 3342 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 3343 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 3344 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 3345 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 3346 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" 3347 // ----------------------------------------------------------------------------- 3348 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH 3349 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 3350 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 3351 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 3352 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 3353 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" 3354 // ----------------------------------------------------------------------------- 3355 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW 3356 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 3357 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 3358 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 3359 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 3360 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" 3361 // ----------------------------------------------------------------------------- 3362 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH 3363 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 3364 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 3365 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 3366 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 3367 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" 3368 // ----------------------------------------------------------------------------- 3369 // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW 3370 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 3371 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 3372 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 3373 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 3374 #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" 3375 // ----------------------------------------------------------------------------- 3376 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH 3377 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 3378 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 3379 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) 3380 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) 3381 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" 3382 // ----------------------------------------------------------------------------- 3383 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW 3384 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 3385 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 3386 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) 3387 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) 3388 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" 3389 // ----------------------------------------------------------------------------- 3390 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH 3391 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 3392 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 3393 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 3394 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 3395 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" 3396 // ----------------------------------------------------------------------------- 3397 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW 3398 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 3399 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 3400 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) 3401 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) 3402 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" 3403 // ----------------------------------------------------------------------------- 3404 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH 3405 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 3406 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 3407 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) 3408 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) 3409 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" 3410 // ----------------------------------------------------------------------------- 3411 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW 3412 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 3413 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 3414 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) 3415 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) 3416 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" 3417 // ----------------------------------------------------------------------------- 3418 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH 3419 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 3420 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 3421 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 3422 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 3423 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" 3424 // ----------------------------------------------------------------------------- 3425 // Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW 3426 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 3427 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 3428 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) 3429 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) 3430 #define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" 3431 // ============================================================================= 3432 // Register : IO_QSPI_DORMANT_WAKE_INTS 3433 // Description : Interrupt status after masking & forcing for dormant_wake 3434 #define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x0000023c) 3435 #define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0xffffffff) 3436 #define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) 3437 // ----------------------------------------------------------------------------- 3438 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH 3439 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) 3440 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) 3441 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) 3442 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) 3443 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" 3444 // ----------------------------------------------------------------------------- 3445 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW 3446 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) 3447 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) 3448 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) 3449 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) 3450 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" 3451 // ----------------------------------------------------------------------------- 3452 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH 3453 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) 3454 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) 3455 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) 3456 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) 3457 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" 3458 // ----------------------------------------------------------------------------- 3459 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW 3460 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) 3461 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) 3462 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) 3463 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) 3464 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" 3465 // ----------------------------------------------------------------------------- 3466 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH 3467 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) 3468 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) 3469 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) 3470 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) 3471 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" 3472 // ----------------------------------------------------------------------------- 3473 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW 3474 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) 3475 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) 3476 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) 3477 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) 3478 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" 3479 // ----------------------------------------------------------------------------- 3480 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH 3481 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) 3482 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) 3483 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) 3484 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) 3485 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" 3486 // ----------------------------------------------------------------------------- 3487 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW 3488 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) 3489 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) 3490 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) 3491 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) 3492 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" 3493 // ----------------------------------------------------------------------------- 3494 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH 3495 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) 3496 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) 3497 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) 3498 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) 3499 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" 3500 // ----------------------------------------------------------------------------- 3501 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW 3502 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) 3503 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) 3504 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) 3505 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) 3506 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" 3507 // ----------------------------------------------------------------------------- 3508 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH 3509 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) 3510 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) 3511 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) 3512 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) 3513 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" 3514 // ----------------------------------------------------------------------------- 3515 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW 3516 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) 3517 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) 3518 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) 3519 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) 3520 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" 3521 // ----------------------------------------------------------------------------- 3522 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH 3523 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) 3524 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) 3525 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) 3526 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) 3527 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" 3528 // ----------------------------------------------------------------------------- 3529 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW 3530 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) 3531 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) 3532 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) 3533 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) 3534 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" 3535 // ----------------------------------------------------------------------------- 3536 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH 3537 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) 3538 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) 3539 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) 3540 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) 3541 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" 3542 // ----------------------------------------------------------------------------- 3543 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW 3544 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) 3545 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) 3546 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) 3547 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) 3548 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" 3549 // ----------------------------------------------------------------------------- 3550 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH 3551 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) 3552 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) 3553 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) 3554 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) 3555 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" 3556 // ----------------------------------------------------------------------------- 3557 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW 3558 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) 3559 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) 3560 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) 3561 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) 3562 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" 3563 // ----------------------------------------------------------------------------- 3564 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH 3565 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) 3566 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) 3567 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) 3568 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) 3569 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" 3570 // ----------------------------------------------------------------------------- 3571 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW 3572 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) 3573 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) 3574 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) 3575 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) 3576 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" 3577 // ----------------------------------------------------------------------------- 3578 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH 3579 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) 3580 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) 3581 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) 3582 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) 3583 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" 3584 // ----------------------------------------------------------------------------- 3585 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW 3586 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) 3587 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) 3588 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) 3589 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) 3590 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" 3591 // ----------------------------------------------------------------------------- 3592 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH 3593 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) 3594 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) 3595 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) 3596 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) 3597 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" 3598 // ----------------------------------------------------------------------------- 3599 // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW 3600 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) 3601 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) 3602 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) 3603 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) 3604 #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" 3605 // ----------------------------------------------------------------------------- 3606 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH 3607 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) 3608 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) 3609 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) 3610 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) 3611 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" 3612 // ----------------------------------------------------------------------------- 3613 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW 3614 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) 3615 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) 3616 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) 3617 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) 3618 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" 3619 // ----------------------------------------------------------------------------- 3620 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH 3621 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) 3622 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) 3623 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) 3624 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) 3625 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" 3626 // ----------------------------------------------------------------------------- 3627 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW 3628 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) 3629 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) 3630 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) 3631 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) 3632 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" 3633 // ----------------------------------------------------------------------------- 3634 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH 3635 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) 3636 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) 3637 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) 3638 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) 3639 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" 3640 // ----------------------------------------------------------------------------- 3641 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW 3642 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) 3643 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) 3644 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) 3645 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) 3646 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" 3647 // ----------------------------------------------------------------------------- 3648 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH 3649 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) 3650 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) 3651 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) 3652 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) 3653 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" 3654 // ----------------------------------------------------------------------------- 3655 // Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW 3656 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) 3657 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) 3658 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) 3659 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) 3660 #define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" 3661 // ============================================================================= 3662 #endif // _HARDWARE_REGS_IO_QSPI_H 3663 3664
