1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : HSTX_FIFO
10 // Version        : 1
11 // Bus type       : ahbl
12 // Description    : FIFO status and write access for HSTX
13 // =============================================================================
14 #ifndef _HARDWARE_REGS_HSTX_FIFO_H
15 #define _HARDWARE_REGS_HSTX_FIFO_H
16 // =============================================================================
17 // Register    : HSTX_FIFO_STAT
18 // Description : FIFO status
19 #define HSTX_FIFO_STAT_OFFSET _u(0x00000000)
20 #define HSTX_FIFO_STAT_BITS   _u(0x000007ff)
21 #define HSTX_FIFO_STAT_RESET  _u(0x00000000)
22 // -----------------------------------------------------------------------------
23 // Field       : HSTX_FIFO_STAT_WOF
24 // Description : FIFO was written when full. Write 1 to clear.
25 #define HSTX_FIFO_STAT_WOF_RESET  _u(0x0)
26 #define HSTX_FIFO_STAT_WOF_BITS   _u(0x00000400)
27 #define HSTX_FIFO_STAT_WOF_MSB    _u(10)
28 #define HSTX_FIFO_STAT_WOF_LSB    _u(10)
29 #define HSTX_FIFO_STAT_WOF_ACCESS "WC"
30 // -----------------------------------------------------------------------------
31 // Field       : HSTX_FIFO_STAT_EMPTY
32 #define HSTX_FIFO_STAT_EMPTY_RESET  "-"
33 #define HSTX_FIFO_STAT_EMPTY_BITS   _u(0x00000200)
34 #define HSTX_FIFO_STAT_EMPTY_MSB    _u(9)
35 #define HSTX_FIFO_STAT_EMPTY_LSB    _u(9)
36 #define HSTX_FIFO_STAT_EMPTY_ACCESS "RO"
37 // -----------------------------------------------------------------------------
38 // Field       : HSTX_FIFO_STAT_FULL
39 #define HSTX_FIFO_STAT_FULL_RESET  "-"
40 #define HSTX_FIFO_STAT_FULL_BITS   _u(0x00000100)
41 #define HSTX_FIFO_STAT_FULL_MSB    _u(8)
42 #define HSTX_FIFO_STAT_FULL_LSB    _u(8)
43 #define HSTX_FIFO_STAT_FULL_ACCESS "RO"
44 // -----------------------------------------------------------------------------
45 // Field       : HSTX_FIFO_STAT_LEVEL
46 #define HSTX_FIFO_STAT_LEVEL_RESET  _u(0x00)
47 #define HSTX_FIFO_STAT_LEVEL_BITS   _u(0x000000ff)
48 #define HSTX_FIFO_STAT_LEVEL_MSB    _u(7)
49 #define HSTX_FIFO_STAT_LEVEL_LSB    _u(0)
50 #define HSTX_FIFO_STAT_LEVEL_ACCESS "RO"
51 // =============================================================================
52 // Register    : HSTX_FIFO_FIFO
53 // Description : Write access to FIFO
54 #define HSTX_FIFO_FIFO_OFFSET _u(0x00000004)
55 #define HSTX_FIFO_FIFO_BITS   _u(0xffffffff)
56 #define HSTX_FIFO_FIFO_RESET  _u(0x00000000)
57 #define HSTX_FIFO_FIFO_MSB    _u(31)
58 #define HSTX_FIFO_FIFO_LSB    _u(0)
59 #define HSTX_FIFO_FIFO_ACCESS "WF"
60 // =============================================================================
61 #endif // _HARDWARE_REGS_HSTX_FIFO_H
62 
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