1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : GLITCH_DETECTOR 10 // Version : 1 11 // Bus type : apb 12 // Description : Glitch detector controls 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H 15 #define _HARDWARE_REGS_GLITCH_DETECTOR_H 16 // ============================================================================= 17 // Register : GLITCH_DETECTOR_ARM 18 // Description : Forcibly arm the glitch detectors, if they are not already 19 // armed by OTP. When armed, any individual detector trigger will 20 // cause a restart of the switched core power domain's power-on 21 // reset state machine. 22 // 23 // Glitch detector triggers are recorded accumulatively in 24 // TRIG_STATUS. If the system is reset by a glitch detector 25 // trigger, this is recorded in POWMAN_CHIP_RESET. 26 // 27 // This register is Secure read/write only. 28 // 0x5bad -> Do not force the glitch detectors to be armed 29 // 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) 30 #define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000) 31 #define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff) 32 #define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad) 33 #define GLITCH_DETECTOR_ARM_MSB _u(15) 34 #define GLITCH_DETECTOR_ARM_LSB _u(0) 35 #define GLITCH_DETECTOR_ARM_ACCESS "RW" 36 #define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad) 37 #define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000) 38 // ============================================================================= 39 // Register : GLITCH_DETECTOR_DISARM 40 // Description : None 41 // Forcibly disarm the glitch detectors, if they are armed by OTP. 42 // Ignored if ARM is YES. 43 // 44 // This register is Secure read/write only. 45 // 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) 46 // 0xdcaf -> Disarm the glitch detectors 47 #define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004) 48 #define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff) 49 #define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000) 50 #define GLITCH_DETECTOR_DISARM_MSB _u(15) 51 #define GLITCH_DETECTOR_DISARM_LSB _u(0) 52 #define GLITCH_DETECTOR_DISARM_ACCESS "RW" 53 #define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000) 54 #define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf) 55 // ============================================================================= 56 // Register : GLITCH_DETECTOR_SENSITIVITY 57 // Description : Adjust the sensitivity of glitch detectors to values other than 58 // their OTP-provided defaults. 59 // 60 // This register is Secure read/write only. 61 #define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008) 62 #define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff) 63 #define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000) 64 // ----------------------------------------------------------------------------- 65 // Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT 66 // 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) 67 // 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register. 68 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00) 69 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000) 70 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31) 71 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24) 72 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW" 73 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00) 74 #define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde) 75 // ----------------------------------------------------------------------------- 76 // Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV 77 // Description : Must be the inverse of DET3, else the default value is used. 78 #define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0) 79 #define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000) 80 #define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15) 81 #define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14) 82 #define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW" 83 // ----------------------------------------------------------------------------- 84 // Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV 85 // Description : Must be the inverse of DET2, else the default value is used. 86 #define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0) 87 #define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000) 88 #define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13) 89 #define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12) 90 #define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW" 91 // ----------------------------------------------------------------------------- 92 // Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV 93 // Description : Must be the inverse of DET1, else the default value is used. 94 #define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0) 95 #define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00) 96 #define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11) 97 #define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10) 98 #define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW" 99 // ----------------------------------------------------------------------------- 100 // Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV 101 // Description : Must be the inverse of DET0, else the default value is used. 102 #define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0) 103 #define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300) 104 #define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9) 105 #define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8) 106 #define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW" 107 // ----------------------------------------------------------------------------- 108 // Field : GLITCH_DETECTOR_SENSITIVITY_DET3 109 // Description : Set sensitivity for detector 3. Higher values are more 110 // sensitive. 111 #define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0) 112 #define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0) 113 #define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7) 114 #define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6) 115 #define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW" 116 // ----------------------------------------------------------------------------- 117 // Field : GLITCH_DETECTOR_SENSITIVITY_DET2 118 // Description : Set sensitivity for detector 2. Higher values are more 119 // sensitive. 120 #define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0) 121 #define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030) 122 #define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5) 123 #define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4) 124 #define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW" 125 // ----------------------------------------------------------------------------- 126 // Field : GLITCH_DETECTOR_SENSITIVITY_DET1 127 // Description : Set sensitivity for detector 1. Higher values are more 128 // sensitive. 129 #define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0) 130 #define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c) 131 #define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3) 132 #define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2) 133 #define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW" 134 // ----------------------------------------------------------------------------- 135 // Field : GLITCH_DETECTOR_SENSITIVITY_DET0 136 // Description : Set sensitivity for detector 0. Higher values are more 137 // sensitive. 138 #define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0) 139 #define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003) 140 #define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1) 141 #define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0) 142 #define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW" 143 // ============================================================================= 144 // Register : GLITCH_DETECTOR_LOCK 145 // Description : None 146 // Write any nonzero value to disable writes to ARM, DISARM, 147 // SENSITIVITY and LOCK. This register is Secure read/write only. 148 #define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c) 149 #define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff) 150 #define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000) 151 #define GLITCH_DETECTOR_LOCK_MSB _u(7) 152 #define GLITCH_DETECTOR_LOCK_LSB _u(0) 153 #define GLITCH_DETECTOR_LOCK_ACCESS "RW" 154 // ============================================================================= 155 // Register : GLITCH_DETECTOR_TRIG_STATUS 156 // Description : Set when a detector output triggers. Write-1-clear. 157 // 158 // (May immediately return high if the detector remains in a 159 // failed state. Detectors can only be cleared by a full reset of 160 // the switched core power domain.) 161 // 162 // This register is Secure read/write only. 163 #define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010) 164 #define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f) 165 #define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000) 166 // ----------------------------------------------------------------------------- 167 // Field : GLITCH_DETECTOR_TRIG_STATUS_DET3 168 #define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0) 169 #define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008) 170 #define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3) 171 #define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3) 172 #define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC" 173 // ----------------------------------------------------------------------------- 174 // Field : GLITCH_DETECTOR_TRIG_STATUS_DET2 175 #define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0) 176 #define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004) 177 #define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2) 178 #define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2) 179 #define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC" 180 // ----------------------------------------------------------------------------- 181 // Field : GLITCH_DETECTOR_TRIG_STATUS_DET1 182 #define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0) 183 #define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002) 184 #define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1) 185 #define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1) 186 #define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC" 187 // ----------------------------------------------------------------------------- 188 // Field : GLITCH_DETECTOR_TRIG_STATUS_DET0 189 #define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0) 190 #define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001) 191 #define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0) 192 #define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0) 193 #define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC" 194 // ============================================================================= 195 // Register : GLITCH_DETECTOR_TRIG_FORCE 196 // Description : Simulate the firing of one or more detectors. Writing ones to 197 // this register will set the matching bits in STATUS_TRIG. 198 // 199 // If the glitch detectors are currently armed, writing ones will 200 // also immediately reset the switched core power domain, and set 201 // the reset reason latches in POWMAN_CHIP_RESET to indicate a 202 // glitch detector resets. 203 // 204 // This register is Secure read/write only. 205 #define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014) 206 #define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f) 207 #define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000) 208 #define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3) 209 #define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0) 210 #define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC" 211 // ============================================================================= 212 #endif // _HARDWARE_REGS_GLITCH_DETECTOR_H 213 214
