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Searched refs:CCR (Results 1 – 5 of 5) sorted by relevance

/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/
Darmv7m_cachel1.h58 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
65 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
81 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
146 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
167 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
195 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/
Dcore_cm0plus.h367 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
Dcore_cm33.h528 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/
DRP2040.h566 …__IOM uint32_t CCR; /*!< The Configuration and Control Register permanen… member
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/
DRP2350.h960 …__IOM uint32_t CCR; /*!< Sets or returns configuration and control data … member