1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : BUSCTRL 10 // Version : 1 11 // Bus type : apb 12 // Description : Register block for busfabric control signals and performance 13 // counters 14 // ============================================================================= 15 #ifndef _HARDWARE_REGS_BUSCTRL_H 16 #define _HARDWARE_REGS_BUSCTRL_H 17 // ============================================================================= 18 // Register : BUSCTRL_BUS_PRIORITY 19 // Description : Set the priority of each master for bus arbitration. 20 #define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) 21 #define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) 22 #define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) 23 // ----------------------------------------------------------------------------- 24 // Field : BUSCTRL_BUS_PRIORITY_DMA_W 25 // Description : 0 - low priority, 1 - high priority 26 #define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) 27 #define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) 28 #define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) 29 #define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) 30 #define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" 31 // ----------------------------------------------------------------------------- 32 // Field : BUSCTRL_BUS_PRIORITY_DMA_R 33 // Description : 0 - low priority, 1 - high priority 34 #define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) 35 #define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) 36 #define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) 37 #define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) 38 #define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" 39 // ----------------------------------------------------------------------------- 40 // Field : BUSCTRL_BUS_PRIORITY_PROC1 41 // Description : 0 - low priority, 1 - high priority 42 #define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) 43 #define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) 44 #define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) 45 #define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) 46 #define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" 47 // ----------------------------------------------------------------------------- 48 // Field : BUSCTRL_BUS_PRIORITY_PROC0 49 // Description : 0 - low priority, 1 - high priority 50 #define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) 51 #define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) 52 #define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) 53 #define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) 54 #define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" 55 // ============================================================================= 56 // Register : BUSCTRL_BUS_PRIORITY_ACK 57 // Description : Bus priority acknowledge 58 // Goes to 1 once all arbiters have registered the new global 59 // priority levels. 60 // Arbiters update their local priority when servicing a new 61 // nonsequential access. 62 // In normal circumstances this will happen almost immediately. 63 #define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) 64 #define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) 65 #define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) 66 #define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) 67 #define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) 68 #define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" 69 // ============================================================================= 70 // Register : BUSCTRL_PERFCTR_EN 71 // Description : Enable the performance counters. If 0, the performance counters 72 // do not increment. This can be used to precisely start/stop 73 // event sampling around the profiled section of code. 74 // 75 // The performance counters are initially disabled, to save 76 // energy. 77 #define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008) 78 #define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001) 79 #define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000) 80 #define BUSCTRL_PERFCTR_EN_MSB _u(0) 81 #define BUSCTRL_PERFCTR_EN_LSB _u(0) 82 #define BUSCTRL_PERFCTR_EN_ACCESS "RW" 83 // ============================================================================= 84 // Register : BUSCTRL_PERFCTR0 85 // Description : Bus fabric performance counter 0 86 // Busfabric saturating performance counter 0 87 // Count some event signal from the busfabric arbiters, if 88 // PERFCTR_EN is set. 89 // Write any value to clear. Select an event to count using 90 // PERFSEL0 91 #define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c) 92 #define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) 93 #define BUSCTRL_PERFCTR0_RESET _u(0x00000000) 94 #define BUSCTRL_PERFCTR0_MSB _u(23) 95 #define BUSCTRL_PERFCTR0_LSB _u(0) 96 #define BUSCTRL_PERFCTR0_ACCESS "WC" 97 // ============================================================================= 98 // Register : BUSCTRL_PERFSEL0 99 // Description : Bus fabric performance event select for PERFCTR0 100 // Select an event for PERFCTR0. For each downstream port of the 101 // main crossbar, four events are available: ACCESS, an access 102 // took place; ACCESS_CONTESTED, an access took place that 103 // previously stalled due to contention from other masters; 104 // STALL_DOWNSTREAM, count cycles where any master stalled due to 105 // a stall on the downstream bus; STALL_UPSTREAM, count cycles 106 // where any master stalled for any reason, including contention 107 // from other masters. 108 // 0x00 -> siob_proc1_stall_upstream 109 // 0x01 -> siob_proc1_stall_downstream 110 // 0x02 -> siob_proc1_access_contested 111 // 0x03 -> siob_proc1_access 112 // 0x04 -> siob_proc0_stall_upstream 113 // 0x05 -> siob_proc0_stall_downstream 114 // 0x06 -> siob_proc0_access_contested 115 // 0x07 -> siob_proc0_access 116 // 0x08 -> apb_stall_upstream 117 // 0x09 -> apb_stall_downstream 118 // 0x0a -> apb_access_contested 119 // 0x0b -> apb_access 120 // 0x0c -> fastperi_stall_upstream 121 // 0x0d -> fastperi_stall_downstream 122 // 0x0e -> fastperi_access_contested 123 // 0x0f -> fastperi_access 124 // 0x10 -> sram9_stall_upstream 125 // 0x11 -> sram9_stall_downstream 126 // 0x12 -> sram9_access_contested 127 // 0x13 -> sram9_access 128 // 0x14 -> sram8_stall_upstream 129 // 0x15 -> sram8_stall_downstream 130 // 0x16 -> sram8_access_contested 131 // 0x17 -> sram8_access 132 // 0x18 -> sram7_stall_upstream 133 // 0x19 -> sram7_stall_downstream 134 // 0x1a -> sram7_access_contested 135 // 0x1b -> sram7_access 136 // 0x1c -> sram6_stall_upstream 137 // 0x1d -> sram6_stall_downstream 138 // 0x1e -> sram6_access_contested 139 // 0x1f -> sram6_access 140 // 0x20 -> sram5_stall_upstream 141 // 0x21 -> sram5_stall_downstream 142 // 0x22 -> sram5_access_contested 143 // 0x23 -> sram5_access 144 // 0x24 -> sram4_stall_upstream 145 // 0x25 -> sram4_stall_downstream 146 // 0x26 -> sram4_access_contested 147 // 0x27 -> sram4_access 148 // 0x28 -> sram3_stall_upstream 149 // 0x29 -> sram3_stall_downstream 150 // 0x2a -> sram3_access_contested 151 // 0x2b -> sram3_access 152 // 0x2c -> sram2_stall_upstream 153 // 0x2d -> sram2_stall_downstream 154 // 0x2e -> sram2_access_contested 155 // 0x2f -> sram2_access 156 // 0x30 -> sram1_stall_upstream 157 // 0x31 -> sram1_stall_downstream 158 // 0x32 -> sram1_access_contested 159 // 0x33 -> sram1_access 160 // 0x34 -> sram0_stall_upstream 161 // 0x35 -> sram0_stall_downstream 162 // 0x36 -> sram0_access_contested 163 // 0x37 -> sram0_access 164 // 0x38 -> xip_main1_stall_upstream 165 // 0x39 -> xip_main1_stall_downstream 166 // 0x3a -> xip_main1_access_contested 167 // 0x3b -> xip_main1_access 168 // 0x3c -> xip_main0_stall_upstream 169 // 0x3d -> xip_main0_stall_downstream 170 // 0x3e -> xip_main0_access_contested 171 // 0x3f -> xip_main0_access 172 // 0x40 -> rom_stall_upstream 173 // 0x41 -> rom_stall_downstream 174 // 0x42 -> rom_access_contested 175 // 0x43 -> rom_access 176 #define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010) 177 #define BUSCTRL_PERFSEL0_BITS _u(0x0000007f) 178 #define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) 179 #define BUSCTRL_PERFSEL0_MSB _u(6) 180 #define BUSCTRL_PERFSEL0_LSB _u(0) 181 #define BUSCTRL_PERFSEL0_ACCESS "RW" 182 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) 183 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) 184 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) 185 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03) 186 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) 187 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) 188 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) 189 #define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07) 190 #define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08) 191 #define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09) 192 #define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a) 193 #define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b) 194 #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) 195 #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) 196 #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) 197 #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f) 198 #define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) 199 #define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) 200 #define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) 201 #define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13) 202 #define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) 203 #define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) 204 #define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) 205 #define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17) 206 #define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) 207 #define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) 208 #define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) 209 #define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b) 210 #define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) 211 #define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) 212 #define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) 213 #define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f) 214 #define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) 215 #define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) 216 #define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) 217 #define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23) 218 #define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) 219 #define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) 220 #define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) 221 #define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27) 222 #define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) 223 #define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) 224 #define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) 225 #define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b) 226 #define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) 227 #define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) 228 #define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) 229 #define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f) 230 #define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) 231 #define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) 232 #define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) 233 #define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33) 234 #define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) 235 #define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) 236 #define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) 237 #define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37) 238 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) 239 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) 240 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) 241 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b) 242 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) 243 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) 244 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) 245 #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f) 246 #define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40) 247 #define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) 248 #define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42) 249 #define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43) 250 // ============================================================================= 251 // Register : BUSCTRL_PERFCTR1 252 // Description : Bus fabric performance counter 1 253 // Busfabric saturating performance counter 1 254 // Count some event signal from the busfabric arbiters, if 255 // PERFCTR_EN is set. 256 // Write any value to clear. Select an event to count using 257 // PERFSEL1 258 #define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014) 259 #define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) 260 #define BUSCTRL_PERFCTR1_RESET _u(0x00000000) 261 #define BUSCTRL_PERFCTR1_MSB _u(23) 262 #define BUSCTRL_PERFCTR1_LSB _u(0) 263 #define BUSCTRL_PERFCTR1_ACCESS "WC" 264 // ============================================================================= 265 // Register : BUSCTRL_PERFSEL1 266 // Description : Bus fabric performance event select for PERFCTR1 267 // Select an event for PERFCTR1. For each downstream port of the 268 // main crossbar, four events are available: ACCESS, an access 269 // took place; ACCESS_CONTESTED, an access took place that 270 // previously stalled due to contention from other masters; 271 // STALL_DOWNSTREAM, count cycles where any master stalled due to 272 // a stall on the downstream bus; STALL_UPSTREAM, count cycles 273 // where any master stalled for any reason, including contention 274 // from other masters. 275 // 0x00 -> siob_proc1_stall_upstream 276 // 0x01 -> siob_proc1_stall_downstream 277 // 0x02 -> siob_proc1_access_contested 278 // 0x03 -> siob_proc1_access 279 // 0x04 -> siob_proc0_stall_upstream 280 // 0x05 -> siob_proc0_stall_downstream 281 // 0x06 -> siob_proc0_access_contested 282 // 0x07 -> siob_proc0_access 283 // 0x08 -> apb_stall_upstream 284 // 0x09 -> apb_stall_downstream 285 // 0x0a -> apb_access_contested 286 // 0x0b -> apb_access 287 // 0x0c -> fastperi_stall_upstream 288 // 0x0d -> fastperi_stall_downstream 289 // 0x0e -> fastperi_access_contested 290 // 0x0f -> fastperi_access 291 // 0x10 -> sram9_stall_upstream 292 // 0x11 -> sram9_stall_downstream 293 // 0x12 -> sram9_access_contested 294 // 0x13 -> sram9_access 295 // 0x14 -> sram8_stall_upstream 296 // 0x15 -> sram8_stall_downstream 297 // 0x16 -> sram8_access_contested 298 // 0x17 -> sram8_access 299 // 0x18 -> sram7_stall_upstream 300 // 0x19 -> sram7_stall_downstream 301 // 0x1a -> sram7_access_contested 302 // 0x1b -> sram7_access 303 // 0x1c -> sram6_stall_upstream 304 // 0x1d -> sram6_stall_downstream 305 // 0x1e -> sram6_access_contested 306 // 0x1f -> sram6_access 307 // 0x20 -> sram5_stall_upstream 308 // 0x21 -> sram5_stall_downstream 309 // 0x22 -> sram5_access_contested 310 // 0x23 -> sram5_access 311 // 0x24 -> sram4_stall_upstream 312 // 0x25 -> sram4_stall_downstream 313 // 0x26 -> sram4_access_contested 314 // 0x27 -> sram4_access 315 // 0x28 -> sram3_stall_upstream 316 // 0x29 -> sram3_stall_downstream 317 // 0x2a -> sram3_access_contested 318 // 0x2b -> sram3_access 319 // 0x2c -> sram2_stall_upstream 320 // 0x2d -> sram2_stall_downstream 321 // 0x2e -> sram2_access_contested 322 // 0x2f -> sram2_access 323 // 0x30 -> sram1_stall_upstream 324 // 0x31 -> sram1_stall_downstream 325 // 0x32 -> sram1_access_contested 326 // 0x33 -> sram1_access 327 // 0x34 -> sram0_stall_upstream 328 // 0x35 -> sram0_stall_downstream 329 // 0x36 -> sram0_access_contested 330 // 0x37 -> sram0_access 331 // 0x38 -> xip_main1_stall_upstream 332 // 0x39 -> xip_main1_stall_downstream 333 // 0x3a -> xip_main1_access_contested 334 // 0x3b -> xip_main1_access 335 // 0x3c -> xip_main0_stall_upstream 336 // 0x3d -> xip_main0_stall_downstream 337 // 0x3e -> xip_main0_access_contested 338 // 0x3f -> xip_main0_access 339 // 0x40 -> rom_stall_upstream 340 // 0x41 -> rom_stall_downstream 341 // 0x42 -> rom_access_contested 342 // 0x43 -> rom_access 343 #define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018) 344 #define BUSCTRL_PERFSEL1_BITS _u(0x0000007f) 345 #define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) 346 #define BUSCTRL_PERFSEL1_MSB _u(6) 347 #define BUSCTRL_PERFSEL1_LSB _u(0) 348 #define BUSCTRL_PERFSEL1_ACCESS "RW" 349 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) 350 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) 351 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) 352 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03) 353 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) 354 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) 355 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) 356 #define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07) 357 #define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08) 358 #define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09) 359 #define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a) 360 #define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b) 361 #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) 362 #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) 363 #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) 364 #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f) 365 #define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) 366 #define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) 367 #define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) 368 #define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13) 369 #define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) 370 #define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) 371 #define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) 372 #define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17) 373 #define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) 374 #define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) 375 #define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) 376 #define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b) 377 #define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) 378 #define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) 379 #define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) 380 #define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f) 381 #define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) 382 #define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) 383 #define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) 384 #define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23) 385 #define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) 386 #define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) 387 #define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) 388 #define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27) 389 #define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) 390 #define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) 391 #define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) 392 #define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b) 393 #define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) 394 #define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) 395 #define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) 396 #define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f) 397 #define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) 398 #define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) 399 #define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) 400 #define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33) 401 #define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) 402 #define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) 403 #define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) 404 #define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37) 405 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) 406 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) 407 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) 408 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b) 409 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) 410 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) 411 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) 412 #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f) 413 #define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40) 414 #define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) 415 #define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42) 416 #define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43) 417 // ============================================================================= 418 // Register : BUSCTRL_PERFCTR2 419 // Description : Bus fabric performance counter 2 420 // Busfabric saturating performance counter 2 421 // Count some event signal from the busfabric arbiters, if 422 // PERFCTR_EN is set. 423 // Write any value to clear. Select an event to count using 424 // PERFSEL2 425 #define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c) 426 #define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) 427 #define BUSCTRL_PERFCTR2_RESET _u(0x00000000) 428 #define BUSCTRL_PERFCTR2_MSB _u(23) 429 #define BUSCTRL_PERFCTR2_LSB _u(0) 430 #define BUSCTRL_PERFCTR2_ACCESS "WC" 431 // ============================================================================= 432 // Register : BUSCTRL_PERFSEL2 433 // Description : Bus fabric performance event select for PERFCTR2 434 // Select an event for PERFCTR2. For each downstream port of the 435 // main crossbar, four events are available: ACCESS, an access 436 // took place; ACCESS_CONTESTED, an access took place that 437 // previously stalled due to contention from other masters; 438 // STALL_DOWNSTREAM, count cycles where any master stalled due to 439 // a stall on the downstream bus; STALL_UPSTREAM, count cycles 440 // where any master stalled for any reason, including contention 441 // from other masters. 442 // 0x00 -> siob_proc1_stall_upstream 443 // 0x01 -> siob_proc1_stall_downstream 444 // 0x02 -> siob_proc1_access_contested 445 // 0x03 -> siob_proc1_access 446 // 0x04 -> siob_proc0_stall_upstream 447 // 0x05 -> siob_proc0_stall_downstream 448 // 0x06 -> siob_proc0_access_contested 449 // 0x07 -> siob_proc0_access 450 // 0x08 -> apb_stall_upstream 451 // 0x09 -> apb_stall_downstream 452 // 0x0a -> apb_access_contested 453 // 0x0b -> apb_access 454 // 0x0c -> fastperi_stall_upstream 455 // 0x0d -> fastperi_stall_downstream 456 // 0x0e -> fastperi_access_contested 457 // 0x0f -> fastperi_access 458 // 0x10 -> sram9_stall_upstream 459 // 0x11 -> sram9_stall_downstream 460 // 0x12 -> sram9_access_contested 461 // 0x13 -> sram9_access 462 // 0x14 -> sram8_stall_upstream 463 // 0x15 -> sram8_stall_downstream 464 // 0x16 -> sram8_access_contested 465 // 0x17 -> sram8_access 466 // 0x18 -> sram7_stall_upstream 467 // 0x19 -> sram7_stall_downstream 468 // 0x1a -> sram7_access_contested 469 // 0x1b -> sram7_access 470 // 0x1c -> sram6_stall_upstream 471 // 0x1d -> sram6_stall_downstream 472 // 0x1e -> sram6_access_contested 473 // 0x1f -> sram6_access 474 // 0x20 -> sram5_stall_upstream 475 // 0x21 -> sram5_stall_downstream 476 // 0x22 -> sram5_access_contested 477 // 0x23 -> sram5_access 478 // 0x24 -> sram4_stall_upstream 479 // 0x25 -> sram4_stall_downstream 480 // 0x26 -> sram4_access_contested 481 // 0x27 -> sram4_access 482 // 0x28 -> sram3_stall_upstream 483 // 0x29 -> sram3_stall_downstream 484 // 0x2a -> sram3_access_contested 485 // 0x2b -> sram3_access 486 // 0x2c -> sram2_stall_upstream 487 // 0x2d -> sram2_stall_downstream 488 // 0x2e -> sram2_access_contested 489 // 0x2f -> sram2_access 490 // 0x30 -> sram1_stall_upstream 491 // 0x31 -> sram1_stall_downstream 492 // 0x32 -> sram1_access_contested 493 // 0x33 -> sram1_access 494 // 0x34 -> sram0_stall_upstream 495 // 0x35 -> sram0_stall_downstream 496 // 0x36 -> sram0_access_contested 497 // 0x37 -> sram0_access 498 // 0x38 -> xip_main1_stall_upstream 499 // 0x39 -> xip_main1_stall_downstream 500 // 0x3a -> xip_main1_access_contested 501 // 0x3b -> xip_main1_access 502 // 0x3c -> xip_main0_stall_upstream 503 // 0x3d -> xip_main0_stall_downstream 504 // 0x3e -> xip_main0_access_contested 505 // 0x3f -> xip_main0_access 506 // 0x40 -> rom_stall_upstream 507 // 0x41 -> rom_stall_downstream 508 // 0x42 -> rom_access_contested 509 // 0x43 -> rom_access 510 #define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020) 511 #define BUSCTRL_PERFSEL2_BITS _u(0x0000007f) 512 #define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) 513 #define BUSCTRL_PERFSEL2_MSB _u(6) 514 #define BUSCTRL_PERFSEL2_LSB _u(0) 515 #define BUSCTRL_PERFSEL2_ACCESS "RW" 516 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) 517 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) 518 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) 519 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03) 520 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) 521 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) 522 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) 523 #define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07) 524 #define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08) 525 #define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09) 526 #define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a) 527 #define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b) 528 #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) 529 #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) 530 #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) 531 #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f) 532 #define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) 533 #define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) 534 #define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) 535 #define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13) 536 #define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) 537 #define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) 538 #define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) 539 #define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17) 540 #define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) 541 #define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) 542 #define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) 543 #define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b) 544 #define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) 545 #define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) 546 #define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) 547 #define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f) 548 #define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) 549 #define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) 550 #define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) 551 #define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23) 552 #define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) 553 #define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) 554 #define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) 555 #define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27) 556 #define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) 557 #define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) 558 #define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) 559 #define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b) 560 #define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) 561 #define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) 562 #define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) 563 #define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f) 564 #define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) 565 #define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) 566 #define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) 567 #define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33) 568 #define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) 569 #define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) 570 #define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) 571 #define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37) 572 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) 573 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) 574 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) 575 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b) 576 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) 577 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) 578 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) 579 #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f) 580 #define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40) 581 #define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) 582 #define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42) 583 #define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43) 584 // ============================================================================= 585 // Register : BUSCTRL_PERFCTR3 586 // Description : Bus fabric performance counter 3 587 // Busfabric saturating performance counter 3 588 // Count some event signal from the busfabric arbiters, if 589 // PERFCTR_EN is set. 590 // Write any value to clear. Select an event to count using 591 // PERFSEL3 592 #define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024) 593 #define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) 594 #define BUSCTRL_PERFCTR3_RESET _u(0x00000000) 595 #define BUSCTRL_PERFCTR3_MSB _u(23) 596 #define BUSCTRL_PERFCTR3_LSB _u(0) 597 #define BUSCTRL_PERFCTR3_ACCESS "WC" 598 // ============================================================================= 599 // Register : BUSCTRL_PERFSEL3 600 // Description : Bus fabric performance event select for PERFCTR3 601 // Select an event for PERFCTR3. For each downstream port of the 602 // main crossbar, four events are available: ACCESS, an access 603 // took place; ACCESS_CONTESTED, an access took place that 604 // previously stalled due to contention from other masters; 605 // STALL_DOWNSTREAM, count cycles where any master stalled due to 606 // a stall on the downstream bus; STALL_UPSTREAM, count cycles 607 // where any master stalled for any reason, including contention 608 // from other masters. 609 // 0x00 -> siob_proc1_stall_upstream 610 // 0x01 -> siob_proc1_stall_downstream 611 // 0x02 -> siob_proc1_access_contested 612 // 0x03 -> siob_proc1_access 613 // 0x04 -> siob_proc0_stall_upstream 614 // 0x05 -> siob_proc0_stall_downstream 615 // 0x06 -> siob_proc0_access_contested 616 // 0x07 -> siob_proc0_access 617 // 0x08 -> apb_stall_upstream 618 // 0x09 -> apb_stall_downstream 619 // 0x0a -> apb_access_contested 620 // 0x0b -> apb_access 621 // 0x0c -> fastperi_stall_upstream 622 // 0x0d -> fastperi_stall_downstream 623 // 0x0e -> fastperi_access_contested 624 // 0x0f -> fastperi_access 625 // 0x10 -> sram9_stall_upstream 626 // 0x11 -> sram9_stall_downstream 627 // 0x12 -> sram9_access_contested 628 // 0x13 -> sram9_access 629 // 0x14 -> sram8_stall_upstream 630 // 0x15 -> sram8_stall_downstream 631 // 0x16 -> sram8_access_contested 632 // 0x17 -> sram8_access 633 // 0x18 -> sram7_stall_upstream 634 // 0x19 -> sram7_stall_downstream 635 // 0x1a -> sram7_access_contested 636 // 0x1b -> sram7_access 637 // 0x1c -> sram6_stall_upstream 638 // 0x1d -> sram6_stall_downstream 639 // 0x1e -> sram6_access_contested 640 // 0x1f -> sram6_access 641 // 0x20 -> sram5_stall_upstream 642 // 0x21 -> sram5_stall_downstream 643 // 0x22 -> sram5_access_contested 644 // 0x23 -> sram5_access 645 // 0x24 -> sram4_stall_upstream 646 // 0x25 -> sram4_stall_downstream 647 // 0x26 -> sram4_access_contested 648 // 0x27 -> sram4_access 649 // 0x28 -> sram3_stall_upstream 650 // 0x29 -> sram3_stall_downstream 651 // 0x2a -> sram3_access_contested 652 // 0x2b -> sram3_access 653 // 0x2c -> sram2_stall_upstream 654 // 0x2d -> sram2_stall_downstream 655 // 0x2e -> sram2_access_contested 656 // 0x2f -> sram2_access 657 // 0x30 -> sram1_stall_upstream 658 // 0x31 -> sram1_stall_downstream 659 // 0x32 -> sram1_access_contested 660 // 0x33 -> sram1_access 661 // 0x34 -> sram0_stall_upstream 662 // 0x35 -> sram0_stall_downstream 663 // 0x36 -> sram0_access_contested 664 // 0x37 -> sram0_access 665 // 0x38 -> xip_main1_stall_upstream 666 // 0x39 -> xip_main1_stall_downstream 667 // 0x3a -> xip_main1_access_contested 668 // 0x3b -> xip_main1_access 669 // 0x3c -> xip_main0_stall_upstream 670 // 0x3d -> xip_main0_stall_downstream 671 // 0x3e -> xip_main0_access_contested 672 // 0x3f -> xip_main0_access 673 // 0x40 -> rom_stall_upstream 674 // 0x41 -> rom_stall_downstream 675 // 0x42 -> rom_access_contested 676 // 0x43 -> rom_access 677 #define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028) 678 #define BUSCTRL_PERFSEL3_BITS _u(0x0000007f) 679 #define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) 680 #define BUSCTRL_PERFSEL3_MSB _u(6) 681 #define BUSCTRL_PERFSEL3_LSB _u(0) 682 #define BUSCTRL_PERFSEL3_ACCESS "RW" 683 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) 684 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) 685 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) 686 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03) 687 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) 688 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) 689 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) 690 #define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07) 691 #define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08) 692 #define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09) 693 #define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a) 694 #define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b) 695 #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) 696 #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) 697 #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) 698 #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f) 699 #define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) 700 #define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) 701 #define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) 702 #define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13) 703 #define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) 704 #define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) 705 #define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) 706 #define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17) 707 #define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) 708 #define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) 709 #define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) 710 #define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b) 711 #define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) 712 #define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) 713 #define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) 714 #define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f) 715 #define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) 716 #define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) 717 #define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) 718 #define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23) 719 #define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) 720 #define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) 721 #define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) 722 #define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27) 723 #define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) 724 #define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) 725 #define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) 726 #define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b) 727 #define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) 728 #define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) 729 #define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) 730 #define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f) 731 #define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) 732 #define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) 733 #define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) 734 #define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33) 735 #define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) 736 #define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) 737 #define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) 738 #define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37) 739 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) 740 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) 741 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) 742 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b) 743 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) 744 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) 745 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) 746 #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f) 747 #define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40) 748 #define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) 749 #define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42) 750 #define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43) 751 // ============================================================================= 752 #endif // _HARDWARE_REGS_BUSCTRL_H 753 754
