1 /**
2  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 // =============================================================================
7 // Register block : XOSC
8 // Version        : 1
9 // Bus type       : apb
10 // Description    : Controls the crystal oscillator
11 // =============================================================================
12 #ifndef HARDWARE_REGS_XOSC_DEFINED
13 #define HARDWARE_REGS_XOSC_DEFINED
14 // =============================================================================
15 // Register    : XOSC_CTRL
16 // Description : Crystal Oscillator Control
17 #define XOSC_CTRL_OFFSET _u(0x00000000)
18 #define XOSC_CTRL_BITS   _u(0x00ffffff)
19 #define XOSC_CTRL_RESET  _u(0x00000000)
20 // -----------------------------------------------------------------------------
21 // Field       : XOSC_CTRL_ENABLE
22 // Description : On power-up this field is initialised to DISABLE and the chip
23 //               runs from the ROSC.
24 //               If the chip has subsequently been programmed to run from the
25 //               XOSC then setting this field to DISABLE may lock-up the chip.
26 //               If this is a concern then run the clk_ref from the ROSC and
27 //               enable the clk_sys RESUS feature.
28 //               The 12-bit code is intended to give some protection against
29 //               accidental writes. An invalid setting will enable the
30 //               oscillator.
31 //               0xd1e -> DISABLE
32 //               0xfab -> ENABLE
33 #define XOSC_CTRL_ENABLE_RESET         "-"
34 #define XOSC_CTRL_ENABLE_BITS          _u(0x00fff000)
35 #define XOSC_CTRL_ENABLE_MSB           _u(23)
36 #define XOSC_CTRL_ENABLE_LSB           _u(12)
37 #define XOSC_CTRL_ENABLE_ACCESS        "RW"
38 #define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
39 #define XOSC_CTRL_ENABLE_VALUE_ENABLE  _u(0xfab)
40 // -----------------------------------------------------------------------------
41 // Field       : XOSC_CTRL_FREQ_RANGE
42 // Description : Frequency range. This resets to 0xAA0 and cannot be changed.
43 //               0xaa0 -> 1_15MHZ
44 //               0xaa1 -> RESERVED_1
45 //               0xaa2 -> RESERVED_2
46 //               0xaa3 -> RESERVED_3
47 #define XOSC_CTRL_FREQ_RANGE_RESET            "-"
48 #define XOSC_CTRL_FREQ_RANGE_BITS             _u(0x00000fff)
49 #define XOSC_CTRL_FREQ_RANGE_MSB              _u(11)
50 #define XOSC_CTRL_FREQ_RANGE_LSB              _u(0)
51 #define XOSC_CTRL_FREQ_RANGE_ACCESS           "RW"
52 #define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ    _u(0xaa0)
53 #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
54 #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
55 #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
56 // =============================================================================
57 // Register    : XOSC_STATUS
58 // Description : Crystal Oscillator Status
59 #define XOSC_STATUS_OFFSET _u(0x00000004)
60 #define XOSC_STATUS_BITS   _u(0x81001003)
61 #define XOSC_STATUS_RESET  _u(0x00000000)
62 // -----------------------------------------------------------------------------
63 // Field       : XOSC_STATUS_STABLE
64 // Description : Oscillator is running and stable
65 #define XOSC_STATUS_STABLE_RESET  _u(0x0)
66 #define XOSC_STATUS_STABLE_BITS   _u(0x80000000)
67 #define XOSC_STATUS_STABLE_MSB    _u(31)
68 #define XOSC_STATUS_STABLE_LSB    _u(31)
69 #define XOSC_STATUS_STABLE_ACCESS "RO"
70 // -----------------------------------------------------------------------------
71 // Field       : XOSC_STATUS_BADWRITE
72 // Description : An invalid value has been written to CTRL_ENABLE or
73 //               CTRL_FREQ_RANGE or DORMANT
74 #define XOSC_STATUS_BADWRITE_RESET  _u(0x0)
75 #define XOSC_STATUS_BADWRITE_BITS   _u(0x01000000)
76 #define XOSC_STATUS_BADWRITE_MSB    _u(24)
77 #define XOSC_STATUS_BADWRITE_LSB    _u(24)
78 #define XOSC_STATUS_BADWRITE_ACCESS "WC"
79 // -----------------------------------------------------------------------------
80 // Field       : XOSC_STATUS_ENABLED
81 // Description : Oscillator is enabled but not necessarily running and stable,
82 //               resets to 0
83 #define XOSC_STATUS_ENABLED_RESET  "-"
84 #define XOSC_STATUS_ENABLED_BITS   _u(0x00001000)
85 #define XOSC_STATUS_ENABLED_MSB    _u(12)
86 #define XOSC_STATUS_ENABLED_LSB    _u(12)
87 #define XOSC_STATUS_ENABLED_ACCESS "RO"
88 // -----------------------------------------------------------------------------
89 // Field       : XOSC_STATUS_FREQ_RANGE
90 // Description : The current frequency range setting, always reads 0
91 //               0x0 -> 1_15MHZ
92 //               0x1 -> RESERVED_1
93 //               0x2 -> RESERVED_2
94 //               0x3 -> RESERVED_3
95 #define XOSC_STATUS_FREQ_RANGE_RESET            "-"
96 #define XOSC_STATUS_FREQ_RANGE_BITS             _u(0x00000003)
97 #define XOSC_STATUS_FREQ_RANGE_MSB              _u(1)
98 #define XOSC_STATUS_FREQ_RANGE_LSB              _u(0)
99 #define XOSC_STATUS_FREQ_RANGE_ACCESS           "RO"
100 #define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ    _u(0x0)
101 #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
102 #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
103 #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
104 // =============================================================================
105 // Register    : XOSC_DORMANT
106 // Description : Crystal Oscillator pause control
107 //               This is used to save power by pausing the XOSC
108 //               On power-up this field is initialised to WAKE
109 //               An invalid write will also select WAKE
110 //               WARNING: stop the PLLs before selecting dormant mode
111 //               WARNING: setup the irq before selecting dormant mode
112 //               0x636f6d61 -> DORMANT
113 //               0x77616b65 -> WAKE
114 #define XOSC_DORMANT_OFFSET        _u(0x00000008)
115 #define XOSC_DORMANT_BITS          _u(0xffffffff)
116 #define XOSC_DORMANT_RESET         "-"
117 #define XOSC_DORMANT_MSB           _u(31)
118 #define XOSC_DORMANT_LSB           _u(0)
119 #define XOSC_DORMANT_ACCESS        "RW"
120 #define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
121 #define XOSC_DORMANT_VALUE_WAKE    _u(0x77616b65)
122 // =============================================================================
123 // Register    : XOSC_STARTUP
124 // Description : Controls the startup delay
125 #define XOSC_STARTUP_OFFSET _u(0x0000000c)
126 #define XOSC_STARTUP_BITS   _u(0x00103fff)
127 #define XOSC_STARTUP_RESET  _u(0x000000c4)
128 // -----------------------------------------------------------------------------
129 // Field       : XOSC_STARTUP_X4
130 // Description : Multiplies the startup_delay by 4. This is of little value to
131 //               the user given that the delay can be programmed directly.
132 #define XOSC_STARTUP_X4_RESET  _u(0x0)
133 #define XOSC_STARTUP_X4_BITS   _u(0x00100000)
134 #define XOSC_STARTUP_X4_MSB    _u(20)
135 #define XOSC_STARTUP_X4_LSB    _u(20)
136 #define XOSC_STARTUP_X4_ACCESS "RW"
137 // -----------------------------------------------------------------------------
138 // Field       : XOSC_STARTUP_DELAY
139 // Description : in multiples of 256*xtal_period. The reset value of 0xc4
140 //               corresponds to approx 50 000 cycles.
141 #define XOSC_STARTUP_DELAY_RESET  _u(0x00c4)
142 #define XOSC_STARTUP_DELAY_BITS   _u(0x00003fff)
143 #define XOSC_STARTUP_DELAY_MSB    _u(13)
144 #define XOSC_STARTUP_DELAY_LSB    _u(0)
145 #define XOSC_STARTUP_DELAY_ACCESS "RW"
146 // =============================================================================
147 // Register    : XOSC_COUNT
148 // Description : A down counter running at the xosc frequency which counts to
149 //               zero and stops.
150 //               To start the counter write a non-zero value.
151 //               Can be used for short software pauses when setting up time
152 //               sensitive hardware.
153 #define XOSC_COUNT_OFFSET _u(0x0000001c)
154 #define XOSC_COUNT_BITS   _u(0x000000ff)
155 #define XOSC_COUNT_RESET  _u(0x00000000)
156 #define XOSC_COUNT_MSB    _u(7)
157 #define XOSC_COUNT_LSB    _u(0)
158 #define XOSC_COUNT_ACCESS "RW"
159 // =============================================================================
160 #endif // HARDWARE_REGS_XOSC_DEFINED
161