1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : RESETS 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_RESETS_DEFINED 13 #define HARDWARE_REGS_RESETS_DEFINED 14 // ============================================================================= 15 // Register : RESETS_RESET 16 // Description : Reset control. If a bit is set it means the peripheral is in 17 // reset. 0 means the peripheral's reset is deasserted. 18 #define RESETS_RESET_OFFSET _u(0x00000000) 19 #define RESETS_RESET_BITS _u(0x01ffffff) 20 #define RESETS_RESET_RESET _u(0x01ffffff) 21 // ----------------------------------------------------------------------------- 22 // Field : RESETS_RESET_USBCTRL 23 // Description : None 24 #define RESETS_RESET_USBCTRL_RESET _u(0x1) 25 #define RESETS_RESET_USBCTRL_BITS _u(0x01000000) 26 #define RESETS_RESET_USBCTRL_MSB _u(24) 27 #define RESETS_RESET_USBCTRL_LSB _u(24) 28 #define RESETS_RESET_USBCTRL_ACCESS "RW" 29 // ----------------------------------------------------------------------------- 30 // Field : RESETS_RESET_UART1 31 // Description : None 32 #define RESETS_RESET_UART1_RESET _u(0x1) 33 #define RESETS_RESET_UART1_BITS _u(0x00800000) 34 #define RESETS_RESET_UART1_MSB _u(23) 35 #define RESETS_RESET_UART1_LSB _u(23) 36 #define RESETS_RESET_UART1_ACCESS "RW" 37 // ----------------------------------------------------------------------------- 38 // Field : RESETS_RESET_UART0 39 // Description : None 40 #define RESETS_RESET_UART0_RESET _u(0x1) 41 #define RESETS_RESET_UART0_BITS _u(0x00400000) 42 #define RESETS_RESET_UART0_MSB _u(22) 43 #define RESETS_RESET_UART0_LSB _u(22) 44 #define RESETS_RESET_UART0_ACCESS "RW" 45 // ----------------------------------------------------------------------------- 46 // Field : RESETS_RESET_TIMER 47 // Description : None 48 #define RESETS_RESET_TIMER_RESET _u(0x1) 49 #define RESETS_RESET_TIMER_BITS _u(0x00200000) 50 #define RESETS_RESET_TIMER_MSB _u(21) 51 #define RESETS_RESET_TIMER_LSB _u(21) 52 #define RESETS_RESET_TIMER_ACCESS "RW" 53 // ----------------------------------------------------------------------------- 54 // Field : RESETS_RESET_TBMAN 55 // Description : None 56 #define RESETS_RESET_TBMAN_RESET _u(0x1) 57 #define RESETS_RESET_TBMAN_BITS _u(0x00100000) 58 #define RESETS_RESET_TBMAN_MSB _u(20) 59 #define RESETS_RESET_TBMAN_LSB _u(20) 60 #define RESETS_RESET_TBMAN_ACCESS "RW" 61 // ----------------------------------------------------------------------------- 62 // Field : RESETS_RESET_SYSINFO 63 // Description : None 64 #define RESETS_RESET_SYSINFO_RESET _u(0x1) 65 #define RESETS_RESET_SYSINFO_BITS _u(0x00080000) 66 #define RESETS_RESET_SYSINFO_MSB _u(19) 67 #define RESETS_RESET_SYSINFO_LSB _u(19) 68 #define RESETS_RESET_SYSINFO_ACCESS "RW" 69 // ----------------------------------------------------------------------------- 70 // Field : RESETS_RESET_SYSCFG 71 // Description : None 72 #define RESETS_RESET_SYSCFG_RESET _u(0x1) 73 #define RESETS_RESET_SYSCFG_BITS _u(0x00040000) 74 #define RESETS_RESET_SYSCFG_MSB _u(18) 75 #define RESETS_RESET_SYSCFG_LSB _u(18) 76 #define RESETS_RESET_SYSCFG_ACCESS "RW" 77 // ----------------------------------------------------------------------------- 78 // Field : RESETS_RESET_SPI1 79 // Description : None 80 #define RESETS_RESET_SPI1_RESET _u(0x1) 81 #define RESETS_RESET_SPI1_BITS _u(0x00020000) 82 #define RESETS_RESET_SPI1_MSB _u(17) 83 #define RESETS_RESET_SPI1_LSB _u(17) 84 #define RESETS_RESET_SPI1_ACCESS "RW" 85 // ----------------------------------------------------------------------------- 86 // Field : RESETS_RESET_SPI0 87 // Description : None 88 #define RESETS_RESET_SPI0_RESET _u(0x1) 89 #define RESETS_RESET_SPI0_BITS _u(0x00010000) 90 #define RESETS_RESET_SPI0_MSB _u(16) 91 #define RESETS_RESET_SPI0_LSB _u(16) 92 #define RESETS_RESET_SPI0_ACCESS "RW" 93 // ----------------------------------------------------------------------------- 94 // Field : RESETS_RESET_RTC 95 // Description : None 96 #define RESETS_RESET_RTC_RESET _u(0x1) 97 #define RESETS_RESET_RTC_BITS _u(0x00008000) 98 #define RESETS_RESET_RTC_MSB _u(15) 99 #define RESETS_RESET_RTC_LSB _u(15) 100 #define RESETS_RESET_RTC_ACCESS "RW" 101 // ----------------------------------------------------------------------------- 102 // Field : RESETS_RESET_PWM 103 // Description : None 104 #define RESETS_RESET_PWM_RESET _u(0x1) 105 #define RESETS_RESET_PWM_BITS _u(0x00004000) 106 #define RESETS_RESET_PWM_MSB _u(14) 107 #define RESETS_RESET_PWM_LSB _u(14) 108 #define RESETS_RESET_PWM_ACCESS "RW" 109 // ----------------------------------------------------------------------------- 110 // Field : RESETS_RESET_PLL_USB 111 // Description : None 112 #define RESETS_RESET_PLL_USB_RESET _u(0x1) 113 #define RESETS_RESET_PLL_USB_BITS _u(0x00002000) 114 #define RESETS_RESET_PLL_USB_MSB _u(13) 115 #define RESETS_RESET_PLL_USB_LSB _u(13) 116 #define RESETS_RESET_PLL_USB_ACCESS "RW" 117 // ----------------------------------------------------------------------------- 118 // Field : RESETS_RESET_PLL_SYS 119 // Description : None 120 #define RESETS_RESET_PLL_SYS_RESET _u(0x1) 121 #define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) 122 #define RESETS_RESET_PLL_SYS_MSB _u(12) 123 #define RESETS_RESET_PLL_SYS_LSB _u(12) 124 #define RESETS_RESET_PLL_SYS_ACCESS "RW" 125 // ----------------------------------------------------------------------------- 126 // Field : RESETS_RESET_PIO1 127 // Description : None 128 #define RESETS_RESET_PIO1_RESET _u(0x1) 129 #define RESETS_RESET_PIO1_BITS _u(0x00000800) 130 #define RESETS_RESET_PIO1_MSB _u(11) 131 #define RESETS_RESET_PIO1_LSB _u(11) 132 #define RESETS_RESET_PIO1_ACCESS "RW" 133 // ----------------------------------------------------------------------------- 134 // Field : RESETS_RESET_PIO0 135 // Description : None 136 #define RESETS_RESET_PIO0_RESET _u(0x1) 137 #define RESETS_RESET_PIO0_BITS _u(0x00000400) 138 #define RESETS_RESET_PIO0_MSB _u(10) 139 #define RESETS_RESET_PIO0_LSB _u(10) 140 #define RESETS_RESET_PIO0_ACCESS "RW" 141 // ----------------------------------------------------------------------------- 142 // Field : RESETS_RESET_PADS_QSPI 143 // Description : None 144 #define RESETS_RESET_PADS_QSPI_RESET _u(0x1) 145 #define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) 146 #define RESETS_RESET_PADS_QSPI_MSB _u(9) 147 #define RESETS_RESET_PADS_QSPI_LSB _u(9) 148 #define RESETS_RESET_PADS_QSPI_ACCESS "RW" 149 // ----------------------------------------------------------------------------- 150 // Field : RESETS_RESET_PADS_BANK0 151 // Description : None 152 #define RESETS_RESET_PADS_BANK0_RESET _u(0x1) 153 #define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) 154 #define RESETS_RESET_PADS_BANK0_MSB _u(8) 155 #define RESETS_RESET_PADS_BANK0_LSB _u(8) 156 #define RESETS_RESET_PADS_BANK0_ACCESS "RW" 157 // ----------------------------------------------------------------------------- 158 // Field : RESETS_RESET_JTAG 159 // Description : None 160 #define RESETS_RESET_JTAG_RESET _u(0x1) 161 #define RESETS_RESET_JTAG_BITS _u(0x00000080) 162 #define RESETS_RESET_JTAG_MSB _u(7) 163 #define RESETS_RESET_JTAG_LSB _u(7) 164 #define RESETS_RESET_JTAG_ACCESS "RW" 165 // ----------------------------------------------------------------------------- 166 // Field : RESETS_RESET_IO_QSPI 167 // Description : None 168 #define RESETS_RESET_IO_QSPI_RESET _u(0x1) 169 #define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) 170 #define RESETS_RESET_IO_QSPI_MSB _u(6) 171 #define RESETS_RESET_IO_QSPI_LSB _u(6) 172 #define RESETS_RESET_IO_QSPI_ACCESS "RW" 173 // ----------------------------------------------------------------------------- 174 // Field : RESETS_RESET_IO_BANK0 175 // Description : None 176 #define RESETS_RESET_IO_BANK0_RESET _u(0x1) 177 #define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) 178 #define RESETS_RESET_IO_BANK0_MSB _u(5) 179 #define RESETS_RESET_IO_BANK0_LSB _u(5) 180 #define RESETS_RESET_IO_BANK0_ACCESS "RW" 181 // ----------------------------------------------------------------------------- 182 // Field : RESETS_RESET_I2C1 183 // Description : None 184 #define RESETS_RESET_I2C1_RESET _u(0x1) 185 #define RESETS_RESET_I2C1_BITS _u(0x00000010) 186 #define RESETS_RESET_I2C1_MSB _u(4) 187 #define RESETS_RESET_I2C1_LSB _u(4) 188 #define RESETS_RESET_I2C1_ACCESS "RW" 189 // ----------------------------------------------------------------------------- 190 // Field : RESETS_RESET_I2C0 191 // Description : None 192 #define RESETS_RESET_I2C0_RESET _u(0x1) 193 #define RESETS_RESET_I2C0_BITS _u(0x00000008) 194 #define RESETS_RESET_I2C0_MSB _u(3) 195 #define RESETS_RESET_I2C0_LSB _u(3) 196 #define RESETS_RESET_I2C0_ACCESS "RW" 197 // ----------------------------------------------------------------------------- 198 // Field : RESETS_RESET_DMA 199 // Description : None 200 #define RESETS_RESET_DMA_RESET _u(0x1) 201 #define RESETS_RESET_DMA_BITS _u(0x00000004) 202 #define RESETS_RESET_DMA_MSB _u(2) 203 #define RESETS_RESET_DMA_LSB _u(2) 204 #define RESETS_RESET_DMA_ACCESS "RW" 205 // ----------------------------------------------------------------------------- 206 // Field : RESETS_RESET_BUSCTRL 207 // Description : None 208 #define RESETS_RESET_BUSCTRL_RESET _u(0x1) 209 #define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) 210 #define RESETS_RESET_BUSCTRL_MSB _u(1) 211 #define RESETS_RESET_BUSCTRL_LSB _u(1) 212 #define RESETS_RESET_BUSCTRL_ACCESS "RW" 213 // ----------------------------------------------------------------------------- 214 // Field : RESETS_RESET_ADC 215 // Description : None 216 #define RESETS_RESET_ADC_RESET _u(0x1) 217 #define RESETS_RESET_ADC_BITS _u(0x00000001) 218 #define RESETS_RESET_ADC_MSB _u(0) 219 #define RESETS_RESET_ADC_LSB _u(0) 220 #define RESETS_RESET_ADC_ACCESS "RW" 221 // ============================================================================= 222 // Register : RESETS_WDSEL 223 // Description : Watchdog select. If a bit is set then the watchdog will reset 224 // this peripheral when the watchdog fires. 225 #define RESETS_WDSEL_OFFSET _u(0x00000004) 226 #define RESETS_WDSEL_BITS _u(0x01ffffff) 227 #define RESETS_WDSEL_RESET _u(0x00000000) 228 // ----------------------------------------------------------------------------- 229 // Field : RESETS_WDSEL_USBCTRL 230 // Description : None 231 #define RESETS_WDSEL_USBCTRL_RESET _u(0x0) 232 #define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) 233 #define RESETS_WDSEL_USBCTRL_MSB _u(24) 234 #define RESETS_WDSEL_USBCTRL_LSB _u(24) 235 #define RESETS_WDSEL_USBCTRL_ACCESS "RW" 236 // ----------------------------------------------------------------------------- 237 // Field : RESETS_WDSEL_UART1 238 // Description : None 239 #define RESETS_WDSEL_UART1_RESET _u(0x0) 240 #define RESETS_WDSEL_UART1_BITS _u(0x00800000) 241 #define RESETS_WDSEL_UART1_MSB _u(23) 242 #define RESETS_WDSEL_UART1_LSB _u(23) 243 #define RESETS_WDSEL_UART1_ACCESS "RW" 244 // ----------------------------------------------------------------------------- 245 // Field : RESETS_WDSEL_UART0 246 // Description : None 247 #define RESETS_WDSEL_UART0_RESET _u(0x0) 248 #define RESETS_WDSEL_UART0_BITS _u(0x00400000) 249 #define RESETS_WDSEL_UART0_MSB _u(22) 250 #define RESETS_WDSEL_UART0_LSB _u(22) 251 #define RESETS_WDSEL_UART0_ACCESS "RW" 252 // ----------------------------------------------------------------------------- 253 // Field : RESETS_WDSEL_TIMER 254 // Description : None 255 #define RESETS_WDSEL_TIMER_RESET _u(0x0) 256 #define RESETS_WDSEL_TIMER_BITS _u(0x00200000) 257 #define RESETS_WDSEL_TIMER_MSB _u(21) 258 #define RESETS_WDSEL_TIMER_LSB _u(21) 259 #define RESETS_WDSEL_TIMER_ACCESS "RW" 260 // ----------------------------------------------------------------------------- 261 // Field : RESETS_WDSEL_TBMAN 262 // Description : None 263 #define RESETS_WDSEL_TBMAN_RESET _u(0x0) 264 #define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) 265 #define RESETS_WDSEL_TBMAN_MSB _u(20) 266 #define RESETS_WDSEL_TBMAN_LSB _u(20) 267 #define RESETS_WDSEL_TBMAN_ACCESS "RW" 268 // ----------------------------------------------------------------------------- 269 // Field : RESETS_WDSEL_SYSINFO 270 // Description : None 271 #define RESETS_WDSEL_SYSINFO_RESET _u(0x0) 272 #define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) 273 #define RESETS_WDSEL_SYSINFO_MSB _u(19) 274 #define RESETS_WDSEL_SYSINFO_LSB _u(19) 275 #define RESETS_WDSEL_SYSINFO_ACCESS "RW" 276 // ----------------------------------------------------------------------------- 277 // Field : RESETS_WDSEL_SYSCFG 278 // Description : None 279 #define RESETS_WDSEL_SYSCFG_RESET _u(0x0) 280 #define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) 281 #define RESETS_WDSEL_SYSCFG_MSB _u(18) 282 #define RESETS_WDSEL_SYSCFG_LSB _u(18) 283 #define RESETS_WDSEL_SYSCFG_ACCESS "RW" 284 // ----------------------------------------------------------------------------- 285 // Field : RESETS_WDSEL_SPI1 286 // Description : None 287 #define RESETS_WDSEL_SPI1_RESET _u(0x0) 288 #define RESETS_WDSEL_SPI1_BITS _u(0x00020000) 289 #define RESETS_WDSEL_SPI1_MSB _u(17) 290 #define RESETS_WDSEL_SPI1_LSB _u(17) 291 #define RESETS_WDSEL_SPI1_ACCESS "RW" 292 // ----------------------------------------------------------------------------- 293 // Field : RESETS_WDSEL_SPI0 294 // Description : None 295 #define RESETS_WDSEL_SPI0_RESET _u(0x0) 296 #define RESETS_WDSEL_SPI0_BITS _u(0x00010000) 297 #define RESETS_WDSEL_SPI0_MSB _u(16) 298 #define RESETS_WDSEL_SPI0_LSB _u(16) 299 #define RESETS_WDSEL_SPI0_ACCESS "RW" 300 // ----------------------------------------------------------------------------- 301 // Field : RESETS_WDSEL_RTC 302 // Description : None 303 #define RESETS_WDSEL_RTC_RESET _u(0x0) 304 #define RESETS_WDSEL_RTC_BITS _u(0x00008000) 305 #define RESETS_WDSEL_RTC_MSB _u(15) 306 #define RESETS_WDSEL_RTC_LSB _u(15) 307 #define RESETS_WDSEL_RTC_ACCESS "RW" 308 // ----------------------------------------------------------------------------- 309 // Field : RESETS_WDSEL_PWM 310 // Description : None 311 #define RESETS_WDSEL_PWM_RESET _u(0x0) 312 #define RESETS_WDSEL_PWM_BITS _u(0x00004000) 313 #define RESETS_WDSEL_PWM_MSB _u(14) 314 #define RESETS_WDSEL_PWM_LSB _u(14) 315 #define RESETS_WDSEL_PWM_ACCESS "RW" 316 // ----------------------------------------------------------------------------- 317 // Field : RESETS_WDSEL_PLL_USB 318 // Description : None 319 #define RESETS_WDSEL_PLL_USB_RESET _u(0x0) 320 #define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) 321 #define RESETS_WDSEL_PLL_USB_MSB _u(13) 322 #define RESETS_WDSEL_PLL_USB_LSB _u(13) 323 #define RESETS_WDSEL_PLL_USB_ACCESS "RW" 324 // ----------------------------------------------------------------------------- 325 // Field : RESETS_WDSEL_PLL_SYS 326 // Description : None 327 #define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) 328 #define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) 329 #define RESETS_WDSEL_PLL_SYS_MSB _u(12) 330 #define RESETS_WDSEL_PLL_SYS_LSB _u(12) 331 #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" 332 // ----------------------------------------------------------------------------- 333 // Field : RESETS_WDSEL_PIO1 334 // Description : None 335 #define RESETS_WDSEL_PIO1_RESET _u(0x0) 336 #define RESETS_WDSEL_PIO1_BITS _u(0x00000800) 337 #define RESETS_WDSEL_PIO1_MSB _u(11) 338 #define RESETS_WDSEL_PIO1_LSB _u(11) 339 #define RESETS_WDSEL_PIO1_ACCESS "RW" 340 // ----------------------------------------------------------------------------- 341 // Field : RESETS_WDSEL_PIO0 342 // Description : None 343 #define RESETS_WDSEL_PIO0_RESET _u(0x0) 344 #define RESETS_WDSEL_PIO0_BITS _u(0x00000400) 345 #define RESETS_WDSEL_PIO0_MSB _u(10) 346 #define RESETS_WDSEL_PIO0_LSB _u(10) 347 #define RESETS_WDSEL_PIO0_ACCESS "RW" 348 // ----------------------------------------------------------------------------- 349 // Field : RESETS_WDSEL_PADS_QSPI 350 // Description : None 351 #define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) 352 #define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) 353 #define RESETS_WDSEL_PADS_QSPI_MSB _u(9) 354 #define RESETS_WDSEL_PADS_QSPI_LSB _u(9) 355 #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" 356 // ----------------------------------------------------------------------------- 357 // Field : RESETS_WDSEL_PADS_BANK0 358 // Description : None 359 #define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) 360 #define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) 361 #define RESETS_WDSEL_PADS_BANK0_MSB _u(8) 362 #define RESETS_WDSEL_PADS_BANK0_LSB _u(8) 363 #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" 364 // ----------------------------------------------------------------------------- 365 // Field : RESETS_WDSEL_JTAG 366 // Description : None 367 #define RESETS_WDSEL_JTAG_RESET _u(0x0) 368 #define RESETS_WDSEL_JTAG_BITS _u(0x00000080) 369 #define RESETS_WDSEL_JTAG_MSB _u(7) 370 #define RESETS_WDSEL_JTAG_LSB _u(7) 371 #define RESETS_WDSEL_JTAG_ACCESS "RW" 372 // ----------------------------------------------------------------------------- 373 // Field : RESETS_WDSEL_IO_QSPI 374 // Description : None 375 #define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) 376 #define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) 377 #define RESETS_WDSEL_IO_QSPI_MSB _u(6) 378 #define RESETS_WDSEL_IO_QSPI_LSB _u(6) 379 #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" 380 // ----------------------------------------------------------------------------- 381 // Field : RESETS_WDSEL_IO_BANK0 382 // Description : None 383 #define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) 384 #define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) 385 #define RESETS_WDSEL_IO_BANK0_MSB _u(5) 386 #define RESETS_WDSEL_IO_BANK0_LSB _u(5) 387 #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" 388 // ----------------------------------------------------------------------------- 389 // Field : RESETS_WDSEL_I2C1 390 // Description : None 391 #define RESETS_WDSEL_I2C1_RESET _u(0x0) 392 #define RESETS_WDSEL_I2C1_BITS _u(0x00000010) 393 #define RESETS_WDSEL_I2C1_MSB _u(4) 394 #define RESETS_WDSEL_I2C1_LSB _u(4) 395 #define RESETS_WDSEL_I2C1_ACCESS "RW" 396 // ----------------------------------------------------------------------------- 397 // Field : RESETS_WDSEL_I2C0 398 // Description : None 399 #define RESETS_WDSEL_I2C0_RESET _u(0x0) 400 #define RESETS_WDSEL_I2C0_BITS _u(0x00000008) 401 #define RESETS_WDSEL_I2C0_MSB _u(3) 402 #define RESETS_WDSEL_I2C0_LSB _u(3) 403 #define RESETS_WDSEL_I2C0_ACCESS "RW" 404 // ----------------------------------------------------------------------------- 405 // Field : RESETS_WDSEL_DMA 406 // Description : None 407 #define RESETS_WDSEL_DMA_RESET _u(0x0) 408 #define RESETS_WDSEL_DMA_BITS _u(0x00000004) 409 #define RESETS_WDSEL_DMA_MSB _u(2) 410 #define RESETS_WDSEL_DMA_LSB _u(2) 411 #define RESETS_WDSEL_DMA_ACCESS "RW" 412 // ----------------------------------------------------------------------------- 413 // Field : RESETS_WDSEL_BUSCTRL 414 // Description : None 415 #define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) 416 #define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) 417 #define RESETS_WDSEL_BUSCTRL_MSB _u(1) 418 #define RESETS_WDSEL_BUSCTRL_LSB _u(1) 419 #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" 420 // ----------------------------------------------------------------------------- 421 // Field : RESETS_WDSEL_ADC 422 // Description : None 423 #define RESETS_WDSEL_ADC_RESET _u(0x0) 424 #define RESETS_WDSEL_ADC_BITS _u(0x00000001) 425 #define RESETS_WDSEL_ADC_MSB _u(0) 426 #define RESETS_WDSEL_ADC_LSB _u(0) 427 #define RESETS_WDSEL_ADC_ACCESS "RW" 428 // ============================================================================= 429 // Register : RESETS_RESET_DONE 430 // Description : Reset done. If a bit is set then a reset done signal has been 431 // returned by the peripheral. This indicates that the 432 // peripheral's registers are ready to be accessed. 433 #define RESETS_RESET_DONE_OFFSET _u(0x00000008) 434 #define RESETS_RESET_DONE_BITS _u(0x01ffffff) 435 #define RESETS_RESET_DONE_RESET _u(0x00000000) 436 // ----------------------------------------------------------------------------- 437 // Field : RESETS_RESET_DONE_USBCTRL 438 // Description : None 439 #define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) 440 #define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) 441 #define RESETS_RESET_DONE_USBCTRL_MSB _u(24) 442 #define RESETS_RESET_DONE_USBCTRL_LSB _u(24) 443 #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" 444 // ----------------------------------------------------------------------------- 445 // Field : RESETS_RESET_DONE_UART1 446 // Description : None 447 #define RESETS_RESET_DONE_UART1_RESET _u(0x0) 448 #define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) 449 #define RESETS_RESET_DONE_UART1_MSB _u(23) 450 #define RESETS_RESET_DONE_UART1_LSB _u(23) 451 #define RESETS_RESET_DONE_UART1_ACCESS "RO" 452 // ----------------------------------------------------------------------------- 453 // Field : RESETS_RESET_DONE_UART0 454 // Description : None 455 #define RESETS_RESET_DONE_UART0_RESET _u(0x0) 456 #define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) 457 #define RESETS_RESET_DONE_UART0_MSB _u(22) 458 #define RESETS_RESET_DONE_UART0_LSB _u(22) 459 #define RESETS_RESET_DONE_UART0_ACCESS "RO" 460 // ----------------------------------------------------------------------------- 461 // Field : RESETS_RESET_DONE_TIMER 462 // Description : None 463 #define RESETS_RESET_DONE_TIMER_RESET _u(0x0) 464 #define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) 465 #define RESETS_RESET_DONE_TIMER_MSB _u(21) 466 #define RESETS_RESET_DONE_TIMER_LSB _u(21) 467 #define RESETS_RESET_DONE_TIMER_ACCESS "RO" 468 // ----------------------------------------------------------------------------- 469 // Field : RESETS_RESET_DONE_TBMAN 470 // Description : None 471 #define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) 472 #define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) 473 #define RESETS_RESET_DONE_TBMAN_MSB _u(20) 474 #define RESETS_RESET_DONE_TBMAN_LSB _u(20) 475 #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" 476 // ----------------------------------------------------------------------------- 477 // Field : RESETS_RESET_DONE_SYSINFO 478 // Description : None 479 #define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) 480 #define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) 481 #define RESETS_RESET_DONE_SYSINFO_MSB _u(19) 482 #define RESETS_RESET_DONE_SYSINFO_LSB _u(19) 483 #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" 484 // ----------------------------------------------------------------------------- 485 // Field : RESETS_RESET_DONE_SYSCFG 486 // Description : None 487 #define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) 488 #define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) 489 #define RESETS_RESET_DONE_SYSCFG_MSB _u(18) 490 #define RESETS_RESET_DONE_SYSCFG_LSB _u(18) 491 #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" 492 // ----------------------------------------------------------------------------- 493 // Field : RESETS_RESET_DONE_SPI1 494 // Description : None 495 #define RESETS_RESET_DONE_SPI1_RESET _u(0x0) 496 #define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) 497 #define RESETS_RESET_DONE_SPI1_MSB _u(17) 498 #define RESETS_RESET_DONE_SPI1_LSB _u(17) 499 #define RESETS_RESET_DONE_SPI1_ACCESS "RO" 500 // ----------------------------------------------------------------------------- 501 // Field : RESETS_RESET_DONE_SPI0 502 // Description : None 503 #define RESETS_RESET_DONE_SPI0_RESET _u(0x0) 504 #define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) 505 #define RESETS_RESET_DONE_SPI0_MSB _u(16) 506 #define RESETS_RESET_DONE_SPI0_LSB _u(16) 507 #define RESETS_RESET_DONE_SPI0_ACCESS "RO" 508 // ----------------------------------------------------------------------------- 509 // Field : RESETS_RESET_DONE_RTC 510 // Description : None 511 #define RESETS_RESET_DONE_RTC_RESET _u(0x0) 512 #define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) 513 #define RESETS_RESET_DONE_RTC_MSB _u(15) 514 #define RESETS_RESET_DONE_RTC_LSB _u(15) 515 #define RESETS_RESET_DONE_RTC_ACCESS "RO" 516 // ----------------------------------------------------------------------------- 517 // Field : RESETS_RESET_DONE_PWM 518 // Description : None 519 #define RESETS_RESET_DONE_PWM_RESET _u(0x0) 520 #define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) 521 #define RESETS_RESET_DONE_PWM_MSB _u(14) 522 #define RESETS_RESET_DONE_PWM_LSB _u(14) 523 #define RESETS_RESET_DONE_PWM_ACCESS "RO" 524 // ----------------------------------------------------------------------------- 525 // Field : RESETS_RESET_DONE_PLL_USB 526 // Description : None 527 #define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) 528 #define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) 529 #define RESETS_RESET_DONE_PLL_USB_MSB _u(13) 530 #define RESETS_RESET_DONE_PLL_USB_LSB _u(13) 531 #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" 532 // ----------------------------------------------------------------------------- 533 // Field : RESETS_RESET_DONE_PLL_SYS 534 // Description : None 535 #define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) 536 #define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) 537 #define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) 538 #define RESETS_RESET_DONE_PLL_SYS_LSB _u(12) 539 #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" 540 // ----------------------------------------------------------------------------- 541 // Field : RESETS_RESET_DONE_PIO1 542 // Description : None 543 #define RESETS_RESET_DONE_PIO1_RESET _u(0x0) 544 #define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) 545 #define RESETS_RESET_DONE_PIO1_MSB _u(11) 546 #define RESETS_RESET_DONE_PIO1_LSB _u(11) 547 #define RESETS_RESET_DONE_PIO1_ACCESS "RO" 548 // ----------------------------------------------------------------------------- 549 // Field : RESETS_RESET_DONE_PIO0 550 // Description : None 551 #define RESETS_RESET_DONE_PIO0_RESET _u(0x0) 552 #define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) 553 #define RESETS_RESET_DONE_PIO0_MSB _u(10) 554 #define RESETS_RESET_DONE_PIO0_LSB _u(10) 555 #define RESETS_RESET_DONE_PIO0_ACCESS "RO" 556 // ----------------------------------------------------------------------------- 557 // Field : RESETS_RESET_DONE_PADS_QSPI 558 // Description : None 559 #define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) 560 #define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) 561 #define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) 562 #define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9) 563 #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" 564 // ----------------------------------------------------------------------------- 565 // Field : RESETS_RESET_DONE_PADS_BANK0 566 // Description : None 567 #define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) 568 #define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) 569 #define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) 570 #define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8) 571 #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" 572 // ----------------------------------------------------------------------------- 573 // Field : RESETS_RESET_DONE_JTAG 574 // Description : None 575 #define RESETS_RESET_DONE_JTAG_RESET _u(0x0) 576 #define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) 577 #define RESETS_RESET_DONE_JTAG_MSB _u(7) 578 #define RESETS_RESET_DONE_JTAG_LSB _u(7) 579 #define RESETS_RESET_DONE_JTAG_ACCESS "RO" 580 // ----------------------------------------------------------------------------- 581 // Field : RESETS_RESET_DONE_IO_QSPI 582 // Description : None 583 #define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) 584 #define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) 585 #define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) 586 #define RESETS_RESET_DONE_IO_QSPI_LSB _u(6) 587 #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" 588 // ----------------------------------------------------------------------------- 589 // Field : RESETS_RESET_DONE_IO_BANK0 590 // Description : None 591 #define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) 592 #define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) 593 #define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) 594 #define RESETS_RESET_DONE_IO_BANK0_LSB _u(5) 595 #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" 596 // ----------------------------------------------------------------------------- 597 // Field : RESETS_RESET_DONE_I2C1 598 // Description : None 599 #define RESETS_RESET_DONE_I2C1_RESET _u(0x0) 600 #define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) 601 #define RESETS_RESET_DONE_I2C1_MSB _u(4) 602 #define RESETS_RESET_DONE_I2C1_LSB _u(4) 603 #define RESETS_RESET_DONE_I2C1_ACCESS "RO" 604 // ----------------------------------------------------------------------------- 605 // Field : RESETS_RESET_DONE_I2C0 606 // Description : None 607 #define RESETS_RESET_DONE_I2C0_RESET _u(0x0) 608 #define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) 609 #define RESETS_RESET_DONE_I2C0_MSB _u(3) 610 #define RESETS_RESET_DONE_I2C0_LSB _u(3) 611 #define RESETS_RESET_DONE_I2C0_ACCESS "RO" 612 // ----------------------------------------------------------------------------- 613 // Field : RESETS_RESET_DONE_DMA 614 // Description : None 615 #define RESETS_RESET_DONE_DMA_RESET _u(0x0) 616 #define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) 617 #define RESETS_RESET_DONE_DMA_MSB _u(2) 618 #define RESETS_RESET_DONE_DMA_LSB _u(2) 619 #define RESETS_RESET_DONE_DMA_ACCESS "RO" 620 // ----------------------------------------------------------------------------- 621 // Field : RESETS_RESET_DONE_BUSCTRL 622 // Description : None 623 #define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) 624 #define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) 625 #define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) 626 #define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) 627 #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" 628 // ----------------------------------------------------------------------------- 629 // Field : RESETS_RESET_DONE_ADC 630 // Description : None 631 #define RESETS_RESET_DONE_ADC_RESET _u(0x0) 632 #define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) 633 #define RESETS_RESET_DONE_ADC_MSB _u(0) 634 #define RESETS_RESET_DONE_ADC_LSB _u(0) 635 #define RESETS_RESET_DONE_ADC_ACCESS "RO" 636 // ============================================================================= 637 #endif // HARDWARE_REGS_RESETS_DEFINED 638
