1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : RTC 8 // Version : 1 9 // Bus type : apb 10 // Description : Register block to control RTC 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_RTC_DEFINED 13 #define HARDWARE_REGS_RTC_DEFINED 14 // ============================================================================= 15 // Register : RTC_CLKDIV_M1 16 // Description : Divider minus 1 for the 1 second counter. Safe to change the 17 // value when RTC is not enabled. 18 #define RTC_CLKDIV_M1_OFFSET _u(0x00000000) 19 #define RTC_CLKDIV_M1_BITS _u(0x0000ffff) 20 #define RTC_CLKDIV_M1_RESET _u(0x00000000) 21 #define RTC_CLKDIV_M1_MSB _u(15) 22 #define RTC_CLKDIV_M1_LSB _u(0) 23 #define RTC_CLKDIV_M1_ACCESS "RW" 24 // ============================================================================= 25 // Register : RTC_SETUP_0 26 // Description : RTC setup register 0 27 #define RTC_SETUP_0_OFFSET _u(0x00000004) 28 #define RTC_SETUP_0_BITS _u(0x00ffff1f) 29 #define RTC_SETUP_0_RESET _u(0x00000000) 30 // ----------------------------------------------------------------------------- 31 // Field : RTC_SETUP_0_YEAR 32 // Description : Year 33 #define RTC_SETUP_0_YEAR_RESET _u(0x000) 34 #define RTC_SETUP_0_YEAR_BITS _u(0x00fff000) 35 #define RTC_SETUP_0_YEAR_MSB _u(23) 36 #define RTC_SETUP_0_YEAR_LSB _u(12) 37 #define RTC_SETUP_0_YEAR_ACCESS "RW" 38 // ----------------------------------------------------------------------------- 39 // Field : RTC_SETUP_0_MONTH 40 // Description : Month (1..12) 41 #define RTC_SETUP_0_MONTH_RESET _u(0x0) 42 #define RTC_SETUP_0_MONTH_BITS _u(0x00000f00) 43 #define RTC_SETUP_0_MONTH_MSB _u(11) 44 #define RTC_SETUP_0_MONTH_LSB _u(8) 45 #define RTC_SETUP_0_MONTH_ACCESS "RW" 46 // ----------------------------------------------------------------------------- 47 // Field : RTC_SETUP_0_DAY 48 // Description : Day of the month (1..31) 49 #define RTC_SETUP_0_DAY_RESET _u(0x00) 50 #define RTC_SETUP_0_DAY_BITS _u(0x0000001f) 51 #define RTC_SETUP_0_DAY_MSB _u(4) 52 #define RTC_SETUP_0_DAY_LSB _u(0) 53 #define RTC_SETUP_0_DAY_ACCESS "RW" 54 // ============================================================================= 55 // Register : RTC_SETUP_1 56 // Description : RTC setup register 1 57 #define RTC_SETUP_1_OFFSET _u(0x00000008) 58 #define RTC_SETUP_1_BITS _u(0x071f3f3f) 59 #define RTC_SETUP_1_RESET _u(0x00000000) 60 // ----------------------------------------------------------------------------- 61 // Field : RTC_SETUP_1_DOTW 62 // Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 63 #define RTC_SETUP_1_DOTW_RESET _u(0x0) 64 #define RTC_SETUP_1_DOTW_BITS _u(0x07000000) 65 #define RTC_SETUP_1_DOTW_MSB _u(26) 66 #define RTC_SETUP_1_DOTW_LSB _u(24) 67 #define RTC_SETUP_1_DOTW_ACCESS "RW" 68 // ----------------------------------------------------------------------------- 69 // Field : RTC_SETUP_1_HOUR 70 // Description : Hours 71 #define RTC_SETUP_1_HOUR_RESET _u(0x00) 72 #define RTC_SETUP_1_HOUR_BITS _u(0x001f0000) 73 #define RTC_SETUP_1_HOUR_MSB _u(20) 74 #define RTC_SETUP_1_HOUR_LSB _u(16) 75 #define RTC_SETUP_1_HOUR_ACCESS "RW" 76 // ----------------------------------------------------------------------------- 77 // Field : RTC_SETUP_1_MIN 78 // Description : Minutes 79 #define RTC_SETUP_1_MIN_RESET _u(0x00) 80 #define RTC_SETUP_1_MIN_BITS _u(0x00003f00) 81 #define RTC_SETUP_1_MIN_MSB _u(13) 82 #define RTC_SETUP_1_MIN_LSB _u(8) 83 #define RTC_SETUP_1_MIN_ACCESS "RW" 84 // ----------------------------------------------------------------------------- 85 // Field : RTC_SETUP_1_SEC 86 // Description : Seconds 87 #define RTC_SETUP_1_SEC_RESET _u(0x00) 88 #define RTC_SETUP_1_SEC_BITS _u(0x0000003f) 89 #define RTC_SETUP_1_SEC_MSB _u(5) 90 #define RTC_SETUP_1_SEC_LSB _u(0) 91 #define RTC_SETUP_1_SEC_ACCESS "RW" 92 // ============================================================================= 93 // Register : RTC_CTRL 94 // Description : RTC Control and status 95 #define RTC_CTRL_OFFSET _u(0x0000000c) 96 #define RTC_CTRL_BITS _u(0x00000113) 97 #define RTC_CTRL_RESET _u(0x00000000) 98 // ----------------------------------------------------------------------------- 99 // Field : RTC_CTRL_FORCE_NOTLEAPYEAR 100 // Description : If set, leapyear is forced off. 101 // Useful for years divisible by 100 but not by 400 102 #define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0) 103 #define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100) 104 #define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8) 105 #define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8) 106 #define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" 107 // ----------------------------------------------------------------------------- 108 // Field : RTC_CTRL_LOAD 109 // Description : Load RTC 110 #define RTC_CTRL_LOAD_RESET _u(0x0) 111 #define RTC_CTRL_LOAD_BITS _u(0x00000010) 112 #define RTC_CTRL_LOAD_MSB _u(4) 113 #define RTC_CTRL_LOAD_LSB _u(4) 114 #define RTC_CTRL_LOAD_ACCESS "SC" 115 // ----------------------------------------------------------------------------- 116 // Field : RTC_CTRL_RTC_ACTIVE 117 // Description : RTC enabled (running) 118 #define RTC_CTRL_RTC_ACTIVE_RESET "-" 119 #define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002) 120 #define RTC_CTRL_RTC_ACTIVE_MSB _u(1) 121 #define RTC_CTRL_RTC_ACTIVE_LSB _u(1) 122 #define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" 123 // ----------------------------------------------------------------------------- 124 // Field : RTC_CTRL_RTC_ENABLE 125 // Description : Enable RTC 126 #define RTC_CTRL_RTC_ENABLE_RESET _u(0x0) 127 #define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001) 128 #define RTC_CTRL_RTC_ENABLE_MSB _u(0) 129 #define RTC_CTRL_RTC_ENABLE_LSB _u(0) 130 #define RTC_CTRL_RTC_ENABLE_ACCESS "RW" 131 // ============================================================================= 132 // Register : RTC_IRQ_SETUP_0 133 // Description : Interrupt setup register 0 134 #define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010) 135 #define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f) 136 #define RTC_IRQ_SETUP_0_RESET _u(0x00000000) 137 // ----------------------------------------------------------------------------- 138 // Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE 139 // Description : None 140 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" 141 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) 142 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) 143 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29) 144 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" 145 // ----------------------------------------------------------------------------- 146 // Field : RTC_IRQ_SETUP_0_MATCH_ENA 147 // Description : Global match enable. Don't change any other value while this 148 // one is enabled 149 #define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0) 150 #define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000) 151 #define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28) 152 #define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28) 153 #define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" 154 // ----------------------------------------------------------------------------- 155 // Field : RTC_IRQ_SETUP_0_YEAR_ENA 156 // Description : Enable year matching 157 #define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0) 158 #define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000) 159 #define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26) 160 #define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26) 161 #define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : RTC_IRQ_SETUP_0_MONTH_ENA 164 // Description : Enable month matching 165 #define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0) 166 #define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000) 167 #define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25) 168 #define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25) 169 #define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" 170 // ----------------------------------------------------------------------------- 171 // Field : RTC_IRQ_SETUP_0_DAY_ENA 172 // Description : Enable day matching 173 #define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0) 174 #define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000) 175 #define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24) 176 #define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24) 177 #define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" 178 // ----------------------------------------------------------------------------- 179 // Field : RTC_IRQ_SETUP_0_YEAR 180 // Description : Year 181 #define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000) 182 #define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000) 183 #define RTC_IRQ_SETUP_0_YEAR_MSB _u(23) 184 #define RTC_IRQ_SETUP_0_YEAR_LSB _u(12) 185 #define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" 186 // ----------------------------------------------------------------------------- 187 // Field : RTC_IRQ_SETUP_0_MONTH 188 // Description : Month (1..12) 189 #define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0) 190 #define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00) 191 #define RTC_IRQ_SETUP_0_MONTH_MSB _u(11) 192 #define RTC_IRQ_SETUP_0_MONTH_LSB _u(8) 193 #define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" 194 // ----------------------------------------------------------------------------- 195 // Field : RTC_IRQ_SETUP_0_DAY 196 // Description : Day of the month (1..31) 197 #define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00) 198 #define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f) 199 #define RTC_IRQ_SETUP_0_DAY_MSB _u(4) 200 #define RTC_IRQ_SETUP_0_DAY_LSB _u(0) 201 #define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" 202 // ============================================================================= 203 // Register : RTC_IRQ_SETUP_1 204 // Description : Interrupt setup register 1 205 #define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014) 206 #define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f) 207 #define RTC_IRQ_SETUP_1_RESET _u(0x00000000) 208 // ----------------------------------------------------------------------------- 209 // Field : RTC_IRQ_SETUP_1_DOTW_ENA 210 // Description : Enable day of the week matching 211 #define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0) 212 #define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000) 213 #define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31) 214 #define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31) 215 #define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" 216 // ----------------------------------------------------------------------------- 217 // Field : RTC_IRQ_SETUP_1_HOUR_ENA 218 // Description : Enable hour matching 219 #define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0) 220 #define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000) 221 #define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30) 222 #define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30) 223 #define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" 224 // ----------------------------------------------------------------------------- 225 // Field : RTC_IRQ_SETUP_1_MIN_ENA 226 // Description : Enable minute matching 227 #define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0) 228 #define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000) 229 #define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29) 230 #define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29) 231 #define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" 232 // ----------------------------------------------------------------------------- 233 // Field : RTC_IRQ_SETUP_1_SEC_ENA 234 // Description : Enable second matching 235 #define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0) 236 #define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000) 237 #define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28) 238 #define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28) 239 #define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" 240 // ----------------------------------------------------------------------------- 241 // Field : RTC_IRQ_SETUP_1_DOTW 242 // Description : Day of the week 243 #define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0) 244 #define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000) 245 #define RTC_IRQ_SETUP_1_DOTW_MSB _u(26) 246 #define RTC_IRQ_SETUP_1_DOTW_LSB _u(24) 247 #define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" 248 // ----------------------------------------------------------------------------- 249 // Field : RTC_IRQ_SETUP_1_HOUR 250 // Description : Hours 251 #define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00) 252 #define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000) 253 #define RTC_IRQ_SETUP_1_HOUR_MSB _u(20) 254 #define RTC_IRQ_SETUP_1_HOUR_LSB _u(16) 255 #define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" 256 // ----------------------------------------------------------------------------- 257 // Field : RTC_IRQ_SETUP_1_MIN 258 // Description : Minutes 259 #define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00) 260 #define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00) 261 #define RTC_IRQ_SETUP_1_MIN_MSB _u(13) 262 #define RTC_IRQ_SETUP_1_MIN_LSB _u(8) 263 #define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" 264 // ----------------------------------------------------------------------------- 265 // Field : RTC_IRQ_SETUP_1_SEC 266 // Description : Seconds 267 #define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00) 268 #define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f) 269 #define RTC_IRQ_SETUP_1_SEC_MSB _u(5) 270 #define RTC_IRQ_SETUP_1_SEC_LSB _u(0) 271 #define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" 272 // ============================================================================= 273 // Register : RTC_RTC_1 274 // Description : RTC register 1. 275 #define RTC_RTC_1_OFFSET _u(0x00000018) 276 #define RTC_RTC_1_BITS _u(0x00ffff1f) 277 #define RTC_RTC_1_RESET _u(0x00000000) 278 // ----------------------------------------------------------------------------- 279 // Field : RTC_RTC_1_YEAR 280 // Description : Year 281 #define RTC_RTC_1_YEAR_RESET "-" 282 #define RTC_RTC_1_YEAR_BITS _u(0x00fff000) 283 #define RTC_RTC_1_YEAR_MSB _u(23) 284 #define RTC_RTC_1_YEAR_LSB _u(12) 285 #define RTC_RTC_1_YEAR_ACCESS "RO" 286 // ----------------------------------------------------------------------------- 287 // Field : RTC_RTC_1_MONTH 288 // Description : Month (1..12) 289 #define RTC_RTC_1_MONTH_RESET "-" 290 #define RTC_RTC_1_MONTH_BITS _u(0x00000f00) 291 #define RTC_RTC_1_MONTH_MSB _u(11) 292 #define RTC_RTC_1_MONTH_LSB _u(8) 293 #define RTC_RTC_1_MONTH_ACCESS "RO" 294 // ----------------------------------------------------------------------------- 295 // Field : RTC_RTC_1_DAY 296 // Description : Day of the month (1..31) 297 #define RTC_RTC_1_DAY_RESET "-" 298 #define RTC_RTC_1_DAY_BITS _u(0x0000001f) 299 #define RTC_RTC_1_DAY_MSB _u(4) 300 #define RTC_RTC_1_DAY_LSB _u(0) 301 #define RTC_RTC_1_DAY_ACCESS "RO" 302 // ============================================================================= 303 // Register : RTC_RTC_0 304 // Description : RTC register 0 305 // Read this before RTC 1! 306 #define RTC_RTC_0_OFFSET _u(0x0000001c) 307 #define RTC_RTC_0_BITS _u(0x071f3f3f) 308 #define RTC_RTC_0_RESET _u(0x00000000) 309 // ----------------------------------------------------------------------------- 310 // Field : RTC_RTC_0_DOTW 311 // Description : Day of the week 312 #define RTC_RTC_0_DOTW_RESET "-" 313 #define RTC_RTC_0_DOTW_BITS _u(0x07000000) 314 #define RTC_RTC_0_DOTW_MSB _u(26) 315 #define RTC_RTC_0_DOTW_LSB _u(24) 316 #define RTC_RTC_0_DOTW_ACCESS "RF" 317 // ----------------------------------------------------------------------------- 318 // Field : RTC_RTC_0_HOUR 319 // Description : Hours 320 #define RTC_RTC_0_HOUR_RESET "-" 321 #define RTC_RTC_0_HOUR_BITS _u(0x001f0000) 322 #define RTC_RTC_0_HOUR_MSB _u(20) 323 #define RTC_RTC_0_HOUR_LSB _u(16) 324 #define RTC_RTC_0_HOUR_ACCESS "RF" 325 // ----------------------------------------------------------------------------- 326 // Field : RTC_RTC_0_MIN 327 // Description : Minutes 328 #define RTC_RTC_0_MIN_RESET "-" 329 #define RTC_RTC_0_MIN_BITS _u(0x00003f00) 330 #define RTC_RTC_0_MIN_MSB _u(13) 331 #define RTC_RTC_0_MIN_LSB _u(8) 332 #define RTC_RTC_0_MIN_ACCESS "RF" 333 // ----------------------------------------------------------------------------- 334 // Field : RTC_RTC_0_SEC 335 // Description : Seconds 336 #define RTC_RTC_0_SEC_RESET "-" 337 #define RTC_RTC_0_SEC_BITS _u(0x0000003f) 338 #define RTC_RTC_0_SEC_MSB _u(5) 339 #define RTC_RTC_0_SEC_LSB _u(0) 340 #define RTC_RTC_0_SEC_ACCESS "RF" 341 // ============================================================================= 342 // Register : RTC_INTR 343 // Description : Raw Interrupts 344 #define RTC_INTR_OFFSET _u(0x00000020) 345 #define RTC_INTR_BITS _u(0x00000001) 346 #define RTC_INTR_RESET _u(0x00000000) 347 // ----------------------------------------------------------------------------- 348 // Field : RTC_INTR_RTC 349 // Description : None 350 #define RTC_INTR_RTC_RESET _u(0x0) 351 #define RTC_INTR_RTC_BITS _u(0x00000001) 352 #define RTC_INTR_RTC_MSB _u(0) 353 #define RTC_INTR_RTC_LSB _u(0) 354 #define RTC_INTR_RTC_ACCESS "RO" 355 // ============================================================================= 356 // Register : RTC_INTE 357 // Description : Interrupt Enable 358 #define RTC_INTE_OFFSET _u(0x00000024) 359 #define RTC_INTE_BITS _u(0x00000001) 360 #define RTC_INTE_RESET _u(0x00000000) 361 // ----------------------------------------------------------------------------- 362 // Field : RTC_INTE_RTC 363 // Description : None 364 #define RTC_INTE_RTC_RESET _u(0x0) 365 #define RTC_INTE_RTC_BITS _u(0x00000001) 366 #define RTC_INTE_RTC_MSB _u(0) 367 #define RTC_INTE_RTC_LSB _u(0) 368 #define RTC_INTE_RTC_ACCESS "RW" 369 // ============================================================================= 370 // Register : RTC_INTF 371 // Description : Interrupt Force 372 #define RTC_INTF_OFFSET _u(0x00000028) 373 #define RTC_INTF_BITS _u(0x00000001) 374 #define RTC_INTF_RESET _u(0x00000000) 375 // ----------------------------------------------------------------------------- 376 // Field : RTC_INTF_RTC 377 // Description : None 378 #define RTC_INTF_RTC_RESET _u(0x0) 379 #define RTC_INTF_RTC_BITS _u(0x00000001) 380 #define RTC_INTF_RTC_MSB _u(0) 381 #define RTC_INTF_RTC_LSB _u(0) 382 #define RTC_INTF_RTC_ACCESS "RW" 383 // ============================================================================= 384 // Register : RTC_INTS 385 // Description : Interrupt status after masking & forcing 386 #define RTC_INTS_OFFSET _u(0x0000002c) 387 #define RTC_INTS_BITS _u(0x00000001) 388 #define RTC_INTS_RESET _u(0x00000000) 389 // ----------------------------------------------------------------------------- 390 // Field : RTC_INTS_RTC 391 // Description : None 392 #define RTC_INTS_RTC_RESET _u(0x0) 393 #define RTC_INTS_RTC_BITS _u(0x00000001) 394 #define RTC_INTS_RTC_MSB _u(0) 395 #define RTC_INTS_RTC_LSB _u(0) 396 #define RTC_INTS_RTC_ACCESS "RO" 397 // ============================================================================= 398 #endif // HARDWARE_REGS_RTC_DEFINED 399
