1 /**
2  * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 // =============================================================================
7 // Register block : PIO
8 // Version        : 1
9 // Bus type       : ahbl
10 // Description    : Programmable IO block
11 // =============================================================================
12 #ifndef HARDWARE_REGS_PIO_DEFINED
13 #define HARDWARE_REGS_PIO_DEFINED
14 // =============================================================================
15 // Register    : PIO_CTRL
16 // Description : PIO control register
17 #define PIO_CTRL_OFFSET _u(0x00000000)
18 #define PIO_CTRL_BITS   _u(0x00000fff)
19 #define PIO_CTRL_RESET  _u(0x00000000)
20 // -----------------------------------------------------------------------------
21 // Field       : PIO_CTRL_CLKDIV_RESTART
22 // Description : Restart a state machine's clock divider from an initial phase
23 //               of 0. Clock dividers are free-running, so once started, their
24 //               output (including fractional jitter) is completely determined
25 //               by the integer/fractional divisor configured in SMx_CLKDIV.
26 //               This means that, if multiple clock dividers with the same
27 //               divisor are restarted simultaneously, by writing multiple 1
28 //               bits to this field, the execution clocks of those state
29 //               machines will run in precise lockstep.
30 //
31 //               Note that setting/clearing SM_ENABLE does not stop the clock
32 //               divider from running, so once multiple state machines' clocks
33 //               are synchronised, it is safe to disable/reenable a state
34 //               machine, whilst keeping the clock dividers in sync.
35 //
36 //               Note also that CLKDIV_RESTART can be written to whilst the
37 //               state machine is running, and this is useful to resynchronise
38 //               clock dividers after the divisors (SMx_CLKDIV) have been
39 //               changed on-the-fly.
40 #define PIO_CTRL_CLKDIV_RESTART_RESET  _u(0x0)
41 #define PIO_CTRL_CLKDIV_RESTART_BITS   _u(0x00000f00)
42 #define PIO_CTRL_CLKDIV_RESTART_MSB    _u(11)
43 #define PIO_CTRL_CLKDIV_RESTART_LSB    _u(8)
44 #define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC"
45 // -----------------------------------------------------------------------------
46 // Field       : PIO_CTRL_SM_RESTART
47 // Description : Write 1 to instantly clear internal SM state which may be
48 //               otherwise difficult to access and will affect future execution.
49 //
50 //               Specifically, the following are cleared: input and output shift
51 //               counters; the contents of the input shift register; the delay
52 //               counter; the waiting-on-IRQ state; any stalled instruction
53 //               written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
54 //               asserted due to OUT_STICKY.
55 //
56 //               The program counter, the contents of the output shift register
57 //               and the X/Y scratch registers are not affected.
58 #define PIO_CTRL_SM_RESTART_RESET  _u(0x0)
59 #define PIO_CTRL_SM_RESTART_BITS   _u(0x000000f0)
60 #define PIO_CTRL_SM_RESTART_MSB    _u(7)
61 #define PIO_CTRL_SM_RESTART_LSB    _u(4)
62 #define PIO_CTRL_SM_RESTART_ACCESS "SC"
63 // -----------------------------------------------------------------------------
64 // Field       : PIO_CTRL_SM_ENABLE
65 // Description : Enable/disable each of the four state machines by writing 1/0
66 //               to each of these four bits. When disabled, a state machine will
67 //               cease executing instructions, except those written directly to
68 //               SMx_INSTR by the system. Multiple bits can be set/cleared at
69 //               once to run/halt multiple state machines simultaneously.
70 #define PIO_CTRL_SM_ENABLE_RESET  _u(0x0)
71 #define PIO_CTRL_SM_ENABLE_BITS   _u(0x0000000f)
72 #define PIO_CTRL_SM_ENABLE_MSB    _u(3)
73 #define PIO_CTRL_SM_ENABLE_LSB    _u(0)
74 #define PIO_CTRL_SM_ENABLE_ACCESS "RW"
75 // =============================================================================
76 // Register    : PIO_FSTAT
77 // Description : FIFO status register
78 #define PIO_FSTAT_OFFSET _u(0x00000004)
79 #define PIO_FSTAT_BITS   _u(0x0f0f0f0f)
80 #define PIO_FSTAT_RESET  _u(0x0f000f00)
81 // -----------------------------------------------------------------------------
82 // Field       : PIO_FSTAT_TXEMPTY
83 // Description : State machine TX FIFO is empty
84 #define PIO_FSTAT_TXEMPTY_RESET  _u(0xf)
85 #define PIO_FSTAT_TXEMPTY_BITS   _u(0x0f000000)
86 #define PIO_FSTAT_TXEMPTY_MSB    _u(27)
87 #define PIO_FSTAT_TXEMPTY_LSB    _u(24)
88 #define PIO_FSTAT_TXEMPTY_ACCESS "RO"
89 // -----------------------------------------------------------------------------
90 // Field       : PIO_FSTAT_TXFULL
91 // Description : State machine TX FIFO is full
92 #define PIO_FSTAT_TXFULL_RESET  _u(0x0)
93 #define PIO_FSTAT_TXFULL_BITS   _u(0x000f0000)
94 #define PIO_FSTAT_TXFULL_MSB    _u(19)
95 #define PIO_FSTAT_TXFULL_LSB    _u(16)
96 #define PIO_FSTAT_TXFULL_ACCESS "RO"
97 // -----------------------------------------------------------------------------
98 // Field       : PIO_FSTAT_RXEMPTY
99 // Description : State machine RX FIFO is empty
100 #define PIO_FSTAT_RXEMPTY_RESET  _u(0xf)
101 #define PIO_FSTAT_RXEMPTY_BITS   _u(0x00000f00)
102 #define PIO_FSTAT_RXEMPTY_MSB    _u(11)
103 #define PIO_FSTAT_RXEMPTY_LSB    _u(8)
104 #define PIO_FSTAT_RXEMPTY_ACCESS "RO"
105 // -----------------------------------------------------------------------------
106 // Field       : PIO_FSTAT_RXFULL
107 // Description : State machine RX FIFO is full
108 #define PIO_FSTAT_RXFULL_RESET  _u(0x0)
109 #define PIO_FSTAT_RXFULL_BITS   _u(0x0000000f)
110 #define PIO_FSTAT_RXFULL_MSB    _u(3)
111 #define PIO_FSTAT_RXFULL_LSB    _u(0)
112 #define PIO_FSTAT_RXFULL_ACCESS "RO"
113 // =============================================================================
114 // Register    : PIO_FDEBUG
115 // Description : FIFO debug register
116 #define PIO_FDEBUG_OFFSET _u(0x00000008)
117 #define PIO_FDEBUG_BITS   _u(0x0f0f0f0f)
118 #define PIO_FDEBUG_RESET  _u(0x00000000)
119 // -----------------------------------------------------------------------------
120 // Field       : PIO_FDEBUG_TXSTALL
121 // Description : State machine has stalled on empty TX FIFO during a blocking
122 //               PULL, or an OUT with autopull enabled. Write 1 to clear.
123 #define PIO_FDEBUG_TXSTALL_RESET  _u(0x0)
124 #define PIO_FDEBUG_TXSTALL_BITS   _u(0x0f000000)
125 #define PIO_FDEBUG_TXSTALL_MSB    _u(27)
126 #define PIO_FDEBUG_TXSTALL_LSB    _u(24)
127 #define PIO_FDEBUG_TXSTALL_ACCESS "WC"
128 // -----------------------------------------------------------------------------
129 // Field       : PIO_FDEBUG_TXOVER
130 // Description : TX FIFO overflow (i.e. write-on-full by the system) has
131 //               occurred. Write 1 to clear. Note that write-on-full does not
132 //               alter the state or contents of the FIFO in any way, but the
133 //               data that the system attempted to write is dropped, so if this
134 //               flag is set, your software has quite likely dropped some data
135 //               on the floor.
136 #define PIO_FDEBUG_TXOVER_RESET  _u(0x0)
137 #define PIO_FDEBUG_TXOVER_BITS   _u(0x000f0000)
138 #define PIO_FDEBUG_TXOVER_MSB    _u(19)
139 #define PIO_FDEBUG_TXOVER_LSB    _u(16)
140 #define PIO_FDEBUG_TXOVER_ACCESS "WC"
141 // -----------------------------------------------------------------------------
142 // Field       : PIO_FDEBUG_RXUNDER
143 // Description : RX FIFO underflow (i.e. read-on-empty by the system) has
144 //               occurred. Write 1 to clear. Note that read-on-empty does not
145 //               perturb the state of the FIFO in any way, but the data returned
146 //               by reading from an empty FIFO is undefined, so this flag
147 //               generally only becomes set due to some kind of software error.
148 #define PIO_FDEBUG_RXUNDER_RESET  _u(0x0)
149 #define PIO_FDEBUG_RXUNDER_BITS   _u(0x00000f00)
150 #define PIO_FDEBUG_RXUNDER_MSB    _u(11)
151 #define PIO_FDEBUG_RXUNDER_LSB    _u(8)
152 #define PIO_FDEBUG_RXUNDER_ACCESS "WC"
153 // -----------------------------------------------------------------------------
154 // Field       : PIO_FDEBUG_RXSTALL
155 // Description : State machine has stalled on full RX FIFO during a blocking
156 //               PUSH, or an IN with autopush enabled. This flag is also set
157 //               when a nonblocking PUSH to a full FIFO took place, in which
158 //               case the state machine has dropped data. Write 1 to clear.
159 #define PIO_FDEBUG_RXSTALL_RESET  _u(0x0)
160 #define PIO_FDEBUG_RXSTALL_BITS   _u(0x0000000f)
161 #define PIO_FDEBUG_RXSTALL_MSB    _u(3)
162 #define PIO_FDEBUG_RXSTALL_LSB    _u(0)
163 #define PIO_FDEBUG_RXSTALL_ACCESS "WC"
164 // =============================================================================
165 // Register    : PIO_FLEVEL
166 // Description : FIFO levels
167 #define PIO_FLEVEL_OFFSET _u(0x0000000c)
168 #define PIO_FLEVEL_BITS   _u(0xffffffff)
169 #define PIO_FLEVEL_RESET  _u(0x00000000)
170 // -----------------------------------------------------------------------------
171 // Field       : PIO_FLEVEL_RX3
172 // Description : None
173 #define PIO_FLEVEL_RX3_RESET  _u(0x0)
174 #define PIO_FLEVEL_RX3_BITS   _u(0xf0000000)
175 #define PIO_FLEVEL_RX3_MSB    _u(31)
176 #define PIO_FLEVEL_RX3_LSB    _u(28)
177 #define PIO_FLEVEL_RX3_ACCESS "RO"
178 // -----------------------------------------------------------------------------
179 // Field       : PIO_FLEVEL_TX3
180 // Description : None
181 #define PIO_FLEVEL_TX3_RESET  _u(0x0)
182 #define PIO_FLEVEL_TX3_BITS   _u(0x0f000000)
183 #define PIO_FLEVEL_TX3_MSB    _u(27)
184 #define PIO_FLEVEL_TX3_LSB    _u(24)
185 #define PIO_FLEVEL_TX3_ACCESS "RO"
186 // -----------------------------------------------------------------------------
187 // Field       : PIO_FLEVEL_RX2
188 // Description : None
189 #define PIO_FLEVEL_RX2_RESET  _u(0x0)
190 #define PIO_FLEVEL_RX2_BITS   _u(0x00f00000)
191 #define PIO_FLEVEL_RX2_MSB    _u(23)
192 #define PIO_FLEVEL_RX2_LSB    _u(20)
193 #define PIO_FLEVEL_RX2_ACCESS "RO"
194 // -----------------------------------------------------------------------------
195 // Field       : PIO_FLEVEL_TX2
196 // Description : None
197 #define PIO_FLEVEL_TX2_RESET  _u(0x0)
198 #define PIO_FLEVEL_TX2_BITS   _u(0x000f0000)
199 #define PIO_FLEVEL_TX2_MSB    _u(19)
200 #define PIO_FLEVEL_TX2_LSB    _u(16)
201 #define PIO_FLEVEL_TX2_ACCESS "RO"
202 // -----------------------------------------------------------------------------
203 // Field       : PIO_FLEVEL_RX1
204 // Description : None
205 #define PIO_FLEVEL_RX1_RESET  _u(0x0)
206 #define PIO_FLEVEL_RX1_BITS   _u(0x0000f000)
207 #define PIO_FLEVEL_RX1_MSB    _u(15)
208 #define PIO_FLEVEL_RX1_LSB    _u(12)
209 #define PIO_FLEVEL_RX1_ACCESS "RO"
210 // -----------------------------------------------------------------------------
211 // Field       : PIO_FLEVEL_TX1
212 // Description : None
213 #define PIO_FLEVEL_TX1_RESET  _u(0x0)
214 #define PIO_FLEVEL_TX1_BITS   _u(0x00000f00)
215 #define PIO_FLEVEL_TX1_MSB    _u(11)
216 #define PIO_FLEVEL_TX1_LSB    _u(8)
217 #define PIO_FLEVEL_TX1_ACCESS "RO"
218 // -----------------------------------------------------------------------------
219 // Field       : PIO_FLEVEL_RX0
220 // Description : None
221 #define PIO_FLEVEL_RX0_RESET  _u(0x0)
222 #define PIO_FLEVEL_RX0_BITS   _u(0x000000f0)
223 #define PIO_FLEVEL_RX0_MSB    _u(7)
224 #define PIO_FLEVEL_RX0_LSB    _u(4)
225 #define PIO_FLEVEL_RX0_ACCESS "RO"
226 // -----------------------------------------------------------------------------
227 // Field       : PIO_FLEVEL_TX0
228 // Description : None
229 #define PIO_FLEVEL_TX0_RESET  _u(0x0)
230 #define PIO_FLEVEL_TX0_BITS   _u(0x0000000f)
231 #define PIO_FLEVEL_TX0_MSB    _u(3)
232 #define PIO_FLEVEL_TX0_LSB    _u(0)
233 #define PIO_FLEVEL_TX0_ACCESS "RO"
234 // =============================================================================
235 // Register    : PIO_TXF0
236 // Description : Direct write access to the TX FIFO for this state machine. Each
237 //               write pushes one word to the FIFO. Attempting to write to a
238 //               full FIFO has no effect on the FIFO state or contents, and sets
239 //               the sticky FDEBUG_TXOVER error flag for this FIFO.
240 #define PIO_TXF0_OFFSET _u(0x00000010)
241 #define PIO_TXF0_BITS   _u(0xffffffff)
242 #define PIO_TXF0_RESET  _u(0x00000000)
243 #define PIO_TXF0_MSB    _u(31)
244 #define PIO_TXF0_LSB    _u(0)
245 #define PIO_TXF0_ACCESS "WF"
246 // =============================================================================
247 // Register    : PIO_TXF1
248 // Description : Direct write access to the TX FIFO for this state machine. Each
249 //               write pushes one word to the FIFO. Attempting to write to a
250 //               full FIFO has no effect on the FIFO state or contents, and sets
251 //               the sticky FDEBUG_TXOVER error flag for this FIFO.
252 #define PIO_TXF1_OFFSET _u(0x00000014)
253 #define PIO_TXF1_BITS   _u(0xffffffff)
254 #define PIO_TXF1_RESET  _u(0x00000000)
255 #define PIO_TXF1_MSB    _u(31)
256 #define PIO_TXF1_LSB    _u(0)
257 #define PIO_TXF1_ACCESS "WF"
258 // =============================================================================
259 // Register    : PIO_TXF2
260 // Description : Direct write access to the TX FIFO for this state machine. Each
261 //               write pushes one word to the FIFO. Attempting to write to a
262 //               full FIFO has no effect on the FIFO state or contents, and sets
263 //               the sticky FDEBUG_TXOVER error flag for this FIFO.
264 #define PIO_TXF2_OFFSET _u(0x00000018)
265 #define PIO_TXF2_BITS   _u(0xffffffff)
266 #define PIO_TXF2_RESET  _u(0x00000000)
267 #define PIO_TXF2_MSB    _u(31)
268 #define PIO_TXF2_LSB    _u(0)
269 #define PIO_TXF2_ACCESS "WF"
270 // =============================================================================
271 // Register    : PIO_TXF3
272 // Description : Direct write access to the TX FIFO for this state machine. Each
273 //               write pushes one word to the FIFO. Attempting to write to a
274 //               full FIFO has no effect on the FIFO state or contents, and sets
275 //               the sticky FDEBUG_TXOVER error flag for this FIFO.
276 #define PIO_TXF3_OFFSET _u(0x0000001c)
277 #define PIO_TXF3_BITS   _u(0xffffffff)
278 #define PIO_TXF3_RESET  _u(0x00000000)
279 #define PIO_TXF3_MSB    _u(31)
280 #define PIO_TXF3_LSB    _u(0)
281 #define PIO_TXF3_ACCESS "WF"
282 // =============================================================================
283 // Register    : PIO_RXF0
284 // Description : Direct read access to the RX FIFO for this state machine. Each
285 //               read pops one word from the FIFO. Attempting to read from an
286 //               empty FIFO has no effect on the FIFO state, and sets the sticky
287 //               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
288 //               the system on a read from an empty FIFO is undefined.
289 #define PIO_RXF0_OFFSET _u(0x00000020)
290 #define PIO_RXF0_BITS   _u(0xffffffff)
291 #define PIO_RXF0_RESET  "-"
292 #define PIO_RXF0_MSB    _u(31)
293 #define PIO_RXF0_LSB    _u(0)
294 #define PIO_RXF0_ACCESS "RF"
295 // =============================================================================
296 // Register    : PIO_RXF1
297 // Description : Direct read access to the RX FIFO for this state machine. Each
298 //               read pops one word from the FIFO. Attempting to read from an
299 //               empty FIFO has no effect on the FIFO state, and sets the sticky
300 //               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
301 //               the system on a read from an empty FIFO is undefined.
302 #define PIO_RXF1_OFFSET _u(0x00000024)
303 #define PIO_RXF1_BITS   _u(0xffffffff)
304 #define PIO_RXF1_RESET  "-"
305 #define PIO_RXF1_MSB    _u(31)
306 #define PIO_RXF1_LSB    _u(0)
307 #define PIO_RXF1_ACCESS "RF"
308 // =============================================================================
309 // Register    : PIO_RXF2
310 // Description : Direct read access to the RX FIFO for this state machine. Each
311 //               read pops one word from the FIFO. Attempting to read from an
312 //               empty FIFO has no effect on the FIFO state, and sets the sticky
313 //               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
314 //               the system on a read from an empty FIFO is undefined.
315 #define PIO_RXF2_OFFSET _u(0x00000028)
316 #define PIO_RXF2_BITS   _u(0xffffffff)
317 #define PIO_RXF2_RESET  "-"
318 #define PIO_RXF2_MSB    _u(31)
319 #define PIO_RXF2_LSB    _u(0)
320 #define PIO_RXF2_ACCESS "RF"
321 // =============================================================================
322 // Register    : PIO_RXF3
323 // Description : Direct read access to the RX FIFO for this state machine. Each
324 //               read pops one word from the FIFO. Attempting to read from an
325 //               empty FIFO has no effect on the FIFO state, and sets the sticky
326 //               FDEBUG_RXUNDER error flag for this FIFO. The data returned to
327 //               the system on a read from an empty FIFO is undefined.
328 #define PIO_RXF3_OFFSET _u(0x0000002c)
329 #define PIO_RXF3_BITS   _u(0xffffffff)
330 #define PIO_RXF3_RESET  "-"
331 #define PIO_RXF3_MSB    _u(31)
332 #define PIO_RXF3_LSB    _u(0)
333 #define PIO_RXF3_ACCESS "RF"
334 // =============================================================================
335 // Register    : PIO_IRQ
336 // Description : State machine IRQ flags register. Write 1 to clear. There are 8
337 //               state machine IRQ flags, which can be set, cleared, and waited
338 //               on by the state machines. There's no fixed association between
339 //               flags and state machines -- any state machine can use any flag.
340 //
341 //               Any of the 8 flags can be used for timing synchronisation
342 //               between state machines, using IRQ and WAIT instructions. The
343 //               lower four of these flags are also routed out to system-level
344 //               interrupt requests, alongside FIFO status interrupts -- see
345 //               e.g. IRQ0_INTE.
346 #define PIO_IRQ_OFFSET _u(0x00000030)
347 #define PIO_IRQ_BITS   _u(0x000000ff)
348 #define PIO_IRQ_RESET  _u(0x00000000)
349 #define PIO_IRQ_MSB    _u(7)
350 #define PIO_IRQ_LSB    _u(0)
351 #define PIO_IRQ_ACCESS "WC"
352 // =============================================================================
353 // Register    : PIO_IRQ_FORCE
354 // Description : Writing a 1 to each of these bits will forcibly assert the
355 //               corresponding IRQ. Note this is different to the INTF register:
356 //               writing here affects PIO internal state. INTF just asserts the
357 //               processor-facing IRQ signal for testing ISRs, and is not
358 //               visible to the state machines.
359 #define PIO_IRQ_FORCE_OFFSET _u(0x00000034)
360 #define PIO_IRQ_FORCE_BITS   _u(0x000000ff)
361 #define PIO_IRQ_FORCE_RESET  _u(0x00000000)
362 #define PIO_IRQ_FORCE_MSB    _u(7)
363 #define PIO_IRQ_FORCE_LSB    _u(0)
364 #define PIO_IRQ_FORCE_ACCESS "WF"
365 // =============================================================================
366 // Register    : PIO_INPUT_SYNC_BYPASS
367 // Description : There is a 2-flipflop synchronizer on each GPIO input, which
368 //               protects PIO logic from metastabilities. This increases input
369 //               delay, and for fast synchronous IO (e.g. SPI) these
370 //               synchronizers may need to be bypassed. Each bit in this
371 //               register corresponds to one GPIO.
372 //               0 -> input is synchronized (default)
373 //               1 -> synchronizer is bypassed
374 //               If in doubt, leave this register as all zeroes.
375 #define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038)
376 #define PIO_INPUT_SYNC_BYPASS_BITS   _u(0xffffffff)
377 #define PIO_INPUT_SYNC_BYPASS_RESET  _u(0x00000000)
378 #define PIO_INPUT_SYNC_BYPASS_MSB    _u(31)
379 #define PIO_INPUT_SYNC_BYPASS_LSB    _u(0)
380 #define PIO_INPUT_SYNC_BYPASS_ACCESS "RW"
381 // =============================================================================
382 // Register    : PIO_DBG_PADOUT
383 // Description : Read to sample the pad output values PIO is currently driving
384 //               to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
385 //               significant bits are hardwired to 0.
386 #define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
387 #define PIO_DBG_PADOUT_BITS   _u(0xffffffff)
388 #define PIO_DBG_PADOUT_RESET  _u(0x00000000)
389 #define PIO_DBG_PADOUT_MSB    _u(31)
390 #define PIO_DBG_PADOUT_LSB    _u(0)
391 #define PIO_DBG_PADOUT_ACCESS "RO"
392 // =============================================================================
393 // Register    : PIO_DBG_PADOE
394 // Description : Read to sample the pad output enables (direction) PIO is
395 //               currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
396 //               so the two most significant bits are hardwired to 0.
397 #define PIO_DBG_PADOE_OFFSET _u(0x00000040)
398 #define PIO_DBG_PADOE_BITS   _u(0xffffffff)
399 #define PIO_DBG_PADOE_RESET  _u(0x00000000)
400 #define PIO_DBG_PADOE_MSB    _u(31)
401 #define PIO_DBG_PADOE_LSB    _u(0)
402 #define PIO_DBG_PADOE_ACCESS "RO"
403 // =============================================================================
404 // Register    : PIO_DBG_CFGINFO
405 // Description : The PIO hardware has some free parameters that may vary between
406 //               chip products.
407 //               These should be provided in the chip datasheet, but are also
408 //               exposed here.
409 #define PIO_DBG_CFGINFO_OFFSET _u(0x00000044)
410 #define PIO_DBG_CFGINFO_BITS   _u(0x003f0f3f)
411 #define PIO_DBG_CFGINFO_RESET  _u(0x00000000)
412 // -----------------------------------------------------------------------------
413 // Field       : PIO_DBG_CFGINFO_IMEM_SIZE
414 // Description : The size of the instruction memory, measured in units of one
415 //               instruction
416 #define PIO_DBG_CFGINFO_IMEM_SIZE_RESET  "-"
417 #define PIO_DBG_CFGINFO_IMEM_SIZE_BITS   _u(0x003f0000)
418 #define PIO_DBG_CFGINFO_IMEM_SIZE_MSB    _u(21)
419 #define PIO_DBG_CFGINFO_IMEM_SIZE_LSB    _u(16)
420 #define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO"
421 // -----------------------------------------------------------------------------
422 // Field       : PIO_DBG_CFGINFO_SM_COUNT
423 // Description : The number of state machines this PIO instance is equipped
424 //               with.
425 #define PIO_DBG_CFGINFO_SM_COUNT_RESET  "-"
426 #define PIO_DBG_CFGINFO_SM_COUNT_BITS   _u(0x00000f00)
427 #define PIO_DBG_CFGINFO_SM_COUNT_MSB    _u(11)
428 #define PIO_DBG_CFGINFO_SM_COUNT_LSB    _u(8)
429 #define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO"
430 // -----------------------------------------------------------------------------
431 // Field       : PIO_DBG_CFGINFO_FIFO_DEPTH
432 // Description : The depth of the state machine TX/RX FIFOs, measured in words.
433 //               Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double
434 //               this depth.
435 #define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET  "-"
436 #define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS   _u(0x0000003f)
437 #define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB    _u(5)
438 #define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB    _u(0)
439 #define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO"
440 // =============================================================================
441 // Register    : PIO_INSTR_MEM0
442 // Description : Write-only access to instruction memory location 0
443 #define PIO_INSTR_MEM0_OFFSET _u(0x00000048)
444 #define PIO_INSTR_MEM0_BITS   _u(0x0000ffff)
445 #define PIO_INSTR_MEM0_RESET  _u(0x00000000)
446 #define PIO_INSTR_MEM0_MSB    _u(15)
447 #define PIO_INSTR_MEM0_LSB    _u(0)
448 #define PIO_INSTR_MEM0_ACCESS "WO"
449 // =============================================================================
450 // Register    : PIO_INSTR_MEM1
451 // Description : Write-only access to instruction memory location 1
452 #define PIO_INSTR_MEM1_OFFSET _u(0x0000004c)
453 #define PIO_INSTR_MEM1_BITS   _u(0x0000ffff)
454 #define PIO_INSTR_MEM1_RESET  _u(0x00000000)
455 #define PIO_INSTR_MEM1_MSB    _u(15)
456 #define PIO_INSTR_MEM1_LSB    _u(0)
457 #define PIO_INSTR_MEM1_ACCESS "WO"
458 // =============================================================================
459 // Register    : PIO_INSTR_MEM2
460 // Description : Write-only access to instruction memory location 2
461 #define PIO_INSTR_MEM2_OFFSET _u(0x00000050)
462 #define PIO_INSTR_MEM2_BITS   _u(0x0000ffff)
463 #define PIO_INSTR_MEM2_RESET  _u(0x00000000)
464 #define PIO_INSTR_MEM2_MSB    _u(15)
465 #define PIO_INSTR_MEM2_LSB    _u(0)
466 #define PIO_INSTR_MEM2_ACCESS "WO"
467 // =============================================================================
468 // Register    : PIO_INSTR_MEM3
469 // Description : Write-only access to instruction memory location 3
470 #define PIO_INSTR_MEM3_OFFSET _u(0x00000054)
471 #define PIO_INSTR_MEM3_BITS   _u(0x0000ffff)
472 #define PIO_INSTR_MEM3_RESET  _u(0x00000000)
473 #define PIO_INSTR_MEM3_MSB    _u(15)
474 #define PIO_INSTR_MEM3_LSB    _u(0)
475 #define PIO_INSTR_MEM3_ACCESS "WO"
476 // =============================================================================
477 // Register    : PIO_INSTR_MEM4
478 // Description : Write-only access to instruction memory location 4
479 #define PIO_INSTR_MEM4_OFFSET _u(0x00000058)
480 #define PIO_INSTR_MEM4_BITS   _u(0x0000ffff)
481 #define PIO_INSTR_MEM4_RESET  _u(0x00000000)
482 #define PIO_INSTR_MEM4_MSB    _u(15)
483 #define PIO_INSTR_MEM4_LSB    _u(0)
484 #define PIO_INSTR_MEM4_ACCESS "WO"
485 // =============================================================================
486 // Register    : PIO_INSTR_MEM5
487 // Description : Write-only access to instruction memory location 5
488 #define PIO_INSTR_MEM5_OFFSET _u(0x0000005c)
489 #define PIO_INSTR_MEM5_BITS   _u(0x0000ffff)
490 #define PIO_INSTR_MEM5_RESET  _u(0x00000000)
491 #define PIO_INSTR_MEM5_MSB    _u(15)
492 #define PIO_INSTR_MEM5_LSB    _u(0)
493 #define PIO_INSTR_MEM5_ACCESS "WO"
494 // =============================================================================
495 // Register    : PIO_INSTR_MEM6
496 // Description : Write-only access to instruction memory location 6
497 #define PIO_INSTR_MEM6_OFFSET _u(0x00000060)
498 #define PIO_INSTR_MEM6_BITS   _u(0x0000ffff)
499 #define PIO_INSTR_MEM6_RESET  _u(0x00000000)
500 #define PIO_INSTR_MEM6_MSB    _u(15)
501 #define PIO_INSTR_MEM6_LSB    _u(0)
502 #define PIO_INSTR_MEM6_ACCESS "WO"
503 // =============================================================================
504 // Register    : PIO_INSTR_MEM7
505 // Description : Write-only access to instruction memory location 7
506 #define PIO_INSTR_MEM7_OFFSET _u(0x00000064)
507 #define PIO_INSTR_MEM7_BITS   _u(0x0000ffff)
508 #define PIO_INSTR_MEM7_RESET  _u(0x00000000)
509 #define PIO_INSTR_MEM7_MSB    _u(15)
510 #define PIO_INSTR_MEM7_LSB    _u(0)
511 #define PIO_INSTR_MEM7_ACCESS "WO"
512 // =============================================================================
513 // Register    : PIO_INSTR_MEM8
514 // Description : Write-only access to instruction memory location 8
515 #define PIO_INSTR_MEM8_OFFSET _u(0x00000068)
516 #define PIO_INSTR_MEM8_BITS   _u(0x0000ffff)
517 #define PIO_INSTR_MEM8_RESET  _u(0x00000000)
518 #define PIO_INSTR_MEM8_MSB    _u(15)
519 #define PIO_INSTR_MEM8_LSB    _u(0)
520 #define PIO_INSTR_MEM8_ACCESS "WO"
521 // =============================================================================
522 // Register    : PIO_INSTR_MEM9
523 // Description : Write-only access to instruction memory location 9
524 #define PIO_INSTR_MEM9_OFFSET _u(0x0000006c)
525 #define PIO_INSTR_MEM9_BITS   _u(0x0000ffff)
526 #define PIO_INSTR_MEM9_RESET  _u(0x00000000)
527 #define PIO_INSTR_MEM9_MSB    _u(15)
528 #define PIO_INSTR_MEM9_LSB    _u(0)
529 #define PIO_INSTR_MEM9_ACCESS "WO"
530 // =============================================================================
531 // Register    : PIO_INSTR_MEM10
532 // Description : Write-only access to instruction memory location 10
533 #define PIO_INSTR_MEM10_OFFSET _u(0x00000070)
534 #define PIO_INSTR_MEM10_BITS   _u(0x0000ffff)
535 #define PIO_INSTR_MEM10_RESET  _u(0x00000000)
536 #define PIO_INSTR_MEM10_MSB    _u(15)
537 #define PIO_INSTR_MEM10_LSB    _u(0)
538 #define PIO_INSTR_MEM10_ACCESS "WO"
539 // =============================================================================
540 // Register    : PIO_INSTR_MEM11
541 // Description : Write-only access to instruction memory location 11
542 #define PIO_INSTR_MEM11_OFFSET _u(0x00000074)
543 #define PIO_INSTR_MEM11_BITS   _u(0x0000ffff)
544 #define PIO_INSTR_MEM11_RESET  _u(0x00000000)
545 #define PIO_INSTR_MEM11_MSB    _u(15)
546 #define PIO_INSTR_MEM11_LSB    _u(0)
547 #define PIO_INSTR_MEM11_ACCESS "WO"
548 // =============================================================================
549 // Register    : PIO_INSTR_MEM12
550 // Description : Write-only access to instruction memory location 12
551 #define PIO_INSTR_MEM12_OFFSET _u(0x00000078)
552 #define PIO_INSTR_MEM12_BITS   _u(0x0000ffff)
553 #define PIO_INSTR_MEM12_RESET  _u(0x00000000)
554 #define PIO_INSTR_MEM12_MSB    _u(15)
555 #define PIO_INSTR_MEM12_LSB    _u(0)
556 #define PIO_INSTR_MEM12_ACCESS "WO"
557 // =============================================================================
558 // Register    : PIO_INSTR_MEM13
559 // Description : Write-only access to instruction memory location 13
560 #define PIO_INSTR_MEM13_OFFSET _u(0x0000007c)
561 #define PIO_INSTR_MEM13_BITS   _u(0x0000ffff)
562 #define PIO_INSTR_MEM13_RESET  _u(0x00000000)
563 #define PIO_INSTR_MEM13_MSB    _u(15)
564 #define PIO_INSTR_MEM13_LSB    _u(0)
565 #define PIO_INSTR_MEM13_ACCESS "WO"
566 // =============================================================================
567 // Register    : PIO_INSTR_MEM14
568 // Description : Write-only access to instruction memory location 14
569 #define PIO_INSTR_MEM14_OFFSET _u(0x00000080)
570 #define PIO_INSTR_MEM14_BITS   _u(0x0000ffff)
571 #define PIO_INSTR_MEM14_RESET  _u(0x00000000)
572 #define PIO_INSTR_MEM14_MSB    _u(15)
573 #define PIO_INSTR_MEM14_LSB    _u(0)
574 #define PIO_INSTR_MEM14_ACCESS "WO"
575 // =============================================================================
576 // Register    : PIO_INSTR_MEM15
577 // Description : Write-only access to instruction memory location 15
578 #define PIO_INSTR_MEM15_OFFSET _u(0x00000084)
579 #define PIO_INSTR_MEM15_BITS   _u(0x0000ffff)
580 #define PIO_INSTR_MEM15_RESET  _u(0x00000000)
581 #define PIO_INSTR_MEM15_MSB    _u(15)
582 #define PIO_INSTR_MEM15_LSB    _u(0)
583 #define PIO_INSTR_MEM15_ACCESS "WO"
584 // =============================================================================
585 // Register    : PIO_INSTR_MEM16
586 // Description : Write-only access to instruction memory location 16
587 #define PIO_INSTR_MEM16_OFFSET _u(0x00000088)
588 #define PIO_INSTR_MEM16_BITS   _u(0x0000ffff)
589 #define PIO_INSTR_MEM16_RESET  _u(0x00000000)
590 #define PIO_INSTR_MEM16_MSB    _u(15)
591 #define PIO_INSTR_MEM16_LSB    _u(0)
592 #define PIO_INSTR_MEM16_ACCESS "WO"
593 // =============================================================================
594 // Register    : PIO_INSTR_MEM17
595 // Description : Write-only access to instruction memory location 17
596 #define PIO_INSTR_MEM17_OFFSET _u(0x0000008c)
597 #define PIO_INSTR_MEM17_BITS   _u(0x0000ffff)
598 #define PIO_INSTR_MEM17_RESET  _u(0x00000000)
599 #define PIO_INSTR_MEM17_MSB    _u(15)
600 #define PIO_INSTR_MEM17_LSB    _u(0)
601 #define PIO_INSTR_MEM17_ACCESS "WO"
602 // =============================================================================
603 // Register    : PIO_INSTR_MEM18
604 // Description : Write-only access to instruction memory location 18
605 #define PIO_INSTR_MEM18_OFFSET _u(0x00000090)
606 #define PIO_INSTR_MEM18_BITS   _u(0x0000ffff)
607 #define PIO_INSTR_MEM18_RESET  _u(0x00000000)
608 #define PIO_INSTR_MEM18_MSB    _u(15)
609 #define PIO_INSTR_MEM18_LSB    _u(0)
610 #define PIO_INSTR_MEM18_ACCESS "WO"
611 // =============================================================================
612 // Register    : PIO_INSTR_MEM19
613 // Description : Write-only access to instruction memory location 19
614 #define PIO_INSTR_MEM19_OFFSET _u(0x00000094)
615 #define PIO_INSTR_MEM19_BITS   _u(0x0000ffff)
616 #define PIO_INSTR_MEM19_RESET  _u(0x00000000)
617 #define PIO_INSTR_MEM19_MSB    _u(15)
618 #define PIO_INSTR_MEM19_LSB    _u(0)
619 #define PIO_INSTR_MEM19_ACCESS "WO"
620 // =============================================================================
621 // Register    : PIO_INSTR_MEM20
622 // Description : Write-only access to instruction memory location 20
623 #define PIO_INSTR_MEM20_OFFSET _u(0x00000098)
624 #define PIO_INSTR_MEM20_BITS   _u(0x0000ffff)
625 #define PIO_INSTR_MEM20_RESET  _u(0x00000000)
626 #define PIO_INSTR_MEM20_MSB    _u(15)
627 #define PIO_INSTR_MEM20_LSB    _u(0)
628 #define PIO_INSTR_MEM20_ACCESS "WO"
629 // =============================================================================
630 // Register    : PIO_INSTR_MEM21
631 // Description : Write-only access to instruction memory location 21
632 #define PIO_INSTR_MEM21_OFFSET _u(0x0000009c)
633 #define PIO_INSTR_MEM21_BITS   _u(0x0000ffff)
634 #define PIO_INSTR_MEM21_RESET  _u(0x00000000)
635 #define PIO_INSTR_MEM21_MSB    _u(15)
636 #define PIO_INSTR_MEM21_LSB    _u(0)
637 #define PIO_INSTR_MEM21_ACCESS "WO"
638 // =============================================================================
639 // Register    : PIO_INSTR_MEM22
640 // Description : Write-only access to instruction memory location 22
641 #define PIO_INSTR_MEM22_OFFSET _u(0x000000a0)
642 #define PIO_INSTR_MEM22_BITS   _u(0x0000ffff)
643 #define PIO_INSTR_MEM22_RESET  _u(0x00000000)
644 #define PIO_INSTR_MEM22_MSB    _u(15)
645 #define PIO_INSTR_MEM22_LSB    _u(0)
646 #define PIO_INSTR_MEM22_ACCESS "WO"
647 // =============================================================================
648 // Register    : PIO_INSTR_MEM23
649 // Description : Write-only access to instruction memory location 23
650 #define PIO_INSTR_MEM23_OFFSET _u(0x000000a4)
651 #define PIO_INSTR_MEM23_BITS   _u(0x0000ffff)
652 #define PIO_INSTR_MEM23_RESET  _u(0x00000000)
653 #define PIO_INSTR_MEM23_MSB    _u(15)
654 #define PIO_INSTR_MEM23_LSB    _u(0)
655 #define PIO_INSTR_MEM23_ACCESS "WO"
656 // =============================================================================
657 // Register    : PIO_INSTR_MEM24
658 // Description : Write-only access to instruction memory location 24
659 #define PIO_INSTR_MEM24_OFFSET _u(0x000000a8)
660 #define PIO_INSTR_MEM24_BITS   _u(0x0000ffff)
661 #define PIO_INSTR_MEM24_RESET  _u(0x00000000)
662 #define PIO_INSTR_MEM24_MSB    _u(15)
663 #define PIO_INSTR_MEM24_LSB    _u(0)
664 #define PIO_INSTR_MEM24_ACCESS "WO"
665 // =============================================================================
666 // Register    : PIO_INSTR_MEM25
667 // Description : Write-only access to instruction memory location 25
668 #define PIO_INSTR_MEM25_OFFSET _u(0x000000ac)
669 #define PIO_INSTR_MEM25_BITS   _u(0x0000ffff)
670 #define PIO_INSTR_MEM25_RESET  _u(0x00000000)
671 #define PIO_INSTR_MEM25_MSB    _u(15)
672 #define PIO_INSTR_MEM25_LSB    _u(0)
673 #define PIO_INSTR_MEM25_ACCESS "WO"
674 // =============================================================================
675 // Register    : PIO_INSTR_MEM26
676 // Description : Write-only access to instruction memory location 26
677 #define PIO_INSTR_MEM26_OFFSET _u(0x000000b0)
678 #define PIO_INSTR_MEM26_BITS   _u(0x0000ffff)
679 #define PIO_INSTR_MEM26_RESET  _u(0x00000000)
680 #define PIO_INSTR_MEM26_MSB    _u(15)
681 #define PIO_INSTR_MEM26_LSB    _u(0)
682 #define PIO_INSTR_MEM26_ACCESS "WO"
683 // =============================================================================
684 // Register    : PIO_INSTR_MEM27
685 // Description : Write-only access to instruction memory location 27
686 #define PIO_INSTR_MEM27_OFFSET _u(0x000000b4)
687 #define PIO_INSTR_MEM27_BITS   _u(0x0000ffff)
688 #define PIO_INSTR_MEM27_RESET  _u(0x00000000)
689 #define PIO_INSTR_MEM27_MSB    _u(15)
690 #define PIO_INSTR_MEM27_LSB    _u(0)
691 #define PIO_INSTR_MEM27_ACCESS "WO"
692 // =============================================================================
693 // Register    : PIO_INSTR_MEM28
694 // Description : Write-only access to instruction memory location 28
695 #define PIO_INSTR_MEM28_OFFSET _u(0x000000b8)
696 #define PIO_INSTR_MEM28_BITS   _u(0x0000ffff)
697 #define PIO_INSTR_MEM28_RESET  _u(0x00000000)
698 #define PIO_INSTR_MEM28_MSB    _u(15)
699 #define PIO_INSTR_MEM28_LSB    _u(0)
700 #define PIO_INSTR_MEM28_ACCESS "WO"
701 // =============================================================================
702 // Register    : PIO_INSTR_MEM29
703 // Description : Write-only access to instruction memory location 29
704 #define PIO_INSTR_MEM29_OFFSET _u(0x000000bc)
705 #define PIO_INSTR_MEM29_BITS   _u(0x0000ffff)
706 #define PIO_INSTR_MEM29_RESET  _u(0x00000000)
707 #define PIO_INSTR_MEM29_MSB    _u(15)
708 #define PIO_INSTR_MEM29_LSB    _u(0)
709 #define PIO_INSTR_MEM29_ACCESS "WO"
710 // =============================================================================
711 // Register    : PIO_INSTR_MEM30
712 // Description : Write-only access to instruction memory location 30
713 #define PIO_INSTR_MEM30_OFFSET _u(0x000000c0)
714 #define PIO_INSTR_MEM30_BITS   _u(0x0000ffff)
715 #define PIO_INSTR_MEM30_RESET  _u(0x00000000)
716 #define PIO_INSTR_MEM30_MSB    _u(15)
717 #define PIO_INSTR_MEM30_LSB    _u(0)
718 #define PIO_INSTR_MEM30_ACCESS "WO"
719 // =============================================================================
720 // Register    : PIO_INSTR_MEM31
721 // Description : Write-only access to instruction memory location 31
722 #define PIO_INSTR_MEM31_OFFSET _u(0x000000c4)
723 #define PIO_INSTR_MEM31_BITS   _u(0x0000ffff)
724 #define PIO_INSTR_MEM31_RESET  _u(0x00000000)
725 #define PIO_INSTR_MEM31_MSB    _u(15)
726 #define PIO_INSTR_MEM31_LSB    _u(0)
727 #define PIO_INSTR_MEM31_ACCESS "WO"
728 // =============================================================================
729 // Register    : PIO_SM0_CLKDIV
730 // Description : Clock divisor register for state machine 0
731 //               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
732 #define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8)
733 #define PIO_SM0_CLKDIV_BITS   _u(0xffffff00)
734 #define PIO_SM0_CLKDIV_RESET  _u(0x00010000)
735 // -----------------------------------------------------------------------------
736 // Field       : PIO_SM0_CLKDIV_INT
737 // Description : Effective frequency is sysclk/(int + frac/256).
738 //               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
739 //               be 0.
740 #define PIO_SM0_CLKDIV_INT_RESET  _u(0x0001)
741 #define PIO_SM0_CLKDIV_INT_BITS   _u(0xffff0000)
742 #define PIO_SM0_CLKDIV_INT_MSB    _u(31)
743 #define PIO_SM0_CLKDIV_INT_LSB    _u(16)
744 #define PIO_SM0_CLKDIV_INT_ACCESS "RW"
745 // -----------------------------------------------------------------------------
746 // Field       : PIO_SM0_CLKDIV_FRAC
747 // Description : Fractional part of clock divisor
748 #define PIO_SM0_CLKDIV_FRAC_RESET  _u(0x00)
749 #define PIO_SM0_CLKDIV_FRAC_BITS   _u(0x0000ff00)
750 #define PIO_SM0_CLKDIV_FRAC_MSB    _u(15)
751 #define PIO_SM0_CLKDIV_FRAC_LSB    _u(8)
752 #define PIO_SM0_CLKDIV_FRAC_ACCESS "RW"
753 // =============================================================================
754 // Register    : PIO_SM0_EXECCTRL
755 // Description : Execution/behavioural settings for state machine 0
756 #define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc)
757 #define PIO_SM0_EXECCTRL_BITS   _u(0xffffff9f)
758 #define PIO_SM0_EXECCTRL_RESET  _u(0x0001f000)
759 // -----------------------------------------------------------------------------
760 // Field       : PIO_SM0_EXECCTRL_EXEC_STALLED
761 // Description : If 1, an instruction written to SMx_INSTR is stalled, and
762 //               latched by the state machine. Will clear to 0 once this
763 //               instruction completes.
764 #define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
765 #define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
766 #define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB    _u(31)
767 #define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB    _u(31)
768 #define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO"
769 // -----------------------------------------------------------------------------
770 // Field       : PIO_SM0_EXECCTRL_SIDE_EN
771 // Description : If 1, the MSB of the Delay/Side-set instruction field is used
772 //               as side-set enable, rather than a side-set data bit. This
773 //               allows instructions to perform side-set optionally, rather than
774 //               on every instruction, but the maximum possible side-set width
775 //               is reduced from 5 to 4. Note that the value of
776 //               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
777 #define PIO_SM0_EXECCTRL_SIDE_EN_RESET  _u(0x0)
778 #define PIO_SM0_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
779 #define PIO_SM0_EXECCTRL_SIDE_EN_MSB    _u(30)
780 #define PIO_SM0_EXECCTRL_SIDE_EN_LSB    _u(30)
781 #define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW"
782 // -----------------------------------------------------------------------------
783 // Field       : PIO_SM0_EXECCTRL_SIDE_PINDIR
784 // Description : If 1, side-set data is asserted to pin directions, instead of
785 //               pin values
786 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
787 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
788 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
789 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
790 #define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
791 // -----------------------------------------------------------------------------
792 // Field       : PIO_SM0_EXECCTRL_JMP_PIN
793 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by
794 //               input mapping.
795 #define PIO_SM0_EXECCTRL_JMP_PIN_RESET  _u(0x00)
796 #define PIO_SM0_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
797 #define PIO_SM0_EXECCTRL_JMP_PIN_MSB    _u(28)
798 #define PIO_SM0_EXECCTRL_JMP_PIN_LSB    _u(24)
799 #define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW"
800 // -----------------------------------------------------------------------------
801 // Field       : PIO_SM0_EXECCTRL_OUT_EN_SEL
802 // Description : Which data bit to use for inline OUT enable
803 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
804 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
805 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
806 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
807 #define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
808 // -----------------------------------------------------------------------------
809 // Field       : PIO_SM0_EXECCTRL_INLINE_OUT_EN
810 // Description : If 1, use a bit of OUT data as an auxiliary write enable
811 //               When used in conjunction with OUT_STICKY, writes with an enable
812 //               of 0 will
813 //               deassert the latest pin write. This can create useful
814 //               masking/override behaviour
815 //               due to the priority ordering of state machine pin writes (SM0 <
816 //               SM1 < ...)
817 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
818 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
819 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
820 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
821 #define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
822 // -----------------------------------------------------------------------------
823 // Field       : PIO_SM0_EXECCTRL_OUT_STICKY
824 // Description : Continuously assert the most recent OUT/SET to the pins
825 #define PIO_SM0_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
826 #define PIO_SM0_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
827 #define PIO_SM0_EXECCTRL_OUT_STICKY_MSB    _u(17)
828 #define PIO_SM0_EXECCTRL_OUT_STICKY_LSB    _u(17)
829 #define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW"
830 // -----------------------------------------------------------------------------
831 // Field       : PIO_SM0_EXECCTRL_WRAP_TOP
832 // Description : After reaching this address, execution is wrapped to
833 //               wrap_bottom.
834 //               If the instruction is a jump, and the jump condition is true,
835 //               the jump takes priority.
836 #define PIO_SM0_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
837 #define PIO_SM0_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
838 #define PIO_SM0_EXECCTRL_WRAP_TOP_MSB    _u(16)
839 #define PIO_SM0_EXECCTRL_WRAP_TOP_LSB    _u(12)
840 #define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW"
841 // -----------------------------------------------------------------------------
842 // Field       : PIO_SM0_EXECCTRL_WRAP_BOTTOM
843 // Description : After reaching wrap_top, execution is wrapped to this address.
844 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
845 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
846 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
847 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
848 #define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
849 // -----------------------------------------------------------------------------
850 // Field       : PIO_SM0_EXECCTRL_STATUS_SEL
851 // Description : Comparison used for the MOV x, STATUS instruction.
852 //               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
853 //               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
854 #define PIO_SM0_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
855 #define PIO_SM0_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
856 #define PIO_SM0_EXECCTRL_STATUS_SEL_MSB           _u(4)
857 #define PIO_SM0_EXECCTRL_STATUS_SEL_LSB           _u(4)
858 #define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS        "RW"
859 #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
860 #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
861 // -----------------------------------------------------------------------------
862 // Field       : PIO_SM0_EXECCTRL_STATUS_N
863 // Description : Comparison level for the MOV x, STATUS instruction
864 #define PIO_SM0_EXECCTRL_STATUS_N_RESET  _u(0x0)
865 #define PIO_SM0_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
866 #define PIO_SM0_EXECCTRL_STATUS_N_MSB    _u(3)
867 #define PIO_SM0_EXECCTRL_STATUS_N_LSB    _u(0)
868 #define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW"
869 // =============================================================================
870 // Register    : PIO_SM0_SHIFTCTRL
871 // Description : Control behaviour of the input/output shift registers for state
872 //               machine 0
873 #define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0)
874 #define PIO_SM0_SHIFTCTRL_BITS   _u(0xffff0000)
875 #define PIO_SM0_SHIFTCTRL_RESET  _u(0x000c0000)
876 // -----------------------------------------------------------------------------
877 // Field       : PIO_SM0_SHIFTCTRL_FJOIN_RX
878 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
879 //               as deep.
880 //               TX FIFO is disabled as a result (always reads as both full and
881 //               empty).
882 //               FIFOs are flushed when this bit is changed.
883 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
884 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
885 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
886 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
887 #define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
888 // -----------------------------------------------------------------------------
889 // Field       : PIO_SM0_SHIFTCTRL_FJOIN_TX
890 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
891 //               as deep.
892 //               RX FIFO is disabled as a result (always reads as both full and
893 //               empty).
894 //               FIFOs are flushed when this bit is changed.
895 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
896 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
897 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
898 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
899 #define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
900 // -----------------------------------------------------------------------------
901 // Field       : PIO_SM0_SHIFTCTRL_PULL_THRESH
902 // Description : Number of bits shifted out of OSR before autopull, or
903 //               conditional pull (PULL IFEMPTY), will take place.
904 //               Write 0 for value of 32.
905 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
906 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
907 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
908 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
909 #define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
910 // -----------------------------------------------------------------------------
911 // Field       : PIO_SM0_SHIFTCTRL_PUSH_THRESH
912 // Description : Number of bits shifted into ISR before autopush, or conditional
913 //               push (PUSH IFFULL), will take place.
914 //               Write 0 for value of 32.
915 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
916 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
917 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
918 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
919 #define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
920 // -----------------------------------------------------------------------------
921 // Field       : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR
922 // Description : 1 = shift out of output shift register to right. 0 = to left.
923 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
924 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
925 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
926 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
927 #define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
928 // -----------------------------------------------------------------------------
929 // Field       : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR
930 // Description : 1 = shift input shift register to right (data enters from
931 //               left). 0 = to left.
932 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
933 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
934 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
935 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
936 #define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
937 // -----------------------------------------------------------------------------
938 // Field       : PIO_SM0_SHIFTCTRL_AUTOPULL
939 // Description : Pull automatically when the output shift register is emptied,
940 //               i.e. on or following an OUT instruction which causes the output
941 //               shift counter to reach or exceed PULL_THRESH.
942 #define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
943 #define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
944 #define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB    _u(17)
945 #define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB    _u(17)
946 #define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW"
947 // -----------------------------------------------------------------------------
948 // Field       : PIO_SM0_SHIFTCTRL_AUTOPUSH
949 // Description : Push automatically when the input shift register is filled,
950 //               i.e. on an IN instruction which causes the input shift counter
951 //               to reach or exceed PUSH_THRESH.
952 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
953 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
954 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
955 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
956 #define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
957 // =============================================================================
958 // Register    : PIO_SM0_ADDR
959 // Description : Current instruction address of state machine 0
960 #define PIO_SM0_ADDR_OFFSET _u(0x000000d4)
961 #define PIO_SM0_ADDR_BITS   _u(0x0000001f)
962 #define PIO_SM0_ADDR_RESET  _u(0x00000000)
963 #define PIO_SM0_ADDR_MSB    _u(4)
964 #define PIO_SM0_ADDR_LSB    _u(0)
965 #define PIO_SM0_ADDR_ACCESS "RO"
966 // =============================================================================
967 // Register    : PIO_SM0_INSTR
968 // Description : Read to see the instruction currently addressed by state
969 //               machine 0's program counter
970 //               Write to execute an instruction immediately (including jumps)
971 //               and then resume execution.
972 #define PIO_SM0_INSTR_OFFSET _u(0x000000d8)
973 #define PIO_SM0_INSTR_BITS   _u(0x0000ffff)
974 #define PIO_SM0_INSTR_RESET  "-"
975 #define PIO_SM0_INSTR_MSB    _u(15)
976 #define PIO_SM0_INSTR_LSB    _u(0)
977 #define PIO_SM0_INSTR_ACCESS "RW"
978 // =============================================================================
979 // Register    : PIO_SM0_PINCTRL
980 // Description : State machine pin control
981 #define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc)
982 #define PIO_SM0_PINCTRL_BITS   _u(0xffffffff)
983 #define PIO_SM0_PINCTRL_RESET  _u(0x14000000)
984 // -----------------------------------------------------------------------------
985 // Field       : PIO_SM0_PINCTRL_SIDESET_COUNT
986 // Description : The number of MSBs of the Delay/Side-set instruction field
987 //               which are used for side-set. Inclusive of the enable bit, if
988 //               present. Minimum of 0 (all delay bits, no side-set) and maximum
989 //               of 5 (all side-set, no delay).
990 #define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
991 #define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
992 #define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB    _u(31)
993 #define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB    _u(29)
994 #define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW"
995 // -----------------------------------------------------------------------------
996 // Field       : PIO_SM0_PINCTRL_SET_COUNT
997 // Description : The number of pins asserted by a SET. In the range 0 to 5
998 //               inclusive.
999 #define PIO_SM0_PINCTRL_SET_COUNT_RESET  _u(0x5)
1000 #define PIO_SM0_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
1001 #define PIO_SM0_PINCTRL_SET_COUNT_MSB    _u(28)
1002 #define PIO_SM0_PINCTRL_SET_COUNT_LSB    _u(26)
1003 #define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW"
1004 // -----------------------------------------------------------------------------
1005 // Field       : PIO_SM0_PINCTRL_OUT_COUNT
1006 // Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
1007 //               PINS instruction. In the range 0 to 32 inclusive.
1008 #define PIO_SM0_PINCTRL_OUT_COUNT_RESET  _u(0x00)
1009 #define PIO_SM0_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
1010 #define PIO_SM0_PINCTRL_OUT_COUNT_MSB    _u(25)
1011 #define PIO_SM0_PINCTRL_OUT_COUNT_LSB    _u(20)
1012 #define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW"
1013 // -----------------------------------------------------------------------------
1014 // Field       : PIO_SM0_PINCTRL_IN_BASE
1015 // Description : The pin which is mapped to the least-significant bit of a state
1016 //               machine's IN data bus. Higher-numbered pins are mapped to
1017 //               consecutively more-significant data bits, with a modulo of 32
1018 //               applied to pin number.
1019 #define PIO_SM0_PINCTRL_IN_BASE_RESET  _u(0x00)
1020 #define PIO_SM0_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
1021 #define PIO_SM0_PINCTRL_IN_BASE_MSB    _u(19)
1022 #define PIO_SM0_PINCTRL_IN_BASE_LSB    _u(15)
1023 #define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW"
1024 // -----------------------------------------------------------------------------
1025 // Field       : PIO_SM0_PINCTRL_SIDESET_BASE
1026 // Description : The lowest-numbered pin that will be affected by a side-set
1027 //               operation. The MSBs of an instruction's side-set/delay field
1028 //               (up to 5, determined by SIDESET_COUNT) are used for side-set
1029 //               data, with the remaining LSBs used for delay. The
1030 //               least-significant bit of the side-set portion is the bit
1031 //               written to this pin, with more-significant bits written to
1032 //               higher-numbered pins.
1033 #define PIO_SM0_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
1034 #define PIO_SM0_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
1035 #define PIO_SM0_PINCTRL_SIDESET_BASE_MSB    _u(14)
1036 #define PIO_SM0_PINCTRL_SIDESET_BASE_LSB    _u(10)
1037 #define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW"
1038 // -----------------------------------------------------------------------------
1039 // Field       : PIO_SM0_PINCTRL_SET_BASE
1040 // Description : The lowest-numbered pin that will be affected by a SET PINS or
1041 //               SET PINDIRS instruction. The data written to this pin is the
1042 //               least-significant bit of the SET data.
1043 #define PIO_SM0_PINCTRL_SET_BASE_RESET  _u(0x00)
1044 #define PIO_SM0_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
1045 #define PIO_SM0_PINCTRL_SET_BASE_MSB    _u(9)
1046 #define PIO_SM0_PINCTRL_SET_BASE_LSB    _u(5)
1047 #define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW"
1048 // -----------------------------------------------------------------------------
1049 // Field       : PIO_SM0_PINCTRL_OUT_BASE
1050 // Description : The lowest-numbered pin that will be affected by an OUT PINS,
1051 //               OUT PINDIRS or MOV PINS instruction. The data written to this
1052 //               pin will always be the least-significant bit of the OUT or MOV
1053 //               data.
1054 #define PIO_SM0_PINCTRL_OUT_BASE_RESET  _u(0x00)
1055 #define PIO_SM0_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
1056 #define PIO_SM0_PINCTRL_OUT_BASE_MSB    _u(4)
1057 #define PIO_SM0_PINCTRL_OUT_BASE_LSB    _u(0)
1058 #define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW"
1059 // =============================================================================
1060 // Register    : PIO_SM1_CLKDIV
1061 // Description : Clock divisor register for state machine 1
1062 //               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
1063 #define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0)
1064 #define PIO_SM1_CLKDIV_BITS   _u(0xffffff00)
1065 #define PIO_SM1_CLKDIV_RESET  _u(0x00010000)
1066 // -----------------------------------------------------------------------------
1067 // Field       : PIO_SM1_CLKDIV_INT
1068 // Description : Effective frequency is sysclk/(int + frac/256).
1069 //               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
1070 //               be 0.
1071 #define PIO_SM1_CLKDIV_INT_RESET  _u(0x0001)
1072 #define PIO_SM1_CLKDIV_INT_BITS   _u(0xffff0000)
1073 #define PIO_SM1_CLKDIV_INT_MSB    _u(31)
1074 #define PIO_SM1_CLKDIV_INT_LSB    _u(16)
1075 #define PIO_SM1_CLKDIV_INT_ACCESS "RW"
1076 // -----------------------------------------------------------------------------
1077 // Field       : PIO_SM1_CLKDIV_FRAC
1078 // Description : Fractional part of clock divisor
1079 #define PIO_SM1_CLKDIV_FRAC_RESET  _u(0x00)
1080 #define PIO_SM1_CLKDIV_FRAC_BITS   _u(0x0000ff00)
1081 #define PIO_SM1_CLKDIV_FRAC_MSB    _u(15)
1082 #define PIO_SM1_CLKDIV_FRAC_LSB    _u(8)
1083 #define PIO_SM1_CLKDIV_FRAC_ACCESS "RW"
1084 // =============================================================================
1085 // Register    : PIO_SM1_EXECCTRL
1086 // Description : Execution/behavioural settings for state machine 1
1087 #define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4)
1088 #define PIO_SM1_EXECCTRL_BITS   _u(0xffffff9f)
1089 #define PIO_SM1_EXECCTRL_RESET  _u(0x0001f000)
1090 // -----------------------------------------------------------------------------
1091 // Field       : PIO_SM1_EXECCTRL_EXEC_STALLED
1092 // Description : If 1, an instruction written to SMx_INSTR is stalled, and
1093 //               latched by the state machine. Will clear to 0 once this
1094 //               instruction completes.
1095 #define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
1096 #define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
1097 #define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB    _u(31)
1098 #define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB    _u(31)
1099 #define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO"
1100 // -----------------------------------------------------------------------------
1101 // Field       : PIO_SM1_EXECCTRL_SIDE_EN
1102 // Description : If 1, the MSB of the Delay/Side-set instruction field is used
1103 //               as side-set enable, rather than a side-set data bit. This
1104 //               allows instructions to perform side-set optionally, rather than
1105 //               on every instruction, but the maximum possible side-set width
1106 //               is reduced from 5 to 4. Note that the value of
1107 //               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
1108 #define PIO_SM1_EXECCTRL_SIDE_EN_RESET  _u(0x0)
1109 #define PIO_SM1_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
1110 #define PIO_SM1_EXECCTRL_SIDE_EN_MSB    _u(30)
1111 #define PIO_SM1_EXECCTRL_SIDE_EN_LSB    _u(30)
1112 #define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW"
1113 // -----------------------------------------------------------------------------
1114 // Field       : PIO_SM1_EXECCTRL_SIDE_PINDIR
1115 // Description : If 1, side-set data is asserted to pin directions, instead of
1116 //               pin values
1117 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
1118 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
1119 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
1120 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
1121 #define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
1122 // -----------------------------------------------------------------------------
1123 // Field       : PIO_SM1_EXECCTRL_JMP_PIN
1124 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by
1125 //               input mapping.
1126 #define PIO_SM1_EXECCTRL_JMP_PIN_RESET  _u(0x00)
1127 #define PIO_SM1_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
1128 #define PIO_SM1_EXECCTRL_JMP_PIN_MSB    _u(28)
1129 #define PIO_SM1_EXECCTRL_JMP_PIN_LSB    _u(24)
1130 #define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW"
1131 // -----------------------------------------------------------------------------
1132 // Field       : PIO_SM1_EXECCTRL_OUT_EN_SEL
1133 // Description : Which data bit to use for inline OUT enable
1134 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
1135 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
1136 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
1137 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
1138 #define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
1139 // -----------------------------------------------------------------------------
1140 // Field       : PIO_SM1_EXECCTRL_INLINE_OUT_EN
1141 // Description : If 1, use a bit of OUT data as an auxiliary write enable
1142 //               When used in conjunction with OUT_STICKY, writes with an enable
1143 //               of 0 will
1144 //               deassert the latest pin write. This can create useful
1145 //               masking/override behaviour
1146 //               due to the priority ordering of state machine pin writes (SM0 <
1147 //               SM1 < ...)
1148 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
1149 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
1150 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
1151 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
1152 #define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
1153 // -----------------------------------------------------------------------------
1154 // Field       : PIO_SM1_EXECCTRL_OUT_STICKY
1155 // Description : Continuously assert the most recent OUT/SET to the pins
1156 #define PIO_SM1_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
1157 #define PIO_SM1_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
1158 #define PIO_SM1_EXECCTRL_OUT_STICKY_MSB    _u(17)
1159 #define PIO_SM1_EXECCTRL_OUT_STICKY_LSB    _u(17)
1160 #define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW"
1161 // -----------------------------------------------------------------------------
1162 // Field       : PIO_SM1_EXECCTRL_WRAP_TOP
1163 // Description : After reaching this address, execution is wrapped to
1164 //               wrap_bottom.
1165 //               If the instruction is a jump, and the jump condition is true,
1166 //               the jump takes priority.
1167 #define PIO_SM1_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
1168 #define PIO_SM1_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
1169 #define PIO_SM1_EXECCTRL_WRAP_TOP_MSB    _u(16)
1170 #define PIO_SM1_EXECCTRL_WRAP_TOP_LSB    _u(12)
1171 #define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW"
1172 // -----------------------------------------------------------------------------
1173 // Field       : PIO_SM1_EXECCTRL_WRAP_BOTTOM
1174 // Description : After reaching wrap_top, execution is wrapped to this address.
1175 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
1176 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
1177 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
1178 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
1179 #define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
1180 // -----------------------------------------------------------------------------
1181 // Field       : PIO_SM1_EXECCTRL_STATUS_SEL
1182 // Description : Comparison used for the MOV x, STATUS instruction.
1183 //               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
1184 //               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
1185 #define PIO_SM1_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
1186 #define PIO_SM1_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
1187 #define PIO_SM1_EXECCTRL_STATUS_SEL_MSB           _u(4)
1188 #define PIO_SM1_EXECCTRL_STATUS_SEL_LSB           _u(4)
1189 #define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS        "RW"
1190 #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
1191 #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
1192 // -----------------------------------------------------------------------------
1193 // Field       : PIO_SM1_EXECCTRL_STATUS_N
1194 // Description : Comparison level for the MOV x, STATUS instruction
1195 #define PIO_SM1_EXECCTRL_STATUS_N_RESET  _u(0x0)
1196 #define PIO_SM1_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
1197 #define PIO_SM1_EXECCTRL_STATUS_N_MSB    _u(3)
1198 #define PIO_SM1_EXECCTRL_STATUS_N_LSB    _u(0)
1199 #define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW"
1200 // =============================================================================
1201 // Register    : PIO_SM1_SHIFTCTRL
1202 // Description : Control behaviour of the input/output shift registers for state
1203 //               machine 1
1204 #define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8)
1205 #define PIO_SM1_SHIFTCTRL_BITS   _u(0xffff0000)
1206 #define PIO_SM1_SHIFTCTRL_RESET  _u(0x000c0000)
1207 // -----------------------------------------------------------------------------
1208 // Field       : PIO_SM1_SHIFTCTRL_FJOIN_RX
1209 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
1210 //               as deep.
1211 //               TX FIFO is disabled as a result (always reads as both full and
1212 //               empty).
1213 //               FIFOs are flushed when this bit is changed.
1214 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
1215 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
1216 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
1217 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
1218 #define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
1219 // -----------------------------------------------------------------------------
1220 // Field       : PIO_SM1_SHIFTCTRL_FJOIN_TX
1221 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
1222 //               as deep.
1223 //               RX FIFO is disabled as a result (always reads as both full and
1224 //               empty).
1225 //               FIFOs are flushed when this bit is changed.
1226 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
1227 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
1228 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
1229 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
1230 #define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
1231 // -----------------------------------------------------------------------------
1232 // Field       : PIO_SM1_SHIFTCTRL_PULL_THRESH
1233 // Description : Number of bits shifted out of OSR before autopull, or
1234 //               conditional pull (PULL IFEMPTY), will take place.
1235 //               Write 0 for value of 32.
1236 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
1237 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
1238 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
1239 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
1240 #define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
1241 // -----------------------------------------------------------------------------
1242 // Field       : PIO_SM1_SHIFTCTRL_PUSH_THRESH
1243 // Description : Number of bits shifted into ISR before autopush, or conditional
1244 //               push (PUSH IFFULL), will take place.
1245 //               Write 0 for value of 32.
1246 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
1247 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
1248 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
1249 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
1250 #define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
1251 // -----------------------------------------------------------------------------
1252 // Field       : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR
1253 // Description : 1 = shift out of output shift register to right. 0 = to left.
1254 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
1255 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
1256 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
1257 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
1258 #define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
1259 // -----------------------------------------------------------------------------
1260 // Field       : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR
1261 // Description : 1 = shift input shift register to right (data enters from
1262 //               left). 0 = to left.
1263 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
1264 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
1265 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
1266 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
1267 #define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
1268 // -----------------------------------------------------------------------------
1269 // Field       : PIO_SM1_SHIFTCTRL_AUTOPULL
1270 // Description : Pull automatically when the output shift register is emptied,
1271 //               i.e. on or following an OUT instruction which causes the output
1272 //               shift counter to reach or exceed PULL_THRESH.
1273 #define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
1274 #define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
1275 #define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB    _u(17)
1276 #define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB    _u(17)
1277 #define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW"
1278 // -----------------------------------------------------------------------------
1279 // Field       : PIO_SM1_SHIFTCTRL_AUTOPUSH
1280 // Description : Push automatically when the input shift register is filled,
1281 //               i.e. on an IN instruction which causes the input shift counter
1282 //               to reach or exceed PUSH_THRESH.
1283 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
1284 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
1285 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
1286 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
1287 #define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
1288 // =============================================================================
1289 // Register    : PIO_SM1_ADDR
1290 // Description : Current instruction address of state machine 1
1291 #define PIO_SM1_ADDR_OFFSET _u(0x000000ec)
1292 #define PIO_SM1_ADDR_BITS   _u(0x0000001f)
1293 #define PIO_SM1_ADDR_RESET  _u(0x00000000)
1294 #define PIO_SM1_ADDR_MSB    _u(4)
1295 #define PIO_SM1_ADDR_LSB    _u(0)
1296 #define PIO_SM1_ADDR_ACCESS "RO"
1297 // =============================================================================
1298 // Register    : PIO_SM1_INSTR
1299 // Description : Read to see the instruction currently addressed by state
1300 //               machine 1's program counter
1301 //               Write to execute an instruction immediately (including jumps)
1302 //               and then resume execution.
1303 #define PIO_SM1_INSTR_OFFSET _u(0x000000f0)
1304 #define PIO_SM1_INSTR_BITS   _u(0x0000ffff)
1305 #define PIO_SM1_INSTR_RESET  "-"
1306 #define PIO_SM1_INSTR_MSB    _u(15)
1307 #define PIO_SM1_INSTR_LSB    _u(0)
1308 #define PIO_SM1_INSTR_ACCESS "RW"
1309 // =============================================================================
1310 // Register    : PIO_SM1_PINCTRL
1311 // Description : State machine pin control
1312 #define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4)
1313 #define PIO_SM1_PINCTRL_BITS   _u(0xffffffff)
1314 #define PIO_SM1_PINCTRL_RESET  _u(0x14000000)
1315 // -----------------------------------------------------------------------------
1316 // Field       : PIO_SM1_PINCTRL_SIDESET_COUNT
1317 // Description : The number of MSBs of the Delay/Side-set instruction field
1318 //               which are used for side-set. Inclusive of the enable bit, if
1319 //               present. Minimum of 0 (all delay bits, no side-set) and maximum
1320 //               of 5 (all side-set, no delay).
1321 #define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
1322 #define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
1323 #define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB    _u(31)
1324 #define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB    _u(29)
1325 #define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW"
1326 // -----------------------------------------------------------------------------
1327 // Field       : PIO_SM1_PINCTRL_SET_COUNT
1328 // Description : The number of pins asserted by a SET. In the range 0 to 5
1329 //               inclusive.
1330 #define PIO_SM1_PINCTRL_SET_COUNT_RESET  _u(0x5)
1331 #define PIO_SM1_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
1332 #define PIO_SM1_PINCTRL_SET_COUNT_MSB    _u(28)
1333 #define PIO_SM1_PINCTRL_SET_COUNT_LSB    _u(26)
1334 #define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW"
1335 // -----------------------------------------------------------------------------
1336 // Field       : PIO_SM1_PINCTRL_OUT_COUNT
1337 // Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
1338 //               PINS instruction. In the range 0 to 32 inclusive.
1339 #define PIO_SM1_PINCTRL_OUT_COUNT_RESET  _u(0x00)
1340 #define PIO_SM1_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
1341 #define PIO_SM1_PINCTRL_OUT_COUNT_MSB    _u(25)
1342 #define PIO_SM1_PINCTRL_OUT_COUNT_LSB    _u(20)
1343 #define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW"
1344 // -----------------------------------------------------------------------------
1345 // Field       : PIO_SM1_PINCTRL_IN_BASE
1346 // Description : The pin which is mapped to the least-significant bit of a state
1347 //               machine's IN data bus. Higher-numbered pins are mapped to
1348 //               consecutively more-significant data bits, with a modulo of 32
1349 //               applied to pin number.
1350 #define PIO_SM1_PINCTRL_IN_BASE_RESET  _u(0x00)
1351 #define PIO_SM1_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
1352 #define PIO_SM1_PINCTRL_IN_BASE_MSB    _u(19)
1353 #define PIO_SM1_PINCTRL_IN_BASE_LSB    _u(15)
1354 #define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW"
1355 // -----------------------------------------------------------------------------
1356 // Field       : PIO_SM1_PINCTRL_SIDESET_BASE
1357 // Description : The lowest-numbered pin that will be affected by a side-set
1358 //               operation. The MSBs of an instruction's side-set/delay field
1359 //               (up to 5, determined by SIDESET_COUNT) are used for side-set
1360 //               data, with the remaining LSBs used for delay. The
1361 //               least-significant bit of the side-set portion is the bit
1362 //               written to this pin, with more-significant bits written to
1363 //               higher-numbered pins.
1364 #define PIO_SM1_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
1365 #define PIO_SM1_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
1366 #define PIO_SM1_PINCTRL_SIDESET_BASE_MSB    _u(14)
1367 #define PIO_SM1_PINCTRL_SIDESET_BASE_LSB    _u(10)
1368 #define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW"
1369 // -----------------------------------------------------------------------------
1370 // Field       : PIO_SM1_PINCTRL_SET_BASE
1371 // Description : The lowest-numbered pin that will be affected by a SET PINS or
1372 //               SET PINDIRS instruction. The data written to this pin is the
1373 //               least-significant bit of the SET data.
1374 #define PIO_SM1_PINCTRL_SET_BASE_RESET  _u(0x00)
1375 #define PIO_SM1_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
1376 #define PIO_SM1_PINCTRL_SET_BASE_MSB    _u(9)
1377 #define PIO_SM1_PINCTRL_SET_BASE_LSB    _u(5)
1378 #define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW"
1379 // -----------------------------------------------------------------------------
1380 // Field       : PIO_SM1_PINCTRL_OUT_BASE
1381 // Description : The lowest-numbered pin that will be affected by an OUT PINS,
1382 //               OUT PINDIRS or MOV PINS instruction. The data written to this
1383 //               pin will always be the least-significant bit of the OUT or MOV
1384 //               data.
1385 #define PIO_SM1_PINCTRL_OUT_BASE_RESET  _u(0x00)
1386 #define PIO_SM1_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
1387 #define PIO_SM1_PINCTRL_OUT_BASE_MSB    _u(4)
1388 #define PIO_SM1_PINCTRL_OUT_BASE_LSB    _u(0)
1389 #define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW"
1390 // =============================================================================
1391 // Register    : PIO_SM2_CLKDIV
1392 // Description : Clock divisor register for state machine 2
1393 //               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
1394 #define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8)
1395 #define PIO_SM2_CLKDIV_BITS   _u(0xffffff00)
1396 #define PIO_SM2_CLKDIV_RESET  _u(0x00010000)
1397 // -----------------------------------------------------------------------------
1398 // Field       : PIO_SM2_CLKDIV_INT
1399 // Description : Effective frequency is sysclk/(int + frac/256).
1400 //               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
1401 //               be 0.
1402 #define PIO_SM2_CLKDIV_INT_RESET  _u(0x0001)
1403 #define PIO_SM2_CLKDIV_INT_BITS   _u(0xffff0000)
1404 #define PIO_SM2_CLKDIV_INT_MSB    _u(31)
1405 #define PIO_SM2_CLKDIV_INT_LSB    _u(16)
1406 #define PIO_SM2_CLKDIV_INT_ACCESS "RW"
1407 // -----------------------------------------------------------------------------
1408 // Field       : PIO_SM2_CLKDIV_FRAC
1409 // Description : Fractional part of clock divisor
1410 #define PIO_SM2_CLKDIV_FRAC_RESET  _u(0x00)
1411 #define PIO_SM2_CLKDIV_FRAC_BITS   _u(0x0000ff00)
1412 #define PIO_SM2_CLKDIV_FRAC_MSB    _u(15)
1413 #define PIO_SM2_CLKDIV_FRAC_LSB    _u(8)
1414 #define PIO_SM2_CLKDIV_FRAC_ACCESS "RW"
1415 // =============================================================================
1416 // Register    : PIO_SM2_EXECCTRL
1417 // Description : Execution/behavioural settings for state machine 2
1418 #define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc)
1419 #define PIO_SM2_EXECCTRL_BITS   _u(0xffffff9f)
1420 #define PIO_SM2_EXECCTRL_RESET  _u(0x0001f000)
1421 // -----------------------------------------------------------------------------
1422 // Field       : PIO_SM2_EXECCTRL_EXEC_STALLED
1423 // Description : If 1, an instruction written to SMx_INSTR is stalled, and
1424 //               latched by the state machine. Will clear to 0 once this
1425 //               instruction completes.
1426 #define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
1427 #define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
1428 #define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB    _u(31)
1429 #define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB    _u(31)
1430 #define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO"
1431 // -----------------------------------------------------------------------------
1432 // Field       : PIO_SM2_EXECCTRL_SIDE_EN
1433 // Description : If 1, the MSB of the Delay/Side-set instruction field is used
1434 //               as side-set enable, rather than a side-set data bit. This
1435 //               allows instructions to perform side-set optionally, rather than
1436 //               on every instruction, but the maximum possible side-set width
1437 //               is reduced from 5 to 4. Note that the value of
1438 //               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
1439 #define PIO_SM2_EXECCTRL_SIDE_EN_RESET  _u(0x0)
1440 #define PIO_SM2_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
1441 #define PIO_SM2_EXECCTRL_SIDE_EN_MSB    _u(30)
1442 #define PIO_SM2_EXECCTRL_SIDE_EN_LSB    _u(30)
1443 #define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW"
1444 // -----------------------------------------------------------------------------
1445 // Field       : PIO_SM2_EXECCTRL_SIDE_PINDIR
1446 // Description : If 1, side-set data is asserted to pin directions, instead of
1447 //               pin values
1448 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
1449 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
1450 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
1451 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
1452 #define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
1453 // -----------------------------------------------------------------------------
1454 // Field       : PIO_SM2_EXECCTRL_JMP_PIN
1455 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by
1456 //               input mapping.
1457 #define PIO_SM2_EXECCTRL_JMP_PIN_RESET  _u(0x00)
1458 #define PIO_SM2_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
1459 #define PIO_SM2_EXECCTRL_JMP_PIN_MSB    _u(28)
1460 #define PIO_SM2_EXECCTRL_JMP_PIN_LSB    _u(24)
1461 #define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW"
1462 // -----------------------------------------------------------------------------
1463 // Field       : PIO_SM2_EXECCTRL_OUT_EN_SEL
1464 // Description : Which data bit to use for inline OUT enable
1465 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
1466 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
1467 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
1468 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
1469 #define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
1470 // -----------------------------------------------------------------------------
1471 // Field       : PIO_SM2_EXECCTRL_INLINE_OUT_EN
1472 // Description : If 1, use a bit of OUT data as an auxiliary write enable
1473 //               When used in conjunction with OUT_STICKY, writes with an enable
1474 //               of 0 will
1475 //               deassert the latest pin write. This can create useful
1476 //               masking/override behaviour
1477 //               due to the priority ordering of state machine pin writes (SM0 <
1478 //               SM1 < ...)
1479 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
1480 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
1481 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
1482 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
1483 #define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
1484 // -----------------------------------------------------------------------------
1485 // Field       : PIO_SM2_EXECCTRL_OUT_STICKY
1486 // Description : Continuously assert the most recent OUT/SET to the pins
1487 #define PIO_SM2_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
1488 #define PIO_SM2_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
1489 #define PIO_SM2_EXECCTRL_OUT_STICKY_MSB    _u(17)
1490 #define PIO_SM2_EXECCTRL_OUT_STICKY_LSB    _u(17)
1491 #define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW"
1492 // -----------------------------------------------------------------------------
1493 // Field       : PIO_SM2_EXECCTRL_WRAP_TOP
1494 // Description : After reaching this address, execution is wrapped to
1495 //               wrap_bottom.
1496 //               If the instruction is a jump, and the jump condition is true,
1497 //               the jump takes priority.
1498 #define PIO_SM2_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
1499 #define PIO_SM2_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
1500 #define PIO_SM2_EXECCTRL_WRAP_TOP_MSB    _u(16)
1501 #define PIO_SM2_EXECCTRL_WRAP_TOP_LSB    _u(12)
1502 #define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW"
1503 // -----------------------------------------------------------------------------
1504 // Field       : PIO_SM2_EXECCTRL_WRAP_BOTTOM
1505 // Description : After reaching wrap_top, execution is wrapped to this address.
1506 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
1507 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
1508 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
1509 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
1510 #define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
1511 // -----------------------------------------------------------------------------
1512 // Field       : PIO_SM2_EXECCTRL_STATUS_SEL
1513 // Description : Comparison used for the MOV x, STATUS instruction.
1514 //               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
1515 //               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
1516 #define PIO_SM2_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
1517 #define PIO_SM2_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
1518 #define PIO_SM2_EXECCTRL_STATUS_SEL_MSB           _u(4)
1519 #define PIO_SM2_EXECCTRL_STATUS_SEL_LSB           _u(4)
1520 #define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS        "RW"
1521 #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
1522 #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
1523 // -----------------------------------------------------------------------------
1524 // Field       : PIO_SM2_EXECCTRL_STATUS_N
1525 // Description : Comparison level for the MOV x, STATUS instruction
1526 #define PIO_SM2_EXECCTRL_STATUS_N_RESET  _u(0x0)
1527 #define PIO_SM2_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
1528 #define PIO_SM2_EXECCTRL_STATUS_N_MSB    _u(3)
1529 #define PIO_SM2_EXECCTRL_STATUS_N_LSB    _u(0)
1530 #define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW"
1531 // =============================================================================
1532 // Register    : PIO_SM2_SHIFTCTRL
1533 // Description : Control behaviour of the input/output shift registers for state
1534 //               machine 2
1535 #define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100)
1536 #define PIO_SM2_SHIFTCTRL_BITS   _u(0xffff0000)
1537 #define PIO_SM2_SHIFTCTRL_RESET  _u(0x000c0000)
1538 // -----------------------------------------------------------------------------
1539 // Field       : PIO_SM2_SHIFTCTRL_FJOIN_RX
1540 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
1541 //               as deep.
1542 //               TX FIFO is disabled as a result (always reads as both full and
1543 //               empty).
1544 //               FIFOs are flushed when this bit is changed.
1545 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
1546 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
1547 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
1548 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
1549 #define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
1550 // -----------------------------------------------------------------------------
1551 // Field       : PIO_SM2_SHIFTCTRL_FJOIN_TX
1552 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
1553 //               as deep.
1554 //               RX FIFO is disabled as a result (always reads as both full and
1555 //               empty).
1556 //               FIFOs are flushed when this bit is changed.
1557 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
1558 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
1559 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
1560 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
1561 #define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
1562 // -----------------------------------------------------------------------------
1563 // Field       : PIO_SM2_SHIFTCTRL_PULL_THRESH
1564 // Description : Number of bits shifted out of OSR before autopull, or
1565 //               conditional pull (PULL IFEMPTY), will take place.
1566 //               Write 0 for value of 32.
1567 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
1568 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
1569 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
1570 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
1571 #define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
1572 // -----------------------------------------------------------------------------
1573 // Field       : PIO_SM2_SHIFTCTRL_PUSH_THRESH
1574 // Description : Number of bits shifted into ISR before autopush, or conditional
1575 //               push (PUSH IFFULL), will take place.
1576 //               Write 0 for value of 32.
1577 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
1578 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
1579 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
1580 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
1581 #define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
1582 // -----------------------------------------------------------------------------
1583 // Field       : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR
1584 // Description : 1 = shift out of output shift register to right. 0 = to left.
1585 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
1586 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
1587 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
1588 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
1589 #define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
1590 // -----------------------------------------------------------------------------
1591 // Field       : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR
1592 // Description : 1 = shift input shift register to right (data enters from
1593 //               left). 0 = to left.
1594 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
1595 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
1596 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
1597 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
1598 #define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
1599 // -----------------------------------------------------------------------------
1600 // Field       : PIO_SM2_SHIFTCTRL_AUTOPULL
1601 // Description : Pull automatically when the output shift register is emptied,
1602 //               i.e. on or following an OUT instruction which causes the output
1603 //               shift counter to reach or exceed PULL_THRESH.
1604 #define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
1605 #define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
1606 #define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB    _u(17)
1607 #define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB    _u(17)
1608 #define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW"
1609 // -----------------------------------------------------------------------------
1610 // Field       : PIO_SM2_SHIFTCTRL_AUTOPUSH
1611 // Description : Push automatically when the input shift register is filled,
1612 //               i.e. on an IN instruction which causes the input shift counter
1613 //               to reach or exceed PUSH_THRESH.
1614 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
1615 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
1616 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
1617 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
1618 #define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
1619 // =============================================================================
1620 // Register    : PIO_SM2_ADDR
1621 // Description : Current instruction address of state machine 2
1622 #define PIO_SM2_ADDR_OFFSET _u(0x00000104)
1623 #define PIO_SM2_ADDR_BITS   _u(0x0000001f)
1624 #define PIO_SM2_ADDR_RESET  _u(0x00000000)
1625 #define PIO_SM2_ADDR_MSB    _u(4)
1626 #define PIO_SM2_ADDR_LSB    _u(0)
1627 #define PIO_SM2_ADDR_ACCESS "RO"
1628 // =============================================================================
1629 // Register    : PIO_SM2_INSTR
1630 // Description : Read to see the instruction currently addressed by state
1631 //               machine 2's program counter
1632 //               Write to execute an instruction immediately (including jumps)
1633 //               and then resume execution.
1634 #define PIO_SM2_INSTR_OFFSET _u(0x00000108)
1635 #define PIO_SM2_INSTR_BITS   _u(0x0000ffff)
1636 #define PIO_SM2_INSTR_RESET  "-"
1637 #define PIO_SM2_INSTR_MSB    _u(15)
1638 #define PIO_SM2_INSTR_LSB    _u(0)
1639 #define PIO_SM2_INSTR_ACCESS "RW"
1640 // =============================================================================
1641 // Register    : PIO_SM2_PINCTRL
1642 // Description : State machine pin control
1643 #define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c)
1644 #define PIO_SM2_PINCTRL_BITS   _u(0xffffffff)
1645 #define PIO_SM2_PINCTRL_RESET  _u(0x14000000)
1646 // -----------------------------------------------------------------------------
1647 // Field       : PIO_SM2_PINCTRL_SIDESET_COUNT
1648 // Description : The number of MSBs of the Delay/Side-set instruction field
1649 //               which are used for side-set. Inclusive of the enable bit, if
1650 //               present. Minimum of 0 (all delay bits, no side-set) and maximum
1651 //               of 5 (all side-set, no delay).
1652 #define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
1653 #define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
1654 #define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB    _u(31)
1655 #define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB    _u(29)
1656 #define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW"
1657 // -----------------------------------------------------------------------------
1658 // Field       : PIO_SM2_PINCTRL_SET_COUNT
1659 // Description : The number of pins asserted by a SET. In the range 0 to 5
1660 //               inclusive.
1661 #define PIO_SM2_PINCTRL_SET_COUNT_RESET  _u(0x5)
1662 #define PIO_SM2_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
1663 #define PIO_SM2_PINCTRL_SET_COUNT_MSB    _u(28)
1664 #define PIO_SM2_PINCTRL_SET_COUNT_LSB    _u(26)
1665 #define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW"
1666 // -----------------------------------------------------------------------------
1667 // Field       : PIO_SM2_PINCTRL_OUT_COUNT
1668 // Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
1669 //               PINS instruction. In the range 0 to 32 inclusive.
1670 #define PIO_SM2_PINCTRL_OUT_COUNT_RESET  _u(0x00)
1671 #define PIO_SM2_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
1672 #define PIO_SM2_PINCTRL_OUT_COUNT_MSB    _u(25)
1673 #define PIO_SM2_PINCTRL_OUT_COUNT_LSB    _u(20)
1674 #define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW"
1675 // -----------------------------------------------------------------------------
1676 // Field       : PIO_SM2_PINCTRL_IN_BASE
1677 // Description : The pin which is mapped to the least-significant bit of a state
1678 //               machine's IN data bus. Higher-numbered pins are mapped to
1679 //               consecutively more-significant data bits, with a modulo of 32
1680 //               applied to pin number.
1681 #define PIO_SM2_PINCTRL_IN_BASE_RESET  _u(0x00)
1682 #define PIO_SM2_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
1683 #define PIO_SM2_PINCTRL_IN_BASE_MSB    _u(19)
1684 #define PIO_SM2_PINCTRL_IN_BASE_LSB    _u(15)
1685 #define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW"
1686 // -----------------------------------------------------------------------------
1687 // Field       : PIO_SM2_PINCTRL_SIDESET_BASE
1688 // Description : The lowest-numbered pin that will be affected by a side-set
1689 //               operation. The MSBs of an instruction's side-set/delay field
1690 //               (up to 5, determined by SIDESET_COUNT) are used for side-set
1691 //               data, with the remaining LSBs used for delay. The
1692 //               least-significant bit of the side-set portion is the bit
1693 //               written to this pin, with more-significant bits written to
1694 //               higher-numbered pins.
1695 #define PIO_SM2_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
1696 #define PIO_SM2_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
1697 #define PIO_SM2_PINCTRL_SIDESET_BASE_MSB    _u(14)
1698 #define PIO_SM2_PINCTRL_SIDESET_BASE_LSB    _u(10)
1699 #define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW"
1700 // -----------------------------------------------------------------------------
1701 // Field       : PIO_SM2_PINCTRL_SET_BASE
1702 // Description : The lowest-numbered pin that will be affected by a SET PINS or
1703 //               SET PINDIRS instruction. The data written to this pin is the
1704 //               least-significant bit of the SET data.
1705 #define PIO_SM2_PINCTRL_SET_BASE_RESET  _u(0x00)
1706 #define PIO_SM2_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
1707 #define PIO_SM2_PINCTRL_SET_BASE_MSB    _u(9)
1708 #define PIO_SM2_PINCTRL_SET_BASE_LSB    _u(5)
1709 #define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW"
1710 // -----------------------------------------------------------------------------
1711 // Field       : PIO_SM2_PINCTRL_OUT_BASE
1712 // Description : The lowest-numbered pin that will be affected by an OUT PINS,
1713 //               OUT PINDIRS or MOV PINS instruction. The data written to this
1714 //               pin will always be the least-significant bit of the OUT or MOV
1715 //               data.
1716 #define PIO_SM2_PINCTRL_OUT_BASE_RESET  _u(0x00)
1717 #define PIO_SM2_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
1718 #define PIO_SM2_PINCTRL_OUT_BASE_MSB    _u(4)
1719 #define PIO_SM2_PINCTRL_OUT_BASE_LSB    _u(0)
1720 #define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW"
1721 // =============================================================================
1722 // Register    : PIO_SM3_CLKDIV
1723 // Description : Clock divisor register for state machine 3
1724 //               Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
1725 #define PIO_SM3_CLKDIV_OFFSET _u(0x00000110)
1726 #define PIO_SM3_CLKDIV_BITS   _u(0xffffff00)
1727 #define PIO_SM3_CLKDIV_RESET  _u(0x00010000)
1728 // -----------------------------------------------------------------------------
1729 // Field       : PIO_SM3_CLKDIV_INT
1730 // Description : Effective frequency is sysclk/(int + frac/256).
1731 //               Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
1732 //               be 0.
1733 #define PIO_SM3_CLKDIV_INT_RESET  _u(0x0001)
1734 #define PIO_SM3_CLKDIV_INT_BITS   _u(0xffff0000)
1735 #define PIO_SM3_CLKDIV_INT_MSB    _u(31)
1736 #define PIO_SM3_CLKDIV_INT_LSB    _u(16)
1737 #define PIO_SM3_CLKDIV_INT_ACCESS "RW"
1738 // -----------------------------------------------------------------------------
1739 // Field       : PIO_SM3_CLKDIV_FRAC
1740 // Description : Fractional part of clock divisor
1741 #define PIO_SM3_CLKDIV_FRAC_RESET  _u(0x00)
1742 #define PIO_SM3_CLKDIV_FRAC_BITS   _u(0x0000ff00)
1743 #define PIO_SM3_CLKDIV_FRAC_MSB    _u(15)
1744 #define PIO_SM3_CLKDIV_FRAC_LSB    _u(8)
1745 #define PIO_SM3_CLKDIV_FRAC_ACCESS "RW"
1746 // =============================================================================
1747 // Register    : PIO_SM3_EXECCTRL
1748 // Description : Execution/behavioural settings for state machine 3
1749 #define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114)
1750 #define PIO_SM3_EXECCTRL_BITS   _u(0xffffff9f)
1751 #define PIO_SM3_EXECCTRL_RESET  _u(0x0001f000)
1752 // -----------------------------------------------------------------------------
1753 // Field       : PIO_SM3_EXECCTRL_EXEC_STALLED
1754 // Description : If 1, an instruction written to SMx_INSTR is stalled, and
1755 //               latched by the state machine. Will clear to 0 once this
1756 //               instruction completes.
1757 #define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET  _u(0x0)
1758 #define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS   _u(0x80000000)
1759 #define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB    _u(31)
1760 #define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB    _u(31)
1761 #define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO"
1762 // -----------------------------------------------------------------------------
1763 // Field       : PIO_SM3_EXECCTRL_SIDE_EN
1764 // Description : If 1, the MSB of the Delay/Side-set instruction field is used
1765 //               as side-set enable, rather than a side-set data bit. This
1766 //               allows instructions to perform side-set optionally, rather than
1767 //               on every instruction, but the maximum possible side-set width
1768 //               is reduced from 5 to 4. Note that the value of
1769 //               PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
1770 #define PIO_SM3_EXECCTRL_SIDE_EN_RESET  _u(0x0)
1771 #define PIO_SM3_EXECCTRL_SIDE_EN_BITS   _u(0x40000000)
1772 #define PIO_SM3_EXECCTRL_SIDE_EN_MSB    _u(30)
1773 #define PIO_SM3_EXECCTRL_SIDE_EN_LSB    _u(30)
1774 #define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW"
1775 // -----------------------------------------------------------------------------
1776 // Field       : PIO_SM3_EXECCTRL_SIDE_PINDIR
1777 // Description : If 1, side-set data is asserted to pin directions, instead of
1778 //               pin values
1779 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET  _u(0x0)
1780 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS   _u(0x20000000)
1781 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB    _u(29)
1782 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB    _u(29)
1783 #define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
1784 // -----------------------------------------------------------------------------
1785 // Field       : PIO_SM3_EXECCTRL_JMP_PIN
1786 // Description : The GPIO number to use as condition for JMP PIN. Unaffected by
1787 //               input mapping.
1788 #define PIO_SM3_EXECCTRL_JMP_PIN_RESET  _u(0x00)
1789 #define PIO_SM3_EXECCTRL_JMP_PIN_BITS   _u(0x1f000000)
1790 #define PIO_SM3_EXECCTRL_JMP_PIN_MSB    _u(28)
1791 #define PIO_SM3_EXECCTRL_JMP_PIN_LSB    _u(24)
1792 #define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW"
1793 // -----------------------------------------------------------------------------
1794 // Field       : PIO_SM3_EXECCTRL_OUT_EN_SEL
1795 // Description : Which data bit to use for inline OUT enable
1796 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET  _u(0x00)
1797 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS   _u(0x00f80000)
1798 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB    _u(23)
1799 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB    _u(19)
1800 #define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
1801 // -----------------------------------------------------------------------------
1802 // Field       : PIO_SM3_EXECCTRL_INLINE_OUT_EN
1803 // Description : If 1, use a bit of OUT data as an auxiliary write enable
1804 //               When used in conjunction with OUT_STICKY, writes with an enable
1805 //               of 0 will
1806 //               deassert the latest pin write. This can create useful
1807 //               masking/override behaviour
1808 //               due to the priority ordering of state machine pin writes (SM0 <
1809 //               SM1 < ...)
1810 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET  _u(0x0)
1811 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS   _u(0x00040000)
1812 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB    _u(18)
1813 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB    _u(18)
1814 #define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
1815 // -----------------------------------------------------------------------------
1816 // Field       : PIO_SM3_EXECCTRL_OUT_STICKY
1817 // Description : Continuously assert the most recent OUT/SET to the pins
1818 #define PIO_SM3_EXECCTRL_OUT_STICKY_RESET  _u(0x0)
1819 #define PIO_SM3_EXECCTRL_OUT_STICKY_BITS   _u(0x00020000)
1820 #define PIO_SM3_EXECCTRL_OUT_STICKY_MSB    _u(17)
1821 #define PIO_SM3_EXECCTRL_OUT_STICKY_LSB    _u(17)
1822 #define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW"
1823 // -----------------------------------------------------------------------------
1824 // Field       : PIO_SM3_EXECCTRL_WRAP_TOP
1825 // Description : After reaching this address, execution is wrapped to
1826 //               wrap_bottom.
1827 //               If the instruction is a jump, and the jump condition is true,
1828 //               the jump takes priority.
1829 #define PIO_SM3_EXECCTRL_WRAP_TOP_RESET  _u(0x1f)
1830 #define PIO_SM3_EXECCTRL_WRAP_TOP_BITS   _u(0x0001f000)
1831 #define PIO_SM3_EXECCTRL_WRAP_TOP_MSB    _u(16)
1832 #define PIO_SM3_EXECCTRL_WRAP_TOP_LSB    _u(12)
1833 #define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW"
1834 // -----------------------------------------------------------------------------
1835 // Field       : PIO_SM3_EXECCTRL_WRAP_BOTTOM
1836 // Description : After reaching wrap_top, execution is wrapped to this address.
1837 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET  _u(0x00)
1838 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS   _u(0x00000f80)
1839 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB    _u(11)
1840 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB    _u(7)
1841 #define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
1842 // -----------------------------------------------------------------------------
1843 // Field       : PIO_SM3_EXECCTRL_STATUS_SEL
1844 // Description : Comparison used for the MOV x, STATUS instruction.
1845 //               0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
1846 //               0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
1847 #define PIO_SM3_EXECCTRL_STATUS_SEL_RESET         _u(0x0)
1848 #define PIO_SM3_EXECCTRL_STATUS_SEL_BITS          _u(0x00000010)
1849 #define PIO_SM3_EXECCTRL_STATUS_SEL_MSB           _u(4)
1850 #define PIO_SM3_EXECCTRL_STATUS_SEL_LSB           _u(4)
1851 #define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS        "RW"
1852 #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
1853 #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
1854 // -----------------------------------------------------------------------------
1855 // Field       : PIO_SM3_EXECCTRL_STATUS_N
1856 // Description : Comparison level for the MOV x, STATUS instruction
1857 #define PIO_SM3_EXECCTRL_STATUS_N_RESET  _u(0x0)
1858 #define PIO_SM3_EXECCTRL_STATUS_N_BITS   _u(0x0000000f)
1859 #define PIO_SM3_EXECCTRL_STATUS_N_MSB    _u(3)
1860 #define PIO_SM3_EXECCTRL_STATUS_N_LSB    _u(0)
1861 #define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW"
1862 // =============================================================================
1863 // Register    : PIO_SM3_SHIFTCTRL
1864 // Description : Control behaviour of the input/output shift registers for state
1865 //               machine 3
1866 #define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118)
1867 #define PIO_SM3_SHIFTCTRL_BITS   _u(0xffff0000)
1868 #define PIO_SM3_SHIFTCTRL_RESET  _u(0x000c0000)
1869 // -----------------------------------------------------------------------------
1870 // Field       : PIO_SM3_SHIFTCTRL_FJOIN_RX
1871 // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
1872 //               as deep.
1873 //               TX FIFO is disabled as a result (always reads as both full and
1874 //               empty).
1875 //               FIFOs are flushed when this bit is changed.
1876 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET  _u(0x0)
1877 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS   _u(0x80000000)
1878 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB    _u(31)
1879 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB    _u(31)
1880 #define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
1881 // -----------------------------------------------------------------------------
1882 // Field       : PIO_SM3_SHIFTCTRL_FJOIN_TX
1883 // Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
1884 //               as deep.
1885 //               RX FIFO is disabled as a result (always reads as both full and
1886 //               empty).
1887 //               FIFOs are flushed when this bit is changed.
1888 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET  _u(0x0)
1889 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS   _u(0x40000000)
1890 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB    _u(30)
1891 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB    _u(30)
1892 #define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
1893 // -----------------------------------------------------------------------------
1894 // Field       : PIO_SM3_SHIFTCTRL_PULL_THRESH
1895 // Description : Number of bits shifted out of OSR before autopull, or
1896 //               conditional pull (PULL IFEMPTY), will take place.
1897 //               Write 0 for value of 32.
1898 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET  _u(0x00)
1899 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS   _u(0x3e000000)
1900 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB    _u(29)
1901 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB    _u(25)
1902 #define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
1903 // -----------------------------------------------------------------------------
1904 // Field       : PIO_SM3_SHIFTCTRL_PUSH_THRESH
1905 // Description : Number of bits shifted into ISR before autopush, or conditional
1906 //               push (PUSH IFFULL), will take place.
1907 //               Write 0 for value of 32.
1908 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET  _u(0x00)
1909 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS   _u(0x01f00000)
1910 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB    _u(24)
1911 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB    _u(20)
1912 #define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
1913 // -----------------------------------------------------------------------------
1914 // Field       : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR
1915 // Description : 1 = shift out of output shift register to right. 0 = to left.
1916 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET  _u(0x1)
1917 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS   _u(0x00080000)
1918 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB    _u(19)
1919 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB    _u(19)
1920 #define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
1921 // -----------------------------------------------------------------------------
1922 // Field       : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR
1923 // Description : 1 = shift input shift register to right (data enters from
1924 //               left). 0 = to left.
1925 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET  _u(0x1)
1926 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS   _u(0x00040000)
1927 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB    _u(18)
1928 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB    _u(18)
1929 #define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
1930 // -----------------------------------------------------------------------------
1931 // Field       : PIO_SM3_SHIFTCTRL_AUTOPULL
1932 // Description : Pull automatically when the output shift register is emptied,
1933 //               i.e. on or following an OUT instruction which causes the output
1934 //               shift counter to reach or exceed PULL_THRESH.
1935 #define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET  _u(0x0)
1936 #define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS   _u(0x00020000)
1937 #define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB    _u(17)
1938 #define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB    _u(17)
1939 #define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW"
1940 // -----------------------------------------------------------------------------
1941 // Field       : PIO_SM3_SHIFTCTRL_AUTOPUSH
1942 // Description : Push automatically when the input shift register is filled,
1943 //               i.e. on an IN instruction which causes the input shift counter
1944 //               to reach or exceed PUSH_THRESH.
1945 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET  _u(0x0)
1946 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS   _u(0x00010000)
1947 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB    _u(16)
1948 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB    _u(16)
1949 #define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
1950 // =============================================================================
1951 // Register    : PIO_SM3_ADDR
1952 // Description : Current instruction address of state machine 3
1953 #define PIO_SM3_ADDR_OFFSET _u(0x0000011c)
1954 #define PIO_SM3_ADDR_BITS   _u(0x0000001f)
1955 #define PIO_SM3_ADDR_RESET  _u(0x00000000)
1956 #define PIO_SM3_ADDR_MSB    _u(4)
1957 #define PIO_SM3_ADDR_LSB    _u(0)
1958 #define PIO_SM3_ADDR_ACCESS "RO"
1959 // =============================================================================
1960 // Register    : PIO_SM3_INSTR
1961 // Description : Read to see the instruction currently addressed by state
1962 //               machine 3's program counter
1963 //               Write to execute an instruction immediately (including jumps)
1964 //               and then resume execution.
1965 #define PIO_SM3_INSTR_OFFSET _u(0x00000120)
1966 #define PIO_SM3_INSTR_BITS   _u(0x0000ffff)
1967 #define PIO_SM3_INSTR_RESET  "-"
1968 #define PIO_SM3_INSTR_MSB    _u(15)
1969 #define PIO_SM3_INSTR_LSB    _u(0)
1970 #define PIO_SM3_INSTR_ACCESS "RW"
1971 // =============================================================================
1972 // Register    : PIO_SM3_PINCTRL
1973 // Description : State machine pin control
1974 #define PIO_SM3_PINCTRL_OFFSET _u(0x00000124)
1975 #define PIO_SM3_PINCTRL_BITS   _u(0xffffffff)
1976 #define PIO_SM3_PINCTRL_RESET  _u(0x14000000)
1977 // -----------------------------------------------------------------------------
1978 // Field       : PIO_SM3_PINCTRL_SIDESET_COUNT
1979 // Description : The number of MSBs of the Delay/Side-set instruction field
1980 //               which are used for side-set. Inclusive of the enable bit, if
1981 //               present. Minimum of 0 (all delay bits, no side-set) and maximum
1982 //               of 5 (all side-set, no delay).
1983 #define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET  _u(0x0)
1984 #define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS   _u(0xe0000000)
1985 #define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB    _u(31)
1986 #define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB    _u(29)
1987 #define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW"
1988 // -----------------------------------------------------------------------------
1989 // Field       : PIO_SM3_PINCTRL_SET_COUNT
1990 // Description : The number of pins asserted by a SET. In the range 0 to 5
1991 //               inclusive.
1992 #define PIO_SM3_PINCTRL_SET_COUNT_RESET  _u(0x5)
1993 #define PIO_SM3_PINCTRL_SET_COUNT_BITS   _u(0x1c000000)
1994 #define PIO_SM3_PINCTRL_SET_COUNT_MSB    _u(28)
1995 #define PIO_SM3_PINCTRL_SET_COUNT_LSB    _u(26)
1996 #define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW"
1997 // -----------------------------------------------------------------------------
1998 // Field       : PIO_SM3_PINCTRL_OUT_COUNT
1999 // Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
2000 //               PINS instruction. In the range 0 to 32 inclusive.
2001 #define PIO_SM3_PINCTRL_OUT_COUNT_RESET  _u(0x00)
2002 #define PIO_SM3_PINCTRL_OUT_COUNT_BITS   _u(0x03f00000)
2003 #define PIO_SM3_PINCTRL_OUT_COUNT_MSB    _u(25)
2004 #define PIO_SM3_PINCTRL_OUT_COUNT_LSB    _u(20)
2005 #define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW"
2006 // -----------------------------------------------------------------------------
2007 // Field       : PIO_SM3_PINCTRL_IN_BASE
2008 // Description : The pin which is mapped to the least-significant bit of a state
2009 //               machine's IN data bus. Higher-numbered pins are mapped to
2010 //               consecutively more-significant data bits, with a modulo of 32
2011 //               applied to pin number.
2012 #define PIO_SM3_PINCTRL_IN_BASE_RESET  _u(0x00)
2013 #define PIO_SM3_PINCTRL_IN_BASE_BITS   _u(0x000f8000)
2014 #define PIO_SM3_PINCTRL_IN_BASE_MSB    _u(19)
2015 #define PIO_SM3_PINCTRL_IN_BASE_LSB    _u(15)
2016 #define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW"
2017 // -----------------------------------------------------------------------------
2018 // Field       : PIO_SM3_PINCTRL_SIDESET_BASE
2019 // Description : The lowest-numbered pin that will be affected by a side-set
2020 //               operation. The MSBs of an instruction's side-set/delay field
2021 //               (up to 5, determined by SIDESET_COUNT) are used for side-set
2022 //               data, with the remaining LSBs used for delay. The
2023 //               least-significant bit of the side-set portion is the bit
2024 //               written to this pin, with more-significant bits written to
2025 //               higher-numbered pins.
2026 #define PIO_SM3_PINCTRL_SIDESET_BASE_RESET  _u(0x00)
2027 #define PIO_SM3_PINCTRL_SIDESET_BASE_BITS   _u(0x00007c00)
2028 #define PIO_SM3_PINCTRL_SIDESET_BASE_MSB    _u(14)
2029 #define PIO_SM3_PINCTRL_SIDESET_BASE_LSB    _u(10)
2030 #define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW"
2031 // -----------------------------------------------------------------------------
2032 // Field       : PIO_SM3_PINCTRL_SET_BASE
2033 // Description : The lowest-numbered pin that will be affected by a SET PINS or
2034 //               SET PINDIRS instruction. The data written to this pin is the
2035 //               least-significant bit of the SET data.
2036 #define PIO_SM3_PINCTRL_SET_BASE_RESET  _u(0x00)
2037 #define PIO_SM3_PINCTRL_SET_BASE_BITS   _u(0x000003e0)
2038 #define PIO_SM3_PINCTRL_SET_BASE_MSB    _u(9)
2039 #define PIO_SM3_PINCTRL_SET_BASE_LSB    _u(5)
2040 #define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW"
2041 // -----------------------------------------------------------------------------
2042 // Field       : PIO_SM3_PINCTRL_OUT_BASE
2043 // Description : The lowest-numbered pin that will be affected by an OUT PINS,
2044 //               OUT PINDIRS or MOV PINS instruction. The data written to this
2045 //               pin will always be the least-significant bit of the OUT or MOV
2046 //               data.
2047 #define PIO_SM3_PINCTRL_OUT_BASE_RESET  _u(0x00)
2048 #define PIO_SM3_PINCTRL_OUT_BASE_BITS   _u(0x0000001f)
2049 #define PIO_SM3_PINCTRL_OUT_BASE_MSB    _u(4)
2050 #define PIO_SM3_PINCTRL_OUT_BASE_LSB    _u(0)
2051 #define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW"
2052 // =============================================================================
2053 // Register    : PIO_INTR
2054 // Description : Raw Interrupts
2055 #define PIO_INTR_OFFSET _u(0x00000128)
2056 #define PIO_INTR_BITS   _u(0x00000fff)
2057 #define PIO_INTR_RESET  _u(0x00000000)
2058 // -----------------------------------------------------------------------------
2059 // Field       : PIO_INTR_SM3
2060 // Description : None
2061 #define PIO_INTR_SM3_RESET  _u(0x0)
2062 #define PIO_INTR_SM3_BITS   _u(0x00000800)
2063 #define PIO_INTR_SM3_MSB    _u(11)
2064 #define PIO_INTR_SM3_LSB    _u(11)
2065 #define PIO_INTR_SM3_ACCESS "RO"
2066 // -----------------------------------------------------------------------------
2067 // Field       : PIO_INTR_SM2
2068 // Description : None
2069 #define PIO_INTR_SM2_RESET  _u(0x0)
2070 #define PIO_INTR_SM2_BITS   _u(0x00000400)
2071 #define PIO_INTR_SM2_MSB    _u(10)
2072 #define PIO_INTR_SM2_LSB    _u(10)
2073 #define PIO_INTR_SM2_ACCESS "RO"
2074 // -----------------------------------------------------------------------------
2075 // Field       : PIO_INTR_SM1
2076 // Description : None
2077 #define PIO_INTR_SM1_RESET  _u(0x0)
2078 #define PIO_INTR_SM1_BITS   _u(0x00000200)
2079 #define PIO_INTR_SM1_MSB    _u(9)
2080 #define PIO_INTR_SM1_LSB    _u(9)
2081 #define PIO_INTR_SM1_ACCESS "RO"
2082 // -----------------------------------------------------------------------------
2083 // Field       : PIO_INTR_SM0
2084 // Description : None
2085 #define PIO_INTR_SM0_RESET  _u(0x0)
2086 #define PIO_INTR_SM0_BITS   _u(0x00000100)
2087 #define PIO_INTR_SM0_MSB    _u(8)
2088 #define PIO_INTR_SM0_LSB    _u(8)
2089 #define PIO_INTR_SM0_ACCESS "RO"
2090 // -----------------------------------------------------------------------------
2091 // Field       : PIO_INTR_SM3_TXNFULL
2092 // Description : None
2093 #define PIO_INTR_SM3_TXNFULL_RESET  _u(0x0)
2094 #define PIO_INTR_SM3_TXNFULL_BITS   _u(0x00000080)
2095 #define PIO_INTR_SM3_TXNFULL_MSB    _u(7)
2096 #define PIO_INTR_SM3_TXNFULL_LSB    _u(7)
2097 #define PIO_INTR_SM3_TXNFULL_ACCESS "RO"
2098 // -----------------------------------------------------------------------------
2099 // Field       : PIO_INTR_SM2_TXNFULL
2100 // Description : None
2101 #define PIO_INTR_SM2_TXNFULL_RESET  _u(0x0)
2102 #define PIO_INTR_SM2_TXNFULL_BITS   _u(0x00000040)
2103 #define PIO_INTR_SM2_TXNFULL_MSB    _u(6)
2104 #define PIO_INTR_SM2_TXNFULL_LSB    _u(6)
2105 #define PIO_INTR_SM2_TXNFULL_ACCESS "RO"
2106 // -----------------------------------------------------------------------------
2107 // Field       : PIO_INTR_SM1_TXNFULL
2108 // Description : None
2109 #define PIO_INTR_SM1_TXNFULL_RESET  _u(0x0)
2110 #define PIO_INTR_SM1_TXNFULL_BITS   _u(0x00000020)
2111 #define PIO_INTR_SM1_TXNFULL_MSB    _u(5)
2112 #define PIO_INTR_SM1_TXNFULL_LSB    _u(5)
2113 #define PIO_INTR_SM1_TXNFULL_ACCESS "RO"
2114 // -----------------------------------------------------------------------------
2115 // Field       : PIO_INTR_SM0_TXNFULL
2116 // Description : None
2117 #define PIO_INTR_SM0_TXNFULL_RESET  _u(0x0)
2118 #define PIO_INTR_SM0_TXNFULL_BITS   _u(0x00000010)
2119 #define PIO_INTR_SM0_TXNFULL_MSB    _u(4)
2120 #define PIO_INTR_SM0_TXNFULL_LSB    _u(4)
2121 #define PIO_INTR_SM0_TXNFULL_ACCESS "RO"
2122 // -----------------------------------------------------------------------------
2123 // Field       : PIO_INTR_SM3_RXNEMPTY
2124 // Description : None
2125 #define PIO_INTR_SM3_RXNEMPTY_RESET  _u(0x0)
2126 #define PIO_INTR_SM3_RXNEMPTY_BITS   _u(0x00000008)
2127 #define PIO_INTR_SM3_RXNEMPTY_MSB    _u(3)
2128 #define PIO_INTR_SM3_RXNEMPTY_LSB    _u(3)
2129 #define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO"
2130 // -----------------------------------------------------------------------------
2131 // Field       : PIO_INTR_SM2_RXNEMPTY
2132 // Description : None
2133 #define PIO_INTR_SM2_RXNEMPTY_RESET  _u(0x0)
2134 #define PIO_INTR_SM2_RXNEMPTY_BITS   _u(0x00000004)
2135 #define PIO_INTR_SM2_RXNEMPTY_MSB    _u(2)
2136 #define PIO_INTR_SM2_RXNEMPTY_LSB    _u(2)
2137 #define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO"
2138 // -----------------------------------------------------------------------------
2139 // Field       : PIO_INTR_SM1_RXNEMPTY
2140 // Description : None
2141 #define PIO_INTR_SM1_RXNEMPTY_RESET  _u(0x0)
2142 #define PIO_INTR_SM1_RXNEMPTY_BITS   _u(0x00000002)
2143 #define PIO_INTR_SM1_RXNEMPTY_MSB    _u(1)
2144 #define PIO_INTR_SM1_RXNEMPTY_LSB    _u(1)
2145 #define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO"
2146 // -----------------------------------------------------------------------------
2147 // Field       : PIO_INTR_SM0_RXNEMPTY
2148 // Description : None
2149 #define PIO_INTR_SM0_RXNEMPTY_RESET  _u(0x0)
2150 #define PIO_INTR_SM0_RXNEMPTY_BITS   _u(0x00000001)
2151 #define PIO_INTR_SM0_RXNEMPTY_MSB    _u(0)
2152 #define PIO_INTR_SM0_RXNEMPTY_LSB    _u(0)
2153 #define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO"
2154 // =============================================================================
2155 // Register    : PIO_IRQ0_INTE
2156 // Description : Interrupt Enable for irq0
2157 #define PIO_IRQ0_INTE_OFFSET _u(0x0000012c)
2158 #define PIO_IRQ0_INTE_BITS   _u(0x00000fff)
2159 #define PIO_IRQ0_INTE_RESET  _u(0x00000000)
2160 // -----------------------------------------------------------------------------
2161 // Field       : PIO_IRQ0_INTE_SM3
2162 // Description : None
2163 #define PIO_IRQ0_INTE_SM3_RESET  _u(0x0)
2164 #define PIO_IRQ0_INTE_SM3_BITS   _u(0x00000800)
2165 #define PIO_IRQ0_INTE_SM3_MSB    _u(11)
2166 #define PIO_IRQ0_INTE_SM3_LSB    _u(11)
2167 #define PIO_IRQ0_INTE_SM3_ACCESS "RW"
2168 // -----------------------------------------------------------------------------
2169 // Field       : PIO_IRQ0_INTE_SM2
2170 // Description : None
2171 #define PIO_IRQ0_INTE_SM2_RESET  _u(0x0)
2172 #define PIO_IRQ0_INTE_SM2_BITS   _u(0x00000400)
2173 #define PIO_IRQ0_INTE_SM2_MSB    _u(10)
2174 #define PIO_IRQ0_INTE_SM2_LSB    _u(10)
2175 #define PIO_IRQ0_INTE_SM2_ACCESS "RW"
2176 // -----------------------------------------------------------------------------
2177 // Field       : PIO_IRQ0_INTE_SM1
2178 // Description : None
2179 #define PIO_IRQ0_INTE_SM1_RESET  _u(0x0)
2180 #define PIO_IRQ0_INTE_SM1_BITS   _u(0x00000200)
2181 #define PIO_IRQ0_INTE_SM1_MSB    _u(9)
2182 #define PIO_IRQ0_INTE_SM1_LSB    _u(9)
2183 #define PIO_IRQ0_INTE_SM1_ACCESS "RW"
2184 // -----------------------------------------------------------------------------
2185 // Field       : PIO_IRQ0_INTE_SM0
2186 // Description : None
2187 #define PIO_IRQ0_INTE_SM0_RESET  _u(0x0)
2188 #define PIO_IRQ0_INTE_SM0_BITS   _u(0x00000100)
2189 #define PIO_IRQ0_INTE_SM0_MSB    _u(8)
2190 #define PIO_IRQ0_INTE_SM0_LSB    _u(8)
2191 #define PIO_IRQ0_INTE_SM0_ACCESS "RW"
2192 // -----------------------------------------------------------------------------
2193 // Field       : PIO_IRQ0_INTE_SM3_TXNFULL
2194 // Description : None
2195 #define PIO_IRQ0_INTE_SM3_TXNFULL_RESET  _u(0x0)
2196 #define PIO_IRQ0_INTE_SM3_TXNFULL_BITS   _u(0x00000080)
2197 #define PIO_IRQ0_INTE_SM3_TXNFULL_MSB    _u(7)
2198 #define PIO_IRQ0_INTE_SM3_TXNFULL_LSB    _u(7)
2199 #define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW"
2200 // -----------------------------------------------------------------------------
2201 // Field       : PIO_IRQ0_INTE_SM2_TXNFULL
2202 // Description : None
2203 #define PIO_IRQ0_INTE_SM2_TXNFULL_RESET  _u(0x0)
2204 #define PIO_IRQ0_INTE_SM2_TXNFULL_BITS   _u(0x00000040)
2205 #define PIO_IRQ0_INTE_SM2_TXNFULL_MSB    _u(6)
2206 #define PIO_IRQ0_INTE_SM2_TXNFULL_LSB    _u(6)
2207 #define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW"
2208 // -----------------------------------------------------------------------------
2209 // Field       : PIO_IRQ0_INTE_SM1_TXNFULL
2210 // Description : None
2211 #define PIO_IRQ0_INTE_SM1_TXNFULL_RESET  _u(0x0)
2212 #define PIO_IRQ0_INTE_SM1_TXNFULL_BITS   _u(0x00000020)
2213 #define PIO_IRQ0_INTE_SM1_TXNFULL_MSB    _u(5)
2214 #define PIO_IRQ0_INTE_SM1_TXNFULL_LSB    _u(5)
2215 #define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW"
2216 // -----------------------------------------------------------------------------
2217 // Field       : PIO_IRQ0_INTE_SM0_TXNFULL
2218 // Description : None
2219 #define PIO_IRQ0_INTE_SM0_TXNFULL_RESET  _u(0x0)
2220 #define PIO_IRQ0_INTE_SM0_TXNFULL_BITS   _u(0x00000010)
2221 #define PIO_IRQ0_INTE_SM0_TXNFULL_MSB    _u(4)
2222 #define PIO_IRQ0_INTE_SM0_TXNFULL_LSB    _u(4)
2223 #define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW"
2224 // -----------------------------------------------------------------------------
2225 // Field       : PIO_IRQ0_INTE_SM3_RXNEMPTY
2226 // Description : None
2227 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET  _u(0x0)
2228 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS   _u(0x00000008)
2229 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB    _u(3)
2230 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB    _u(3)
2231 #define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW"
2232 // -----------------------------------------------------------------------------
2233 // Field       : PIO_IRQ0_INTE_SM2_RXNEMPTY
2234 // Description : None
2235 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET  _u(0x0)
2236 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS   _u(0x00000004)
2237 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB    _u(2)
2238 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB    _u(2)
2239 #define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW"
2240 // -----------------------------------------------------------------------------
2241 // Field       : PIO_IRQ0_INTE_SM1_RXNEMPTY
2242 // Description : None
2243 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET  _u(0x0)
2244 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS   _u(0x00000002)
2245 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB    _u(1)
2246 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB    _u(1)
2247 #define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW"
2248 // -----------------------------------------------------------------------------
2249 // Field       : PIO_IRQ0_INTE_SM0_RXNEMPTY
2250 // Description : None
2251 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET  _u(0x0)
2252 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS   _u(0x00000001)
2253 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB    _u(0)
2254 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB    _u(0)
2255 #define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW"
2256 // =============================================================================
2257 // Register    : PIO_IRQ0_INTF
2258 // Description : Interrupt Force for irq0
2259 #define PIO_IRQ0_INTF_OFFSET _u(0x00000130)
2260 #define PIO_IRQ0_INTF_BITS   _u(0x00000fff)
2261 #define PIO_IRQ0_INTF_RESET  _u(0x00000000)
2262 // -----------------------------------------------------------------------------
2263 // Field       : PIO_IRQ0_INTF_SM3
2264 // Description : None
2265 #define PIO_IRQ0_INTF_SM3_RESET  _u(0x0)
2266 #define PIO_IRQ0_INTF_SM3_BITS   _u(0x00000800)
2267 #define PIO_IRQ0_INTF_SM3_MSB    _u(11)
2268 #define PIO_IRQ0_INTF_SM3_LSB    _u(11)
2269 #define PIO_IRQ0_INTF_SM3_ACCESS "RW"
2270 // -----------------------------------------------------------------------------
2271 // Field       : PIO_IRQ0_INTF_SM2
2272 // Description : None
2273 #define PIO_IRQ0_INTF_SM2_RESET  _u(0x0)
2274 #define PIO_IRQ0_INTF_SM2_BITS   _u(0x00000400)
2275 #define PIO_IRQ0_INTF_SM2_MSB    _u(10)
2276 #define PIO_IRQ0_INTF_SM2_LSB    _u(10)
2277 #define PIO_IRQ0_INTF_SM2_ACCESS "RW"
2278 // -----------------------------------------------------------------------------
2279 // Field       : PIO_IRQ0_INTF_SM1
2280 // Description : None
2281 #define PIO_IRQ0_INTF_SM1_RESET  _u(0x0)
2282 #define PIO_IRQ0_INTF_SM1_BITS   _u(0x00000200)
2283 #define PIO_IRQ0_INTF_SM1_MSB    _u(9)
2284 #define PIO_IRQ0_INTF_SM1_LSB    _u(9)
2285 #define PIO_IRQ0_INTF_SM1_ACCESS "RW"
2286 // -----------------------------------------------------------------------------
2287 // Field       : PIO_IRQ0_INTF_SM0
2288 // Description : None
2289 #define PIO_IRQ0_INTF_SM0_RESET  _u(0x0)
2290 #define PIO_IRQ0_INTF_SM0_BITS   _u(0x00000100)
2291 #define PIO_IRQ0_INTF_SM0_MSB    _u(8)
2292 #define PIO_IRQ0_INTF_SM0_LSB    _u(8)
2293 #define PIO_IRQ0_INTF_SM0_ACCESS "RW"
2294 // -----------------------------------------------------------------------------
2295 // Field       : PIO_IRQ0_INTF_SM3_TXNFULL
2296 // Description : None
2297 #define PIO_IRQ0_INTF_SM3_TXNFULL_RESET  _u(0x0)
2298 #define PIO_IRQ0_INTF_SM3_TXNFULL_BITS   _u(0x00000080)
2299 #define PIO_IRQ0_INTF_SM3_TXNFULL_MSB    _u(7)
2300 #define PIO_IRQ0_INTF_SM3_TXNFULL_LSB    _u(7)
2301 #define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW"
2302 // -----------------------------------------------------------------------------
2303 // Field       : PIO_IRQ0_INTF_SM2_TXNFULL
2304 // Description : None
2305 #define PIO_IRQ0_INTF_SM2_TXNFULL_RESET  _u(0x0)
2306 #define PIO_IRQ0_INTF_SM2_TXNFULL_BITS   _u(0x00000040)
2307 #define PIO_IRQ0_INTF_SM2_TXNFULL_MSB    _u(6)
2308 #define PIO_IRQ0_INTF_SM2_TXNFULL_LSB    _u(6)
2309 #define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW"
2310 // -----------------------------------------------------------------------------
2311 // Field       : PIO_IRQ0_INTF_SM1_TXNFULL
2312 // Description : None
2313 #define PIO_IRQ0_INTF_SM1_TXNFULL_RESET  _u(0x0)
2314 #define PIO_IRQ0_INTF_SM1_TXNFULL_BITS   _u(0x00000020)
2315 #define PIO_IRQ0_INTF_SM1_TXNFULL_MSB    _u(5)
2316 #define PIO_IRQ0_INTF_SM1_TXNFULL_LSB    _u(5)
2317 #define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW"
2318 // -----------------------------------------------------------------------------
2319 // Field       : PIO_IRQ0_INTF_SM0_TXNFULL
2320 // Description : None
2321 #define PIO_IRQ0_INTF_SM0_TXNFULL_RESET  _u(0x0)
2322 #define PIO_IRQ0_INTF_SM0_TXNFULL_BITS   _u(0x00000010)
2323 #define PIO_IRQ0_INTF_SM0_TXNFULL_MSB    _u(4)
2324 #define PIO_IRQ0_INTF_SM0_TXNFULL_LSB    _u(4)
2325 #define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW"
2326 // -----------------------------------------------------------------------------
2327 // Field       : PIO_IRQ0_INTF_SM3_RXNEMPTY
2328 // Description : None
2329 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET  _u(0x0)
2330 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS   _u(0x00000008)
2331 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB    _u(3)
2332 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB    _u(3)
2333 #define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW"
2334 // -----------------------------------------------------------------------------
2335 // Field       : PIO_IRQ0_INTF_SM2_RXNEMPTY
2336 // Description : None
2337 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET  _u(0x0)
2338 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS   _u(0x00000004)
2339 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB    _u(2)
2340 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB    _u(2)
2341 #define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW"
2342 // -----------------------------------------------------------------------------
2343 // Field       : PIO_IRQ0_INTF_SM1_RXNEMPTY
2344 // Description : None
2345 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET  _u(0x0)
2346 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS   _u(0x00000002)
2347 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB    _u(1)
2348 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB    _u(1)
2349 #define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW"
2350 // -----------------------------------------------------------------------------
2351 // Field       : PIO_IRQ0_INTF_SM0_RXNEMPTY
2352 // Description : None
2353 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET  _u(0x0)
2354 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS   _u(0x00000001)
2355 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB    _u(0)
2356 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB    _u(0)
2357 #define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW"
2358 // =============================================================================
2359 // Register    : PIO_IRQ0_INTS
2360 // Description : Interrupt status after masking & forcing for irq0
2361 #define PIO_IRQ0_INTS_OFFSET _u(0x00000134)
2362 #define PIO_IRQ0_INTS_BITS   _u(0x00000fff)
2363 #define PIO_IRQ0_INTS_RESET  _u(0x00000000)
2364 // -----------------------------------------------------------------------------
2365 // Field       : PIO_IRQ0_INTS_SM3
2366 // Description : None
2367 #define PIO_IRQ0_INTS_SM3_RESET  _u(0x0)
2368 #define PIO_IRQ0_INTS_SM3_BITS   _u(0x00000800)
2369 #define PIO_IRQ0_INTS_SM3_MSB    _u(11)
2370 #define PIO_IRQ0_INTS_SM3_LSB    _u(11)
2371 #define PIO_IRQ0_INTS_SM3_ACCESS "RO"
2372 // -----------------------------------------------------------------------------
2373 // Field       : PIO_IRQ0_INTS_SM2
2374 // Description : None
2375 #define PIO_IRQ0_INTS_SM2_RESET  _u(0x0)
2376 #define PIO_IRQ0_INTS_SM2_BITS   _u(0x00000400)
2377 #define PIO_IRQ0_INTS_SM2_MSB    _u(10)
2378 #define PIO_IRQ0_INTS_SM2_LSB    _u(10)
2379 #define PIO_IRQ0_INTS_SM2_ACCESS "RO"
2380 // -----------------------------------------------------------------------------
2381 // Field       : PIO_IRQ0_INTS_SM1
2382 // Description : None
2383 #define PIO_IRQ0_INTS_SM1_RESET  _u(0x0)
2384 #define PIO_IRQ0_INTS_SM1_BITS   _u(0x00000200)
2385 #define PIO_IRQ0_INTS_SM1_MSB    _u(9)
2386 #define PIO_IRQ0_INTS_SM1_LSB    _u(9)
2387 #define PIO_IRQ0_INTS_SM1_ACCESS "RO"
2388 // -----------------------------------------------------------------------------
2389 // Field       : PIO_IRQ0_INTS_SM0
2390 // Description : None
2391 #define PIO_IRQ0_INTS_SM0_RESET  _u(0x0)
2392 #define PIO_IRQ0_INTS_SM0_BITS   _u(0x00000100)
2393 #define PIO_IRQ0_INTS_SM0_MSB    _u(8)
2394 #define PIO_IRQ0_INTS_SM0_LSB    _u(8)
2395 #define PIO_IRQ0_INTS_SM0_ACCESS "RO"
2396 // -----------------------------------------------------------------------------
2397 // Field       : PIO_IRQ0_INTS_SM3_TXNFULL
2398 // Description : None
2399 #define PIO_IRQ0_INTS_SM3_TXNFULL_RESET  _u(0x0)
2400 #define PIO_IRQ0_INTS_SM3_TXNFULL_BITS   _u(0x00000080)
2401 #define PIO_IRQ0_INTS_SM3_TXNFULL_MSB    _u(7)
2402 #define PIO_IRQ0_INTS_SM3_TXNFULL_LSB    _u(7)
2403 #define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO"
2404 // -----------------------------------------------------------------------------
2405 // Field       : PIO_IRQ0_INTS_SM2_TXNFULL
2406 // Description : None
2407 #define PIO_IRQ0_INTS_SM2_TXNFULL_RESET  _u(0x0)
2408 #define PIO_IRQ0_INTS_SM2_TXNFULL_BITS   _u(0x00000040)
2409 #define PIO_IRQ0_INTS_SM2_TXNFULL_MSB    _u(6)
2410 #define PIO_IRQ0_INTS_SM2_TXNFULL_LSB    _u(6)
2411 #define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO"
2412 // -----------------------------------------------------------------------------
2413 // Field       : PIO_IRQ0_INTS_SM1_TXNFULL
2414 // Description : None
2415 #define PIO_IRQ0_INTS_SM1_TXNFULL_RESET  _u(0x0)
2416 #define PIO_IRQ0_INTS_SM1_TXNFULL_BITS   _u(0x00000020)
2417 #define PIO_IRQ0_INTS_SM1_TXNFULL_MSB    _u(5)
2418 #define PIO_IRQ0_INTS_SM1_TXNFULL_LSB    _u(5)
2419 #define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO"
2420 // -----------------------------------------------------------------------------
2421 // Field       : PIO_IRQ0_INTS_SM0_TXNFULL
2422 // Description : None
2423 #define PIO_IRQ0_INTS_SM0_TXNFULL_RESET  _u(0x0)
2424 #define PIO_IRQ0_INTS_SM0_TXNFULL_BITS   _u(0x00000010)
2425 #define PIO_IRQ0_INTS_SM0_TXNFULL_MSB    _u(4)
2426 #define PIO_IRQ0_INTS_SM0_TXNFULL_LSB    _u(4)
2427 #define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO"
2428 // -----------------------------------------------------------------------------
2429 // Field       : PIO_IRQ0_INTS_SM3_RXNEMPTY
2430 // Description : None
2431 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET  _u(0x0)
2432 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS   _u(0x00000008)
2433 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB    _u(3)
2434 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB    _u(3)
2435 #define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO"
2436 // -----------------------------------------------------------------------------
2437 // Field       : PIO_IRQ0_INTS_SM2_RXNEMPTY
2438 // Description : None
2439 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET  _u(0x0)
2440 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS   _u(0x00000004)
2441 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB    _u(2)
2442 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB    _u(2)
2443 #define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO"
2444 // -----------------------------------------------------------------------------
2445 // Field       : PIO_IRQ0_INTS_SM1_RXNEMPTY
2446 // Description : None
2447 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET  _u(0x0)
2448 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS   _u(0x00000002)
2449 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB    _u(1)
2450 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB    _u(1)
2451 #define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO"
2452 // -----------------------------------------------------------------------------
2453 // Field       : PIO_IRQ0_INTS_SM0_RXNEMPTY
2454 // Description : None
2455 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET  _u(0x0)
2456 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS   _u(0x00000001)
2457 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB    _u(0)
2458 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB    _u(0)
2459 #define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO"
2460 // =============================================================================
2461 // Register    : PIO_IRQ1_INTE
2462 // Description : Interrupt Enable for irq1
2463 #define PIO_IRQ1_INTE_OFFSET _u(0x00000138)
2464 #define PIO_IRQ1_INTE_BITS   _u(0x00000fff)
2465 #define PIO_IRQ1_INTE_RESET  _u(0x00000000)
2466 // -----------------------------------------------------------------------------
2467 // Field       : PIO_IRQ1_INTE_SM3
2468 // Description : None
2469 #define PIO_IRQ1_INTE_SM3_RESET  _u(0x0)
2470 #define PIO_IRQ1_INTE_SM3_BITS   _u(0x00000800)
2471 #define PIO_IRQ1_INTE_SM3_MSB    _u(11)
2472 #define PIO_IRQ1_INTE_SM3_LSB    _u(11)
2473 #define PIO_IRQ1_INTE_SM3_ACCESS "RW"
2474 // -----------------------------------------------------------------------------
2475 // Field       : PIO_IRQ1_INTE_SM2
2476 // Description : None
2477 #define PIO_IRQ1_INTE_SM2_RESET  _u(0x0)
2478 #define PIO_IRQ1_INTE_SM2_BITS   _u(0x00000400)
2479 #define PIO_IRQ1_INTE_SM2_MSB    _u(10)
2480 #define PIO_IRQ1_INTE_SM2_LSB    _u(10)
2481 #define PIO_IRQ1_INTE_SM2_ACCESS "RW"
2482 // -----------------------------------------------------------------------------
2483 // Field       : PIO_IRQ1_INTE_SM1
2484 // Description : None
2485 #define PIO_IRQ1_INTE_SM1_RESET  _u(0x0)
2486 #define PIO_IRQ1_INTE_SM1_BITS   _u(0x00000200)
2487 #define PIO_IRQ1_INTE_SM1_MSB    _u(9)
2488 #define PIO_IRQ1_INTE_SM1_LSB    _u(9)
2489 #define PIO_IRQ1_INTE_SM1_ACCESS "RW"
2490 // -----------------------------------------------------------------------------
2491 // Field       : PIO_IRQ1_INTE_SM0
2492 // Description : None
2493 #define PIO_IRQ1_INTE_SM0_RESET  _u(0x0)
2494 #define PIO_IRQ1_INTE_SM0_BITS   _u(0x00000100)
2495 #define PIO_IRQ1_INTE_SM0_MSB    _u(8)
2496 #define PIO_IRQ1_INTE_SM0_LSB    _u(8)
2497 #define PIO_IRQ1_INTE_SM0_ACCESS "RW"
2498 // -----------------------------------------------------------------------------
2499 // Field       : PIO_IRQ1_INTE_SM3_TXNFULL
2500 // Description : None
2501 #define PIO_IRQ1_INTE_SM3_TXNFULL_RESET  _u(0x0)
2502 #define PIO_IRQ1_INTE_SM3_TXNFULL_BITS   _u(0x00000080)
2503 #define PIO_IRQ1_INTE_SM3_TXNFULL_MSB    _u(7)
2504 #define PIO_IRQ1_INTE_SM3_TXNFULL_LSB    _u(7)
2505 #define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW"
2506 // -----------------------------------------------------------------------------
2507 // Field       : PIO_IRQ1_INTE_SM2_TXNFULL
2508 // Description : None
2509 #define PIO_IRQ1_INTE_SM2_TXNFULL_RESET  _u(0x0)
2510 #define PIO_IRQ1_INTE_SM2_TXNFULL_BITS   _u(0x00000040)
2511 #define PIO_IRQ1_INTE_SM2_TXNFULL_MSB    _u(6)
2512 #define PIO_IRQ1_INTE_SM2_TXNFULL_LSB    _u(6)
2513 #define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW"
2514 // -----------------------------------------------------------------------------
2515 // Field       : PIO_IRQ1_INTE_SM1_TXNFULL
2516 // Description : None
2517 #define PIO_IRQ1_INTE_SM1_TXNFULL_RESET  _u(0x0)
2518 #define PIO_IRQ1_INTE_SM1_TXNFULL_BITS   _u(0x00000020)
2519 #define PIO_IRQ1_INTE_SM1_TXNFULL_MSB    _u(5)
2520 #define PIO_IRQ1_INTE_SM1_TXNFULL_LSB    _u(5)
2521 #define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW"
2522 // -----------------------------------------------------------------------------
2523 // Field       : PIO_IRQ1_INTE_SM0_TXNFULL
2524 // Description : None
2525 #define PIO_IRQ1_INTE_SM0_TXNFULL_RESET  _u(0x0)
2526 #define PIO_IRQ1_INTE_SM0_TXNFULL_BITS   _u(0x00000010)
2527 #define PIO_IRQ1_INTE_SM0_TXNFULL_MSB    _u(4)
2528 #define PIO_IRQ1_INTE_SM0_TXNFULL_LSB    _u(4)
2529 #define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW"
2530 // -----------------------------------------------------------------------------
2531 // Field       : PIO_IRQ1_INTE_SM3_RXNEMPTY
2532 // Description : None
2533 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET  _u(0x0)
2534 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS   _u(0x00000008)
2535 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB    _u(3)
2536 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB    _u(3)
2537 #define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW"
2538 // -----------------------------------------------------------------------------
2539 // Field       : PIO_IRQ1_INTE_SM2_RXNEMPTY
2540 // Description : None
2541 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET  _u(0x0)
2542 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS   _u(0x00000004)
2543 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB    _u(2)
2544 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB    _u(2)
2545 #define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW"
2546 // -----------------------------------------------------------------------------
2547 // Field       : PIO_IRQ1_INTE_SM1_RXNEMPTY
2548 // Description : None
2549 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET  _u(0x0)
2550 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS   _u(0x00000002)
2551 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB    _u(1)
2552 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB    _u(1)
2553 #define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW"
2554 // -----------------------------------------------------------------------------
2555 // Field       : PIO_IRQ1_INTE_SM0_RXNEMPTY
2556 // Description : None
2557 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET  _u(0x0)
2558 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS   _u(0x00000001)
2559 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB    _u(0)
2560 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB    _u(0)
2561 #define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW"
2562 // =============================================================================
2563 // Register    : PIO_IRQ1_INTF
2564 // Description : Interrupt Force for irq1
2565 #define PIO_IRQ1_INTF_OFFSET _u(0x0000013c)
2566 #define PIO_IRQ1_INTF_BITS   _u(0x00000fff)
2567 #define PIO_IRQ1_INTF_RESET  _u(0x00000000)
2568 // -----------------------------------------------------------------------------
2569 // Field       : PIO_IRQ1_INTF_SM3
2570 // Description : None
2571 #define PIO_IRQ1_INTF_SM3_RESET  _u(0x0)
2572 #define PIO_IRQ1_INTF_SM3_BITS   _u(0x00000800)
2573 #define PIO_IRQ1_INTF_SM3_MSB    _u(11)
2574 #define PIO_IRQ1_INTF_SM3_LSB    _u(11)
2575 #define PIO_IRQ1_INTF_SM3_ACCESS "RW"
2576 // -----------------------------------------------------------------------------
2577 // Field       : PIO_IRQ1_INTF_SM2
2578 // Description : None
2579 #define PIO_IRQ1_INTF_SM2_RESET  _u(0x0)
2580 #define PIO_IRQ1_INTF_SM2_BITS   _u(0x00000400)
2581 #define PIO_IRQ1_INTF_SM2_MSB    _u(10)
2582 #define PIO_IRQ1_INTF_SM2_LSB    _u(10)
2583 #define PIO_IRQ1_INTF_SM2_ACCESS "RW"
2584 // -----------------------------------------------------------------------------
2585 // Field       : PIO_IRQ1_INTF_SM1
2586 // Description : None
2587 #define PIO_IRQ1_INTF_SM1_RESET  _u(0x0)
2588 #define PIO_IRQ1_INTF_SM1_BITS   _u(0x00000200)
2589 #define PIO_IRQ1_INTF_SM1_MSB    _u(9)
2590 #define PIO_IRQ1_INTF_SM1_LSB    _u(9)
2591 #define PIO_IRQ1_INTF_SM1_ACCESS "RW"
2592 // -----------------------------------------------------------------------------
2593 // Field       : PIO_IRQ1_INTF_SM0
2594 // Description : None
2595 #define PIO_IRQ1_INTF_SM0_RESET  _u(0x0)
2596 #define PIO_IRQ1_INTF_SM0_BITS   _u(0x00000100)
2597 #define PIO_IRQ1_INTF_SM0_MSB    _u(8)
2598 #define PIO_IRQ1_INTF_SM0_LSB    _u(8)
2599 #define PIO_IRQ1_INTF_SM0_ACCESS "RW"
2600 // -----------------------------------------------------------------------------
2601 // Field       : PIO_IRQ1_INTF_SM3_TXNFULL
2602 // Description : None
2603 #define PIO_IRQ1_INTF_SM3_TXNFULL_RESET  _u(0x0)
2604 #define PIO_IRQ1_INTF_SM3_TXNFULL_BITS   _u(0x00000080)
2605 #define PIO_IRQ1_INTF_SM3_TXNFULL_MSB    _u(7)
2606 #define PIO_IRQ1_INTF_SM3_TXNFULL_LSB    _u(7)
2607 #define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW"
2608 // -----------------------------------------------------------------------------
2609 // Field       : PIO_IRQ1_INTF_SM2_TXNFULL
2610 // Description : None
2611 #define PIO_IRQ1_INTF_SM2_TXNFULL_RESET  _u(0x0)
2612 #define PIO_IRQ1_INTF_SM2_TXNFULL_BITS   _u(0x00000040)
2613 #define PIO_IRQ1_INTF_SM2_TXNFULL_MSB    _u(6)
2614 #define PIO_IRQ1_INTF_SM2_TXNFULL_LSB    _u(6)
2615 #define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW"
2616 // -----------------------------------------------------------------------------
2617 // Field       : PIO_IRQ1_INTF_SM1_TXNFULL
2618 // Description : None
2619 #define PIO_IRQ1_INTF_SM1_TXNFULL_RESET  _u(0x0)
2620 #define PIO_IRQ1_INTF_SM1_TXNFULL_BITS   _u(0x00000020)
2621 #define PIO_IRQ1_INTF_SM1_TXNFULL_MSB    _u(5)
2622 #define PIO_IRQ1_INTF_SM1_TXNFULL_LSB    _u(5)
2623 #define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW"
2624 // -----------------------------------------------------------------------------
2625 // Field       : PIO_IRQ1_INTF_SM0_TXNFULL
2626 // Description : None
2627 #define PIO_IRQ1_INTF_SM0_TXNFULL_RESET  _u(0x0)
2628 #define PIO_IRQ1_INTF_SM0_TXNFULL_BITS   _u(0x00000010)
2629 #define PIO_IRQ1_INTF_SM0_TXNFULL_MSB    _u(4)
2630 #define PIO_IRQ1_INTF_SM0_TXNFULL_LSB    _u(4)
2631 #define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW"
2632 // -----------------------------------------------------------------------------
2633 // Field       : PIO_IRQ1_INTF_SM3_RXNEMPTY
2634 // Description : None
2635 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET  _u(0x0)
2636 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS   _u(0x00000008)
2637 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB    _u(3)
2638 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB    _u(3)
2639 #define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW"
2640 // -----------------------------------------------------------------------------
2641 // Field       : PIO_IRQ1_INTF_SM2_RXNEMPTY
2642 // Description : None
2643 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET  _u(0x0)
2644 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS   _u(0x00000004)
2645 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB    _u(2)
2646 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB    _u(2)
2647 #define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW"
2648 // -----------------------------------------------------------------------------
2649 // Field       : PIO_IRQ1_INTF_SM1_RXNEMPTY
2650 // Description : None
2651 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET  _u(0x0)
2652 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS   _u(0x00000002)
2653 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB    _u(1)
2654 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB    _u(1)
2655 #define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW"
2656 // -----------------------------------------------------------------------------
2657 // Field       : PIO_IRQ1_INTF_SM0_RXNEMPTY
2658 // Description : None
2659 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET  _u(0x0)
2660 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS   _u(0x00000001)
2661 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB    _u(0)
2662 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB    _u(0)
2663 #define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW"
2664 // =============================================================================
2665 // Register    : PIO_IRQ1_INTS
2666 // Description : Interrupt status after masking & forcing for irq1
2667 #define PIO_IRQ1_INTS_OFFSET _u(0x00000140)
2668 #define PIO_IRQ1_INTS_BITS   _u(0x00000fff)
2669 #define PIO_IRQ1_INTS_RESET  _u(0x00000000)
2670 // -----------------------------------------------------------------------------
2671 // Field       : PIO_IRQ1_INTS_SM3
2672 // Description : None
2673 #define PIO_IRQ1_INTS_SM3_RESET  _u(0x0)
2674 #define PIO_IRQ1_INTS_SM3_BITS   _u(0x00000800)
2675 #define PIO_IRQ1_INTS_SM3_MSB    _u(11)
2676 #define PIO_IRQ1_INTS_SM3_LSB    _u(11)
2677 #define PIO_IRQ1_INTS_SM3_ACCESS "RO"
2678 // -----------------------------------------------------------------------------
2679 // Field       : PIO_IRQ1_INTS_SM2
2680 // Description : None
2681 #define PIO_IRQ1_INTS_SM2_RESET  _u(0x0)
2682 #define PIO_IRQ1_INTS_SM2_BITS   _u(0x00000400)
2683 #define PIO_IRQ1_INTS_SM2_MSB    _u(10)
2684 #define PIO_IRQ1_INTS_SM2_LSB    _u(10)
2685 #define PIO_IRQ1_INTS_SM2_ACCESS "RO"
2686 // -----------------------------------------------------------------------------
2687 // Field       : PIO_IRQ1_INTS_SM1
2688 // Description : None
2689 #define PIO_IRQ1_INTS_SM1_RESET  _u(0x0)
2690 #define PIO_IRQ1_INTS_SM1_BITS   _u(0x00000200)
2691 #define PIO_IRQ1_INTS_SM1_MSB    _u(9)
2692 #define PIO_IRQ1_INTS_SM1_LSB    _u(9)
2693 #define PIO_IRQ1_INTS_SM1_ACCESS "RO"
2694 // -----------------------------------------------------------------------------
2695 // Field       : PIO_IRQ1_INTS_SM0
2696 // Description : None
2697 #define PIO_IRQ1_INTS_SM0_RESET  _u(0x0)
2698 #define PIO_IRQ1_INTS_SM0_BITS   _u(0x00000100)
2699 #define PIO_IRQ1_INTS_SM0_MSB    _u(8)
2700 #define PIO_IRQ1_INTS_SM0_LSB    _u(8)
2701 #define PIO_IRQ1_INTS_SM0_ACCESS "RO"
2702 // -----------------------------------------------------------------------------
2703 // Field       : PIO_IRQ1_INTS_SM3_TXNFULL
2704 // Description : None
2705 #define PIO_IRQ1_INTS_SM3_TXNFULL_RESET  _u(0x0)
2706 #define PIO_IRQ1_INTS_SM3_TXNFULL_BITS   _u(0x00000080)
2707 #define PIO_IRQ1_INTS_SM3_TXNFULL_MSB    _u(7)
2708 #define PIO_IRQ1_INTS_SM3_TXNFULL_LSB    _u(7)
2709 #define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO"
2710 // -----------------------------------------------------------------------------
2711 // Field       : PIO_IRQ1_INTS_SM2_TXNFULL
2712 // Description : None
2713 #define PIO_IRQ1_INTS_SM2_TXNFULL_RESET  _u(0x0)
2714 #define PIO_IRQ1_INTS_SM2_TXNFULL_BITS   _u(0x00000040)
2715 #define PIO_IRQ1_INTS_SM2_TXNFULL_MSB    _u(6)
2716 #define PIO_IRQ1_INTS_SM2_TXNFULL_LSB    _u(6)
2717 #define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO"
2718 // -----------------------------------------------------------------------------
2719 // Field       : PIO_IRQ1_INTS_SM1_TXNFULL
2720 // Description : None
2721 #define PIO_IRQ1_INTS_SM1_TXNFULL_RESET  _u(0x0)
2722 #define PIO_IRQ1_INTS_SM1_TXNFULL_BITS   _u(0x00000020)
2723 #define PIO_IRQ1_INTS_SM1_TXNFULL_MSB    _u(5)
2724 #define PIO_IRQ1_INTS_SM1_TXNFULL_LSB    _u(5)
2725 #define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO"
2726 // -----------------------------------------------------------------------------
2727 // Field       : PIO_IRQ1_INTS_SM0_TXNFULL
2728 // Description : None
2729 #define PIO_IRQ1_INTS_SM0_TXNFULL_RESET  _u(0x0)
2730 #define PIO_IRQ1_INTS_SM0_TXNFULL_BITS   _u(0x00000010)
2731 #define PIO_IRQ1_INTS_SM0_TXNFULL_MSB    _u(4)
2732 #define PIO_IRQ1_INTS_SM0_TXNFULL_LSB    _u(4)
2733 #define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO"
2734 // -----------------------------------------------------------------------------
2735 // Field       : PIO_IRQ1_INTS_SM3_RXNEMPTY
2736 // Description : None
2737 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET  _u(0x0)
2738 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS   _u(0x00000008)
2739 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB    _u(3)
2740 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB    _u(3)
2741 #define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO"
2742 // -----------------------------------------------------------------------------
2743 // Field       : PIO_IRQ1_INTS_SM2_RXNEMPTY
2744 // Description : None
2745 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET  _u(0x0)
2746 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS   _u(0x00000004)
2747 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB    _u(2)
2748 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB    _u(2)
2749 #define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO"
2750 // -----------------------------------------------------------------------------
2751 // Field       : PIO_IRQ1_INTS_SM1_RXNEMPTY
2752 // Description : None
2753 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET  _u(0x0)
2754 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS   _u(0x00000002)
2755 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB    _u(1)
2756 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB    _u(1)
2757 #define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO"
2758 // -----------------------------------------------------------------------------
2759 // Field       : PIO_IRQ1_INTS_SM0_RXNEMPTY
2760 // Description : None
2761 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET  _u(0x0)
2762 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS   _u(0x00000001)
2763 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB    _u(0)
2764 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB    _u(0)
2765 #define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO"
2766 // =============================================================================
2767 #endif // HARDWARE_REGS_PIO_DEFINED
2768