1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : PADS_BANK0 8 // Version : 1 9 // Bus type : apb 10 // Description : None 11 // ============================================================================= 12 #ifndef HARDWARE_REGS_PADS_BANK0_DEFINED 13 #define HARDWARE_REGS_PADS_BANK0_DEFINED 14 // ============================================================================= 15 // Register : PADS_BANK0_VOLTAGE_SELECT 16 // Description : Voltage select. Per bank control 17 // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) 18 // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) 19 #define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) 20 #define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) 21 #define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) 22 #define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) 23 #define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) 24 #define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" 25 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) 26 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) 27 // ============================================================================= 28 // Register : PADS_BANK0_GPIO0 29 // Description : Pad control register 30 #define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) 31 #define PADS_BANK0_GPIO0_BITS _u(0x000000ff) 32 #define PADS_BANK0_GPIO0_RESET _u(0x00000056) 33 // ----------------------------------------------------------------------------- 34 // Field : PADS_BANK0_GPIO0_OD 35 // Description : Output disable. Has priority over output enable from 36 // peripherals 37 #define PADS_BANK0_GPIO0_OD_RESET _u(0x0) 38 #define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) 39 #define PADS_BANK0_GPIO0_OD_MSB _u(7) 40 #define PADS_BANK0_GPIO0_OD_LSB _u(7) 41 #define PADS_BANK0_GPIO0_OD_ACCESS "RW" 42 // ----------------------------------------------------------------------------- 43 // Field : PADS_BANK0_GPIO0_IE 44 // Description : Input enable 45 #define PADS_BANK0_GPIO0_IE_RESET _u(0x1) 46 #define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) 47 #define PADS_BANK0_GPIO0_IE_MSB _u(6) 48 #define PADS_BANK0_GPIO0_IE_LSB _u(6) 49 #define PADS_BANK0_GPIO0_IE_ACCESS "RW" 50 // ----------------------------------------------------------------------------- 51 // Field : PADS_BANK0_GPIO0_DRIVE 52 // Description : Drive strength. 53 // 0x0 -> 2mA 54 // 0x1 -> 4mA 55 // 0x2 -> 8mA 56 // 0x3 -> 12mA 57 #define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) 58 #define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) 59 #define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) 60 #define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) 61 #define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" 62 #define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) 63 #define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) 64 #define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) 65 #define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) 66 // ----------------------------------------------------------------------------- 67 // Field : PADS_BANK0_GPIO0_PUE 68 // Description : Pull up enable 69 #define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) 70 #define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) 71 #define PADS_BANK0_GPIO0_PUE_MSB _u(3) 72 #define PADS_BANK0_GPIO0_PUE_LSB _u(3) 73 #define PADS_BANK0_GPIO0_PUE_ACCESS "RW" 74 // ----------------------------------------------------------------------------- 75 // Field : PADS_BANK0_GPIO0_PDE 76 // Description : Pull down enable 77 #define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) 78 #define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) 79 #define PADS_BANK0_GPIO0_PDE_MSB _u(2) 80 #define PADS_BANK0_GPIO0_PDE_LSB _u(2) 81 #define PADS_BANK0_GPIO0_PDE_ACCESS "RW" 82 // ----------------------------------------------------------------------------- 83 // Field : PADS_BANK0_GPIO0_SCHMITT 84 // Description : Enable schmitt trigger 85 #define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) 86 #define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) 87 #define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) 88 #define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) 89 #define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" 90 // ----------------------------------------------------------------------------- 91 // Field : PADS_BANK0_GPIO0_SLEWFAST 92 // Description : Slew rate control. 1 = Fast, 0 = Slow 93 #define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) 94 #define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) 95 #define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) 96 #define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) 97 #define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" 98 // ============================================================================= 99 // Register : PADS_BANK0_GPIO1 100 // Description : Pad control register 101 #define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) 102 #define PADS_BANK0_GPIO1_BITS _u(0x000000ff) 103 #define PADS_BANK0_GPIO1_RESET _u(0x00000056) 104 // ----------------------------------------------------------------------------- 105 // Field : PADS_BANK0_GPIO1_OD 106 // Description : Output disable. Has priority over output enable from 107 // peripherals 108 #define PADS_BANK0_GPIO1_OD_RESET _u(0x0) 109 #define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) 110 #define PADS_BANK0_GPIO1_OD_MSB _u(7) 111 #define PADS_BANK0_GPIO1_OD_LSB _u(7) 112 #define PADS_BANK0_GPIO1_OD_ACCESS "RW" 113 // ----------------------------------------------------------------------------- 114 // Field : PADS_BANK0_GPIO1_IE 115 // Description : Input enable 116 #define PADS_BANK0_GPIO1_IE_RESET _u(0x1) 117 #define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) 118 #define PADS_BANK0_GPIO1_IE_MSB _u(6) 119 #define PADS_BANK0_GPIO1_IE_LSB _u(6) 120 #define PADS_BANK0_GPIO1_IE_ACCESS "RW" 121 // ----------------------------------------------------------------------------- 122 // Field : PADS_BANK0_GPIO1_DRIVE 123 // Description : Drive strength. 124 // 0x0 -> 2mA 125 // 0x1 -> 4mA 126 // 0x2 -> 8mA 127 // 0x3 -> 12mA 128 #define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) 129 #define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) 130 #define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) 131 #define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) 132 #define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" 133 #define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) 134 #define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) 135 #define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) 136 #define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) 137 // ----------------------------------------------------------------------------- 138 // Field : PADS_BANK0_GPIO1_PUE 139 // Description : Pull up enable 140 #define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) 141 #define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) 142 #define PADS_BANK0_GPIO1_PUE_MSB _u(3) 143 #define PADS_BANK0_GPIO1_PUE_LSB _u(3) 144 #define PADS_BANK0_GPIO1_PUE_ACCESS "RW" 145 // ----------------------------------------------------------------------------- 146 // Field : PADS_BANK0_GPIO1_PDE 147 // Description : Pull down enable 148 #define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) 149 #define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) 150 #define PADS_BANK0_GPIO1_PDE_MSB _u(2) 151 #define PADS_BANK0_GPIO1_PDE_LSB _u(2) 152 #define PADS_BANK0_GPIO1_PDE_ACCESS "RW" 153 // ----------------------------------------------------------------------------- 154 // Field : PADS_BANK0_GPIO1_SCHMITT 155 // Description : Enable schmitt trigger 156 #define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) 157 #define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) 158 #define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) 159 #define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) 160 #define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" 161 // ----------------------------------------------------------------------------- 162 // Field : PADS_BANK0_GPIO1_SLEWFAST 163 // Description : Slew rate control. 1 = Fast, 0 = Slow 164 #define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) 165 #define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) 166 #define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) 167 #define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) 168 #define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" 169 // ============================================================================= 170 // Register : PADS_BANK0_GPIO2 171 // Description : Pad control register 172 #define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) 173 #define PADS_BANK0_GPIO2_BITS _u(0x000000ff) 174 #define PADS_BANK0_GPIO2_RESET _u(0x00000056) 175 // ----------------------------------------------------------------------------- 176 // Field : PADS_BANK0_GPIO2_OD 177 // Description : Output disable. Has priority over output enable from 178 // peripherals 179 #define PADS_BANK0_GPIO2_OD_RESET _u(0x0) 180 #define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) 181 #define PADS_BANK0_GPIO2_OD_MSB _u(7) 182 #define PADS_BANK0_GPIO2_OD_LSB _u(7) 183 #define PADS_BANK0_GPIO2_OD_ACCESS "RW" 184 // ----------------------------------------------------------------------------- 185 // Field : PADS_BANK0_GPIO2_IE 186 // Description : Input enable 187 #define PADS_BANK0_GPIO2_IE_RESET _u(0x1) 188 #define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) 189 #define PADS_BANK0_GPIO2_IE_MSB _u(6) 190 #define PADS_BANK0_GPIO2_IE_LSB _u(6) 191 #define PADS_BANK0_GPIO2_IE_ACCESS "RW" 192 // ----------------------------------------------------------------------------- 193 // Field : PADS_BANK0_GPIO2_DRIVE 194 // Description : Drive strength. 195 // 0x0 -> 2mA 196 // 0x1 -> 4mA 197 // 0x2 -> 8mA 198 // 0x3 -> 12mA 199 #define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) 200 #define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) 201 #define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) 202 #define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) 203 #define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" 204 #define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) 205 #define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) 206 #define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) 207 #define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) 208 // ----------------------------------------------------------------------------- 209 // Field : PADS_BANK0_GPIO2_PUE 210 // Description : Pull up enable 211 #define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) 212 #define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) 213 #define PADS_BANK0_GPIO2_PUE_MSB _u(3) 214 #define PADS_BANK0_GPIO2_PUE_LSB _u(3) 215 #define PADS_BANK0_GPIO2_PUE_ACCESS "RW" 216 // ----------------------------------------------------------------------------- 217 // Field : PADS_BANK0_GPIO2_PDE 218 // Description : Pull down enable 219 #define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) 220 #define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) 221 #define PADS_BANK0_GPIO2_PDE_MSB _u(2) 222 #define PADS_BANK0_GPIO2_PDE_LSB _u(2) 223 #define PADS_BANK0_GPIO2_PDE_ACCESS "RW" 224 // ----------------------------------------------------------------------------- 225 // Field : PADS_BANK0_GPIO2_SCHMITT 226 // Description : Enable schmitt trigger 227 #define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) 228 #define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) 229 #define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) 230 #define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) 231 #define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" 232 // ----------------------------------------------------------------------------- 233 // Field : PADS_BANK0_GPIO2_SLEWFAST 234 // Description : Slew rate control. 1 = Fast, 0 = Slow 235 #define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) 236 #define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) 237 #define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) 238 #define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) 239 #define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" 240 // ============================================================================= 241 // Register : PADS_BANK0_GPIO3 242 // Description : Pad control register 243 #define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) 244 #define PADS_BANK0_GPIO3_BITS _u(0x000000ff) 245 #define PADS_BANK0_GPIO3_RESET _u(0x00000056) 246 // ----------------------------------------------------------------------------- 247 // Field : PADS_BANK0_GPIO3_OD 248 // Description : Output disable. Has priority over output enable from 249 // peripherals 250 #define PADS_BANK0_GPIO3_OD_RESET _u(0x0) 251 #define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) 252 #define PADS_BANK0_GPIO3_OD_MSB _u(7) 253 #define PADS_BANK0_GPIO3_OD_LSB _u(7) 254 #define PADS_BANK0_GPIO3_OD_ACCESS "RW" 255 // ----------------------------------------------------------------------------- 256 // Field : PADS_BANK0_GPIO3_IE 257 // Description : Input enable 258 #define PADS_BANK0_GPIO3_IE_RESET _u(0x1) 259 #define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) 260 #define PADS_BANK0_GPIO3_IE_MSB _u(6) 261 #define PADS_BANK0_GPIO3_IE_LSB _u(6) 262 #define PADS_BANK0_GPIO3_IE_ACCESS "RW" 263 // ----------------------------------------------------------------------------- 264 // Field : PADS_BANK0_GPIO3_DRIVE 265 // Description : Drive strength. 266 // 0x0 -> 2mA 267 // 0x1 -> 4mA 268 // 0x2 -> 8mA 269 // 0x3 -> 12mA 270 #define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) 271 #define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) 272 #define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) 273 #define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) 274 #define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" 275 #define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) 276 #define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) 277 #define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) 278 #define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) 279 // ----------------------------------------------------------------------------- 280 // Field : PADS_BANK0_GPIO3_PUE 281 // Description : Pull up enable 282 #define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) 283 #define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) 284 #define PADS_BANK0_GPIO3_PUE_MSB _u(3) 285 #define PADS_BANK0_GPIO3_PUE_LSB _u(3) 286 #define PADS_BANK0_GPIO3_PUE_ACCESS "RW" 287 // ----------------------------------------------------------------------------- 288 // Field : PADS_BANK0_GPIO3_PDE 289 // Description : Pull down enable 290 #define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) 291 #define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) 292 #define PADS_BANK0_GPIO3_PDE_MSB _u(2) 293 #define PADS_BANK0_GPIO3_PDE_LSB _u(2) 294 #define PADS_BANK0_GPIO3_PDE_ACCESS "RW" 295 // ----------------------------------------------------------------------------- 296 // Field : PADS_BANK0_GPIO3_SCHMITT 297 // Description : Enable schmitt trigger 298 #define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) 299 #define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) 300 #define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) 301 #define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) 302 #define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" 303 // ----------------------------------------------------------------------------- 304 // Field : PADS_BANK0_GPIO3_SLEWFAST 305 // Description : Slew rate control. 1 = Fast, 0 = Slow 306 #define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) 307 #define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) 308 #define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) 309 #define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) 310 #define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" 311 // ============================================================================= 312 // Register : PADS_BANK0_GPIO4 313 // Description : Pad control register 314 #define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) 315 #define PADS_BANK0_GPIO4_BITS _u(0x000000ff) 316 #define PADS_BANK0_GPIO4_RESET _u(0x00000056) 317 // ----------------------------------------------------------------------------- 318 // Field : PADS_BANK0_GPIO4_OD 319 // Description : Output disable. Has priority over output enable from 320 // peripherals 321 #define PADS_BANK0_GPIO4_OD_RESET _u(0x0) 322 #define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) 323 #define PADS_BANK0_GPIO4_OD_MSB _u(7) 324 #define PADS_BANK0_GPIO4_OD_LSB _u(7) 325 #define PADS_BANK0_GPIO4_OD_ACCESS "RW" 326 // ----------------------------------------------------------------------------- 327 // Field : PADS_BANK0_GPIO4_IE 328 // Description : Input enable 329 #define PADS_BANK0_GPIO4_IE_RESET _u(0x1) 330 #define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) 331 #define PADS_BANK0_GPIO4_IE_MSB _u(6) 332 #define PADS_BANK0_GPIO4_IE_LSB _u(6) 333 #define PADS_BANK0_GPIO4_IE_ACCESS "RW" 334 // ----------------------------------------------------------------------------- 335 // Field : PADS_BANK0_GPIO4_DRIVE 336 // Description : Drive strength. 337 // 0x0 -> 2mA 338 // 0x1 -> 4mA 339 // 0x2 -> 8mA 340 // 0x3 -> 12mA 341 #define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) 342 #define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) 343 #define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) 344 #define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) 345 #define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" 346 #define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) 347 #define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) 348 #define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) 349 #define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) 350 // ----------------------------------------------------------------------------- 351 // Field : PADS_BANK0_GPIO4_PUE 352 // Description : Pull up enable 353 #define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) 354 #define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) 355 #define PADS_BANK0_GPIO4_PUE_MSB _u(3) 356 #define PADS_BANK0_GPIO4_PUE_LSB _u(3) 357 #define PADS_BANK0_GPIO4_PUE_ACCESS "RW" 358 // ----------------------------------------------------------------------------- 359 // Field : PADS_BANK0_GPIO4_PDE 360 // Description : Pull down enable 361 #define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) 362 #define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) 363 #define PADS_BANK0_GPIO4_PDE_MSB _u(2) 364 #define PADS_BANK0_GPIO4_PDE_LSB _u(2) 365 #define PADS_BANK0_GPIO4_PDE_ACCESS "RW" 366 // ----------------------------------------------------------------------------- 367 // Field : PADS_BANK0_GPIO4_SCHMITT 368 // Description : Enable schmitt trigger 369 #define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) 370 #define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) 371 #define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) 372 #define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) 373 #define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" 374 // ----------------------------------------------------------------------------- 375 // Field : PADS_BANK0_GPIO4_SLEWFAST 376 // Description : Slew rate control. 1 = Fast, 0 = Slow 377 #define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) 378 #define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) 379 #define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) 380 #define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) 381 #define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" 382 // ============================================================================= 383 // Register : PADS_BANK0_GPIO5 384 // Description : Pad control register 385 #define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) 386 #define PADS_BANK0_GPIO5_BITS _u(0x000000ff) 387 #define PADS_BANK0_GPIO5_RESET _u(0x00000056) 388 // ----------------------------------------------------------------------------- 389 // Field : PADS_BANK0_GPIO5_OD 390 // Description : Output disable. Has priority over output enable from 391 // peripherals 392 #define PADS_BANK0_GPIO5_OD_RESET _u(0x0) 393 #define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) 394 #define PADS_BANK0_GPIO5_OD_MSB _u(7) 395 #define PADS_BANK0_GPIO5_OD_LSB _u(7) 396 #define PADS_BANK0_GPIO5_OD_ACCESS "RW" 397 // ----------------------------------------------------------------------------- 398 // Field : PADS_BANK0_GPIO5_IE 399 // Description : Input enable 400 #define PADS_BANK0_GPIO5_IE_RESET _u(0x1) 401 #define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) 402 #define PADS_BANK0_GPIO5_IE_MSB _u(6) 403 #define PADS_BANK0_GPIO5_IE_LSB _u(6) 404 #define PADS_BANK0_GPIO5_IE_ACCESS "RW" 405 // ----------------------------------------------------------------------------- 406 // Field : PADS_BANK0_GPIO5_DRIVE 407 // Description : Drive strength. 408 // 0x0 -> 2mA 409 // 0x1 -> 4mA 410 // 0x2 -> 8mA 411 // 0x3 -> 12mA 412 #define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) 413 #define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) 414 #define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) 415 #define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) 416 #define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" 417 #define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) 418 #define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) 419 #define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) 420 #define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) 421 // ----------------------------------------------------------------------------- 422 // Field : PADS_BANK0_GPIO5_PUE 423 // Description : Pull up enable 424 #define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) 425 #define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) 426 #define PADS_BANK0_GPIO5_PUE_MSB _u(3) 427 #define PADS_BANK0_GPIO5_PUE_LSB _u(3) 428 #define PADS_BANK0_GPIO5_PUE_ACCESS "RW" 429 // ----------------------------------------------------------------------------- 430 // Field : PADS_BANK0_GPIO5_PDE 431 // Description : Pull down enable 432 #define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) 433 #define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) 434 #define PADS_BANK0_GPIO5_PDE_MSB _u(2) 435 #define PADS_BANK0_GPIO5_PDE_LSB _u(2) 436 #define PADS_BANK0_GPIO5_PDE_ACCESS "RW" 437 // ----------------------------------------------------------------------------- 438 // Field : PADS_BANK0_GPIO5_SCHMITT 439 // Description : Enable schmitt trigger 440 #define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) 441 #define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) 442 #define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) 443 #define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) 444 #define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" 445 // ----------------------------------------------------------------------------- 446 // Field : PADS_BANK0_GPIO5_SLEWFAST 447 // Description : Slew rate control. 1 = Fast, 0 = Slow 448 #define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) 449 #define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) 450 #define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) 451 #define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) 452 #define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" 453 // ============================================================================= 454 // Register : PADS_BANK0_GPIO6 455 // Description : Pad control register 456 #define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) 457 #define PADS_BANK0_GPIO6_BITS _u(0x000000ff) 458 #define PADS_BANK0_GPIO6_RESET _u(0x00000056) 459 // ----------------------------------------------------------------------------- 460 // Field : PADS_BANK0_GPIO6_OD 461 // Description : Output disable. Has priority over output enable from 462 // peripherals 463 #define PADS_BANK0_GPIO6_OD_RESET _u(0x0) 464 #define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) 465 #define PADS_BANK0_GPIO6_OD_MSB _u(7) 466 #define PADS_BANK0_GPIO6_OD_LSB _u(7) 467 #define PADS_BANK0_GPIO6_OD_ACCESS "RW" 468 // ----------------------------------------------------------------------------- 469 // Field : PADS_BANK0_GPIO6_IE 470 // Description : Input enable 471 #define PADS_BANK0_GPIO6_IE_RESET _u(0x1) 472 #define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) 473 #define PADS_BANK0_GPIO6_IE_MSB _u(6) 474 #define PADS_BANK0_GPIO6_IE_LSB _u(6) 475 #define PADS_BANK0_GPIO6_IE_ACCESS "RW" 476 // ----------------------------------------------------------------------------- 477 // Field : PADS_BANK0_GPIO6_DRIVE 478 // Description : Drive strength. 479 // 0x0 -> 2mA 480 // 0x1 -> 4mA 481 // 0x2 -> 8mA 482 // 0x3 -> 12mA 483 #define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) 484 #define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) 485 #define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) 486 #define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) 487 #define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" 488 #define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) 489 #define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) 490 #define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) 491 #define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) 492 // ----------------------------------------------------------------------------- 493 // Field : PADS_BANK0_GPIO6_PUE 494 // Description : Pull up enable 495 #define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) 496 #define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) 497 #define PADS_BANK0_GPIO6_PUE_MSB _u(3) 498 #define PADS_BANK0_GPIO6_PUE_LSB _u(3) 499 #define PADS_BANK0_GPIO6_PUE_ACCESS "RW" 500 // ----------------------------------------------------------------------------- 501 // Field : PADS_BANK0_GPIO6_PDE 502 // Description : Pull down enable 503 #define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) 504 #define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) 505 #define PADS_BANK0_GPIO6_PDE_MSB _u(2) 506 #define PADS_BANK0_GPIO6_PDE_LSB _u(2) 507 #define PADS_BANK0_GPIO6_PDE_ACCESS "RW" 508 // ----------------------------------------------------------------------------- 509 // Field : PADS_BANK0_GPIO6_SCHMITT 510 // Description : Enable schmitt trigger 511 #define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) 512 #define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) 513 #define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) 514 #define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) 515 #define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" 516 // ----------------------------------------------------------------------------- 517 // Field : PADS_BANK0_GPIO6_SLEWFAST 518 // Description : Slew rate control. 1 = Fast, 0 = Slow 519 #define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) 520 #define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) 521 #define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) 522 #define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) 523 #define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" 524 // ============================================================================= 525 // Register : PADS_BANK0_GPIO7 526 // Description : Pad control register 527 #define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) 528 #define PADS_BANK0_GPIO7_BITS _u(0x000000ff) 529 #define PADS_BANK0_GPIO7_RESET _u(0x00000056) 530 // ----------------------------------------------------------------------------- 531 // Field : PADS_BANK0_GPIO7_OD 532 // Description : Output disable. Has priority over output enable from 533 // peripherals 534 #define PADS_BANK0_GPIO7_OD_RESET _u(0x0) 535 #define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) 536 #define PADS_BANK0_GPIO7_OD_MSB _u(7) 537 #define PADS_BANK0_GPIO7_OD_LSB _u(7) 538 #define PADS_BANK0_GPIO7_OD_ACCESS "RW" 539 // ----------------------------------------------------------------------------- 540 // Field : PADS_BANK0_GPIO7_IE 541 // Description : Input enable 542 #define PADS_BANK0_GPIO7_IE_RESET _u(0x1) 543 #define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) 544 #define PADS_BANK0_GPIO7_IE_MSB _u(6) 545 #define PADS_BANK0_GPIO7_IE_LSB _u(6) 546 #define PADS_BANK0_GPIO7_IE_ACCESS "RW" 547 // ----------------------------------------------------------------------------- 548 // Field : PADS_BANK0_GPIO7_DRIVE 549 // Description : Drive strength. 550 // 0x0 -> 2mA 551 // 0x1 -> 4mA 552 // 0x2 -> 8mA 553 // 0x3 -> 12mA 554 #define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) 555 #define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) 556 #define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) 557 #define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) 558 #define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" 559 #define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) 560 #define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) 561 #define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) 562 #define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) 563 // ----------------------------------------------------------------------------- 564 // Field : PADS_BANK0_GPIO7_PUE 565 // Description : Pull up enable 566 #define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) 567 #define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) 568 #define PADS_BANK0_GPIO7_PUE_MSB _u(3) 569 #define PADS_BANK0_GPIO7_PUE_LSB _u(3) 570 #define PADS_BANK0_GPIO7_PUE_ACCESS "RW" 571 // ----------------------------------------------------------------------------- 572 // Field : PADS_BANK0_GPIO7_PDE 573 // Description : Pull down enable 574 #define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) 575 #define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) 576 #define PADS_BANK0_GPIO7_PDE_MSB _u(2) 577 #define PADS_BANK0_GPIO7_PDE_LSB _u(2) 578 #define PADS_BANK0_GPIO7_PDE_ACCESS "RW" 579 // ----------------------------------------------------------------------------- 580 // Field : PADS_BANK0_GPIO7_SCHMITT 581 // Description : Enable schmitt trigger 582 #define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) 583 #define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) 584 #define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) 585 #define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) 586 #define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" 587 // ----------------------------------------------------------------------------- 588 // Field : PADS_BANK0_GPIO7_SLEWFAST 589 // Description : Slew rate control. 1 = Fast, 0 = Slow 590 #define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) 591 #define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) 592 #define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) 593 #define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) 594 #define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" 595 // ============================================================================= 596 // Register : PADS_BANK0_GPIO8 597 // Description : Pad control register 598 #define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) 599 #define PADS_BANK0_GPIO8_BITS _u(0x000000ff) 600 #define PADS_BANK0_GPIO8_RESET _u(0x00000056) 601 // ----------------------------------------------------------------------------- 602 // Field : PADS_BANK0_GPIO8_OD 603 // Description : Output disable. Has priority over output enable from 604 // peripherals 605 #define PADS_BANK0_GPIO8_OD_RESET _u(0x0) 606 #define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) 607 #define PADS_BANK0_GPIO8_OD_MSB _u(7) 608 #define PADS_BANK0_GPIO8_OD_LSB _u(7) 609 #define PADS_BANK0_GPIO8_OD_ACCESS "RW" 610 // ----------------------------------------------------------------------------- 611 // Field : PADS_BANK0_GPIO8_IE 612 // Description : Input enable 613 #define PADS_BANK0_GPIO8_IE_RESET _u(0x1) 614 #define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) 615 #define PADS_BANK0_GPIO8_IE_MSB _u(6) 616 #define PADS_BANK0_GPIO8_IE_LSB _u(6) 617 #define PADS_BANK0_GPIO8_IE_ACCESS "RW" 618 // ----------------------------------------------------------------------------- 619 // Field : PADS_BANK0_GPIO8_DRIVE 620 // Description : Drive strength. 621 // 0x0 -> 2mA 622 // 0x1 -> 4mA 623 // 0x2 -> 8mA 624 // 0x3 -> 12mA 625 #define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) 626 #define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) 627 #define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) 628 #define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) 629 #define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" 630 #define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) 631 #define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) 632 #define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) 633 #define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) 634 // ----------------------------------------------------------------------------- 635 // Field : PADS_BANK0_GPIO8_PUE 636 // Description : Pull up enable 637 #define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) 638 #define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) 639 #define PADS_BANK0_GPIO8_PUE_MSB _u(3) 640 #define PADS_BANK0_GPIO8_PUE_LSB _u(3) 641 #define PADS_BANK0_GPIO8_PUE_ACCESS "RW" 642 // ----------------------------------------------------------------------------- 643 // Field : PADS_BANK0_GPIO8_PDE 644 // Description : Pull down enable 645 #define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) 646 #define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) 647 #define PADS_BANK0_GPIO8_PDE_MSB _u(2) 648 #define PADS_BANK0_GPIO8_PDE_LSB _u(2) 649 #define PADS_BANK0_GPIO8_PDE_ACCESS "RW" 650 // ----------------------------------------------------------------------------- 651 // Field : PADS_BANK0_GPIO8_SCHMITT 652 // Description : Enable schmitt trigger 653 #define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) 654 #define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) 655 #define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) 656 #define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) 657 #define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" 658 // ----------------------------------------------------------------------------- 659 // Field : PADS_BANK0_GPIO8_SLEWFAST 660 // Description : Slew rate control. 1 = Fast, 0 = Slow 661 #define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) 662 #define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) 663 #define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) 664 #define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) 665 #define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" 666 // ============================================================================= 667 // Register : PADS_BANK0_GPIO9 668 // Description : Pad control register 669 #define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) 670 #define PADS_BANK0_GPIO9_BITS _u(0x000000ff) 671 #define PADS_BANK0_GPIO9_RESET _u(0x00000056) 672 // ----------------------------------------------------------------------------- 673 // Field : PADS_BANK0_GPIO9_OD 674 // Description : Output disable. Has priority over output enable from 675 // peripherals 676 #define PADS_BANK0_GPIO9_OD_RESET _u(0x0) 677 #define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) 678 #define PADS_BANK0_GPIO9_OD_MSB _u(7) 679 #define PADS_BANK0_GPIO9_OD_LSB _u(7) 680 #define PADS_BANK0_GPIO9_OD_ACCESS "RW" 681 // ----------------------------------------------------------------------------- 682 // Field : PADS_BANK0_GPIO9_IE 683 // Description : Input enable 684 #define PADS_BANK0_GPIO9_IE_RESET _u(0x1) 685 #define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) 686 #define PADS_BANK0_GPIO9_IE_MSB _u(6) 687 #define PADS_BANK0_GPIO9_IE_LSB _u(6) 688 #define PADS_BANK0_GPIO9_IE_ACCESS "RW" 689 // ----------------------------------------------------------------------------- 690 // Field : PADS_BANK0_GPIO9_DRIVE 691 // Description : Drive strength. 692 // 0x0 -> 2mA 693 // 0x1 -> 4mA 694 // 0x2 -> 8mA 695 // 0x3 -> 12mA 696 #define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) 697 #define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) 698 #define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) 699 #define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) 700 #define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" 701 #define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) 702 #define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) 703 #define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) 704 #define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) 705 // ----------------------------------------------------------------------------- 706 // Field : PADS_BANK0_GPIO9_PUE 707 // Description : Pull up enable 708 #define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) 709 #define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) 710 #define PADS_BANK0_GPIO9_PUE_MSB _u(3) 711 #define PADS_BANK0_GPIO9_PUE_LSB _u(3) 712 #define PADS_BANK0_GPIO9_PUE_ACCESS "RW" 713 // ----------------------------------------------------------------------------- 714 // Field : PADS_BANK0_GPIO9_PDE 715 // Description : Pull down enable 716 #define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) 717 #define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) 718 #define PADS_BANK0_GPIO9_PDE_MSB _u(2) 719 #define PADS_BANK0_GPIO9_PDE_LSB _u(2) 720 #define PADS_BANK0_GPIO9_PDE_ACCESS "RW" 721 // ----------------------------------------------------------------------------- 722 // Field : PADS_BANK0_GPIO9_SCHMITT 723 // Description : Enable schmitt trigger 724 #define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) 725 #define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) 726 #define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) 727 #define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) 728 #define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" 729 // ----------------------------------------------------------------------------- 730 // Field : PADS_BANK0_GPIO9_SLEWFAST 731 // Description : Slew rate control. 1 = Fast, 0 = Slow 732 #define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) 733 #define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) 734 #define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) 735 #define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) 736 #define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" 737 // ============================================================================= 738 // Register : PADS_BANK0_GPIO10 739 // Description : Pad control register 740 #define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) 741 #define PADS_BANK0_GPIO10_BITS _u(0x000000ff) 742 #define PADS_BANK0_GPIO10_RESET _u(0x00000056) 743 // ----------------------------------------------------------------------------- 744 // Field : PADS_BANK0_GPIO10_OD 745 // Description : Output disable. Has priority over output enable from 746 // peripherals 747 #define PADS_BANK0_GPIO10_OD_RESET _u(0x0) 748 #define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) 749 #define PADS_BANK0_GPIO10_OD_MSB _u(7) 750 #define PADS_BANK0_GPIO10_OD_LSB _u(7) 751 #define PADS_BANK0_GPIO10_OD_ACCESS "RW" 752 // ----------------------------------------------------------------------------- 753 // Field : PADS_BANK0_GPIO10_IE 754 // Description : Input enable 755 #define PADS_BANK0_GPIO10_IE_RESET _u(0x1) 756 #define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) 757 #define PADS_BANK0_GPIO10_IE_MSB _u(6) 758 #define PADS_BANK0_GPIO10_IE_LSB _u(6) 759 #define PADS_BANK0_GPIO10_IE_ACCESS "RW" 760 // ----------------------------------------------------------------------------- 761 // Field : PADS_BANK0_GPIO10_DRIVE 762 // Description : Drive strength. 763 // 0x0 -> 2mA 764 // 0x1 -> 4mA 765 // 0x2 -> 8mA 766 // 0x3 -> 12mA 767 #define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) 768 #define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) 769 #define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) 770 #define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) 771 #define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" 772 #define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) 773 #define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) 774 #define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) 775 #define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) 776 // ----------------------------------------------------------------------------- 777 // Field : PADS_BANK0_GPIO10_PUE 778 // Description : Pull up enable 779 #define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) 780 #define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) 781 #define PADS_BANK0_GPIO10_PUE_MSB _u(3) 782 #define PADS_BANK0_GPIO10_PUE_LSB _u(3) 783 #define PADS_BANK0_GPIO10_PUE_ACCESS "RW" 784 // ----------------------------------------------------------------------------- 785 // Field : PADS_BANK0_GPIO10_PDE 786 // Description : Pull down enable 787 #define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) 788 #define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) 789 #define PADS_BANK0_GPIO10_PDE_MSB _u(2) 790 #define PADS_BANK0_GPIO10_PDE_LSB _u(2) 791 #define PADS_BANK0_GPIO10_PDE_ACCESS "RW" 792 // ----------------------------------------------------------------------------- 793 // Field : PADS_BANK0_GPIO10_SCHMITT 794 // Description : Enable schmitt trigger 795 #define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) 796 #define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) 797 #define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) 798 #define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) 799 #define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" 800 // ----------------------------------------------------------------------------- 801 // Field : PADS_BANK0_GPIO10_SLEWFAST 802 // Description : Slew rate control. 1 = Fast, 0 = Slow 803 #define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) 804 #define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) 805 #define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) 806 #define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) 807 #define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" 808 // ============================================================================= 809 // Register : PADS_BANK0_GPIO11 810 // Description : Pad control register 811 #define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) 812 #define PADS_BANK0_GPIO11_BITS _u(0x000000ff) 813 #define PADS_BANK0_GPIO11_RESET _u(0x00000056) 814 // ----------------------------------------------------------------------------- 815 // Field : PADS_BANK0_GPIO11_OD 816 // Description : Output disable. Has priority over output enable from 817 // peripherals 818 #define PADS_BANK0_GPIO11_OD_RESET _u(0x0) 819 #define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) 820 #define PADS_BANK0_GPIO11_OD_MSB _u(7) 821 #define PADS_BANK0_GPIO11_OD_LSB _u(7) 822 #define PADS_BANK0_GPIO11_OD_ACCESS "RW" 823 // ----------------------------------------------------------------------------- 824 // Field : PADS_BANK0_GPIO11_IE 825 // Description : Input enable 826 #define PADS_BANK0_GPIO11_IE_RESET _u(0x1) 827 #define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) 828 #define PADS_BANK0_GPIO11_IE_MSB _u(6) 829 #define PADS_BANK0_GPIO11_IE_LSB _u(6) 830 #define PADS_BANK0_GPIO11_IE_ACCESS "RW" 831 // ----------------------------------------------------------------------------- 832 // Field : PADS_BANK0_GPIO11_DRIVE 833 // Description : Drive strength. 834 // 0x0 -> 2mA 835 // 0x1 -> 4mA 836 // 0x2 -> 8mA 837 // 0x3 -> 12mA 838 #define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) 839 #define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) 840 #define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) 841 #define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) 842 #define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" 843 #define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) 844 #define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) 845 #define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) 846 #define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) 847 // ----------------------------------------------------------------------------- 848 // Field : PADS_BANK0_GPIO11_PUE 849 // Description : Pull up enable 850 #define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) 851 #define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) 852 #define PADS_BANK0_GPIO11_PUE_MSB _u(3) 853 #define PADS_BANK0_GPIO11_PUE_LSB _u(3) 854 #define PADS_BANK0_GPIO11_PUE_ACCESS "RW" 855 // ----------------------------------------------------------------------------- 856 // Field : PADS_BANK0_GPIO11_PDE 857 // Description : Pull down enable 858 #define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) 859 #define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) 860 #define PADS_BANK0_GPIO11_PDE_MSB _u(2) 861 #define PADS_BANK0_GPIO11_PDE_LSB _u(2) 862 #define PADS_BANK0_GPIO11_PDE_ACCESS "RW" 863 // ----------------------------------------------------------------------------- 864 // Field : PADS_BANK0_GPIO11_SCHMITT 865 // Description : Enable schmitt trigger 866 #define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) 867 #define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) 868 #define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) 869 #define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) 870 #define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" 871 // ----------------------------------------------------------------------------- 872 // Field : PADS_BANK0_GPIO11_SLEWFAST 873 // Description : Slew rate control. 1 = Fast, 0 = Slow 874 #define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) 875 #define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) 876 #define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) 877 #define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) 878 #define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" 879 // ============================================================================= 880 // Register : PADS_BANK0_GPIO12 881 // Description : Pad control register 882 #define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) 883 #define PADS_BANK0_GPIO12_BITS _u(0x000000ff) 884 #define PADS_BANK0_GPIO12_RESET _u(0x00000056) 885 // ----------------------------------------------------------------------------- 886 // Field : PADS_BANK0_GPIO12_OD 887 // Description : Output disable. Has priority over output enable from 888 // peripherals 889 #define PADS_BANK0_GPIO12_OD_RESET _u(0x0) 890 #define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) 891 #define PADS_BANK0_GPIO12_OD_MSB _u(7) 892 #define PADS_BANK0_GPIO12_OD_LSB _u(7) 893 #define PADS_BANK0_GPIO12_OD_ACCESS "RW" 894 // ----------------------------------------------------------------------------- 895 // Field : PADS_BANK0_GPIO12_IE 896 // Description : Input enable 897 #define PADS_BANK0_GPIO12_IE_RESET _u(0x1) 898 #define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) 899 #define PADS_BANK0_GPIO12_IE_MSB _u(6) 900 #define PADS_BANK0_GPIO12_IE_LSB _u(6) 901 #define PADS_BANK0_GPIO12_IE_ACCESS "RW" 902 // ----------------------------------------------------------------------------- 903 // Field : PADS_BANK0_GPIO12_DRIVE 904 // Description : Drive strength. 905 // 0x0 -> 2mA 906 // 0x1 -> 4mA 907 // 0x2 -> 8mA 908 // 0x3 -> 12mA 909 #define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) 910 #define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) 911 #define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) 912 #define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) 913 #define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" 914 #define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) 915 #define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) 916 #define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) 917 #define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) 918 // ----------------------------------------------------------------------------- 919 // Field : PADS_BANK0_GPIO12_PUE 920 // Description : Pull up enable 921 #define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) 922 #define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) 923 #define PADS_BANK0_GPIO12_PUE_MSB _u(3) 924 #define PADS_BANK0_GPIO12_PUE_LSB _u(3) 925 #define PADS_BANK0_GPIO12_PUE_ACCESS "RW" 926 // ----------------------------------------------------------------------------- 927 // Field : PADS_BANK0_GPIO12_PDE 928 // Description : Pull down enable 929 #define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) 930 #define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) 931 #define PADS_BANK0_GPIO12_PDE_MSB _u(2) 932 #define PADS_BANK0_GPIO12_PDE_LSB _u(2) 933 #define PADS_BANK0_GPIO12_PDE_ACCESS "RW" 934 // ----------------------------------------------------------------------------- 935 // Field : PADS_BANK0_GPIO12_SCHMITT 936 // Description : Enable schmitt trigger 937 #define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) 938 #define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) 939 #define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) 940 #define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) 941 #define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" 942 // ----------------------------------------------------------------------------- 943 // Field : PADS_BANK0_GPIO12_SLEWFAST 944 // Description : Slew rate control. 1 = Fast, 0 = Slow 945 #define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) 946 #define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) 947 #define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) 948 #define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) 949 #define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" 950 // ============================================================================= 951 // Register : PADS_BANK0_GPIO13 952 // Description : Pad control register 953 #define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) 954 #define PADS_BANK0_GPIO13_BITS _u(0x000000ff) 955 #define PADS_BANK0_GPIO13_RESET _u(0x00000056) 956 // ----------------------------------------------------------------------------- 957 // Field : PADS_BANK0_GPIO13_OD 958 // Description : Output disable. Has priority over output enable from 959 // peripherals 960 #define PADS_BANK0_GPIO13_OD_RESET _u(0x0) 961 #define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) 962 #define PADS_BANK0_GPIO13_OD_MSB _u(7) 963 #define PADS_BANK0_GPIO13_OD_LSB _u(7) 964 #define PADS_BANK0_GPIO13_OD_ACCESS "RW" 965 // ----------------------------------------------------------------------------- 966 // Field : PADS_BANK0_GPIO13_IE 967 // Description : Input enable 968 #define PADS_BANK0_GPIO13_IE_RESET _u(0x1) 969 #define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) 970 #define PADS_BANK0_GPIO13_IE_MSB _u(6) 971 #define PADS_BANK0_GPIO13_IE_LSB _u(6) 972 #define PADS_BANK0_GPIO13_IE_ACCESS "RW" 973 // ----------------------------------------------------------------------------- 974 // Field : PADS_BANK0_GPIO13_DRIVE 975 // Description : Drive strength. 976 // 0x0 -> 2mA 977 // 0x1 -> 4mA 978 // 0x2 -> 8mA 979 // 0x3 -> 12mA 980 #define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) 981 #define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) 982 #define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) 983 #define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) 984 #define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" 985 #define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) 986 #define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) 987 #define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) 988 #define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) 989 // ----------------------------------------------------------------------------- 990 // Field : PADS_BANK0_GPIO13_PUE 991 // Description : Pull up enable 992 #define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) 993 #define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) 994 #define PADS_BANK0_GPIO13_PUE_MSB _u(3) 995 #define PADS_BANK0_GPIO13_PUE_LSB _u(3) 996 #define PADS_BANK0_GPIO13_PUE_ACCESS "RW" 997 // ----------------------------------------------------------------------------- 998 // Field : PADS_BANK0_GPIO13_PDE 999 // Description : Pull down enable 1000 #define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) 1001 #define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) 1002 #define PADS_BANK0_GPIO13_PDE_MSB _u(2) 1003 #define PADS_BANK0_GPIO13_PDE_LSB _u(2) 1004 #define PADS_BANK0_GPIO13_PDE_ACCESS "RW" 1005 // ----------------------------------------------------------------------------- 1006 // Field : PADS_BANK0_GPIO13_SCHMITT 1007 // Description : Enable schmitt trigger 1008 #define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) 1009 #define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) 1010 #define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) 1011 #define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) 1012 #define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" 1013 // ----------------------------------------------------------------------------- 1014 // Field : PADS_BANK0_GPIO13_SLEWFAST 1015 // Description : Slew rate control. 1 = Fast, 0 = Slow 1016 #define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) 1017 #define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) 1018 #define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) 1019 #define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) 1020 #define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" 1021 // ============================================================================= 1022 // Register : PADS_BANK0_GPIO14 1023 // Description : Pad control register 1024 #define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) 1025 #define PADS_BANK0_GPIO14_BITS _u(0x000000ff) 1026 #define PADS_BANK0_GPIO14_RESET _u(0x00000056) 1027 // ----------------------------------------------------------------------------- 1028 // Field : PADS_BANK0_GPIO14_OD 1029 // Description : Output disable. Has priority over output enable from 1030 // peripherals 1031 #define PADS_BANK0_GPIO14_OD_RESET _u(0x0) 1032 #define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) 1033 #define PADS_BANK0_GPIO14_OD_MSB _u(7) 1034 #define PADS_BANK0_GPIO14_OD_LSB _u(7) 1035 #define PADS_BANK0_GPIO14_OD_ACCESS "RW" 1036 // ----------------------------------------------------------------------------- 1037 // Field : PADS_BANK0_GPIO14_IE 1038 // Description : Input enable 1039 #define PADS_BANK0_GPIO14_IE_RESET _u(0x1) 1040 #define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) 1041 #define PADS_BANK0_GPIO14_IE_MSB _u(6) 1042 #define PADS_BANK0_GPIO14_IE_LSB _u(6) 1043 #define PADS_BANK0_GPIO14_IE_ACCESS "RW" 1044 // ----------------------------------------------------------------------------- 1045 // Field : PADS_BANK0_GPIO14_DRIVE 1046 // Description : Drive strength. 1047 // 0x0 -> 2mA 1048 // 0x1 -> 4mA 1049 // 0x2 -> 8mA 1050 // 0x3 -> 12mA 1051 #define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) 1052 #define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) 1053 #define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) 1054 #define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) 1055 #define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" 1056 #define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) 1057 #define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) 1058 #define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) 1059 #define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) 1060 // ----------------------------------------------------------------------------- 1061 // Field : PADS_BANK0_GPIO14_PUE 1062 // Description : Pull up enable 1063 #define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) 1064 #define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) 1065 #define PADS_BANK0_GPIO14_PUE_MSB _u(3) 1066 #define PADS_BANK0_GPIO14_PUE_LSB _u(3) 1067 #define PADS_BANK0_GPIO14_PUE_ACCESS "RW" 1068 // ----------------------------------------------------------------------------- 1069 // Field : PADS_BANK0_GPIO14_PDE 1070 // Description : Pull down enable 1071 #define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) 1072 #define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) 1073 #define PADS_BANK0_GPIO14_PDE_MSB _u(2) 1074 #define PADS_BANK0_GPIO14_PDE_LSB _u(2) 1075 #define PADS_BANK0_GPIO14_PDE_ACCESS "RW" 1076 // ----------------------------------------------------------------------------- 1077 // Field : PADS_BANK0_GPIO14_SCHMITT 1078 // Description : Enable schmitt trigger 1079 #define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) 1080 #define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) 1081 #define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) 1082 #define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) 1083 #define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" 1084 // ----------------------------------------------------------------------------- 1085 // Field : PADS_BANK0_GPIO14_SLEWFAST 1086 // Description : Slew rate control. 1 = Fast, 0 = Slow 1087 #define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) 1088 #define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) 1089 #define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) 1090 #define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) 1091 #define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" 1092 // ============================================================================= 1093 // Register : PADS_BANK0_GPIO15 1094 // Description : Pad control register 1095 #define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) 1096 #define PADS_BANK0_GPIO15_BITS _u(0x000000ff) 1097 #define PADS_BANK0_GPIO15_RESET _u(0x00000056) 1098 // ----------------------------------------------------------------------------- 1099 // Field : PADS_BANK0_GPIO15_OD 1100 // Description : Output disable. Has priority over output enable from 1101 // peripherals 1102 #define PADS_BANK0_GPIO15_OD_RESET _u(0x0) 1103 #define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) 1104 #define PADS_BANK0_GPIO15_OD_MSB _u(7) 1105 #define PADS_BANK0_GPIO15_OD_LSB _u(7) 1106 #define PADS_BANK0_GPIO15_OD_ACCESS "RW" 1107 // ----------------------------------------------------------------------------- 1108 // Field : PADS_BANK0_GPIO15_IE 1109 // Description : Input enable 1110 #define PADS_BANK0_GPIO15_IE_RESET _u(0x1) 1111 #define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) 1112 #define PADS_BANK0_GPIO15_IE_MSB _u(6) 1113 #define PADS_BANK0_GPIO15_IE_LSB _u(6) 1114 #define PADS_BANK0_GPIO15_IE_ACCESS "RW" 1115 // ----------------------------------------------------------------------------- 1116 // Field : PADS_BANK0_GPIO15_DRIVE 1117 // Description : Drive strength. 1118 // 0x0 -> 2mA 1119 // 0x1 -> 4mA 1120 // 0x2 -> 8mA 1121 // 0x3 -> 12mA 1122 #define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) 1123 #define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) 1124 #define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) 1125 #define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) 1126 #define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" 1127 #define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) 1128 #define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) 1129 #define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) 1130 #define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) 1131 // ----------------------------------------------------------------------------- 1132 // Field : PADS_BANK0_GPIO15_PUE 1133 // Description : Pull up enable 1134 #define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) 1135 #define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) 1136 #define PADS_BANK0_GPIO15_PUE_MSB _u(3) 1137 #define PADS_BANK0_GPIO15_PUE_LSB _u(3) 1138 #define PADS_BANK0_GPIO15_PUE_ACCESS "RW" 1139 // ----------------------------------------------------------------------------- 1140 // Field : PADS_BANK0_GPIO15_PDE 1141 // Description : Pull down enable 1142 #define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) 1143 #define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) 1144 #define PADS_BANK0_GPIO15_PDE_MSB _u(2) 1145 #define PADS_BANK0_GPIO15_PDE_LSB _u(2) 1146 #define PADS_BANK0_GPIO15_PDE_ACCESS "RW" 1147 // ----------------------------------------------------------------------------- 1148 // Field : PADS_BANK0_GPIO15_SCHMITT 1149 // Description : Enable schmitt trigger 1150 #define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) 1151 #define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) 1152 #define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) 1153 #define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) 1154 #define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" 1155 // ----------------------------------------------------------------------------- 1156 // Field : PADS_BANK0_GPIO15_SLEWFAST 1157 // Description : Slew rate control. 1 = Fast, 0 = Slow 1158 #define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) 1159 #define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) 1160 #define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) 1161 #define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) 1162 #define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" 1163 // ============================================================================= 1164 // Register : PADS_BANK0_GPIO16 1165 // Description : Pad control register 1166 #define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) 1167 #define PADS_BANK0_GPIO16_BITS _u(0x000000ff) 1168 #define PADS_BANK0_GPIO16_RESET _u(0x00000056) 1169 // ----------------------------------------------------------------------------- 1170 // Field : PADS_BANK0_GPIO16_OD 1171 // Description : Output disable. Has priority over output enable from 1172 // peripherals 1173 #define PADS_BANK0_GPIO16_OD_RESET _u(0x0) 1174 #define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) 1175 #define PADS_BANK0_GPIO16_OD_MSB _u(7) 1176 #define PADS_BANK0_GPIO16_OD_LSB _u(7) 1177 #define PADS_BANK0_GPIO16_OD_ACCESS "RW" 1178 // ----------------------------------------------------------------------------- 1179 // Field : PADS_BANK0_GPIO16_IE 1180 // Description : Input enable 1181 #define PADS_BANK0_GPIO16_IE_RESET _u(0x1) 1182 #define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) 1183 #define PADS_BANK0_GPIO16_IE_MSB _u(6) 1184 #define PADS_BANK0_GPIO16_IE_LSB _u(6) 1185 #define PADS_BANK0_GPIO16_IE_ACCESS "RW" 1186 // ----------------------------------------------------------------------------- 1187 // Field : PADS_BANK0_GPIO16_DRIVE 1188 // Description : Drive strength. 1189 // 0x0 -> 2mA 1190 // 0x1 -> 4mA 1191 // 0x2 -> 8mA 1192 // 0x3 -> 12mA 1193 #define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) 1194 #define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) 1195 #define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) 1196 #define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) 1197 #define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" 1198 #define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) 1199 #define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) 1200 #define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) 1201 #define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) 1202 // ----------------------------------------------------------------------------- 1203 // Field : PADS_BANK0_GPIO16_PUE 1204 // Description : Pull up enable 1205 #define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) 1206 #define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) 1207 #define PADS_BANK0_GPIO16_PUE_MSB _u(3) 1208 #define PADS_BANK0_GPIO16_PUE_LSB _u(3) 1209 #define PADS_BANK0_GPIO16_PUE_ACCESS "RW" 1210 // ----------------------------------------------------------------------------- 1211 // Field : PADS_BANK0_GPIO16_PDE 1212 // Description : Pull down enable 1213 #define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) 1214 #define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) 1215 #define PADS_BANK0_GPIO16_PDE_MSB _u(2) 1216 #define PADS_BANK0_GPIO16_PDE_LSB _u(2) 1217 #define PADS_BANK0_GPIO16_PDE_ACCESS "RW" 1218 // ----------------------------------------------------------------------------- 1219 // Field : PADS_BANK0_GPIO16_SCHMITT 1220 // Description : Enable schmitt trigger 1221 #define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) 1222 #define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) 1223 #define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) 1224 #define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) 1225 #define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" 1226 // ----------------------------------------------------------------------------- 1227 // Field : PADS_BANK0_GPIO16_SLEWFAST 1228 // Description : Slew rate control. 1 = Fast, 0 = Slow 1229 #define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) 1230 #define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) 1231 #define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) 1232 #define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) 1233 #define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" 1234 // ============================================================================= 1235 // Register : PADS_BANK0_GPIO17 1236 // Description : Pad control register 1237 #define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) 1238 #define PADS_BANK0_GPIO17_BITS _u(0x000000ff) 1239 #define PADS_BANK0_GPIO17_RESET _u(0x00000056) 1240 // ----------------------------------------------------------------------------- 1241 // Field : PADS_BANK0_GPIO17_OD 1242 // Description : Output disable. Has priority over output enable from 1243 // peripherals 1244 #define PADS_BANK0_GPIO17_OD_RESET _u(0x0) 1245 #define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) 1246 #define PADS_BANK0_GPIO17_OD_MSB _u(7) 1247 #define PADS_BANK0_GPIO17_OD_LSB _u(7) 1248 #define PADS_BANK0_GPIO17_OD_ACCESS "RW" 1249 // ----------------------------------------------------------------------------- 1250 // Field : PADS_BANK0_GPIO17_IE 1251 // Description : Input enable 1252 #define PADS_BANK0_GPIO17_IE_RESET _u(0x1) 1253 #define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) 1254 #define PADS_BANK0_GPIO17_IE_MSB _u(6) 1255 #define PADS_BANK0_GPIO17_IE_LSB _u(6) 1256 #define PADS_BANK0_GPIO17_IE_ACCESS "RW" 1257 // ----------------------------------------------------------------------------- 1258 // Field : PADS_BANK0_GPIO17_DRIVE 1259 // Description : Drive strength. 1260 // 0x0 -> 2mA 1261 // 0x1 -> 4mA 1262 // 0x2 -> 8mA 1263 // 0x3 -> 12mA 1264 #define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) 1265 #define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) 1266 #define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) 1267 #define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) 1268 #define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" 1269 #define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) 1270 #define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) 1271 #define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) 1272 #define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) 1273 // ----------------------------------------------------------------------------- 1274 // Field : PADS_BANK0_GPIO17_PUE 1275 // Description : Pull up enable 1276 #define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) 1277 #define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) 1278 #define PADS_BANK0_GPIO17_PUE_MSB _u(3) 1279 #define PADS_BANK0_GPIO17_PUE_LSB _u(3) 1280 #define PADS_BANK0_GPIO17_PUE_ACCESS "RW" 1281 // ----------------------------------------------------------------------------- 1282 // Field : PADS_BANK0_GPIO17_PDE 1283 // Description : Pull down enable 1284 #define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) 1285 #define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) 1286 #define PADS_BANK0_GPIO17_PDE_MSB _u(2) 1287 #define PADS_BANK0_GPIO17_PDE_LSB _u(2) 1288 #define PADS_BANK0_GPIO17_PDE_ACCESS "RW" 1289 // ----------------------------------------------------------------------------- 1290 // Field : PADS_BANK0_GPIO17_SCHMITT 1291 // Description : Enable schmitt trigger 1292 #define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) 1293 #define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) 1294 #define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) 1295 #define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) 1296 #define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" 1297 // ----------------------------------------------------------------------------- 1298 // Field : PADS_BANK0_GPIO17_SLEWFAST 1299 // Description : Slew rate control. 1 = Fast, 0 = Slow 1300 #define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) 1301 #define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) 1302 #define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) 1303 #define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) 1304 #define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" 1305 // ============================================================================= 1306 // Register : PADS_BANK0_GPIO18 1307 // Description : Pad control register 1308 #define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) 1309 #define PADS_BANK0_GPIO18_BITS _u(0x000000ff) 1310 #define PADS_BANK0_GPIO18_RESET _u(0x00000056) 1311 // ----------------------------------------------------------------------------- 1312 // Field : PADS_BANK0_GPIO18_OD 1313 // Description : Output disable. Has priority over output enable from 1314 // peripherals 1315 #define PADS_BANK0_GPIO18_OD_RESET _u(0x0) 1316 #define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) 1317 #define PADS_BANK0_GPIO18_OD_MSB _u(7) 1318 #define PADS_BANK0_GPIO18_OD_LSB _u(7) 1319 #define PADS_BANK0_GPIO18_OD_ACCESS "RW" 1320 // ----------------------------------------------------------------------------- 1321 // Field : PADS_BANK0_GPIO18_IE 1322 // Description : Input enable 1323 #define PADS_BANK0_GPIO18_IE_RESET _u(0x1) 1324 #define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) 1325 #define PADS_BANK0_GPIO18_IE_MSB _u(6) 1326 #define PADS_BANK0_GPIO18_IE_LSB _u(6) 1327 #define PADS_BANK0_GPIO18_IE_ACCESS "RW" 1328 // ----------------------------------------------------------------------------- 1329 // Field : PADS_BANK0_GPIO18_DRIVE 1330 // Description : Drive strength. 1331 // 0x0 -> 2mA 1332 // 0x1 -> 4mA 1333 // 0x2 -> 8mA 1334 // 0x3 -> 12mA 1335 #define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) 1336 #define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) 1337 #define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) 1338 #define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) 1339 #define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" 1340 #define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) 1341 #define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) 1342 #define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) 1343 #define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) 1344 // ----------------------------------------------------------------------------- 1345 // Field : PADS_BANK0_GPIO18_PUE 1346 // Description : Pull up enable 1347 #define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) 1348 #define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) 1349 #define PADS_BANK0_GPIO18_PUE_MSB _u(3) 1350 #define PADS_BANK0_GPIO18_PUE_LSB _u(3) 1351 #define PADS_BANK0_GPIO18_PUE_ACCESS "RW" 1352 // ----------------------------------------------------------------------------- 1353 // Field : PADS_BANK0_GPIO18_PDE 1354 // Description : Pull down enable 1355 #define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) 1356 #define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) 1357 #define PADS_BANK0_GPIO18_PDE_MSB _u(2) 1358 #define PADS_BANK0_GPIO18_PDE_LSB _u(2) 1359 #define PADS_BANK0_GPIO18_PDE_ACCESS "RW" 1360 // ----------------------------------------------------------------------------- 1361 // Field : PADS_BANK0_GPIO18_SCHMITT 1362 // Description : Enable schmitt trigger 1363 #define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) 1364 #define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) 1365 #define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) 1366 #define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) 1367 #define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" 1368 // ----------------------------------------------------------------------------- 1369 // Field : PADS_BANK0_GPIO18_SLEWFAST 1370 // Description : Slew rate control. 1 = Fast, 0 = Slow 1371 #define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) 1372 #define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) 1373 #define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) 1374 #define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) 1375 #define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" 1376 // ============================================================================= 1377 // Register : PADS_BANK0_GPIO19 1378 // Description : Pad control register 1379 #define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) 1380 #define PADS_BANK0_GPIO19_BITS _u(0x000000ff) 1381 #define PADS_BANK0_GPIO19_RESET _u(0x00000056) 1382 // ----------------------------------------------------------------------------- 1383 // Field : PADS_BANK0_GPIO19_OD 1384 // Description : Output disable. Has priority over output enable from 1385 // peripherals 1386 #define PADS_BANK0_GPIO19_OD_RESET _u(0x0) 1387 #define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) 1388 #define PADS_BANK0_GPIO19_OD_MSB _u(7) 1389 #define PADS_BANK0_GPIO19_OD_LSB _u(7) 1390 #define PADS_BANK0_GPIO19_OD_ACCESS "RW" 1391 // ----------------------------------------------------------------------------- 1392 // Field : PADS_BANK0_GPIO19_IE 1393 // Description : Input enable 1394 #define PADS_BANK0_GPIO19_IE_RESET _u(0x1) 1395 #define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) 1396 #define PADS_BANK0_GPIO19_IE_MSB _u(6) 1397 #define PADS_BANK0_GPIO19_IE_LSB _u(6) 1398 #define PADS_BANK0_GPIO19_IE_ACCESS "RW" 1399 // ----------------------------------------------------------------------------- 1400 // Field : PADS_BANK0_GPIO19_DRIVE 1401 // Description : Drive strength. 1402 // 0x0 -> 2mA 1403 // 0x1 -> 4mA 1404 // 0x2 -> 8mA 1405 // 0x3 -> 12mA 1406 #define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) 1407 #define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) 1408 #define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) 1409 #define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) 1410 #define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" 1411 #define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) 1412 #define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) 1413 #define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) 1414 #define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) 1415 // ----------------------------------------------------------------------------- 1416 // Field : PADS_BANK0_GPIO19_PUE 1417 // Description : Pull up enable 1418 #define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) 1419 #define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) 1420 #define PADS_BANK0_GPIO19_PUE_MSB _u(3) 1421 #define PADS_BANK0_GPIO19_PUE_LSB _u(3) 1422 #define PADS_BANK0_GPIO19_PUE_ACCESS "RW" 1423 // ----------------------------------------------------------------------------- 1424 // Field : PADS_BANK0_GPIO19_PDE 1425 // Description : Pull down enable 1426 #define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) 1427 #define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) 1428 #define PADS_BANK0_GPIO19_PDE_MSB _u(2) 1429 #define PADS_BANK0_GPIO19_PDE_LSB _u(2) 1430 #define PADS_BANK0_GPIO19_PDE_ACCESS "RW" 1431 // ----------------------------------------------------------------------------- 1432 // Field : PADS_BANK0_GPIO19_SCHMITT 1433 // Description : Enable schmitt trigger 1434 #define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) 1435 #define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) 1436 #define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) 1437 #define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) 1438 #define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" 1439 // ----------------------------------------------------------------------------- 1440 // Field : PADS_BANK0_GPIO19_SLEWFAST 1441 // Description : Slew rate control. 1 = Fast, 0 = Slow 1442 #define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) 1443 #define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) 1444 #define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) 1445 #define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) 1446 #define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" 1447 // ============================================================================= 1448 // Register : PADS_BANK0_GPIO20 1449 // Description : Pad control register 1450 #define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) 1451 #define PADS_BANK0_GPIO20_BITS _u(0x000000ff) 1452 #define PADS_BANK0_GPIO20_RESET _u(0x00000056) 1453 // ----------------------------------------------------------------------------- 1454 // Field : PADS_BANK0_GPIO20_OD 1455 // Description : Output disable. Has priority over output enable from 1456 // peripherals 1457 #define PADS_BANK0_GPIO20_OD_RESET _u(0x0) 1458 #define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) 1459 #define PADS_BANK0_GPIO20_OD_MSB _u(7) 1460 #define PADS_BANK0_GPIO20_OD_LSB _u(7) 1461 #define PADS_BANK0_GPIO20_OD_ACCESS "RW" 1462 // ----------------------------------------------------------------------------- 1463 // Field : PADS_BANK0_GPIO20_IE 1464 // Description : Input enable 1465 #define PADS_BANK0_GPIO20_IE_RESET _u(0x1) 1466 #define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) 1467 #define PADS_BANK0_GPIO20_IE_MSB _u(6) 1468 #define PADS_BANK0_GPIO20_IE_LSB _u(6) 1469 #define PADS_BANK0_GPIO20_IE_ACCESS "RW" 1470 // ----------------------------------------------------------------------------- 1471 // Field : PADS_BANK0_GPIO20_DRIVE 1472 // Description : Drive strength. 1473 // 0x0 -> 2mA 1474 // 0x1 -> 4mA 1475 // 0x2 -> 8mA 1476 // 0x3 -> 12mA 1477 #define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) 1478 #define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) 1479 #define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) 1480 #define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) 1481 #define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" 1482 #define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) 1483 #define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) 1484 #define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) 1485 #define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) 1486 // ----------------------------------------------------------------------------- 1487 // Field : PADS_BANK0_GPIO20_PUE 1488 // Description : Pull up enable 1489 #define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) 1490 #define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) 1491 #define PADS_BANK0_GPIO20_PUE_MSB _u(3) 1492 #define PADS_BANK0_GPIO20_PUE_LSB _u(3) 1493 #define PADS_BANK0_GPIO20_PUE_ACCESS "RW" 1494 // ----------------------------------------------------------------------------- 1495 // Field : PADS_BANK0_GPIO20_PDE 1496 // Description : Pull down enable 1497 #define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) 1498 #define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) 1499 #define PADS_BANK0_GPIO20_PDE_MSB _u(2) 1500 #define PADS_BANK0_GPIO20_PDE_LSB _u(2) 1501 #define PADS_BANK0_GPIO20_PDE_ACCESS "RW" 1502 // ----------------------------------------------------------------------------- 1503 // Field : PADS_BANK0_GPIO20_SCHMITT 1504 // Description : Enable schmitt trigger 1505 #define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) 1506 #define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) 1507 #define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) 1508 #define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) 1509 #define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" 1510 // ----------------------------------------------------------------------------- 1511 // Field : PADS_BANK0_GPIO20_SLEWFAST 1512 // Description : Slew rate control. 1 = Fast, 0 = Slow 1513 #define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) 1514 #define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) 1515 #define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) 1516 #define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) 1517 #define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" 1518 // ============================================================================= 1519 // Register : PADS_BANK0_GPIO21 1520 // Description : Pad control register 1521 #define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) 1522 #define PADS_BANK0_GPIO21_BITS _u(0x000000ff) 1523 #define PADS_BANK0_GPIO21_RESET _u(0x00000056) 1524 // ----------------------------------------------------------------------------- 1525 // Field : PADS_BANK0_GPIO21_OD 1526 // Description : Output disable. Has priority over output enable from 1527 // peripherals 1528 #define PADS_BANK0_GPIO21_OD_RESET _u(0x0) 1529 #define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) 1530 #define PADS_BANK0_GPIO21_OD_MSB _u(7) 1531 #define PADS_BANK0_GPIO21_OD_LSB _u(7) 1532 #define PADS_BANK0_GPIO21_OD_ACCESS "RW" 1533 // ----------------------------------------------------------------------------- 1534 // Field : PADS_BANK0_GPIO21_IE 1535 // Description : Input enable 1536 #define PADS_BANK0_GPIO21_IE_RESET _u(0x1) 1537 #define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) 1538 #define PADS_BANK0_GPIO21_IE_MSB _u(6) 1539 #define PADS_BANK0_GPIO21_IE_LSB _u(6) 1540 #define PADS_BANK0_GPIO21_IE_ACCESS "RW" 1541 // ----------------------------------------------------------------------------- 1542 // Field : PADS_BANK0_GPIO21_DRIVE 1543 // Description : Drive strength. 1544 // 0x0 -> 2mA 1545 // 0x1 -> 4mA 1546 // 0x2 -> 8mA 1547 // 0x3 -> 12mA 1548 #define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) 1549 #define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) 1550 #define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) 1551 #define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) 1552 #define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" 1553 #define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) 1554 #define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) 1555 #define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) 1556 #define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) 1557 // ----------------------------------------------------------------------------- 1558 // Field : PADS_BANK0_GPIO21_PUE 1559 // Description : Pull up enable 1560 #define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) 1561 #define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) 1562 #define PADS_BANK0_GPIO21_PUE_MSB _u(3) 1563 #define PADS_BANK0_GPIO21_PUE_LSB _u(3) 1564 #define PADS_BANK0_GPIO21_PUE_ACCESS "RW" 1565 // ----------------------------------------------------------------------------- 1566 // Field : PADS_BANK0_GPIO21_PDE 1567 // Description : Pull down enable 1568 #define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) 1569 #define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) 1570 #define PADS_BANK0_GPIO21_PDE_MSB _u(2) 1571 #define PADS_BANK0_GPIO21_PDE_LSB _u(2) 1572 #define PADS_BANK0_GPIO21_PDE_ACCESS "RW" 1573 // ----------------------------------------------------------------------------- 1574 // Field : PADS_BANK0_GPIO21_SCHMITT 1575 // Description : Enable schmitt trigger 1576 #define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) 1577 #define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) 1578 #define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) 1579 #define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) 1580 #define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" 1581 // ----------------------------------------------------------------------------- 1582 // Field : PADS_BANK0_GPIO21_SLEWFAST 1583 // Description : Slew rate control. 1 = Fast, 0 = Slow 1584 #define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) 1585 #define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) 1586 #define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) 1587 #define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) 1588 #define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" 1589 // ============================================================================= 1590 // Register : PADS_BANK0_GPIO22 1591 // Description : Pad control register 1592 #define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) 1593 #define PADS_BANK0_GPIO22_BITS _u(0x000000ff) 1594 #define PADS_BANK0_GPIO22_RESET _u(0x00000056) 1595 // ----------------------------------------------------------------------------- 1596 // Field : PADS_BANK0_GPIO22_OD 1597 // Description : Output disable. Has priority over output enable from 1598 // peripherals 1599 #define PADS_BANK0_GPIO22_OD_RESET _u(0x0) 1600 #define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) 1601 #define PADS_BANK0_GPIO22_OD_MSB _u(7) 1602 #define PADS_BANK0_GPIO22_OD_LSB _u(7) 1603 #define PADS_BANK0_GPIO22_OD_ACCESS "RW" 1604 // ----------------------------------------------------------------------------- 1605 // Field : PADS_BANK0_GPIO22_IE 1606 // Description : Input enable 1607 #define PADS_BANK0_GPIO22_IE_RESET _u(0x1) 1608 #define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) 1609 #define PADS_BANK0_GPIO22_IE_MSB _u(6) 1610 #define PADS_BANK0_GPIO22_IE_LSB _u(6) 1611 #define PADS_BANK0_GPIO22_IE_ACCESS "RW" 1612 // ----------------------------------------------------------------------------- 1613 // Field : PADS_BANK0_GPIO22_DRIVE 1614 // Description : Drive strength. 1615 // 0x0 -> 2mA 1616 // 0x1 -> 4mA 1617 // 0x2 -> 8mA 1618 // 0x3 -> 12mA 1619 #define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) 1620 #define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) 1621 #define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) 1622 #define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) 1623 #define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" 1624 #define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) 1625 #define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) 1626 #define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) 1627 #define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) 1628 // ----------------------------------------------------------------------------- 1629 // Field : PADS_BANK0_GPIO22_PUE 1630 // Description : Pull up enable 1631 #define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) 1632 #define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) 1633 #define PADS_BANK0_GPIO22_PUE_MSB _u(3) 1634 #define PADS_BANK0_GPIO22_PUE_LSB _u(3) 1635 #define PADS_BANK0_GPIO22_PUE_ACCESS "RW" 1636 // ----------------------------------------------------------------------------- 1637 // Field : PADS_BANK0_GPIO22_PDE 1638 // Description : Pull down enable 1639 #define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) 1640 #define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) 1641 #define PADS_BANK0_GPIO22_PDE_MSB _u(2) 1642 #define PADS_BANK0_GPIO22_PDE_LSB _u(2) 1643 #define PADS_BANK0_GPIO22_PDE_ACCESS "RW" 1644 // ----------------------------------------------------------------------------- 1645 // Field : PADS_BANK0_GPIO22_SCHMITT 1646 // Description : Enable schmitt trigger 1647 #define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) 1648 #define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) 1649 #define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) 1650 #define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) 1651 #define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" 1652 // ----------------------------------------------------------------------------- 1653 // Field : PADS_BANK0_GPIO22_SLEWFAST 1654 // Description : Slew rate control. 1 = Fast, 0 = Slow 1655 #define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) 1656 #define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) 1657 #define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) 1658 #define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) 1659 #define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" 1660 // ============================================================================= 1661 // Register : PADS_BANK0_GPIO23 1662 // Description : Pad control register 1663 #define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) 1664 #define PADS_BANK0_GPIO23_BITS _u(0x000000ff) 1665 #define PADS_BANK0_GPIO23_RESET _u(0x00000056) 1666 // ----------------------------------------------------------------------------- 1667 // Field : PADS_BANK0_GPIO23_OD 1668 // Description : Output disable. Has priority over output enable from 1669 // peripherals 1670 #define PADS_BANK0_GPIO23_OD_RESET _u(0x0) 1671 #define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) 1672 #define PADS_BANK0_GPIO23_OD_MSB _u(7) 1673 #define PADS_BANK0_GPIO23_OD_LSB _u(7) 1674 #define PADS_BANK0_GPIO23_OD_ACCESS "RW" 1675 // ----------------------------------------------------------------------------- 1676 // Field : PADS_BANK0_GPIO23_IE 1677 // Description : Input enable 1678 #define PADS_BANK0_GPIO23_IE_RESET _u(0x1) 1679 #define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) 1680 #define PADS_BANK0_GPIO23_IE_MSB _u(6) 1681 #define PADS_BANK0_GPIO23_IE_LSB _u(6) 1682 #define PADS_BANK0_GPIO23_IE_ACCESS "RW" 1683 // ----------------------------------------------------------------------------- 1684 // Field : PADS_BANK0_GPIO23_DRIVE 1685 // Description : Drive strength. 1686 // 0x0 -> 2mA 1687 // 0x1 -> 4mA 1688 // 0x2 -> 8mA 1689 // 0x3 -> 12mA 1690 #define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) 1691 #define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) 1692 #define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) 1693 #define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) 1694 #define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" 1695 #define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) 1696 #define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) 1697 #define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) 1698 #define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) 1699 // ----------------------------------------------------------------------------- 1700 // Field : PADS_BANK0_GPIO23_PUE 1701 // Description : Pull up enable 1702 #define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) 1703 #define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) 1704 #define PADS_BANK0_GPIO23_PUE_MSB _u(3) 1705 #define PADS_BANK0_GPIO23_PUE_LSB _u(3) 1706 #define PADS_BANK0_GPIO23_PUE_ACCESS "RW" 1707 // ----------------------------------------------------------------------------- 1708 // Field : PADS_BANK0_GPIO23_PDE 1709 // Description : Pull down enable 1710 #define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) 1711 #define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) 1712 #define PADS_BANK0_GPIO23_PDE_MSB _u(2) 1713 #define PADS_BANK0_GPIO23_PDE_LSB _u(2) 1714 #define PADS_BANK0_GPIO23_PDE_ACCESS "RW" 1715 // ----------------------------------------------------------------------------- 1716 // Field : PADS_BANK0_GPIO23_SCHMITT 1717 // Description : Enable schmitt trigger 1718 #define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) 1719 #define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) 1720 #define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) 1721 #define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) 1722 #define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" 1723 // ----------------------------------------------------------------------------- 1724 // Field : PADS_BANK0_GPIO23_SLEWFAST 1725 // Description : Slew rate control. 1 = Fast, 0 = Slow 1726 #define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) 1727 #define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) 1728 #define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) 1729 #define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) 1730 #define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" 1731 // ============================================================================= 1732 // Register : PADS_BANK0_GPIO24 1733 // Description : Pad control register 1734 #define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) 1735 #define PADS_BANK0_GPIO24_BITS _u(0x000000ff) 1736 #define PADS_BANK0_GPIO24_RESET _u(0x00000056) 1737 // ----------------------------------------------------------------------------- 1738 // Field : PADS_BANK0_GPIO24_OD 1739 // Description : Output disable. Has priority over output enable from 1740 // peripherals 1741 #define PADS_BANK0_GPIO24_OD_RESET _u(0x0) 1742 #define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) 1743 #define PADS_BANK0_GPIO24_OD_MSB _u(7) 1744 #define PADS_BANK0_GPIO24_OD_LSB _u(7) 1745 #define PADS_BANK0_GPIO24_OD_ACCESS "RW" 1746 // ----------------------------------------------------------------------------- 1747 // Field : PADS_BANK0_GPIO24_IE 1748 // Description : Input enable 1749 #define PADS_BANK0_GPIO24_IE_RESET _u(0x1) 1750 #define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) 1751 #define PADS_BANK0_GPIO24_IE_MSB _u(6) 1752 #define PADS_BANK0_GPIO24_IE_LSB _u(6) 1753 #define PADS_BANK0_GPIO24_IE_ACCESS "RW" 1754 // ----------------------------------------------------------------------------- 1755 // Field : PADS_BANK0_GPIO24_DRIVE 1756 // Description : Drive strength. 1757 // 0x0 -> 2mA 1758 // 0x1 -> 4mA 1759 // 0x2 -> 8mA 1760 // 0x3 -> 12mA 1761 #define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) 1762 #define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) 1763 #define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) 1764 #define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) 1765 #define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" 1766 #define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) 1767 #define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) 1768 #define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) 1769 #define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) 1770 // ----------------------------------------------------------------------------- 1771 // Field : PADS_BANK0_GPIO24_PUE 1772 // Description : Pull up enable 1773 #define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) 1774 #define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) 1775 #define PADS_BANK0_GPIO24_PUE_MSB _u(3) 1776 #define PADS_BANK0_GPIO24_PUE_LSB _u(3) 1777 #define PADS_BANK0_GPIO24_PUE_ACCESS "RW" 1778 // ----------------------------------------------------------------------------- 1779 // Field : PADS_BANK0_GPIO24_PDE 1780 // Description : Pull down enable 1781 #define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) 1782 #define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) 1783 #define PADS_BANK0_GPIO24_PDE_MSB _u(2) 1784 #define PADS_BANK0_GPIO24_PDE_LSB _u(2) 1785 #define PADS_BANK0_GPIO24_PDE_ACCESS "RW" 1786 // ----------------------------------------------------------------------------- 1787 // Field : PADS_BANK0_GPIO24_SCHMITT 1788 // Description : Enable schmitt trigger 1789 #define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) 1790 #define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) 1791 #define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) 1792 #define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) 1793 #define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" 1794 // ----------------------------------------------------------------------------- 1795 // Field : PADS_BANK0_GPIO24_SLEWFAST 1796 // Description : Slew rate control. 1 = Fast, 0 = Slow 1797 #define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) 1798 #define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) 1799 #define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) 1800 #define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) 1801 #define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" 1802 // ============================================================================= 1803 // Register : PADS_BANK0_GPIO25 1804 // Description : Pad control register 1805 #define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) 1806 #define PADS_BANK0_GPIO25_BITS _u(0x000000ff) 1807 #define PADS_BANK0_GPIO25_RESET _u(0x00000056) 1808 // ----------------------------------------------------------------------------- 1809 // Field : PADS_BANK0_GPIO25_OD 1810 // Description : Output disable. Has priority over output enable from 1811 // peripherals 1812 #define PADS_BANK0_GPIO25_OD_RESET _u(0x0) 1813 #define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) 1814 #define PADS_BANK0_GPIO25_OD_MSB _u(7) 1815 #define PADS_BANK0_GPIO25_OD_LSB _u(7) 1816 #define PADS_BANK0_GPIO25_OD_ACCESS "RW" 1817 // ----------------------------------------------------------------------------- 1818 // Field : PADS_BANK0_GPIO25_IE 1819 // Description : Input enable 1820 #define PADS_BANK0_GPIO25_IE_RESET _u(0x1) 1821 #define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) 1822 #define PADS_BANK0_GPIO25_IE_MSB _u(6) 1823 #define PADS_BANK0_GPIO25_IE_LSB _u(6) 1824 #define PADS_BANK0_GPIO25_IE_ACCESS "RW" 1825 // ----------------------------------------------------------------------------- 1826 // Field : PADS_BANK0_GPIO25_DRIVE 1827 // Description : Drive strength. 1828 // 0x0 -> 2mA 1829 // 0x1 -> 4mA 1830 // 0x2 -> 8mA 1831 // 0x3 -> 12mA 1832 #define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) 1833 #define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) 1834 #define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) 1835 #define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) 1836 #define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" 1837 #define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) 1838 #define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) 1839 #define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) 1840 #define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) 1841 // ----------------------------------------------------------------------------- 1842 // Field : PADS_BANK0_GPIO25_PUE 1843 // Description : Pull up enable 1844 #define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) 1845 #define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) 1846 #define PADS_BANK0_GPIO25_PUE_MSB _u(3) 1847 #define PADS_BANK0_GPIO25_PUE_LSB _u(3) 1848 #define PADS_BANK0_GPIO25_PUE_ACCESS "RW" 1849 // ----------------------------------------------------------------------------- 1850 // Field : PADS_BANK0_GPIO25_PDE 1851 // Description : Pull down enable 1852 #define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) 1853 #define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) 1854 #define PADS_BANK0_GPIO25_PDE_MSB _u(2) 1855 #define PADS_BANK0_GPIO25_PDE_LSB _u(2) 1856 #define PADS_BANK0_GPIO25_PDE_ACCESS "RW" 1857 // ----------------------------------------------------------------------------- 1858 // Field : PADS_BANK0_GPIO25_SCHMITT 1859 // Description : Enable schmitt trigger 1860 #define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) 1861 #define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) 1862 #define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) 1863 #define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) 1864 #define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" 1865 // ----------------------------------------------------------------------------- 1866 // Field : PADS_BANK0_GPIO25_SLEWFAST 1867 // Description : Slew rate control. 1 = Fast, 0 = Slow 1868 #define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) 1869 #define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) 1870 #define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) 1871 #define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) 1872 #define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" 1873 // ============================================================================= 1874 // Register : PADS_BANK0_GPIO26 1875 // Description : Pad control register 1876 #define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) 1877 #define PADS_BANK0_GPIO26_BITS _u(0x000000ff) 1878 #define PADS_BANK0_GPIO26_RESET _u(0x00000056) 1879 // ----------------------------------------------------------------------------- 1880 // Field : PADS_BANK0_GPIO26_OD 1881 // Description : Output disable. Has priority over output enable from 1882 // peripherals 1883 #define PADS_BANK0_GPIO26_OD_RESET _u(0x0) 1884 #define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) 1885 #define PADS_BANK0_GPIO26_OD_MSB _u(7) 1886 #define PADS_BANK0_GPIO26_OD_LSB _u(7) 1887 #define PADS_BANK0_GPIO26_OD_ACCESS "RW" 1888 // ----------------------------------------------------------------------------- 1889 // Field : PADS_BANK0_GPIO26_IE 1890 // Description : Input enable 1891 #define PADS_BANK0_GPIO26_IE_RESET _u(0x1) 1892 #define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) 1893 #define PADS_BANK0_GPIO26_IE_MSB _u(6) 1894 #define PADS_BANK0_GPIO26_IE_LSB _u(6) 1895 #define PADS_BANK0_GPIO26_IE_ACCESS "RW" 1896 // ----------------------------------------------------------------------------- 1897 // Field : PADS_BANK0_GPIO26_DRIVE 1898 // Description : Drive strength. 1899 // 0x0 -> 2mA 1900 // 0x1 -> 4mA 1901 // 0x2 -> 8mA 1902 // 0x3 -> 12mA 1903 #define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) 1904 #define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) 1905 #define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) 1906 #define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) 1907 #define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" 1908 #define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) 1909 #define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) 1910 #define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) 1911 #define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) 1912 // ----------------------------------------------------------------------------- 1913 // Field : PADS_BANK0_GPIO26_PUE 1914 // Description : Pull up enable 1915 #define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) 1916 #define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) 1917 #define PADS_BANK0_GPIO26_PUE_MSB _u(3) 1918 #define PADS_BANK0_GPIO26_PUE_LSB _u(3) 1919 #define PADS_BANK0_GPIO26_PUE_ACCESS "RW" 1920 // ----------------------------------------------------------------------------- 1921 // Field : PADS_BANK0_GPIO26_PDE 1922 // Description : Pull down enable 1923 #define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) 1924 #define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) 1925 #define PADS_BANK0_GPIO26_PDE_MSB _u(2) 1926 #define PADS_BANK0_GPIO26_PDE_LSB _u(2) 1927 #define PADS_BANK0_GPIO26_PDE_ACCESS "RW" 1928 // ----------------------------------------------------------------------------- 1929 // Field : PADS_BANK0_GPIO26_SCHMITT 1930 // Description : Enable schmitt trigger 1931 #define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) 1932 #define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) 1933 #define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) 1934 #define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) 1935 #define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" 1936 // ----------------------------------------------------------------------------- 1937 // Field : PADS_BANK0_GPIO26_SLEWFAST 1938 // Description : Slew rate control. 1 = Fast, 0 = Slow 1939 #define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) 1940 #define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) 1941 #define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) 1942 #define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) 1943 #define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" 1944 // ============================================================================= 1945 // Register : PADS_BANK0_GPIO27 1946 // Description : Pad control register 1947 #define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) 1948 #define PADS_BANK0_GPIO27_BITS _u(0x000000ff) 1949 #define PADS_BANK0_GPIO27_RESET _u(0x00000056) 1950 // ----------------------------------------------------------------------------- 1951 // Field : PADS_BANK0_GPIO27_OD 1952 // Description : Output disable. Has priority over output enable from 1953 // peripherals 1954 #define PADS_BANK0_GPIO27_OD_RESET _u(0x0) 1955 #define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) 1956 #define PADS_BANK0_GPIO27_OD_MSB _u(7) 1957 #define PADS_BANK0_GPIO27_OD_LSB _u(7) 1958 #define PADS_BANK0_GPIO27_OD_ACCESS "RW" 1959 // ----------------------------------------------------------------------------- 1960 // Field : PADS_BANK0_GPIO27_IE 1961 // Description : Input enable 1962 #define PADS_BANK0_GPIO27_IE_RESET _u(0x1) 1963 #define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) 1964 #define PADS_BANK0_GPIO27_IE_MSB _u(6) 1965 #define PADS_BANK0_GPIO27_IE_LSB _u(6) 1966 #define PADS_BANK0_GPIO27_IE_ACCESS "RW" 1967 // ----------------------------------------------------------------------------- 1968 // Field : PADS_BANK0_GPIO27_DRIVE 1969 // Description : Drive strength. 1970 // 0x0 -> 2mA 1971 // 0x1 -> 4mA 1972 // 0x2 -> 8mA 1973 // 0x3 -> 12mA 1974 #define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) 1975 #define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) 1976 #define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) 1977 #define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) 1978 #define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" 1979 #define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) 1980 #define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) 1981 #define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) 1982 #define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) 1983 // ----------------------------------------------------------------------------- 1984 // Field : PADS_BANK0_GPIO27_PUE 1985 // Description : Pull up enable 1986 #define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) 1987 #define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) 1988 #define PADS_BANK0_GPIO27_PUE_MSB _u(3) 1989 #define PADS_BANK0_GPIO27_PUE_LSB _u(3) 1990 #define PADS_BANK0_GPIO27_PUE_ACCESS "RW" 1991 // ----------------------------------------------------------------------------- 1992 // Field : PADS_BANK0_GPIO27_PDE 1993 // Description : Pull down enable 1994 #define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) 1995 #define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) 1996 #define PADS_BANK0_GPIO27_PDE_MSB _u(2) 1997 #define PADS_BANK0_GPIO27_PDE_LSB _u(2) 1998 #define PADS_BANK0_GPIO27_PDE_ACCESS "RW" 1999 // ----------------------------------------------------------------------------- 2000 // Field : PADS_BANK0_GPIO27_SCHMITT 2001 // Description : Enable schmitt trigger 2002 #define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) 2003 #define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) 2004 #define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) 2005 #define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) 2006 #define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" 2007 // ----------------------------------------------------------------------------- 2008 // Field : PADS_BANK0_GPIO27_SLEWFAST 2009 // Description : Slew rate control. 1 = Fast, 0 = Slow 2010 #define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) 2011 #define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) 2012 #define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) 2013 #define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) 2014 #define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" 2015 // ============================================================================= 2016 // Register : PADS_BANK0_GPIO28 2017 // Description : Pad control register 2018 #define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) 2019 #define PADS_BANK0_GPIO28_BITS _u(0x000000ff) 2020 #define PADS_BANK0_GPIO28_RESET _u(0x00000056) 2021 // ----------------------------------------------------------------------------- 2022 // Field : PADS_BANK0_GPIO28_OD 2023 // Description : Output disable. Has priority over output enable from 2024 // peripherals 2025 #define PADS_BANK0_GPIO28_OD_RESET _u(0x0) 2026 #define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) 2027 #define PADS_BANK0_GPIO28_OD_MSB _u(7) 2028 #define PADS_BANK0_GPIO28_OD_LSB _u(7) 2029 #define PADS_BANK0_GPIO28_OD_ACCESS "RW" 2030 // ----------------------------------------------------------------------------- 2031 // Field : PADS_BANK0_GPIO28_IE 2032 // Description : Input enable 2033 #define PADS_BANK0_GPIO28_IE_RESET _u(0x1) 2034 #define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) 2035 #define PADS_BANK0_GPIO28_IE_MSB _u(6) 2036 #define PADS_BANK0_GPIO28_IE_LSB _u(6) 2037 #define PADS_BANK0_GPIO28_IE_ACCESS "RW" 2038 // ----------------------------------------------------------------------------- 2039 // Field : PADS_BANK0_GPIO28_DRIVE 2040 // Description : Drive strength. 2041 // 0x0 -> 2mA 2042 // 0x1 -> 4mA 2043 // 0x2 -> 8mA 2044 // 0x3 -> 12mA 2045 #define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) 2046 #define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) 2047 #define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) 2048 #define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) 2049 #define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" 2050 #define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) 2051 #define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) 2052 #define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) 2053 #define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) 2054 // ----------------------------------------------------------------------------- 2055 // Field : PADS_BANK0_GPIO28_PUE 2056 // Description : Pull up enable 2057 #define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) 2058 #define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) 2059 #define PADS_BANK0_GPIO28_PUE_MSB _u(3) 2060 #define PADS_BANK0_GPIO28_PUE_LSB _u(3) 2061 #define PADS_BANK0_GPIO28_PUE_ACCESS "RW" 2062 // ----------------------------------------------------------------------------- 2063 // Field : PADS_BANK0_GPIO28_PDE 2064 // Description : Pull down enable 2065 #define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) 2066 #define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) 2067 #define PADS_BANK0_GPIO28_PDE_MSB _u(2) 2068 #define PADS_BANK0_GPIO28_PDE_LSB _u(2) 2069 #define PADS_BANK0_GPIO28_PDE_ACCESS "RW" 2070 // ----------------------------------------------------------------------------- 2071 // Field : PADS_BANK0_GPIO28_SCHMITT 2072 // Description : Enable schmitt trigger 2073 #define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) 2074 #define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) 2075 #define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) 2076 #define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) 2077 #define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" 2078 // ----------------------------------------------------------------------------- 2079 // Field : PADS_BANK0_GPIO28_SLEWFAST 2080 // Description : Slew rate control. 1 = Fast, 0 = Slow 2081 #define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) 2082 #define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) 2083 #define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) 2084 #define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) 2085 #define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" 2086 // ============================================================================= 2087 // Register : PADS_BANK0_GPIO29 2088 // Description : Pad control register 2089 #define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) 2090 #define PADS_BANK0_GPIO29_BITS _u(0x000000ff) 2091 #define PADS_BANK0_GPIO29_RESET _u(0x00000056) 2092 // ----------------------------------------------------------------------------- 2093 // Field : PADS_BANK0_GPIO29_OD 2094 // Description : Output disable. Has priority over output enable from 2095 // peripherals 2096 #define PADS_BANK0_GPIO29_OD_RESET _u(0x0) 2097 #define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) 2098 #define PADS_BANK0_GPIO29_OD_MSB _u(7) 2099 #define PADS_BANK0_GPIO29_OD_LSB _u(7) 2100 #define PADS_BANK0_GPIO29_OD_ACCESS "RW" 2101 // ----------------------------------------------------------------------------- 2102 // Field : PADS_BANK0_GPIO29_IE 2103 // Description : Input enable 2104 #define PADS_BANK0_GPIO29_IE_RESET _u(0x1) 2105 #define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) 2106 #define PADS_BANK0_GPIO29_IE_MSB _u(6) 2107 #define PADS_BANK0_GPIO29_IE_LSB _u(6) 2108 #define PADS_BANK0_GPIO29_IE_ACCESS "RW" 2109 // ----------------------------------------------------------------------------- 2110 // Field : PADS_BANK0_GPIO29_DRIVE 2111 // Description : Drive strength. 2112 // 0x0 -> 2mA 2113 // 0x1 -> 4mA 2114 // 0x2 -> 8mA 2115 // 0x3 -> 12mA 2116 #define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) 2117 #define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) 2118 #define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) 2119 #define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) 2120 #define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" 2121 #define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) 2122 #define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) 2123 #define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) 2124 #define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) 2125 // ----------------------------------------------------------------------------- 2126 // Field : PADS_BANK0_GPIO29_PUE 2127 // Description : Pull up enable 2128 #define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) 2129 #define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) 2130 #define PADS_BANK0_GPIO29_PUE_MSB _u(3) 2131 #define PADS_BANK0_GPIO29_PUE_LSB _u(3) 2132 #define PADS_BANK0_GPIO29_PUE_ACCESS "RW" 2133 // ----------------------------------------------------------------------------- 2134 // Field : PADS_BANK0_GPIO29_PDE 2135 // Description : Pull down enable 2136 #define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) 2137 #define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) 2138 #define PADS_BANK0_GPIO29_PDE_MSB _u(2) 2139 #define PADS_BANK0_GPIO29_PDE_LSB _u(2) 2140 #define PADS_BANK0_GPIO29_PDE_ACCESS "RW" 2141 // ----------------------------------------------------------------------------- 2142 // Field : PADS_BANK0_GPIO29_SCHMITT 2143 // Description : Enable schmitt trigger 2144 #define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) 2145 #define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) 2146 #define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) 2147 #define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) 2148 #define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" 2149 // ----------------------------------------------------------------------------- 2150 // Field : PADS_BANK0_GPIO29_SLEWFAST 2151 // Description : Slew rate control. 1 = Fast, 0 = Slow 2152 #define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) 2153 #define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) 2154 #define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) 2155 #define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) 2156 #define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" 2157 // ============================================================================= 2158 // Register : PADS_BANK0_SWCLK 2159 // Description : Pad control register 2160 #define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c) 2161 #define PADS_BANK0_SWCLK_BITS _u(0x000000ff) 2162 #define PADS_BANK0_SWCLK_RESET _u(0x000000da) 2163 // ----------------------------------------------------------------------------- 2164 // Field : PADS_BANK0_SWCLK_OD 2165 // Description : Output disable. Has priority over output enable from 2166 // peripherals 2167 #define PADS_BANK0_SWCLK_OD_RESET _u(0x1) 2168 #define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) 2169 #define PADS_BANK0_SWCLK_OD_MSB _u(7) 2170 #define PADS_BANK0_SWCLK_OD_LSB _u(7) 2171 #define PADS_BANK0_SWCLK_OD_ACCESS "RW" 2172 // ----------------------------------------------------------------------------- 2173 // Field : PADS_BANK0_SWCLK_IE 2174 // Description : Input enable 2175 #define PADS_BANK0_SWCLK_IE_RESET _u(0x1) 2176 #define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) 2177 #define PADS_BANK0_SWCLK_IE_MSB _u(6) 2178 #define PADS_BANK0_SWCLK_IE_LSB _u(6) 2179 #define PADS_BANK0_SWCLK_IE_ACCESS "RW" 2180 // ----------------------------------------------------------------------------- 2181 // Field : PADS_BANK0_SWCLK_DRIVE 2182 // Description : Drive strength. 2183 // 0x0 -> 2mA 2184 // 0x1 -> 4mA 2185 // 0x2 -> 8mA 2186 // 0x3 -> 12mA 2187 #define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) 2188 #define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) 2189 #define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) 2190 #define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) 2191 #define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" 2192 #define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) 2193 #define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) 2194 #define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) 2195 #define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) 2196 // ----------------------------------------------------------------------------- 2197 // Field : PADS_BANK0_SWCLK_PUE 2198 // Description : Pull up enable 2199 #define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) 2200 #define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) 2201 #define PADS_BANK0_SWCLK_PUE_MSB _u(3) 2202 #define PADS_BANK0_SWCLK_PUE_LSB _u(3) 2203 #define PADS_BANK0_SWCLK_PUE_ACCESS "RW" 2204 // ----------------------------------------------------------------------------- 2205 // Field : PADS_BANK0_SWCLK_PDE 2206 // Description : Pull down enable 2207 #define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) 2208 #define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) 2209 #define PADS_BANK0_SWCLK_PDE_MSB _u(2) 2210 #define PADS_BANK0_SWCLK_PDE_LSB _u(2) 2211 #define PADS_BANK0_SWCLK_PDE_ACCESS "RW" 2212 // ----------------------------------------------------------------------------- 2213 // Field : PADS_BANK0_SWCLK_SCHMITT 2214 // Description : Enable schmitt trigger 2215 #define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) 2216 #define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) 2217 #define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) 2218 #define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) 2219 #define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" 2220 // ----------------------------------------------------------------------------- 2221 // Field : PADS_BANK0_SWCLK_SLEWFAST 2222 // Description : Slew rate control. 1 = Fast, 0 = Slow 2223 #define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) 2224 #define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) 2225 #define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) 2226 #define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) 2227 #define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" 2228 // ============================================================================= 2229 // Register : PADS_BANK0_SWD 2230 // Description : Pad control register 2231 #define PADS_BANK0_SWD_OFFSET _u(0x00000080) 2232 #define PADS_BANK0_SWD_BITS _u(0x000000ff) 2233 #define PADS_BANK0_SWD_RESET _u(0x0000005a) 2234 // ----------------------------------------------------------------------------- 2235 // Field : PADS_BANK0_SWD_OD 2236 // Description : Output disable. Has priority over output enable from 2237 // peripherals 2238 #define PADS_BANK0_SWD_OD_RESET _u(0x0) 2239 #define PADS_BANK0_SWD_OD_BITS _u(0x00000080) 2240 #define PADS_BANK0_SWD_OD_MSB _u(7) 2241 #define PADS_BANK0_SWD_OD_LSB _u(7) 2242 #define PADS_BANK0_SWD_OD_ACCESS "RW" 2243 // ----------------------------------------------------------------------------- 2244 // Field : PADS_BANK0_SWD_IE 2245 // Description : Input enable 2246 #define PADS_BANK0_SWD_IE_RESET _u(0x1) 2247 #define PADS_BANK0_SWD_IE_BITS _u(0x00000040) 2248 #define PADS_BANK0_SWD_IE_MSB _u(6) 2249 #define PADS_BANK0_SWD_IE_LSB _u(6) 2250 #define PADS_BANK0_SWD_IE_ACCESS "RW" 2251 // ----------------------------------------------------------------------------- 2252 // Field : PADS_BANK0_SWD_DRIVE 2253 // Description : Drive strength. 2254 // 0x0 -> 2mA 2255 // 0x1 -> 4mA 2256 // 0x2 -> 8mA 2257 // 0x3 -> 12mA 2258 #define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) 2259 #define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) 2260 #define PADS_BANK0_SWD_DRIVE_MSB _u(5) 2261 #define PADS_BANK0_SWD_DRIVE_LSB _u(4) 2262 #define PADS_BANK0_SWD_DRIVE_ACCESS "RW" 2263 #define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) 2264 #define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) 2265 #define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) 2266 #define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) 2267 // ----------------------------------------------------------------------------- 2268 // Field : PADS_BANK0_SWD_PUE 2269 // Description : Pull up enable 2270 #define PADS_BANK0_SWD_PUE_RESET _u(0x1) 2271 #define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) 2272 #define PADS_BANK0_SWD_PUE_MSB _u(3) 2273 #define PADS_BANK0_SWD_PUE_LSB _u(3) 2274 #define PADS_BANK0_SWD_PUE_ACCESS "RW" 2275 // ----------------------------------------------------------------------------- 2276 // Field : PADS_BANK0_SWD_PDE 2277 // Description : Pull down enable 2278 #define PADS_BANK0_SWD_PDE_RESET _u(0x0) 2279 #define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) 2280 #define PADS_BANK0_SWD_PDE_MSB _u(2) 2281 #define PADS_BANK0_SWD_PDE_LSB _u(2) 2282 #define PADS_BANK0_SWD_PDE_ACCESS "RW" 2283 // ----------------------------------------------------------------------------- 2284 // Field : PADS_BANK0_SWD_SCHMITT 2285 // Description : Enable schmitt trigger 2286 #define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) 2287 #define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) 2288 #define PADS_BANK0_SWD_SCHMITT_MSB _u(1) 2289 #define PADS_BANK0_SWD_SCHMITT_LSB _u(1) 2290 #define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" 2291 // ----------------------------------------------------------------------------- 2292 // Field : PADS_BANK0_SWD_SLEWFAST 2293 // Description : Slew rate control. 1 = Fast, 0 = Slow 2294 #define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) 2295 #define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) 2296 #define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) 2297 #define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) 2298 #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" 2299 // ============================================================================= 2300 #endif // HARDWARE_REGS_PADS_BANK0_DEFINED 2301
