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/hal_rpi_pico-3.4.0/src/rp2_common/cmsis/stub/CMSIS/Core/Include/
Dcore_cm0plus.h330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ member
746 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
764 … return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); in __NVIC_GetEnableIRQ()