1 /**
2  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 // =============================================================================
7 // Register block : IO_BANK0
8 // Version        : 1
9 // Bus type       : apb
10 // Description    : None
11 // =============================================================================
12 #ifndef HARDWARE_REGS_IO_BANK0_DEFINED
13 #define HARDWARE_REGS_IO_BANK0_DEFINED
14 // =============================================================================
15 // Register    : IO_BANK0_GPIO0_STATUS
16 // Description : GPIO status
17 #define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)
18 #define IO_BANK0_GPIO0_STATUS_BITS   _u(0x050a3300)
19 #define IO_BANK0_GPIO0_STATUS_RESET  _u(0x00000000)
20 // -----------------------------------------------------------------------------
21 // Field       : IO_BANK0_GPIO0_STATUS_IRQTOPROC
22 // Description : interrupt to processors, after override is applied
23 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET  _u(0x0)
24 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS   _u(0x04000000)
25 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB    _u(26)
26 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB    _u(26)
27 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO"
28 // -----------------------------------------------------------------------------
29 // Field       : IO_BANK0_GPIO0_STATUS_IRQFROMPAD
30 // Description : interrupt from pad before override is applied
31 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET  _u(0x0)
32 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
33 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB    _u(24)
34 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB    _u(24)
35 #define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO"
36 // -----------------------------------------------------------------------------
37 // Field       : IO_BANK0_GPIO0_STATUS_INTOPERI
38 // Description : input signal to peripheral, after override is applied
39 #define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET  _u(0x0)
40 #define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS   _u(0x00080000)
41 #define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB    _u(19)
42 #define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB    _u(19)
43 #define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO"
44 // -----------------------------------------------------------------------------
45 // Field       : IO_BANK0_GPIO0_STATUS_INFROMPAD
46 // Description : input signal from pad, before override is applied
47 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET  _u(0x0)
48 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS   _u(0x00020000)
49 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB    _u(17)
50 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB    _u(17)
51 #define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO"
52 // -----------------------------------------------------------------------------
53 // Field       : IO_BANK0_GPIO0_STATUS_OETOPAD
54 // Description : output enable to pad after register override is applied
55 #define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET  _u(0x0)
56 #define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS   _u(0x00002000)
57 #define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB    _u(13)
58 #define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB    _u(13)
59 #define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO"
60 // -----------------------------------------------------------------------------
61 // Field       : IO_BANK0_GPIO0_STATUS_OEFROMPERI
62 // Description : output enable from selected peripheral, before register
63 //               override is applied
64 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET  _u(0x0)
65 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS   _u(0x00001000)
66 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB    _u(12)
67 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB    _u(12)
68 #define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO"
69 // -----------------------------------------------------------------------------
70 // Field       : IO_BANK0_GPIO0_STATUS_OUTTOPAD
71 // Description : output signal to pad after register override is applied
72 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET  _u(0x0)
73 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS   _u(0x00000200)
74 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB    _u(9)
75 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB    _u(9)
76 #define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO"
77 // -----------------------------------------------------------------------------
78 // Field       : IO_BANK0_GPIO0_STATUS_OUTFROMPERI
79 // Description : output signal from selected peripheral, before register
80 //               override is applied
81 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET  _u(0x0)
82 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
83 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB    _u(8)
84 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB    _u(8)
85 #define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO"
86 // =============================================================================
87 // Register    : IO_BANK0_GPIO0_CTRL
88 // Description : GPIO control including function select and overrides.
89 #define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004)
90 #define IO_BANK0_GPIO0_CTRL_BITS   _u(0x3003331f)
91 #define IO_BANK0_GPIO0_CTRL_RESET  _u(0x0000001f)
92 // -----------------------------------------------------------------------------
93 // Field       : IO_BANK0_GPIO0_CTRL_IRQOVER
94 // Description : 0x0 -> don't invert the interrupt
95 //               0x1 -> invert the interrupt
96 //               0x2 -> drive interrupt low
97 //               0x3 -> drive interrupt high
98 #define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET        _u(0x0)
99 #define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS         _u(0x30000000)
100 #define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB          _u(29)
101 #define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB          _u(28)
102 #define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS       "RW"
103 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
104 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
105 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
106 #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
107 // -----------------------------------------------------------------------------
108 // Field       : IO_BANK0_GPIO0_CTRL_INOVER
109 // Description : 0x0 -> don't invert the peri input
110 //               0x1 -> invert the peri input
111 //               0x2 -> drive peri input low
112 //               0x3 -> drive peri input high
113 #define IO_BANK0_GPIO0_CTRL_INOVER_RESET        _u(0x0)
114 #define IO_BANK0_GPIO0_CTRL_INOVER_BITS         _u(0x00030000)
115 #define IO_BANK0_GPIO0_CTRL_INOVER_MSB          _u(17)
116 #define IO_BANK0_GPIO0_CTRL_INOVER_LSB          _u(16)
117 #define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS       "RW"
118 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
119 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1)
120 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW    _u(0x2)
121 #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH   _u(0x3)
122 // -----------------------------------------------------------------------------
123 // Field       : IO_BANK0_GPIO0_CTRL_OEOVER
124 // Description : 0x0 -> drive output enable from peripheral signal selected by
125 //               funcsel
126 //               0x1 -> drive output enable from inverse of peripheral signal
127 //               selected by funcsel
128 //               0x2 -> disable output
129 //               0x3 -> enable output
130 #define IO_BANK0_GPIO0_CTRL_OEOVER_RESET         _u(0x0)
131 #define IO_BANK0_GPIO0_CTRL_OEOVER_BITS          _u(0x00003000)
132 #define IO_BANK0_GPIO0_CTRL_OEOVER_MSB           _u(13)
133 #define IO_BANK0_GPIO0_CTRL_OEOVER_LSB           _u(12)
134 #define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS        "RW"
135 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
136 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
137 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
138 #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
139 // -----------------------------------------------------------------------------
140 // Field       : IO_BANK0_GPIO0_CTRL_OUTOVER
141 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
142 //               0x1 -> drive output from inverse of peripheral signal selected
143 //               by funcsel
144 //               0x2 -> drive output low
145 //               0x3 -> drive output high
146 #define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET        _u(0x0)
147 #define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS         _u(0x00000300)
148 #define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB          _u(9)
149 #define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB          _u(8)
150 #define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS       "RW"
151 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
152 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
153 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
154 #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
155 // -----------------------------------------------------------------------------
156 // Field       : IO_BANK0_GPIO0_CTRL_FUNCSEL
157 // Description : 0-31 -> selects pin function according to the gpio table
158 //               31 == NULL
159 //               0x00 -> jtag_tck
160 //               0x01 -> spi0_rx
161 //               0x02 -> uart0_tx
162 //               0x03 -> i2c0_sda
163 //               0x04 -> pwm_a_0
164 //               0x05 -> sio_0
165 //               0x06 -> pio0_0
166 //               0x07 -> pio1_0
167 //               0x09 -> usb_muxing_overcurr_detect
168 //               0x1f -> null
169 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET                            _u(0x1f)
170 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
171 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB                              _u(4)
172 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB                              _u(0)
173 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS                           "RW"
174 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK                   _u(0x00)
175 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX                    _u(0x01)
176 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX                   _u(0x02)
177 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA                   _u(0x03)
178 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0                    _u(0x04)
179 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0                      _u(0x05)
180 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0                     _u(0x06)
181 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0                     _u(0x07)
182 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
183 #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
184 // =============================================================================
185 // Register    : IO_BANK0_GPIO1_STATUS
186 // Description : GPIO status
187 #define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008)
188 #define IO_BANK0_GPIO1_STATUS_BITS   _u(0x050a3300)
189 #define IO_BANK0_GPIO1_STATUS_RESET  _u(0x00000000)
190 // -----------------------------------------------------------------------------
191 // Field       : IO_BANK0_GPIO1_STATUS_IRQTOPROC
192 // Description : interrupt to processors, after override is applied
193 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET  _u(0x0)
194 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS   _u(0x04000000)
195 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB    _u(26)
196 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB    _u(26)
197 #define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO"
198 // -----------------------------------------------------------------------------
199 // Field       : IO_BANK0_GPIO1_STATUS_IRQFROMPAD
200 // Description : interrupt from pad before override is applied
201 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET  _u(0x0)
202 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
203 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB    _u(24)
204 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB    _u(24)
205 #define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO"
206 // -----------------------------------------------------------------------------
207 // Field       : IO_BANK0_GPIO1_STATUS_INTOPERI
208 // Description : input signal to peripheral, after override is applied
209 #define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET  _u(0x0)
210 #define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS   _u(0x00080000)
211 #define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB    _u(19)
212 #define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB    _u(19)
213 #define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO"
214 // -----------------------------------------------------------------------------
215 // Field       : IO_BANK0_GPIO1_STATUS_INFROMPAD
216 // Description : input signal from pad, before override is applied
217 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET  _u(0x0)
218 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS   _u(0x00020000)
219 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB    _u(17)
220 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB    _u(17)
221 #define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO"
222 // -----------------------------------------------------------------------------
223 // Field       : IO_BANK0_GPIO1_STATUS_OETOPAD
224 // Description : output enable to pad after register override is applied
225 #define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET  _u(0x0)
226 #define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS   _u(0x00002000)
227 #define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB    _u(13)
228 #define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB    _u(13)
229 #define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO"
230 // -----------------------------------------------------------------------------
231 // Field       : IO_BANK0_GPIO1_STATUS_OEFROMPERI
232 // Description : output enable from selected peripheral, before register
233 //               override is applied
234 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET  _u(0x0)
235 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS   _u(0x00001000)
236 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB    _u(12)
237 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB    _u(12)
238 #define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO"
239 // -----------------------------------------------------------------------------
240 // Field       : IO_BANK0_GPIO1_STATUS_OUTTOPAD
241 // Description : output signal to pad after register override is applied
242 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET  _u(0x0)
243 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS   _u(0x00000200)
244 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB    _u(9)
245 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB    _u(9)
246 #define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO"
247 // -----------------------------------------------------------------------------
248 // Field       : IO_BANK0_GPIO1_STATUS_OUTFROMPERI
249 // Description : output signal from selected peripheral, before register
250 //               override is applied
251 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET  _u(0x0)
252 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
253 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB    _u(8)
254 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB    _u(8)
255 #define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO"
256 // =============================================================================
257 // Register    : IO_BANK0_GPIO1_CTRL
258 // Description : GPIO control including function select and overrides.
259 #define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c)
260 #define IO_BANK0_GPIO1_CTRL_BITS   _u(0x3003331f)
261 #define IO_BANK0_GPIO1_CTRL_RESET  _u(0x0000001f)
262 // -----------------------------------------------------------------------------
263 // Field       : IO_BANK0_GPIO1_CTRL_IRQOVER
264 // Description : 0x0 -> don't invert the interrupt
265 //               0x1 -> invert the interrupt
266 //               0x2 -> drive interrupt low
267 //               0x3 -> drive interrupt high
268 #define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET        _u(0x0)
269 #define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS         _u(0x30000000)
270 #define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB          _u(29)
271 #define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB          _u(28)
272 #define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS       "RW"
273 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
274 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
275 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
276 #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
277 // -----------------------------------------------------------------------------
278 // Field       : IO_BANK0_GPIO1_CTRL_INOVER
279 // Description : 0x0 -> don't invert the peri input
280 //               0x1 -> invert the peri input
281 //               0x2 -> drive peri input low
282 //               0x3 -> drive peri input high
283 #define IO_BANK0_GPIO1_CTRL_INOVER_RESET        _u(0x0)
284 #define IO_BANK0_GPIO1_CTRL_INOVER_BITS         _u(0x00030000)
285 #define IO_BANK0_GPIO1_CTRL_INOVER_MSB          _u(17)
286 #define IO_BANK0_GPIO1_CTRL_INOVER_LSB          _u(16)
287 #define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS       "RW"
288 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
289 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1)
290 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW    _u(0x2)
291 #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH   _u(0x3)
292 // -----------------------------------------------------------------------------
293 // Field       : IO_BANK0_GPIO1_CTRL_OEOVER
294 // Description : 0x0 -> drive output enable from peripheral signal selected by
295 //               funcsel
296 //               0x1 -> drive output enable from inverse of peripheral signal
297 //               selected by funcsel
298 //               0x2 -> disable output
299 //               0x3 -> enable output
300 #define IO_BANK0_GPIO1_CTRL_OEOVER_RESET         _u(0x0)
301 #define IO_BANK0_GPIO1_CTRL_OEOVER_BITS          _u(0x00003000)
302 #define IO_BANK0_GPIO1_CTRL_OEOVER_MSB           _u(13)
303 #define IO_BANK0_GPIO1_CTRL_OEOVER_LSB           _u(12)
304 #define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS        "RW"
305 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
306 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
307 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
308 #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
309 // -----------------------------------------------------------------------------
310 // Field       : IO_BANK0_GPIO1_CTRL_OUTOVER
311 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
312 //               0x1 -> drive output from inverse of peripheral signal selected
313 //               by funcsel
314 //               0x2 -> drive output low
315 //               0x3 -> drive output high
316 #define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET        _u(0x0)
317 #define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS         _u(0x00000300)
318 #define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB          _u(9)
319 #define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB          _u(8)
320 #define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS       "RW"
321 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
322 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
323 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
324 #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
325 // -----------------------------------------------------------------------------
326 // Field       : IO_BANK0_GPIO1_CTRL_FUNCSEL
327 // Description : 0-31 -> selects pin function according to the gpio table
328 //               31 == NULL
329 //               0x00 -> jtag_tms
330 //               0x01 -> spi0_ss_n
331 //               0x02 -> uart0_rx
332 //               0x03 -> i2c0_scl
333 //               0x04 -> pwm_b_0
334 //               0x05 -> sio_1
335 //               0x06 -> pio0_1
336 //               0x07 -> pio1_1
337 //               0x09 -> usb_muxing_vbus_detect
338 //               0x1f -> null
339 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET                        _u(0x1f)
340 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
341 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB                          _u(4)
342 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB                          _u(0)
343 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS                       "RW"
344 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS               _u(0x00)
345 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N              _u(0x01)
346 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX               _u(0x02)
347 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL               _u(0x03)
348 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0                _u(0x04)
349 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1                  _u(0x05)
350 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1                 _u(0x06)
351 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1                 _u(0x07)
352 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
353 #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
354 // =============================================================================
355 // Register    : IO_BANK0_GPIO2_STATUS
356 // Description : GPIO status
357 #define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010)
358 #define IO_BANK0_GPIO2_STATUS_BITS   _u(0x050a3300)
359 #define IO_BANK0_GPIO2_STATUS_RESET  _u(0x00000000)
360 // -----------------------------------------------------------------------------
361 // Field       : IO_BANK0_GPIO2_STATUS_IRQTOPROC
362 // Description : interrupt to processors, after override is applied
363 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET  _u(0x0)
364 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS   _u(0x04000000)
365 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB    _u(26)
366 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB    _u(26)
367 #define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO"
368 // -----------------------------------------------------------------------------
369 // Field       : IO_BANK0_GPIO2_STATUS_IRQFROMPAD
370 // Description : interrupt from pad before override is applied
371 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET  _u(0x0)
372 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
373 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB    _u(24)
374 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB    _u(24)
375 #define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO"
376 // -----------------------------------------------------------------------------
377 // Field       : IO_BANK0_GPIO2_STATUS_INTOPERI
378 // Description : input signal to peripheral, after override is applied
379 #define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET  _u(0x0)
380 #define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS   _u(0x00080000)
381 #define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB    _u(19)
382 #define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB    _u(19)
383 #define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO"
384 // -----------------------------------------------------------------------------
385 // Field       : IO_BANK0_GPIO2_STATUS_INFROMPAD
386 // Description : input signal from pad, before override is applied
387 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET  _u(0x0)
388 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS   _u(0x00020000)
389 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB    _u(17)
390 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB    _u(17)
391 #define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO"
392 // -----------------------------------------------------------------------------
393 // Field       : IO_BANK0_GPIO2_STATUS_OETOPAD
394 // Description : output enable to pad after register override is applied
395 #define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET  _u(0x0)
396 #define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS   _u(0x00002000)
397 #define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB    _u(13)
398 #define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB    _u(13)
399 #define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO"
400 // -----------------------------------------------------------------------------
401 // Field       : IO_BANK0_GPIO2_STATUS_OEFROMPERI
402 // Description : output enable from selected peripheral, before register
403 //               override is applied
404 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET  _u(0x0)
405 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS   _u(0x00001000)
406 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB    _u(12)
407 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB    _u(12)
408 #define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO"
409 // -----------------------------------------------------------------------------
410 // Field       : IO_BANK0_GPIO2_STATUS_OUTTOPAD
411 // Description : output signal to pad after register override is applied
412 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET  _u(0x0)
413 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS   _u(0x00000200)
414 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB    _u(9)
415 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB    _u(9)
416 #define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO"
417 // -----------------------------------------------------------------------------
418 // Field       : IO_BANK0_GPIO2_STATUS_OUTFROMPERI
419 // Description : output signal from selected peripheral, before register
420 //               override is applied
421 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET  _u(0x0)
422 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
423 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB    _u(8)
424 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB    _u(8)
425 #define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO"
426 // =============================================================================
427 // Register    : IO_BANK0_GPIO2_CTRL
428 // Description : GPIO control including function select and overrides.
429 #define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014)
430 #define IO_BANK0_GPIO2_CTRL_BITS   _u(0x3003331f)
431 #define IO_BANK0_GPIO2_CTRL_RESET  _u(0x0000001f)
432 // -----------------------------------------------------------------------------
433 // Field       : IO_BANK0_GPIO2_CTRL_IRQOVER
434 // Description : 0x0 -> don't invert the interrupt
435 //               0x1 -> invert the interrupt
436 //               0x2 -> drive interrupt low
437 //               0x3 -> drive interrupt high
438 #define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET        _u(0x0)
439 #define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS         _u(0x30000000)
440 #define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB          _u(29)
441 #define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB          _u(28)
442 #define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS       "RW"
443 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
444 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
445 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
446 #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
447 // -----------------------------------------------------------------------------
448 // Field       : IO_BANK0_GPIO2_CTRL_INOVER
449 // Description : 0x0 -> don't invert the peri input
450 //               0x1 -> invert the peri input
451 //               0x2 -> drive peri input low
452 //               0x3 -> drive peri input high
453 #define IO_BANK0_GPIO2_CTRL_INOVER_RESET        _u(0x0)
454 #define IO_BANK0_GPIO2_CTRL_INOVER_BITS         _u(0x00030000)
455 #define IO_BANK0_GPIO2_CTRL_INOVER_MSB          _u(17)
456 #define IO_BANK0_GPIO2_CTRL_INOVER_LSB          _u(16)
457 #define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS       "RW"
458 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
459 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1)
460 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW    _u(0x2)
461 #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH   _u(0x3)
462 // -----------------------------------------------------------------------------
463 // Field       : IO_BANK0_GPIO2_CTRL_OEOVER
464 // Description : 0x0 -> drive output enable from peripheral signal selected by
465 //               funcsel
466 //               0x1 -> drive output enable from inverse of peripheral signal
467 //               selected by funcsel
468 //               0x2 -> disable output
469 //               0x3 -> enable output
470 #define IO_BANK0_GPIO2_CTRL_OEOVER_RESET         _u(0x0)
471 #define IO_BANK0_GPIO2_CTRL_OEOVER_BITS          _u(0x00003000)
472 #define IO_BANK0_GPIO2_CTRL_OEOVER_MSB           _u(13)
473 #define IO_BANK0_GPIO2_CTRL_OEOVER_LSB           _u(12)
474 #define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS        "RW"
475 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
476 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
477 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
478 #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
479 // -----------------------------------------------------------------------------
480 // Field       : IO_BANK0_GPIO2_CTRL_OUTOVER
481 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
482 //               0x1 -> drive output from inverse of peripheral signal selected
483 //               by funcsel
484 //               0x2 -> drive output low
485 //               0x3 -> drive output high
486 #define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET        _u(0x0)
487 #define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS         _u(0x00000300)
488 #define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB          _u(9)
489 #define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB          _u(8)
490 #define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS       "RW"
491 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
492 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
493 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
494 #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
495 // -----------------------------------------------------------------------------
496 // Field       : IO_BANK0_GPIO2_CTRL_FUNCSEL
497 // Description : 0-31 -> selects pin function according to the gpio table
498 //               31 == NULL
499 //               0x00 -> jtag_tdi
500 //               0x01 -> spi0_sclk
501 //               0x02 -> uart0_cts
502 //               0x03 -> i2c1_sda
503 //               0x04 -> pwm_a_1
504 //               0x05 -> sio_2
505 //               0x06 -> pio0_2
506 //               0x07 -> pio1_2
507 //               0x09 -> usb_muxing_vbus_en
508 //               0x1f -> null
509 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET                    _u(0x1f)
510 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
511 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB                      _u(4)
512 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB                      _u(0)
513 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS                   "RW"
514 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI           _u(0x00)
515 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK          _u(0x01)
516 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS          _u(0x02)
517 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA           _u(0x03)
518 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1            _u(0x04)
519 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2              _u(0x05)
520 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2             _u(0x06)
521 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2             _u(0x07)
522 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
523 #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
524 // =============================================================================
525 // Register    : IO_BANK0_GPIO3_STATUS
526 // Description : GPIO status
527 #define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018)
528 #define IO_BANK0_GPIO3_STATUS_BITS   _u(0x050a3300)
529 #define IO_BANK0_GPIO3_STATUS_RESET  _u(0x00000000)
530 // -----------------------------------------------------------------------------
531 // Field       : IO_BANK0_GPIO3_STATUS_IRQTOPROC
532 // Description : interrupt to processors, after override is applied
533 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET  _u(0x0)
534 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS   _u(0x04000000)
535 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB    _u(26)
536 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB    _u(26)
537 #define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO"
538 // -----------------------------------------------------------------------------
539 // Field       : IO_BANK0_GPIO3_STATUS_IRQFROMPAD
540 // Description : interrupt from pad before override is applied
541 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET  _u(0x0)
542 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
543 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB    _u(24)
544 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB    _u(24)
545 #define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO"
546 // -----------------------------------------------------------------------------
547 // Field       : IO_BANK0_GPIO3_STATUS_INTOPERI
548 // Description : input signal to peripheral, after override is applied
549 #define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET  _u(0x0)
550 #define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS   _u(0x00080000)
551 #define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB    _u(19)
552 #define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB    _u(19)
553 #define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO"
554 // -----------------------------------------------------------------------------
555 // Field       : IO_BANK0_GPIO3_STATUS_INFROMPAD
556 // Description : input signal from pad, before override is applied
557 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET  _u(0x0)
558 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS   _u(0x00020000)
559 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB    _u(17)
560 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB    _u(17)
561 #define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO"
562 // -----------------------------------------------------------------------------
563 // Field       : IO_BANK0_GPIO3_STATUS_OETOPAD
564 // Description : output enable to pad after register override is applied
565 #define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET  _u(0x0)
566 #define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS   _u(0x00002000)
567 #define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB    _u(13)
568 #define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB    _u(13)
569 #define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO"
570 // -----------------------------------------------------------------------------
571 // Field       : IO_BANK0_GPIO3_STATUS_OEFROMPERI
572 // Description : output enable from selected peripheral, before register
573 //               override is applied
574 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET  _u(0x0)
575 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS   _u(0x00001000)
576 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB    _u(12)
577 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB    _u(12)
578 #define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO"
579 // -----------------------------------------------------------------------------
580 // Field       : IO_BANK0_GPIO3_STATUS_OUTTOPAD
581 // Description : output signal to pad after register override is applied
582 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET  _u(0x0)
583 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS   _u(0x00000200)
584 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB    _u(9)
585 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB    _u(9)
586 #define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO"
587 // -----------------------------------------------------------------------------
588 // Field       : IO_BANK0_GPIO3_STATUS_OUTFROMPERI
589 // Description : output signal from selected peripheral, before register
590 //               override is applied
591 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET  _u(0x0)
592 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
593 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB    _u(8)
594 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB    _u(8)
595 #define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO"
596 // =============================================================================
597 // Register    : IO_BANK0_GPIO3_CTRL
598 // Description : GPIO control including function select and overrides.
599 #define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c)
600 #define IO_BANK0_GPIO3_CTRL_BITS   _u(0x3003331f)
601 #define IO_BANK0_GPIO3_CTRL_RESET  _u(0x0000001f)
602 // -----------------------------------------------------------------------------
603 // Field       : IO_BANK0_GPIO3_CTRL_IRQOVER
604 // Description : 0x0 -> don't invert the interrupt
605 //               0x1 -> invert the interrupt
606 //               0x2 -> drive interrupt low
607 //               0x3 -> drive interrupt high
608 #define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET        _u(0x0)
609 #define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS         _u(0x30000000)
610 #define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB          _u(29)
611 #define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB          _u(28)
612 #define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS       "RW"
613 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
614 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
615 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
616 #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
617 // -----------------------------------------------------------------------------
618 // Field       : IO_BANK0_GPIO3_CTRL_INOVER
619 // Description : 0x0 -> don't invert the peri input
620 //               0x1 -> invert the peri input
621 //               0x2 -> drive peri input low
622 //               0x3 -> drive peri input high
623 #define IO_BANK0_GPIO3_CTRL_INOVER_RESET        _u(0x0)
624 #define IO_BANK0_GPIO3_CTRL_INOVER_BITS         _u(0x00030000)
625 #define IO_BANK0_GPIO3_CTRL_INOVER_MSB          _u(17)
626 #define IO_BANK0_GPIO3_CTRL_INOVER_LSB          _u(16)
627 #define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS       "RW"
628 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
629 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1)
630 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW    _u(0x2)
631 #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH   _u(0x3)
632 // -----------------------------------------------------------------------------
633 // Field       : IO_BANK0_GPIO3_CTRL_OEOVER
634 // Description : 0x0 -> drive output enable from peripheral signal selected by
635 //               funcsel
636 //               0x1 -> drive output enable from inverse of peripheral signal
637 //               selected by funcsel
638 //               0x2 -> disable output
639 //               0x3 -> enable output
640 #define IO_BANK0_GPIO3_CTRL_OEOVER_RESET         _u(0x0)
641 #define IO_BANK0_GPIO3_CTRL_OEOVER_BITS          _u(0x00003000)
642 #define IO_BANK0_GPIO3_CTRL_OEOVER_MSB           _u(13)
643 #define IO_BANK0_GPIO3_CTRL_OEOVER_LSB           _u(12)
644 #define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS        "RW"
645 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
646 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
647 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
648 #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
649 // -----------------------------------------------------------------------------
650 // Field       : IO_BANK0_GPIO3_CTRL_OUTOVER
651 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
652 //               0x1 -> drive output from inverse of peripheral signal selected
653 //               by funcsel
654 //               0x2 -> drive output low
655 //               0x3 -> drive output high
656 #define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET        _u(0x0)
657 #define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS         _u(0x00000300)
658 #define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB          _u(9)
659 #define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB          _u(8)
660 #define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS       "RW"
661 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
662 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
663 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
664 #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
665 // -----------------------------------------------------------------------------
666 // Field       : IO_BANK0_GPIO3_CTRL_FUNCSEL
667 // Description : 0-31 -> selects pin function according to the gpio table
668 //               31 == NULL
669 //               0x00 -> jtag_tdo
670 //               0x01 -> spi0_tx
671 //               0x02 -> uart0_rts
672 //               0x03 -> i2c1_scl
673 //               0x04 -> pwm_b_1
674 //               0x05 -> sio_3
675 //               0x06 -> pio0_3
676 //               0x07 -> pio1_3
677 //               0x09 -> usb_muxing_overcurr_detect
678 //               0x1f -> null
679 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET                            _u(0x1f)
680 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
681 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB                              _u(4)
682 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB                              _u(0)
683 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS                           "RW"
684 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO                   _u(0x00)
685 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX                    _u(0x01)
686 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS                  _u(0x02)
687 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL                   _u(0x03)
688 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1                    _u(0x04)
689 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3                      _u(0x05)
690 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3                     _u(0x06)
691 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3                     _u(0x07)
692 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
693 #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
694 // =============================================================================
695 // Register    : IO_BANK0_GPIO4_STATUS
696 // Description : GPIO status
697 #define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020)
698 #define IO_BANK0_GPIO4_STATUS_BITS   _u(0x050a3300)
699 #define IO_BANK0_GPIO4_STATUS_RESET  _u(0x00000000)
700 // -----------------------------------------------------------------------------
701 // Field       : IO_BANK0_GPIO4_STATUS_IRQTOPROC
702 // Description : interrupt to processors, after override is applied
703 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET  _u(0x0)
704 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS   _u(0x04000000)
705 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB    _u(26)
706 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB    _u(26)
707 #define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO"
708 // -----------------------------------------------------------------------------
709 // Field       : IO_BANK0_GPIO4_STATUS_IRQFROMPAD
710 // Description : interrupt from pad before override is applied
711 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET  _u(0x0)
712 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
713 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB    _u(24)
714 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB    _u(24)
715 #define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO"
716 // -----------------------------------------------------------------------------
717 // Field       : IO_BANK0_GPIO4_STATUS_INTOPERI
718 // Description : input signal to peripheral, after override is applied
719 #define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET  _u(0x0)
720 #define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS   _u(0x00080000)
721 #define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB    _u(19)
722 #define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB    _u(19)
723 #define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO"
724 // -----------------------------------------------------------------------------
725 // Field       : IO_BANK0_GPIO4_STATUS_INFROMPAD
726 // Description : input signal from pad, before override is applied
727 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET  _u(0x0)
728 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS   _u(0x00020000)
729 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB    _u(17)
730 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB    _u(17)
731 #define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO"
732 // -----------------------------------------------------------------------------
733 // Field       : IO_BANK0_GPIO4_STATUS_OETOPAD
734 // Description : output enable to pad after register override is applied
735 #define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET  _u(0x0)
736 #define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS   _u(0x00002000)
737 #define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB    _u(13)
738 #define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB    _u(13)
739 #define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO"
740 // -----------------------------------------------------------------------------
741 // Field       : IO_BANK0_GPIO4_STATUS_OEFROMPERI
742 // Description : output enable from selected peripheral, before register
743 //               override is applied
744 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET  _u(0x0)
745 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS   _u(0x00001000)
746 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB    _u(12)
747 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB    _u(12)
748 #define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO"
749 // -----------------------------------------------------------------------------
750 // Field       : IO_BANK0_GPIO4_STATUS_OUTTOPAD
751 // Description : output signal to pad after register override is applied
752 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET  _u(0x0)
753 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS   _u(0x00000200)
754 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB    _u(9)
755 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB    _u(9)
756 #define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO"
757 // -----------------------------------------------------------------------------
758 // Field       : IO_BANK0_GPIO4_STATUS_OUTFROMPERI
759 // Description : output signal from selected peripheral, before register
760 //               override is applied
761 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET  _u(0x0)
762 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
763 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB    _u(8)
764 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB    _u(8)
765 #define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO"
766 // =============================================================================
767 // Register    : IO_BANK0_GPIO4_CTRL
768 // Description : GPIO control including function select and overrides.
769 #define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024)
770 #define IO_BANK0_GPIO4_CTRL_BITS   _u(0x3003331f)
771 #define IO_BANK0_GPIO4_CTRL_RESET  _u(0x0000001f)
772 // -----------------------------------------------------------------------------
773 // Field       : IO_BANK0_GPIO4_CTRL_IRQOVER
774 // Description : 0x0 -> don't invert the interrupt
775 //               0x1 -> invert the interrupt
776 //               0x2 -> drive interrupt low
777 //               0x3 -> drive interrupt high
778 #define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET        _u(0x0)
779 #define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS         _u(0x30000000)
780 #define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB          _u(29)
781 #define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB          _u(28)
782 #define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS       "RW"
783 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
784 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
785 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
786 #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
787 // -----------------------------------------------------------------------------
788 // Field       : IO_BANK0_GPIO4_CTRL_INOVER
789 // Description : 0x0 -> don't invert the peri input
790 //               0x1 -> invert the peri input
791 //               0x2 -> drive peri input low
792 //               0x3 -> drive peri input high
793 #define IO_BANK0_GPIO4_CTRL_INOVER_RESET        _u(0x0)
794 #define IO_BANK0_GPIO4_CTRL_INOVER_BITS         _u(0x00030000)
795 #define IO_BANK0_GPIO4_CTRL_INOVER_MSB          _u(17)
796 #define IO_BANK0_GPIO4_CTRL_INOVER_LSB          _u(16)
797 #define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS       "RW"
798 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0)
799 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1)
800 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW    _u(0x2)
801 #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH   _u(0x3)
802 // -----------------------------------------------------------------------------
803 // Field       : IO_BANK0_GPIO4_CTRL_OEOVER
804 // Description : 0x0 -> drive output enable from peripheral signal selected by
805 //               funcsel
806 //               0x1 -> drive output enable from inverse of peripheral signal
807 //               selected by funcsel
808 //               0x2 -> disable output
809 //               0x3 -> enable output
810 #define IO_BANK0_GPIO4_CTRL_OEOVER_RESET         _u(0x0)
811 #define IO_BANK0_GPIO4_CTRL_OEOVER_BITS          _u(0x00003000)
812 #define IO_BANK0_GPIO4_CTRL_OEOVER_MSB           _u(13)
813 #define IO_BANK0_GPIO4_CTRL_OEOVER_LSB           _u(12)
814 #define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS        "RW"
815 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
816 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
817 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
818 #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
819 // -----------------------------------------------------------------------------
820 // Field       : IO_BANK0_GPIO4_CTRL_OUTOVER
821 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
822 //               0x1 -> drive output from inverse of peripheral signal selected
823 //               by funcsel
824 //               0x2 -> drive output low
825 //               0x3 -> drive output high
826 #define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET        _u(0x0)
827 #define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS         _u(0x00000300)
828 #define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB          _u(9)
829 #define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB          _u(8)
830 #define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS       "RW"
831 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
832 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
833 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
834 #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
835 // -----------------------------------------------------------------------------
836 // Field       : IO_BANK0_GPIO4_CTRL_FUNCSEL
837 // Description : 0-31 -> selects pin function according to the gpio table
838 //               31 == NULL
839 //               0x01 -> spi0_rx
840 //               0x02 -> uart1_tx
841 //               0x03 -> i2c0_sda
842 //               0x04 -> pwm_a_2
843 //               0x05 -> sio_4
844 //               0x06 -> pio0_4
845 //               0x07 -> pio1_4
846 //               0x09 -> usb_muxing_vbus_detect
847 //               0x1f -> null
848 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET                        _u(0x1f)
849 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
850 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB                          _u(4)
851 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB                          _u(0)
852 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS                       "RW"
853 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX                _u(0x01)
854 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX               _u(0x02)
855 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA               _u(0x03)
856 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2                _u(0x04)
857 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4                  _u(0x05)
858 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4                 _u(0x06)
859 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4                 _u(0x07)
860 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
861 #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
862 // =============================================================================
863 // Register    : IO_BANK0_GPIO5_STATUS
864 // Description : GPIO status
865 #define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028)
866 #define IO_BANK0_GPIO5_STATUS_BITS   _u(0x050a3300)
867 #define IO_BANK0_GPIO5_STATUS_RESET  _u(0x00000000)
868 // -----------------------------------------------------------------------------
869 // Field       : IO_BANK0_GPIO5_STATUS_IRQTOPROC
870 // Description : interrupt to processors, after override is applied
871 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET  _u(0x0)
872 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS   _u(0x04000000)
873 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB    _u(26)
874 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB    _u(26)
875 #define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO"
876 // -----------------------------------------------------------------------------
877 // Field       : IO_BANK0_GPIO5_STATUS_IRQFROMPAD
878 // Description : interrupt from pad before override is applied
879 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET  _u(0x0)
880 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
881 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB    _u(24)
882 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB    _u(24)
883 #define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO"
884 // -----------------------------------------------------------------------------
885 // Field       : IO_BANK0_GPIO5_STATUS_INTOPERI
886 // Description : input signal to peripheral, after override is applied
887 #define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET  _u(0x0)
888 #define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS   _u(0x00080000)
889 #define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB    _u(19)
890 #define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB    _u(19)
891 #define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO"
892 // -----------------------------------------------------------------------------
893 // Field       : IO_BANK0_GPIO5_STATUS_INFROMPAD
894 // Description : input signal from pad, before override is applied
895 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET  _u(0x0)
896 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS   _u(0x00020000)
897 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB    _u(17)
898 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB    _u(17)
899 #define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO"
900 // -----------------------------------------------------------------------------
901 // Field       : IO_BANK0_GPIO5_STATUS_OETOPAD
902 // Description : output enable to pad after register override is applied
903 #define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET  _u(0x0)
904 #define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS   _u(0x00002000)
905 #define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB    _u(13)
906 #define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB    _u(13)
907 #define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO"
908 // -----------------------------------------------------------------------------
909 // Field       : IO_BANK0_GPIO5_STATUS_OEFROMPERI
910 // Description : output enable from selected peripheral, before register
911 //               override is applied
912 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET  _u(0x0)
913 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS   _u(0x00001000)
914 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB    _u(12)
915 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB    _u(12)
916 #define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO"
917 // -----------------------------------------------------------------------------
918 // Field       : IO_BANK0_GPIO5_STATUS_OUTTOPAD
919 // Description : output signal to pad after register override is applied
920 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET  _u(0x0)
921 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS   _u(0x00000200)
922 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB    _u(9)
923 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB    _u(9)
924 #define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO"
925 // -----------------------------------------------------------------------------
926 // Field       : IO_BANK0_GPIO5_STATUS_OUTFROMPERI
927 // Description : output signal from selected peripheral, before register
928 //               override is applied
929 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET  _u(0x0)
930 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
931 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB    _u(8)
932 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB    _u(8)
933 #define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO"
934 // =============================================================================
935 // Register    : IO_BANK0_GPIO5_CTRL
936 // Description : GPIO control including function select and overrides.
937 #define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c)
938 #define IO_BANK0_GPIO5_CTRL_BITS   _u(0x3003331f)
939 #define IO_BANK0_GPIO5_CTRL_RESET  _u(0x0000001f)
940 // -----------------------------------------------------------------------------
941 // Field       : IO_BANK0_GPIO5_CTRL_IRQOVER
942 // Description : 0x0 -> don't invert the interrupt
943 //               0x1 -> invert the interrupt
944 //               0x2 -> drive interrupt low
945 //               0x3 -> drive interrupt high
946 #define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET        _u(0x0)
947 #define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS         _u(0x30000000)
948 #define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB          _u(29)
949 #define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB          _u(28)
950 #define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS       "RW"
951 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
952 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
953 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
954 #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
955 // -----------------------------------------------------------------------------
956 // Field       : IO_BANK0_GPIO5_CTRL_INOVER
957 // Description : 0x0 -> don't invert the peri input
958 //               0x1 -> invert the peri input
959 //               0x2 -> drive peri input low
960 //               0x3 -> drive peri input high
961 #define IO_BANK0_GPIO5_CTRL_INOVER_RESET        _u(0x0)
962 #define IO_BANK0_GPIO5_CTRL_INOVER_BITS         _u(0x00030000)
963 #define IO_BANK0_GPIO5_CTRL_INOVER_MSB          _u(17)
964 #define IO_BANK0_GPIO5_CTRL_INOVER_LSB          _u(16)
965 #define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS       "RW"
966 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0)
967 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1)
968 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW    _u(0x2)
969 #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH   _u(0x3)
970 // -----------------------------------------------------------------------------
971 // Field       : IO_BANK0_GPIO5_CTRL_OEOVER
972 // Description : 0x0 -> drive output enable from peripheral signal selected by
973 //               funcsel
974 //               0x1 -> drive output enable from inverse of peripheral signal
975 //               selected by funcsel
976 //               0x2 -> disable output
977 //               0x3 -> enable output
978 #define IO_BANK0_GPIO5_CTRL_OEOVER_RESET         _u(0x0)
979 #define IO_BANK0_GPIO5_CTRL_OEOVER_BITS          _u(0x00003000)
980 #define IO_BANK0_GPIO5_CTRL_OEOVER_MSB           _u(13)
981 #define IO_BANK0_GPIO5_CTRL_OEOVER_LSB           _u(12)
982 #define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS        "RW"
983 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
984 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
985 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
986 #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
987 // -----------------------------------------------------------------------------
988 // Field       : IO_BANK0_GPIO5_CTRL_OUTOVER
989 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
990 //               0x1 -> drive output from inverse of peripheral signal selected
991 //               by funcsel
992 //               0x2 -> drive output low
993 //               0x3 -> drive output high
994 #define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET        _u(0x0)
995 #define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS         _u(0x00000300)
996 #define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB          _u(9)
997 #define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB          _u(8)
998 #define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS       "RW"
999 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
1000 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
1001 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
1002 #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
1003 // -----------------------------------------------------------------------------
1004 // Field       : IO_BANK0_GPIO5_CTRL_FUNCSEL
1005 // Description : 0-31 -> selects pin function according to the gpio table
1006 //               31 == NULL
1007 //               0x01 -> spi0_ss_n
1008 //               0x02 -> uart1_rx
1009 //               0x03 -> i2c0_scl
1010 //               0x04 -> pwm_b_2
1011 //               0x05 -> sio_5
1012 //               0x06 -> pio0_5
1013 //               0x07 -> pio1_5
1014 //               0x09 -> usb_muxing_vbus_en
1015 //               0x1f -> null
1016 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET                    _u(0x1f)
1017 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
1018 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB                      _u(4)
1019 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB                      _u(0)
1020 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS                   "RW"
1021 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N          _u(0x01)
1022 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX           _u(0x02)
1023 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL           _u(0x03)
1024 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2            _u(0x04)
1025 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5              _u(0x05)
1026 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5             _u(0x06)
1027 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5             _u(0x07)
1028 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
1029 #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
1030 // =============================================================================
1031 // Register    : IO_BANK0_GPIO6_STATUS
1032 // Description : GPIO status
1033 #define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030)
1034 #define IO_BANK0_GPIO6_STATUS_BITS   _u(0x050a3300)
1035 #define IO_BANK0_GPIO6_STATUS_RESET  _u(0x00000000)
1036 // -----------------------------------------------------------------------------
1037 // Field       : IO_BANK0_GPIO6_STATUS_IRQTOPROC
1038 // Description : interrupt to processors, after override is applied
1039 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET  _u(0x0)
1040 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS   _u(0x04000000)
1041 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB    _u(26)
1042 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB    _u(26)
1043 #define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO"
1044 // -----------------------------------------------------------------------------
1045 // Field       : IO_BANK0_GPIO6_STATUS_IRQFROMPAD
1046 // Description : interrupt from pad before override is applied
1047 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET  _u(0x0)
1048 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
1049 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB    _u(24)
1050 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB    _u(24)
1051 #define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO"
1052 // -----------------------------------------------------------------------------
1053 // Field       : IO_BANK0_GPIO6_STATUS_INTOPERI
1054 // Description : input signal to peripheral, after override is applied
1055 #define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET  _u(0x0)
1056 #define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS   _u(0x00080000)
1057 #define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB    _u(19)
1058 #define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB    _u(19)
1059 #define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO"
1060 // -----------------------------------------------------------------------------
1061 // Field       : IO_BANK0_GPIO6_STATUS_INFROMPAD
1062 // Description : input signal from pad, before override is applied
1063 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET  _u(0x0)
1064 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS   _u(0x00020000)
1065 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB    _u(17)
1066 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB    _u(17)
1067 #define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO"
1068 // -----------------------------------------------------------------------------
1069 // Field       : IO_BANK0_GPIO6_STATUS_OETOPAD
1070 // Description : output enable to pad after register override is applied
1071 #define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET  _u(0x0)
1072 #define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS   _u(0x00002000)
1073 #define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB    _u(13)
1074 #define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB    _u(13)
1075 #define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO"
1076 // -----------------------------------------------------------------------------
1077 // Field       : IO_BANK0_GPIO6_STATUS_OEFROMPERI
1078 // Description : output enable from selected peripheral, before register
1079 //               override is applied
1080 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET  _u(0x0)
1081 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS   _u(0x00001000)
1082 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB    _u(12)
1083 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB    _u(12)
1084 #define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO"
1085 // -----------------------------------------------------------------------------
1086 // Field       : IO_BANK0_GPIO6_STATUS_OUTTOPAD
1087 // Description : output signal to pad after register override is applied
1088 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET  _u(0x0)
1089 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS   _u(0x00000200)
1090 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB    _u(9)
1091 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB    _u(9)
1092 #define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO"
1093 // -----------------------------------------------------------------------------
1094 // Field       : IO_BANK0_GPIO6_STATUS_OUTFROMPERI
1095 // Description : output signal from selected peripheral, before register
1096 //               override is applied
1097 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET  _u(0x0)
1098 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
1099 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB    _u(8)
1100 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB    _u(8)
1101 #define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO"
1102 // =============================================================================
1103 // Register    : IO_BANK0_GPIO6_CTRL
1104 // Description : GPIO control including function select and overrides.
1105 #define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034)
1106 #define IO_BANK0_GPIO6_CTRL_BITS   _u(0x3003331f)
1107 #define IO_BANK0_GPIO6_CTRL_RESET  _u(0x0000001f)
1108 // -----------------------------------------------------------------------------
1109 // Field       : IO_BANK0_GPIO6_CTRL_IRQOVER
1110 // Description : 0x0 -> don't invert the interrupt
1111 //               0x1 -> invert the interrupt
1112 //               0x2 -> drive interrupt low
1113 //               0x3 -> drive interrupt high
1114 #define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET        _u(0x0)
1115 #define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS         _u(0x30000000)
1116 #define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB          _u(29)
1117 #define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB          _u(28)
1118 #define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS       "RW"
1119 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
1120 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
1121 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
1122 #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
1123 // -----------------------------------------------------------------------------
1124 // Field       : IO_BANK0_GPIO6_CTRL_INOVER
1125 // Description : 0x0 -> don't invert the peri input
1126 //               0x1 -> invert the peri input
1127 //               0x2 -> drive peri input low
1128 //               0x3 -> drive peri input high
1129 #define IO_BANK0_GPIO6_CTRL_INOVER_RESET        _u(0x0)
1130 #define IO_BANK0_GPIO6_CTRL_INOVER_BITS         _u(0x00030000)
1131 #define IO_BANK0_GPIO6_CTRL_INOVER_MSB          _u(17)
1132 #define IO_BANK0_GPIO6_CTRL_INOVER_LSB          _u(16)
1133 #define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS       "RW"
1134 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0)
1135 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1)
1136 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW    _u(0x2)
1137 #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH   _u(0x3)
1138 // -----------------------------------------------------------------------------
1139 // Field       : IO_BANK0_GPIO6_CTRL_OEOVER
1140 // Description : 0x0 -> drive output enable from peripheral signal selected by
1141 //               funcsel
1142 //               0x1 -> drive output enable from inverse of peripheral signal
1143 //               selected by funcsel
1144 //               0x2 -> disable output
1145 //               0x3 -> enable output
1146 #define IO_BANK0_GPIO6_CTRL_OEOVER_RESET         _u(0x0)
1147 #define IO_BANK0_GPIO6_CTRL_OEOVER_BITS          _u(0x00003000)
1148 #define IO_BANK0_GPIO6_CTRL_OEOVER_MSB           _u(13)
1149 #define IO_BANK0_GPIO6_CTRL_OEOVER_LSB           _u(12)
1150 #define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS        "RW"
1151 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
1152 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
1153 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
1154 #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
1155 // -----------------------------------------------------------------------------
1156 // Field       : IO_BANK0_GPIO6_CTRL_OUTOVER
1157 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
1158 //               0x1 -> drive output from inverse of peripheral signal selected
1159 //               by funcsel
1160 //               0x2 -> drive output low
1161 //               0x3 -> drive output high
1162 #define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET        _u(0x0)
1163 #define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS         _u(0x00000300)
1164 #define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB          _u(9)
1165 #define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB          _u(8)
1166 #define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS       "RW"
1167 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
1168 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
1169 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
1170 #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
1171 // -----------------------------------------------------------------------------
1172 // Field       : IO_BANK0_GPIO6_CTRL_FUNCSEL
1173 // Description : 0-31 -> selects pin function according to the gpio table
1174 //               31 == NULL
1175 //               0x01 -> spi0_sclk
1176 //               0x02 -> uart1_cts
1177 //               0x03 -> i2c1_sda
1178 //               0x04 -> pwm_a_3
1179 //               0x05 -> sio_6
1180 //               0x06 -> pio0_6
1181 //               0x07 -> pio1_6
1182 //               0x08 -> usb_muxing_extphy_softcon
1183 //               0x09 -> usb_muxing_overcurr_detect
1184 //               0x1f -> null
1185 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET                            _u(0x1f)
1186 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
1187 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB                              _u(4)
1188 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB                              _u(0)
1189 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS                           "RW"
1190 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK                  _u(0x01)
1191 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS                  _u(0x02)
1192 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA                   _u(0x03)
1193 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3                    _u(0x04)
1194 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6                      _u(0x05)
1195 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6                     _u(0x06)
1196 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6                     _u(0x07)
1197 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON  _u(0x08)
1198 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
1199 #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
1200 // =============================================================================
1201 // Register    : IO_BANK0_GPIO7_STATUS
1202 // Description : GPIO status
1203 #define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038)
1204 #define IO_BANK0_GPIO7_STATUS_BITS   _u(0x050a3300)
1205 #define IO_BANK0_GPIO7_STATUS_RESET  _u(0x00000000)
1206 // -----------------------------------------------------------------------------
1207 // Field       : IO_BANK0_GPIO7_STATUS_IRQTOPROC
1208 // Description : interrupt to processors, after override is applied
1209 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET  _u(0x0)
1210 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS   _u(0x04000000)
1211 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB    _u(26)
1212 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB    _u(26)
1213 #define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO"
1214 // -----------------------------------------------------------------------------
1215 // Field       : IO_BANK0_GPIO7_STATUS_IRQFROMPAD
1216 // Description : interrupt from pad before override is applied
1217 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET  _u(0x0)
1218 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
1219 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB    _u(24)
1220 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB    _u(24)
1221 #define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO"
1222 // -----------------------------------------------------------------------------
1223 // Field       : IO_BANK0_GPIO7_STATUS_INTOPERI
1224 // Description : input signal to peripheral, after override is applied
1225 #define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET  _u(0x0)
1226 #define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS   _u(0x00080000)
1227 #define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB    _u(19)
1228 #define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB    _u(19)
1229 #define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO"
1230 // -----------------------------------------------------------------------------
1231 // Field       : IO_BANK0_GPIO7_STATUS_INFROMPAD
1232 // Description : input signal from pad, before override is applied
1233 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET  _u(0x0)
1234 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS   _u(0x00020000)
1235 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB    _u(17)
1236 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB    _u(17)
1237 #define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO"
1238 // -----------------------------------------------------------------------------
1239 // Field       : IO_BANK0_GPIO7_STATUS_OETOPAD
1240 // Description : output enable to pad after register override is applied
1241 #define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET  _u(0x0)
1242 #define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS   _u(0x00002000)
1243 #define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB    _u(13)
1244 #define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB    _u(13)
1245 #define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO"
1246 // -----------------------------------------------------------------------------
1247 // Field       : IO_BANK0_GPIO7_STATUS_OEFROMPERI
1248 // Description : output enable from selected peripheral, before register
1249 //               override is applied
1250 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET  _u(0x0)
1251 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS   _u(0x00001000)
1252 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB    _u(12)
1253 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB    _u(12)
1254 #define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO"
1255 // -----------------------------------------------------------------------------
1256 // Field       : IO_BANK0_GPIO7_STATUS_OUTTOPAD
1257 // Description : output signal to pad after register override is applied
1258 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET  _u(0x0)
1259 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS   _u(0x00000200)
1260 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB    _u(9)
1261 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB    _u(9)
1262 #define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO"
1263 // -----------------------------------------------------------------------------
1264 // Field       : IO_BANK0_GPIO7_STATUS_OUTFROMPERI
1265 // Description : output signal from selected peripheral, before register
1266 //               override is applied
1267 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET  _u(0x0)
1268 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
1269 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB    _u(8)
1270 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB    _u(8)
1271 #define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO"
1272 // =============================================================================
1273 // Register    : IO_BANK0_GPIO7_CTRL
1274 // Description : GPIO control including function select and overrides.
1275 #define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c)
1276 #define IO_BANK0_GPIO7_CTRL_BITS   _u(0x3003331f)
1277 #define IO_BANK0_GPIO7_CTRL_RESET  _u(0x0000001f)
1278 // -----------------------------------------------------------------------------
1279 // Field       : IO_BANK0_GPIO7_CTRL_IRQOVER
1280 // Description : 0x0 -> don't invert the interrupt
1281 //               0x1 -> invert the interrupt
1282 //               0x2 -> drive interrupt low
1283 //               0x3 -> drive interrupt high
1284 #define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET        _u(0x0)
1285 #define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS         _u(0x30000000)
1286 #define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB          _u(29)
1287 #define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB          _u(28)
1288 #define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS       "RW"
1289 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
1290 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
1291 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
1292 #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
1293 // -----------------------------------------------------------------------------
1294 // Field       : IO_BANK0_GPIO7_CTRL_INOVER
1295 // Description : 0x0 -> don't invert the peri input
1296 //               0x1 -> invert the peri input
1297 //               0x2 -> drive peri input low
1298 //               0x3 -> drive peri input high
1299 #define IO_BANK0_GPIO7_CTRL_INOVER_RESET        _u(0x0)
1300 #define IO_BANK0_GPIO7_CTRL_INOVER_BITS         _u(0x00030000)
1301 #define IO_BANK0_GPIO7_CTRL_INOVER_MSB          _u(17)
1302 #define IO_BANK0_GPIO7_CTRL_INOVER_LSB          _u(16)
1303 #define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS       "RW"
1304 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0)
1305 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1)
1306 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW    _u(0x2)
1307 #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH   _u(0x3)
1308 // -----------------------------------------------------------------------------
1309 // Field       : IO_BANK0_GPIO7_CTRL_OEOVER
1310 // Description : 0x0 -> drive output enable from peripheral signal selected by
1311 //               funcsel
1312 //               0x1 -> drive output enable from inverse of peripheral signal
1313 //               selected by funcsel
1314 //               0x2 -> disable output
1315 //               0x3 -> enable output
1316 #define IO_BANK0_GPIO7_CTRL_OEOVER_RESET         _u(0x0)
1317 #define IO_BANK0_GPIO7_CTRL_OEOVER_BITS          _u(0x00003000)
1318 #define IO_BANK0_GPIO7_CTRL_OEOVER_MSB           _u(13)
1319 #define IO_BANK0_GPIO7_CTRL_OEOVER_LSB           _u(12)
1320 #define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS        "RW"
1321 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
1322 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
1323 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
1324 #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
1325 // -----------------------------------------------------------------------------
1326 // Field       : IO_BANK0_GPIO7_CTRL_OUTOVER
1327 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
1328 //               0x1 -> drive output from inverse of peripheral signal selected
1329 //               by funcsel
1330 //               0x2 -> drive output low
1331 //               0x3 -> drive output high
1332 #define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET        _u(0x0)
1333 #define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS         _u(0x00000300)
1334 #define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB          _u(9)
1335 #define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB          _u(8)
1336 #define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS       "RW"
1337 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
1338 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
1339 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
1340 #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
1341 // -----------------------------------------------------------------------------
1342 // Field       : IO_BANK0_GPIO7_CTRL_FUNCSEL
1343 // Description : 0-31 -> selects pin function according to the gpio table
1344 //               31 == NULL
1345 //               0x01 -> spi0_tx
1346 //               0x02 -> uart1_rts
1347 //               0x03 -> i2c1_scl
1348 //               0x04 -> pwm_b_3
1349 //               0x05 -> sio_7
1350 //               0x06 -> pio0_7
1351 //               0x07 -> pio1_7
1352 //               0x08 -> usb_muxing_extphy_oe_n
1353 //               0x09 -> usb_muxing_vbus_detect
1354 //               0x1f -> null
1355 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET                        _u(0x1f)
1356 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
1357 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB                          _u(4)
1358 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB                          _u(0)
1359 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS                       "RW"
1360 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX                _u(0x01)
1361 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS              _u(0x02)
1362 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL               _u(0x03)
1363 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3                _u(0x04)
1364 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7                  _u(0x05)
1365 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7                 _u(0x06)
1366 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7                 _u(0x07)
1367 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08)
1368 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
1369 #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
1370 // =============================================================================
1371 // Register    : IO_BANK0_GPIO8_STATUS
1372 // Description : GPIO status
1373 #define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040)
1374 #define IO_BANK0_GPIO8_STATUS_BITS   _u(0x050a3300)
1375 #define IO_BANK0_GPIO8_STATUS_RESET  _u(0x00000000)
1376 // -----------------------------------------------------------------------------
1377 // Field       : IO_BANK0_GPIO8_STATUS_IRQTOPROC
1378 // Description : interrupt to processors, after override is applied
1379 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET  _u(0x0)
1380 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS   _u(0x04000000)
1381 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB    _u(26)
1382 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB    _u(26)
1383 #define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO"
1384 // -----------------------------------------------------------------------------
1385 // Field       : IO_BANK0_GPIO8_STATUS_IRQFROMPAD
1386 // Description : interrupt from pad before override is applied
1387 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET  _u(0x0)
1388 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
1389 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB    _u(24)
1390 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB    _u(24)
1391 #define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO"
1392 // -----------------------------------------------------------------------------
1393 // Field       : IO_BANK0_GPIO8_STATUS_INTOPERI
1394 // Description : input signal to peripheral, after override is applied
1395 #define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET  _u(0x0)
1396 #define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS   _u(0x00080000)
1397 #define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB    _u(19)
1398 #define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB    _u(19)
1399 #define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO"
1400 // -----------------------------------------------------------------------------
1401 // Field       : IO_BANK0_GPIO8_STATUS_INFROMPAD
1402 // Description : input signal from pad, before override is applied
1403 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET  _u(0x0)
1404 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS   _u(0x00020000)
1405 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB    _u(17)
1406 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB    _u(17)
1407 #define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO"
1408 // -----------------------------------------------------------------------------
1409 // Field       : IO_BANK0_GPIO8_STATUS_OETOPAD
1410 // Description : output enable to pad after register override is applied
1411 #define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET  _u(0x0)
1412 #define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS   _u(0x00002000)
1413 #define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB    _u(13)
1414 #define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB    _u(13)
1415 #define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO"
1416 // -----------------------------------------------------------------------------
1417 // Field       : IO_BANK0_GPIO8_STATUS_OEFROMPERI
1418 // Description : output enable from selected peripheral, before register
1419 //               override is applied
1420 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET  _u(0x0)
1421 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS   _u(0x00001000)
1422 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB    _u(12)
1423 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB    _u(12)
1424 #define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO"
1425 // -----------------------------------------------------------------------------
1426 // Field       : IO_BANK0_GPIO8_STATUS_OUTTOPAD
1427 // Description : output signal to pad after register override is applied
1428 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET  _u(0x0)
1429 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS   _u(0x00000200)
1430 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB    _u(9)
1431 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB    _u(9)
1432 #define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO"
1433 // -----------------------------------------------------------------------------
1434 // Field       : IO_BANK0_GPIO8_STATUS_OUTFROMPERI
1435 // Description : output signal from selected peripheral, before register
1436 //               override is applied
1437 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET  _u(0x0)
1438 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
1439 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB    _u(8)
1440 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB    _u(8)
1441 #define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO"
1442 // =============================================================================
1443 // Register    : IO_BANK0_GPIO8_CTRL
1444 // Description : GPIO control including function select and overrides.
1445 #define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044)
1446 #define IO_BANK0_GPIO8_CTRL_BITS   _u(0x3003331f)
1447 #define IO_BANK0_GPIO8_CTRL_RESET  _u(0x0000001f)
1448 // -----------------------------------------------------------------------------
1449 // Field       : IO_BANK0_GPIO8_CTRL_IRQOVER
1450 // Description : 0x0 -> don't invert the interrupt
1451 //               0x1 -> invert the interrupt
1452 //               0x2 -> drive interrupt low
1453 //               0x3 -> drive interrupt high
1454 #define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET        _u(0x0)
1455 #define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS         _u(0x30000000)
1456 #define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB          _u(29)
1457 #define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB          _u(28)
1458 #define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS       "RW"
1459 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
1460 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
1461 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
1462 #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
1463 // -----------------------------------------------------------------------------
1464 // Field       : IO_BANK0_GPIO8_CTRL_INOVER
1465 // Description : 0x0 -> don't invert the peri input
1466 //               0x1 -> invert the peri input
1467 //               0x2 -> drive peri input low
1468 //               0x3 -> drive peri input high
1469 #define IO_BANK0_GPIO8_CTRL_INOVER_RESET        _u(0x0)
1470 #define IO_BANK0_GPIO8_CTRL_INOVER_BITS         _u(0x00030000)
1471 #define IO_BANK0_GPIO8_CTRL_INOVER_MSB          _u(17)
1472 #define IO_BANK0_GPIO8_CTRL_INOVER_LSB          _u(16)
1473 #define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS       "RW"
1474 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0)
1475 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1)
1476 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW    _u(0x2)
1477 #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH   _u(0x3)
1478 // -----------------------------------------------------------------------------
1479 // Field       : IO_BANK0_GPIO8_CTRL_OEOVER
1480 // Description : 0x0 -> drive output enable from peripheral signal selected by
1481 //               funcsel
1482 //               0x1 -> drive output enable from inverse of peripheral signal
1483 //               selected by funcsel
1484 //               0x2 -> disable output
1485 //               0x3 -> enable output
1486 #define IO_BANK0_GPIO8_CTRL_OEOVER_RESET         _u(0x0)
1487 #define IO_BANK0_GPIO8_CTRL_OEOVER_BITS          _u(0x00003000)
1488 #define IO_BANK0_GPIO8_CTRL_OEOVER_MSB           _u(13)
1489 #define IO_BANK0_GPIO8_CTRL_OEOVER_LSB           _u(12)
1490 #define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS        "RW"
1491 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
1492 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
1493 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
1494 #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
1495 // -----------------------------------------------------------------------------
1496 // Field       : IO_BANK0_GPIO8_CTRL_OUTOVER
1497 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
1498 //               0x1 -> drive output from inverse of peripheral signal selected
1499 //               by funcsel
1500 //               0x2 -> drive output low
1501 //               0x3 -> drive output high
1502 #define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET        _u(0x0)
1503 #define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS         _u(0x00000300)
1504 #define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB          _u(9)
1505 #define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB          _u(8)
1506 #define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS       "RW"
1507 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
1508 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
1509 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
1510 #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
1511 // -----------------------------------------------------------------------------
1512 // Field       : IO_BANK0_GPIO8_CTRL_FUNCSEL
1513 // Description : 0-31 -> selects pin function according to the gpio table
1514 //               31 == NULL
1515 //               0x01 -> spi1_rx
1516 //               0x02 -> uart1_tx
1517 //               0x03 -> i2c0_sda
1518 //               0x04 -> pwm_a_4
1519 //               0x05 -> sio_8
1520 //               0x06 -> pio0_8
1521 //               0x07 -> pio1_8
1522 //               0x08 -> usb_muxing_extphy_rcv
1523 //               0x09 -> usb_muxing_vbus_en
1524 //               0x1f -> null
1525 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET                       _u(0x1f)
1526 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS                        _u(0x0000001f)
1527 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB                         _u(4)
1528 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB                         _u(0)
1529 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS                      "RW"
1530 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX               _u(0x01)
1531 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX              _u(0x02)
1532 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA              _u(0x03)
1533 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4               _u(0x04)
1534 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8                 _u(0x05)
1535 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8                _u(0x06)
1536 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8                _u(0x07)
1537 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08)
1538 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN    _u(0x09)
1539 #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL                  _u(0x1f)
1540 // =============================================================================
1541 // Register    : IO_BANK0_GPIO9_STATUS
1542 // Description : GPIO status
1543 #define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048)
1544 #define IO_BANK0_GPIO9_STATUS_BITS   _u(0x050a3300)
1545 #define IO_BANK0_GPIO9_STATUS_RESET  _u(0x00000000)
1546 // -----------------------------------------------------------------------------
1547 // Field       : IO_BANK0_GPIO9_STATUS_IRQTOPROC
1548 // Description : interrupt to processors, after override is applied
1549 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET  _u(0x0)
1550 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS   _u(0x04000000)
1551 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB    _u(26)
1552 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB    _u(26)
1553 #define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO"
1554 // -----------------------------------------------------------------------------
1555 // Field       : IO_BANK0_GPIO9_STATUS_IRQFROMPAD
1556 // Description : interrupt from pad before override is applied
1557 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET  _u(0x0)
1558 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
1559 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB    _u(24)
1560 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB    _u(24)
1561 #define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO"
1562 // -----------------------------------------------------------------------------
1563 // Field       : IO_BANK0_GPIO9_STATUS_INTOPERI
1564 // Description : input signal to peripheral, after override is applied
1565 #define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET  _u(0x0)
1566 #define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS   _u(0x00080000)
1567 #define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB    _u(19)
1568 #define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB    _u(19)
1569 #define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO"
1570 // -----------------------------------------------------------------------------
1571 // Field       : IO_BANK0_GPIO9_STATUS_INFROMPAD
1572 // Description : input signal from pad, before override is applied
1573 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET  _u(0x0)
1574 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS   _u(0x00020000)
1575 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB    _u(17)
1576 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB    _u(17)
1577 #define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO"
1578 // -----------------------------------------------------------------------------
1579 // Field       : IO_BANK0_GPIO9_STATUS_OETOPAD
1580 // Description : output enable to pad after register override is applied
1581 #define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET  _u(0x0)
1582 #define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS   _u(0x00002000)
1583 #define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB    _u(13)
1584 #define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB    _u(13)
1585 #define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO"
1586 // -----------------------------------------------------------------------------
1587 // Field       : IO_BANK0_GPIO9_STATUS_OEFROMPERI
1588 // Description : output enable from selected peripheral, before register
1589 //               override is applied
1590 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET  _u(0x0)
1591 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS   _u(0x00001000)
1592 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB    _u(12)
1593 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB    _u(12)
1594 #define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO"
1595 // -----------------------------------------------------------------------------
1596 // Field       : IO_BANK0_GPIO9_STATUS_OUTTOPAD
1597 // Description : output signal to pad after register override is applied
1598 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET  _u(0x0)
1599 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS   _u(0x00000200)
1600 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB    _u(9)
1601 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB    _u(9)
1602 #define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO"
1603 // -----------------------------------------------------------------------------
1604 // Field       : IO_BANK0_GPIO9_STATUS_OUTFROMPERI
1605 // Description : output signal from selected peripheral, before register
1606 //               override is applied
1607 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET  _u(0x0)
1608 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
1609 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB    _u(8)
1610 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB    _u(8)
1611 #define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO"
1612 // =============================================================================
1613 // Register    : IO_BANK0_GPIO9_CTRL
1614 // Description : GPIO control including function select and overrides.
1615 #define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c)
1616 #define IO_BANK0_GPIO9_CTRL_BITS   _u(0x3003331f)
1617 #define IO_BANK0_GPIO9_CTRL_RESET  _u(0x0000001f)
1618 // -----------------------------------------------------------------------------
1619 // Field       : IO_BANK0_GPIO9_CTRL_IRQOVER
1620 // Description : 0x0 -> don't invert the interrupt
1621 //               0x1 -> invert the interrupt
1622 //               0x2 -> drive interrupt low
1623 //               0x3 -> drive interrupt high
1624 #define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET        _u(0x0)
1625 #define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS         _u(0x30000000)
1626 #define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB          _u(29)
1627 #define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB          _u(28)
1628 #define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS       "RW"
1629 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
1630 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
1631 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
1632 #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
1633 // -----------------------------------------------------------------------------
1634 // Field       : IO_BANK0_GPIO9_CTRL_INOVER
1635 // Description : 0x0 -> don't invert the peri input
1636 //               0x1 -> invert the peri input
1637 //               0x2 -> drive peri input low
1638 //               0x3 -> drive peri input high
1639 #define IO_BANK0_GPIO9_CTRL_INOVER_RESET        _u(0x0)
1640 #define IO_BANK0_GPIO9_CTRL_INOVER_BITS         _u(0x00030000)
1641 #define IO_BANK0_GPIO9_CTRL_INOVER_MSB          _u(17)
1642 #define IO_BANK0_GPIO9_CTRL_INOVER_LSB          _u(16)
1643 #define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS       "RW"
1644 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0)
1645 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1)
1646 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW    _u(0x2)
1647 #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH   _u(0x3)
1648 // -----------------------------------------------------------------------------
1649 // Field       : IO_BANK0_GPIO9_CTRL_OEOVER
1650 // Description : 0x0 -> drive output enable from peripheral signal selected by
1651 //               funcsel
1652 //               0x1 -> drive output enable from inverse of peripheral signal
1653 //               selected by funcsel
1654 //               0x2 -> disable output
1655 //               0x3 -> enable output
1656 #define IO_BANK0_GPIO9_CTRL_OEOVER_RESET         _u(0x0)
1657 #define IO_BANK0_GPIO9_CTRL_OEOVER_BITS          _u(0x00003000)
1658 #define IO_BANK0_GPIO9_CTRL_OEOVER_MSB           _u(13)
1659 #define IO_BANK0_GPIO9_CTRL_OEOVER_LSB           _u(12)
1660 #define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS        "RW"
1661 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
1662 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
1663 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
1664 #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
1665 // -----------------------------------------------------------------------------
1666 // Field       : IO_BANK0_GPIO9_CTRL_OUTOVER
1667 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
1668 //               0x1 -> drive output from inverse of peripheral signal selected
1669 //               by funcsel
1670 //               0x2 -> drive output low
1671 //               0x3 -> drive output high
1672 #define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET        _u(0x0)
1673 #define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS         _u(0x00000300)
1674 #define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB          _u(9)
1675 #define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB          _u(8)
1676 #define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS       "RW"
1677 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
1678 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
1679 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
1680 #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
1681 // -----------------------------------------------------------------------------
1682 // Field       : IO_BANK0_GPIO9_CTRL_FUNCSEL
1683 // Description : 0-31 -> selects pin function according to the gpio table
1684 //               31 == NULL
1685 //               0x01 -> spi1_ss_n
1686 //               0x02 -> uart1_rx
1687 //               0x03 -> i2c0_scl
1688 //               0x04 -> pwm_b_4
1689 //               0x05 -> sio_9
1690 //               0x06 -> pio0_9
1691 //               0x07 -> pio1_9
1692 //               0x08 -> usb_muxing_extphy_vp
1693 //               0x09 -> usb_muxing_overcurr_detect
1694 //               0x1f -> null
1695 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET                            _u(0x1f)
1696 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
1697 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB                              _u(4)
1698 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB                              _u(0)
1699 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS                           "RW"
1700 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N                  _u(0x01)
1701 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX                   _u(0x02)
1702 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL                   _u(0x03)
1703 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4                    _u(0x04)
1704 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9                      _u(0x05)
1705 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9                     _u(0x06)
1706 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9                     _u(0x07)
1707 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP       _u(0x08)
1708 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
1709 #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
1710 // =============================================================================
1711 // Register    : IO_BANK0_GPIO10_STATUS
1712 // Description : GPIO status
1713 #define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050)
1714 #define IO_BANK0_GPIO10_STATUS_BITS   _u(0x050a3300)
1715 #define IO_BANK0_GPIO10_STATUS_RESET  _u(0x00000000)
1716 // -----------------------------------------------------------------------------
1717 // Field       : IO_BANK0_GPIO10_STATUS_IRQTOPROC
1718 // Description : interrupt to processors, after override is applied
1719 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET  _u(0x0)
1720 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS   _u(0x04000000)
1721 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB    _u(26)
1722 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB    _u(26)
1723 #define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO"
1724 // -----------------------------------------------------------------------------
1725 // Field       : IO_BANK0_GPIO10_STATUS_IRQFROMPAD
1726 // Description : interrupt from pad before override is applied
1727 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET  _u(0x0)
1728 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
1729 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB    _u(24)
1730 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB    _u(24)
1731 #define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO"
1732 // -----------------------------------------------------------------------------
1733 // Field       : IO_BANK0_GPIO10_STATUS_INTOPERI
1734 // Description : input signal to peripheral, after override is applied
1735 #define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET  _u(0x0)
1736 #define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS   _u(0x00080000)
1737 #define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB    _u(19)
1738 #define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB    _u(19)
1739 #define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO"
1740 // -----------------------------------------------------------------------------
1741 // Field       : IO_BANK0_GPIO10_STATUS_INFROMPAD
1742 // Description : input signal from pad, before override is applied
1743 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET  _u(0x0)
1744 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS   _u(0x00020000)
1745 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB    _u(17)
1746 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB    _u(17)
1747 #define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO"
1748 // -----------------------------------------------------------------------------
1749 // Field       : IO_BANK0_GPIO10_STATUS_OETOPAD
1750 // Description : output enable to pad after register override is applied
1751 #define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET  _u(0x0)
1752 #define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS   _u(0x00002000)
1753 #define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB    _u(13)
1754 #define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB    _u(13)
1755 #define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO"
1756 // -----------------------------------------------------------------------------
1757 // Field       : IO_BANK0_GPIO10_STATUS_OEFROMPERI
1758 // Description : output enable from selected peripheral, before register
1759 //               override is applied
1760 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET  _u(0x0)
1761 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS   _u(0x00001000)
1762 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB    _u(12)
1763 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB    _u(12)
1764 #define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO"
1765 // -----------------------------------------------------------------------------
1766 // Field       : IO_BANK0_GPIO10_STATUS_OUTTOPAD
1767 // Description : output signal to pad after register override is applied
1768 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET  _u(0x0)
1769 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS   _u(0x00000200)
1770 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB    _u(9)
1771 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB    _u(9)
1772 #define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO"
1773 // -----------------------------------------------------------------------------
1774 // Field       : IO_BANK0_GPIO10_STATUS_OUTFROMPERI
1775 // Description : output signal from selected peripheral, before register
1776 //               override is applied
1777 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET  _u(0x0)
1778 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
1779 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB    _u(8)
1780 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB    _u(8)
1781 #define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO"
1782 // =============================================================================
1783 // Register    : IO_BANK0_GPIO10_CTRL
1784 // Description : GPIO control including function select and overrides.
1785 #define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054)
1786 #define IO_BANK0_GPIO10_CTRL_BITS   _u(0x3003331f)
1787 #define IO_BANK0_GPIO10_CTRL_RESET  _u(0x0000001f)
1788 // -----------------------------------------------------------------------------
1789 // Field       : IO_BANK0_GPIO10_CTRL_IRQOVER
1790 // Description : 0x0 -> don't invert the interrupt
1791 //               0x1 -> invert the interrupt
1792 //               0x2 -> drive interrupt low
1793 //               0x3 -> drive interrupt high
1794 #define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET        _u(0x0)
1795 #define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS         _u(0x30000000)
1796 #define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB          _u(29)
1797 #define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB          _u(28)
1798 #define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS       "RW"
1799 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
1800 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
1801 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
1802 #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
1803 // -----------------------------------------------------------------------------
1804 // Field       : IO_BANK0_GPIO10_CTRL_INOVER
1805 // Description : 0x0 -> don't invert the peri input
1806 //               0x1 -> invert the peri input
1807 //               0x2 -> drive peri input low
1808 //               0x3 -> drive peri input high
1809 #define IO_BANK0_GPIO10_CTRL_INOVER_RESET        _u(0x0)
1810 #define IO_BANK0_GPIO10_CTRL_INOVER_BITS         _u(0x00030000)
1811 #define IO_BANK0_GPIO10_CTRL_INOVER_MSB          _u(17)
1812 #define IO_BANK0_GPIO10_CTRL_INOVER_LSB          _u(16)
1813 #define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS       "RW"
1814 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0)
1815 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1)
1816 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW    _u(0x2)
1817 #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH   _u(0x3)
1818 // -----------------------------------------------------------------------------
1819 // Field       : IO_BANK0_GPIO10_CTRL_OEOVER
1820 // Description : 0x0 -> drive output enable from peripheral signal selected by
1821 //               funcsel
1822 //               0x1 -> drive output enable from inverse of peripheral signal
1823 //               selected by funcsel
1824 //               0x2 -> disable output
1825 //               0x3 -> enable output
1826 #define IO_BANK0_GPIO10_CTRL_OEOVER_RESET         _u(0x0)
1827 #define IO_BANK0_GPIO10_CTRL_OEOVER_BITS          _u(0x00003000)
1828 #define IO_BANK0_GPIO10_CTRL_OEOVER_MSB           _u(13)
1829 #define IO_BANK0_GPIO10_CTRL_OEOVER_LSB           _u(12)
1830 #define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS        "RW"
1831 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
1832 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
1833 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
1834 #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
1835 // -----------------------------------------------------------------------------
1836 // Field       : IO_BANK0_GPIO10_CTRL_OUTOVER
1837 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
1838 //               0x1 -> drive output from inverse of peripheral signal selected
1839 //               by funcsel
1840 //               0x2 -> drive output low
1841 //               0x3 -> drive output high
1842 #define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET        _u(0x0)
1843 #define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS         _u(0x00000300)
1844 #define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB          _u(9)
1845 #define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB          _u(8)
1846 #define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS       "RW"
1847 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
1848 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
1849 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
1850 #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
1851 // -----------------------------------------------------------------------------
1852 // Field       : IO_BANK0_GPIO10_CTRL_FUNCSEL
1853 // Description : 0-31 -> selects pin function according to the gpio table
1854 //               31 == NULL
1855 //               0x01 -> spi1_sclk
1856 //               0x02 -> uart1_cts
1857 //               0x03 -> i2c1_sda
1858 //               0x04 -> pwm_a_5
1859 //               0x05 -> sio_10
1860 //               0x06 -> pio0_10
1861 //               0x07 -> pio1_10
1862 //               0x08 -> usb_muxing_extphy_vm
1863 //               0x09 -> usb_muxing_vbus_detect
1864 //               0x1f -> null
1865 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET                        _u(0x1f)
1866 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
1867 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB                          _u(4)
1868 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB                          _u(0)
1869 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS                       "RW"
1870 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK              _u(0x01)
1871 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS              _u(0x02)
1872 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA               _u(0x03)
1873 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5                _u(0x04)
1874 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10                 _u(0x05)
1875 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10                _u(0x06)
1876 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10                _u(0x07)
1877 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM   _u(0x08)
1878 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
1879 #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
1880 // =============================================================================
1881 // Register    : IO_BANK0_GPIO11_STATUS
1882 // Description : GPIO status
1883 #define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058)
1884 #define IO_BANK0_GPIO11_STATUS_BITS   _u(0x050a3300)
1885 #define IO_BANK0_GPIO11_STATUS_RESET  _u(0x00000000)
1886 // -----------------------------------------------------------------------------
1887 // Field       : IO_BANK0_GPIO11_STATUS_IRQTOPROC
1888 // Description : interrupt to processors, after override is applied
1889 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET  _u(0x0)
1890 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS   _u(0x04000000)
1891 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB    _u(26)
1892 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB    _u(26)
1893 #define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO"
1894 // -----------------------------------------------------------------------------
1895 // Field       : IO_BANK0_GPIO11_STATUS_IRQFROMPAD
1896 // Description : interrupt from pad before override is applied
1897 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET  _u(0x0)
1898 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
1899 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB    _u(24)
1900 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB    _u(24)
1901 #define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO"
1902 // -----------------------------------------------------------------------------
1903 // Field       : IO_BANK0_GPIO11_STATUS_INTOPERI
1904 // Description : input signal to peripheral, after override is applied
1905 #define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET  _u(0x0)
1906 #define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS   _u(0x00080000)
1907 #define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB    _u(19)
1908 #define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB    _u(19)
1909 #define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO"
1910 // -----------------------------------------------------------------------------
1911 // Field       : IO_BANK0_GPIO11_STATUS_INFROMPAD
1912 // Description : input signal from pad, before override is applied
1913 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET  _u(0x0)
1914 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS   _u(0x00020000)
1915 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB    _u(17)
1916 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB    _u(17)
1917 #define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO"
1918 // -----------------------------------------------------------------------------
1919 // Field       : IO_BANK0_GPIO11_STATUS_OETOPAD
1920 // Description : output enable to pad after register override is applied
1921 #define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET  _u(0x0)
1922 #define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS   _u(0x00002000)
1923 #define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB    _u(13)
1924 #define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB    _u(13)
1925 #define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO"
1926 // -----------------------------------------------------------------------------
1927 // Field       : IO_BANK0_GPIO11_STATUS_OEFROMPERI
1928 // Description : output enable from selected peripheral, before register
1929 //               override is applied
1930 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET  _u(0x0)
1931 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS   _u(0x00001000)
1932 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB    _u(12)
1933 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB    _u(12)
1934 #define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO"
1935 // -----------------------------------------------------------------------------
1936 // Field       : IO_BANK0_GPIO11_STATUS_OUTTOPAD
1937 // Description : output signal to pad after register override is applied
1938 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET  _u(0x0)
1939 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS   _u(0x00000200)
1940 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB    _u(9)
1941 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB    _u(9)
1942 #define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO"
1943 // -----------------------------------------------------------------------------
1944 // Field       : IO_BANK0_GPIO11_STATUS_OUTFROMPERI
1945 // Description : output signal from selected peripheral, before register
1946 //               override is applied
1947 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET  _u(0x0)
1948 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
1949 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB    _u(8)
1950 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB    _u(8)
1951 #define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO"
1952 // =============================================================================
1953 // Register    : IO_BANK0_GPIO11_CTRL
1954 // Description : GPIO control including function select and overrides.
1955 #define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c)
1956 #define IO_BANK0_GPIO11_CTRL_BITS   _u(0x3003331f)
1957 #define IO_BANK0_GPIO11_CTRL_RESET  _u(0x0000001f)
1958 // -----------------------------------------------------------------------------
1959 // Field       : IO_BANK0_GPIO11_CTRL_IRQOVER
1960 // Description : 0x0 -> don't invert the interrupt
1961 //               0x1 -> invert the interrupt
1962 //               0x2 -> drive interrupt low
1963 //               0x3 -> drive interrupt high
1964 #define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET        _u(0x0)
1965 #define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS         _u(0x30000000)
1966 #define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB          _u(29)
1967 #define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB          _u(28)
1968 #define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS       "RW"
1969 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
1970 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
1971 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
1972 #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
1973 // -----------------------------------------------------------------------------
1974 // Field       : IO_BANK0_GPIO11_CTRL_INOVER
1975 // Description : 0x0 -> don't invert the peri input
1976 //               0x1 -> invert the peri input
1977 //               0x2 -> drive peri input low
1978 //               0x3 -> drive peri input high
1979 #define IO_BANK0_GPIO11_CTRL_INOVER_RESET        _u(0x0)
1980 #define IO_BANK0_GPIO11_CTRL_INOVER_BITS         _u(0x00030000)
1981 #define IO_BANK0_GPIO11_CTRL_INOVER_MSB          _u(17)
1982 #define IO_BANK0_GPIO11_CTRL_INOVER_LSB          _u(16)
1983 #define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS       "RW"
1984 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0)
1985 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1)
1986 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW    _u(0x2)
1987 #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH   _u(0x3)
1988 // -----------------------------------------------------------------------------
1989 // Field       : IO_BANK0_GPIO11_CTRL_OEOVER
1990 // Description : 0x0 -> drive output enable from peripheral signal selected by
1991 //               funcsel
1992 //               0x1 -> drive output enable from inverse of peripheral signal
1993 //               selected by funcsel
1994 //               0x2 -> disable output
1995 //               0x3 -> enable output
1996 #define IO_BANK0_GPIO11_CTRL_OEOVER_RESET         _u(0x0)
1997 #define IO_BANK0_GPIO11_CTRL_OEOVER_BITS          _u(0x00003000)
1998 #define IO_BANK0_GPIO11_CTRL_OEOVER_MSB           _u(13)
1999 #define IO_BANK0_GPIO11_CTRL_OEOVER_LSB           _u(12)
2000 #define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS        "RW"
2001 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
2002 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
2003 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
2004 #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
2005 // -----------------------------------------------------------------------------
2006 // Field       : IO_BANK0_GPIO11_CTRL_OUTOVER
2007 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
2008 //               0x1 -> drive output from inverse of peripheral signal selected
2009 //               by funcsel
2010 //               0x2 -> drive output low
2011 //               0x3 -> drive output high
2012 #define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET        _u(0x0)
2013 #define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS         _u(0x00000300)
2014 #define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB          _u(9)
2015 #define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB          _u(8)
2016 #define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS       "RW"
2017 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
2018 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
2019 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
2020 #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
2021 // -----------------------------------------------------------------------------
2022 // Field       : IO_BANK0_GPIO11_CTRL_FUNCSEL
2023 // Description : 0-31 -> selects pin function according to the gpio table
2024 //               31 == NULL
2025 //               0x01 -> spi1_tx
2026 //               0x02 -> uart1_rts
2027 //               0x03 -> i2c1_scl
2028 //               0x04 -> pwm_b_5
2029 //               0x05 -> sio_11
2030 //               0x06 -> pio0_11
2031 //               0x07 -> pio1_11
2032 //               0x08 -> usb_muxing_extphy_suspnd
2033 //               0x09 -> usb_muxing_vbus_en
2034 //               0x1f -> null
2035 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET                          _u(0x1f)
2036 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS                           _u(0x0000001f)
2037 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB                            _u(4)
2038 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB                            _u(0)
2039 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS                         "RW"
2040 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX                  _u(0x01)
2041 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS                _u(0x02)
2042 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL                 _u(0x03)
2043 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5                  _u(0x04)
2044 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11                   _u(0x05)
2045 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11                  _u(0x06)
2046 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11                  _u(0x07)
2047 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08)
2048 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN       _u(0x09)
2049 #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL                     _u(0x1f)
2050 // =============================================================================
2051 // Register    : IO_BANK0_GPIO12_STATUS
2052 // Description : GPIO status
2053 #define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060)
2054 #define IO_BANK0_GPIO12_STATUS_BITS   _u(0x050a3300)
2055 #define IO_BANK0_GPIO12_STATUS_RESET  _u(0x00000000)
2056 // -----------------------------------------------------------------------------
2057 // Field       : IO_BANK0_GPIO12_STATUS_IRQTOPROC
2058 // Description : interrupt to processors, after override is applied
2059 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET  _u(0x0)
2060 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS   _u(0x04000000)
2061 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB    _u(26)
2062 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB    _u(26)
2063 #define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO"
2064 // -----------------------------------------------------------------------------
2065 // Field       : IO_BANK0_GPIO12_STATUS_IRQFROMPAD
2066 // Description : interrupt from pad before override is applied
2067 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET  _u(0x0)
2068 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
2069 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB    _u(24)
2070 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB    _u(24)
2071 #define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO"
2072 // -----------------------------------------------------------------------------
2073 // Field       : IO_BANK0_GPIO12_STATUS_INTOPERI
2074 // Description : input signal to peripheral, after override is applied
2075 #define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET  _u(0x0)
2076 #define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS   _u(0x00080000)
2077 #define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB    _u(19)
2078 #define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB    _u(19)
2079 #define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO"
2080 // -----------------------------------------------------------------------------
2081 // Field       : IO_BANK0_GPIO12_STATUS_INFROMPAD
2082 // Description : input signal from pad, before override is applied
2083 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET  _u(0x0)
2084 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS   _u(0x00020000)
2085 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB    _u(17)
2086 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB    _u(17)
2087 #define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO"
2088 // -----------------------------------------------------------------------------
2089 // Field       : IO_BANK0_GPIO12_STATUS_OETOPAD
2090 // Description : output enable to pad after register override is applied
2091 #define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET  _u(0x0)
2092 #define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS   _u(0x00002000)
2093 #define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB    _u(13)
2094 #define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB    _u(13)
2095 #define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO"
2096 // -----------------------------------------------------------------------------
2097 // Field       : IO_BANK0_GPIO12_STATUS_OEFROMPERI
2098 // Description : output enable from selected peripheral, before register
2099 //               override is applied
2100 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET  _u(0x0)
2101 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS   _u(0x00001000)
2102 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB    _u(12)
2103 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB    _u(12)
2104 #define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO"
2105 // -----------------------------------------------------------------------------
2106 // Field       : IO_BANK0_GPIO12_STATUS_OUTTOPAD
2107 // Description : output signal to pad after register override is applied
2108 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET  _u(0x0)
2109 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS   _u(0x00000200)
2110 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB    _u(9)
2111 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB    _u(9)
2112 #define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO"
2113 // -----------------------------------------------------------------------------
2114 // Field       : IO_BANK0_GPIO12_STATUS_OUTFROMPERI
2115 // Description : output signal from selected peripheral, before register
2116 //               override is applied
2117 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET  _u(0x0)
2118 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
2119 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB    _u(8)
2120 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB    _u(8)
2121 #define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO"
2122 // =============================================================================
2123 // Register    : IO_BANK0_GPIO12_CTRL
2124 // Description : GPIO control including function select and overrides.
2125 #define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064)
2126 #define IO_BANK0_GPIO12_CTRL_BITS   _u(0x3003331f)
2127 #define IO_BANK0_GPIO12_CTRL_RESET  _u(0x0000001f)
2128 // -----------------------------------------------------------------------------
2129 // Field       : IO_BANK0_GPIO12_CTRL_IRQOVER
2130 // Description : 0x0 -> don't invert the interrupt
2131 //               0x1 -> invert the interrupt
2132 //               0x2 -> drive interrupt low
2133 //               0x3 -> drive interrupt high
2134 #define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET        _u(0x0)
2135 #define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS         _u(0x30000000)
2136 #define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB          _u(29)
2137 #define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB          _u(28)
2138 #define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS       "RW"
2139 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
2140 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
2141 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
2142 #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
2143 // -----------------------------------------------------------------------------
2144 // Field       : IO_BANK0_GPIO12_CTRL_INOVER
2145 // Description : 0x0 -> don't invert the peri input
2146 //               0x1 -> invert the peri input
2147 //               0x2 -> drive peri input low
2148 //               0x3 -> drive peri input high
2149 #define IO_BANK0_GPIO12_CTRL_INOVER_RESET        _u(0x0)
2150 #define IO_BANK0_GPIO12_CTRL_INOVER_BITS         _u(0x00030000)
2151 #define IO_BANK0_GPIO12_CTRL_INOVER_MSB          _u(17)
2152 #define IO_BANK0_GPIO12_CTRL_INOVER_LSB          _u(16)
2153 #define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS       "RW"
2154 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0)
2155 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1)
2156 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW    _u(0x2)
2157 #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH   _u(0x3)
2158 // -----------------------------------------------------------------------------
2159 // Field       : IO_BANK0_GPIO12_CTRL_OEOVER
2160 // Description : 0x0 -> drive output enable from peripheral signal selected by
2161 //               funcsel
2162 //               0x1 -> drive output enable from inverse of peripheral signal
2163 //               selected by funcsel
2164 //               0x2 -> disable output
2165 //               0x3 -> enable output
2166 #define IO_BANK0_GPIO12_CTRL_OEOVER_RESET         _u(0x0)
2167 #define IO_BANK0_GPIO12_CTRL_OEOVER_BITS          _u(0x00003000)
2168 #define IO_BANK0_GPIO12_CTRL_OEOVER_MSB           _u(13)
2169 #define IO_BANK0_GPIO12_CTRL_OEOVER_LSB           _u(12)
2170 #define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS        "RW"
2171 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
2172 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
2173 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
2174 #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
2175 // -----------------------------------------------------------------------------
2176 // Field       : IO_BANK0_GPIO12_CTRL_OUTOVER
2177 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
2178 //               0x1 -> drive output from inverse of peripheral signal selected
2179 //               by funcsel
2180 //               0x2 -> drive output low
2181 //               0x3 -> drive output high
2182 #define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET        _u(0x0)
2183 #define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS         _u(0x00000300)
2184 #define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB          _u(9)
2185 #define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB          _u(8)
2186 #define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS       "RW"
2187 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
2188 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
2189 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
2190 #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
2191 // -----------------------------------------------------------------------------
2192 // Field       : IO_BANK0_GPIO12_CTRL_FUNCSEL
2193 // Description : 0-31 -> selects pin function according to the gpio table
2194 //               31 == NULL
2195 //               0x01 -> spi1_rx
2196 //               0x02 -> uart0_tx
2197 //               0x03 -> i2c0_sda
2198 //               0x04 -> pwm_a_6
2199 //               0x05 -> sio_12
2200 //               0x06 -> pio0_12
2201 //               0x07 -> pio1_12
2202 //               0x08 -> usb_muxing_extphy_speed
2203 //               0x09 -> usb_muxing_overcurr_detect
2204 //               0x1f -> null
2205 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET                            _u(0x1f)
2206 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
2207 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB                              _u(4)
2208 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB                              _u(0)
2209 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS                           "RW"
2210 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX                    _u(0x01)
2211 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX                   _u(0x02)
2212 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA                   _u(0x03)
2213 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6                    _u(0x04)
2214 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12                     _u(0x05)
2215 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12                    _u(0x06)
2216 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12                    _u(0x07)
2217 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED    _u(0x08)
2218 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
2219 #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
2220 // =============================================================================
2221 // Register    : IO_BANK0_GPIO13_STATUS
2222 // Description : GPIO status
2223 #define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068)
2224 #define IO_BANK0_GPIO13_STATUS_BITS   _u(0x050a3300)
2225 #define IO_BANK0_GPIO13_STATUS_RESET  _u(0x00000000)
2226 // -----------------------------------------------------------------------------
2227 // Field       : IO_BANK0_GPIO13_STATUS_IRQTOPROC
2228 // Description : interrupt to processors, after override is applied
2229 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET  _u(0x0)
2230 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS   _u(0x04000000)
2231 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB    _u(26)
2232 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB    _u(26)
2233 #define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO"
2234 // -----------------------------------------------------------------------------
2235 // Field       : IO_BANK0_GPIO13_STATUS_IRQFROMPAD
2236 // Description : interrupt from pad before override is applied
2237 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET  _u(0x0)
2238 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
2239 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB    _u(24)
2240 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB    _u(24)
2241 #define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO"
2242 // -----------------------------------------------------------------------------
2243 // Field       : IO_BANK0_GPIO13_STATUS_INTOPERI
2244 // Description : input signal to peripheral, after override is applied
2245 #define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET  _u(0x0)
2246 #define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS   _u(0x00080000)
2247 #define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB    _u(19)
2248 #define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB    _u(19)
2249 #define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO"
2250 // -----------------------------------------------------------------------------
2251 // Field       : IO_BANK0_GPIO13_STATUS_INFROMPAD
2252 // Description : input signal from pad, before override is applied
2253 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET  _u(0x0)
2254 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS   _u(0x00020000)
2255 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB    _u(17)
2256 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB    _u(17)
2257 #define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO"
2258 // -----------------------------------------------------------------------------
2259 // Field       : IO_BANK0_GPIO13_STATUS_OETOPAD
2260 // Description : output enable to pad after register override is applied
2261 #define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET  _u(0x0)
2262 #define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS   _u(0x00002000)
2263 #define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB    _u(13)
2264 #define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB    _u(13)
2265 #define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO"
2266 // -----------------------------------------------------------------------------
2267 // Field       : IO_BANK0_GPIO13_STATUS_OEFROMPERI
2268 // Description : output enable from selected peripheral, before register
2269 //               override is applied
2270 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET  _u(0x0)
2271 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS   _u(0x00001000)
2272 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB    _u(12)
2273 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB    _u(12)
2274 #define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO"
2275 // -----------------------------------------------------------------------------
2276 // Field       : IO_BANK0_GPIO13_STATUS_OUTTOPAD
2277 // Description : output signal to pad after register override is applied
2278 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET  _u(0x0)
2279 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS   _u(0x00000200)
2280 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB    _u(9)
2281 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB    _u(9)
2282 #define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO"
2283 // -----------------------------------------------------------------------------
2284 // Field       : IO_BANK0_GPIO13_STATUS_OUTFROMPERI
2285 // Description : output signal from selected peripheral, before register
2286 //               override is applied
2287 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET  _u(0x0)
2288 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
2289 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB    _u(8)
2290 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB    _u(8)
2291 #define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO"
2292 // =============================================================================
2293 // Register    : IO_BANK0_GPIO13_CTRL
2294 // Description : GPIO control including function select and overrides.
2295 #define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c)
2296 #define IO_BANK0_GPIO13_CTRL_BITS   _u(0x3003331f)
2297 #define IO_BANK0_GPIO13_CTRL_RESET  _u(0x0000001f)
2298 // -----------------------------------------------------------------------------
2299 // Field       : IO_BANK0_GPIO13_CTRL_IRQOVER
2300 // Description : 0x0 -> don't invert the interrupt
2301 //               0x1 -> invert the interrupt
2302 //               0x2 -> drive interrupt low
2303 //               0x3 -> drive interrupt high
2304 #define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET        _u(0x0)
2305 #define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS         _u(0x30000000)
2306 #define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB          _u(29)
2307 #define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB          _u(28)
2308 #define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS       "RW"
2309 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
2310 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
2311 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
2312 #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
2313 // -----------------------------------------------------------------------------
2314 // Field       : IO_BANK0_GPIO13_CTRL_INOVER
2315 // Description : 0x0 -> don't invert the peri input
2316 //               0x1 -> invert the peri input
2317 //               0x2 -> drive peri input low
2318 //               0x3 -> drive peri input high
2319 #define IO_BANK0_GPIO13_CTRL_INOVER_RESET        _u(0x0)
2320 #define IO_BANK0_GPIO13_CTRL_INOVER_BITS         _u(0x00030000)
2321 #define IO_BANK0_GPIO13_CTRL_INOVER_MSB          _u(17)
2322 #define IO_BANK0_GPIO13_CTRL_INOVER_LSB          _u(16)
2323 #define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS       "RW"
2324 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0)
2325 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1)
2326 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW    _u(0x2)
2327 #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH   _u(0x3)
2328 // -----------------------------------------------------------------------------
2329 // Field       : IO_BANK0_GPIO13_CTRL_OEOVER
2330 // Description : 0x0 -> drive output enable from peripheral signal selected by
2331 //               funcsel
2332 //               0x1 -> drive output enable from inverse of peripheral signal
2333 //               selected by funcsel
2334 //               0x2 -> disable output
2335 //               0x3 -> enable output
2336 #define IO_BANK0_GPIO13_CTRL_OEOVER_RESET         _u(0x0)
2337 #define IO_BANK0_GPIO13_CTRL_OEOVER_BITS          _u(0x00003000)
2338 #define IO_BANK0_GPIO13_CTRL_OEOVER_MSB           _u(13)
2339 #define IO_BANK0_GPIO13_CTRL_OEOVER_LSB           _u(12)
2340 #define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS        "RW"
2341 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
2342 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
2343 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
2344 #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
2345 // -----------------------------------------------------------------------------
2346 // Field       : IO_BANK0_GPIO13_CTRL_OUTOVER
2347 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
2348 //               0x1 -> drive output from inverse of peripheral signal selected
2349 //               by funcsel
2350 //               0x2 -> drive output low
2351 //               0x3 -> drive output high
2352 #define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET        _u(0x0)
2353 #define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS         _u(0x00000300)
2354 #define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB          _u(9)
2355 #define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB          _u(8)
2356 #define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS       "RW"
2357 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
2358 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
2359 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
2360 #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
2361 // -----------------------------------------------------------------------------
2362 // Field       : IO_BANK0_GPIO13_CTRL_FUNCSEL
2363 // Description : 0-31 -> selects pin function according to the gpio table
2364 //               31 == NULL
2365 //               0x01 -> spi1_ss_n
2366 //               0x02 -> uart0_rx
2367 //               0x03 -> i2c0_scl
2368 //               0x04 -> pwm_b_6
2369 //               0x05 -> sio_13
2370 //               0x06 -> pio0_13
2371 //               0x07 -> pio1_13
2372 //               0x08 -> usb_muxing_extphy_vpo
2373 //               0x09 -> usb_muxing_vbus_detect
2374 //               0x1f -> null
2375 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET                        _u(0x1f)
2376 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
2377 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB                          _u(4)
2378 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB                          _u(0)
2379 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS                       "RW"
2380 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N              _u(0x01)
2381 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX               _u(0x02)
2382 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL               _u(0x03)
2383 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6                _u(0x04)
2384 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13                 _u(0x05)
2385 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13                _u(0x06)
2386 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13                _u(0x07)
2387 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO  _u(0x08)
2388 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
2389 #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
2390 // =============================================================================
2391 // Register    : IO_BANK0_GPIO14_STATUS
2392 // Description : GPIO status
2393 #define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070)
2394 #define IO_BANK0_GPIO14_STATUS_BITS   _u(0x050a3300)
2395 #define IO_BANK0_GPIO14_STATUS_RESET  _u(0x00000000)
2396 // -----------------------------------------------------------------------------
2397 // Field       : IO_BANK0_GPIO14_STATUS_IRQTOPROC
2398 // Description : interrupt to processors, after override is applied
2399 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET  _u(0x0)
2400 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS   _u(0x04000000)
2401 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB    _u(26)
2402 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB    _u(26)
2403 #define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO"
2404 // -----------------------------------------------------------------------------
2405 // Field       : IO_BANK0_GPIO14_STATUS_IRQFROMPAD
2406 // Description : interrupt from pad before override is applied
2407 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET  _u(0x0)
2408 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
2409 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB    _u(24)
2410 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB    _u(24)
2411 #define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO"
2412 // -----------------------------------------------------------------------------
2413 // Field       : IO_BANK0_GPIO14_STATUS_INTOPERI
2414 // Description : input signal to peripheral, after override is applied
2415 #define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET  _u(0x0)
2416 #define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS   _u(0x00080000)
2417 #define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB    _u(19)
2418 #define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB    _u(19)
2419 #define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO"
2420 // -----------------------------------------------------------------------------
2421 // Field       : IO_BANK0_GPIO14_STATUS_INFROMPAD
2422 // Description : input signal from pad, before override is applied
2423 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET  _u(0x0)
2424 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS   _u(0x00020000)
2425 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB    _u(17)
2426 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB    _u(17)
2427 #define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO"
2428 // -----------------------------------------------------------------------------
2429 // Field       : IO_BANK0_GPIO14_STATUS_OETOPAD
2430 // Description : output enable to pad after register override is applied
2431 #define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET  _u(0x0)
2432 #define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS   _u(0x00002000)
2433 #define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB    _u(13)
2434 #define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB    _u(13)
2435 #define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO"
2436 // -----------------------------------------------------------------------------
2437 // Field       : IO_BANK0_GPIO14_STATUS_OEFROMPERI
2438 // Description : output enable from selected peripheral, before register
2439 //               override is applied
2440 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET  _u(0x0)
2441 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS   _u(0x00001000)
2442 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB    _u(12)
2443 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB    _u(12)
2444 #define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO"
2445 // -----------------------------------------------------------------------------
2446 // Field       : IO_BANK0_GPIO14_STATUS_OUTTOPAD
2447 // Description : output signal to pad after register override is applied
2448 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET  _u(0x0)
2449 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS   _u(0x00000200)
2450 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB    _u(9)
2451 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB    _u(9)
2452 #define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO"
2453 // -----------------------------------------------------------------------------
2454 // Field       : IO_BANK0_GPIO14_STATUS_OUTFROMPERI
2455 // Description : output signal from selected peripheral, before register
2456 //               override is applied
2457 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET  _u(0x0)
2458 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
2459 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB    _u(8)
2460 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB    _u(8)
2461 #define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO"
2462 // =============================================================================
2463 // Register    : IO_BANK0_GPIO14_CTRL
2464 // Description : GPIO control including function select and overrides.
2465 #define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074)
2466 #define IO_BANK0_GPIO14_CTRL_BITS   _u(0x3003331f)
2467 #define IO_BANK0_GPIO14_CTRL_RESET  _u(0x0000001f)
2468 // -----------------------------------------------------------------------------
2469 // Field       : IO_BANK0_GPIO14_CTRL_IRQOVER
2470 // Description : 0x0 -> don't invert the interrupt
2471 //               0x1 -> invert the interrupt
2472 //               0x2 -> drive interrupt low
2473 //               0x3 -> drive interrupt high
2474 #define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET        _u(0x0)
2475 #define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS         _u(0x30000000)
2476 #define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB          _u(29)
2477 #define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB          _u(28)
2478 #define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS       "RW"
2479 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
2480 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
2481 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
2482 #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
2483 // -----------------------------------------------------------------------------
2484 // Field       : IO_BANK0_GPIO14_CTRL_INOVER
2485 // Description : 0x0 -> don't invert the peri input
2486 //               0x1 -> invert the peri input
2487 //               0x2 -> drive peri input low
2488 //               0x3 -> drive peri input high
2489 #define IO_BANK0_GPIO14_CTRL_INOVER_RESET        _u(0x0)
2490 #define IO_BANK0_GPIO14_CTRL_INOVER_BITS         _u(0x00030000)
2491 #define IO_BANK0_GPIO14_CTRL_INOVER_MSB          _u(17)
2492 #define IO_BANK0_GPIO14_CTRL_INOVER_LSB          _u(16)
2493 #define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS       "RW"
2494 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0)
2495 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1)
2496 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW    _u(0x2)
2497 #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH   _u(0x3)
2498 // -----------------------------------------------------------------------------
2499 // Field       : IO_BANK0_GPIO14_CTRL_OEOVER
2500 // Description : 0x0 -> drive output enable from peripheral signal selected by
2501 //               funcsel
2502 //               0x1 -> drive output enable from inverse of peripheral signal
2503 //               selected by funcsel
2504 //               0x2 -> disable output
2505 //               0x3 -> enable output
2506 #define IO_BANK0_GPIO14_CTRL_OEOVER_RESET         _u(0x0)
2507 #define IO_BANK0_GPIO14_CTRL_OEOVER_BITS          _u(0x00003000)
2508 #define IO_BANK0_GPIO14_CTRL_OEOVER_MSB           _u(13)
2509 #define IO_BANK0_GPIO14_CTRL_OEOVER_LSB           _u(12)
2510 #define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS        "RW"
2511 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
2512 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
2513 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
2514 #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
2515 // -----------------------------------------------------------------------------
2516 // Field       : IO_BANK0_GPIO14_CTRL_OUTOVER
2517 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
2518 //               0x1 -> drive output from inverse of peripheral signal selected
2519 //               by funcsel
2520 //               0x2 -> drive output low
2521 //               0x3 -> drive output high
2522 #define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET        _u(0x0)
2523 #define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS         _u(0x00000300)
2524 #define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB          _u(9)
2525 #define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB          _u(8)
2526 #define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS       "RW"
2527 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
2528 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
2529 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
2530 #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
2531 // -----------------------------------------------------------------------------
2532 // Field       : IO_BANK0_GPIO14_CTRL_FUNCSEL
2533 // Description : 0-31 -> selects pin function according to the gpio table
2534 //               31 == NULL
2535 //               0x01 -> spi1_sclk
2536 //               0x02 -> uart0_cts
2537 //               0x03 -> i2c1_sda
2538 //               0x04 -> pwm_a_7
2539 //               0x05 -> sio_14
2540 //               0x06 -> pio0_14
2541 //               0x07 -> pio1_14
2542 //               0x08 -> usb_muxing_extphy_vmo
2543 //               0x09 -> usb_muxing_vbus_en
2544 //               0x1f -> null
2545 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET                       _u(0x1f)
2546 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS                        _u(0x0000001f)
2547 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB                         _u(4)
2548 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB                         _u(0)
2549 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS                      "RW"
2550 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK             _u(0x01)
2551 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS             _u(0x02)
2552 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA              _u(0x03)
2553 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7               _u(0x04)
2554 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14                _u(0x05)
2555 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14               _u(0x06)
2556 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14               _u(0x07)
2557 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08)
2558 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN    _u(0x09)
2559 #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL                  _u(0x1f)
2560 // =============================================================================
2561 // Register    : IO_BANK0_GPIO15_STATUS
2562 // Description : GPIO status
2563 #define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078)
2564 #define IO_BANK0_GPIO15_STATUS_BITS   _u(0x050a3300)
2565 #define IO_BANK0_GPIO15_STATUS_RESET  _u(0x00000000)
2566 // -----------------------------------------------------------------------------
2567 // Field       : IO_BANK0_GPIO15_STATUS_IRQTOPROC
2568 // Description : interrupt to processors, after override is applied
2569 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET  _u(0x0)
2570 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS   _u(0x04000000)
2571 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB    _u(26)
2572 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB    _u(26)
2573 #define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO"
2574 // -----------------------------------------------------------------------------
2575 // Field       : IO_BANK0_GPIO15_STATUS_IRQFROMPAD
2576 // Description : interrupt from pad before override is applied
2577 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET  _u(0x0)
2578 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
2579 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB    _u(24)
2580 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB    _u(24)
2581 #define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO"
2582 // -----------------------------------------------------------------------------
2583 // Field       : IO_BANK0_GPIO15_STATUS_INTOPERI
2584 // Description : input signal to peripheral, after override is applied
2585 #define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET  _u(0x0)
2586 #define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS   _u(0x00080000)
2587 #define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB    _u(19)
2588 #define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB    _u(19)
2589 #define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO"
2590 // -----------------------------------------------------------------------------
2591 // Field       : IO_BANK0_GPIO15_STATUS_INFROMPAD
2592 // Description : input signal from pad, before override is applied
2593 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET  _u(0x0)
2594 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS   _u(0x00020000)
2595 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB    _u(17)
2596 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB    _u(17)
2597 #define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO"
2598 // -----------------------------------------------------------------------------
2599 // Field       : IO_BANK0_GPIO15_STATUS_OETOPAD
2600 // Description : output enable to pad after register override is applied
2601 #define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET  _u(0x0)
2602 #define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS   _u(0x00002000)
2603 #define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB    _u(13)
2604 #define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB    _u(13)
2605 #define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO"
2606 // -----------------------------------------------------------------------------
2607 // Field       : IO_BANK0_GPIO15_STATUS_OEFROMPERI
2608 // Description : output enable from selected peripheral, before register
2609 //               override is applied
2610 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET  _u(0x0)
2611 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS   _u(0x00001000)
2612 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB    _u(12)
2613 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB    _u(12)
2614 #define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO"
2615 // -----------------------------------------------------------------------------
2616 // Field       : IO_BANK0_GPIO15_STATUS_OUTTOPAD
2617 // Description : output signal to pad after register override is applied
2618 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET  _u(0x0)
2619 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS   _u(0x00000200)
2620 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB    _u(9)
2621 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB    _u(9)
2622 #define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO"
2623 // -----------------------------------------------------------------------------
2624 // Field       : IO_BANK0_GPIO15_STATUS_OUTFROMPERI
2625 // Description : output signal from selected peripheral, before register
2626 //               override is applied
2627 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET  _u(0x0)
2628 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
2629 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB    _u(8)
2630 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB    _u(8)
2631 #define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO"
2632 // =============================================================================
2633 // Register    : IO_BANK0_GPIO15_CTRL
2634 // Description : GPIO control including function select and overrides.
2635 #define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c)
2636 #define IO_BANK0_GPIO15_CTRL_BITS   _u(0x3003331f)
2637 #define IO_BANK0_GPIO15_CTRL_RESET  _u(0x0000001f)
2638 // -----------------------------------------------------------------------------
2639 // Field       : IO_BANK0_GPIO15_CTRL_IRQOVER
2640 // Description : 0x0 -> don't invert the interrupt
2641 //               0x1 -> invert the interrupt
2642 //               0x2 -> drive interrupt low
2643 //               0x3 -> drive interrupt high
2644 #define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET        _u(0x0)
2645 #define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS         _u(0x30000000)
2646 #define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB          _u(29)
2647 #define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB          _u(28)
2648 #define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS       "RW"
2649 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
2650 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
2651 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
2652 #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
2653 // -----------------------------------------------------------------------------
2654 // Field       : IO_BANK0_GPIO15_CTRL_INOVER
2655 // Description : 0x0 -> don't invert the peri input
2656 //               0x1 -> invert the peri input
2657 //               0x2 -> drive peri input low
2658 //               0x3 -> drive peri input high
2659 #define IO_BANK0_GPIO15_CTRL_INOVER_RESET        _u(0x0)
2660 #define IO_BANK0_GPIO15_CTRL_INOVER_BITS         _u(0x00030000)
2661 #define IO_BANK0_GPIO15_CTRL_INOVER_MSB          _u(17)
2662 #define IO_BANK0_GPIO15_CTRL_INOVER_LSB          _u(16)
2663 #define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS       "RW"
2664 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0)
2665 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1)
2666 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW    _u(0x2)
2667 #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH   _u(0x3)
2668 // -----------------------------------------------------------------------------
2669 // Field       : IO_BANK0_GPIO15_CTRL_OEOVER
2670 // Description : 0x0 -> drive output enable from peripheral signal selected by
2671 //               funcsel
2672 //               0x1 -> drive output enable from inverse of peripheral signal
2673 //               selected by funcsel
2674 //               0x2 -> disable output
2675 //               0x3 -> enable output
2676 #define IO_BANK0_GPIO15_CTRL_OEOVER_RESET         _u(0x0)
2677 #define IO_BANK0_GPIO15_CTRL_OEOVER_BITS          _u(0x00003000)
2678 #define IO_BANK0_GPIO15_CTRL_OEOVER_MSB           _u(13)
2679 #define IO_BANK0_GPIO15_CTRL_OEOVER_LSB           _u(12)
2680 #define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS        "RW"
2681 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
2682 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
2683 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
2684 #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
2685 // -----------------------------------------------------------------------------
2686 // Field       : IO_BANK0_GPIO15_CTRL_OUTOVER
2687 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
2688 //               0x1 -> drive output from inverse of peripheral signal selected
2689 //               by funcsel
2690 //               0x2 -> drive output low
2691 //               0x3 -> drive output high
2692 #define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET        _u(0x0)
2693 #define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS         _u(0x00000300)
2694 #define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB          _u(9)
2695 #define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB          _u(8)
2696 #define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS       "RW"
2697 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
2698 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
2699 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
2700 #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
2701 // -----------------------------------------------------------------------------
2702 // Field       : IO_BANK0_GPIO15_CTRL_FUNCSEL
2703 // Description : 0-31 -> selects pin function according to the gpio table
2704 //               31 == NULL
2705 //               0x01 -> spi1_tx
2706 //               0x02 -> uart0_rts
2707 //               0x03 -> i2c1_scl
2708 //               0x04 -> pwm_b_7
2709 //               0x05 -> sio_15
2710 //               0x06 -> pio0_15
2711 //               0x07 -> pio1_15
2712 //               0x08 -> usb_muxing_digital_dp
2713 //               0x09 -> usb_muxing_overcurr_detect
2714 //               0x1f -> null
2715 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET                            _u(0x1f)
2716 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
2717 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB                              _u(4)
2718 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB                              _u(0)
2719 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS                           "RW"
2720 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX                    _u(0x01)
2721 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS                  _u(0x02)
2722 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL                   _u(0x03)
2723 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7                    _u(0x04)
2724 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15                     _u(0x05)
2725 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15                    _u(0x06)
2726 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15                    _u(0x07)
2727 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP      _u(0x08)
2728 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
2729 #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
2730 // =============================================================================
2731 // Register    : IO_BANK0_GPIO16_STATUS
2732 // Description : GPIO status
2733 #define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080)
2734 #define IO_BANK0_GPIO16_STATUS_BITS   _u(0x050a3300)
2735 #define IO_BANK0_GPIO16_STATUS_RESET  _u(0x00000000)
2736 // -----------------------------------------------------------------------------
2737 // Field       : IO_BANK0_GPIO16_STATUS_IRQTOPROC
2738 // Description : interrupt to processors, after override is applied
2739 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET  _u(0x0)
2740 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS   _u(0x04000000)
2741 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB    _u(26)
2742 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB    _u(26)
2743 #define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO"
2744 // -----------------------------------------------------------------------------
2745 // Field       : IO_BANK0_GPIO16_STATUS_IRQFROMPAD
2746 // Description : interrupt from pad before override is applied
2747 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET  _u(0x0)
2748 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
2749 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB    _u(24)
2750 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB    _u(24)
2751 #define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO"
2752 // -----------------------------------------------------------------------------
2753 // Field       : IO_BANK0_GPIO16_STATUS_INTOPERI
2754 // Description : input signal to peripheral, after override is applied
2755 #define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET  _u(0x0)
2756 #define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS   _u(0x00080000)
2757 #define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB    _u(19)
2758 #define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB    _u(19)
2759 #define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO"
2760 // -----------------------------------------------------------------------------
2761 // Field       : IO_BANK0_GPIO16_STATUS_INFROMPAD
2762 // Description : input signal from pad, before override is applied
2763 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET  _u(0x0)
2764 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS   _u(0x00020000)
2765 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB    _u(17)
2766 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB    _u(17)
2767 #define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO"
2768 // -----------------------------------------------------------------------------
2769 // Field       : IO_BANK0_GPIO16_STATUS_OETOPAD
2770 // Description : output enable to pad after register override is applied
2771 #define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET  _u(0x0)
2772 #define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS   _u(0x00002000)
2773 #define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB    _u(13)
2774 #define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB    _u(13)
2775 #define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO"
2776 // -----------------------------------------------------------------------------
2777 // Field       : IO_BANK0_GPIO16_STATUS_OEFROMPERI
2778 // Description : output enable from selected peripheral, before register
2779 //               override is applied
2780 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET  _u(0x0)
2781 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS   _u(0x00001000)
2782 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB    _u(12)
2783 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB    _u(12)
2784 #define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO"
2785 // -----------------------------------------------------------------------------
2786 // Field       : IO_BANK0_GPIO16_STATUS_OUTTOPAD
2787 // Description : output signal to pad after register override is applied
2788 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET  _u(0x0)
2789 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS   _u(0x00000200)
2790 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB    _u(9)
2791 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB    _u(9)
2792 #define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO"
2793 // -----------------------------------------------------------------------------
2794 // Field       : IO_BANK0_GPIO16_STATUS_OUTFROMPERI
2795 // Description : output signal from selected peripheral, before register
2796 //               override is applied
2797 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET  _u(0x0)
2798 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
2799 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB    _u(8)
2800 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB    _u(8)
2801 #define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO"
2802 // =============================================================================
2803 // Register    : IO_BANK0_GPIO16_CTRL
2804 // Description : GPIO control including function select and overrides.
2805 #define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084)
2806 #define IO_BANK0_GPIO16_CTRL_BITS   _u(0x3003331f)
2807 #define IO_BANK0_GPIO16_CTRL_RESET  _u(0x0000001f)
2808 // -----------------------------------------------------------------------------
2809 // Field       : IO_BANK0_GPIO16_CTRL_IRQOVER
2810 // Description : 0x0 -> don't invert the interrupt
2811 //               0x1 -> invert the interrupt
2812 //               0x2 -> drive interrupt low
2813 //               0x3 -> drive interrupt high
2814 #define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET        _u(0x0)
2815 #define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS         _u(0x30000000)
2816 #define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB          _u(29)
2817 #define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB          _u(28)
2818 #define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS       "RW"
2819 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
2820 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
2821 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
2822 #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
2823 // -----------------------------------------------------------------------------
2824 // Field       : IO_BANK0_GPIO16_CTRL_INOVER
2825 // Description : 0x0 -> don't invert the peri input
2826 //               0x1 -> invert the peri input
2827 //               0x2 -> drive peri input low
2828 //               0x3 -> drive peri input high
2829 #define IO_BANK0_GPIO16_CTRL_INOVER_RESET        _u(0x0)
2830 #define IO_BANK0_GPIO16_CTRL_INOVER_BITS         _u(0x00030000)
2831 #define IO_BANK0_GPIO16_CTRL_INOVER_MSB          _u(17)
2832 #define IO_BANK0_GPIO16_CTRL_INOVER_LSB          _u(16)
2833 #define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS       "RW"
2834 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0)
2835 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1)
2836 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW    _u(0x2)
2837 #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH   _u(0x3)
2838 // -----------------------------------------------------------------------------
2839 // Field       : IO_BANK0_GPIO16_CTRL_OEOVER
2840 // Description : 0x0 -> drive output enable from peripheral signal selected by
2841 //               funcsel
2842 //               0x1 -> drive output enable from inverse of peripheral signal
2843 //               selected by funcsel
2844 //               0x2 -> disable output
2845 //               0x3 -> enable output
2846 #define IO_BANK0_GPIO16_CTRL_OEOVER_RESET         _u(0x0)
2847 #define IO_BANK0_GPIO16_CTRL_OEOVER_BITS          _u(0x00003000)
2848 #define IO_BANK0_GPIO16_CTRL_OEOVER_MSB           _u(13)
2849 #define IO_BANK0_GPIO16_CTRL_OEOVER_LSB           _u(12)
2850 #define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS        "RW"
2851 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
2852 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
2853 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
2854 #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
2855 // -----------------------------------------------------------------------------
2856 // Field       : IO_BANK0_GPIO16_CTRL_OUTOVER
2857 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
2858 //               0x1 -> drive output from inverse of peripheral signal selected
2859 //               by funcsel
2860 //               0x2 -> drive output low
2861 //               0x3 -> drive output high
2862 #define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET        _u(0x0)
2863 #define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS         _u(0x00000300)
2864 #define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB          _u(9)
2865 #define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB          _u(8)
2866 #define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS       "RW"
2867 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
2868 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
2869 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
2870 #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
2871 // -----------------------------------------------------------------------------
2872 // Field       : IO_BANK0_GPIO16_CTRL_FUNCSEL
2873 // Description : 0-31 -> selects pin function according to the gpio table
2874 //               31 == NULL
2875 //               0x01 -> spi0_rx
2876 //               0x02 -> uart0_tx
2877 //               0x03 -> i2c0_sda
2878 //               0x04 -> pwm_a_0
2879 //               0x05 -> sio_16
2880 //               0x06 -> pio0_16
2881 //               0x07 -> pio1_16
2882 //               0x08 -> usb_muxing_digital_dm
2883 //               0x09 -> usb_muxing_vbus_detect
2884 //               0x1f -> null
2885 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET                        _u(0x1f)
2886 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
2887 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB                          _u(4)
2888 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB                          _u(0)
2889 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS                       "RW"
2890 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX                _u(0x01)
2891 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX               _u(0x02)
2892 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA               _u(0x03)
2893 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0                _u(0x04)
2894 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16                 _u(0x05)
2895 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16                _u(0x06)
2896 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16                _u(0x07)
2897 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM  _u(0x08)
2898 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
2899 #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
2900 // =============================================================================
2901 // Register    : IO_BANK0_GPIO17_STATUS
2902 // Description : GPIO status
2903 #define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088)
2904 #define IO_BANK0_GPIO17_STATUS_BITS   _u(0x050a3300)
2905 #define IO_BANK0_GPIO17_STATUS_RESET  _u(0x00000000)
2906 // -----------------------------------------------------------------------------
2907 // Field       : IO_BANK0_GPIO17_STATUS_IRQTOPROC
2908 // Description : interrupt to processors, after override is applied
2909 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET  _u(0x0)
2910 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS   _u(0x04000000)
2911 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB    _u(26)
2912 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB    _u(26)
2913 #define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO"
2914 // -----------------------------------------------------------------------------
2915 // Field       : IO_BANK0_GPIO17_STATUS_IRQFROMPAD
2916 // Description : interrupt from pad before override is applied
2917 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET  _u(0x0)
2918 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
2919 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB    _u(24)
2920 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB    _u(24)
2921 #define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO"
2922 // -----------------------------------------------------------------------------
2923 // Field       : IO_BANK0_GPIO17_STATUS_INTOPERI
2924 // Description : input signal to peripheral, after override is applied
2925 #define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET  _u(0x0)
2926 #define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS   _u(0x00080000)
2927 #define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB    _u(19)
2928 #define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB    _u(19)
2929 #define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO"
2930 // -----------------------------------------------------------------------------
2931 // Field       : IO_BANK0_GPIO17_STATUS_INFROMPAD
2932 // Description : input signal from pad, before override is applied
2933 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET  _u(0x0)
2934 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS   _u(0x00020000)
2935 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB    _u(17)
2936 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB    _u(17)
2937 #define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO"
2938 // -----------------------------------------------------------------------------
2939 // Field       : IO_BANK0_GPIO17_STATUS_OETOPAD
2940 // Description : output enable to pad after register override is applied
2941 #define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET  _u(0x0)
2942 #define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS   _u(0x00002000)
2943 #define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB    _u(13)
2944 #define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB    _u(13)
2945 #define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO"
2946 // -----------------------------------------------------------------------------
2947 // Field       : IO_BANK0_GPIO17_STATUS_OEFROMPERI
2948 // Description : output enable from selected peripheral, before register
2949 //               override is applied
2950 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET  _u(0x0)
2951 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS   _u(0x00001000)
2952 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB    _u(12)
2953 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB    _u(12)
2954 #define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO"
2955 // -----------------------------------------------------------------------------
2956 // Field       : IO_BANK0_GPIO17_STATUS_OUTTOPAD
2957 // Description : output signal to pad after register override is applied
2958 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET  _u(0x0)
2959 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS   _u(0x00000200)
2960 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB    _u(9)
2961 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB    _u(9)
2962 #define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO"
2963 // -----------------------------------------------------------------------------
2964 // Field       : IO_BANK0_GPIO17_STATUS_OUTFROMPERI
2965 // Description : output signal from selected peripheral, before register
2966 //               override is applied
2967 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET  _u(0x0)
2968 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
2969 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB    _u(8)
2970 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB    _u(8)
2971 #define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO"
2972 // =============================================================================
2973 // Register    : IO_BANK0_GPIO17_CTRL
2974 // Description : GPIO control including function select and overrides.
2975 #define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c)
2976 #define IO_BANK0_GPIO17_CTRL_BITS   _u(0x3003331f)
2977 #define IO_BANK0_GPIO17_CTRL_RESET  _u(0x0000001f)
2978 // -----------------------------------------------------------------------------
2979 // Field       : IO_BANK0_GPIO17_CTRL_IRQOVER
2980 // Description : 0x0 -> don't invert the interrupt
2981 //               0x1 -> invert the interrupt
2982 //               0x2 -> drive interrupt low
2983 //               0x3 -> drive interrupt high
2984 #define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET        _u(0x0)
2985 #define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS         _u(0x30000000)
2986 #define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB          _u(29)
2987 #define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB          _u(28)
2988 #define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS       "RW"
2989 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
2990 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
2991 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
2992 #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
2993 // -----------------------------------------------------------------------------
2994 // Field       : IO_BANK0_GPIO17_CTRL_INOVER
2995 // Description : 0x0 -> don't invert the peri input
2996 //               0x1 -> invert the peri input
2997 //               0x2 -> drive peri input low
2998 //               0x3 -> drive peri input high
2999 #define IO_BANK0_GPIO17_CTRL_INOVER_RESET        _u(0x0)
3000 #define IO_BANK0_GPIO17_CTRL_INOVER_BITS         _u(0x00030000)
3001 #define IO_BANK0_GPIO17_CTRL_INOVER_MSB          _u(17)
3002 #define IO_BANK0_GPIO17_CTRL_INOVER_LSB          _u(16)
3003 #define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS       "RW"
3004 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0)
3005 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1)
3006 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW    _u(0x2)
3007 #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH   _u(0x3)
3008 // -----------------------------------------------------------------------------
3009 // Field       : IO_BANK0_GPIO17_CTRL_OEOVER
3010 // Description : 0x0 -> drive output enable from peripheral signal selected by
3011 //               funcsel
3012 //               0x1 -> drive output enable from inverse of peripheral signal
3013 //               selected by funcsel
3014 //               0x2 -> disable output
3015 //               0x3 -> enable output
3016 #define IO_BANK0_GPIO17_CTRL_OEOVER_RESET         _u(0x0)
3017 #define IO_BANK0_GPIO17_CTRL_OEOVER_BITS          _u(0x00003000)
3018 #define IO_BANK0_GPIO17_CTRL_OEOVER_MSB           _u(13)
3019 #define IO_BANK0_GPIO17_CTRL_OEOVER_LSB           _u(12)
3020 #define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS        "RW"
3021 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
3022 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
3023 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
3024 #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
3025 // -----------------------------------------------------------------------------
3026 // Field       : IO_BANK0_GPIO17_CTRL_OUTOVER
3027 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
3028 //               0x1 -> drive output from inverse of peripheral signal selected
3029 //               by funcsel
3030 //               0x2 -> drive output low
3031 //               0x3 -> drive output high
3032 #define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET        _u(0x0)
3033 #define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS         _u(0x00000300)
3034 #define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB          _u(9)
3035 #define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB          _u(8)
3036 #define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS       "RW"
3037 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
3038 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
3039 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
3040 #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
3041 // -----------------------------------------------------------------------------
3042 // Field       : IO_BANK0_GPIO17_CTRL_FUNCSEL
3043 // Description : 0-31 -> selects pin function according to the gpio table
3044 //               31 == NULL
3045 //               0x01 -> spi0_ss_n
3046 //               0x02 -> uart0_rx
3047 //               0x03 -> i2c0_scl
3048 //               0x04 -> pwm_b_0
3049 //               0x05 -> sio_17
3050 //               0x06 -> pio0_17
3051 //               0x07 -> pio1_17
3052 //               0x09 -> usb_muxing_vbus_en
3053 //               0x1f -> null
3054 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET                    _u(0x1f)
3055 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
3056 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB                      _u(4)
3057 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB                      _u(0)
3058 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS                   "RW"
3059 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N          _u(0x01)
3060 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX           _u(0x02)
3061 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL           _u(0x03)
3062 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0            _u(0x04)
3063 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17             _u(0x05)
3064 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17            _u(0x06)
3065 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17            _u(0x07)
3066 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
3067 #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
3068 // =============================================================================
3069 // Register    : IO_BANK0_GPIO18_STATUS
3070 // Description : GPIO status
3071 #define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090)
3072 #define IO_BANK0_GPIO18_STATUS_BITS   _u(0x050a3300)
3073 #define IO_BANK0_GPIO18_STATUS_RESET  _u(0x00000000)
3074 // -----------------------------------------------------------------------------
3075 // Field       : IO_BANK0_GPIO18_STATUS_IRQTOPROC
3076 // Description : interrupt to processors, after override is applied
3077 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET  _u(0x0)
3078 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS   _u(0x04000000)
3079 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB    _u(26)
3080 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB    _u(26)
3081 #define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO"
3082 // -----------------------------------------------------------------------------
3083 // Field       : IO_BANK0_GPIO18_STATUS_IRQFROMPAD
3084 // Description : interrupt from pad before override is applied
3085 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET  _u(0x0)
3086 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
3087 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB    _u(24)
3088 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB    _u(24)
3089 #define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO"
3090 // -----------------------------------------------------------------------------
3091 // Field       : IO_BANK0_GPIO18_STATUS_INTOPERI
3092 // Description : input signal to peripheral, after override is applied
3093 #define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET  _u(0x0)
3094 #define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS   _u(0x00080000)
3095 #define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB    _u(19)
3096 #define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB    _u(19)
3097 #define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO"
3098 // -----------------------------------------------------------------------------
3099 // Field       : IO_BANK0_GPIO18_STATUS_INFROMPAD
3100 // Description : input signal from pad, before override is applied
3101 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET  _u(0x0)
3102 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS   _u(0x00020000)
3103 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB    _u(17)
3104 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB    _u(17)
3105 #define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO"
3106 // -----------------------------------------------------------------------------
3107 // Field       : IO_BANK0_GPIO18_STATUS_OETOPAD
3108 // Description : output enable to pad after register override is applied
3109 #define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET  _u(0x0)
3110 #define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS   _u(0x00002000)
3111 #define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB    _u(13)
3112 #define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB    _u(13)
3113 #define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO"
3114 // -----------------------------------------------------------------------------
3115 // Field       : IO_BANK0_GPIO18_STATUS_OEFROMPERI
3116 // Description : output enable from selected peripheral, before register
3117 //               override is applied
3118 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET  _u(0x0)
3119 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS   _u(0x00001000)
3120 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB    _u(12)
3121 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB    _u(12)
3122 #define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO"
3123 // -----------------------------------------------------------------------------
3124 // Field       : IO_BANK0_GPIO18_STATUS_OUTTOPAD
3125 // Description : output signal to pad after register override is applied
3126 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET  _u(0x0)
3127 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS   _u(0x00000200)
3128 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB    _u(9)
3129 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB    _u(9)
3130 #define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO"
3131 // -----------------------------------------------------------------------------
3132 // Field       : IO_BANK0_GPIO18_STATUS_OUTFROMPERI
3133 // Description : output signal from selected peripheral, before register
3134 //               override is applied
3135 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET  _u(0x0)
3136 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
3137 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB    _u(8)
3138 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB    _u(8)
3139 #define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO"
3140 // =============================================================================
3141 // Register    : IO_BANK0_GPIO18_CTRL
3142 // Description : GPIO control including function select and overrides.
3143 #define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094)
3144 #define IO_BANK0_GPIO18_CTRL_BITS   _u(0x3003331f)
3145 #define IO_BANK0_GPIO18_CTRL_RESET  _u(0x0000001f)
3146 // -----------------------------------------------------------------------------
3147 // Field       : IO_BANK0_GPIO18_CTRL_IRQOVER
3148 // Description : 0x0 -> don't invert the interrupt
3149 //               0x1 -> invert the interrupt
3150 //               0x2 -> drive interrupt low
3151 //               0x3 -> drive interrupt high
3152 #define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET        _u(0x0)
3153 #define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS         _u(0x30000000)
3154 #define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB          _u(29)
3155 #define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB          _u(28)
3156 #define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS       "RW"
3157 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
3158 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
3159 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
3160 #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
3161 // -----------------------------------------------------------------------------
3162 // Field       : IO_BANK0_GPIO18_CTRL_INOVER
3163 // Description : 0x0 -> don't invert the peri input
3164 //               0x1 -> invert the peri input
3165 //               0x2 -> drive peri input low
3166 //               0x3 -> drive peri input high
3167 #define IO_BANK0_GPIO18_CTRL_INOVER_RESET        _u(0x0)
3168 #define IO_BANK0_GPIO18_CTRL_INOVER_BITS         _u(0x00030000)
3169 #define IO_BANK0_GPIO18_CTRL_INOVER_MSB          _u(17)
3170 #define IO_BANK0_GPIO18_CTRL_INOVER_LSB          _u(16)
3171 #define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS       "RW"
3172 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0)
3173 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1)
3174 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW    _u(0x2)
3175 #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH   _u(0x3)
3176 // -----------------------------------------------------------------------------
3177 // Field       : IO_BANK0_GPIO18_CTRL_OEOVER
3178 // Description : 0x0 -> drive output enable from peripheral signal selected by
3179 //               funcsel
3180 //               0x1 -> drive output enable from inverse of peripheral signal
3181 //               selected by funcsel
3182 //               0x2 -> disable output
3183 //               0x3 -> enable output
3184 #define IO_BANK0_GPIO18_CTRL_OEOVER_RESET         _u(0x0)
3185 #define IO_BANK0_GPIO18_CTRL_OEOVER_BITS          _u(0x00003000)
3186 #define IO_BANK0_GPIO18_CTRL_OEOVER_MSB           _u(13)
3187 #define IO_BANK0_GPIO18_CTRL_OEOVER_LSB           _u(12)
3188 #define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS        "RW"
3189 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
3190 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
3191 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
3192 #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
3193 // -----------------------------------------------------------------------------
3194 // Field       : IO_BANK0_GPIO18_CTRL_OUTOVER
3195 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
3196 //               0x1 -> drive output from inverse of peripheral signal selected
3197 //               by funcsel
3198 //               0x2 -> drive output low
3199 //               0x3 -> drive output high
3200 #define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET        _u(0x0)
3201 #define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS         _u(0x00000300)
3202 #define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB          _u(9)
3203 #define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB          _u(8)
3204 #define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS       "RW"
3205 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
3206 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
3207 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
3208 #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
3209 // -----------------------------------------------------------------------------
3210 // Field       : IO_BANK0_GPIO18_CTRL_FUNCSEL
3211 // Description : 0-31 -> selects pin function according to the gpio table
3212 //               31 == NULL
3213 //               0x01 -> spi0_sclk
3214 //               0x02 -> uart0_cts
3215 //               0x03 -> i2c1_sda
3216 //               0x04 -> pwm_a_1
3217 //               0x05 -> sio_18
3218 //               0x06 -> pio0_18
3219 //               0x07 -> pio1_18
3220 //               0x09 -> usb_muxing_overcurr_detect
3221 //               0x1f -> null
3222 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET                            _u(0x1f)
3223 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
3224 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB                              _u(4)
3225 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB                              _u(0)
3226 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS                           "RW"
3227 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK                  _u(0x01)
3228 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS                  _u(0x02)
3229 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA                   _u(0x03)
3230 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1                    _u(0x04)
3231 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18                     _u(0x05)
3232 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18                    _u(0x06)
3233 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18                    _u(0x07)
3234 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
3235 #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
3236 // =============================================================================
3237 // Register    : IO_BANK0_GPIO19_STATUS
3238 // Description : GPIO status
3239 #define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098)
3240 #define IO_BANK0_GPIO19_STATUS_BITS   _u(0x050a3300)
3241 #define IO_BANK0_GPIO19_STATUS_RESET  _u(0x00000000)
3242 // -----------------------------------------------------------------------------
3243 // Field       : IO_BANK0_GPIO19_STATUS_IRQTOPROC
3244 // Description : interrupt to processors, after override is applied
3245 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET  _u(0x0)
3246 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS   _u(0x04000000)
3247 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB    _u(26)
3248 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB    _u(26)
3249 #define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO"
3250 // -----------------------------------------------------------------------------
3251 // Field       : IO_BANK0_GPIO19_STATUS_IRQFROMPAD
3252 // Description : interrupt from pad before override is applied
3253 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET  _u(0x0)
3254 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
3255 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB    _u(24)
3256 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB    _u(24)
3257 #define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO"
3258 // -----------------------------------------------------------------------------
3259 // Field       : IO_BANK0_GPIO19_STATUS_INTOPERI
3260 // Description : input signal to peripheral, after override is applied
3261 #define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET  _u(0x0)
3262 #define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS   _u(0x00080000)
3263 #define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB    _u(19)
3264 #define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB    _u(19)
3265 #define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO"
3266 // -----------------------------------------------------------------------------
3267 // Field       : IO_BANK0_GPIO19_STATUS_INFROMPAD
3268 // Description : input signal from pad, before override is applied
3269 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET  _u(0x0)
3270 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS   _u(0x00020000)
3271 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB    _u(17)
3272 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB    _u(17)
3273 #define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO"
3274 // -----------------------------------------------------------------------------
3275 // Field       : IO_BANK0_GPIO19_STATUS_OETOPAD
3276 // Description : output enable to pad after register override is applied
3277 #define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET  _u(0x0)
3278 #define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS   _u(0x00002000)
3279 #define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB    _u(13)
3280 #define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB    _u(13)
3281 #define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO"
3282 // -----------------------------------------------------------------------------
3283 // Field       : IO_BANK0_GPIO19_STATUS_OEFROMPERI
3284 // Description : output enable from selected peripheral, before register
3285 //               override is applied
3286 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET  _u(0x0)
3287 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS   _u(0x00001000)
3288 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB    _u(12)
3289 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB    _u(12)
3290 #define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO"
3291 // -----------------------------------------------------------------------------
3292 // Field       : IO_BANK0_GPIO19_STATUS_OUTTOPAD
3293 // Description : output signal to pad after register override is applied
3294 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET  _u(0x0)
3295 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS   _u(0x00000200)
3296 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB    _u(9)
3297 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB    _u(9)
3298 #define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO"
3299 // -----------------------------------------------------------------------------
3300 // Field       : IO_BANK0_GPIO19_STATUS_OUTFROMPERI
3301 // Description : output signal from selected peripheral, before register
3302 //               override is applied
3303 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET  _u(0x0)
3304 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
3305 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB    _u(8)
3306 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB    _u(8)
3307 #define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO"
3308 // =============================================================================
3309 // Register    : IO_BANK0_GPIO19_CTRL
3310 // Description : GPIO control including function select and overrides.
3311 #define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c)
3312 #define IO_BANK0_GPIO19_CTRL_BITS   _u(0x3003331f)
3313 #define IO_BANK0_GPIO19_CTRL_RESET  _u(0x0000001f)
3314 // -----------------------------------------------------------------------------
3315 // Field       : IO_BANK0_GPIO19_CTRL_IRQOVER
3316 // Description : 0x0 -> don't invert the interrupt
3317 //               0x1 -> invert the interrupt
3318 //               0x2 -> drive interrupt low
3319 //               0x3 -> drive interrupt high
3320 #define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET        _u(0x0)
3321 #define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS         _u(0x30000000)
3322 #define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB          _u(29)
3323 #define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB          _u(28)
3324 #define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS       "RW"
3325 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
3326 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
3327 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
3328 #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
3329 // -----------------------------------------------------------------------------
3330 // Field       : IO_BANK0_GPIO19_CTRL_INOVER
3331 // Description : 0x0 -> don't invert the peri input
3332 //               0x1 -> invert the peri input
3333 //               0x2 -> drive peri input low
3334 //               0x3 -> drive peri input high
3335 #define IO_BANK0_GPIO19_CTRL_INOVER_RESET        _u(0x0)
3336 #define IO_BANK0_GPIO19_CTRL_INOVER_BITS         _u(0x00030000)
3337 #define IO_BANK0_GPIO19_CTRL_INOVER_MSB          _u(17)
3338 #define IO_BANK0_GPIO19_CTRL_INOVER_LSB          _u(16)
3339 #define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS       "RW"
3340 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0)
3341 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1)
3342 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW    _u(0x2)
3343 #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH   _u(0x3)
3344 // -----------------------------------------------------------------------------
3345 // Field       : IO_BANK0_GPIO19_CTRL_OEOVER
3346 // Description : 0x0 -> drive output enable from peripheral signal selected by
3347 //               funcsel
3348 //               0x1 -> drive output enable from inverse of peripheral signal
3349 //               selected by funcsel
3350 //               0x2 -> disable output
3351 //               0x3 -> enable output
3352 #define IO_BANK0_GPIO19_CTRL_OEOVER_RESET         _u(0x0)
3353 #define IO_BANK0_GPIO19_CTRL_OEOVER_BITS          _u(0x00003000)
3354 #define IO_BANK0_GPIO19_CTRL_OEOVER_MSB           _u(13)
3355 #define IO_BANK0_GPIO19_CTRL_OEOVER_LSB           _u(12)
3356 #define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS        "RW"
3357 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
3358 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
3359 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
3360 #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
3361 // -----------------------------------------------------------------------------
3362 // Field       : IO_BANK0_GPIO19_CTRL_OUTOVER
3363 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
3364 //               0x1 -> drive output from inverse of peripheral signal selected
3365 //               by funcsel
3366 //               0x2 -> drive output low
3367 //               0x3 -> drive output high
3368 #define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET        _u(0x0)
3369 #define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS         _u(0x00000300)
3370 #define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB          _u(9)
3371 #define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB          _u(8)
3372 #define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS       "RW"
3373 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
3374 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
3375 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
3376 #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
3377 // -----------------------------------------------------------------------------
3378 // Field       : IO_BANK0_GPIO19_CTRL_FUNCSEL
3379 // Description : 0-31 -> selects pin function according to the gpio table
3380 //               31 == NULL
3381 //               0x01 -> spi0_tx
3382 //               0x02 -> uart0_rts
3383 //               0x03 -> i2c1_scl
3384 //               0x04 -> pwm_b_1
3385 //               0x05 -> sio_19
3386 //               0x06 -> pio0_19
3387 //               0x07 -> pio1_19
3388 //               0x09 -> usb_muxing_vbus_detect
3389 //               0x1f -> null
3390 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET                        _u(0x1f)
3391 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
3392 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB                          _u(4)
3393 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB                          _u(0)
3394 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS                       "RW"
3395 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX                _u(0x01)
3396 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS              _u(0x02)
3397 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL               _u(0x03)
3398 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1                _u(0x04)
3399 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19                 _u(0x05)
3400 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19                _u(0x06)
3401 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19                _u(0x07)
3402 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
3403 #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
3404 // =============================================================================
3405 // Register    : IO_BANK0_GPIO20_STATUS
3406 // Description : GPIO status
3407 #define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0)
3408 #define IO_BANK0_GPIO20_STATUS_BITS   _u(0x050a3300)
3409 #define IO_BANK0_GPIO20_STATUS_RESET  _u(0x00000000)
3410 // -----------------------------------------------------------------------------
3411 // Field       : IO_BANK0_GPIO20_STATUS_IRQTOPROC
3412 // Description : interrupt to processors, after override is applied
3413 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET  _u(0x0)
3414 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS   _u(0x04000000)
3415 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB    _u(26)
3416 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB    _u(26)
3417 #define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO"
3418 // -----------------------------------------------------------------------------
3419 // Field       : IO_BANK0_GPIO20_STATUS_IRQFROMPAD
3420 // Description : interrupt from pad before override is applied
3421 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET  _u(0x0)
3422 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
3423 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB    _u(24)
3424 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB    _u(24)
3425 #define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO"
3426 // -----------------------------------------------------------------------------
3427 // Field       : IO_BANK0_GPIO20_STATUS_INTOPERI
3428 // Description : input signal to peripheral, after override is applied
3429 #define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET  _u(0x0)
3430 #define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS   _u(0x00080000)
3431 #define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB    _u(19)
3432 #define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB    _u(19)
3433 #define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO"
3434 // -----------------------------------------------------------------------------
3435 // Field       : IO_BANK0_GPIO20_STATUS_INFROMPAD
3436 // Description : input signal from pad, before override is applied
3437 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET  _u(0x0)
3438 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS   _u(0x00020000)
3439 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB    _u(17)
3440 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB    _u(17)
3441 #define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO"
3442 // -----------------------------------------------------------------------------
3443 // Field       : IO_BANK0_GPIO20_STATUS_OETOPAD
3444 // Description : output enable to pad after register override is applied
3445 #define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET  _u(0x0)
3446 #define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS   _u(0x00002000)
3447 #define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB    _u(13)
3448 #define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB    _u(13)
3449 #define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO"
3450 // -----------------------------------------------------------------------------
3451 // Field       : IO_BANK0_GPIO20_STATUS_OEFROMPERI
3452 // Description : output enable from selected peripheral, before register
3453 //               override is applied
3454 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET  _u(0x0)
3455 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS   _u(0x00001000)
3456 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB    _u(12)
3457 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB    _u(12)
3458 #define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO"
3459 // -----------------------------------------------------------------------------
3460 // Field       : IO_BANK0_GPIO20_STATUS_OUTTOPAD
3461 // Description : output signal to pad after register override is applied
3462 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET  _u(0x0)
3463 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS   _u(0x00000200)
3464 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB    _u(9)
3465 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB    _u(9)
3466 #define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO"
3467 // -----------------------------------------------------------------------------
3468 // Field       : IO_BANK0_GPIO20_STATUS_OUTFROMPERI
3469 // Description : output signal from selected peripheral, before register
3470 //               override is applied
3471 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET  _u(0x0)
3472 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
3473 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB    _u(8)
3474 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB    _u(8)
3475 #define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO"
3476 // =============================================================================
3477 // Register    : IO_BANK0_GPIO20_CTRL
3478 // Description : GPIO control including function select and overrides.
3479 #define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4)
3480 #define IO_BANK0_GPIO20_CTRL_BITS   _u(0x3003331f)
3481 #define IO_BANK0_GPIO20_CTRL_RESET  _u(0x0000001f)
3482 // -----------------------------------------------------------------------------
3483 // Field       : IO_BANK0_GPIO20_CTRL_IRQOVER
3484 // Description : 0x0 -> don't invert the interrupt
3485 //               0x1 -> invert the interrupt
3486 //               0x2 -> drive interrupt low
3487 //               0x3 -> drive interrupt high
3488 #define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET        _u(0x0)
3489 #define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS         _u(0x30000000)
3490 #define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB          _u(29)
3491 #define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB          _u(28)
3492 #define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS       "RW"
3493 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
3494 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
3495 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
3496 #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
3497 // -----------------------------------------------------------------------------
3498 // Field       : IO_BANK0_GPIO20_CTRL_INOVER
3499 // Description : 0x0 -> don't invert the peri input
3500 //               0x1 -> invert the peri input
3501 //               0x2 -> drive peri input low
3502 //               0x3 -> drive peri input high
3503 #define IO_BANK0_GPIO20_CTRL_INOVER_RESET        _u(0x0)
3504 #define IO_BANK0_GPIO20_CTRL_INOVER_BITS         _u(0x00030000)
3505 #define IO_BANK0_GPIO20_CTRL_INOVER_MSB          _u(17)
3506 #define IO_BANK0_GPIO20_CTRL_INOVER_LSB          _u(16)
3507 #define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS       "RW"
3508 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0)
3509 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1)
3510 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW    _u(0x2)
3511 #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH   _u(0x3)
3512 // -----------------------------------------------------------------------------
3513 // Field       : IO_BANK0_GPIO20_CTRL_OEOVER
3514 // Description : 0x0 -> drive output enable from peripheral signal selected by
3515 //               funcsel
3516 //               0x1 -> drive output enable from inverse of peripheral signal
3517 //               selected by funcsel
3518 //               0x2 -> disable output
3519 //               0x3 -> enable output
3520 #define IO_BANK0_GPIO20_CTRL_OEOVER_RESET         _u(0x0)
3521 #define IO_BANK0_GPIO20_CTRL_OEOVER_BITS          _u(0x00003000)
3522 #define IO_BANK0_GPIO20_CTRL_OEOVER_MSB           _u(13)
3523 #define IO_BANK0_GPIO20_CTRL_OEOVER_LSB           _u(12)
3524 #define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS        "RW"
3525 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
3526 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
3527 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
3528 #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
3529 // -----------------------------------------------------------------------------
3530 // Field       : IO_BANK0_GPIO20_CTRL_OUTOVER
3531 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
3532 //               0x1 -> drive output from inverse of peripheral signal selected
3533 //               by funcsel
3534 //               0x2 -> drive output low
3535 //               0x3 -> drive output high
3536 #define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET        _u(0x0)
3537 #define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS         _u(0x00000300)
3538 #define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB          _u(9)
3539 #define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB          _u(8)
3540 #define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS       "RW"
3541 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
3542 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
3543 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
3544 #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
3545 // -----------------------------------------------------------------------------
3546 // Field       : IO_BANK0_GPIO20_CTRL_FUNCSEL
3547 // Description : 0-31 -> selects pin function according to the gpio table
3548 //               31 == NULL
3549 //               0x01 -> spi0_rx
3550 //               0x02 -> uart1_tx
3551 //               0x03 -> i2c0_sda
3552 //               0x04 -> pwm_a_2
3553 //               0x05 -> sio_20
3554 //               0x06 -> pio0_20
3555 //               0x07 -> pio1_20
3556 //               0x08 -> clocks_gpin_0
3557 //               0x09 -> usb_muxing_vbus_en
3558 //               0x1f -> null
3559 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET                    _u(0x1f)
3560 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
3561 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB                      _u(4)
3562 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB                      _u(0)
3563 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS                   "RW"
3564 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX            _u(0x01)
3565 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX           _u(0x02)
3566 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA           _u(0x03)
3567 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2            _u(0x04)
3568 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20             _u(0x05)
3569 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20            _u(0x06)
3570 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20            _u(0x07)
3571 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0      _u(0x08)
3572 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
3573 #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
3574 // =============================================================================
3575 // Register    : IO_BANK0_GPIO21_STATUS
3576 // Description : GPIO status
3577 #define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8)
3578 #define IO_BANK0_GPIO21_STATUS_BITS   _u(0x050a3300)
3579 #define IO_BANK0_GPIO21_STATUS_RESET  _u(0x00000000)
3580 // -----------------------------------------------------------------------------
3581 // Field       : IO_BANK0_GPIO21_STATUS_IRQTOPROC
3582 // Description : interrupt to processors, after override is applied
3583 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET  _u(0x0)
3584 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS   _u(0x04000000)
3585 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB    _u(26)
3586 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB    _u(26)
3587 #define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO"
3588 // -----------------------------------------------------------------------------
3589 // Field       : IO_BANK0_GPIO21_STATUS_IRQFROMPAD
3590 // Description : interrupt from pad before override is applied
3591 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET  _u(0x0)
3592 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
3593 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB    _u(24)
3594 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB    _u(24)
3595 #define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO"
3596 // -----------------------------------------------------------------------------
3597 // Field       : IO_BANK0_GPIO21_STATUS_INTOPERI
3598 // Description : input signal to peripheral, after override is applied
3599 #define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET  _u(0x0)
3600 #define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS   _u(0x00080000)
3601 #define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB    _u(19)
3602 #define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB    _u(19)
3603 #define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO"
3604 // -----------------------------------------------------------------------------
3605 // Field       : IO_BANK0_GPIO21_STATUS_INFROMPAD
3606 // Description : input signal from pad, before override is applied
3607 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET  _u(0x0)
3608 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS   _u(0x00020000)
3609 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB    _u(17)
3610 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB    _u(17)
3611 #define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO"
3612 // -----------------------------------------------------------------------------
3613 // Field       : IO_BANK0_GPIO21_STATUS_OETOPAD
3614 // Description : output enable to pad after register override is applied
3615 #define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET  _u(0x0)
3616 #define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS   _u(0x00002000)
3617 #define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB    _u(13)
3618 #define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB    _u(13)
3619 #define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO"
3620 // -----------------------------------------------------------------------------
3621 // Field       : IO_BANK0_GPIO21_STATUS_OEFROMPERI
3622 // Description : output enable from selected peripheral, before register
3623 //               override is applied
3624 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET  _u(0x0)
3625 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS   _u(0x00001000)
3626 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB    _u(12)
3627 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB    _u(12)
3628 #define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO"
3629 // -----------------------------------------------------------------------------
3630 // Field       : IO_BANK0_GPIO21_STATUS_OUTTOPAD
3631 // Description : output signal to pad after register override is applied
3632 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET  _u(0x0)
3633 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS   _u(0x00000200)
3634 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB    _u(9)
3635 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB    _u(9)
3636 #define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO"
3637 // -----------------------------------------------------------------------------
3638 // Field       : IO_BANK0_GPIO21_STATUS_OUTFROMPERI
3639 // Description : output signal from selected peripheral, before register
3640 //               override is applied
3641 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET  _u(0x0)
3642 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
3643 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB    _u(8)
3644 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB    _u(8)
3645 #define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO"
3646 // =============================================================================
3647 // Register    : IO_BANK0_GPIO21_CTRL
3648 // Description : GPIO control including function select and overrides.
3649 #define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac)
3650 #define IO_BANK0_GPIO21_CTRL_BITS   _u(0x3003331f)
3651 #define IO_BANK0_GPIO21_CTRL_RESET  _u(0x0000001f)
3652 // -----------------------------------------------------------------------------
3653 // Field       : IO_BANK0_GPIO21_CTRL_IRQOVER
3654 // Description : 0x0 -> don't invert the interrupt
3655 //               0x1 -> invert the interrupt
3656 //               0x2 -> drive interrupt low
3657 //               0x3 -> drive interrupt high
3658 #define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET        _u(0x0)
3659 #define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS         _u(0x30000000)
3660 #define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB          _u(29)
3661 #define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB          _u(28)
3662 #define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS       "RW"
3663 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
3664 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
3665 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
3666 #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
3667 // -----------------------------------------------------------------------------
3668 // Field       : IO_BANK0_GPIO21_CTRL_INOVER
3669 // Description : 0x0 -> don't invert the peri input
3670 //               0x1 -> invert the peri input
3671 //               0x2 -> drive peri input low
3672 //               0x3 -> drive peri input high
3673 #define IO_BANK0_GPIO21_CTRL_INOVER_RESET        _u(0x0)
3674 #define IO_BANK0_GPIO21_CTRL_INOVER_BITS         _u(0x00030000)
3675 #define IO_BANK0_GPIO21_CTRL_INOVER_MSB          _u(17)
3676 #define IO_BANK0_GPIO21_CTRL_INOVER_LSB          _u(16)
3677 #define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS       "RW"
3678 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0)
3679 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1)
3680 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW    _u(0x2)
3681 #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH   _u(0x3)
3682 // -----------------------------------------------------------------------------
3683 // Field       : IO_BANK0_GPIO21_CTRL_OEOVER
3684 // Description : 0x0 -> drive output enable from peripheral signal selected by
3685 //               funcsel
3686 //               0x1 -> drive output enable from inverse of peripheral signal
3687 //               selected by funcsel
3688 //               0x2 -> disable output
3689 //               0x3 -> enable output
3690 #define IO_BANK0_GPIO21_CTRL_OEOVER_RESET         _u(0x0)
3691 #define IO_BANK0_GPIO21_CTRL_OEOVER_BITS          _u(0x00003000)
3692 #define IO_BANK0_GPIO21_CTRL_OEOVER_MSB           _u(13)
3693 #define IO_BANK0_GPIO21_CTRL_OEOVER_LSB           _u(12)
3694 #define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS        "RW"
3695 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
3696 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
3697 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
3698 #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
3699 // -----------------------------------------------------------------------------
3700 // Field       : IO_BANK0_GPIO21_CTRL_OUTOVER
3701 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
3702 //               0x1 -> drive output from inverse of peripheral signal selected
3703 //               by funcsel
3704 //               0x2 -> drive output low
3705 //               0x3 -> drive output high
3706 #define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET        _u(0x0)
3707 #define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS         _u(0x00000300)
3708 #define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB          _u(9)
3709 #define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB          _u(8)
3710 #define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS       "RW"
3711 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
3712 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
3713 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
3714 #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
3715 // -----------------------------------------------------------------------------
3716 // Field       : IO_BANK0_GPIO21_CTRL_FUNCSEL
3717 // Description : 0-31 -> selects pin function according to the gpio table
3718 //               31 == NULL
3719 //               0x01 -> spi0_ss_n
3720 //               0x02 -> uart1_rx
3721 //               0x03 -> i2c0_scl
3722 //               0x04 -> pwm_b_2
3723 //               0x05 -> sio_21
3724 //               0x06 -> pio0_21
3725 //               0x07 -> pio1_21
3726 //               0x08 -> clocks_gpout_0
3727 //               0x09 -> usb_muxing_overcurr_detect
3728 //               0x1f -> null
3729 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET                            _u(0x1f)
3730 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
3731 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB                              _u(4)
3732 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB                              _u(0)
3733 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS                           "RW"
3734 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N                  _u(0x01)
3735 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX                   _u(0x02)
3736 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL                   _u(0x03)
3737 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2                    _u(0x04)
3738 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21                     _u(0x05)
3739 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21                    _u(0x06)
3740 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21                    _u(0x07)
3741 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0             _u(0x08)
3742 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
3743 #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
3744 // =============================================================================
3745 // Register    : IO_BANK0_GPIO22_STATUS
3746 // Description : GPIO status
3747 #define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0)
3748 #define IO_BANK0_GPIO22_STATUS_BITS   _u(0x050a3300)
3749 #define IO_BANK0_GPIO22_STATUS_RESET  _u(0x00000000)
3750 // -----------------------------------------------------------------------------
3751 // Field       : IO_BANK0_GPIO22_STATUS_IRQTOPROC
3752 // Description : interrupt to processors, after override is applied
3753 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET  _u(0x0)
3754 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS   _u(0x04000000)
3755 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB    _u(26)
3756 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB    _u(26)
3757 #define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO"
3758 // -----------------------------------------------------------------------------
3759 // Field       : IO_BANK0_GPIO22_STATUS_IRQFROMPAD
3760 // Description : interrupt from pad before override is applied
3761 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET  _u(0x0)
3762 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
3763 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB    _u(24)
3764 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB    _u(24)
3765 #define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO"
3766 // -----------------------------------------------------------------------------
3767 // Field       : IO_BANK0_GPIO22_STATUS_INTOPERI
3768 // Description : input signal to peripheral, after override is applied
3769 #define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET  _u(0x0)
3770 #define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS   _u(0x00080000)
3771 #define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB    _u(19)
3772 #define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB    _u(19)
3773 #define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO"
3774 // -----------------------------------------------------------------------------
3775 // Field       : IO_BANK0_GPIO22_STATUS_INFROMPAD
3776 // Description : input signal from pad, before override is applied
3777 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET  _u(0x0)
3778 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS   _u(0x00020000)
3779 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB    _u(17)
3780 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB    _u(17)
3781 #define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO"
3782 // -----------------------------------------------------------------------------
3783 // Field       : IO_BANK0_GPIO22_STATUS_OETOPAD
3784 // Description : output enable to pad after register override is applied
3785 #define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET  _u(0x0)
3786 #define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS   _u(0x00002000)
3787 #define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB    _u(13)
3788 #define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB    _u(13)
3789 #define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO"
3790 // -----------------------------------------------------------------------------
3791 // Field       : IO_BANK0_GPIO22_STATUS_OEFROMPERI
3792 // Description : output enable from selected peripheral, before register
3793 //               override is applied
3794 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET  _u(0x0)
3795 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS   _u(0x00001000)
3796 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB    _u(12)
3797 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB    _u(12)
3798 #define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO"
3799 // -----------------------------------------------------------------------------
3800 // Field       : IO_BANK0_GPIO22_STATUS_OUTTOPAD
3801 // Description : output signal to pad after register override is applied
3802 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET  _u(0x0)
3803 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS   _u(0x00000200)
3804 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB    _u(9)
3805 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB    _u(9)
3806 #define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO"
3807 // -----------------------------------------------------------------------------
3808 // Field       : IO_BANK0_GPIO22_STATUS_OUTFROMPERI
3809 // Description : output signal from selected peripheral, before register
3810 //               override is applied
3811 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET  _u(0x0)
3812 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
3813 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB    _u(8)
3814 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB    _u(8)
3815 #define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO"
3816 // =============================================================================
3817 // Register    : IO_BANK0_GPIO22_CTRL
3818 // Description : GPIO control including function select and overrides.
3819 #define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4)
3820 #define IO_BANK0_GPIO22_CTRL_BITS   _u(0x3003331f)
3821 #define IO_BANK0_GPIO22_CTRL_RESET  _u(0x0000001f)
3822 // -----------------------------------------------------------------------------
3823 // Field       : IO_BANK0_GPIO22_CTRL_IRQOVER
3824 // Description : 0x0 -> don't invert the interrupt
3825 //               0x1 -> invert the interrupt
3826 //               0x2 -> drive interrupt low
3827 //               0x3 -> drive interrupt high
3828 #define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET        _u(0x0)
3829 #define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS         _u(0x30000000)
3830 #define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB          _u(29)
3831 #define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB          _u(28)
3832 #define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS       "RW"
3833 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
3834 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
3835 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
3836 #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
3837 // -----------------------------------------------------------------------------
3838 // Field       : IO_BANK0_GPIO22_CTRL_INOVER
3839 // Description : 0x0 -> don't invert the peri input
3840 //               0x1 -> invert the peri input
3841 //               0x2 -> drive peri input low
3842 //               0x3 -> drive peri input high
3843 #define IO_BANK0_GPIO22_CTRL_INOVER_RESET        _u(0x0)
3844 #define IO_BANK0_GPIO22_CTRL_INOVER_BITS         _u(0x00030000)
3845 #define IO_BANK0_GPIO22_CTRL_INOVER_MSB          _u(17)
3846 #define IO_BANK0_GPIO22_CTRL_INOVER_LSB          _u(16)
3847 #define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS       "RW"
3848 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0)
3849 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1)
3850 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW    _u(0x2)
3851 #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH   _u(0x3)
3852 // -----------------------------------------------------------------------------
3853 // Field       : IO_BANK0_GPIO22_CTRL_OEOVER
3854 // Description : 0x0 -> drive output enable from peripheral signal selected by
3855 //               funcsel
3856 //               0x1 -> drive output enable from inverse of peripheral signal
3857 //               selected by funcsel
3858 //               0x2 -> disable output
3859 //               0x3 -> enable output
3860 #define IO_BANK0_GPIO22_CTRL_OEOVER_RESET         _u(0x0)
3861 #define IO_BANK0_GPIO22_CTRL_OEOVER_BITS          _u(0x00003000)
3862 #define IO_BANK0_GPIO22_CTRL_OEOVER_MSB           _u(13)
3863 #define IO_BANK0_GPIO22_CTRL_OEOVER_LSB           _u(12)
3864 #define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS        "RW"
3865 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
3866 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
3867 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
3868 #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
3869 // -----------------------------------------------------------------------------
3870 // Field       : IO_BANK0_GPIO22_CTRL_OUTOVER
3871 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
3872 //               0x1 -> drive output from inverse of peripheral signal selected
3873 //               by funcsel
3874 //               0x2 -> drive output low
3875 //               0x3 -> drive output high
3876 #define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET        _u(0x0)
3877 #define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS         _u(0x00000300)
3878 #define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB          _u(9)
3879 #define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB          _u(8)
3880 #define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS       "RW"
3881 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
3882 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
3883 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
3884 #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
3885 // -----------------------------------------------------------------------------
3886 // Field       : IO_BANK0_GPIO22_CTRL_FUNCSEL
3887 // Description : 0-31 -> selects pin function according to the gpio table
3888 //               31 == NULL
3889 //               0x01 -> spi0_sclk
3890 //               0x02 -> uart1_cts
3891 //               0x03 -> i2c1_sda
3892 //               0x04 -> pwm_a_3
3893 //               0x05 -> sio_22
3894 //               0x06 -> pio0_22
3895 //               0x07 -> pio1_22
3896 //               0x08 -> clocks_gpin_1
3897 //               0x09 -> usb_muxing_vbus_detect
3898 //               0x1f -> null
3899 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET                        _u(0x1f)
3900 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
3901 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB                          _u(4)
3902 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB                          _u(0)
3903 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS                       "RW"
3904 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK              _u(0x01)
3905 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS              _u(0x02)
3906 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA               _u(0x03)
3907 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3                _u(0x04)
3908 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22                 _u(0x05)
3909 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22                _u(0x06)
3910 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22                _u(0x07)
3911 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1          _u(0x08)
3912 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
3913 #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
3914 // =============================================================================
3915 // Register    : IO_BANK0_GPIO23_STATUS
3916 // Description : GPIO status
3917 #define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8)
3918 #define IO_BANK0_GPIO23_STATUS_BITS   _u(0x050a3300)
3919 #define IO_BANK0_GPIO23_STATUS_RESET  _u(0x00000000)
3920 // -----------------------------------------------------------------------------
3921 // Field       : IO_BANK0_GPIO23_STATUS_IRQTOPROC
3922 // Description : interrupt to processors, after override is applied
3923 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET  _u(0x0)
3924 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS   _u(0x04000000)
3925 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB    _u(26)
3926 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB    _u(26)
3927 #define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO"
3928 // -----------------------------------------------------------------------------
3929 // Field       : IO_BANK0_GPIO23_STATUS_IRQFROMPAD
3930 // Description : interrupt from pad before override is applied
3931 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET  _u(0x0)
3932 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
3933 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB    _u(24)
3934 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB    _u(24)
3935 #define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO"
3936 // -----------------------------------------------------------------------------
3937 // Field       : IO_BANK0_GPIO23_STATUS_INTOPERI
3938 // Description : input signal to peripheral, after override is applied
3939 #define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET  _u(0x0)
3940 #define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS   _u(0x00080000)
3941 #define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB    _u(19)
3942 #define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB    _u(19)
3943 #define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO"
3944 // -----------------------------------------------------------------------------
3945 // Field       : IO_BANK0_GPIO23_STATUS_INFROMPAD
3946 // Description : input signal from pad, before override is applied
3947 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET  _u(0x0)
3948 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS   _u(0x00020000)
3949 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB    _u(17)
3950 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB    _u(17)
3951 #define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO"
3952 // -----------------------------------------------------------------------------
3953 // Field       : IO_BANK0_GPIO23_STATUS_OETOPAD
3954 // Description : output enable to pad after register override is applied
3955 #define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET  _u(0x0)
3956 #define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS   _u(0x00002000)
3957 #define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB    _u(13)
3958 #define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB    _u(13)
3959 #define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO"
3960 // -----------------------------------------------------------------------------
3961 // Field       : IO_BANK0_GPIO23_STATUS_OEFROMPERI
3962 // Description : output enable from selected peripheral, before register
3963 //               override is applied
3964 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET  _u(0x0)
3965 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS   _u(0x00001000)
3966 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB    _u(12)
3967 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB    _u(12)
3968 #define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO"
3969 // -----------------------------------------------------------------------------
3970 // Field       : IO_BANK0_GPIO23_STATUS_OUTTOPAD
3971 // Description : output signal to pad after register override is applied
3972 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET  _u(0x0)
3973 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS   _u(0x00000200)
3974 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB    _u(9)
3975 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB    _u(9)
3976 #define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO"
3977 // -----------------------------------------------------------------------------
3978 // Field       : IO_BANK0_GPIO23_STATUS_OUTFROMPERI
3979 // Description : output signal from selected peripheral, before register
3980 //               override is applied
3981 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET  _u(0x0)
3982 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
3983 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB    _u(8)
3984 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB    _u(8)
3985 #define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO"
3986 // =============================================================================
3987 // Register    : IO_BANK0_GPIO23_CTRL
3988 // Description : GPIO control including function select and overrides.
3989 #define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc)
3990 #define IO_BANK0_GPIO23_CTRL_BITS   _u(0x3003331f)
3991 #define IO_BANK0_GPIO23_CTRL_RESET  _u(0x0000001f)
3992 // -----------------------------------------------------------------------------
3993 // Field       : IO_BANK0_GPIO23_CTRL_IRQOVER
3994 // Description : 0x0 -> don't invert the interrupt
3995 //               0x1 -> invert the interrupt
3996 //               0x2 -> drive interrupt low
3997 //               0x3 -> drive interrupt high
3998 #define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET        _u(0x0)
3999 #define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS         _u(0x30000000)
4000 #define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB          _u(29)
4001 #define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB          _u(28)
4002 #define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS       "RW"
4003 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
4004 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
4005 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
4006 #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
4007 // -----------------------------------------------------------------------------
4008 // Field       : IO_BANK0_GPIO23_CTRL_INOVER
4009 // Description : 0x0 -> don't invert the peri input
4010 //               0x1 -> invert the peri input
4011 //               0x2 -> drive peri input low
4012 //               0x3 -> drive peri input high
4013 #define IO_BANK0_GPIO23_CTRL_INOVER_RESET        _u(0x0)
4014 #define IO_BANK0_GPIO23_CTRL_INOVER_BITS         _u(0x00030000)
4015 #define IO_BANK0_GPIO23_CTRL_INOVER_MSB          _u(17)
4016 #define IO_BANK0_GPIO23_CTRL_INOVER_LSB          _u(16)
4017 #define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS       "RW"
4018 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0)
4019 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1)
4020 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW    _u(0x2)
4021 #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH   _u(0x3)
4022 // -----------------------------------------------------------------------------
4023 // Field       : IO_BANK0_GPIO23_CTRL_OEOVER
4024 // Description : 0x0 -> drive output enable from peripheral signal selected by
4025 //               funcsel
4026 //               0x1 -> drive output enable from inverse of peripheral signal
4027 //               selected by funcsel
4028 //               0x2 -> disable output
4029 //               0x3 -> enable output
4030 #define IO_BANK0_GPIO23_CTRL_OEOVER_RESET         _u(0x0)
4031 #define IO_BANK0_GPIO23_CTRL_OEOVER_BITS          _u(0x00003000)
4032 #define IO_BANK0_GPIO23_CTRL_OEOVER_MSB           _u(13)
4033 #define IO_BANK0_GPIO23_CTRL_OEOVER_LSB           _u(12)
4034 #define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS        "RW"
4035 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
4036 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
4037 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
4038 #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
4039 // -----------------------------------------------------------------------------
4040 // Field       : IO_BANK0_GPIO23_CTRL_OUTOVER
4041 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
4042 //               0x1 -> drive output from inverse of peripheral signal selected
4043 //               by funcsel
4044 //               0x2 -> drive output low
4045 //               0x3 -> drive output high
4046 #define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET        _u(0x0)
4047 #define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS         _u(0x00000300)
4048 #define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB          _u(9)
4049 #define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB          _u(8)
4050 #define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS       "RW"
4051 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
4052 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
4053 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
4054 #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
4055 // -----------------------------------------------------------------------------
4056 // Field       : IO_BANK0_GPIO23_CTRL_FUNCSEL
4057 // Description : 0-31 -> selects pin function according to the gpio table
4058 //               31 == NULL
4059 //               0x01 -> spi0_tx
4060 //               0x02 -> uart1_rts
4061 //               0x03 -> i2c1_scl
4062 //               0x04 -> pwm_b_3
4063 //               0x05 -> sio_23
4064 //               0x06 -> pio0_23
4065 //               0x07 -> pio1_23
4066 //               0x08 -> clocks_gpout_1
4067 //               0x09 -> usb_muxing_vbus_en
4068 //               0x1f -> null
4069 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET                    _u(0x1f)
4070 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
4071 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB                      _u(4)
4072 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB                      _u(0)
4073 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS                   "RW"
4074 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX            _u(0x01)
4075 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS          _u(0x02)
4076 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL           _u(0x03)
4077 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3            _u(0x04)
4078 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23             _u(0x05)
4079 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23            _u(0x06)
4080 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23            _u(0x07)
4081 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1     _u(0x08)
4082 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
4083 #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
4084 // =============================================================================
4085 // Register    : IO_BANK0_GPIO24_STATUS
4086 // Description : GPIO status
4087 #define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0)
4088 #define IO_BANK0_GPIO24_STATUS_BITS   _u(0x050a3300)
4089 #define IO_BANK0_GPIO24_STATUS_RESET  _u(0x00000000)
4090 // -----------------------------------------------------------------------------
4091 // Field       : IO_BANK0_GPIO24_STATUS_IRQTOPROC
4092 // Description : interrupt to processors, after override is applied
4093 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET  _u(0x0)
4094 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS   _u(0x04000000)
4095 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB    _u(26)
4096 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB    _u(26)
4097 #define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO"
4098 // -----------------------------------------------------------------------------
4099 // Field       : IO_BANK0_GPIO24_STATUS_IRQFROMPAD
4100 // Description : interrupt from pad before override is applied
4101 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET  _u(0x0)
4102 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
4103 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB    _u(24)
4104 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB    _u(24)
4105 #define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO"
4106 // -----------------------------------------------------------------------------
4107 // Field       : IO_BANK0_GPIO24_STATUS_INTOPERI
4108 // Description : input signal to peripheral, after override is applied
4109 #define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET  _u(0x0)
4110 #define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS   _u(0x00080000)
4111 #define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB    _u(19)
4112 #define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB    _u(19)
4113 #define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO"
4114 // -----------------------------------------------------------------------------
4115 // Field       : IO_BANK0_GPIO24_STATUS_INFROMPAD
4116 // Description : input signal from pad, before override is applied
4117 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET  _u(0x0)
4118 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS   _u(0x00020000)
4119 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB    _u(17)
4120 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB    _u(17)
4121 #define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO"
4122 // -----------------------------------------------------------------------------
4123 // Field       : IO_BANK0_GPIO24_STATUS_OETOPAD
4124 // Description : output enable to pad after register override is applied
4125 #define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET  _u(0x0)
4126 #define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS   _u(0x00002000)
4127 #define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB    _u(13)
4128 #define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB    _u(13)
4129 #define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO"
4130 // -----------------------------------------------------------------------------
4131 // Field       : IO_BANK0_GPIO24_STATUS_OEFROMPERI
4132 // Description : output enable from selected peripheral, before register
4133 //               override is applied
4134 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET  _u(0x0)
4135 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS   _u(0x00001000)
4136 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB    _u(12)
4137 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB    _u(12)
4138 #define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO"
4139 // -----------------------------------------------------------------------------
4140 // Field       : IO_BANK0_GPIO24_STATUS_OUTTOPAD
4141 // Description : output signal to pad after register override is applied
4142 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET  _u(0x0)
4143 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS   _u(0x00000200)
4144 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB    _u(9)
4145 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB    _u(9)
4146 #define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO"
4147 // -----------------------------------------------------------------------------
4148 // Field       : IO_BANK0_GPIO24_STATUS_OUTFROMPERI
4149 // Description : output signal from selected peripheral, before register
4150 //               override is applied
4151 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET  _u(0x0)
4152 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
4153 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB    _u(8)
4154 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB    _u(8)
4155 #define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO"
4156 // =============================================================================
4157 // Register    : IO_BANK0_GPIO24_CTRL
4158 // Description : GPIO control including function select and overrides.
4159 #define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4)
4160 #define IO_BANK0_GPIO24_CTRL_BITS   _u(0x3003331f)
4161 #define IO_BANK0_GPIO24_CTRL_RESET  _u(0x0000001f)
4162 // -----------------------------------------------------------------------------
4163 // Field       : IO_BANK0_GPIO24_CTRL_IRQOVER
4164 // Description : 0x0 -> don't invert the interrupt
4165 //               0x1 -> invert the interrupt
4166 //               0x2 -> drive interrupt low
4167 //               0x3 -> drive interrupt high
4168 #define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET        _u(0x0)
4169 #define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS         _u(0x30000000)
4170 #define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB          _u(29)
4171 #define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB          _u(28)
4172 #define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS       "RW"
4173 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
4174 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
4175 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
4176 #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
4177 // -----------------------------------------------------------------------------
4178 // Field       : IO_BANK0_GPIO24_CTRL_INOVER
4179 // Description : 0x0 -> don't invert the peri input
4180 //               0x1 -> invert the peri input
4181 //               0x2 -> drive peri input low
4182 //               0x3 -> drive peri input high
4183 #define IO_BANK0_GPIO24_CTRL_INOVER_RESET        _u(0x0)
4184 #define IO_BANK0_GPIO24_CTRL_INOVER_BITS         _u(0x00030000)
4185 #define IO_BANK0_GPIO24_CTRL_INOVER_MSB          _u(17)
4186 #define IO_BANK0_GPIO24_CTRL_INOVER_LSB          _u(16)
4187 #define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS       "RW"
4188 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0)
4189 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1)
4190 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW    _u(0x2)
4191 #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH   _u(0x3)
4192 // -----------------------------------------------------------------------------
4193 // Field       : IO_BANK0_GPIO24_CTRL_OEOVER
4194 // Description : 0x0 -> drive output enable from peripheral signal selected by
4195 //               funcsel
4196 //               0x1 -> drive output enable from inverse of peripheral signal
4197 //               selected by funcsel
4198 //               0x2 -> disable output
4199 //               0x3 -> enable output
4200 #define IO_BANK0_GPIO24_CTRL_OEOVER_RESET         _u(0x0)
4201 #define IO_BANK0_GPIO24_CTRL_OEOVER_BITS          _u(0x00003000)
4202 #define IO_BANK0_GPIO24_CTRL_OEOVER_MSB           _u(13)
4203 #define IO_BANK0_GPIO24_CTRL_OEOVER_LSB           _u(12)
4204 #define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS        "RW"
4205 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
4206 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
4207 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
4208 #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
4209 // -----------------------------------------------------------------------------
4210 // Field       : IO_BANK0_GPIO24_CTRL_OUTOVER
4211 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
4212 //               0x1 -> drive output from inverse of peripheral signal selected
4213 //               by funcsel
4214 //               0x2 -> drive output low
4215 //               0x3 -> drive output high
4216 #define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET        _u(0x0)
4217 #define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS         _u(0x00000300)
4218 #define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB          _u(9)
4219 #define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB          _u(8)
4220 #define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS       "RW"
4221 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
4222 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
4223 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
4224 #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
4225 // -----------------------------------------------------------------------------
4226 // Field       : IO_BANK0_GPIO24_CTRL_FUNCSEL
4227 // Description : 0-31 -> selects pin function according to the gpio table
4228 //               31 == NULL
4229 //               0x01 -> spi1_rx
4230 //               0x02 -> uart1_tx
4231 //               0x03 -> i2c0_sda
4232 //               0x04 -> pwm_a_4
4233 //               0x05 -> sio_24
4234 //               0x06 -> pio0_24
4235 //               0x07 -> pio1_24
4236 //               0x08 -> clocks_gpout_2
4237 //               0x09 -> usb_muxing_overcurr_detect
4238 //               0x1f -> null
4239 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET                            _u(0x1f)
4240 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
4241 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB                              _u(4)
4242 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB                              _u(0)
4243 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS                           "RW"
4244 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX                    _u(0x01)
4245 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX                   _u(0x02)
4246 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA                   _u(0x03)
4247 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4                    _u(0x04)
4248 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24                     _u(0x05)
4249 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24                    _u(0x06)
4250 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24                    _u(0x07)
4251 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2             _u(0x08)
4252 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
4253 #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
4254 // =============================================================================
4255 // Register    : IO_BANK0_GPIO25_STATUS
4256 // Description : GPIO status
4257 #define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8)
4258 #define IO_BANK0_GPIO25_STATUS_BITS   _u(0x050a3300)
4259 #define IO_BANK0_GPIO25_STATUS_RESET  _u(0x00000000)
4260 // -----------------------------------------------------------------------------
4261 // Field       : IO_BANK0_GPIO25_STATUS_IRQTOPROC
4262 // Description : interrupt to processors, after override is applied
4263 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET  _u(0x0)
4264 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS   _u(0x04000000)
4265 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB    _u(26)
4266 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB    _u(26)
4267 #define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO"
4268 // -----------------------------------------------------------------------------
4269 // Field       : IO_BANK0_GPIO25_STATUS_IRQFROMPAD
4270 // Description : interrupt from pad before override is applied
4271 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET  _u(0x0)
4272 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
4273 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB    _u(24)
4274 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB    _u(24)
4275 #define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO"
4276 // -----------------------------------------------------------------------------
4277 // Field       : IO_BANK0_GPIO25_STATUS_INTOPERI
4278 // Description : input signal to peripheral, after override is applied
4279 #define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET  _u(0x0)
4280 #define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS   _u(0x00080000)
4281 #define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB    _u(19)
4282 #define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB    _u(19)
4283 #define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO"
4284 // -----------------------------------------------------------------------------
4285 // Field       : IO_BANK0_GPIO25_STATUS_INFROMPAD
4286 // Description : input signal from pad, before override is applied
4287 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET  _u(0x0)
4288 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS   _u(0x00020000)
4289 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB    _u(17)
4290 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB    _u(17)
4291 #define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO"
4292 // -----------------------------------------------------------------------------
4293 // Field       : IO_BANK0_GPIO25_STATUS_OETOPAD
4294 // Description : output enable to pad after register override is applied
4295 #define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET  _u(0x0)
4296 #define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS   _u(0x00002000)
4297 #define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB    _u(13)
4298 #define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB    _u(13)
4299 #define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO"
4300 // -----------------------------------------------------------------------------
4301 // Field       : IO_BANK0_GPIO25_STATUS_OEFROMPERI
4302 // Description : output enable from selected peripheral, before register
4303 //               override is applied
4304 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET  _u(0x0)
4305 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS   _u(0x00001000)
4306 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB    _u(12)
4307 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB    _u(12)
4308 #define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO"
4309 // -----------------------------------------------------------------------------
4310 // Field       : IO_BANK0_GPIO25_STATUS_OUTTOPAD
4311 // Description : output signal to pad after register override is applied
4312 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET  _u(0x0)
4313 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS   _u(0x00000200)
4314 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB    _u(9)
4315 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB    _u(9)
4316 #define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO"
4317 // -----------------------------------------------------------------------------
4318 // Field       : IO_BANK0_GPIO25_STATUS_OUTFROMPERI
4319 // Description : output signal from selected peripheral, before register
4320 //               override is applied
4321 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET  _u(0x0)
4322 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
4323 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB    _u(8)
4324 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB    _u(8)
4325 #define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO"
4326 // =============================================================================
4327 // Register    : IO_BANK0_GPIO25_CTRL
4328 // Description : GPIO control including function select and overrides.
4329 #define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc)
4330 #define IO_BANK0_GPIO25_CTRL_BITS   _u(0x3003331f)
4331 #define IO_BANK0_GPIO25_CTRL_RESET  _u(0x0000001f)
4332 // -----------------------------------------------------------------------------
4333 // Field       : IO_BANK0_GPIO25_CTRL_IRQOVER
4334 // Description : 0x0 -> don't invert the interrupt
4335 //               0x1 -> invert the interrupt
4336 //               0x2 -> drive interrupt low
4337 //               0x3 -> drive interrupt high
4338 #define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET        _u(0x0)
4339 #define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS         _u(0x30000000)
4340 #define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB          _u(29)
4341 #define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB          _u(28)
4342 #define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS       "RW"
4343 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
4344 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
4345 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
4346 #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
4347 // -----------------------------------------------------------------------------
4348 // Field       : IO_BANK0_GPIO25_CTRL_INOVER
4349 // Description : 0x0 -> don't invert the peri input
4350 //               0x1 -> invert the peri input
4351 //               0x2 -> drive peri input low
4352 //               0x3 -> drive peri input high
4353 #define IO_BANK0_GPIO25_CTRL_INOVER_RESET        _u(0x0)
4354 #define IO_BANK0_GPIO25_CTRL_INOVER_BITS         _u(0x00030000)
4355 #define IO_BANK0_GPIO25_CTRL_INOVER_MSB          _u(17)
4356 #define IO_BANK0_GPIO25_CTRL_INOVER_LSB          _u(16)
4357 #define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS       "RW"
4358 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0)
4359 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1)
4360 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW    _u(0x2)
4361 #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH   _u(0x3)
4362 // -----------------------------------------------------------------------------
4363 // Field       : IO_BANK0_GPIO25_CTRL_OEOVER
4364 // Description : 0x0 -> drive output enable from peripheral signal selected by
4365 //               funcsel
4366 //               0x1 -> drive output enable from inverse of peripheral signal
4367 //               selected by funcsel
4368 //               0x2 -> disable output
4369 //               0x3 -> enable output
4370 #define IO_BANK0_GPIO25_CTRL_OEOVER_RESET         _u(0x0)
4371 #define IO_BANK0_GPIO25_CTRL_OEOVER_BITS          _u(0x00003000)
4372 #define IO_BANK0_GPIO25_CTRL_OEOVER_MSB           _u(13)
4373 #define IO_BANK0_GPIO25_CTRL_OEOVER_LSB           _u(12)
4374 #define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS        "RW"
4375 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
4376 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
4377 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
4378 #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
4379 // -----------------------------------------------------------------------------
4380 // Field       : IO_BANK0_GPIO25_CTRL_OUTOVER
4381 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
4382 //               0x1 -> drive output from inverse of peripheral signal selected
4383 //               by funcsel
4384 //               0x2 -> drive output low
4385 //               0x3 -> drive output high
4386 #define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET        _u(0x0)
4387 #define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS         _u(0x00000300)
4388 #define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB          _u(9)
4389 #define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB          _u(8)
4390 #define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS       "RW"
4391 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
4392 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
4393 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
4394 #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
4395 // -----------------------------------------------------------------------------
4396 // Field       : IO_BANK0_GPIO25_CTRL_FUNCSEL
4397 // Description : 0-31 -> selects pin function according to the gpio table
4398 //               31 == NULL
4399 //               0x01 -> spi1_ss_n
4400 //               0x02 -> uart1_rx
4401 //               0x03 -> i2c0_scl
4402 //               0x04 -> pwm_b_4
4403 //               0x05 -> sio_25
4404 //               0x06 -> pio0_25
4405 //               0x07 -> pio1_25
4406 //               0x08 -> clocks_gpout_3
4407 //               0x09 -> usb_muxing_vbus_detect
4408 //               0x1f -> null
4409 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET                        _u(0x1f)
4410 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
4411 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB                          _u(4)
4412 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB                          _u(0)
4413 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS                       "RW"
4414 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N              _u(0x01)
4415 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX               _u(0x02)
4416 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL               _u(0x03)
4417 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4                _u(0x04)
4418 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25                 _u(0x05)
4419 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25                _u(0x06)
4420 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25                _u(0x07)
4421 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3         _u(0x08)
4422 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
4423 #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
4424 // =============================================================================
4425 // Register    : IO_BANK0_GPIO26_STATUS
4426 // Description : GPIO status
4427 #define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0)
4428 #define IO_BANK0_GPIO26_STATUS_BITS   _u(0x050a3300)
4429 #define IO_BANK0_GPIO26_STATUS_RESET  _u(0x00000000)
4430 // -----------------------------------------------------------------------------
4431 // Field       : IO_BANK0_GPIO26_STATUS_IRQTOPROC
4432 // Description : interrupt to processors, after override is applied
4433 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET  _u(0x0)
4434 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS   _u(0x04000000)
4435 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB    _u(26)
4436 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB    _u(26)
4437 #define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO"
4438 // -----------------------------------------------------------------------------
4439 // Field       : IO_BANK0_GPIO26_STATUS_IRQFROMPAD
4440 // Description : interrupt from pad before override is applied
4441 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET  _u(0x0)
4442 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
4443 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB    _u(24)
4444 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB    _u(24)
4445 #define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO"
4446 // -----------------------------------------------------------------------------
4447 // Field       : IO_BANK0_GPIO26_STATUS_INTOPERI
4448 // Description : input signal to peripheral, after override is applied
4449 #define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET  _u(0x0)
4450 #define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS   _u(0x00080000)
4451 #define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB    _u(19)
4452 #define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB    _u(19)
4453 #define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO"
4454 // -----------------------------------------------------------------------------
4455 // Field       : IO_BANK0_GPIO26_STATUS_INFROMPAD
4456 // Description : input signal from pad, before override is applied
4457 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET  _u(0x0)
4458 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS   _u(0x00020000)
4459 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB    _u(17)
4460 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB    _u(17)
4461 #define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO"
4462 // -----------------------------------------------------------------------------
4463 // Field       : IO_BANK0_GPIO26_STATUS_OETOPAD
4464 // Description : output enable to pad after register override is applied
4465 #define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET  _u(0x0)
4466 #define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS   _u(0x00002000)
4467 #define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB    _u(13)
4468 #define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB    _u(13)
4469 #define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO"
4470 // -----------------------------------------------------------------------------
4471 // Field       : IO_BANK0_GPIO26_STATUS_OEFROMPERI
4472 // Description : output enable from selected peripheral, before register
4473 //               override is applied
4474 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET  _u(0x0)
4475 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS   _u(0x00001000)
4476 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB    _u(12)
4477 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB    _u(12)
4478 #define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO"
4479 // -----------------------------------------------------------------------------
4480 // Field       : IO_BANK0_GPIO26_STATUS_OUTTOPAD
4481 // Description : output signal to pad after register override is applied
4482 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET  _u(0x0)
4483 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS   _u(0x00000200)
4484 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB    _u(9)
4485 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB    _u(9)
4486 #define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO"
4487 // -----------------------------------------------------------------------------
4488 // Field       : IO_BANK0_GPIO26_STATUS_OUTFROMPERI
4489 // Description : output signal from selected peripheral, before register
4490 //               override is applied
4491 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET  _u(0x0)
4492 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
4493 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB    _u(8)
4494 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB    _u(8)
4495 #define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO"
4496 // =============================================================================
4497 // Register    : IO_BANK0_GPIO26_CTRL
4498 // Description : GPIO control including function select and overrides.
4499 #define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4)
4500 #define IO_BANK0_GPIO26_CTRL_BITS   _u(0x3003331f)
4501 #define IO_BANK0_GPIO26_CTRL_RESET  _u(0x0000001f)
4502 // -----------------------------------------------------------------------------
4503 // Field       : IO_BANK0_GPIO26_CTRL_IRQOVER
4504 // Description : 0x0 -> don't invert the interrupt
4505 //               0x1 -> invert the interrupt
4506 //               0x2 -> drive interrupt low
4507 //               0x3 -> drive interrupt high
4508 #define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET        _u(0x0)
4509 #define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS         _u(0x30000000)
4510 #define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB          _u(29)
4511 #define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB          _u(28)
4512 #define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS       "RW"
4513 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
4514 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
4515 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
4516 #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
4517 // -----------------------------------------------------------------------------
4518 // Field       : IO_BANK0_GPIO26_CTRL_INOVER
4519 // Description : 0x0 -> don't invert the peri input
4520 //               0x1 -> invert the peri input
4521 //               0x2 -> drive peri input low
4522 //               0x3 -> drive peri input high
4523 #define IO_BANK0_GPIO26_CTRL_INOVER_RESET        _u(0x0)
4524 #define IO_BANK0_GPIO26_CTRL_INOVER_BITS         _u(0x00030000)
4525 #define IO_BANK0_GPIO26_CTRL_INOVER_MSB          _u(17)
4526 #define IO_BANK0_GPIO26_CTRL_INOVER_LSB          _u(16)
4527 #define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS       "RW"
4528 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0)
4529 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1)
4530 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW    _u(0x2)
4531 #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH   _u(0x3)
4532 // -----------------------------------------------------------------------------
4533 // Field       : IO_BANK0_GPIO26_CTRL_OEOVER
4534 // Description : 0x0 -> drive output enable from peripheral signal selected by
4535 //               funcsel
4536 //               0x1 -> drive output enable from inverse of peripheral signal
4537 //               selected by funcsel
4538 //               0x2 -> disable output
4539 //               0x3 -> enable output
4540 #define IO_BANK0_GPIO26_CTRL_OEOVER_RESET         _u(0x0)
4541 #define IO_BANK0_GPIO26_CTRL_OEOVER_BITS          _u(0x00003000)
4542 #define IO_BANK0_GPIO26_CTRL_OEOVER_MSB           _u(13)
4543 #define IO_BANK0_GPIO26_CTRL_OEOVER_LSB           _u(12)
4544 #define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS        "RW"
4545 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
4546 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
4547 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
4548 #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
4549 // -----------------------------------------------------------------------------
4550 // Field       : IO_BANK0_GPIO26_CTRL_OUTOVER
4551 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
4552 //               0x1 -> drive output from inverse of peripheral signal selected
4553 //               by funcsel
4554 //               0x2 -> drive output low
4555 //               0x3 -> drive output high
4556 #define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET        _u(0x0)
4557 #define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS         _u(0x00000300)
4558 #define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB          _u(9)
4559 #define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB          _u(8)
4560 #define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS       "RW"
4561 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
4562 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
4563 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
4564 #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
4565 // -----------------------------------------------------------------------------
4566 // Field       : IO_BANK0_GPIO26_CTRL_FUNCSEL
4567 // Description : 0-31 -> selects pin function according to the gpio table
4568 //               31 == NULL
4569 //               0x01 -> spi1_sclk
4570 //               0x02 -> uart1_cts
4571 //               0x03 -> i2c1_sda
4572 //               0x04 -> pwm_a_5
4573 //               0x05 -> sio_26
4574 //               0x06 -> pio0_26
4575 //               0x07 -> pio1_26
4576 //               0x09 -> usb_muxing_vbus_en
4577 //               0x1f -> null
4578 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET                    _u(0x1f)
4579 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
4580 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB                      _u(4)
4581 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB                      _u(0)
4582 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS                   "RW"
4583 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK          _u(0x01)
4584 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS          _u(0x02)
4585 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA           _u(0x03)
4586 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5            _u(0x04)
4587 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26             _u(0x05)
4588 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26            _u(0x06)
4589 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26            _u(0x07)
4590 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
4591 #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
4592 // =============================================================================
4593 // Register    : IO_BANK0_GPIO27_STATUS
4594 // Description : GPIO status
4595 #define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8)
4596 #define IO_BANK0_GPIO27_STATUS_BITS   _u(0x050a3300)
4597 #define IO_BANK0_GPIO27_STATUS_RESET  _u(0x00000000)
4598 // -----------------------------------------------------------------------------
4599 // Field       : IO_BANK0_GPIO27_STATUS_IRQTOPROC
4600 // Description : interrupt to processors, after override is applied
4601 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET  _u(0x0)
4602 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS   _u(0x04000000)
4603 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB    _u(26)
4604 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB    _u(26)
4605 #define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO"
4606 // -----------------------------------------------------------------------------
4607 // Field       : IO_BANK0_GPIO27_STATUS_IRQFROMPAD
4608 // Description : interrupt from pad before override is applied
4609 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET  _u(0x0)
4610 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
4611 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB    _u(24)
4612 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB    _u(24)
4613 #define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO"
4614 // -----------------------------------------------------------------------------
4615 // Field       : IO_BANK0_GPIO27_STATUS_INTOPERI
4616 // Description : input signal to peripheral, after override is applied
4617 #define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET  _u(0x0)
4618 #define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS   _u(0x00080000)
4619 #define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB    _u(19)
4620 #define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB    _u(19)
4621 #define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO"
4622 // -----------------------------------------------------------------------------
4623 // Field       : IO_BANK0_GPIO27_STATUS_INFROMPAD
4624 // Description : input signal from pad, before override is applied
4625 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET  _u(0x0)
4626 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS   _u(0x00020000)
4627 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB    _u(17)
4628 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB    _u(17)
4629 #define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO"
4630 // -----------------------------------------------------------------------------
4631 // Field       : IO_BANK0_GPIO27_STATUS_OETOPAD
4632 // Description : output enable to pad after register override is applied
4633 #define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET  _u(0x0)
4634 #define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS   _u(0x00002000)
4635 #define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB    _u(13)
4636 #define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB    _u(13)
4637 #define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO"
4638 // -----------------------------------------------------------------------------
4639 // Field       : IO_BANK0_GPIO27_STATUS_OEFROMPERI
4640 // Description : output enable from selected peripheral, before register
4641 //               override is applied
4642 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET  _u(0x0)
4643 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS   _u(0x00001000)
4644 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB    _u(12)
4645 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB    _u(12)
4646 #define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO"
4647 // -----------------------------------------------------------------------------
4648 // Field       : IO_BANK0_GPIO27_STATUS_OUTTOPAD
4649 // Description : output signal to pad after register override is applied
4650 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET  _u(0x0)
4651 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS   _u(0x00000200)
4652 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB    _u(9)
4653 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB    _u(9)
4654 #define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO"
4655 // -----------------------------------------------------------------------------
4656 // Field       : IO_BANK0_GPIO27_STATUS_OUTFROMPERI
4657 // Description : output signal from selected peripheral, before register
4658 //               override is applied
4659 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET  _u(0x0)
4660 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
4661 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB    _u(8)
4662 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB    _u(8)
4663 #define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO"
4664 // =============================================================================
4665 // Register    : IO_BANK0_GPIO27_CTRL
4666 // Description : GPIO control including function select and overrides.
4667 #define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc)
4668 #define IO_BANK0_GPIO27_CTRL_BITS   _u(0x3003331f)
4669 #define IO_BANK0_GPIO27_CTRL_RESET  _u(0x0000001f)
4670 // -----------------------------------------------------------------------------
4671 // Field       : IO_BANK0_GPIO27_CTRL_IRQOVER
4672 // Description : 0x0 -> don't invert the interrupt
4673 //               0x1 -> invert the interrupt
4674 //               0x2 -> drive interrupt low
4675 //               0x3 -> drive interrupt high
4676 #define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET        _u(0x0)
4677 #define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS         _u(0x30000000)
4678 #define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB          _u(29)
4679 #define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB          _u(28)
4680 #define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS       "RW"
4681 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
4682 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
4683 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
4684 #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
4685 // -----------------------------------------------------------------------------
4686 // Field       : IO_BANK0_GPIO27_CTRL_INOVER
4687 // Description : 0x0 -> don't invert the peri input
4688 //               0x1 -> invert the peri input
4689 //               0x2 -> drive peri input low
4690 //               0x3 -> drive peri input high
4691 #define IO_BANK0_GPIO27_CTRL_INOVER_RESET        _u(0x0)
4692 #define IO_BANK0_GPIO27_CTRL_INOVER_BITS         _u(0x00030000)
4693 #define IO_BANK0_GPIO27_CTRL_INOVER_MSB          _u(17)
4694 #define IO_BANK0_GPIO27_CTRL_INOVER_LSB          _u(16)
4695 #define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS       "RW"
4696 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0)
4697 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1)
4698 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW    _u(0x2)
4699 #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH   _u(0x3)
4700 // -----------------------------------------------------------------------------
4701 // Field       : IO_BANK0_GPIO27_CTRL_OEOVER
4702 // Description : 0x0 -> drive output enable from peripheral signal selected by
4703 //               funcsel
4704 //               0x1 -> drive output enable from inverse of peripheral signal
4705 //               selected by funcsel
4706 //               0x2 -> disable output
4707 //               0x3 -> enable output
4708 #define IO_BANK0_GPIO27_CTRL_OEOVER_RESET         _u(0x0)
4709 #define IO_BANK0_GPIO27_CTRL_OEOVER_BITS          _u(0x00003000)
4710 #define IO_BANK0_GPIO27_CTRL_OEOVER_MSB           _u(13)
4711 #define IO_BANK0_GPIO27_CTRL_OEOVER_LSB           _u(12)
4712 #define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS        "RW"
4713 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
4714 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
4715 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
4716 #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
4717 // -----------------------------------------------------------------------------
4718 // Field       : IO_BANK0_GPIO27_CTRL_OUTOVER
4719 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
4720 //               0x1 -> drive output from inverse of peripheral signal selected
4721 //               by funcsel
4722 //               0x2 -> drive output low
4723 //               0x3 -> drive output high
4724 #define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET        _u(0x0)
4725 #define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS         _u(0x00000300)
4726 #define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB          _u(9)
4727 #define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB          _u(8)
4728 #define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS       "RW"
4729 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
4730 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
4731 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
4732 #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
4733 // -----------------------------------------------------------------------------
4734 // Field       : IO_BANK0_GPIO27_CTRL_FUNCSEL
4735 // Description : 0-31 -> selects pin function according to the gpio table
4736 //               31 == NULL
4737 //               0x01 -> spi1_tx
4738 //               0x02 -> uart1_rts
4739 //               0x03 -> i2c1_scl
4740 //               0x04 -> pwm_b_5
4741 //               0x05 -> sio_27
4742 //               0x06 -> pio0_27
4743 //               0x07 -> pio1_27
4744 //               0x09 -> usb_muxing_overcurr_detect
4745 //               0x1f -> null
4746 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET                            _u(0x1f)
4747 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS                             _u(0x0000001f)
4748 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB                              _u(4)
4749 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB                              _u(0)
4750 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS                           "RW"
4751 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX                    _u(0x01)
4752 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS                  _u(0x02)
4753 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL                   _u(0x03)
4754 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5                    _u(0x04)
4755 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27                     _u(0x05)
4756 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27                    _u(0x06)
4757 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27                    _u(0x07)
4758 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
4759 #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL                       _u(0x1f)
4760 // =============================================================================
4761 // Register    : IO_BANK0_GPIO28_STATUS
4762 // Description : GPIO status
4763 #define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0)
4764 #define IO_BANK0_GPIO28_STATUS_BITS   _u(0x050a3300)
4765 #define IO_BANK0_GPIO28_STATUS_RESET  _u(0x00000000)
4766 // -----------------------------------------------------------------------------
4767 // Field       : IO_BANK0_GPIO28_STATUS_IRQTOPROC
4768 // Description : interrupt to processors, after override is applied
4769 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET  _u(0x0)
4770 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS   _u(0x04000000)
4771 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB    _u(26)
4772 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB    _u(26)
4773 #define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO"
4774 // -----------------------------------------------------------------------------
4775 // Field       : IO_BANK0_GPIO28_STATUS_IRQFROMPAD
4776 // Description : interrupt from pad before override is applied
4777 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET  _u(0x0)
4778 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
4779 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB    _u(24)
4780 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB    _u(24)
4781 #define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO"
4782 // -----------------------------------------------------------------------------
4783 // Field       : IO_BANK0_GPIO28_STATUS_INTOPERI
4784 // Description : input signal to peripheral, after override is applied
4785 #define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET  _u(0x0)
4786 #define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS   _u(0x00080000)
4787 #define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB    _u(19)
4788 #define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB    _u(19)
4789 #define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO"
4790 // -----------------------------------------------------------------------------
4791 // Field       : IO_BANK0_GPIO28_STATUS_INFROMPAD
4792 // Description : input signal from pad, before override is applied
4793 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET  _u(0x0)
4794 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS   _u(0x00020000)
4795 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB    _u(17)
4796 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB    _u(17)
4797 #define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO"
4798 // -----------------------------------------------------------------------------
4799 // Field       : IO_BANK0_GPIO28_STATUS_OETOPAD
4800 // Description : output enable to pad after register override is applied
4801 #define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET  _u(0x0)
4802 #define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS   _u(0x00002000)
4803 #define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB    _u(13)
4804 #define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB    _u(13)
4805 #define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO"
4806 // -----------------------------------------------------------------------------
4807 // Field       : IO_BANK0_GPIO28_STATUS_OEFROMPERI
4808 // Description : output enable from selected peripheral, before register
4809 //               override is applied
4810 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET  _u(0x0)
4811 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS   _u(0x00001000)
4812 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB    _u(12)
4813 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB    _u(12)
4814 #define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO"
4815 // -----------------------------------------------------------------------------
4816 // Field       : IO_BANK0_GPIO28_STATUS_OUTTOPAD
4817 // Description : output signal to pad after register override is applied
4818 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET  _u(0x0)
4819 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS   _u(0x00000200)
4820 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB    _u(9)
4821 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB    _u(9)
4822 #define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO"
4823 // -----------------------------------------------------------------------------
4824 // Field       : IO_BANK0_GPIO28_STATUS_OUTFROMPERI
4825 // Description : output signal from selected peripheral, before register
4826 //               override is applied
4827 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET  _u(0x0)
4828 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
4829 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB    _u(8)
4830 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB    _u(8)
4831 #define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO"
4832 // =============================================================================
4833 // Register    : IO_BANK0_GPIO28_CTRL
4834 // Description : GPIO control including function select and overrides.
4835 #define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4)
4836 #define IO_BANK0_GPIO28_CTRL_BITS   _u(0x3003331f)
4837 #define IO_BANK0_GPIO28_CTRL_RESET  _u(0x0000001f)
4838 // -----------------------------------------------------------------------------
4839 // Field       : IO_BANK0_GPIO28_CTRL_IRQOVER
4840 // Description : 0x0 -> don't invert the interrupt
4841 //               0x1 -> invert the interrupt
4842 //               0x2 -> drive interrupt low
4843 //               0x3 -> drive interrupt high
4844 #define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET        _u(0x0)
4845 #define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS         _u(0x30000000)
4846 #define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB          _u(29)
4847 #define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB          _u(28)
4848 #define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS       "RW"
4849 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
4850 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
4851 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
4852 #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
4853 // -----------------------------------------------------------------------------
4854 // Field       : IO_BANK0_GPIO28_CTRL_INOVER
4855 // Description : 0x0 -> don't invert the peri input
4856 //               0x1 -> invert the peri input
4857 //               0x2 -> drive peri input low
4858 //               0x3 -> drive peri input high
4859 #define IO_BANK0_GPIO28_CTRL_INOVER_RESET        _u(0x0)
4860 #define IO_BANK0_GPIO28_CTRL_INOVER_BITS         _u(0x00030000)
4861 #define IO_BANK0_GPIO28_CTRL_INOVER_MSB          _u(17)
4862 #define IO_BANK0_GPIO28_CTRL_INOVER_LSB          _u(16)
4863 #define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS       "RW"
4864 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0)
4865 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1)
4866 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW    _u(0x2)
4867 #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH   _u(0x3)
4868 // -----------------------------------------------------------------------------
4869 // Field       : IO_BANK0_GPIO28_CTRL_OEOVER
4870 // Description : 0x0 -> drive output enable from peripheral signal selected by
4871 //               funcsel
4872 //               0x1 -> drive output enable from inverse of peripheral signal
4873 //               selected by funcsel
4874 //               0x2 -> disable output
4875 //               0x3 -> enable output
4876 #define IO_BANK0_GPIO28_CTRL_OEOVER_RESET         _u(0x0)
4877 #define IO_BANK0_GPIO28_CTRL_OEOVER_BITS          _u(0x00003000)
4878 #define IO_BANK0_GPIO28_CTRL_OEOVER_MSB           _u(13)
4879 #define IO_BANK0_GPIO28_CTRL_OEOVER_LSB           _u(12)
4880 #define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS        "RW"
4881 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
4882 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
4883 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
4884 #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
4885 // -----------------------------------------------------------------------------
4886 // Field       : IO_BANK0_GPIO28_CTRL_OUTOVER
4887 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
4888 //               0x1 -> drive output from inverse of peripheral signal selected
4889 //               by funcsel
4890 //               0x2 -> drive output low
4891 //               0x3 -> drive output high
4892 #define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET        _u(0x0)
4893 #define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS         _u(0x00000300)
4894 #define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB          _u(9)
4895 #define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB          _u(8)
4896 #define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS       "RW"
4897 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
4898 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
4899 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
4900 #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
4901 // -----------------------------------------------------------------------------
4902 // Field       : IO_BANK0_GPIO28_CTRL_FUNCSEL
4903 // Description : 0-31 -> selects pin function according to the gpio table
4904 //               31 == NULL
4905 //               0x01 -> spi1_rx
4906 //               0x02 -> uart0_tx
4907 //               0x03 -> i2c0_sda
4908 //               0x04 -> pwm_a_6
4909 //               0x05 -> sio_28
4910 //               0x06 -> pio0_28
4911 //               0x07 -> pio1_28
4912 //               0x09 -> usb_muxing_vbus_detect
4913 //               0x1f -> null
4914 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET                        _u(0x1f)
4915 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS                         _u(0x0000001f)
4916 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB                          _u(4)
4917 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB                          _u(0)
4918 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS                       "RW"
4919 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX                _u(0x01)
4920 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX               _u(0x02)
4921 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA               _u(0x03)
4922 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6                _u(0x04)
4923 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28                 _u(0x05)
4924 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28                _u(0x06)
4925 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28                _u(0x07)
4926 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
4927 #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL                   _u(0x1f)
4928 // =============================================================================
4929 // Register    : IO_BANK0_GPIO29_STATUS
4930 // Description : GPIO status
4931 #define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8)
4932 #define IO_BANK0_GPIO29_STATUS_BITS   _u(0x050a3300)
4933 #define IO_BANK0_GPIO29_STATUS_RESET  _u(0x00000000)
4934 // -----------------------------------------------------------------------------
4935 // Field       : IO_BANK0_GPIO29_STATUS_IRQTOPROC
4936 // Description : interrupt to processors, after override is applied
4937 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET  _u(0x0)
4938 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS   _u(0x04000000)
4939 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB    _u(26)
4940 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB    _u(26)
4941 #define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO"
4942 // -----------------------------------------------------------------------------
4943 // Field       : IO_BANK0_GPIO29_STATUS_IRQFROMPAD
4944 // Description : interrupt from pad before override is applied
4945 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET  _u(0x0)
4946 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS   _u(0x01000000)
4947 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB    _u(24)
4948 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB    _u(24)
4949 #define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO"
4950 // -----------------------------------------------------------------------------
4951 // Field       : IO_BANK0_GPIO29_STATUS_INTOPERI
4952 // Description : input signal to peripheral, after override is applied
4953 #define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET  _u(0x0)
4954 #define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS   _u(0x00080000)
4955 #define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB    _u(19)
4956 #define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB    _u(19)
4957 #define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO"
4958 // -----------------------------------------------------------------------------
4959 // Field       : IO_BANK0_GPIO29_STATUS_INFROMPAD
4960 // Description : input signal from pad, before override is applied
4961 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET  _u(0x0)
4962 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS   _u(0x00020000)
4963 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB    _u(17)
4964 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB    _u(17)
4965 #define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO"
4966 // -----------------------------------------------------------------------------
4967 // Field       : IO_BANK0_GPIO29_STATUS_OETOPAD
4968 // Description : output enable to pad after register override is applied
4969 #define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET  _u(0x0)
4970 #define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS   _u(0x00002000)
4971 #define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB    _u(13)
4972 #define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB    _u(13)
4973 #define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO"
4974 // -----------------------------------------------------------------------------
4975 // Field       : IO_BANK0_GPIO29_STATUS_OEFROMPERI
4976 // Description : output enable from selected peripheral, before register
4977 //               override is applied
4978 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET  _u(0x0)
4979 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS   _u(0x00001000)
4980 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB    _u(12)
4981 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB    _u(12)
4982 #define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO"
4983 // -----------------------------------------------------------------------------
4984 // Field       : IO_BANK0_GPIO29_STATUS_OUTTOPAD
4985 // Description : output signal to pad after register override is applied
4986 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET  _u(0x0)
4987 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS   _u(0x00000200)
4988 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB    _u(9)
4989 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB    _u(9)
4990 #define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO"
4991 // -----------------------------------------------------------------------------
4992 // Field       : IO_BANK0_GPIO29_STATUS_OUTFROMPERI
4993 // Description : output signal from selected peripheral, before register
4994 //               override is applied
4995 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET  _u(0x0)
4996 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS   _u(0x00000100)
4997 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB    _u(8)
4998 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB    _u(8)
4999 #define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO"
5000 // =============================================================================
5001 // Register    : IO_BANK0_GPIO29_CTRL
5002 // Description : GPIO control including function select and overrides.
5003 #define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec)
5004 #define IO_BANK0_GPIO29_CTRL_BITS   _u(0x3003331f)
5005 #define IO_BANK0_GPIO29_CTRL_RESET  _u(0x0000001f)
5006 // -----------------------------------------------------------------------------
5007 // Field       : IO_BANK0_GPIO29_CTRL_IRQOVER
5008 // Description : 0x0 -> don't invert the interrupt
5009 //               0x1 -> invert the interrupt
5010 //               0x2 -> drive interrupt low
5011 //               0x3 -> drive interrupt high
5012 #define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET        _u(0x0)
5013 #define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS         _u(0x30000000)
5014 #define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB          _u(29)
5015 #define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB          _u(28)
5016 #define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS       "RW"
5017 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
5018 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
5019 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW    _u(0x2)
5020 #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH   _u(0x3)
5021 // -----------------------------------------------------------------------------
5022 // Field       : IO_BANK0_GPIO29_CTRL_INOVER
5023 // Description : 0x0 -> don't invert the peri input
5024 //               0x1 -> invert the peri input
5025 //               0x2 -> drive peri input low
5026 //               0x3 -> drive peri input high
5027 #define IO_BANK0_GPIO29_CTRL_INOVER_RESET        _u(0x0)
5028 #define IO_BANK0_GPIO29_CTRL_INOVER_BITS         _u(0x00030000)
5029 #define IO_BANK0_GPIO29_CTRL_INOVER_MSB          _u(17)
5030 #define IO_BANK0_GPIO29_CTRL_INOVER_LSB          _u(16)
5031 #define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS       "RW"
5032 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0)
5033 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1)
5034 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW    _u(0x2)
5035 #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH   _u(0x3)
5036 // -----------------------------------------------------------------------------
5037 // Field       : IO_BANK0_GPIO29_CTRL_OEOVER
5038 // Description : 0x0 -> drive output enable from peripheral signal selected by
5039 //               funcsel
5040 //               0x1 -> drive output enable from inverse of peripheral signal
5041 //               selected by funcsel
5042 //               0x2 -> disable output
5043 //               0x3 -> enable output
5044 #define IO_BANK0_GPIO29_CTRL_OEOVER_RESET         _u(0x0)
5045 #define IO_BANK0_GPIO29_CTRL_OEOVER_BITS          _u(0x00003000)
5046 #define IO_BANK0_GPIO29_CTRL_OEOVER_MSB           _u(13)
5047 #define IO_BANK0_GPIO29_CTRL_OEOVER_LSB           _u(12)
5048 #define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS        "RW"
5049 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL  _u(0x0)
5050 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT  _u(0x1)
5051 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
5052 #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE  _u(0x3)
5053 // -----------------------------------------------------------------------------
5054 // Field       : IO_BANK0_GPIO29_CTRL_OUTOVER
5055 // Description : 0x0 -> drive output from peripheral signal selected by funcsel
5056 //               0x1 -> drive output from inverse of peripheral signal selected
5057 //               by funcsel
5058 //               0x2 -> drive output low
5059 //               0x3 -> drive output high
5060 #define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET        _u(0x0)
5061 #define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS         _u(0x00000300)
5062 #define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB          _u(9)
5063 #define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB          _u(8)
5064 #define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS       "RW"
5065 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
5066 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
5067 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW    _u(0x2)
5068 #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH   _u(0x3)
5069 // -----------------------------------------------------------------------------
5070 // Field       : IO_BANK0_GPIO29_CTRL_FUNCSEL
5071 // Description : 0-31 -> selects pin function according to the gpio table
5072 //               31 == NULL
5073 //               0x01 -> spi1_ss_n
5074 //               0x02 -> uart0_rx
5075 //               0x03 -> i2c0_scl
5076 //               0x04 -> pwm_b_6
5077 //               0x05 -> sio_29
5078 //               0x06 -> pio0_29
5079 //               0x07 -> pio1_29
5080 //               0x09 -> usb_muxing_vbus_en
5081 //               0x1f -> null
5082 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET                    _u(0x1f)
5083 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS                     _u(0x0000001f)
5084 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB                      _u(4)
5085 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB                      _u(0)
5086 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS                   "RW"
5087 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N          _u(0x01)
5088 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX           _u(0x02)
5089 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL           _u(0x03)
5090 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6            _u(0x04)
5091 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29             _u(0x05)
5092 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29            _u(0x06)
5093 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29            _u(0x07)
5094 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
5095 #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL               _u(0x1f)
5096 // =============================================================================
5097 // Register    : IO_BANK0_INTR0
5098 // Description : Raw Interrupts
5099 #define IO_BANK0_INTR0_OFFSET _u(0x000000f0)
5100 #define IO_BANK0_INTR0_BITS   _u(0xffffffff)
5101 #define IO_BANK0_INTR0_RESET  _u(0x00000000)
5102 // -----------------------------------------------------------------------------
5103 // Field       : IO_BANK0_INTR0_GPIO7_EDGE_HIGH
5104 // Description : None
5105 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
5106 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
5107 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB    _u(31)
5108 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB    _u(31)
5109 #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC"
5110 // -----------------------------------------------------------------------------
5111 // Field       : IO_BANK0_INTR0_GPIO7_EDGE_LOW
5112 // Description : None
5113 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET  _u(0x0)
5114 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
5115 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB    _u(30)
5116 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB    _u(30)
5117 #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC"
5118 // -----------------------------------------------------------------------------
5119 // Field       : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH
5120 // Description : None
5121 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
5122 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
5123 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB    _u(29)
5124 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB    _u(29)
5125 #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO"
5126 // -----------------------------------------------------------------------------
5127 // Field       : IO_BANK0_INTR0_GPIO7_LEVEL_LOW
5128 // Description : None
5129 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
5130 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
5131 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB    _u(28)
5132 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB    _u(28)
5133 #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO"
5134 // -----------------------------------------------------------------------------
5135 // Field       : IO_BANK0_INTR0_GPIO6_EDGE_HIGH
5136 // Description : None
5137 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
5138 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
5139 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB    _u(27)
5140 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB    _u(27)
5141 #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC"
5142 // -----------------------------------------------------------------------------
5143 // Field       : IO_BANK0_INTR0_GPIO6_EDGE_LOW
5144 // Description : None
5145 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET  _u(0x0)
5146 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
5147 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB    _u(26)
5148 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB    _u(26)
5149 #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC"
5150 // -----------------------------------------------------------------------------
5151 // Field       : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH
5152 // Description : None
5153 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
5154 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
5155 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB    _u(25)
5156 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB    _u(25)
5157 #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO"
5158 // -----------------------------------------------------------------------------
5159 // Field       : IO_BANK0_INTR0_GPIO6_LEVEL_LOW
5160 // Description : None
5161 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
5162 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
5163 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB    _u(24)
5164 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB    _u(24)
5165 #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO"
5166 // -----------------------------------------------------------------------------
5167 // Field       : IO_BANK0_INTR0_GPIO5_EDGE_HIGH
5168 // Description : None
5169 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
5170 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
5171 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB    _u(23)
5172 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB    _u(23)
5173 #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC"
5174 // -----------------------------------------------------------------------------
5175 // Field       : IO_BANK0_INTR0_GPIO5_EDGE_LOW
5176 // Description : None
5177 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET  _u(0x0)
5178 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
5179 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB    _u(22)
5180 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB    _u(22)
5181 #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC"
5182 // -----------------------------------------------------------------------------
5183 // Field       : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH
5184 // Description : None
5185 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
5186 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
5187 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB    _u(21)
5188 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB    _u(21)
5189 #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO"
5190 // -----------------------------------------------------------------------------
5191 // Field       : IO_BANK0_INTR0_GPIO5_LEVEL_LOW
5192 // Description : None
5193 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
5194 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
5195 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB    _u(20)
5196 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB    _u(20)
5197 #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO"
5198 // -----------------------------------------------------------------------------
5199 // Field       : IO_BANK0_INTR0_GPIO4_EDGE_HIGH
5200 // Description : None
5201 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
5202 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
5203 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB    _u(19)
5204 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB    _u(19)
5205 #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC"
5206 // -----------------------------------------------------------------------------
5207 // Field       : IO_BANK0_INTR0_GPIO4_EDGE_LOW
5208 // Description : None
5209 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET  _u(0x0)
5210 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
5211 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB    _u(18)
5212 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB    _u(18)
5213 #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC"
5214 // -----------------------------------------------------------------------------
5215 // Field       : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH
5216 // Description : None
5217 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
5218 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
5219 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB    _u(17)
5220 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB    _u(17)
5221 #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO"
5222 // -----------------------------------------------------------------------------
5223 // Field       : IO_BANK0_INTR0_GPIO4_LEVEL_LOW
5224 // Description : None
5225 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
5226 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
5227 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB    _u(16)
5228 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB    _u(16)
5229 #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO"
5230 // -----------------------------------------------------------------------------
5231 // Field       : IO_BANK0_INTR0_GPIO3_EDGE_HIGH
5232 // Description : None
5233 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
5234 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
5235 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB    _u(15)
5236 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB    _u(15)
5237 #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC"
5238 // -----------------------------------------------------------------------------
5239 // Field       : IO_BANK0_INTR0_GPIO3_EDGE_LOW
5240 // Description : None
5241 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET  _u(0x0)
5242 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
5243 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB    _u(14)
5244 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB    _u(14)
5245 #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC"
5246 // -----------------------------------------------------------------------------
5247 // Field       : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH
5248 // Description : None
5249 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
5250 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
5251 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB    _u(13)
5252 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB    _u(13)
5253 #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO"
5254 // -----------------------------------------------------------------------------
5255 // Field       : IO_BANK0_INTR0_GPIO3_LEVEL_LOW
5256 // Description : None
5257 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
5258 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
5259 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB    _u(12)
5260 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB    _u(12)
5261 #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO"
5262 // -----------------------------------------------------------------------------
5263 // Field       : IO_BANK0_INTR0_GPIO2_EDGE_HIGH
5264 // Description : None
5265 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
5266 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
5267 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB    _u(11)
5268 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB    _u(11)
5269 #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC"
5270 // -----------------------------------------------------------------------------
5271 // Field       : IO_BANK0_INTR0_GPIO2_EDGE_LOW
5272 // Description : None
5273 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET  _u(0x0)
5274 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
5275 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB    _u(10)
5276 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB    _u(10)
5277 #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC"
5278 // -----------------------------------------------------------------------------
5279 // Field       : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH
5280 // Description : None
5281 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
5282 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
5283 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB    _u(9)
5284 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB    _u(9)
5285 #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO"
5286 // -----------------------------------------------------------------------------
5287 // Field       : IO_BANK0_INTR0_GPIO2_LEVEL_LOW
5288 // Description : None
5289 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
5290 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
5291 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB    _u(8)
5292 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB    _u(8)
5293 #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO"
5294 // -----------------------------------------------------------------------------
5295 // Field       : IO_BANK0_INTR0_GPIO1_EDGE_HIGH
5296 // Description : None
5297 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
5298 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
5299 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB    _u(7)
5300 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB    _u(7)
5301 #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC"
5302 // -----------------------------------------------------------------------------
5303 // Field       : IO_BANK0_INTR0_GPIO1_EDGE_LOW
5304 // Description : None
5305 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET  _u(0x0)
5306 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
5307 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB    _u(6)
5308 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB    _u(6)
5309 #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC"
5310 // -----------------------------------------------------------------------------
5311 // Field       : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH
5312 // Description : None
5313 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
5314 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
5315 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB    _u(5)
5316 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB    _u(5)
5317 #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO"
5318 // -----------------------------------------------------------------------------
5319 // Field       : IO_BANK0_INTR0_GPIO1_LEVEL_LOW
5320 // Description : None
5321 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
5322 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
5323 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB    _u(4)
5324 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB    _u(4)
5325 #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO"
5326 // -----------------------------------------------------------------------------
5327 // Field       : IO_BANK0_INTR0_GPIO0_EDGE_HIGH
5328 // Description : None
5329 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
5330 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
5331 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB    _u(3)
5332 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB    _u(3)
5333 #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC"
5334 // -----------------------------------------------------------------------------
5335 // Field       : IO_BANK0_INTR0_GPIO0_EDGE_LOW
5336 // Description : None
5337 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET  _u(0x0)
5338 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
5339 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB    _u(2)
5340 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB    _u(2)
5341 #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC"
5342 // -----------------------------------------------------------------------------
5343 // Field       : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH
5344 // Description : None
5345 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
5346 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
5347 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB    _u(1)
5348 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB    _u(1)
5349 #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO"
5350 // -----------------------------------------------------------------------------
5351 // Field       : IO_BANK0_INTR0_GPIO0_LEVEL_LOW
5352 // Description : None
5353 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
5354 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
5355 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB    _u(0)
5356 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB    _u(0)
5357 #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO"
5358 // =============================================================================
5359 // Register    : IO_BANK0_INTR1
5360 // Description : Raw Interrupts
5361 #define IO_BANK0_INTR1_OFFSET _u(0x000000f4)
5362 #define IO_BANK0_INTR1_BITS   _u(0xffffffff)
5363 #define IO_BANK0_INTR1_RESET  _u(0x00000000)
5364 // -----------------------------------------------------------------------------
5365 // Field       : IO_BANK0_INTR1_GPIO15_EDGE_HIGH
5366 // Description : None
5367 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
5368 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
5369 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB    _u(31)
5370 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB    _u(31)
5371 #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC"
5372 // -----------------------------------------------------------------------------
5373 // Field       : IO_BANK0_INTR1_GPIO15_EDGE_LOW
5374 // Description : None
5375 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET  _u(0x0)
5376 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
5377 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB    _u(30)
5378 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB    _u(30)
5379 #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC"
5380 // -----------------------------------------------------------------------------
5381 // Field       : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH
5382 // Description : None
5383 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
5384 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
5385 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB    _u(29)
5386 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB    _u(29)
5387 #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO"
5388 // -----------------------------------------------------------------------------
5389 // Field       : IO_BANK0_INTR1_GPIO15_LEVEL_LOW
5390 // Description : None
5391 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
5392 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
5393 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB    _u(28)
5394 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB    _u(28)
5395 #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO"
5396 // -----------------------------------------------------------------------------
5397 // Field       : IO_BANK0_INTR1_GPIO14_EDGE_HIGH
5398 // Description : None
5399 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
5400 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
5401 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB    _u(27)
5402 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB    _u(27)
5403 #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC"
5404 // -----------------------------------------------------------------------------
5405 // Field       : IO_BANK0_INTR1_GPIO14_EDGE_LOW
5406 // Description : None
5407 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET  _u(0x0)
5408 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
5409 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB    _u(26)
5410 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB    _u(26)
5411 #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC"
5412 // -----------------------------------------------------------------------------
5413 // Field       : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH
5414 // Description : None
5415 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
5416 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
5417 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB    _u(25)
5418 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB    _u(25)
5419 #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO"
5420 // -----------------------------------------------------------------------------
5421 // Field       : IO_BANK0_INTR1_GPIO14_LEVEL_LOW
5422 // Description : None
5423 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
5424 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
5425 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB    _u(24)
5426 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB    _u(24)
5427 #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO"
5428 // -----------------------------------------------------------------------------
5429 // Field       : IO_BANK0_INTR1_GPIO13_EDGE_HIGH
5430 // Description : None
5431 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
5432 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
5433 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB    _u(23)
5434 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB    _u(23)
5435 #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC"
5436 // -----------------------------------------------------------------------------
5437 // Field       : IO_BANK0_INTR1_GPIO13_EDGE_LOW
5438 // Description : None
5439 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET  _u(0x0)
5440 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
5441 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB    _u(22)
5442 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB    _u(22)
5443 #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC"
5444 // -----------------------------------------------------------------------------
5445 // Field       : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH
5446 // Description : None
5447 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
5448 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
5449 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB    _u(21)
5450 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB    _u(21)
5451 #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO"
5452 // -----------------------------------------------------------------------------
5453 // Field       : IO_BANK0_INTR1_GPIO13_LEVEL_LOW
5454 // Description : None
5455 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
5456 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
5457 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB    _u(20)
5458 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB    _u(20)
5459 #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO"
5460 // -----------------------------------------------------------------------------
5461 // Field       : IO_BANK0_INTR1_GPIO12_EDGE_HIGH
5462 // Description : None
5463 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
5464 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
5465 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB    _u(19)
5466 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB    _u(19)
5467 #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC"
5468 // -----------------------------------------------------------------------------
5469 // Field       : IO_BANK0_INTR1_GPIO12_EDGE_LOW
5470 // Description : None
5471 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET  _u(0x0)
5472 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
5473 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB    _u(18)
5474 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB    _u(18)
5475 #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC"
5476 // -----------------------------------------------------------------------------
5477 // Field       : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH
5478 // Description : None
5479 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
5480 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
5481 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB    _u(17)
5482 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB    _u(17)
5483 #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO"
5484 // -----------------------------------------------------------------------------
5485 // Field       : IO_BANK0_INTR1_GPIO12_LEVEL_LOW
5486 // Description : None
5487 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
5488 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
5489 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB    _u(16)
5490 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB    _u(16)
5491 #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO"
5492 // -----------------------------------------------------------------------------
5493 // Field       : IO_BANK0_INTR1_GPIO11_EDGE_HIGH
5494 // Description : None
5495 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
5496 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
5497 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB    _u(15)
5498 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB    _u(15)
5499 #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC"
5500 // -----------------------------------------------------------------------------
5501 // Field       : IO_BANK0_INTR1_GPIO11_EDGE_LOW
5502 // Description : None
5503 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET  _u(0x0)
5504 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
5505 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB    _u(14)
5506 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB    _u(14)
5507 #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC"
5508 // -----------------------------------------------------------------------------
5509 // Field       : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH
5510 // Description : None
5511 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
5512 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
5513 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB    _u(13)
5514 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB    _u(13)
5515 #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO"
5516 // -----------------------------------------------------------------------------
5517 // Field       : IO_BANK0_INTR1_GPIO11_LEVEL_LOW
5518 // Description : None
5519 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
5520 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
5521 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB    _u(12)
5522 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB    _u(12)
5523 #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO"
5524 // -----------------------------------------------------------------------------
5525 // Field       : IO_BANK0_INTR1_GPIO10_EDGE_HIGH
5526 // Description : None
5527 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
5528 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
5529 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB    _u(11)
5530 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB    _u(11)
5531 #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC"
5532 // -----------------------------------------------------------------------------
5533 // Field       : IO_BANK0_INTR1_GPIO10_EDGE_LOW
5534 // Description : None
5535 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET  _u(0x0)
5536 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
5537 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB    _u(10)
5538 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB    _u(10)
5539 #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC"
5540 // -----------------------------------------------------------------------------
5541 // Field       : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH
5542 // Description : None
5543 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
5544 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
5545 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB    _u(9)
5546 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB    _u(9)
5547 #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO"
5548 // -----------------------------------------------------------------------------
5549 // Field       : IO_BANK0_INTR1_GPIO10_LEVEL_LOW
5550 // Description : None
5551 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
5552 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
5553 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB    _u(8)
5554 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB    _u(8)
5555 #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO"
5556 // -----------------------------------------------------------------------------
5557 // Field       : IO_BANK0_INTR1_GPIO9_EDGE_HIGH
5558 // Description : None
5559 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
5560 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
5561 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB    _u(7)
5562 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB    _u(7)
5563 #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC"
5564 // -----------------------------------------------------------------------------
5565 // Field       : IO_BANK0_INTR1_GPIO9_EDGE_LOW
5566 // Description : None
5567 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET  _u(0x0)
5568 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
5569 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB    _u(6)
5570 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB    _u(6)
5571 #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC"
5572 // -----------------------------------------------------------------------------
5573 // Field       : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH
5574 // Description : None
5575 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
5576 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
5577 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB    _u(5)
5578 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB    _u(5)
5579 #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO"
5580 // -----------------------------------------------------------------------------
5581 // Field       : IO_BANK0_INTR1_GPIO9_LEVEL_LOW
5582 // Description : None
5583 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
5584 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
5585 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB    _u(4)
5586 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB    _u(4)
5587 #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO"
5588 // -----------------------------------------------------------------------------
5589 // Field       : IO_BANK0_INTR1_GPIO8_EDGE_HIGH
5590 // Description : None
5591 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
5592 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
5593 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB    _u(3)
5594 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB    _u(3)
5595 #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC"
5596 // -----------------------------------------------------------------------------
5597 // Field       : IO_BANK0_INTR1_GPIO8_EDGE_LOW
5598 // Description : None
5599 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET  _u(0x0)
5600 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
5601 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB    _u(2)
5602 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB    _u(2)
5603 #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC"
5604 // -----------------------------------------------------------------------------
5605 // Field       : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH
5606 // Description : None
5607 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
5608 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
5609 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB    _u(1)
5610 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB    _u(1)
5611 #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO"
5612 // -----------------------------------------------------------------------------
5613 // Field       : IO_BANK0_INTR1_GPIO8_LEVEL_LOW
5614 // Description : None
5615 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
5616 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
5617 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB    _u(0)
5618 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB    _u(0)
5619 #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO"
5620 // =============================================================================
5621 // Register    : IO_BANK0_INTR2
5622 // Description : Raw Interrupts
5623 #define IO_BANK0_INTR2_OFFSET _u(0x000000f8)
5624 #define IO_BANK0_INTR2_BITS   _u(0xffffffff)
5625 #define IO_BANK0_INTR2_RESET  _u(0x00000000)
5626 // -----------------------------------------------------------------------------
5627 // Field       : IO_BANK0_INTR2_GPIO23_EDGE_HIGH
5628 // Description : None
5629 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
5630 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
5631 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB    _u(31)
5632 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB    _u(31)
5633 #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC"
5634 // -----------------------------------------------------------------------------
5635 // Field       : IO_BANK0_INTR2_GPIO23_EDGE_LOW
5636 // Description : None
5637 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET  _u(0x0)
5638 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
5639 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB    _u(30)
5640 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB    _u(30)
5641 #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC"
5642 // -----------------------------------------------------------------------------
5643 // Field       : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH
5644 // Description : None
5645 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
5646 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
5647 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB    _u(29)
5648 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB    _u(29)
5649 #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO"
5650 // -----------------------------------------------------------------------------
5651 // Field       : IO_BANK0_INTR2_GPIO23_LEVEL_LOW
5652 // Description : None
5653 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
5654 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
5655 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB    _u(28)
5656 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB    _u(28)
5657 #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO"
5658 // -----------------------------------------------------------------------------
5659 // Field       : IO_BANK0_INTR2_GPIO22_EDGE_HIGH
5660 // Description : None
5661 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
5662 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
5663 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB    _u(27)
5664 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB    _u(27)
5665 #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC"
5666 // -----------------------------------------------------------------------------
5667 // Field       : IO_BANK0_INTR2_GPIO22_EDGE_LOW
5668 // Description : None
5669 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET  _u(0x0)
5670 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
5671 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB    _u(26)
5672 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB    _u(26)
5673 #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC"
5674 // -----------------------------------------------------------------------------
5675 // Field       : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH
5676 // Description : None
5677 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
5678 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
5679 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB    _u(25)
5680 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB    _u(25)
5681 #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO"
5682 // -----------------------------------------------------------------------------
5683 // Field       : IO_BANK0_INTR2_GPIO22_LEVEL_LOW
5684 // Description : None
5685 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
5686 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
5687 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB    _u(24)
5688 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB    _u(24)
5689 #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO"
5690 // -----------------------------------------------------------------------------
5691 // Field       : IO_BANK0_INTR2_GPIO21_EDGE_HIGH
5692 // Description : None
5693 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
5694 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
5695 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB    _u(23)
5696 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB    _u(23)
5697 #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC"
5698 // -----------------------------------------------------------------------------
5699 // Field       : IO_BANK0_INTR2_GPIO21_EDGE_LOW
5700 // Description : None
5701 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET  _u(0x0)
5702 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
5703 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB    _u(22)
5704 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB    _u(22)
5705 #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC"
5706 // -----------------------------------------------------------------------------
5707 // Field       : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH
5708 // Description : None
5709 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
5710 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
5711 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB    _u(21)
5712 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB    _u(21)
5713 #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO"
5714 // -----------------------------------------------------------------------------
5715 // Field       : IO_BANK0_INTR2_GPIO21_LEVEL_LOW
5716 // Description : None
5717 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
5718 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
5719 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB    _u(20)
5720 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB    _u(20)
5721 #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO"
5722 // -----------------------------------------------------------------------------
5723 // Field       : IO_BANK0_INTR2_GPIO20_EDGE_HIGH
5724 // Description : None
5725 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
5726 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
5727 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB    _u(19)
5728 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB    _u(19)
5729 #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC"
5730 // -----------------------------------------------------------------------------
5731 // Field       : IO_BANK0_INTR2_GPIO20_EDGE_LOW
5732 // Description : None
5733 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET  _u(0x0)
5734 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
5735 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB    _u(18)
5736 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB    _u(18)
5737 #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC"
5738 // -----------------------------------------------------------------------------
5739 // Field       : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH
5740 // Description : None
5741 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
5742 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
5743 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB    _u(17)
5744 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB    _u(17)
5745 #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO"
5746 // -----------------------------------------------------------------------------
5747 // Field       : IO_BANK0_INTR2_GPIO20_LEVEL_LOW
5748 // Description : None
5749 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
5750 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
5751 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB    _u(16)
5752 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB    _u(16)
5753 #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO"
5754 // -----------------------------------------------------------------------------
5755 // Field       : IO_BANK0_INTR2_GPIO19_EDGE_HIGH
5756 // Description : None
5757 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
5758 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
5759 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB    _u(15)
5760 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB    _u(15)
5761 #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC"
5762 // -----------------------------------------------------------------------------
5763 // Field       : IO_BANK0_INTR2_GPIO19_EDGE_LOW
5764 // Description : None
5765 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET  _u(0x0)
5766 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
5767 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB    _u(14)
5768 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB    _u(14)
5769 #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC"
5770 // -----------------------------------------------------------------------------
5771 // Field       : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH
5772 // Description : None
5773 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
5774 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
5775 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB    _u(13)
5776 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB    _u(13)
5777 #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO"
5778 // -----------------------------------------------------------------------------
5779 // Field       : IO_BANK0_INTR2_GPIO19_LEVEL_LOW
5780 // Description : None
5781 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
5782 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
5783 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB    _u(12)
5784 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB    _u(12)
5785 #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO"
5786 // -----------------------------------------------------------------------------
5787 // Field       : IO_BANK0_INTR2_GPIO18_EDGE_HIGH
5788 // Description : None
5789 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
5790 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
5791 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB    _u(11)
5792 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB    _u(11)
5793 #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC"
5794 // -----------------------------------------------------------------------------
5795 // Field       : IO_BANK0_INTR2_GPIO18_EDGE_LOW
5796 // Description : None
5797 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET  _u(0x0)
5798 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
5799 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB    _u(10)
5800 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB    _u(10)
5801 #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC"
5802 // -----------------------------------------------------------------------------
5803 // Field       : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH
5804 // Description : None
5805 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
5806 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
5807 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB    _u(9)
5808 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB    _u(9)
5809 #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO"
5810 // -----------------------------------------------------------------------------
5811 // Field       : IO_BANK0_INTR2_GPIO18_LEVEL_LOW
5812 // Description : None
5813 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
5814 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
5815 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB    _u(8)
5816 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB    _u(8)
5817 #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO"
5818 // -----------------------------------------------------------------------------
5819 // Field       : IO_BANK0_INTR2_GPIO17_EDGE_HIGH
5820 // Description : None
5821 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
5822 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
5823 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB    _u(7)
5824 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB    _u(7)
5825 #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC"
5826 // -----------------------------------------------------------------------------
5827 // Field       : IO_BANK0_INTR2_GPIO17_EDGE_LOW
5828 // Description : None
5829 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET  _u(0x0)
5830 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
5831 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB    _u(6)
5832 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB    _u(6)
5833 #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC"
5834 // -----------------------------------------------------------------------------
5835 // Field       : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH
5836 // Description : None
5837 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
5838 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
5839 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB    _u(5)
5840 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB    _u(5)
5841 #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO"
5842 // -----------------------------------------------------------------------------
5843 // Field       : IO_BANK0_INTR2_GPIO17_LEVEL_LOW
5844 // Description : None
5845 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
5846 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
5847 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB    _u(4)
5848 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB    _u(4)
5849 #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO"
5850 // -----------------------------------------------------------------------------
5851 // Field       : IO_BANK0_INTR2_GPIO16_EDGE_HIGH
5852 // Description : None
5853 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
5854 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
5855 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB    _u(3)
5856 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB    _u(3)
5857 #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC"
5858 // -----------------------------------------------------------------------------
5859 // Field       : IO_BANK0_INTR2_GPIO16_EDGE_LOW
5860 // Description : None
5861 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET  _u(0x0)
5862 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
5863 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB    _u(2)
5864 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB    _u(2)
5865 #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC"
5866 // -----------------------------------------------------------------------------
5867 // Field       : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH
5868 // Description : None
5869 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
5870 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
5871 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB    _u(1)
5872 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB    _u(1)
5873 #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO"
5874 // -----------------------------------------------------------------------------
5875 // Field       : IO_BANK0_INTR2_GPIO16_LEVEL_LOW
5876 // Description : None
5877 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
5878 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
5879 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB    _u(0)
5880 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB    _u(0)
5881 #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO"
5882 // =============================================================================
5883 // Register    : IO_BANK0_INTR3
5884 // Description : Raw Interrupts
5885 #define IO_BANK0_INTR3_OFFSET _u(0x000000fc)
5886 #define IO_BANK0_INTR3_BITS   _u(0x00ffffff)
5887 #define IO_BANK0_INTR3_RESET  _u(0x00000000)
5888 // -----------------------------------------------------------------------------
5889 // Field       : IO_BANK0_INTR3_GPIO29_EDGE_HIGH
5890 // Description : None
5891 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
5892 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
5893 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB    _u(23)
5894 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB    _u(23)
5895 #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC"
5896 // -----------------------------------------------------------------------------
5897 // Field       : IO_BANK0_INTR3_GPIO29_EDGE_LOW
5898 // Description : None
5899 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET  _u(0x0)
5900 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
5901 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB    _u(22)
5902 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB    _u(22)
5903 #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC"
5904 // -----------------------------------------------------------------------------
5905 // Field       : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH
5906 // Description : None
5907 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
5908 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
5909 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB    _u(21)
5910 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB    _u(21)
5911 #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO"
5912 // -----------------------------------------------------------------------------
5913 // Field       : IO_BANK0_INTR3_GPIO29_LEVEL_LOW
5914 // Description : None
5915 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
5916 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
5917 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB    _u(20)
5918 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB    _u(20)
5919 #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO"
5920 // -----------------------------------------------------------------------------
5921 // Field       : IO_BANK0_INTR3_GPIO28_EDGE_HIGH
5922 // Description : None
5923 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
5924 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
5925 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB    _u(19)
5926 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB    _u(19)
5927 #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC"
5928 // -----------------------------------------------------------------------------
5929 // Field       : IO_BANK0_INTR3_GPIO28_EDGE_LOW
5930 // Description : None
5931 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET  _u(0x0)
5932 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
5933 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB    _u(18)
5934 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB    _u(18)
5935 #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC"
5936 // -----------------------------------------------------------------------------
5937 // Field       : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH
5938 // Description : None
5939 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
5940 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
5941 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB    _u(17)
5942 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB    _u(17)
5943 #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO"
5944 // -----------------------------------------------------------------------------
5945 // Field       : IO_BANK0_INTR3_GPIO28_LEVEL_LOW
5946 // Description : None
5947 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
5948 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
5949 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB    _u(16)
5950 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB    _u(16)
5951 #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO"
5952 // -----------------------------------------------------------------------------
5953 // Field       : IO_BANK0_INTR3_GPIO27_EDGE_HIGH
5954 // Description : None
5955 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
5956 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
5957 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB    _u(15)
5958 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB    _u(15)
5959 #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC"
5960 // -----------------------------------------------------------------------------
5961 // Field       : IO_BANK0_INTR3_GPIO27_EDGE_LOW
5962 // Description : None
5963 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET  _u(0x0)
5964 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
5965 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB    _u(14)
5966 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB    _u(14)
5967 #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC"
5968 // -----------------------------------------------------------------------------
5969 // Field       : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH
5970 // Description : None
5971 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
5972 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
5973 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB    _u(13)
5974 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB    _u(13)
5975 #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO"
5976 // -----------------------------------------------------------------------------
5977 // Field       : IO_BANK0_INTR3_GPIO27_LEVEL_LOW
5978 // Description : None
5979 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
5980 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
5981 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB    _u(12)
5982 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB    _u(12)
5983 #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO"
5984 // -----------------------------------------------------------------------------
5985 // Field       : IO_BANK0_INTR3_GPIO26_EDGE_HIGH
5986 // Description : None
5987 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
5988 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
5989 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB    _u(11)
5990 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB    _u(11)
5991 #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC"
5992 // -----------------------------------------------------------------------------
5993 // Field       : IO_BANK0_INTR3_GPIO26_EDGE_LOW
5994 // Description : None
5995 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET  _u(0x0)
5996 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
5997 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB    _u(10)
5998 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB    _u(10)
5999 #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC"
6000 // -----------------------------------------------------------------------------
6001 // Field       : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH
6002 // Description : None
6003 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
6004 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
6005 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB    _u(9)
6006 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB    _u(9)
6007 #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO"
6008 // -----------------------------------------------------------------------------
6009 // Field       : IO_BANK0_INTR3_GPIO26_LEVEL_LOW
6010 // Description : None
6011 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
6012 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
6013 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB    _u(8)
6014 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB    _u(8)
6015 #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO"
6016 // -----------------------------------------------------------------------------
6017 // Field       : IO_BANK0_INTR3_GPIO25_EDGE_HIGH
6018 // Description : None
6019 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
6020 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
6021 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB    _u(7)
6022 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB    _u(7)
6023 #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC"
6024 // -----------------------------------------------------------------------------
6025 // Field       : IO_BANK0_INTR3_GPIO25_EDGE_LOW
6026 // Description : None
6027 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET  _u(0x0)
6028 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
6029 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB    _u(6)
6030 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB    _u(6)
6031 #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC"
6032 // -----------------------------------------------------------------------------
6033 // Field       : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH
6034 // Description : None
6035 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
6036 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
6037 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB    _u(5)
6038 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB    _u(5)
6039 #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO"
6040 // -----------------------------------------------------------------------------
6041 // Field       : IO_BANK0_INTR3_GPIO25_LEVEL_LOW
6042 // Description : None
6043 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
6044 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
6045 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB    _u(4)
6046 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB    _u(4)
6047 #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO"
6048 // -----------------------------------------------------------------------------
6049 // Field       : IO_BANK0_INTR3_GPIO24_EDGE_HIGH
6050 // Description : None
6051 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
6052 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
6053 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB    _u(3)
6054 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB    _u(3)
6055 #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC"
6056 // -----------------------------------------------------------------------------
6057 // Field       : IO_BANK0_INTR3_GPIO24_EDGE_LOW
6058 // Description : None
6059 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET  _u(0x0)
6060 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
6061 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB    _u(2)
6062 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB    _u(2)
6063 #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC"
6064 // -----------------------------------------------------------------------------
6065 // Field       : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH
6066 // Description : None
6067 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
6068 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
6069 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB    _u(1)
6070 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB    _u(1)
6071 #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO"
6072 // -----------------------------------------------------------------------------
6073 // Field       : IO_BANK0_INTR3_GPIO24_LEVEL_LOW
6074 // Description : None
6075 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
6076 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
6077 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB    _u(0)
6078 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB    _u(0)
6079 #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO"
6080 // =============================================================================
6081 // Register    : IO_BANK0_PROC0_INTE0
6082 // Description : Interrupt Enable for proc0
6083 #define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100)
6084 #define IO_BANK0_PROC0_INTE0_BITS   _u(0xffffffff)
6085 #define IO_BANK0_PROC0_INTE0_RESET  _u(0x00000000)
6086 // -----------------------------------------------------------------------------
6087 // Field       : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH
6088 // Description : None
6089 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
6090 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
6091 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB    _u(31)
6092 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB    _u(31)
6093 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
6094 // -----------------------------------------------------------------------------
6095 // Field       : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW
6096 // Description : None
6097 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET  _u(0x0)
6098 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
6099 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB    _u(30)
6100 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB    _u(30)
6101 #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
6102 // -----------------------------------------------------------------------------
6103 // Field       : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH
6104 // Description : None
6105 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
6106 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
6107 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB    _u(29)
6108 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB    _u(29)
6109 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
6110 // -----------------------------------------------------------------------------
6111 // Field       : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW
6112 // Description : None
6113 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
6114 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
6115 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB    _u(28)
6116 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB    _u(28)
6117 #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
6118 // -----------------------------------------------------------------------------
6119 // Field       : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH
6120 // Description : None
6121 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
6122 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
6123 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB    _u(27)
6124 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB    _u(27)
6125 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
6126 // -----------------------------------------------------------------------------
6127 // Field       : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW
6128 // Description : None
6129 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET  _u(0x0)
6130 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
6131 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB    _u(26)
6132 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB    _u(26)
6133 #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
6134 // -----------------------------------------------------------------------------
6135 // Field       : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH
6136 // Description : None
6137 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
6138 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
6139 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB    _u(25)
6140 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB    _u(25)
6141 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
6142 // -----------------------------------------------------------------------------
6143 // Field       : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW
6144 // Description : None
6145 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
6146 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
6147 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB    _u(24)
6148 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB    _u(24)
6149 #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
6150 // -----------------------------------------------------------------------------
6151 // Field       : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH
6152 // Description : None
6153 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
6154 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
6155 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB    _u(23)
6156 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB    _u(23)
6157 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
6158 // -----------------------------------------------------------------------------
6159 // Field       : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW
6160 // Description : None
6161 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET  _u(0x0)
6162 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
6163 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB    _u(22)
6164 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB    _u(22)
6165 #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
6166 // -----------------------------------------------------------------------------
6167 // Field       : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH
6168 // Description : None
6169 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
6170 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
6171 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB    _u(21)
6172 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB    _u(21)
6173 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
6174 // -----------------------------------------------------------------------------
6175 // Field       : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW
6176 // Description : None
6177 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
6178 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
6179 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB    _u(20)
6180 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB    _u(20)
6181 #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
6182 // -----------------------------------------------------------------------------
6183 // Field       : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH
6184 // Description : None
6185 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
6186 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
6187 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB    _u(19)
6188 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB    _u(19)
6189 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
6190 // -----------------------------------------------------------------------------
6191 // Field       : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW
6192 // Description : None
6193 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET  _u(0x0)
6194 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
6195 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB    _u(18)
6196 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB    _u(18)
6197 #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
6198 // -----------------------------------------------------------------------------
6199 // Field       : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH
6200 // Description : None
6201 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
6202 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
6203 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB    _u(17)
6204 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB    _u(17)
6205 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
6206 // -----------------------------------------------------------------------------
6207 // Field       : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW
6208 // Description : None
6209 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
6210 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
6211 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB    _u(16)
6212 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB    _u(16)
6213 #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
6214 // -----------------------------------------------------------------------------
6215 // Field       : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH
6216 // Description : None
6217 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
6218 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
6219 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB    _u(15)
6220 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB    _u(15)
6221 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
6222 // -----------------------------------------------------------------------------
6223 // Field       : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW
6224 // Description : None
6225 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET  _u(0x0)
6226 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
6227 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB    _u(14)
6228 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB    _u(14)
6229 #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
6230 // -----------------------------------------------------------------------------
6231 // Field       : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH
6232 // Description : None
6233 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
6234 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
6235 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB    _u(13)
6236 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB    _u(13)
6237 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
6238 // -----------------------------------------------------------------------------
6239 // Field       : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW
6240 // Description : None
6241 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
6242 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
6243 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB    _u(12)
6244 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB    _u(12)
6245 #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
6246 // -----------------------------------------------------------------------------
6247 // Field       : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH
6248 // Description : None
6249 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
6250 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
6251 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB    _u(11)
6252 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB    _u(11)
6253 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
6254 // -----------------------------------------------------------------------------
6255 // Field       : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW
6256 // Description : None
6257 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET  _u(0x0)
6258 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
6259 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB    _u(10)
6260 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB    _u(10)
6261 #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
6262 // -----------------------------------------------------------------------------
6263 // Field       : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH
6264 // Description : None
6265 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
6266 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
6267 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB    _u(9)
6268 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB    _u(9)
6269 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
6270 // -----------------------------------------------------------------------------
6271 // Field       : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW
6272 // Description : None
6273 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
6274 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
6275 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB    _u(8)
6276 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB    _u(8)
6277 #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
6278 // -----------------------------------------------------------------------------
6279 // Field       : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH
6280 // Description : None
6281 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
6282 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
6283 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB    _u(7)
6284 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB    _u(7)
6285 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
6286 // -----------------------------------------------------------------------------
6287 // Field       : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW
6288 // Description : None
6289 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET  _u(0x0)
6290 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
6291 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB    _u(6)
6292 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB    _u(6)
6293 #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
6294 // -----------------------------------------------------------------------------
6295 // Field       : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH
6296 // Description : None
6297 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
6298 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
6299 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB    _u(5)
6300 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB    _u(5)
6301 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
6302 // -----------------------------------------------------------------------------
6303 // Field       : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW
6304 // Description : None
6305 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
6306 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
6307 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB    _u(4)
6308 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB    _u(4)
6309 #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
6310 // -----------------------------------------------------------------------------
6311 // Field       : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH
6312 // Description : None
6313 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
6314 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
6315 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB    _u(3)
6316 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB    _u(3)
6317 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
6318 // -----------------------------------------------------------------------------
6319 // Field       : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW
6320 // Description : None
6321 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET  _u(0x0)
6322 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
6323 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB    _u(2)
6324 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB    _u(2)
6325 #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
6326 // -----------------------------------------------------------------------------
6327 // Field       : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH
6328 // Description : None
6329 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
6330 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
6331 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB    _u(1)
6332 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB    _u(1)
6333 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
6334 // -----------------------------------------------------------------------------
6335 // Field       : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW
6336 // Description : None
6337 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
6338 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
6339 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB    _u(0)
6340 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB    _u(0)
6341 #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
6342 // =============================================================================
6343 // Register    : IO_BANK0_PROC0_INTE1
6344 // Description : Interrupt Enable for proc0
6345 #define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104)
6346 #define IO_BANK0_PROC0_INTE1_BITS   _u(0xffffffff)
6347 #define IO_BANK0_PROC0_INTE1_RESET  _u(0x00000000)
6348 // -----------------------------------------------------------------------------
6349 // Field       : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH
6350 // Description : None
6351 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
6352 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
6353 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB    _u(31)
6354 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB    _u(31)
6355 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
6356 // -----------------------------------------------------------------------------
6357 // Field       : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW
6358 // Description : None
6359 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET  _u(0x0)
6360 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
6361 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB    _u(30)
6362 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB    _u(30)
6363 #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
6364 // -----------------------------------------------------------------------------
6365 // Field       : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH
6366 // Description : None
6367 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
6368 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
6369 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB    _u(29)
6370 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB    _u(29)
6371 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
6372 // -----------------------------------------------------------------------------
6373 // Field       : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW
6374 // Description : None
6375 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
6376 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
6377 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB    _u(28)
6378 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB    _u(28)
6379 #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
6380 // -----------------------------------------------------------------------------
6381 // Field       : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH
6382 // Description : None
6383 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
6384 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
6385 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB    _u(27)
6386 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB    _u(27)
6387 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
6388 // -----------------------------------------------------------------------------
6389 // Field       : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW
6390 // Description : None
6391 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET  _u(0x0)
6392 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
6393 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB    _u(26)
6394 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB    _u(26)
6395 #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
6396 // -----------------------------------------------------------------------------
6397 // Field       : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH
6398 // Description : None
6399 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
6400 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
6401 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB    _u(25)
6402 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB    _u(25)
6403 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
6404 // -----------------------------------------------------------------------------
6405 // Field       : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW
6406 // Description : None
6407 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
6408 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
6409 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB    _u(24)
6410 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB    _u(24)
6411 #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
6412 // -----------------------------------------------------------------------------
6413 // Field       : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH
6414 // Description : None
6415 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
6416 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
6417 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB    _u(23)
6418 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB    _u(23)
6419 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
6420 // -----------------------------------------------------------------------------
6421 // Field       : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW
6422 // Description : None
6423 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET  _u(0x0)
6424 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
6425 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB    _u(22)
6426 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB    _u(22)
6427 #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
6428 // -----------------------------------------------------------------------------
6429 // Field       : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH
6430 // Description : None
6431 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
6432 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
6433 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB    _u(21)
6434 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB    _u(21)
6435 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
6436 // -----------------------------------------------------------------------------
6437 // Field       : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW
6438 // Description : None
6439 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
6440 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
6441 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB    _u(20)
6442 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB    _u(20)
6443 #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
6444 // -----------------------------------------------------------------------------
6445 // Field       : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH
6446 // Description : None
6447 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
6448 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
6449 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB    _u(19)
6450 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB    _u(19)
6451 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
6452 // -----------------------------------------------------------------------------
6453 // Field       : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW
6454 // Description : None
6455 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET  _u(0x0)
6456 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
6457 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB    _u(18)
6458 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB    _u(18)
6459 #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
6460 // -----------------------------------------------------------------------------
6461 // Field       : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH
6462 // Description : None
6463 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
6464 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
6465 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB    _u(17)
6466 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB    _u(17)
6467 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
6468 // -----------------------------------------------------------------------------
6469 // Field       : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW
6470 // Description : None
6471 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
6472 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
6473 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB    _u(16)
6474 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB    _u(16)
6475 #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
6476 // -----------------------------------------------------------------------------
6477 // Field       : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH
6478 // Description : None
6479 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
6480 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
6481 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB    _u(15)
6482 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB    _u(15)
6483 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
6484 // -----------------------------------------------------------------------------
6485 // Field       : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW
6486 // Description : None
6487 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET  _u(0x0)
6488 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
6489 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB    _u(14)
6490 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB    _u(14)
6491 #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
6492 // -----------------------------------------------------------------------------
6493 // Field       : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH
6494 // Description : None
6495 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
6496 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
6497 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB    _u(13)
6498 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB    _u(13)
6499 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
6500 // -----------------------------------------------------------------------------
6501 // Field       : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW
6502 // Description : None
6503 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
6504 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
6505 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB    _u(12)
6506 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB    _u(12)
6507 #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
6508 // -----------------------------------------------------------------------------
6509 // Field       : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH
6510 // Description : None
6511 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
6512 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
6513 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB    _u(11)
6514 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB    _u(11)
6515 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
6516 // -----------------------------------------------------------------------------
6517 // Field       : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW
6518 // Description : None
6519 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET  _u(0x0)
6520 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
6521 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB    _u(10)
6522 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB    _u(10)
6523 #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
6524 // -----------------------------------------------------------------------------
6525 // Field       : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH
6526 // Description : None
6527 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
6528 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
6529 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB    _u(9)
6530 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB    _u(9)
6531 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
6532 // -----------------------------------------------------------------------------
6533 // Field       : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW
6534 // Description : None
6535 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
6536 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
6537 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB    _u(8)
6538 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB    _u(8)
6539 #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
6540 // -----------------------------------------------------------------------------
6541 // Field       : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH
6542 // Description : None
6543 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
6544 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
6545 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB    _u(7)
6546 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB    _u(7)
6547 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
6548 // -----------------------------------------------------------------------------
6549 // Field       : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW
6550 // Description : None
6551 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET  _u(0x0)
6552 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
6553 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB    _u(6)
6554 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB    _u(6)
6555 #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
6556 // -----------------------------------------------------------------------------
6557 // Field       : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH
6558 // Description : None
6559 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
6560 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
6561 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB    _u(5)
6562 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB    _u(5)
6563 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
6564 // -----------------------------------------------------------------------------
6565 // Field       : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW
6566 // Description : None
6567 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
6568 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
6569 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB    _u(4)
6570 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB    _u(4)
6571 #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
6572 // -----------------------------------------------------------------------------
6573 // Field       : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH
6574 // Description : None
6575 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
6576 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
6577 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB    _u(3)
6578 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB    _u(3)
6579 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
6580 // -----------------------------------------------------------------------------
6581 // Field       : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW
6582 // Description : None
6583 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET  _u(0x0)
6584 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
6585 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB    _u(2)
6586 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB    _u(2)
6587 #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
6588 // -----------------------------------------------------------------------------
6589 // Field       : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH
6590 // Description : None
6591 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
6592 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
6593 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB    _u(1)
6594 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB    _u(1)
6595 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
6596 // -----------------------------------------------------------------------------
6597 // Field       : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW
6598 // Description : None
6599 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
6600 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
6601 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB    _u(0)
6602 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB    _u(0)
6603 #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
6604 // =============================================================================
6605 // Register    : IO_BANK0_PROC0_INTE2
6606 // Description : Interrupt Enable for proc0
6607 #define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108)
6608 #define IO_BANK0_PROC0_INTE2_BITS   _u(0xffffffff)
6609 #define IO_BANK0_PROC0_INTE2_RESET  _u(0x00000000)
6610 // -----------------------------------------------------------------------------
6611 // Field       : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH
6612 // Description : None
6613 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
6614 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
6615 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB    _u(31)
6616 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB    _u(31)
6617 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
6618 // -----------------------------------------------------------------------------
6619 // Field       : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW
6620 // Description : None
6621 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET  _u(0x0)
6622 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
6623 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB    _u(30)
6624 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB    _u(30)
6625 #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
6626 // -----------------------------------------------------------------------------
6627 // Field       : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH
6628 // Description : None
6629 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
6630 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
6631 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB    _u(29)
6632 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB    _u(29)
6633 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
6634 // -----------------------------------------------------------------------------
6635 // Field       : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW
6636 // Description : None
6637 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
6638 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
6639 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB    _u(28)
6640 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB    _u(28)
6641 #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
6642 // -----------------------------------------------------------------------------
6643 // Field       : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH
6644 // Description : None
6645 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
6646 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
6647 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB    _u(27)
6648 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB    _u(27)
6649 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
6650 // -----------------------------------------------------------------------------
6651 // Field       : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW
6652 // Description : None
6653 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET  _u(0x0)
6654 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
6655 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB    _u(26)
6656 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB    _u(26)
6657 #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
6658 // -----------------------------------------------------------------------------
6659 // Field       : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH
6660 // Description : None
6661 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
6662 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
6663 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB    _u(25)
6664 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB    _u(25)
6665 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
6666 // -----------------------------------------------------------------------------
6667 // Field       : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW
6668 // Description : None
6669 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
6670 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
6671 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB    _u(24)
6672 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB    _u(24)
6673 #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
6674 // -----------------------------------------------------------------------------
6675 // Field       : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH
6676 // Description : None
6677 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
6678 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
6679 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB    _u(23)
6680 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB    _u(23)
6681 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
6682 // -----------------------------------------------------------------------------
6683 // Field       : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW
6684 // Description : None
6685 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET  _u(0x0)
6686 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
6687 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB    _u(22)
6688 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB    _u(22)
6689 #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
6690 // -----------------------------------------------------------------------------
6691 // Field       : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH
6692 // Description : None
6693 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
6694 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
6695 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB    _u(21)
6696 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB    _u(21)
6697 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
6698 // -----------------------------------------------------------------------------
6699 // Field       : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW
6700 // Description : None
6701 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
6702 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
6703 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB    _u(20)
6704 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB    _u(20)
6705 #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
6706 // -----------------------------------------------------------------------------
6707 // Field       : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH
6708 // Description : None
6709 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
6710 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
6711 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB    _u(19)
6712 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB    _u(19)
6713 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
6714 // -----------------------------------------------------------------------------
6715 // Field       : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW
6716 // Description : None
6717 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET  _u(0x0)
6718 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
6719 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB    _u(18)
6720 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB    _u(18)
6721 #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
6722 // -----------------------------------------------------------------------------
6723 // Field       : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH
6724 // Description : None
6725 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
6726 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
6727 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB    _u(17)
6728 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB    _u(17)
6729 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
6730 // -----------------------------------------------------------------------------
6731 // Field       : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW
6732 // Description : None
6733 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
6734 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
6735 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB    _u(16)
6736 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB    _u(16)
6737 #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
6738 // -----------------------------------------------------------------------------
6739 // Field       : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH
6740 // Description : None
6741 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
6742 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
6743 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB    _u(15)
6744 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB    _u(15)
6745 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
6746 // -----------------------------------------------------------------------------
6747 // Field       : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW
6748 // Description : None
6749 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET  _u(0x0)
6750 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
6751 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB    _u(14)
6752 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB    _u(14)
6753 #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
6754 // -----------------------------------------------------------------------------
6755 // Field       : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH
6756 // Description : None
6757 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
6758 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
6759 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB    _u(13)
6760 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB    _u(13)
6761 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
6762 // -----------------------------------------------------------------------------
6763 // Field       : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW
6764 // Description : None
6765 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
6766 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
6767 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB    _u(12)
6768 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB    _u(12)
6769 #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
6770 // -----------------------------------------------------------------------------
6771 // Field       : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH
6772 // Description : None
6773 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
6774 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
6775 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB    _u(11)
6776 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB    _u(11)
6777 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
6778 // -----------------------------------------------------------------------------
6779 // Field       : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW
6780 // Description : None
6781 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET  _u(0x0)
6782 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
6783 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB    _u(10)
6784 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB    _u(10)
6785 #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
6786 // -----------------------------------------------------------------------------
6787 // Field       : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH
6788 // Description : None
6789 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
6790 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
6791 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB    _u(9)
6792 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB    _u(9)
6793 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
6794 // -----------------------------------------------------------------------------
6795 // Field       : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW
6796 // Description : None
6797 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
6798 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
6799 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB    _u(8)
6800 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB    _u(8)
6801 #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
6802 // -----------------------------------------------------------------------------
6803 // Field       : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH
6804 // Description : None
6805 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
6806 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
6807 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB    _u(7)
6808 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB    _u(7)
6809 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
6810 // -----------------------------------------------------------------------------
6811 // Field       : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW
6812 // Description : None
6813 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET  _u(0x0)
6814 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
6815 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB    _u(6)
6816 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB    _u(6)
6817 #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
6818 // -----------------------------------------------------------------------------
6819 // Field       : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH
6820 // Description : None
6821 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
6822 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
6823 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB    _u(5)
6824 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB    _u(5)
6825 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
6826 // -----------------------------------------------------------------------------
6827 // Field       : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW
6828 // Description : None
6829 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
6830 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
6831 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB    _u(4)
6832 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB    _u(4)
6833 #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
6834 // -----------------------------------------------------------------------------
6835 // Field       : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH
6836 // Description : None
6837 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
6838 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
6839 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB    _u(3)
6840 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB    _u(3)
6841 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
6842 // -----------------------------------------------------------------------------
6843 // Field       : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW
6844 // Description : None
6845 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET  _u(0x0)
6846 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
6847 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB    _u(2)
6848 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB    _u(2)
6849 #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
6850 // -----------------------------------------------------------------------------
6851 // Field       : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH
6852 // Description : None
6853 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
6854 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
6855 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB    _u(1)
6856 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB    _u(1)
6857 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
6858 // -----------------------------------------------------------------------------
6859 // Field       : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW
6860 // Description : None
6861 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
6862 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
6863 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB    _u(0)
6864 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB    _u(0)
6865 #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
6866 // =============================================================================
6867 // Register    : IO_BANK0_PROC0_INTE3
6868 // Description : Interrupt Enable for proc0
6869 #define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c)
6870 #define IO_BANK0_PROC0_INTE3_BITS   _u(0x00ffffff)
6871 #define IO_BANK0_PROC0_INTE3_RESET  _u(0x00000000)
6872 // -----------------------------------------------------------------------------
6873 // Field       : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH
6874 // Description : None
6875 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
6876 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
6877 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB    _u(23)
6878 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB    _u(23)
6879 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
6880 // -----------------------------------------------------------------------------
6881 // Field       : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW
6882 // Description : None
6883 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET  _u(0x0)
6884 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
6885 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB    _u(22)
6886 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB    _u(22)
6887 #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
6888 // -----------------------------------------------------------------------------
6889 // Field       : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH
6890 // Description : None
6891 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
6892 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
6893 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB    _u(21)
6894 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB    _u(21)
6895 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
6896 // -----------------------------------------------------------------------------
6897 // Field       : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW
6898 // Description : None
6899 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
6900 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
6901 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB    _u(20)
6902 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB    _u(20)
6903 #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
6904 // -----------------------------------------------------------------------------
6905 // Field       : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH
6906 // Description : None
6907 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
6908 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
6909 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB    _u(19)
6910 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB    _u(19)
6911 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
6912 // -----------------------------------------------------------------------------
6913 // Field       : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW
6914 // Description : None
6915 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET  _u(0x0)
6916 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
6917 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB    _u(18)
6918 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB    _u(18)
6919 #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
6920 // -----------------------------------------------------------------------------
6921 // Field       : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH
6922 // Description : None
6923 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
6924 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
6925 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB    _u(17)
6926 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB    _u(17)
6927 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
6928 // -----------------------------------------------------------------------------
6929 // Field       : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW
6930 // Description : None
6931 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
6932 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
6933 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB    _u(16)
6934 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB    _u(16)
6935 #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
6936 // -----------------------------------------------------------------------------
6937 // Field       : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH
6938 // Description : None
6939 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
6940 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
6941 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB    _u(15)
6942 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB    _u(15)
6943 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
6944 // -----------------------------------------------------------------------------
6945 // Field       : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW
6946 // Description : None
6947 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET  _u(0x0)
6948 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
6949 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB    _u(14)
6950 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB    _u(14)
6951 #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
6952 // -----------------------------------------------------------------------------
6953 // Field       : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH
6954 // Description : None
6955 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
6956 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
6957 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB    _u(13)
6958 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB    _u(13)
6959 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
6960 // -----------------------------------------------------------------------------
6961 // Field       : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW
6962 // Description : None
6963 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
6964 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
6965 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB    _u(12)
6966 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB    _u(12)
6967 #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
6968 // -----------------------------------------------------------------------------
6969 // Field       : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH
6970 // Description : None
6971 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
6972 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
6973 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB    _u(11)
6974 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB    _u(11)
6975 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
6976 // -----------------------------------------------------------------------------
6977 // Field       : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW
6978 // Description : None
6979 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET  _u(0x0)
6980 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
6981 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB    _u(10)
6982 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB    _u(10)
6983 #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
6984 // -----------------------------------------------------------------------------
6985 // Field       : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH
6986 // Description : None
6987 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
6988 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
6989 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB    _u(9)
6990 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB    _u(9)
6991 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
6992 // -----------------------------------------------------------------------------
6993 // Field       : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW
6994 // Description : None
6995 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
6996 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
6997 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB    _u(8)
6998 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB    _u(8)
6999 #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
7000 // -----------------------------------------------------------------------------
7001 // Field       : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH
7002 // Description : None
7003 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
7004 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
7005 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB    _u(7)
7006 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB    _u(7)
7007 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
7008 // -----------------------------------------------------------------------------
7009 // Field       : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW
7010 // Description : None
7011 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET  _u(0x0)
7012 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
7013 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB    _u(6)
7014 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB    _u(6)
7015 #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
7016 // -----------------------------------------------------------------------------
7017 // Field       : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH
7018 // Description : None
7019 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
7020 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
7021 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB    _u(5)
7022 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB    _u(5)
7023 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
7024 // -----------------------------------------------------------------------------
7025 // Field       : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW
7026 // Description : None
7027 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
7028 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
7029 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB    _u(4)
7030 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB    _u(4)
7031 #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
7032 // -----------------------------------------------------------------------------
7033 // Field       : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH
7034 // Description : None
7035 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
7036 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
7037 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB    _u(3)
7038 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB    _u(3)
7039 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
7040 // -----------------------------------------------------------------------------
7041 // Field       : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW
7042 // Description : None
7043 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET  _u(0x0)
7044 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
7045 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB    _u(2)
7046 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB    _u(2)
7047 #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
7048 // -----------------------------------------------------------------------------
7049 // Field       : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH
7050 // Description : None
7051 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
7052 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
7053 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB    _u(1)
7054 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB    _u(1)
7055 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
7056 // -----------------------------------------------------------------------------
7057 // Field       : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW
7058 // Description : None
7059 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
7060 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
7061 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB    _u(0)
7062 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB    _u(0)
7063 #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
7064 // =============================================================================
7065 // Register    : IO_BANK0_PROC0_INTF0
7066 // Description : Interrupt Force for proc0
7067 #define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110)
7068 #define IO_BANK0_PROC0_INTF0_BITS   _u(0xffffffff)
7069 #define IO_BANK0_PROC0_INTF0_RESET  _u(0x00000000)
7070 // -----------------------------------------------------------------------------
7071 // Field       : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH
7072 // Description : None
7073 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
7074 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
7075 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB    _u(31)
7076 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB    _u(31)
7077 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
7078 // -----------------------------------------------------------------------------
7079 // Field       : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW
7080 // Description : None
7081 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET  _u(0x0)
7082 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
7083 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB    _u(30)
7084 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB    _u(30)
7085 #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
7086 // -----------------------------------------------------------------------------
7087 // Field       : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH
7088 // Description : None
7089 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
7090 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
7091 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB    _u(29)
7092 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB    _u(29)
7093 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
7094 // -----------------------------------------------------------------------------
7095 // Field       : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW
7096 // Description : None
7097 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
7098 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
7099 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB    _u(28)
7100 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB    _u(28)
7101 #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
7102 // -----------------------------------------------------------------------------
7103 // Field       : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH
7104 // Description : None
7105 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
7106 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
7107 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB    _u(27)
7108 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB    _u(27)
7109 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
7110 // -----------------------------------------------------------------------------
7111 // Field       : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW
7112 // Description : None
7113 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET  _u(0x0)
7114 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
7115 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB    _u(26)
7116 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB    _u(26)
7117 #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
7118 // -----------------------------------------------------------------------------
7119 // Field       : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH
7120 // Description : None
7121 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
7122 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
7123 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB    _u(25)
7124 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB    _u(25)
7125 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
7126 // -----------------------------------------------------------------------------
7127 // Field       : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW
7128 // Description : None
7129 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
7130 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
7131 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB    _u(24)
7132 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB    _u(24)
7133 #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
7134 // -----------------------------------------------------------------------------
7135 // Field       : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH
7136 // Description : None
7137 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
7138 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
7139 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB    _u(23)
7140 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB    _u(23)
7141 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
7142 // -----------------------------------------------------------------------------
7143 // Field       : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW
7144 // Description : None
7145 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET  _u(0x0)
7146 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
7147 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB    _u(22)
7148 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB    _u(22)
7149 #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
7150 // -----------------------------------------------------------------------------
7151 // Field       : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH
7152 // Description : None
7153 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
7154 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
7155 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB    _u(21)
7156 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB    _u(21)
7157 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
7158 // -----------------------------------------------------------------------------
7159 // Field       : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW
7160 // Description : None
7161 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
7162 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
7163 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB    _u(20)
7164 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB    _u(20)
7165 #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
7166 // -----------------------------------------------------------------------------
7167 // Field       : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH
7168 // Description : None
7169 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
7170 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
7171 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB    _u(19)
7172 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB    _u(19)
7173 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
7174 // -----------------------------------------------------------------------------
7175 // Field       : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW
7176 // Description : None
7177 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET  _u(0x0)
7178 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
7179 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB    _u(18)
7180 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB    _u(18)
7181 #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
7182 // -----------------------------------------------------------------------------
7183 // Field       : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH
7184 // Description : None
7185 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
7186 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
7187 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB    _u(17)
7188 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB    _u(17)
7189 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
7190 // -----------------------------------------------------------------------------
7191 // Field       : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW
7192 // Description : None
7193 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
7194 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
7195 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB    _u(16)
7196 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB    _u(16)
7197 #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
7198 // -----------------------------------------------------------------------------
7199 // Field       : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH
7200 // Description : None
7201 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
7202 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
7203 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB    _u(15)
7204 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB    _u(15)
7205 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
7206 // -----------------------------------------------------------------------------
7207 // Field       : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW
7208 // Description : None
7209 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET  _u(0x0)
7210 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
7211 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB    _u(14)
7212 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB    _u(14)
7213 #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
7214 // -----------------------------------------------------------------------------
7215 // Field       : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH
7216 // Description : None
7217 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
7218 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
7219 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB    _u(13)
7220 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB    _u(13)
7221 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
7222 // -----------------------------------------------------------------------------
7223 // Field       : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW
7224 // Description : None
7225 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
7226 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
7227 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB    _u(12)
7228 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB    _u(12)
7229 #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
7230 // -----------------------------------------------------------------------------
7231 // Field       : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH
7232 // Description : None
7233 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
7234 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
7235 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB    _u(11)
7236 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB    _u(11)
7237 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
7238 // -----------------------------------------------------------------------------
7239 // Field       : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW
7240 // Description : None
7241 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET  _u(0x0)
7242 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
7243 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB    _u(10)
7244 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB    _u(10)
7245 #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
7246 // -----------------------------------------------------------------------------
7247 // Field       : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH
7248 // Description : None
7249 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
7250 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
7251 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB    _u(9)
7252 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB    _u(9)
7253 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
7254 // -----------------------------------------------------------------------------
7255 // Field       : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW
7256 // Description : None
7257 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
7258 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
7259 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB    _u(8)
7260 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB    _u(8)
7261 #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
7262 // -----------------------------------------------------------------------------
7263 // Field       : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH
7264 // Description : None
7265 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
7266 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
7267 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB    _u(7)
7268 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB    _u(7)
7269 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
7270 // -----------------------------------------------------------------------------
7271 // Field       : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW
7272 // Description : None
7273 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET  _u(0x0)
7274 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
7275 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB    _u(6)
7276 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB    _u(6)
7277 #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
7278 // -----------------------------------------------------------------------------
7279 // Field       : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH
7280 // Description : None
7281 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
7282 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
7283 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB    _u(5)
7284 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB    _u(5)
7285 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
7286 // -----------------------------------------------------------------------------
7287 // Field       : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW
7288 // Description : None
7289 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
7290 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
7291 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB    _u(4)
7292 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB    _u(4)
7293 #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
7294 // -----------------------------------------------------------------------------
7295 // Field       : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH
7296 // Description : None
7297 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
7298 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
7299 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB    _u(3)
7300 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB    _u(3)
7301 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
7302 // -----------------------------------------------------------------------------
7303 // Field       : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW
7304 // Description : None
7305 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET  _u(0x0)
7306 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
7307 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB    _u(2)
7308 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB    _u(2)
7309 #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
7310 // -----------------------------------------------------------------------------
7311 // Field       : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH
7312 // Description : None
7313 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
7314 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
7315 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB    _u(1)
7316 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB    _u(1)
7317 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
7318 // -----------------------------------------------------------------------------
7319 // Field       : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW
7320 // Description : None
7321 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
7322 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
7323 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB    _u(0)
7324 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB    _u(0)
7325 #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
7326 // =============================================================================
7327 // Register    : IO_BANK0_PROC0_INTF1
7328 // Description : Interrupt Force for proc0
7329 #define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114)
7330 #define IO_BANK0_PROC0_INTF1_BITS   _u(0xffffffff)
7331 #define IO_BANK0_PROC0_INTF1_RESET  _u(0x00000000)
7332 // -----------------------------------------------------------------------------
7333 // Field       : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH
7334 // Description : None
7335 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
7336 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
7337 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB    _u(31)
7338 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB    _u(31)
7339 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
7340 // -----------------------------------------------------------------------------
7341 // Field       : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW
7342 // Description : None
7343 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET  _u(0x0)
7344 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
7345 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB    _u(30)
7346 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB    _u(30)
7347 #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
7348 // -----------------------------------------------------------------------------
7349 // Field       : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH
7350 // Description : None
7351 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
7352 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
7353 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB    _u(29)
7354 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB    _u(29)
7355 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
7356 // -----------------------------------------------------------------------------
7357 // Field       : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW
7358 // Description : None
7359 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
7360 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
7361 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB    _u(28)
7362 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB    _u(28)
7363 #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
7364 // -----------------------------------------------------------------------------
7365 // Field       : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH
7366 // Description : None
7367 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
7368 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
7369 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB    _u(27)
7370 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB    _u(27)
7371 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
7372 // -----------------------------------------------------------------------------
7373 // Field       : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW
7374 // Description : None
7375 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET  _u(0x0)
7376 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
7377 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB    _u(26)
7378 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB    _u(26)
7379 #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
7380 // -----------------------------------------------------------------------------
7381 // Field       : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH
7382 // Description : None
7383 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
7384 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
7385 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB    _u(25)
7386 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB    _u(25)
7387 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
7388 // -----------------------------------------------------------------------------
7389 // Field       : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW
7390 // Description : None
7391 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
7392 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
7393 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB    _u(24)
7394 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB    _u(24)
7395 #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
7396 // -----------------------------------------------------------------------------
7397 // Field       : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH
7398 // Description : None
7399 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
7400 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
7401 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB    _u(23)
7402 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB    _u(23)
7403 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
7404 // -----------------------------------------------------------------------------
7405 // Field       : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW
7406 // Description : None
7407 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET  _u(0x0)
7408 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
7409 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB    _u(22)
7410 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB    _u(22)
7411 #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
7412 // -----------------------------------------------------------------------------
7413 // Field       : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH
7414 // Description : None
7415 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
7416 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
7417 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB    _u(21)
7418 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB    _u(21)
7419 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
7420 // -----------------------------------------------------------------------------
7421 // Field       : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW
7422 // Description : None
7423 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
7424 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
7425 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB    _u(20)
7426 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB    _u(20)
7427 #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
7428 // -----------------------------------------------------------------------------
7429 // Field       : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH
7430 // Description : None
7431 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
7432 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
7433 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB    _u(19)
7434 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB    _u(19)
7435 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
7436 // -----------------------------------------------------------------------------
7437 // Field       : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW
7438 // Description : None
7439 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET  _u(0x0)
7440 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
7441 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB    _u(18)
7442 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB    _u(18)
7443 #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
7444 // -----------------------------------------------------------------------------
7445 // Field       : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH
7446 // Description : None
7447 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
7448 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
7449 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB    _u(17)
7450 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB    _u(17)
7451 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
7452 // -----------------------------------------------------------------------------
7453 // Field       : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW
7454 // Description : None
7455 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
7456 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
7457 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB    _u(16)
7458 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB    _u(16)
7459 #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
7460 // -----------------------------------------------------------------------------
7461 // Field       : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH
7462 // Description : None
7463 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
7464 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
7465 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB    _u(15)
7466 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB    _u(15)
7467 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
7468 // -----------------------------------------------------------------------------
7469 // Field       : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW
7470 // Description : None
7471 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET  _u(0x0)
7472 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
7473 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB    _u(14)
7474 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB    _u(14)
7475 #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
7476 // -----------------------------------------------------------------------------
7477 // Field       : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH
7478 // Description : None
7479 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
7480 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
7481 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB    _u(13)
7482 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB    _u(13)
7483 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
7484 // -----------------------------------------------------------------------------
7485 // Field       : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW
7486 // Description : None
7487 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
7488 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
7489 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB    _u(12)
7490 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB    _u(12)
7491 #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
7492 // -----------------------------------------------------------------------------
7493 // Field       : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH
7494 // Description : None
7495 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
7496 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
7497 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB    _u(11)
7498 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB    _u(11)
7499 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
7500 // -----------------------------------------------------------------------------
7501 // Field       : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW
7502 // Description : None
7503 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET  _u(0x0)
7504 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
7505 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB    _u(10)
7506 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB    _u(10)
7507 #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
7508 // -----------------------------------------------------------------------------
7509 // Field       : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH
7510 // Description : None
7511 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
7512 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
7513 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB    _u(9)
7514 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB    _u(9)
7515 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
7516 // -----------------------------------------------------------------------------
7517 // Field       : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW
7518 // Description : None
7519 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
7520 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
7521 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB    _u(8)
7522 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB    _u(8)
7523 #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
7524 // -----------------------------------------------------------------------------
7525 // Field       : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH
7526 // Description : None
7527 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
7528 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
7529 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB    _u(7)
7530 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB    _u(7)
7531 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
7532 // -----------------------------------------------------------------------------
7533 // Field       : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW
7534 // Description : None
7535 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET  _u(0x0)
7536 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
7537 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB    _u(6)
7538 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB    _u(6)
7539 #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
7540 // -----------------------------------------------------------------------------
7541 // Field       : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH
7542 // Description : None
7543 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
7544 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
7545 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB    _u(5)
7546 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB    _u(5)
7547 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
7548 // -----------------------------------------------------------------------------
7549 // Field       : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW
7550 // Description : None
7551 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
7552 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
7553 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB    _u(4)
7554 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB    _u(4)
7555 #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
7556 // -----------------------------------------------------------------------------
7557 // Field       : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH
7558 // Description : None
7559 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
7560 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
7561 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB    _u(3)
7562 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB    _u(3)
7563 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
7564 // -----------------------------------------------------------------------------
7565 // Field       : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW
7566 // Description : None
7567 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET  _u(0x0)
7568 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
7569 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB    _u(2)
7570 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB    _u(2)
7571 #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
7572 // -----------------------------------------------------------------------------
7573 // Field       : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH
7574 // Description : None
7575 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
7576 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
7577 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB    _u(1)
7578 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB    _u(1)
7579 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
7580 // -----------------------------------------------------------------------------
7581 // Field       : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW
7582 // Description : None
7583 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
7584 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
7585 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB    _u(0)
7586 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB    _u(0)
7587 #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
7588 // =============================================================================
7589 // Register    : IO_BANK0_PROC0_INTF2
7590 // Description : Interrupt Force for proc0
7591 #define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118)
7592 #define IO_BANK0_PROC0_INTF2_BITS   _u(0xffffffff)
7593 #define IO_BANK0_PROC0_INTF2_RESET  _u(0x00000000)
7594 // -----------------------------------------------------------------------------
7595 // Field       : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH
7596 // Description : None
7597 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
7598 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
7599 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB    _u(31)
7600 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB    _u(31)
7601 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
7602 // -----------------------------------------------------------------------------
7603 // Field       : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW
7604 // Description : None
7605 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET  _u(0x0)
7606 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
7607 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB    _u(30)
7608 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB    _u(30)
7609 #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
7610 // -----------------------------------------------------------------------------
7611 // Field       : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH
7612 // Description : None
7613 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
7614 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
7615 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB    _u(29)
7616 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB    _u(29)
7617 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
7618 // -----------------------------------------------------------------------------
7619 // Field       : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW
7620 // Description : None
7621 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
7622 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
7623 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB    _u(28)
7624 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB    _u(28)
7625 #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
7626 // -----------------------------------------------------------------------------
7627 // Field       : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH
7628 // Description : None
7629 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
7630 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
7631 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB    _u(27)
7632 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB    _u(27)
7633 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
7634 // -----------------------------------------------------------------------------
7635 // Field       : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW
7636 // Description : None
7637 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET  _u(0x0)
7638 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
7639 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB    _u(26)
7640 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB    _u(26)
7641 #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
7642 // -----------------------------------------------------------------------------
7643 // Field       : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH
7644 // Description : None
7645 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
7646 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
7647 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB    _u(25)
7648 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB    _u(25)
7649 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
7650 // -----------------------------------------------------------------------------
7651 // Field       : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW
7652 // Description : None
7653 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
7654 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
7655 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB    _u(24)
7656 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB    _u(24)
7657 #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
7658 // -----------------------------------------------------------------------------
7659 // Field       : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH
7660 // Description : None
7661 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
7662 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
7663 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB    _u(23)
7664 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB    _u(23)
7665 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
7666 // -----------------------------------------------------------------------------
7667 // Field       : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW
7668 // Description : None
7669 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET  _u(0x0)
7670 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
7671 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB    _u(22)
7672 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB    _u(22)
7673 #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
7674 // -----------------------------------------------------------------------------
7675 // Field       : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH
7676 // Description : None
7677 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
7678 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
7679 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB    _u(21)
7680 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB    _u(21)
7681 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
7682 // -----------------------------------------------------------------------------
7683 // Field       : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW
7684 // Description : None
7685 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
7686 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
7687 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB    _u(20)
7688 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB    _u(20)
7689 #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
7690 // -----------------------------------------------------------------------------
7691 // Field       : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH
7692 // Description : None
7693 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
7694 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
7695 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB    _u(19)
7696 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB    _u(19)
7697 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
7698 // -----------------------------------------------------------------------------
7699 // Field       : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW
7700 // Description : None
7701 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET  _u(0x0)
7702 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
7703 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB    _u(18)
7704 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB    _u(18)
7705 #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
7706 // -----------------------------------------------------------------------------
7707 // Field       : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH
7708 // Description : None
7709 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
7710 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
7711 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB    _u(17)
7712 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB    _u(17)
7713 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
7714 // -----------------------------------------------------------------------------
7715 // Field       : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW
7716 // Description : None
7717 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
7718 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
7719 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB    _u(16)
7720 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB    _u(16)
7721 #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
7722 // -----------------------------------------------------------------------------
7723 // Field       : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH
7724 // Description : None
7725 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
7726 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
7727 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB    _u(15)
7728 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB    _u(15)
7729 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
7730 // -----------------------------------------------------------------------------
7731 // Field       : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW
7732 // Description : None
7733 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET  _u(0x0)
7734 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
7735 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB    _u(14)
7736 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB    _u(14)
7737 #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
7738 // -----------------------------------------------------------------------------
7739 // Field       : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH
7740 // Description : None
7741 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
7742 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
7743 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB    _u(13)
7744 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB    _u(13)
7745 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
7746 // -----------------------------------------------------------------------------
7747 // Field       : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW
7748 // Description : None
7749 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
7750 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
7751 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB    _u(12)
7752 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB    _u(12)
7753 #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
7754 // -----------------------------------------------------------------------------
7755 // Field       : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH
7756 // Description : None
7757 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
7758 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
7759 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB    _u(11)
7760 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB    _u(11)
7761 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
7762 // -----------------------------------------------------------------------------
7763 // Field       : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW
7764 // Description : None
7765 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET  _u(0x0)
7766 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
7767 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB    _u(10)
7768 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB    _u(10)
7769 #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
7770 // -----------------------------------------------------------------------------
7771 // Field       : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH
7772 // Description : None
7773 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
7774 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
7775 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB    _u(9)
7776 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB    _u(9)
7777 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
7778 // -----------------------------------------------------------------------------
7779 // Field       : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW
7780 // Description : None
7781 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
7782 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
7783 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB    _u(8)
7784 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB    _u(8)
7785 #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
7786 // -----------------------------------------------------------------------------
7787 // Field       : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH
7788 // Description : None
7789 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
7790 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
7791 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB    _u(7)
7792 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB    _u(7)
7793 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
7794 // -----------------------------------------------------------------------------
7795 // Field       : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW
7796 // Description : None
7797 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET  _u(0x0)
7798 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
7799 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB    _u(6)
7800 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB    _u(6)
7801 #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
7802 // -----------------------------------------------------------------------------
7803 // Field       : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH
7804 // Description : None
7805 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
7806 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
7807 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB    _u(5)
7808 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB    _u(5)
7809 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
7810 // -----------------------------------------------------------------------------
7811 // Field       : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW
7812 // Description : None
7813 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
7814 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
7815 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB    _u(4)
7816 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB    _u(4)
7817 #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
7818 // -----------------------------------------------------------------------------
7819 // Field       : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH
7820 // Description : None
7821 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
7822 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
7823 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB    _u(3)
7824 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB    _u(3)
7825 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
7826 // -----------------------------------------------------------------------------
7827 // Field       : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW
7828 // Description : None
7829 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET  _u(0x0)
7830 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
7831 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB    _u(2)
7832 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB    _u(2)
7833 #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
7834 // -----------------------------------------------------------------------------
7835 // Field       : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH
7836 // Description : None
7837 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
7838 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
7839 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB    _u(1)
7840 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB    _u(1)
7841 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
7842 // -----------------------------------------------------------------------------
7843 // Field       : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW
7844 // Description : None
7845 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
7846 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
7847 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB    _u(0)
7848 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB    _u(0)
7849 #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
7850 // =============================================================================
7851 // Register    : IO_BANK0_PROC0_INTF3
7852 // Description : Interrupt Force for proc0
7853 #define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c)
7854 #define IO_BANK0_PROC0_INTF3_BITS   _u(0x00ffffff)
7855 #define IO_BANK0_PROC0_INTF3_RESET  _u(0x00000000)
7856 // -----------------------------------------------------------------------------
7857 // Field       : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH
7858 // Description : None
7859 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
7860 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
7861 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB    _u(23)
7862 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB    _u(23)
7863 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
7864 // -----------------------------------------------------------------------------
7865 // Field       : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW
7866 // Description : None
7867 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET  _u(0x0)
7868 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
7869 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB    _u(22)
7870 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB    _u(22)
7871 #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
7872 // -----------------------------------------------------------------------------
7873 // Field       : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH
7874 // Description : None
7875 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
7876 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
7877 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB    _u(21)
7878 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB    _u(21)
7879 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
7880 // -----------------------------------------------------------------------------
7881 // Field       : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW
7882 // Description : None
7883 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
7884 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
7885 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB    _u(20)
7886 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB    _u(20)
7887 #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
7888 // -----------------------------------------------------------------------------
7889 // Field       : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH
7890 // Description : None
7891 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
7892 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
7893 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB    _u(19)
7894 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB    _u(19)
7895 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
7896 // -----------------------------------------------------------------------------
7897 // Field       : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW
7898 // Description : None
7899 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET  _u(0x0)
7900 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
7901 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB    _u(18)
7902 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB    _u(18)
7903 #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
7904 // -----------------------------------------------------------------------------
7905 // Field       : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH
7906 // Description : None
7907 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
7908 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
7909 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB    _u(17)
7910 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB    _u(17)
7911 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
7912 // -----------------------------------------------------------------------------
7913 // Field       : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW
7914 // Description : None
7915 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
7916 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
7917 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB    _u(16)
7918 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB    _u(16)
7919 #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
7920 // -----------------------------------------------------------------------------
7921 // Field       : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH
7922 // Description : None
7923 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
7924 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
7925 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB    _u(15)
7926 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB    _u(15)
7927 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
7928 // -----------------------------------------------------------------------------
7929 // Field       : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW
7930 // Description : None
7931 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET  _u(0x0)
7932 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
7933 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB    _u(14)
7934 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB    _u(14)
7935 #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
7936 // -----------------------------------------------------------------------------
7937 // Field       : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH
7938 // Description : None
7939 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
7940 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
7941 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB    _u(13)
7942 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB    _u(13)
7943 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
7944 // -----------------------------------------------------------------------------
7945 // Field       : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW
7946 // Description : None
7947 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
7948 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
7949 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB    _u(12)
7950 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB    _u(12)
7951 #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
7952 // -----------------------------------------------------------------------------
7953 // Field       : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH
7954 // Description : None
7955 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
7956 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
7957 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB    _u(11)
7958 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB    _u(11)
7959 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
7960 // -----------------------------------------------------------------------------
7961 // Field       : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW
7962 // Description : None
7963 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET  _u(0x0)
7964 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
7965 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB    _u(10)
7966 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB    _u(10)
7967 #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
7968 // -----------------------------------------------------------------------------
7969 // Field       : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH
7970 // Description : None
7971 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
7972 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
7973 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB    _u(9)
7974 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB    _u(9)
7975 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
7976 // -----------------------------------------------------------------------------
7977 // Field       : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW
7978 // Description : None
7979 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
7980 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
7981 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB    _u(8)
7982 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB    _u(8)
7983 #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
7984 // -----------------------------------------------------------------------------
7985 // Field       : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH
7986 // Description : None
7987 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
7988 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
7989 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB    _u(7)
7990 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB    _u(7)
7991 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
7992 // -----------------------------------------------------------------------------
7993 // Field       : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW
7994 // Description : None
7995 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET  _u(0x0)
7996 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
7997 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB    _u(6)
7998 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB    _u(6)
7999 #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
8000 // -----------------------------------------------------------------------------
8001 // Field       : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH
8002 // Description : None
8003 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
8004 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
8005 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB    _u(5)
8006 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB    _u(5)
8007 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
8008 // -----------------------------------------------------------------------------
8009 // Field       : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW
8010 // Description : None
8011 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
8012 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
8013 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB    _u(4)
8014 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB    _u(4)
8015 #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
8016 // -----------------------------------------------------------------------------
8017 // Field       : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH
8018 // Description : None
8019 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
8020 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
8021 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB    _u(3)
8022 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB    _u(3)
8023 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
8024 // -----------------------------------------------------------------------------
8025 // Field       : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW
8026 // Description : None
8027 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET  _u(0x0)
8028 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
8029 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB    _u(2)
8030 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB    _u(2)
8031 #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
8032 // -----------------------------------------------------------------------------
8033 // Field       : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH
8034 // Description : None
8035 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
8036 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
8037 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB    _u(1)
8038 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB    _u(1)
8039 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
8040 // -----------------------------------------------------------------------------
8041 // Field       : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW
8042 // Description : None
8043 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
8044 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
8045 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB    _u(0)
8046 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB    _u(0)
8047 #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
8048 // =============================================================================
8049 // Register    : IO_BANK0_PROC0_INTS0
8050 // Description : Interrupt status after masking & forcing for proc0
8051 #define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120)
8052 #define IO_BANK0_PROC0_INTS0_BITS   _u(0xffffffff)
8053 #define IO_BANK0_PROC0_INTS0_RESET  _u(0x00000000)
8054 // -----------------------------------------------------------------------------
8055 // Field       : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH
8056 // Description : None
8057 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
8058 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
8059 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB    _u(31)
8060 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB    _u(31)
8061 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
8062 // -----------------------------------------------------------------------------
8063 // Field       : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW
8064 // Description : None
8065 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET  _u(0x0)
8066 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
8067 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB    _u(30)
8068 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB    _u(30)
8069 #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
8070 // -----------------------------------------------------------------------------
8071 // Field       : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH
8072 // Description : None
8073 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
8074 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
8075 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB    _u(29)
8076 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB    _u(29)
8077 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
8078 // -----------------------------------------------------------------------------
8079 // Field       : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW
8080 // Description : None
8081 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
8082 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
8083 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB    _u(28)
8084 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB    _u(28)
8085 #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
8086 // -----------------------------------------------------------------------------
8087 // Field       : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH
8088 // Description : None
8089 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
8090 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
8091 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB    _u(27)
8092 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB    _u(27)
8093 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
8094 // -----------------------------------------------------------------------------
8095 // Field       : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW
8096 // Description : None
8097 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET  _u(0x0)
8098 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
8099 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB    _u(26)
8100 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB    _u(26)
8101 #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
8102 // -----------------------------------------------------------------------------
8103 // Field       : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH
8104 // Description : None
8105 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
8106 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
8107 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB    _u(25)
8108 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB    _u(25)
8109 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
8110 // -----------------------------------------------------------------------------
8111 // Field       : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW
8112 // Description : None
8113 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
8114 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
8115 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB    _u(24)
8116 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB    _u(24)
8117 #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
8118 // -----------------------------------------------------------------------------
8119 // Field       : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH
8120 // Description : None
8121 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
8122 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
8123 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB    _u(23)
8124 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB    _u(23)
8125 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
8126 // -----------------------------------------------------------------------------
8127 // Field       : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW
8128 // Description : None
8129 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET  _u(0x0)
8130 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
8131 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB    _u(22)
8132 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB    _u(22)
8133 #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
8134 // -----------------------------------------------------------------------------
8135 // Field       : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH
8136 // Description : None
8137 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
8138 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
8139 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB    _u(21)
8140 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB    _u(21)
8141 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
8142 // -----------------------------------------------------------------------------
8143 // Field       : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW
8144 // Description : None
8145 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
8146 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
8147 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB    _u(20)
8148 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB    _u(20)
8149 #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
8150 // -----------------------------------------------------------------------------
8151 // Field       : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH
8152 // Description : None
8153 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
8154 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
8155 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB    _u(19)
8156 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB    _u(19)
8157 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
8158 // -----------------------------------------------------------------------------
8159 // Field       : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW
8160 // Description : None
8161 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET  _u(0x0)
8162 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
8163 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB    _u(18)
8164 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB    _u(18)
8165 #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
8166 // -----------------------------------------------------------------------------
8167 // Field       : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH
8168 // Description : None
8169 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
8170 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
8171 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB    _u(17)
8172 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB    _u(17)
8173 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
8174 // -----------------------------------------------------------------------------
8175 // Field       : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW
8176 // Description : None
8177 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
8178 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
8179 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB    _u(16)
8180 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB    _u(16)
8181 #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
8182 // -----------------------------------------------------------------------------
8183 // Field       : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH
8184 // Description : None
8185 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
8186 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
8187 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB    _u(15)
8188 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB    _u(15)
8189 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
8190 // -----------------------------------------------------------------------------
8191 // Field       : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW
8192 // Description : None
8193 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET  _u(0x0)
8194 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
8195 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB    _u(14)
8196 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB    _u(14)
8197 #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
8198 // -----------------------------------------------------------------------------
8199 // Field       : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH
8200 // Description : None
8201 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
8202 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
8203 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB    _u(13)
8204 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB    _u(13)
8205 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
8206 // -----------------------------------------------------------------------------
8207 // Field       : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW
8208 // Description : None
8209 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
8210 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
8211 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB    _u(12)
8212 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB    _u(12)
8213 #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
8214 // -----------------------------------------------------------------------------
8215 // Field       : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH
8216 // Description : None
8217 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
8218 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
8219 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB    _u(11)
8220 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB    _u(11)
8221 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
8222 // -----------------------------------------------------------------------------
8223 // Field       : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW
8224 // Description : None
8225 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET  _u(0x0)
8226 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
8227 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB    _u(10)
8228 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB    _u(10)
8229 #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
8230 // -----------------------------------------------------------------------------
8231 // Field       : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH
8232 // Description : None
8233 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
8234 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
8235 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB    _u(9)
8236 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB    _u(9)
8237 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
8238 // -----------------------------------------------------------------------------
8239 // Field       : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW
8240 // Description : None
8241 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
8242 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
8243 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB    _u(8)
8244 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB    _u(8)
8245 #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
8246 // -----------------------------------------------------------------------------
8247 // Field       : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH
8248 // Description : None
8249 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
8250 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
8251 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB    _u(7)
8252 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB    _u(7)
8253 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
8254 // -----------------------------------------------------------------------------
8255 // Field       : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW
8256 // Description : None
8257 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET  _u(0x0)
8258 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
8259 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB    _u(6)
8260 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB    _u(6)
8261 #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
8262 // -----------------------------------------------------------------------------
8263 // Field       : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH
8264 // Description : None
8265 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
8266 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
8267 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB    _u(5)
8268 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB    _u(5)
8269 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
8270 // -----------------------------------------------------------------------------
8271 // Field       : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW
8272 // Description : None
8273 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
8274 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
8275 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB    _u(4)
8276 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB    _u(4)
8277 #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
8278 // -----------------------------------------------------------------------------
8279 // Field       : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH
8280 // Description : None
8281 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
8282 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
8283 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB    _u(3)
8284 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB    _u(3)
8285 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
8286 // -----------------------------------------------------------------------------
8287 // Field       : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW
8288 // Description : None
8289 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET  _u(0x0)
8290 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
8291 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB    _u(2)
8292 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB    _u(2)
8293 #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
8294 // -----------------------------------------------------------------------------
8295 // Field       : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH
8296 // Description : None
8297 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
8298 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
8299 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB    _u(1)
8300 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB    _u(1)
8301 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
8302 // -----------------------------------------------------------------------------
8303 // Field       : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW
8304 // Description : None
8305 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
8306 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
8307 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB    _u(0)
8308 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB    _u(0)
8309 #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
8310 // =============================================================================
8311 // Register    : IO_BANK0_PROC0_INTS1
8312 // Description : Interrupt status after masking & forcing for proc0
8313 #define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124)
8314 #define IO_BANK0_PROC0_INTS1_BITS   _u(0xffffffff)
8315 #define IO_BANK0_PROC0_INTS1_RESET  _u(0x00000000)
8316 // -----------------------------------------------------------------------------
8317 // Field       : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH
8318 // Description : None
8319 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
8320 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
8321 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB    _u(31)
8322 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB    _u(31)
8323 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
8324 // -----------------------------------------------------------------------------
8325 // Field       : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW
8326 // Description : None
8327 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET  _u(0x0)
8328 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
8329 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB    _u(30)
8330 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB    _u(30)
8331 #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
8332 // -----------------------------------------------------------------------------
8333 // Field       : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH
8334 // Description : None
8335 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
8336 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
8337 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB    _u(29)
8338 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB    _u(29)
8339 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
8340 // -----------------------------------------------------------------------------
8341 // Field       : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW
8342 // Description : None
8343 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
8344 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
8345 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB    _u(28)
8346 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB    _u(28)
8347 #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
8348 // -----------------------------------------------------------------------------
8349 // Field       : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH
8350 // Description : None
8351 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
8352 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
8353 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB    _u(27)
8354 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB    _u(27)
8355 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
8356 // -----------------------------------------------------------------------------
8357 // Field       : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW
8358 // Description : None
8359 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET  _u(0x0)
8360 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
8361 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB    _u(26)
8362 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB    _u(26)
8363 #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
8364 // -----------------------------------------------------------------------------
8365 // Field       : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH
8366 // Description : None
8367 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
8368 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
8369 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB    _u(25)
8370 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB    _u(25)
8371 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
8372 // -----------------------------------------------------------------------------
8373 // Field       : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW
8374 // Description : None
8375 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
8376 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
8377 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB    _u(24)
8378 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB    _u(24)
8379 #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
8380 // -----------------------------------------------------------------------------
8381 // Field       : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH
8382 // Description : None
8383 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
8384 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
8385 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB    _u(23)
8386 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB    _u(23)
8387 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
8388 // -----------------------------------------------------------------------------
8389 // Field       : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW
8390 // Description : None
8391 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET  _u(0x0)
8392 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
8393 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB    _u(22)
8394 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB    _u(22)
8395 #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
8396 // -----------------------------------------------------------------------------
8397 // Field       : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH
8398 // Description : None
8399 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
8400 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
8401 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB    _u(21)
8402 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB    _u(21)
8403 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
8404 // -----------------------------------------------------------------------------
8405 // Field       : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW
8406 // Description : None
8407 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
8408 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
8409 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB    _u(20)
8410 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB    _u(20)
8411 #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
8412 // -----------------------------------------------------------------------------
8413 // Field       : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH
8414 // Description : None
8415 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
8416 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
8417 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB    _u(19)
8418 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB    _u(19)
8419 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
8420 // -----------------------------------------------------------------------------
8421 // Field       : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW
8422 // Description : None
8423 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET  _u(0x0)
8424 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
8425 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB    _u(18)
8426 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB    _u(18)
8427 #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
8428 // -----------------------------------------------------------------------------
8429 // Field       : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH
8430 // Description : None
8431 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
8432 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
8433 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB    _u(17)
8434 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB    _u(17)
8435 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
8436 // -----------------------------------------------------------------------------
8437 // Field       : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW
8438 // Description : None
8439 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
8440 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
8441 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB    _u(16)
8442 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB    _u(16)
8443 #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
8444 // -----------------------------------------------------------------------------
8445 // Field       : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH
8446 // Description : None
8447 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
8448 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
8449 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB    _u(15)
8450 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB    _u(15)
8451 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
8452 // -----------------------------------------------------------------------------
8453 // Field       : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW
8454 // Description : None
8455 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET  _u(0x0)
8456 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
8457 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB    _u(14)
8458 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB    _u(14)
8459 #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
8460 // -----------------------------------------------------------------------------
8461 // Field       : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH
8462 // Description : None
8463 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
8464 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
8465 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB    _u(13)
8466 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB    _u(13)
8467 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
8468 // -----------------------------------------------------------------------------
8469 // Field       : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW
8470 // Description : None
8471 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
8472 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
8473 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB    _u(12)
8474 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB    _u(12)
8475 #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
8476 // -----------------------------------------------------------------------------
8477 // Field       : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH
8478 // Description : None
8479 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
8480 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
8481 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB    _u(11)
8482 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB    _u(11)
8483 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
8484 // -----------------------------------------------------------------------------
8485 // Field       : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW
8486 // Description : None
8487 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET  _u(0x0)
8488 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
8489 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB    _u(10)
8490 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB    _u(10)
8491 #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
8492 // -----------------------------------------------------------------------------
8493 // Field       : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH
8494 // Description : None
8495 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
8496 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
8497 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB    _u(9)
8498 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB    _u(9)
8499 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
8500 // -----------------------------------------------------------------------------
8501 // Field       : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW
8502 // Description : None
8503 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
8504 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
8505 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB    _u(8)
8506 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB    _u(8)
8507 #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
8508 // -----------------------------------------------------------------------------
8509 // Field       : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH
8510 // Description : None
8511 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
8512 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
8513 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB    _u(7)
8514 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB    _u(7)
8515 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
8516 // -----------------------------------------------------------------------------
8517 // Field       : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW
8518 // Description : None
8519 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET  _u(0x0)
8520 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
8521 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB    _u(6)
8522 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB    _u(6)
8523 #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
8524 // -----------------------------------------------------------------------------
8525 // Field       : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH
8526 // Description : None
8527 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
8528 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
8529 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB    _u(5)
8530 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB    _u(5)
8531 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
8532 // -----------------------------------------------------------------------------
8533 // Field       : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW
8534 // Description : None
8535 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
8536 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
8537 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB    _u(4)
8538 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB    _u(4)
8539 #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
8540 // -----------------------------------------------------------------------------
8541 // Field       : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH
8542 // Description : None
8543 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
8544 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
8545 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB    _u(3)
8546 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB    _u(3)
8547 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
8548 // -----------------------------------------------------------------------------
8549 // Field       : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW
8550 // Description : None
8551 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET  _u(0x0)
8552 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
8553 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB    _u(2)
8554 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB    _u(2)
8555 #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
8556 // -----------------------------------------------------------------------------
8557 // Field       : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH
8558 // Description : None
8559 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
8560 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
8561 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB    _u(1)
8562 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB    _u(1)
8563 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
8564 // -----------------------------------------------------------------------------
8565 // Field       : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW
8566 // Description : None
8567 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
8568 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
8569 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB    _u(0)
8570 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB    _u(0)
8571 #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
8572 // =============================================================================
8573 // Register    : IO_BANK0_PROC0_INTS2
8574 // Description : Interrupt status after masking & forcing for proc0
8575 #define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128)
8576 #define IO_BANK0_PROC0_INTS2_BITS   _u(0xffffffff)
8577 #define IO_BANK0_PROC0_INTS2_RESET  _u(0x00000000)
8578 // -----------------------------------------------------------------------------
8579 // Field       : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH
8580 // Description : None
8581 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
8582 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
8583 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB    _u(31)
8584 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB    _u(31)
8585 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
8586 // -----------------------------------------------------------------------------
8587 // Field       : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW
8588 // Description : None
8589 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET  _u(0x0)
8590 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
8591 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB    _u(30)
8592 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB    _u(30)
8593 #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
8594 // -----------------------------------------------------------------------------
8595 // Field       : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH
8596 // Description : None
8597 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
8598 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
8599 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB    _u(29)
8600 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB    _u(29)
8601 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
8602 // -----------------------------------------------------------------------------
8603 // Field       : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW
8604 // Description : None
8605 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
8606 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
8607 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB    _u(28)
8608 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB    _u(28)
8609 #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
8610 // -----------------------------------------------------------------------------
8611 // Field       : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH
8612 // Description : None
8613 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
8614 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
8615 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB    _u(27)
8616 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB    _u(27)
8617 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
8618 // -----------------------------------------------------------------------------
8619 // Field       : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW
8620 // Description : None
8621 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET  _u(0x0)
8622 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
8623 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB    _u(26)
8624 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB    _u(26)
8625 #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
8626 // -----------------------------------------------------------------------------
8627 // Field       : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH
8628 // Description : None
8629 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
8630 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
8631 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB    _u(25)
8632 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB    _u(25)
8633 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
8634 // -----------------------------------------------------------------------------
8635 // Field       : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW
8636 // Description : None
8637 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
8638 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
8639 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB    _u(24)
8640 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB    _u(24)
8641 #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
8642 // -----------------------------------------------------------------------------
8643 // Field       : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH
8644 // Description : None
8645 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
8646 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
8647 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB    _u(23)
8648 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB    _u(23)
8649 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
8650 // -----------------------------------------------------------------------------
8651 // Field       : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW
8652 // Description : None
8653 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET  _u(0x0)
8654 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
8655 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB    _u(22)
8656 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB    _u(22)
8657 #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
8658 // -----------------------------------------------------------------------------
8659 // Field       : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH
8660 // Description : None
8661 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
8662 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
8663 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB    _u(21)
8664 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB    _u(21)
8665 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
8666 // -----------------------------------------------------------------------------
8667 // Field       : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW
8668 // Description : None
8669 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
8670 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
8671 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB    _u(20)
8672 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB    _u(20)
8673 #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
8674 // -----------------------------------------------------------------------------
8675 // Field       : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH
8676 // Description : None
8677 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
8678 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
8679 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB    _u(19)
8680 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB    _u(19)
8681 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
8682 // -----------------------------------------------------------------------------
8683 // Field       : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW
8684 // Description : None
8685 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET  _u(0x0)
8686 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
8687 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB    _u(18)
8688 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB    _u(18)
8689 #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
8690 // -----------------------------------------------------------------------------
8691 // Field       : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH
8692 // Description : None
8693 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
8694 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
8695 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB    _u(17)
8696 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB    _u(17)
8697 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
8698 // -----------------------------------------------------------------------------
8699 // Field       : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW
8700 // Description : None
8701 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
8702 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
8703 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB    _u(16)
8704 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB    _u(16)
8705 #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
8706 // -----------------------------------------------------------------------------
8707 // Field       : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH
8708 // Description : None
8709 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
8710 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
8711 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB    _u(15)
8712 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB    _u(15)
8713 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
8714 // -----------------------------------------------------------------------------
8715 // Field       : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW
8716 // Description : None
8717 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET  _u(0x0)
8718 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
8719 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB    _u(14)
8720 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB    _u(14)
8721 #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
8722 // -----------------------------------------------------------------------------
8723 // Field       : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH
8724 // Description : None
8725 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
8726 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
8727 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB    _u(13)
8728 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB    _u(13)
8729 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
8730 // -----------------------------------------------------------------------------
8731 // Field       : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW
8732 // Description : None
8733 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
8734 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
8735 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB    _u(12)
8736 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB    _u(12)
8737 #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
8738 // -----------------------------------------------------------------------------
8739 // Field       : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH
8740 // Description : None
8741 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
8742 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
8743 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB    _u(11)
8744 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB    _u(11)
8745 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
8746 // -----------------------------------------------------------------------------
8747 // Field       : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW
8748 // Description : None
8749 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET  _u(0x0)
8750 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
8751 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB    _u(10)
8752 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB    _u(10)
8753 #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
8754 // -----------------------------------------------------------------------------
8755 // Field       : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH
8756 // Description : None
8757 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
8758 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
8759 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB    _u(9)
8760 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB    _u(9)
8761 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
8762 // -----------------------------------------------------------------------------
8763 // Field       : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW
8764 // Description : None
8765 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
8766 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
8767 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB    _u(8)
8768 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB    _u(8)
8769 #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
8770 // -----------------------------------------------------------------------------
8771 // Field       : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH
8772 // Description : None
8773 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
8774 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
8775 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB    _u(7)
8776 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB    _u(7)
8777 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
8778 // -----------------------------------------------------------------------------
8779 // Field       : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW
8780 // Description : None
8781 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET  _u(0x0)
8782 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
8783 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB    _u(6)
8784 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB    _u(6)
8785 #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
8786 // -----------------------------------------------------------------------------
8787 // Field       : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH
8788 // Description : None
8789 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
8790 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
8791 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB    _u(5)
8792 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB    _u(5)
8793 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
8794 // -----------------------------------------------------------------------------
8795 // Field       : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW
8796 // Description : None
8797 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
8798 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
8799 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB    _u(4)
8800 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB    _u(4)
8801 #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
8802 // -----------------------------------------------------------------------------
8803 // Field       : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH
8804 // Description : None
8805 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
8806 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
8807 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB    _u(3)
8808 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB    _u(3)
8809 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
8810 // -----------------------------------------------------------------------------
8811 // Field       : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW
8812 // Description : None
8813 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET  _u(0x0)
8814 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
8815 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB    _u(2)
8816 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB    _u(2)
8817 #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
8818 // -----------------------------------------------------------------------------
8819 // Field       : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH
8820 // Description : None
8821 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
8822 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
8823 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB    _u(1)
8824 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB    _u(1)
8825 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
8826 // -----------------------------------------------------------------------------
8827 // Field       : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW
8828 // Description : None
8829 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
8830 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
8831 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB    _u(0)
8832 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB    _u(0)
8833 #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
8834 // =============================================================================
8835 // Register    : IO_BANK0_PROC0_INTS3
8836 // Description : Interrupt status after masking & forcing for proc0
8837 #define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c)
8838 #define IO_BANK0_PROC0_INTS3_BITS   _u(0x00ffffff)
8839 #define IO_BANK0_PROC0_INTS3_RESET  _u(0x00000000)
8840 // -----------------------------------------------------------------------------
8841 // Field       : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH
8842 // Description : None
8843 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
8844 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
8845 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB    _u(23)
8846 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB    _u(23)
8847 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
8848 // -----------------------------------------------------------------------------
8849 // Field       : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW
8850 // Description : None
8851 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET  _u(0x0)
8852 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
8853 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB    _u(22)
8854 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB    _u(22)
8855 #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
8856 // -----------------------------------------------------------------------------
8857 // Field       : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH
8858 // Description : None
8859 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
8860 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
8861 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB    _u(21)
8862 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB    _u(21)
8863 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
8864 // -----------------------------------------------------------------------------
8865 // Field       : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW
8866 // Description : None
8867 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
8868 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
8869 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB    _u(20)
8870 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB    _u(20)
8871 #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
8872 // -----------------------------------------------------------------------------
8873 // Field       : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH
8874 // Description : None
8875 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
8876 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
8877 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB    _u(19)
8878 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB    _u(19)
8879 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
8880 // -----------------------------------------------------------------------------
8881 // Field       : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW
8882 // Description : None
8883 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET  _u(0x0)
8884 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
8885 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB    _u(18)
8886 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB    _u(18)
8887 #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
8888 // -----------------------------------------------------------------------------
8889 // Field       : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH
8890 // Description : None
8891 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
8892 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
8893 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB    _u(17)
8894 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB    _u(17)
8895 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
8896 // -----------------------------------------------------------------------------
8897 // Field       : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW
8898 // Description : None
8899 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
8900 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
8901 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB    _u(16)
8902 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB    _u(16)
8903 #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
8904 // -----------------------------------------------------------------------------
8905 // Field       : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH
8906 // Description : None
8907 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
8908 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
8909 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB    _u(15)
8910 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB    _u(15)
8911 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
8912 // -----------------------------------------------------------------------------
8913 // Field       : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW
8914 // Description : None
8915 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET  _u(0x0)
8916 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
8917 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB    _u(14)
8918 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB    _u(14)
8919 #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
8920 // -----------------------------------------------------------------------------
8921 // Field       : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH
8922 // Description : None
8923 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
8924 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
8925 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB    _u(13)
8926 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB    _u(13)
8927 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
8928 // -----------------------------------------------------------------------------
8929 // Field       : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW
8930 // Description : None
8931 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
8932 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
8933 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB    _u(12)
8934 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB    _u(12)
8935 #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
8936 // -----------------------------------------------------------------------------
8937 // Field       : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH
8938 // Description : None
8939 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
8940 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
8941 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB    _u(11)
8942 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB    _u(11)
8943 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
8944 // -----------------------------------------------------------------------------
8945 // Field       : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW
8946 // Description : None
8947 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET  _u(0x0)
8948 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
8949 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB    _u(10)
8950 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB    _u(10)
8951 #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
8952 // -----------------------------------------------------------------------------
8953 // Field       : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH
8954 // Description : None
8955 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
8956 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
8957 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB    _u(9)
8958 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB    _u(9)
8959 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
8960 // -----------------------------------------------------------------------------
8961 // Field       : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW
8962 // Description : None
8963 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
8964 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
8965 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB    _u(8)
8966 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB    _u(8)
8967 #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
8968 // -----------------------------------------------------------------------------
8969 // Field       : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH
8970 // Description : None
8971 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
8972 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
8973 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB    _u(7)
8974 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB    _u(7)
8975 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
8976 // -----------------------------------------------------------------------------
8977 // Field       : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW
8978 // Description : None
8979 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET  _u(0x0)
8980 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
8981 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB    _u(6)
8982 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB    _u(6)
8983 #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
8984 // -----------------------------------------------------------------------------
8985 // Field       : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH
8986 // Description : None
8987 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
8988 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
8989 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB    _u(5)
8990 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB    _u(5)
8991 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
8992 // -----------------------------------------------------------------------------
8993 // Field       : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW
8994 // Description : None
8995 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
8996 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
8997 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB    _u(4)
8998 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB    _u(4)
8999 #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
9000 // -----------------------------------------------------------------------------
9001 // Field       : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH
9002 // Description : None
9003 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
9004 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
9005 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB    _u(3)
9006 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB    _u(3)
9007 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
9008 // -----------------------------------------------------------------------------
9009 // Field       : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW
9010 // Description : None
9011 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET  _u(0x0)
9012 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
9013 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB    _u(2)
9014 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB    _u(2)
9015 #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
9016 // -----------------------------------------------------------------------------
9017 // Field       : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH
9018 // Description : None
9019 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
9020 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
9021 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB    _u(1)
9022 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB    _u(1)
9023 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
9024 // -----------------------------------------------------------------------------
9025 // Field       : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW
9026 // Description : None
9027 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
9028 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
9029 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB    _u(0)
9030 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB    _u(0)
9031 #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
9032 // =============================================================================
9033 // Register    : IO_BANK0_PROC1_INTE0
9034 // Description : Interrupt Enable for proc1
9035 #define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130)
9036 #define IO_BANK0_PROC1_INTE0_BITS   _u(0xffffffff)
9037 #define IO_BANK0_PROC1_INTE0_RESET  _u(0x00000000)
9038 // -----------------------------------------------------------------------------
9039 // Field       : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH
9040 // Description : None
9041 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
9042 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
9043 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB    _u(31)
9044 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB    _u(31)
9045 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
9046 // -----------------------------------------------------------------------------
9047 // Field       : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW
9048 // Description : None
9049 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET  _u(0x0)
9050 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
9051 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB    _u(30)
9052 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB    _u(30)
9053 #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
9054 // -----------------------------------------------------------------------------
9055 // Field       : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH
9056 // Description : None
9057 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
9058 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
9059 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB    _u(29)
9060 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB    _u(29)
9061 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
9062 // -----------------------------------------------------------------------------
9063 // Field       : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW
9064 // Description : None
9065 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
9066 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
9067 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB    _u(28)
9068 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB    _u(28)
9069 #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
9070 // -----------------------------------------------------------------------------
9071 // Field       : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH
9072 // Description : None
9073 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
9074 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
9075 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB    _u(27)
9076 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB    _u(27)
9077 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
9078 // -----------------------------------------------------------------------------
9079 // Field       : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW
9080 // Description : None
9081 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET  _u(0x0)
9082 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
9083 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB    _u(26)
9084 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB    _u(26)
9085 #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
9086 // -----------------------------------------------------------------------------
9087 // Field       : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH
9088 // Description : None
9089 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
9090 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
9091 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB    _u(25)
9092 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB    _u(25)
9093 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
9094 // -----------------------------------------------------------------------------
9095 // Field       : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW
9096 // Description : None
9097 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
9098 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
9099 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB    _u(24)
9100 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB    _u(24)
9101 #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
9102 // -----------------------------------------------------------------------------
9103 // Field       : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH
9104 // Description : None
9105 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
9106 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
9107 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB    _u(23)
9108 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB    _u(23)
9109 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
9110 // -----------------------------------------------------------------------------
9111 // Field       : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW
9112 // Description : None
9113 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET  _u(0x0)
9114 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
9115 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB    _u(22)
9116 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB    _u(22)
9117 #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
9118 // -----------------------------------------------------------------------------
9119 // Field       : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH
9120 // Description : None
9121 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
9122 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
9123 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB    _u(21)
9124 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB    _u(21)
9125 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
9126 // -----------------------------------------------------------------------------
9127 // Field       : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW
9128 // Description : None
9129 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
9130 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
9131 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB    _u(20)
9132 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB    _u(20)
9133 #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
9134 // -----------------------------------------------------------------------------
9135 // Field       : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH
9136 // Description : None
9137 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
9138 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
9139 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB    _u(19)
9140 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB    _u(19)
9141 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
9142 // -----------------------------------------------------------------------------
9143 // Field       : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW
9144 // Description : None
9145 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET  _u(0x0)
9146 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
9147 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB    _u(18)
9148 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB    _u(18)
9149 #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
9150 // -----------------------------------------------------------------------------
9151 // Field       : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH
9152 // Description : None
9153 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
9154 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
9155 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB    _u(17)
9156 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB    _u(17)
9157 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
9158 // -----------------------------------------------------------------------------
9159 // Field       : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW
9160 // Description : None
9161 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
9162 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
9163 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB    _u(16)
9164 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB    _u(16)
9165 #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
9166 // -----------------------------------------------------------------------------
9167 // Field       : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH
9168 // Description : None
9169 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
9170 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
9171 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB    _u(15)
9172 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB    _u(15)
9173 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
9174 // -----------------------------------------------------------------------------
9175 // Field       : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW
9176 // Description : None
9177 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET  _u(0x0)
9178 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
9179 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB    _u(14)
9180 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB    _u(14)
9181 #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
9182 // -----------------------------------------------------------------------------
9183 // Field       : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH
9184 // Description : None
9185 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
9186 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
9187 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB    _u(13)
9188 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB    _u(13)
9189 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
9190 // -----------------------------------------------------------------------------
9191 // Field       : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW
9192 // Description : None
9193 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
9194 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
9195 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB    _u(12)
9196 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB    _u(12)
9197 #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
9198 // -----------------------------------------------------------------------------
9199 // Field       : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH
9200 // Description : None
9201 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
9202 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
9203 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB    _u(11)
9204 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB    _u(11)
9205 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
9206 // -----------------------------------------------------------------------------
9207 // Field       : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW
9208 // Description : None
9209 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET  _u(0x0)
9210 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
9211 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB    _u(10)
9212 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB    _u(10)
9213 #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
9214 // -----------------------------------------------------------------------------
9215 // Field       : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH
9216 // Description : None
9217 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
9218 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
9219 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB    _u(9)
9220 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB    _u(9)
9221 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
9222 // -----------------------------------------------------------------------------
9223 // Field       : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW
9224 // Description : None
9225 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
9226 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
9227 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB    _u(8)
9228 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB    _u(8)
9229 #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
9230 // -----------------------------------------------------------------------------
9231 // Field       : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH
9232 // Description : None
9233 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
9234 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
9235 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB    _u(7)
9236 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB    _u(7)
9237 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
9238 // -----------------------------------------------------------------------------
9239 // Field       : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW
9240 // Description : None
9241 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET  _u(0x0)
9242 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
9243 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB    _u(6)
9244 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB    _u(6)
9245 #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
9246 // -----------------------------------------------------------------------------
9247 // Field       : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH
9248 // Description : None
9249 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
9250 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
9251 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB    _u(5)
9252 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB    _u(5)
9253 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
9254 // -----------------------------------------------------------------------------
9255 // Field       : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW
9256 // Description : None
9257 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
9258 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
9259 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB    _u(4)
9260 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB    _u(4)
9261 #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
9262 // -----------------------------------------------------------------------------
9263 // Field       : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH
9264 // Description : None
9265 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
9266 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
9267 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB    _u(3)
9268 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB    _u(3)
9269 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
9270 // -----------------------------------------------------------------------------
9271 // Field       : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW
9272 // Description : None
9273 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET  _u(0x0)
9274 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
9275 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB    _u(2)
9276 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB    _u(2)
9277 #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
9278 // -----------------------------------------------------------------------------
9279 // Field       : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH
9280 // Description : None
9281 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
9282 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
9283 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB    _u(1)
9284 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB    _u(1)
9285 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
9286 // -----------------------------------------------------------------------------
9287 // Field       : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW
9288 // Description : None
9289 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
9290 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
9291 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB    _u(0)
9292 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB    _u(0)
9293 #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
9294 // =============================================================================
9295 // Register    : IO_BANK0_PROC1_INTE1
9296 // Description : Interrupt Enable for proc1
9297 #define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134)
9298 #define IO_BANK0_PROC1_INTE1_BITS   _u(0xffffffff)
9299 #define IO_BANK0_PROC1_INTE1_RESET  _u(0x00000000)
9300 // -----------------------------------------------------------------------------
9301 // Field       : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH
9302 // Description : None
9303 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
9304 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
9305 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB    _u(31)
9306 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB    _u(31)
9307 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
9308 // -----------------------------------------------------------------------------
9309 // Field       : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW
9310 // Description : None
9311 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET  _u(0x0)
9312 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
9313 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB    _u(30)
9314 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB    _u(30)
9315 #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
9316 // -----------------------------------------------------------------------------
9317 // Field       : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH
9318 // Description : None
9319 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
9320 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
9321 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB    _u(29)
9322 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB    _u(29)
9323 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
9324 // -----------------------------------------------------------------------------
9325 // Field       : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW
9326 // Description : None
9327 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
9328 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
9329 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB    _u(28)
9330 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB    _u(28)
9331 #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
9332 // -----------------------------------------------------------------------------
9333 // Field       : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH
9334 // Description : None
9335 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
9336 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
9337 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB    _u(27)
9338 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB    _u(27)
9339 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
9340 // -----------------------------------------------------------------------------
9341 // Field       : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW
9342 // Description : None
9343 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET  _u(0x0)
9344 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
9345 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB    _u(26)
9346 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB    _u(26)
9347 #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
9348 // -----------------------------------------------------------------------------
9349 // Field       : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH
9350 // Description : None
9351 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
9352 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
9353 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB    _u(25)
9354 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB    _u(25)
9355 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
9356 // -----------------------------------------------------------------------------
9357 // Field       : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW
9358 // Description : None
9359 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
9360 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
9361 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB    _u(24)
9362 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB    _u(24)
9363 #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
9364 // -----------------------------------------------------------------------------
9365 // Field       : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH
9366 // Description : None
9367 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
9368 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
9369 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB    _u(23)
9370 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB    _u(23)
9371 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
9372 // -----------------------------------------------------------------------------
9373 // Field       : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW
9374 // Description : None
9375 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET  _u(0x0)
9376 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
9377 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB    _u(22)
9378 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB    _u(22)
9379 #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
9380 // -----------------------------------------------------------------------------
9381 // Field       : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH
9382 // Description : None
9383 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
9384 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
9385 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB    _u(21)
9386 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB    _u(21)
9387 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
9388 // -----------------------------------------------------------------------------
9389 // Field       : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW
9390 // Description : None
9391 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
9392 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
9393 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB    _u(20)
9394 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB    _u(20)
9395 #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
9396 // -----------------------------------------------------------------------------
9397 // Field       : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH
9398 // Description : None
9399 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
9400 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
9401 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB    _u(19)
9402 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB    _u(19)
9403 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
9404 // -----------------------------------------------------------------------------
9405 // Field       : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW
9406 // Description : None
9407 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET  _u(0x0)
9408 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
9409 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB    _u(18)
9410 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB    _u(18)
9411 #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
9412 // -----------------------------------------------------------------------------
9413 // Field       : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH
9414 // Description : None
9415 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
9416 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
9417 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB    _u(17)
9418 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB    _u(17)
9419 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
9420 // -----------------------------------------------------------------------------
9421 // Field       : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW
9422 // Description : None
9423 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
9424 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
9425 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB    _u(16)
9426 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB    _u(16)
9427 #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
9428 // -----------------------------------------------------------------------------
9429 // Field       : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH
9430 // Description : None
9431 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
9432 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
9433 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB    _u(15)
9434 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB    _u(15)
9435 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
9436 // -----------------------------------------------------------------------------
9437 // Field       : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW
9438 // Description : None
9439 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET  _u(0x0)
9440 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
9441 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB    _u(14)
9442 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB    _u(14)
9443 #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
9444 // -----------------------------------------------------------------------------
9445 // Field       : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH
9446 // Description : None
9447 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
9448 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
9449 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB    _u(13)
9450 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB    _u(13)
9451 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
9452 // -----------------------------------------------------------------------------
9453 // Field       : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW
9454 // Description : None
9455 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
9456 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
9457 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB    _u(12)
9458 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB    _u(12)
9459 #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
9460 // -----------------------------------------------------------------------------
9461 // Field       : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH
9462 // Description : None
9463 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
9464 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
9465 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB    _u(11)
9466 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB    _u(11)
9467 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
9468 // -----------------------------------------------------------------------------
9469 // Field       : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW
9470 // Description : None
9471 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET  _u(0x0)
9472 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
9473 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB    _u(10)
9474 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB    _u(10)
9475 #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
9476 // -----------------------------------------------------------------------------
9477 // Field       : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH
9478 // Description : None
9479 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
9480 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
9481 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB    _u(9)
9482 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB    _u(9)
9483 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
9484 // -----------------------------------------------------------------------------
9485 // Field       : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW
9486 // Description : None
9487 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
9488 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
9489 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB    _u(8)
9490 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB    _u(8)
9491 #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
9492 // -----------------------------------------------------------------------------
9493 // Field       : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH
9494 // Description : None
9495 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
9496 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
9497 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB    _u(7)
9498 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB    _u(7)
9499 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
9500 // -----------------------------------------------------------------------------
9501 // Field       : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW
9502 // Description : None
9503 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET  _u(0x0)
9504 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
9505 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB    _u(6)
9506 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB    _u(6)
9507 #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
9508 // -----------------------------------------------------------------------------
9509 // Field       : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH
9510 // Description : None
9511 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
9512 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
9513 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB    _u(5)
9514 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB    _u(5)
9515 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
9516 // -----------------------------------------------------------------------------
9517 // Field       : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW
9518 // Description : None
9519 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
9520 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
9521 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB    _u(4)
9522 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB    _u(4)
9523 #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
9524 // -----------------------------------------------------------------------------
9525 // Field       : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH
9526 // Description : None
9527 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
9528 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
9529 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB    _u(3)
9530 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB    _u(3)
9531 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
9532 // -----------------------------------------------------------------------------
9533 // Field       : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW
9534 // Description : None
9535 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET  _u(0x0)
9536 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
9537 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB    _u(2)
9538 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB    _u(2)
9539 #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
9540 // -----------------------------------------------------------------------------
9541 // Field       : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH
9542 // Description : None
9543 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
9544 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
9545 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB    _u(1)
9546 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB    _u(1)
9547 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
9548 // -----------------------------------------------------------------------------
9549 // Field       : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW
9550 // Description : None
9551 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
9552 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
9553 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB    _u(0)
9554 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB    _u(0)
9555 #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
9556 // =============================================================================
9557 // Register    : IO_BANK0_PROC1_INTE2
9558 // Description : Interrupt Enable for proc1
9559 #define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138)
9560 #define IO_BANK0_PROC1_INTE2_BITS   _u(0xffffffff)
9561 #define IO_BANK0_PROC1_INTE2_RESET  _u(0x00000000)
9562 // -----------------------------------------------------------------------------
9563 // Field       : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH
9564 // Description : None
9565 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
9566 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
9567 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB    _u(31)
9568 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB    _u(31)
9569 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
9570 // -----------------------------------------------------------------------------
9571 // Field       : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW
9572 // Description : None
9573 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET  _u(0x0)
9574 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
9575 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB    _u(30)
9576 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB    _u(30)
9577 #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
9578 // -----------------------------------------------------------------------------
9579 // Field       : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH
9580 // Description : None
9581 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
9582 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
9583 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB    _u(29)
9584 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB    _u(29)
9585 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
9586 // -----------------------------------------------------------------------------
9587 // Field       : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW
9588 // Description : None
9589 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
9590 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
9591 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB    _u(28)
9592 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB    _u(28)
9593 #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
9594 // -----------------------------------------------------------------------------
9595 // Field       : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH
9596 // Description : None
9597 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
9598 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
9599 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB    _u(27)
9600 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB    _u(27)
9601 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
9602 // -----------------------------------------------------------------------------
9603 // Field       : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW
9604 // Description : None
9605 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET  _u(0x0)
9606 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
9607 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB    _u(26)
9608 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB    _u(26)
9609 #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
9610 // -----------------------------------------------------------------------------
9611 // Field       : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH
9612 // Description : None
9613 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
9614 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
9615 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB    _u(25)
9616 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB    _u(25)
9617 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
9618 // -----------------------------------------------------------------------------
9619 // Field       : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW
9620 // Description : None
9621 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
9622 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
9623 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB    _u(24)
9624 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB    _u(24)
9625 #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
9626 // -----------------------------------------------------------------------------
9627 // Field       : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH
9628 // Description : None
9629 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
9630 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
9631 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB    _u(23)
9632 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB    _u(23)
9633 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
9634 // -----------------------------------------------------------------------------
9635 // Field       : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW
9636 // Description : None
9637 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET  _u(0x0)
9638 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
9639 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB    _u(22)
9640 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB    _u(22)
9641 #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
9642 // -----------------------------------------------------------------------------
9643 // Field       : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH
9644 // Description : None
9645 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
9646 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
9647 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB    _u(21)
9648 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB    _u(21)
9649 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
9650 // -----------------------------------------------------------------------------
9651 // Field       : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW
9652 // Description : None
9653 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
9654 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
9655 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB    _u(20)
9656 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB    _u(20)
9657 #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
9658 // -----------------------------------------------------------------------------
9659 // Field       : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH
9660 // Description : None
9661 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
9662 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
9663 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB    _u(19)
9664 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB    _u(19)
9665 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
9666 // -----------------------------------------------------------------------------
9667 // Field       : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW
9668 // Description : None
9669 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET  _u(0x0)
9670 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
9671 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB    _u(18)
9672 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB    _u(18)
9673 #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
9674 // -----------------------------------------------------------------------------
9675 // Field       : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH
9676 // Description : None
9677 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
9678 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
9679 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB    _u(17)
9680 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB    _u(17)
9681 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
9682 // -----------------------------------------------------------------------------
9683 // Field       : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW
9684 // Description : None
9685 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
9686 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
9687 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB    _u(16)
9688 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB    _u(16)
9689 #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
9690 // -----------------------------------------------------------------------------
9691 // Field       : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH
9692 // Description : None
9693 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
9694 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
9695 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB    _u(15)
9696 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB    _u(15)
9697 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
9698 // -----------------------------------------------------------------------------
9699 // Field       : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW
9700 // Description : None
9701 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET  _u(0x0)
9702 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
9703 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB    _u(14)
9704 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB    _u(14)
9705 #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
9706 // -----------------------------------------------------------------------------
9707 // Field       : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH
9708 // Description : None
9709 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
9710 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
9711 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB    _u(13)
9712 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB    _u(13)
9713 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
9714 // -----------------------------------------------------------------------------
9715 // Field       : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW
9716 // Description : None
9717 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
9718 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
9719 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB    _u(12)
9720 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB    _u(12)
9721 #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
9722 // -----------------------------------------------------------------------------
9723 // Field       : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH
9724 // Description : None
9725 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
9726 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
9727 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB    _u(11)
9728 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB    _u(11)
9729 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
9730 // -----------------------------------------------------------------------------
9731 // Field       : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW
9732 // Description : None
9733 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET  _u(0x0)
9734 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
9735 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB    _u(10)
9736 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB    _u(10)
9737 #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
9738 // -----------------------------------------------------------------------------
9739 // Field       : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH
9740 // Description : None
9741 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
9742 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
9743 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB    _u(9)
9744 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB    _u(9)
9745 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
9746 // -----------------------------------------------------------------------------
9747 // Field       : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW
9748 // Description : None
9749 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
9750 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
9751 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB    _u(8)
9752 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB    _u(8)
9753 #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
9754 // -----------------------------------------------------------------------------
9755 // Field       : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH
9756 // Description : None
9757 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
9758 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
9759 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB    _u(7)
9760 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB    _u(7)
9761 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
9762 // -----------------------------------------------------------------------------
9763 // Field       : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW
9764 // Description : None
9765 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET  _u(0x0)
9766 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
9767 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB    _u(6)
9768 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB    _u(6)
9769 #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
9770 // -----------------------------------------------------------------------------
9771 // Field       : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH
9772 // Description : None
9773 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
9774 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
9775 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB    _u(5)
9776 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB    _u(5)
9777 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
9778 // -----------------------------------------------------------------------------
9779 // Field       : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW
9780 // Description : None
9781 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
9782 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
9783 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB    _u(4)
9784 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB    _u(4)
9785 #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
9786 // -----------------------------------------------------------------------------
9787 // Field       : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH
9788 // Description : None
9789 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
9790 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
9791 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB    _u(3)
9792 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB    _u(3)
9793 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
9794 // -----------------------------------------------------------------------------
9795 // Field       : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW
9796 // Description : None
9797 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET  _u(0x0)
9798 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
9799 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB    _u(2)
9800 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB    _u(2)
9801 #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
9802 // -----------------------------------------------------------------------------
9803 // Field       : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH
9804 // Description : None
9805 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
9806 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
9807 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB    _u(1)
9808 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB    _u(1)
9809 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
9810 // -----------------------------------------------------------------------------
9811 // Field       : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW
9812 // Description : None
9813 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
9814 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
9815 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB    _u(0)
9816 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB    _u(0)
9817 #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
9818 // =============================================================================
9819 // Register    : IO_BANK0_PROC1_INTE3
9820 // Description : Interrupt Enable for proc1
9821 #define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c)
9822 #define IO_BANK0_PROC1_INTE3_BITS   _u(0x00ffffff)
9823 #define IO_BANK0_PROC1_INTE3_RESET  _u(0x00000000)
9824 // -----------------------------------------------------------------------------
9825 // Field       : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH
9826 // Description : None
9827 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
9828 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
9829 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB    _u(23)
9830 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB    _u(23)
9831 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
9832 // -----------------------------------------------------------------------------
9833 // Field       : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW
9834 // Description : None
9835 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET  _u(0x0)
9836 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
9837 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB    _u(22)
9838 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB    _u(22)
9839 #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
9840 // -----------------------------------------------------------------------------
9841 // Field       : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH
9842 // Description : None
9843 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
9844 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
9845 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB    _u(21)
9846 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB    _u(21)
9847 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
9848 // -----------------------------------------------------------------------------
9849 // Field       : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW
9850 // Description : None
9851 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
9852 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
9853 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB    _u(20)
9854 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB    _u(20)
9855 #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
9856 // -----------------------------------------------------------------------------
9857 // Field       : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH
9858 // Description : None
9859 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
9860 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
9861 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB    _u(19)
9862 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB    _u(19)
9863 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
9864 // -----------------------------------------------------------------------------
9865 // Field       : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW
9866 // Description : None
9867 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET  _u(0x0)
9868 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
9869 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB    _u(18)
9870 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB    _u(18)
9871 #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
9872 // -----------------------------------------------------------------------------
9873 // Field       : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH
9874 // Description : None
9875 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
9876 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
9877 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB    _u(17)
9878 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB    _u(17)
9879 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
9880 // -----------------------------------------------------------------------------
9881 // Field       : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW
9882 // Description : None
9883 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
9884 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
9885 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB    _u(16)
9886 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB    _u(16)
9887 #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
9888 // -----------------------------------------------------------------------------
9889 // Field       : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH
9890 // Description : None
9891 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
9892 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
9893 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB    _u(15)
9894 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB    _u(15)
9895 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
9896 // -----------------------------------------------------------------------------
9897 // Field       : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW
9898 // Description : None
9899 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET  _u(0x0)
9900 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
9901 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB    _u(14)
9902 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB    _u(14)
9903 #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
9904 // -----------------------------------------------------------------------------
9905 // Field       : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH
9906 // Description : None
9907 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
9908 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
9909 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB    _u(13)
9910 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB    _u(13)
9911 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
9912 // -----------------------------------------------------------------------------
9913 // Field       : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW
9914 // Description : None
9915 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
9916 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
9917 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB    _u(12)
9918 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB    _u(12)
9919 #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
9920 // -----------------------------------------------------------------------------
9921 // Field       : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH
9922 // Description : None
9923 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
9924 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
9925 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB    _u(11)
9926 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB    _u(11)
9927 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
9928 // -----------------------------------------------------------------------------
9929 // Field       : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW
9930 // Description : None
9931 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET  _u(0x0)
9932 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
9933 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB    _u(10)
9934 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB    _u(10)
9935 #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
9936 // -----------------------------------------------------------------------------
9937 // Field       : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH
9938 // Description : None
9939 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
9940 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
9941 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB    _u(9)
9942 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB    _u(9)
9943 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
9944 // -----------------------------------------------------------------------------
9945 // Field       : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW
9946 // Description : None
9947 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
9948 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
9949 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB    _u(8)
9950 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB    _u(8)
9951 #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
9952 // -----------------------------------------------------------------------------
9953 // Field       : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH
9954 // Description : None
9955 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
9956 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
9957 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB    _u(7)
9958 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB    _u(7)
9959 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
9960 // -----------------------------------------------------------------------------
9961 // Field       : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW
9962 // Description : None
9963 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET  _u(0x0)
9964 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
9965 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB    _u(6)
9966 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB    _u(6)
9967 #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
9968 // -----------------------------------------------------------------------------
9969 // Field       : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH
9970 // Description : None
9971 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
9972 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
9973 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB    _u(5)
9974 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB    _u(5)
9975 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
9976 // -----------------------------------------------------------------------------
9977 // Field       : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW
9978 // Description : None
9979 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
9980 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
9981 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB    _u(4)
9982 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB    _u(4)
9983 #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
9984 // -----------------------------------------------------------------------------
9985 // Field       : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH
9986 // Description : None
9987 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
9988 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
9989 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB    _u(3)
9990 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB    _u(3)
9991 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
9992 // -----------------------------------------------------------------------------
9993 // Field       : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW
9994 // Description : None
9995 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET  _u(0x0)
9996 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
9997 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB    _u(2)
9998 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB    _u(2)
9999 #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
10000 // -----------------------------------------------------------------------------
10001 // Field       : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH
10002 // Description : None
10003 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
10004 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
10005 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB    _u(1)
10006 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB    _u(1)
10007 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
10008 // -----------------------------------------------------------------------------
10009 // Field       : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW
10010 // Description : None
10011 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
10012 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
10013 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB    _u(0)
10014 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB    _u(0)
10015 #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
10016 // =============================================================================
10017 // Register    : IO_BANK0_PROC1_INTF0
10018 // Description : Interrupt Force for proc1
10019 #define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140)
10020 #define IO_BANK0_PROC1_INTF0_BITS   _u(0xffffffff)
10021 #define IO_BANK0_PROC1_INTF0_RESET  _u(0x00000000)
10022 // -----------------------------------------------------------------------------
10023 // Field       : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH
10024 // Description : None
10025 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
10026 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
10027 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB    _u(31)
10028 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB    _u(31)
10029 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
10030 // -----------------------------------------------------------------------------
10031 // Field       : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW
10032 // Description : None
10033 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET  _u(0x0)
10034 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
10035 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB    _u(30)
10036 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB    _u(30)
10037 #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
10038 // -----------------------------------------------------------------------------
10039 // Field       : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH
10040 // Description : None
10041 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
10042 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
10043 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB    _u(29)
10044 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB    _u(29)
10045 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
10046 // -----------------------------------------------------------------------------
10047 // Field       : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW
10048 // Description : None
10049 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
10050 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
10051 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB    _u(28)
10052 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB    _u(28)
10053 #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
10054 // -----------------------------------------------------------------------------
10055 // Field       : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH
10056 // Description : None
10057 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
10058 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
10059 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB    _u(27)
10060 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB    _u(27)
10061 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
10062 // -----------------------------------------------------------------------------
10063 // Field       : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW
10064 // Description : None
10065 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET  _u(0x0)
10066 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
10067 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB    _u(26)
10068 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB    _u(26)
10069 #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
10070 // -----------------------------------------------------------------------------
10071 // Field       : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH
10072 // Description : None
10073 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
10074 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
10075 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB    _u(25)
10076 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB    _u(25)
10077 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
10078 // -----------------------------------------------------------------------------
10079 // Field       : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW
10080 // Description : None
10081 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
10082 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
10083 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB    _u(24)
10084 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB    _u(24)
10085 #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
10086 // -----------------------------------------------------------------------------
10087 // Field       : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH
10088 // Description : None
10089 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
10090 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
10091 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB    _u(23)
10092 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB    _u(23)
10093 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
10094 // -----------------------------------------------------------------------------
10095 // Field       : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW
10096 // Description : None
10097 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET  _u(0x0)
10098 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
10099 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB    _u(22)
10100 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB    _u(22)
10101 #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
10102 // -----------------------------------------------------------------------------
10103 // Field       : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH
10104 // Description : None
10105 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
10106 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
10107 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB    _u(21)
10108 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB    _u(21)
10109 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
10110 // -----------------------------------------------------------------------------
10111 // Field       : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW
10112 // Description : None
10113 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
10114 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
10115 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB    _u(20)
10116 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB    _u(20)
10117 #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
10118 // -----------------------------------------------------------------------------
10119 // Field       : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH
10120 // Description : None
10121 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
10122 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
10123 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB    _u(19)
10124 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB    _u(19)
10125 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
10126 // -----------------------------------------------------------------------------
10127 // Field       : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW
10128 // Description : None
10129 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET  _u(0x0)
10130 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
10131 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB    _u(18)
10132 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB    _u(18)
10133 #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
10134 // -----------------------------------------------------------------------------
10135 // Field       : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH
10136 // Description : None
10137 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
10138 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
10139 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB    _u(17)
10140 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB    _u(17)
10141 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
10142 // -----------------------------------------------------------------------------
10143 // Field       : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW
10144 // Description : None
10145 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
10146 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
10147 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB    _u(16)
10148 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB    _u(16)
10149 #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
10150 // -----------------------------------------------------------------------------
10151 // Field       : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH
10152 // Description : None
10153 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
10154 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
10155 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB    _u(15)
10156 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB    _u(15)
10157 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
10158 // -----------------------------------------------------------------------------
10159 // Field       : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW
10160 // Description : None
10161 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET  _u(0x0)
10162 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
10163 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB    _u(14)
10164 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB    _u(14)
10165 #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
10166 // -----------------------------------------------------------------------------
10167 // Field       : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH
10168 // Description : None
10169 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
10170 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
10171 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB    _u(13)
10172 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB    _u(13)
10173 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
10174 // -----------------------------------------------------------------------------
10175 // Field       : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW
10176 // Description : None
10177 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
10178 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
10179 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB    _u(12)
10180 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB    _u(12)
10181 #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
10182 // -----------------------------------------------------------------------------
10183 // Field       : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH
10184 // Description : None
10185 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
10186 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
10187 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB    _u(11)
10188 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB    _u(11)
10189 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
10190 // -----------------------------------------------------------------------------
10191 // Field       : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW
10192 // Description : None
10193 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET  _u(0x0)
10194 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
10195 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB    _u(10)
10196 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB    _u(10)
10197 #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
10198 // -----------------------------------------------------------------------------
10199 // Field       : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH
10200 // Description : None
10201 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
10202 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
10203 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB    _u(9)
10204 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB    _u(9)
10205 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
10206 // -----------------------------------------------------------------------------
10207 // Field       : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW
10208 // Description : None
10209 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
10210 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
10211 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB    _u(8)
10212 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB    _u(8)
10213 #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
10214 // -----------------------------------------------------------------------------
10215 // Field       : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH
10216 // Description : None
10217 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
10218 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
10219 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB    _u(7)
10220 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB    _u(7)
10221 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
10222 // -----------------------------------------------------------------------------
10223 // Field       : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW
10224 // Description : None
10225 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET  _u(0x0)
10226 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
10227 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB    _u(6)
10228 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB    _u(6)
10229 #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
10230 // -----------------------------------------------------------------------------
10231 // Field       : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH
10232 // Description : None
10233 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
10234 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
10235 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB    _u(5)
10236 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB    _u(5)
10237 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
10238 // -----------------------------------------------------------------------------
10239 // Field       : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW
10240 // Description : None
10241 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
10242 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
10243 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB    _u(4)
10244 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB    _u(4)
10245 #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
10246 // -----------------------------------------------------------------------------
10247 // Field       : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH
10248 // Description : None
10249 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
10250 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
10251 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB    _u(3)
10252 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB    _u(3)
10253 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
10254 // -----------------------------------------------------------------------------
10255 // Field       : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW
10256 // Description : None
10257 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET  _u(0x0)
10258 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
10259 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB    _u(2)
10260 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB    _u(2)
10261 #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
10262 // -----------------------------------------------------------------------------
10263 // Field       : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH
10264 // Description : None
10265 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
10266 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
10267 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB    _u(1)
10268 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB    _u(1)
10269 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
10270 // -----------------------------------------------------------------------------
10271 // Field       : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW
10272 // Description : None
10273 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
10274 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
10275 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB    _u(0)
10276 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB    _u(0)
10277 #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
10278 // =============================================================================
10279 // Register    : IO_BANK0_PROC1_INTF1
10280 // Description : Interrupt Force for proc1
10281 #define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144)
10282 #define IO_BANK0_PROC1_INTF1_BITS   _u(0xffffffff)
10283 #define IO_BANK0_PROC1_INTF1_RESET  _u(0x00000000)
10284 // -----------------------------------------------------------------------------
10285 // Field       : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH
10286 // Description : None
10287 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
10288 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
10289 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB    _u(31)
10290 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB    _u(31)
10291 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
10292 // -----------------------------------------------------------------------------
10293 // Field       : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW
10294 // Description : None
10295 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET  _u(0x0)
10296 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
10297 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB    _u(30)
10298 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB    _u(30)
10299 #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
10300 // -----------------------------------------------------------------------------
10301 // Field       : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH
10302 // Description : None
10303 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
10304 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
10305 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB    _u(29)
10306 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB    _u(29)
10307 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
10308 // -----------------------------------------------------------------------------
10309 // Field       : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW
10310 // Description : None
10311 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
10312 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
10313 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB    _u(28)
10314 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB    _u(28)
10315 #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
10316 // -----------------------------------------------------------------------------
10317 // Field       : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH
10318 // Description : None
10319 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
10320 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
10321 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB    _u(27)
10322 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB    _u(27)
10323 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
10324 // -----------------------------------------------------------------------------
10325 // Field       : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW
10326 // Description : None
10327 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET  _u(0x0)
10328 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
10329 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB    _u(26)
10330 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB    _u(26)
10331 #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
10332 // -----------------------------------------------------------------------------
10333 // Field       : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH
10334 // Description : None
10335 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
10336 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
10337 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB    _u(25)
10338 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB    _u(25)
10339 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
10340 // -----------------------------------------------------------------------------
10341 // Field       : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW
10342 // Description : None
10343 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
10344 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
10345 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB    _u(24)
10346 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB    _u(24)
10347 #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
10348 // -----------------------------------------------------------------------------
10349 // Field       : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH
10350 // Description : None
10351 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
10352 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
10353 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB    _u(23)
10354 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB    _u(23)
10355 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
10356 // -----------------------------------------------------------------------------
10357 // Field       : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW
10358 // Description : None
10359 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET  _u(0x0)
10360 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
10361 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB    _u(22)
10362 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB    _u(22)
10363 #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
10364 // -----------------------------------------------------------------------------
10365 // Field       : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH
10366 // Description : None
10367 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
10368 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
10369 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB    _u(21)
10370 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB    _u(21)
10371 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
10372 // -----------------------------------------------------------------------------
10373 // Field       : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW
10374 // Description : None
10375 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
10376 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
10377 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB    _u(20)
10378 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB    _u(20)
10379 #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
10380 // -----------------------------------------------------------------------------
10381 // Field       : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH
10382 // Description : None
10383 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
10384 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
10385 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB    _u(19)
10386 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB    _u(19)
10387 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
10388 // -----------------------------------------------------------------------------
10389 // Field       : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW
10390 // Description : None
10391 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET  _u(0x0)
10392 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
10393 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB    _u(18)
10394 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB    _u(18)
10395 #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
10396 // -----------------------------------------------------------------------------
10397 // Field       : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH
10398 // Description : None
10399 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
10400 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
10401 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB    _u(17)
10402 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB    _u(17)
10403 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
10404 // -----------------------------------------------------------------------------
10405 // Field       : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW
10406 // Description : None
10407 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
10408 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
10409 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB    _u(16)
10410 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB    _u(16)
10411 #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
10412 // -----------------------------------------------------------------------------
10413 // Field       : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH
10414 // Description : None
10415 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
10416 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
10417 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB    _u(15)
10418 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB    _u(15)
10419 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
10420 // -----------------------------------------------------------------------------
10421 // Field       : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW
10422 // Description : None
10423 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET  _u(0x0)
10424 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
10425 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB    _u(14)
10426 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB    _u(14)
10427 #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
10428 // -----------------------------------------------------------------------------
10429 // Field       : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH
10430 // Description : None
10431 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
10432 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
10433 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB    _u(13)
10434 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB    _u(13)
10435 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
10436 // -----------------------------------------------------------------------------
10437 // Field       : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW
10438 // Description : None
10439 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
10440 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
10441 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB    _u(12)
10442 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB    _u(12)
10443 #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
10444 // -----------------------------------------------------------------------------
10445 // Field       : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH
10446 // Description : None
10447 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
10448 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
10449 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB    _u(11)
10450 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB    _u(11)
10451 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
10452 // -----------------------------------------------------------------------------
10453 // Field       : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW
10454 // Description : None
10455 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET  _u(0x0)
10456 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
10457 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB    _u(10)
10458 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB    _u(10)
10459 #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
10460 // -----------------------------------------------------------------------------
10461 // Field       : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH
10462 // Description : None
10463 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
10464 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
10465 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB    _u(9)
10466 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB    _u(9)
10467 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
10468 // -----------------------------------------------------------------------------
10469 // Field       : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW
10470 // Description : None
10471 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
10472 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
10473 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB    _u(8)
10474 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB    _u(8)
10475 #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
10476 // -----------------------------------------------------------------------------
10477 // Field       : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH
10478 // Description : None
10479 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
10480 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
10481 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB    _u(7)
10482 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB    _u(7)
10483 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
10484 // -----------------------------------------------------------------------------
10485 // Field       : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW
10486 // Description : None
10487 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET  _u(0x0)
10488 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
10489 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB    _u(6)
10490 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB    _u(6)
10491 #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
10492 // -----------------------------------------------------------------------------
10493 // Field       : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH
10494 // Description : None
10495 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
10496 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
10497 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB    _u(5)
10498 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB    _u(5)
10499 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
10500 // -----------------------------------------------------------------------------
10501 // Field       : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW
10502 // Description : None
10503 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
10504 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
10505 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB    _u(4)
10506 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB    _u(4)
10507 #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
10508 // -----------------------------------------------------------------------------
10509 // Field       : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH
10510 // Description : None
10511 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
10512 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
10513 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB    _u(3)
10514 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB    _u(3)
10515 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
10516 // -----------------------------------------------------------------------------
10517 // Field       : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW
10518 // Description : None
10519 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET  _u(0x0)
10520 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
10521 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB    _u(2)
10522 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB    _u(2)
10523 #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
10524 // -----------------------------------------------------------------------------
10525 // Field       : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH
10526 // Description : None
10527 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
10528 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
10529 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB    _u(1)
10530 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB    _u(1)
10531 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
10532 // -----------------------------------------------------------------------------
10533 // Field       : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW
10534 // Description : None
10535 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
10536 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
10537 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB    _u(0)
10538 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB    _u(0)
10539 #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
10540 // =============================================================================
10541 // Register    : IO_BANK0_PROC1_INTF2
10542 // Description : Interrupt Force for proc1
10543 #define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148)
10544 #define IO_BANK0_PROC1_INTF2_BITS   _u(0xffffffff)
10545 #define IO_BANK0_PROC1_INTF2_RESET  _u(0x00000000)
10546 // -----------------------------------------------------------------------------
10547 // Field       : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH
10548 // Description : None
10549 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
10550 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
10551 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB    _u(31)
10552 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB    _u(31)
10553 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
10554 // -----------------------------------------------------------------------------
10555 // Field       : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW
10556 // Description : None
10557 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET  _u(0x0)
10558 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
10559 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB    _u(30)
10560 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB    _u(30)
10561 #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
10562 // -----------------------------------------------------------------------------
10563 // Field       : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH
10564 // Description : None
10565 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
10566 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
10567 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB    _u(29)
10568 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB    _u(29)
10569 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
10570 // -----------------------------------------------------------------------------
10571 // Field       : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW
10572 // Description : None
10573 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
10574 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
10575 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB    _u(28)
10576 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB    _u(28)
10577 #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
10578 // -----------------------------------------------------------------------------
10579 // Field       : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH
10580 // Description : None
10581 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
10582 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
10583 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB    _u(27)
10584 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB    _u(27)
10585 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
10586 // -----------------------------------------------------------------------------
10587 // Field       : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW
10588 // Description : None
10589 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET  _u(0x0)
10590 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
10591 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB    _u(26)
10592 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB    _u(26)
10593 #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
10594 // -----------------------------------------------------------------------------
10595 // Field       : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH
10596 // Description : None
10597 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
10598 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
10599 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB    _u(25)
10600 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB    _u(25)
10601 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
10602 // -----------------------------------------------------------------------------
10603 // Field       : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW
10604 // Description : None
10605 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
10606 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
10607 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB    _u(24)
10608 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB    _u(24)
10609 #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
10610 // -----------------------------------------------------------------------------
10611 // Field       : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH
10612 // Description : None
10613 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
10614 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
10615 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB    _u(23)
10616 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB    _u(23)
10617 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
10618 // -----------------------------------------------------------------------------
10619 // Field       : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW
10620 // Description : None
10621 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET  _u(0x0)
10622 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
10623 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB    _u(22)
10624 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB    _u(22)
10625 #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
10626 // -----------------------------------------------------------------------------
10627 // Field       : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH
10628 // Description : None
10629 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
10630 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
10631 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB    _u(21)
10632 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB    _u(21)
10633 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
10634 // -----------------------------------------------------------------------------
10635 // Field       : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW
10636 // Description : None
10637 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
10638 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
10639 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB    _u(20)
10640 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB    _u(20)
10641 #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
10642 // -----------------------------------------------------------------------------
10643 // Field       : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH
10644 // Description : None
10645 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
10646 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
10647 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB    _u(19)
10648 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB    _u(19)
10649 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
10650 // -----------------------------------------------------------------------------
10651 // Field       : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW
10652 // Description : None
10653 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET  _u(0x0)
10654 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
10655 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB    _u(18)
10656 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB    _u(18)
10657 #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
10658 // -----------------------------------------------------------------------------
10659 // Field       : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH
10660 // Description : None
10661 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
10662 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
10663 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB    _u(17)
10664 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB    _u(17)
10665 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
10666 // -----------------------------------------------------------------------------
10667 // Field       : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW
10668 // Description : None
10669 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
10670 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
10671 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB    _u(16)
10672 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB    _u(16)
10673 #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
10674 // -----------------------------------------------------------------------------
10675 // Field       : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH
10676 // Description : None
10677 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
10678 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
10679 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB    _u(15)
10680 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB    _u(15)
10681 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
10682 // -----------------------------------------------------------------------------
10683 // Field       : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW
10684 // Description : None
10685 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET  _u(0x0)
10686 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
10687 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB    _u(14)
10688 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB    _u(14)
10689 #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
10690 // -----------------------------------------------------------------------------
10691 // Field       : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH
10692 // Description : None
10693 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
10694 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
10695 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB    _u(13)
10696 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB    _u(13)
10697 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
10698 // -----------------------------------------------------------------------------
10699 // Field       : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW
10700 // Description : None
10701 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
10702 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
10703 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB    _u(12)
10704 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB    _u(12)
10705 #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
10706 // -----------------------------------------------------------------------------
10707 // Field       : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH
10708 // Description : None
10709 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
10710 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
10711 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB    _u(11)
10712 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB    _u(11)
10713 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
10714 // -----------------------------------------------------------------------------
10715 // Field       : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW
10716 // Description : None
10717 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET  _u(0x0)
10718 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
10719 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB    _u(10)
10720 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB    _u(10)
10721 #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
10722 // -----------------------------------------------------------------------------
10723 // Field       : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH
10724 // Description : None
10725 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
10726 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
10727 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB    _u(9)
10728 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB    _u(9)
10729 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
10730 // -----------------------------------------------------------------------------
10731 // Field       : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW
10732 // Description : None
10733 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
10734 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
10735 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB    _u(8)
10736 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB    _u(8)
10737 #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
10738 // -----------------------------------------------------------------------------
10739 // Field       : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH
10740 // Description : None
10741 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
10742 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
10743 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB    _u(7)
10744 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB    _u(7)
10745 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
10746 // -----------------------------------------------------------------------------
10747 // Field       : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW
10748 // Description : None
10749 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET  _u(0x0)
10750 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
10751 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB    _u(6)
10752 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB    _u(6)
10753 #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
10754 // -----------------------------------------------------------------------------
10755 // Field       : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH
10756 // Description : None
10757 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
10758 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
10759 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB    _u(5)
10760 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB    _u(5)
10761 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
10762 // -----------------------------------------------------------------------------
10763 // Field       : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW
10764 // Description : None
10765 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
10766 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
10767 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB    _u(4)
10768 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB    _u(4)
10769 #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
10770 // -----------------------------------------------------------------------------
10771 // Field       : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH
10772 // Description : None
10773 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
10774 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
10775 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB    _u(3)
10776 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB    _u(3)
10777 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
10778 // -----------------------------------------------------------------------------
10779 // Field       : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW
10780 // Description : None
10781 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET  _u(0x0)
10782 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
10783 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB    _u(2)
10784 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB    _u(2)
10785 #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
10786 // -----------------------------------------------------------------------------
10787 // Field       : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH
10788 // Description : None
10789 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
10790 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
10791 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB    _u(1)
10792 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB    _u(1)
10793 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
10794 // -----------------------------------------------------------------------------
10795 // Field       : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW
10796 // Description : None
10797 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
10798 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
10799 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB    _u(0)
10800 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB    _u(0)
10801 #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
10802 // =============================================================================
10803 // Register    : IO_BANK0_PROC1_INTF3
10804 // Description : Interrupt Force for proc1
10805 #define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c)
10806 #define IO_BANK0_PROC1_INTF3_BITS   _u(0x00ffffff)
10807 #define IO_BANK0_PROC1_INTF3_RESET  _u(0x00000000)
10808 // -----------------------------------------------------------------------------
10809 // Field       : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH
10810 // Description : None
10811 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
10812 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
10813 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB    _u(23)
10814 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB    _u(23)
10815 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
10816 // -----------------------------------------------------------------------------
10817 // Field       : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW
10818 // Description : None
10819 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET  _u(0x0)
10820 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
10821 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB    _u(22)
10822 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB    _u(22)
10823 #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
10824 // -----------------------------------------------------------------------------
10825 // Field       : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH
10826 // Description : None
10827 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
10828 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
10829 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB    _u(21)
10830 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB    _u(21)
10831 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
10832 // -----------------------------------------------------------------------------
10833 // Field       : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW
10834 // Description : None
10835 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
10836 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
10837 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB    _u(20)
10838 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB    _u(20)
10839 #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
10840 // -----------------------------------------------------------------------------
10841 // Field       : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH
10842 // Description : None
10843 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
10844 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
10845 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB    _u(19)
10846 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB    _u(19)
10847 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
10848 // -----------------------------------------------------------------------------
10849 // Field       : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW
10850 // Description : None
10851 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET  _u(0x0)
10852 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
10853 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB    _u(18)
10854 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB    _u(18)
10855 #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
10856 // -----------------------------------------------------------------------------
10857 // Field       : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH
10858 // Description : None
10859 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
10860 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
10861 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB    _u(17)
10862 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB    _u(17)
10863 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
10864 // -----------------------------------------------------------------------------
10865 // Field       : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW
10866 // Description : None
10867 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
10868 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
10869 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB    _u(16)
10870 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB    _u(16)
10871 #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
10872 // -----------------------------------------------------------------------------
10873 // Field       : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH
10874 // Description : None
10875 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
10876 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
10877 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB    _u(15)
10878 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB    _u(15)
10879 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
10880 // -----------------------------------------------------------------------------
10881 // Field       : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW
10882 // Description : None
10883 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET  _u(0x0)
10884 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
10885 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB    _u(14)
10886 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB    _u(14)
10887 #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
10888 // -----------------------------------------------------------------------------
10889 // Field       : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH
10890 // Description : None
10891 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
10892 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
10893 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB    _u(13)
10894 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB    _u(13)
10895 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
10896 // -----------------------------------------------------------------------------
10897 // Field       : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW
10898 // Description : None
10899 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
10900 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
10901 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB    _u(12)
10902 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB    _u(12)
10903 #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
10904 // -----------------------------------------------------------------------------
10905 // Field       : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH
10906 // Description : None
10907 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
10908 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
10909 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB    _u(11)
10910 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB    _u(11)
10911 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
10912 // -----------------------------------------------------------------------------
10913 // Field       : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW
10914 // Description : None
10915 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET  _u(0x0)
10916 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
10917 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB    _u(10)
10918 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB    _u(10)
10919 #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
10920 // -----------------------------------------------------------------------------
10921 // Field       : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH
10922 // Description : None
10923 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
10924 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
10925 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB    _u(9)
10926 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB    _u(9)
10927 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
10928 // -----------------------------------------------------------------------------
10929 // Field       : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW
10930 // Description : None
10931 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
10932 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
10933 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB    _u(8)
10934 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB    _u(8)
10935 #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
10936 // -----------------------------------------------------------------------------
10937 // Field       : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH
10938 // Description : None
10939 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
10940 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
10941 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB    _u(7)
10942 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB    _u(7)
10943 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
10944 // -----------------------------------------------------------------------------
10945 // Field       : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW
10946 // Description : None
10947 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET  _u(0x0)
10948 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
10949 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB    _u(6)
10950 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB    _u(6)
10951 #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
10952 // -----------------------------------------------------------------------------
10953 // Field       : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH
10954 // Description : None
10955 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
10956 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
10957 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB    _u(5)
10958 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB    _u(5)
10959 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
10960 // -----------------------------------------------------------------------------
10961 // Field       : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW
10962 // Description : None
10963 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
10964 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
10965 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB    _u(4)
10966 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB    _u(4)
10967 #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
10968 // -----------------------------------------------------------------------------
10969 // Field       : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH
10970 // Description : None
10971 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
10972 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
10973 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB    _u(3)
10974 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB    _u(3)
10975 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
10976 // -----------------------------------------------------------------------------
10977 // Field       : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW
10978 // Description : None
10979 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET  _u(0x0)
10980 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
10981 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB    _u(2)
10982 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB    _u(2)
10983 #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
10984 // -----------------------------------------------------------------------------
10985 // Field       : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH
10986 // Description : None
10987 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
10988 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
10989 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB    _u(1)
10990 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB    _u(1)
10991 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
10992 // -----------------------------------------------------------------------------
10993 // Field       : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW
10994 // Description : None
10995 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
10996 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
10997 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB    _u(0)
10998 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB    _u(0)
10999 #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
11000 // =============================================================================
11001 // Register    : IO_BANK0_PROC1_INTS0
11002 // Description : Interrupt status after masking & forcing for proc1
11003 #define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150)
11004 #define IO_BANK0_PROC1_INTS0_BITS   _u(0xffffffff)
11005 #define IO_BANK0_PROC1_INTS0_RESET  _u(0x00000000)
11006 // -----------------------------------------------------------------------------
11007 // Field       : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH
11008 // Description : None
11009 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
11010 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
11011 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB    _u(31)
11012 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB    _u(31)
11013 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
11014 // -----------------------------------------------------------------------------
11015 // Field       : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW
11016 // Description : None
11017 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET  _u(0x0)
11018 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
11019 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB    _u(30)
11020 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB    _u(30)
11021 #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
11022 // -----------------------------------------------------------------------------
11023 // Field       : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH
11024 // Description : None
11025 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
11026 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
11027 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB    _u(29)
11028 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB    _u(29)
11029 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
11030 // -----------------------------------------------------------------------------
11031 // Field       : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW
11032 // Description : None
11033 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
11034 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
11035 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB    _u(28)
11036 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB    _u(28)
11037 #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
11038 // -----------------------------------------------------------------------------
11039 // Field       : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH
11040 // Description : None
11041 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
11042 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
11043 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB    _u(27)
11044 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB    _u(27)
11045 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
11046 // -----------------------------------------------------------------------------
11047 // Field       : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW
11048 // Description : None
11049 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET  _u(0x0)
11050 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
11051 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB    _u(26)
11052 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB    _u(26)
11053 #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
11054 // -----------------------------------------------------------------------------
11055 // Field       : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH
11056 // Description : None
11057 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
11058 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
11059 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB    _u(25)
11060 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB    _u(25)
11061 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
11062 // -----------------------------------------------------------------------------
11063 // Field       : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW
11064 // Description : None
11065 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
11066 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
11067 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB    _u(24)
11068 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB    _u(24)
11069 #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
11070 // -----------------------------------------------------------------------------
11071 // Field       : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH
11072 // Description : None
11073 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
11074 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
11075 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB    _u(23)
11076 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB    _u(23)
11077 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
11078 // -----------------------------------------------------------------------------
11079 // Field       : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW
11080 // Description : None
11081 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET  _u(0x0)
11082 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
11083 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB    _u(22)
11084 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB    _u(22)
11085 #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
11086 // -----------------------------------------------------------------------------
11087 // Field       : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH
11088 // Description : None
11089 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
11090 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
11091 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB    _u(21)
11092 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB    _u(21)
11093 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
11094 // -----------------------------------------------------------------------------
11095 // Field       : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW
11096 // Description : None
11097 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
11098 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
11099 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB    _u(20)
11100 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB    _u(20)
11101 #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
11102 // -----------------------------------------------------------------------------
11103 // Field       : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH
11104 // Description : None
11105 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
11106 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
11107 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB    _u(19)
11108 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB    _u(19)
11109 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
11110 // -----------------------------------------------------------------------------
11111 // Field       : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW
11112 // Description : None
11113 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET  _u(0x0)
11114 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
11115 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB    _u(18)
11116 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB    _u(18)
11117 #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
11118 // -----------------------------------------------------------------------------
11119 // Field       : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH
11120 // Description : None
11121 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
11122 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
11123 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB    _u(17)
11124 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB    _u(17)
11125 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
11126 // -----------------------------------------------------------------------------
11127 // Field       : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW
11128 // Description : None
11129 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
11130 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
11131 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB    _u(16)
11132 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB    _u(16)
11133 #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
11134 // -----------------------------------------------------------------------------
11135 // Field       : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH
11136 // Description : None
11137 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
11138 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
11139 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB    _u(15)
11140 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB    _u(15)
11141 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
11142 // -----------------------------------------------------------------------------
11143 // Field       : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW
11144 // Description : None
11145 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET  _u(0x0)
11146 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
11147 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB    _u(14)
11148 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB    _u(14)
11149 #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
11150 // -----------------------------------------------------------------------------
11151 // Field       : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH
11152 // Description : None
11153 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
11154 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
11155 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB    _u(13)
11156 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB    _u(13)
11157 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
11158 // -----------------------------------------------------------------------------
11159 // Field       : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW
11160 // Description : None
11161 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
11162 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
11163 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB    _u(12)
11164 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB    _u(12)
11165 #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
11166 // -----------------------------------------------------------------------------
11167 // Field       : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH
11168 // Description : None
11169 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
11170 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
11171 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB    _u(11)
11172 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB    _u(11)
11173 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
11174 // -----------------------------------------------------------------------------
11175 // Field       : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW
11176 // Description : None
11177 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET  _u(0x0)
11178 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
11179 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB    _u(10)
11180 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB    _u(10)
11181 #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
11182 // -----------------------------------------------------------------------------
11183 // Field       : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH
11184 // Description : None
11185 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
11186 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
11187 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB    _u(9)
11188 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB    _u(9)
11189 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
11190 // -----------------------------------------------------------------------------
11191 // Field       : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW
11192 // Description : None
11193 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
11194 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
11195 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB    _u(8)
11196 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB    _u(8)
11197 #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
11198 // -----------------------------------------------------------------------------
11199 // Field       : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH
11200 // Description : None
11201 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
11202 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
11203 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB    _u(7)
11204 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB    _u(7)
11205 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
11206 // -----------------------------------------------------------------------------
11207 // Field       : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW
11208 // Description : None
11209 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET  _u(0x0)
11210 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
11211 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB    _u(6)
11212 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB    _u(6)
11213 #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
11214 // -----------------------------------------------------------------------------
11215 // Field       : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH
11216 // Description : None
11217 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
11218 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
11219 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB    _u(5)
11220 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB    _u(5)
11221 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
11222 // -----------------------------------------------------------------------------
11223 // Field       : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW
11224 // Description : None
11225 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
11226 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
11227 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB    _u(4)
11228 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB    _u(4)
11229 #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
11230 // -----------------------------------------------------------------------------
11231 // Field       : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH
11232 // Description : None
11233 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
11234 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
11235 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB    _u(3)
11236 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB    _u(3)
11237 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
11238 // -----------------------------------------------------------------------------
11239 // Field       : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW
11240 // Description : None
11241 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET  _u(0x0)
11242 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
11243 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB    _u(2)
11244 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB    _u(2)
11245 #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
11246 // -----------------------------------------------------------------------------
11247 // Field       : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH
11248 // Description : None
11249 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
11250 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
11251 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB    _u(1)
11252 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB    _u(1)
11253 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
11254 // -----------------------------------------------------------------------------
11255 // Field       : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW
11256 // Description : None
11257 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
11258 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
11259 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB    _u(0)
11260 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB    _u(0)
11261 #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
11262 // =============================================================================
11263 // Register    : IO_BANK0_PROC1_INTS1
11264 // Description : Interrupt status after masking & forcing for proc1
11265 #define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154)
11266 #define IO_BANK0_PROC1_INTS1_BITS   _u(0xffffffff)
11267 #define IO_BANK0_PROC1_INTS1_RESET  _u(0x00000000)
11268 // -----------------------------------------------------------------------------
11269 // Field       : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH
11270 // Description : None
11271 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
11272 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
11273 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB    _u(31)
11274 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB    _u(31)
11275 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
11276 // -----------------------------------------------------------------------------
11277 // Field       : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW
11278 // Description : None
11279 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET  _u(0x0)
11280 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
11281 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB    _u(30)
11282 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB    _u(30)
11283 #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
11284 // -----------------------------------------------------------------------------
11285 // Field       : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH
11286 // Description : None
11287 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
11288 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
11289 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB    _u(29)
11290 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB    _u(29)
11291 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
11292 // -----------------------------------------------------------------------------
11293 // Field       : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW
11294 // Description : None
11295 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
11296 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
11297 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB    _u(28)
11298 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB    _u(28)
11299 #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
11300 // -----------------------------------------------------------------------------
11301 // Field       : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH
11302 // Description : None
11303 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
11304 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
11305 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB    _u(27)
11306 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB    _u(27)
11307 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
11308 // -----------------------------------------------------------------------------
11309 // Field       : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW
11310 // Description : None
11311 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET  _u(0x0)
11312 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
11313 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB    _u(26)
11314 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB    _u(26)
11315 #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
11316 // -----------------------------------------------------------------------------
11317 // Field       : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH
11318 // Description : None
11319 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
11320 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
11321 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB    _u(25)
11322 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB    _u(25)
11323 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
11324 // -----------------------------------------------------------------------------
11325 // Field       : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW
11326 // Description : None
11327 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
11328 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
11329 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB    _u(24)
11330 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB    _u(24)
11331 #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
11332 // -----------------------------------------------------------------------------
11333 // Field       : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH
11334 // Description : None
11335 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
11336 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
11337 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB    _u(23)
11338 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB    _u(23)
11339 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
11340 // -----------------------------------------------------------------------------
11341 // Field       : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW
11342 // Description : None
11343 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET  _u(0x0)
11344 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
11345 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB    _u(22)
11346 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB    _u(22)
11347 #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
11348 // -----------------------------------------------------------------------------
11349 // Field       : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH
11350 // Description : None
11351 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
11352 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
11353 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB    _u(21)
11354 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB    _u(21)
11355 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
11356 // -----------------------------------------------------------------------------
11357 // Field       : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW
11358 // Description : None
11359 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
11360 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
11361 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB    _u(20)
11362 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB    _u(20)
11363 #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
11364 // -----------------------------------------------------------------------------
11365 // Field       : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH
11366 // Description : None
11367 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
11368 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
11369 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB    _u(19)
11370 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB    _u(19)
11371 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
11372 // -----------------------------------------------------------------------------
11373 // Field       : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW
11374 // Description : None
11375 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET  _u(0x0)
11376 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
11377 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB    _u(18)
11378 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB    _u(18)
11379 #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
11380 // -----------------------------------------------------------------------------
11381 // Field       : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH
11382 // Description : None
11383 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
11384 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
11385 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB    _u(17)
11386 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB    _u(17)
11387 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
11388 // -----------------------------------------------------------------------------
11389 // Field       : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW
11390 // Description : None
11391 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
11392 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
11393 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB    _u(16)
11394 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB    _u(16)
11395 #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
11396 // -----------------------------------------------------------------------------
11397 // Field       : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH
11398 // Description : None
11399 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
11400 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
11401 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB    _u(15)
11402 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB    _u(15)
11403 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
11404 // -----------------------------------------------------------------------------
11405 // Field       : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW
11406 // Description : None
11407 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET  _u(0x0)
11408 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
11409 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB    _u(14)
11410 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB    _u(14)
11411 #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
11412 // -----------------------------------------------------------------------------
11413 // Field       : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH
11414 // Description : None
11415 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
11416 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
11417 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB    _u(13)
11418 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB    _u(13)
11419 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
11420 // -----------------------------------------------------------------------------
11421 // Field       : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW
11422 // Description : None
11423 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
11424 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
11425 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB    _u(12)
11426 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB    _u(12)
11427 #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
11428 // -----------------------------------------------------------------------------
11429 // Field       : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH
11430 // Description : None
11431 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
11432 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
11433 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB    _u(11)
11434 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB    _u(11)
11435 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
11436 // -----------------------------------------------------------------------------
11437 // Field       : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW
11438 // Description : None
11439 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET  _u(0x0)
11440 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
11441 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB    _u(10)
11442 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB    _u(10)
11443 #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
11444 // -----------------------------------------------------------------------------
11445 // Field       : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH
11446 // Description : None
11447 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
11448 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
11449 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB    _u(9)
11450 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB    _u(9)
11451 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
11452 // -----------------------------------------------------------------------------
11453 // Field       : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW
11454 // Description : None
11455 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
11456 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
11457 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB    _u(8)
11458 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB    _u(8)
11459 #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
11460 // -----------------------------------------------------------------------------
11461 // Field       : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH
11462 // Description : None
11463 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
11464 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
11465 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB    _u(7)
11466 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB    _u(7)
11467 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
11468 // -----------------------------------------------------------------------------
11469 // Field       : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW
11470 // Description : None
11471 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET  _u(0x0)
11472 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
11473 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB    _u(6)
11474 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB    _u(6)
11475 #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
11476 // -----------------------------------------------------------------------------
11477 // Field       : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH
11478 // Description : None
11479 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
11480 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
11481 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB    _u(5)
11482 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB    _u(5)
11483 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
11484 // -----------------------------------------------------------------------------
11485 // Field       : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW
11486 // Description : None
11487 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
11488 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
11489 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB    _u(4)
11490 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB    _u(4)
11491 #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
11492 // -----------------------------------------------------------------------------
11493 // Field       : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH
11494 // Description : None
11495 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
11496 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
11497 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB    _u(3)
11498 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB    _u(3)
11499 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
11500 // -----------------------------------------------------------------------------
11501 // Field       : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW
11502 // Description : None
11503 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET  _u(0x0)
11504 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
11505 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB    _u(2)
11506 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB    _u(2)
11507 #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
11508 // -----------------------------------------------------------------------------
11509 // Field       : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH
11510 // Description : None
11511 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
11512 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
11513 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB    _u(1)
11514 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB    _u(1)
11515 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
11516 // -----------------------------------------------------------------------------
11517 // Field       : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW
11518 // Description : None
11519 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
11520 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
11521 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB    _u(0)
11522 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB    _u(0)
11523 #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
11524 // =============================================================================
11525 // Register    : IO_BANK0_PROC1_INTS2
11526 // Description : Interrupt status after masking & forcing for proc1
11527 #define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158)
11528 #define IO_BANK0_PROC1_INTS2_BITS   _u(0xffffffff)
11529 #define IO_BANK0_PROC1_INTS2_RESET  _u(0x00000000)
11530 // -----------------------------------------------------------------------------
11531 // Field       : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH
11532 // Description : None
11533 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
11534 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
11535 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB    _u(31)
11536 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB    _u(31)
11537 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
11538 // -----------------------------------------------------------------------------
11539 // Field       : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW
11540 // Description : None
11541 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET  _u(0x0)
11542 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
11543 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB    _u(30)
11544 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB    _u(30)
11545 #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
11546 // -----------------------------------------------------------------------------
11547 // Field       : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH
11548 // Description : None
11549 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
11550 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
11551 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB    _u(29)
11552 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB    _u(29)
11553 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
11554 // -----------------------------------------------------------------------------
11555 // Field       : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW
11556 // Description : None
11557 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
11558 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
11559 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB    _u(28)
11560 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB    _u(28)
11561 #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
11562 // -----------------------------------------------------------------------------
11563 // Field       : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH
11564 // Description : None
11565 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
11566 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
11567 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB    _u(27)
11568 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB    _u(27)
11569 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
11570 // -----------------------------------------------------------------------------
11571 // Field       : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW
11572 // Description : None
11573 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET  _u(0x0)
11574 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
11575 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB    _u(26)
11576 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB    _u(26)
11577 #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
11578 // -----------------------------------------------------------------------------
11579 // Field       : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH
11580 // Description : None
11581 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
11582 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
11583 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB    _u(25)
11584 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB    _u(25)
11585 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
11586 // -----------------------------------------------------------------------------
11587 // Field       : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW
11588 // Description : None
11589 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
11590 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
11591 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB    _u(24)
11592 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB    _u(24)
11593 #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
11594 // -----------------------------------------------------------------------------
11595 // Field       : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH
11596 // Description : None
11597 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
11598 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
11599 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB    _u(23)
11600 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB    _u(23)
11601 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
11602 // -----------------------------------------------------------------------------
11603 // Field       : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW
11604 // Description : None
11605 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET  _u(0x0)
11606 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
11607 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB    _u(22)
11608 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB    _u(22)
11609 #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
11610 // -----------------------------------------------------------------------------
11611 // Field       : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH
11612 // Description : None
11613 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
11614 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
11615 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB    _u(21)
11616 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB    _u(21)
11617 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
11618 // -----------------------------------------------------------------------------
11619 // Field       : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW
11620 // Description : None
11621 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
11622 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
11623 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB    _u(20)
11624 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB    _u(20)
11625 #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
11626 // -----------------------------------------------------------------------------
11627 // Field       : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH
11628 // Description : None
11629 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
11630 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
11631 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB    _u(19)
11632 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB    _u(19)
11633 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
11634 // -----------------------------------------------------------------------------
11635 // Field       : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW
11636 // Description : None
11637 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET  _u(0x0)
11638 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
11639 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB    _u(18)
11640 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB    _u(18)
11641 #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
11642 // -----------------------------------------------------------------------------
11643 // Field       : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH
11644 // Description : None
11645 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
11646 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
11647 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB    _u(17)
11648 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB    _u(17)
11649 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
11650 // -----------------------------------------------------------------------------
11651 // Field       : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW
11652 // Description : None
11653 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
11654 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
11655 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB    _u(16)
11656 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB    _u(16)
11657 #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
11658 // -----------------------------------------------------------------------------
11659 // Field       : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH
11660 // Description : None
11661 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
11662 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
11663 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB    _u(15)
11664 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB    _u(15)
11665 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
11666 // -----------------------------------------------------------------------------
11667 // Field       : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW
11668 // Description : None
11669 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET  _u(0x0)
11670 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
11671 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB    _u(14)
11672 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB    _u(14)
11673 #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
11674 // -----------------------------------------------------------------------------
11675 // Field       : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH
11676 // Description : None
11677 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
11678 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
11679 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB    _u(13)
11680 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB    _u(13)
11681 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
11682 // -----------------------------------------------------------------------------
11683 // Field       : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW
11684 // Description : None
11685 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
11686 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
11687 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB    _u(12)
11688 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB    _u(12)
11689 #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
11690 // -----------------------------------------------------------------------------
11691 // Field       : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH
11692 // Description : None
11693 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
11694 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
11695 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB    _u(11)
11696 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB    _u(11)
11697 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
11698 // -----------------------------------------------------------------------------
11699 // Field       : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW
11700 // Description : None
11701 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET  _u(0x0)
11702 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
11703 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB    _u(10)
11704 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB    _u(10)
11705 #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
11706 // -----------------------------------------------------------------------------
11707 // Field       : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH
11708 // Description : None
11709 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
11710 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
11711 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB    _u(9)
11712 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB    _u(9)
11713 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
11714 // -----------------------------------------------------------------------------
11715 // Field       : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW
11716 // Description : None
11717 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
11718 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
11719 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB    _u(8)
11720 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB    _u(8)
11721 #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
11722 // -----------------------------------------------------------------------------
11723 // Field       : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH
11724 // Description : None
11725 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
11726 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
11727 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB    _u(7)
11728 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB    _u(7)
11729 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
11730 // -----------------------------------------------------------------------------
11731 // Field       : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW
11732 // Description : None
11733 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET  _u(0x0)
11734 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
11735 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB    _u(6)
11736 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB    _u(6)
11737 #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
11738 // -----------------------------------------------------------------------------
11739 // Field       : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH
11740 // Description : None
11741 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
11742 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
11743 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB    _u(5)
11744 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB    _u(5)
11745 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
11746 // -----------------------------------------------------------------------------
11747 // Field       : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW
11748 // Description : None
11749 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
11750 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
11751 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB    _u(4)
11752 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB    _u(4)
11753 #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
11754 // -----------------------------------------------------------------------------
11755 // Field       : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH
11756 // Description : None
11757 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
11758 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
11759 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB    _u(3)
11760 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB    _u(3)
11761 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
11762 // -----------------------------------------------------------------------------
11763 // Field       : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW
11764 // Description : None
11765 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET  _u(0x0)
11766 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
11767 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB    _u(2)
11768 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB    _u(2)
11769 #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
11770 // -----------------------------------------------------------------------------
11771 // Field       : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH
11772 // Description : None
11773 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
11774 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
11775 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB    _u(1)
11776 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB    _u(1)
11777 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
11778 // -----------------------------------------------------------------------------
11779 // Field       : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW
11780 // Description : None
11781 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
11782 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
11783 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB    _u(0)
11784 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB    _u(0)
11785 #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
11786 // =============================================================================
11787 // Register    : IO_BANK0_PROC1_INTS3
11788 // Description : Interrupt status after masking & forcing for proc1
11789 #define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c)
11790 #define IO_BANK0_PROC1_INTS3_BITS   _u(0x00ffffff)
11791 #define IO_BANK0_PROC1_INTS3_RESET  _u(0x00000000)
11792 // -----------------------------------------------------------------------------
11793 // Field       : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH
11794 // Description : None
11795 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
11796 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
11797 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB    _u(23)
11798 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB    _u(23)
11799 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
11800 // -----------------------------------------------------------------------------
11801 // Field       : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW
11802 // Description : None
11803 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET  _u(0x0)
11804 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
11805 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB    _u(22)
11806 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB    _u(22)
11807 #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
11808 // -----------------------------------------------------------------------------
11809 // Field       : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH
11810 // Description : None
11811 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
11812 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
11813 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB    _u(21)
11814 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB    _u(21)
11815 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
11816 // -----------------------------------------------------------------------------
11817 // Field       : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW
11818 // Description : None
11819 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
11820 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
11821 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB    _u(20)
11822 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB    _u(20)
11823 #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
11824 // -----------------------------------------------------------------------------
11825 // Field       : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH
11826 // Description : None
11827 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
11828 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
11829 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB    _u(19)
11830 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB    _u(19)
11831 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
11832 // -----------------------------------------------------------------------------
11833 // Field       : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW
11834 // Description : None
11835 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET  _u(0x0)
11836 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
11837 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB    _u(18)
11838 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB    _u(18)
11839 #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
11840 // -----------------------------------------------------------------------------
11841 // Field       : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH
11842 // Description : None
11843 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
11844 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
11845 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB    _u(17)
11846 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB    _u(17)
11847 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
11848 // -----------------------------------------------------------------------------
11849 // Field       : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW
11850 // Description : None
11851 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
11852 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
11853 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB    _u(16)
11854 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB    _u(16)
11855 #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
11856 // -----------------------------------------------------------------------------
11857 // Field       : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH
11858 // Description : None
11859 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
11860 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
11861 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB    _u(15)
11862 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB    _u(15)
11863 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
11864 // -----------------------------------------------------------------------------
11865 // Field       : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW
11866 // Description : None
11867 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET  _u(0x0)
11868 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
11869 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB    _u(14)
11870 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB    _u(14)
11871 #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
11872 // -----------------------------------------------------------------------------
11873 // Field       : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH
11874 // Description : None
11875 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
11876 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
11877 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB    _u(13)
11878 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB    _u(13)
11879 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
11880 // -----------------------------------------------------------------------------
11881 // Field       : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW
11882 // Description : None
11883 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
11884 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
11885 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB    _u(12)
11886 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB    _u(12)
11887 #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
11888 // -----------------------------------------------------------------------------
11889 // Field       : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH
11890 // Description : None
11891 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
11892 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
11893 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB    _u(11)
11894 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB    _u(11)
11895 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
11896 // -----------------------------------------------------------------------------
11897 // Field       : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW
11898 // Description : None
11899 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET  _u(0x0)
11900 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
11901 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB    _u(10)
11902 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB    _u(10)
11903 #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
11904 // -----------------------------------------------------------------------------
11905 // Field       : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH
11906 // Description : None
11907 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
11908 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
11909 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB    _u(9)
11910 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB    _u(9)
11911 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
11912 // -----------------------------------------------------------------------------
11913 // Field       : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW
11914 // Description : None
11915 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
11916 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
11917 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB    _u(8)
11918 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB    _u(8)
11919 #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
11920 // -----------------------------------------------------------------------------
11921 // Field       : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH
11922 // Description : None
11923 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
11924 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
11925 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB    _u(7)
11926 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB    _u(7)
11927 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
11928 // -----------------------------------------------------------------------------
11929 // Field       : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW
11930 // Description : None
11931 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET  _u(0x0)
11932 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
11933 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB    _u(6)
11934 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB    _u(6)
11935 #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
11936 // -----------------------------------------------------------------------------
11937 // Field       : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH
11938 // Description : None
11939 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
11940 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
11941 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB    _u(5)
11942 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB    _u(5)
11943 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
11944 // -----------------------------------------------------------------------------
11945 // Field       : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW
11946 // Description : None
11947 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
11948 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
11949 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB    _u(4)
11950 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB    _u(4)
11951 #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
11952 // -----------------------------------------------------------------------------
11953 // Field       : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH
11954 // Description : None
11955 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
11956 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
11957 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB    _u(3)
11958 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB    _u(3)
11959 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
11960 // -----------------------------------------------------------------------------
11961 // Field       : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW
11962 // Description : None
11963 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET  _u(0x0)
11964 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
11965 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB    _u(2)
11966 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB    _u(2)
11967 #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
11968 // -----------------------------------------------------------------------------
11969 // Field       : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH
11970 // Description : None
11971 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
11972 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
11973 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB    _u(1)
11974 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB    _u(1)
11975 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
11976 // -----------------------------------------------------------------------------
11977 // Field       : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW
11978 // Description : None
11979 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
11980 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
11981 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB    _u(0)
11982 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB    _u(0)
11983 #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
11984 // =============================================================================
11985 // Register    : IO_BANK0_DORMANT_WAKE_INTE0
11986 // Description : Interrupt Enable for dormant_wake
11987 #define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160)
11988 #define IO_BANK0_DORMANT_WAKE_INTE0_BITS   _u(0xffffffff)
11989 #define IO_BANK0_DORMANT_WAKE_INTE0_RESET  _u(0x00000000)
11990 // -----------------------------------------------------------------------------
11991 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH
11992 // Description : None
11993 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
11994 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
11995 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB    _u(31)
11996 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB    _u(31)
11997 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
11998 // -----------------------------------------------------------------------------
11999 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW
12000 // Description : None
12001 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET  _u(0x0)
12002 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
12003 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB    _u(30)
12004 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB    _u(30)
12005 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
12006 // -----------------------------------------------------------------------------
12007 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH
12008 // Description : None
12009 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
12010 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
12011 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB    _u(29)
12012 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB    _u(29)
12013 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
12014 // -----------------------------------------------------------------------------
12015 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW
12016 // Description : None
12017 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
12018 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
12019 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB    _u(28)
12020 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB    _u(28)
12021 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
12022 // -----------------------------------------------------------------------------
12023 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH
12024 // Description : None
12025 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
12026 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
12027 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB    _u(27)
12028 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB    _u(27)
12029 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
12030 // -----------------------------------------------------------------------------
12031 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW
12032 // Description : None
12033 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET  _u(0x0)
12034 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
12035 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB    _u(26)
12036 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB    _u(26)
12037 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
12038 // -----------------------------------------------------------------------------
12039 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH
12040 // Description : None
12041 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
12042 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
12043 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB    _u(25)
12044 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB    _u(25)
12045 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
12046 // -----------------------------------------------------------------------------
12047 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW
12048 // Description : None
12049 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
12050 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
12051 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB    _u(24)
12052 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB    _u(24)
12053 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
12054 // -----------------------------------------------------------------------------
12055 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH
12056 // Description : None
12057 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
12058 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
12059 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB    _u(23)
12060 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB    _u(23)
12061 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
12062 // -----------------------------------------------------------------------------
12063 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW
12064 // Description : None
12065 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET  _u(0x0)
12066 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
12067 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB    _u(22)
12068 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB    _u(22)
12069 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
12070 // -----------------------------------------------------------------------------
12071 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH
12072 // Description : None
12073 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
12074 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
12075 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB    _u(21)
12076 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB    _u(21)
12077 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
12078 // -----------------------------------------------------------------------------
12079 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW
12080 // Description : None
12081 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
12082 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
12083 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB    _u(20)
12084 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB    _u(20)
12085 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
12086 // -----------------------------------------------------------------------------
12087 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH
12088 // Description : None
12089 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
12090 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
12091 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB    _u(19)
12092 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB    _u(19)
12093 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
12094 // -----------------------------------------------------------------------------
12095 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW
12096 // Description : None
12097 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET  _u(0x0)
12098 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
12099 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB    _u(18)
12100 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB    _u(18)
12101 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
12102 // -----------------------------------------------------------------------------
12103 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH
12104 // Description : None
12105 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
12106 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
12107 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB    _u(17)
12108 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB    _u(17)
12109 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
12110 // -----------------------------------------------------------------------------
12111 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW
12112 // Description : None
12113 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
12114 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
12115 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB    _u(16)
12116 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB    _u(16)
12117 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
12118 // -----------------------------------------------------------------------------
12119 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH
12120 // Description : None
12121 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
12122 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
12123 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB    _u(15)
12124 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB    _u(15)
12125 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
12126 // -----------------------------------------------------------------------------
12127 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW
12128 // Description : None
12129 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET  _u(0x0)
12130 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
12131 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB    _u(14)
12132 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB    _u(14)
12133 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
12134 // -----------------------------------------------------------------------------
12135 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH
12136 // Description : None
12137 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
12138 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
12139 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB    _u(13)
12140 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB    _u(13)
12141 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
12142 // -----------------------------------------------------------------------------
12143 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW
12144 // Description : None
12145 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
12146 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
12147 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB    _u(12)
12148 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB    _u(12)
12149 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
12150 // -----------------------------------------------------------------------------
12151 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH
12152 // Description : None
12153 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
12154 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
12155 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB    _u(11)
12156 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB    _u(11)
12157 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
12158 // -----------------------------------------------------------------------------
12159 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW
12160 // Description : None
12161 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET  _u(0x0)
12162 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
12163 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB    _u(10)
12164 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB    _u(10)
12165 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
12166 // -----------------------------------------------------------------------------
12167 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH
12168 // Description : None
12169 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
12170 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
12171 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB    _u(9)
12172 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB    _u(9)
12173 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
12174 // -----------------------------------------------------------------------------
12175 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW
12176 // Description : None
12177 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
12178 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
12179 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB    _u(8)
12180 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB    _u(8)
12181 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
12182 // -----------------------------------------------------------------------------
12183 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH
12184 // Description : None
12185 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
12186 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
12187 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB    _u(7)
12188 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB    _u(7)
12189 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
12190 // -----------------------------------------------------------------------------
12191 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW
12192 // Description : None
12193 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET  _u(0x0)
12194 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
12195 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB    _u(6)
12196 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB    _u(6)
12197 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
12198 // -----------------------------------------------------------------------------
12199 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH
12200 // Description : None
12201 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
12202 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
12203 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB    _u(5)
12204 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB    _u(5)
12205 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
12206 // -----------------------------------------------------------------------------
12207 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW
12208 // Description : None
12209 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
12210 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
12211 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB    _u(4)
12212 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB    _u(4)
12213 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
12214 // -----------------------------------------------------------------------------
12215 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH
12216 // Description : None
12217 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
12218 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
12219 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB    _u(3)
12220 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB    _u(3)
12221 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
12222 // -----------------------------------------------------------------------------
12223 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW
12224 // Description : None
12225 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET  _u(0x0)
12226 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
12227 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB    _u(2)
12228 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB    _u(2)
12229 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
12230 // -----------------------------------------------------------------------------
12231 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH
12232 // Description : None
12233 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
12234 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
12235 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB    _u(1)
12236 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB    _u(1)
12237 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
12238 // -----------------------------------------------------------------------------
12239 // Field       : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW
12240 // Description : None
12241 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
12242 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
12243 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB    _u(0)
12244 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB    _u(0)
12245 #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
12246 // =============================================================================
12247 // Register    : IO_BANK0_DORMANT_WAKE_INTE1
12248 // Description : Interrupt Enable for dormant_wake
12249 #define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164)
12250 #define IO_BANK0_DORMANT_WAKE_INTE1_BITS   _u(0xffffffff)
12251 #define IO_BANK0_DORMANT_WAKE_INTE1_RESET  _u(0x00000000)
12252 // -----------------------------------------------------------------------------
12253 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH
12254 // Description : None
12255 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
12256 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
12257 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB    _u(31)
12258 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB    _u(31)
12259 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
12260 // -----------------------------------------------------------------------------
12261 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW
12262 // Description : None
12263 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET  _u(0x0)
12264 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
12265 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB    _u(30)
12266 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB    _u(30)
12267 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
12268 // -----------------------------------------------------------------------------
12269 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH
12270 // Description : None
12271 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
12272 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
12273 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB    _u(29)
12274 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB    _u(29)
12275 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
12276 // -----------------------------------------------------------------------------
12277 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW
12278 // Description : None
12279 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
12280 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
12281 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB    _u(28)
12282 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB    _u(28)
12283 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
12284 // -----------------------------------------------------------------------------
12285 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH
12286 // Description : None
12287 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
12288 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
12289 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB    _u(27)
12290 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB    _u(27)
12291 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
12292 // -----------------------------------------------------------------------------
12293 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW
12294 // Description : None
12295 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET  _u(0x0)
12296 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
12297 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB    _u(26)
12298 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB    _u(26)
12299 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
12300 // -----------------------------------------------------------------------------
12301 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH
12302 // Description : None
12303 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
12304 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
12305 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB    _u(25)
12306 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB    _u(25)
12307 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
12308 // -----------------------------------------------------------------------------
12309 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW
12310 // Description : None
12311 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
12312 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
12313 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB    _u(24)
12314 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB    _u(24)
12315 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
12316 // -----------------------------------------------------------------------------
12317 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH
12318 // Description : None
12319 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
12320 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
12321 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB    _u(23)
12322 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB    _u(23)
12323 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
12324 // -----------------------------------------------------------------------------
12325 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW
12326 // Description : None
12327 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET  _u(0x0)
12328 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
12329 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB    _u(22)
12330 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB    _u(22)
12331 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
12332 // -----------------------------------------------------------------------------
12333 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH
12334 // Description : None
12335 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
12336 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
12337 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB    _u(21)
12338 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB    _u(21)
12339 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
12340 // -----------------------------------------------------------------------------
12341 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW
12342 // Description : None
12343 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
12344 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
12345 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB    _u(20)
12346 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB    _u(20)
12347 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
12348 // -----------------------------------------------------------------------------
12349 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH
12350 // Description : None
12351 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
12352 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
12353 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB    _u(19)
12354 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB    _u(19)
12355 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
12356 // -----------------------------------------------------------------------------
12357 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW
12358 // Description : None
12359 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET  _u(0x0)
12360 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
12361 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB    _u(18)
12362 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB    _u(18)
12363 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
12364 // -----------------------------------------------------------------------------
12365 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH
12366 // Description : None
12367 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
12368 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
12369 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB    _u(17)
12370 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB    _u(17)
12371 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
12372 // -----------------------------------------------------------------------------
12373 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW
12374 // Description : None
12375 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
12376 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
12377 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB    _u(16)
12378 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB    _u(16)
12379 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
12380 // -----------------------------------------------------------------------------
12381 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH
12382 // Description : None
12383 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
12384 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
12385 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB    _u(15)
12386 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB    _u(15)
12387 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
12388 // -----------------------------------------------------------------------------
12389 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW
12390 // Description : None
12391 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET  _u(0x0)
12392 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
12393 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB    _u(14)
12394 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB    _u(14)
12395 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
12396 // -----------------------------------------------------------------------------
12397 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH
12398 // Description : None
12399 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
12400 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
12401 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB    _u(13)
12402 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB    _u(13)
12403 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
12404 // -----------------------------------------------------------------------------
12405 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW
12406 // Description : None
12407 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
12408 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
12409 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB    _u(12)
12410 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB    _u(12)
12411 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
12412 // -----------------------------------------------------------------------------
12413 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH
12414 // Description : None
12415 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
12416 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
12417 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB    _u(11)
12418 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB    _u(11)
12419 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
12420 // -----------------------------------------------------------------------------
12421 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW
12422 // Description : None
12423 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET  _u(0x0)
12424 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
12425 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB    _u(10)
12426 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB    _u(10)
12427 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
12428 // -----------------------------------------------------------------------------
12429 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH
12430 // Description : None
12431 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
12432 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
12433 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB    _u(9)
12434 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB    _u(9)
12435 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
12436 // -----------------------------------------------------------------------------
12437 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW
12438 // Description : None
12439 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
12440 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
12441 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB    _u(8)
12442 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB    _u(8)
12443 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
12444 // -----------------------------------------------------------------------------
12445 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH
12446 // Description : None
12447 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
12448 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
12449 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB    _u(7)
12450 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB    _u(7)
12451 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
12452 // -----------------------------------------------------------------------------
12453 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW
12454 // Description : None
12455 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET  _u(0x0)
12456 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
12457 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB    _u(6)
12458 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB    _u(6)
12459 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
12460 // -----------------------------------------------------------------------------
12461 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH
12462 // Description : None
12463 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
12464 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
12465 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB    _u(5)
12466 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB    _u(5)
12467 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
12468 // -----------------------------------------------------------------------------
12469 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW
12470 // Description : None
12471 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
12472 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
12473 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB    _u(4)
12474 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB    _u(4)
12475 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
12476 // -----------------------------------------------------------------------------
12477 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH
12478 // Description : None
12479 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
12480 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
12481 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB    _u(3)
12482 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB    _u(3)
12483 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
12484 // -----------------------------------------------------------------------------
12485 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW
12486 // Description : None
12487 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET  _u(0x0)
12488 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
12489 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB    _u(2)
12490 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB    _u(2)
12491 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
12492 // -----------------------------------------------------------------------------
12493 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH
12494 // Description : None
12495 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
12496 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
12497 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB    _u(1)
12498 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB    _u(1)
12499 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
12500 // -----------------------------------------------------------------------------
12501 // Field       : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW
12502 // Description : None
12503 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
12504 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
12505 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB    _u(0)
12506 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB    _u(0)
12507 #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
12508 // =============================================================================
12509 // Register    : IO_BANK0_DORMANT_WAKE_INTE2
12510 // Description : Interrupt Enable for dormant_wake
12511 #define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168)
12512 #define IO_BANK0_DORMANT_WAKE_INTE2_BITS   _u(0xffffffff)
12513 #define IO_BANK0_DORMANT_WAKE_INTE2_RESET  _u(0x00000000)
12514 // -----------------------------------------------------------------------------
12515 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH
12516 // Description : None
12517 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
12518 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
12519 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB    _u(31)
12520 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB    _u(31)
12521 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
12522 // -----------------------------------------------------------------------------
12523 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW
12524 // Description : None
12525 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET  _u(0x0)
12526 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
12527 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB    _u(30)
12528 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB    _u(30)
12529 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
12530 // -----------------------------------------------------------------------------
12531 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH
12532 // Description : None
12533 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
12534 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
12535 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB    _u(29)
12536 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB    _u(29)
12537 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
12538 // -----------------------------------------------------------------------------
12539 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW
12540 // Description : None
12541 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
12542 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
12543 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB    _u(28)
12544 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB    _u(28)
12545 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
12546 // -----------------------------------------------------------------------------
12547 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH
12548 // Description : None
12549 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
12550 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
12551 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB    _u(27)
12552 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB    _u(27)
12553 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
12554 // -----------------------------------------------------------------------------
12555 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW
12556 // Description : None
12557 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET  _u(0x0)
12558 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
12559 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB    _u(26)
12560 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB    _u(26)
12561 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
12562 // -----------------------------------------------------------------------------
12563 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH
12564 // Description : None
12565 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
12566 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
12567 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB    _u(25)
12568 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB    _u(25)
12569 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
12570 // -----------------------------------------------------------------------------
12571 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW
12572 // Description : None
12573 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
12574 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
12575 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB    _u(24)
12576 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB    _u(24)
12577 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
12578 // -----------------------------------------------------------------------------
12579 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH
12580 // Description : None
12581 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
12582 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
12583 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB    _u(23)
12584 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB    _u(23)
12585 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
12586 // -----------------------------------------------------------------------------
12587 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW
12588 // Description : None
12589 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET  _u(0x0)
12590 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
12591 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB    _u(22)
12592 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB    _u(22)
12593 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
12594 // -----------------------------------------------------------------------------
12595 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH
12596 // Description : None
12597 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
12598 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
12599 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB    _u(21)
12600 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB    _u(21)
12601 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
12602 // -----------------------------------------------------------------------------
12603 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW
12604 // Description : None
12605 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
12606 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
12607 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB    _u(20)
12608 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB    _u(20)
12609 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
12610 // -----------------------------------------------------------------------------
12611 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH
12612 // Description : None
12613 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
12614 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
12615 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB    _u(19)
12616 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB    _u(19)
12617 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
12618 // -----------------------------------------------------------------------------
12619 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW
12620 // Description : None
12621 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET  _u(0x0)
12622 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
12623 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB    _u(18)
12624 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB    _u(18)
12625 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
12626 // -----------------------------------------------------------------------------
12627 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH
12628 // Description : None
12629 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
12630 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
12631 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB    _u(17)
12632 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB    _u(17)
12633 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
12634 // -----------------------------------------------------------------------------
12635 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW
12636 // Description : None
12637 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
12638 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
12639 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB    _u(16)
12640 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB    _u(16)
12641 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
12642 // -----------------------------------------------------------------------------
12643 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH
12644 // Description : None
12645 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
12646 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
12647 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB    _u(15)
12648 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB    _u(15)
12649 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
12650 // -----------------------------------------------------------------------------
12651 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW
12652 // Description : None
12653 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET  _u(0x0)
12654 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
12655 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB    _u(14)
12656 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB    _u(14)
12657 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
12658 // -----------------------------------------------------------------------------
12659 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH
12660 // Description : None
12661 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
12662 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
12663 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB    _u(13)
12664 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB    _u(13)
12665 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
12666 // -----------------------------------------------------------------------------
12667 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW
12668 // Description : None
12669 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
12670 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
12671 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB    _u(12)
12672 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB    _u(12)
12673 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
12674 // -----------------------------------------------------------------------------
12675 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH
12676 // Description : None
12677 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
12678 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
12679 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB    _u(11)
12680 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB    _u(11)
12681 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
12682 // -----------------------------------------------------------------------------
12683 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW
12684 // Description : None
12685 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET  _u(0x0)
12686 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
12687 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB    _u(10)
12688 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB    _u(10)
12689 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
12690 // -----------------------------------------------------------------------------
12691 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH
12692 // Description : None
12693 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
12694 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
12695 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB    _u(9)
12696 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB    _u(9)
12697 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
12698 // -----------------------------------------------------------------------------
12699 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW
12700 // Description : None
12701 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
12702 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
12703 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB    _u(8)
12704 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB    _u(8)
12705 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
12706 // -----------------------------------------------------------------------------
12707 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH
12708 // Description : None
12709 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
12710 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
12711 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB    _u(7)
12712 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB    _u(7)
12713 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
12714 // -----------------------------------------------------------------------------
12715 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW
12716 // Description : None
12717 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET  _u(0x0)
12718 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
12719 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB    _u(6)
12720 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB    _u(6)
12721 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
12722 // -----------------------------------------------------------------------------
12723 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH
12724 // Description : None
12725 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
12726 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
12727 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB    _u(5)
12728 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB    _u(5)
12729 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
12730 // -----------------------------------------------------------------------------
12731 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW
12732 // Description : None
12733 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
12734 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
12735 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB    _u(4)
12736 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB    _u(4)
12737 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
12738 // -----------------------------------------------------------------------------
12739 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH
12740 // Description : None
12741 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
12742 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
12743 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB    _u(3)
12744 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB    _u(3)
12745 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
12746 // -----------------------------------------------------------------------------
12747 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW
12748 // Description : None
12749 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET  _u(0x0)
12750 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
12751 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB    _u(2)
12752 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB    _u(2)
12753 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
12754 // -----------------------------------------------------------------------------
12755 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH
12756 // Description : None
12757 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
12758 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
12759 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB    _u(1)
12760 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB    _u(1)
12761 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
12762 // -----------------------------------------------------------------------------
12763 // Field       : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW
12764 // Description : None
12765 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
12766 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
12767 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB    _u(0)
12768 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB    _u(0)
12769 #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
12770 // =============================================================================
12771 // Register    : IO_BANK0_DORMANT_WAKE_INTE3
12772 // Description : Interrupt Enable for dormant_wake
12773 #define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c)
12774 #define IO_BANK0_DORMANT_WAKE_INTE3_BITS   _u(0x00ffffff)
12775 #define IO_BANK0_DORMANT_WAKE_INTE3_RESET  _u(0x00000000)
12776 // -----------------------------------------------------------------------------
12777 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH
12778 // Description : None
12779 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
12780 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
12781 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB    _u(23)
12782 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB    _u(23)
12783 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
12784 // -----------------------------------------------------------------------------
12785 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW
12786 // Description : None
12787 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET  _u(0x0)
12788 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
12789 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB    _u(22)
12790 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB    _u(22)
12791 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
12792 // -----------------------------------------------------------------------------
12793 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH
12794 // Description : None
12795 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
12796 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
12797 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB    _u(21)
12798 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB    _u(21)
12799 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
12800 // -----------------------------------------------------------------------------
12801 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW
12802 // Description : None
12803 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
12804 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
12805 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB    _u(20)
12806 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB    _u(20)
12807 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
12808 // -----------------------------------------------------------------------------
12809 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH
12810 // Description : None
12811 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
12812 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
12813 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB    _u(19)
12814 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB    _u(19)
12815 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
12816 // -----------------------------------------------------------------------------
12817 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW
12818 // Description : None
12819 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET  _u(0x0)
12820 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
12821 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB    _u(18)
12822 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB    _u(18)
12823 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
12824 // -----------------------------------------------------------------------------
12825 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH
12826 // Description : None
12827 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
12828 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
12829 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB    _u(17)
12830 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB    _u(17)
12831 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
12832 // -----------------------------------------------------------------------------
12833 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW
12834 // Description : None
12835 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
12836 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
12837 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB    _u(16)
12838 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB    _u(16)
12839 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
12840 // -----------------------------------------------------------------------------
12841 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH
12842 // Description : None
12843 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
12844 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
12845 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB    _u(15)
12846 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB    _u(15)
12847 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
12848 // -----------------------------------------------------------------------------
12849 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW
12850 // Description : None
12851 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET  _u(0x0)
12852 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
12853 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB    _u(14)
12854 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB    _u(14)
12855 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
12856 // -----------------------------------------------------------------------------
12857 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH
12858 // Description : None
12859 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
12860 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
12861 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB    _u(13)
12862 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB    _u(13)
12863 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
12864 // -----------------------------------------------------------------------------
12865 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW
12866 // Description : None
12867 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
12868 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
12869 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB    _u(12)
12870 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB    _u(12)
12871 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
12872 // -----------------------------------------------------------------------------
12873 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH
12874 // Description : None
12875 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
12876 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
12877 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB    _u(11)
12878 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB    _u(11)
12879 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
12880 // -----------------------------------------------------------------------------
12881 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW
12882 // Description : None
12883 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET  _u(0x0)
12884 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
12885 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB    _u(10)
12886 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB    _u(10)
12887 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
12888 // -----------------------------------------------------------------------------
12889 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH
12890 // Description : None
12891 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
12892 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
12893 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB    _u(9)
12894 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB    _u(9)
12895 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
12896 // -----------------------------------------------------------------------------
12897 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW
12898 // Description : None
12899 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
12900 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
12901 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB    _u(8)
12902 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB    _u(8)
12903 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
12904 // -----------------------------------------------------------------------------
12905 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH
12906 // Description : None
12907 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
12908 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
12909 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB    _u(7)
12910 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB    _u(7)
12911 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
12912 // -----------------------------------------------------------------------------
12913 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW
12914 // Description : None
12915 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET  _u(0x0)
12916 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
12917 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB    _u(6)
12918 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB    _u(6)
12919 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
12920 // -----------------------------------------------------------------------------
12921 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH
12922 // Description : None
12923 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
12924 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
12925 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB    _u(5)
12926 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB    _u(5)
12927 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
12928 // -----------------------------------------------------------------------------
12929 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW
12930 // Description : None
12931 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
12932 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
12933 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB    _u(4)
12934 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB    _u(4)
12935 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
12936 // -----------------------------------------------------------------------------
12937 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH
12938 // Description : None
12939 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
12940 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
12941 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB    _u(3)
12942 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB    _u(3)
12943 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
12944 // -----------------------------------------------------------------------------
12945 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW
12946 // Description : None
12947 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET  _u(0x0)
12948 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
12949 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB    _u(2)
12950 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB    _u(2)
12951 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
12952 // -----------------------------------------------------------------------------
12953 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH
12954 // Description : None
12955 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
12956 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
12957 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB    _u(1)
12958 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB    _u(1)
12959 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
12960 // -----------------------------------------------------------------------------
12961 // Field       : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW
12962 // Description : None
12963 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
12964 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
12965 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB    _u(0)
12966 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB    _u(0)
12967 #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
12968 // =============================================================================
12969 // Register    : IO_BANK0_DORMANT_WAKE_INTF0
12970 // Description : Interrupt Force for dormant_wake
12971 #define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170)
12972 #define IO_BANK0_DORMANT_WAKE_INTF0_BITS   _u(0xffffffff)
12973 #define IO_BANK0_DORMANT_WAKE_INTF0_RESET  _u(0x00000000)
12974 // -----------------------------------------------------------------------------
12975 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH
12976 // Description : None
12977 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
12978 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
12979 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB    _u(31)
12980 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB    _u(31)
12981 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
12982 // -----------------------------------------------------------------------------
12983 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW
12984 // Description : None
12985 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET  _u(0x0)
12986 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
12987 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB    _u(30)
12988 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB    _u(30)
12989 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
12990 // -----------------------------------------------------------------------------
12991 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH
12992 // Description : None
12993 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
12994 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
12995 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB    _u(29)
12996 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB    _u(29)
12997 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
12998 // -----------------------------------------------------------------------------
12999 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW
13000 // Description : None
13001 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
13002 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
13003 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB    _u(28)
13004 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB    _u(28)
13005 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
13006 // -----------------------------------------------------------------------------
13007 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH
13008 // Description : None
13009 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
13010 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
13011 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB    _u(27)
13012 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB    _u(27)
13013 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
13014 // -----------------------------------------------------------------------------
13015 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW
13016 // Description : None
13017 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET  _u(0x0)
13018 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
13019 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB    _u(26)
13020 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB    _u(26)
13021 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
13022 // -----------------------------------------------------------------------------
13023 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH
13024 // Description : None
13025 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
13026 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
13027 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB    _u(25)
13028 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB    _u(25)
13029 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
13030 // -----------------------------------------------------------------------------
13031 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW
13032 // Description : None
13033 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
13034 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
13035 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB    _u(24)
13036 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB    _u(24)
13037 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
13038 // -----------------------------------------------------------------------------
13039 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH
13040 // Description : None
13041 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
13042 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
13043 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB    _u(23)
13044 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB    _u(23)
13045 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
13046 // -----------------------------------------------------------------------------
13047 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW
13048 // Description : None
13049 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET  _u(0x0)
13050 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
13051 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB    _u(22)
13052 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB    _u(22)
13053 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
13054 // -----------------------------------------------------------------------------
13055 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH
13056 // Description : None
13057 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
13058 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
13059 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB    _u(21)
13060 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB    _u(21)
13061 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
13062 // -----------------------------------------------------------------------------
13063 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW
13064 // Description : None
13065 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
13066 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
13067 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB    _u(20)
13068 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB    _u(20)
13069 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
13070 // -----------------------------------------------------------------------------
13071 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH
13072 // Description : None
13073 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
13074 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
13075 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB    _u(19)
13076 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB    _u(19)
13077 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
13078 // -----------------------------------------------------------------------------
13079 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW
13080 // Description : None
13081 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET  _u(0x0)
13082 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
13083 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB    _u(18)
13084 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB    _u(18)
13085 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
13086 // -----------------------------------------------------------------------------
13087 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH
13088 // Description : None
13089 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
13090 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
13091 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB    _u(17)
13092 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB    _u(17)
13093 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
13094 // -----------------------------------------------------------------------------
13095 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW
13096 // Description : None
13097 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
13098 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
13099 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB    _u(16)
13100 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB    _u(16)
13101 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
13102 // -----------------------------------------------------------------------------
13103 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH
13104 // Description : None
13105 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
13106 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
13107 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB    _u(15)
13108 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB    _u(15)
13109 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
13110 // -----------------------------------------------------------------------------
13111 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW
13112 // Description : None
13113 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET  _u(0x0)
13114 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
13115 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB    _u(14)
13116 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB    _u(14)
13117 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
13118 // -----------------------------------------------------------------------------
13119 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH
13120 // Description : None
13121 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
13122 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
13123 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB    _u(13)
13124 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB    _u(13)
13125 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
13126 // -----------------------------------------------------------------------------
13127 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW
13128 // Description : None
13129 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
13130 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
13131 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB    _u(12)
13132 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB    _u(12)
13133 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
13134 // -----------------------------------------------------------------------------
13135 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH
13136 // Description : None
13137 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
13138 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
13139 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB    _u(11)
13140 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB    _u(11)
13141 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
13142 // -----------------------------------------------------------------------------
13143 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW
13144 // Description : None
13145 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET  _u(0x0)
13146 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
13147 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB    _u(10)
13148 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB    _u(10)
13149 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
13150 // -----------------------------------------------------------------------------
13151 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH
13152 // Description : None
13153 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
13154 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
13155 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB    _u(9)
13156 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB    _u(9)
13157 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
13158 // -----------------------------------------------------------------------------
13159 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW
13160 // Description : None
13161 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
13162 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
13163 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB    _u(8)
13164 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB    _u(8)
13165 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
13166 // -----------------------------------------------------------------------------
13167 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH
13168 // Description : None
13169 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
13170 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
13171 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB    _u(7)
13172 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB    _u(7)
13173 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
13174 // -----------------------------------------------------------------------------
13175 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW
13176 // Description : None
13177 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET  _u(0x0)
13178 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
13179 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB    _u(6)
13180 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB    _u(6)
13181 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
13182 // -----------------------------------------------------------------------------
13183 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH
13184 // Description : None
13185 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
13186 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
13187 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB    _u(5)
13188 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB    _u(5)
13189 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
13190 // -----------------------------------------------------------------------------
13191 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW
13192 // Description : None
13193 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
13194 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
13195 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB    _u(4)
13196 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB    _u(4)
13197 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
13198 // -----------------------------------------------------------------------------
13199 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH
13200 // Description : None
13201 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
13202 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
13203 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB    _u(3)
13204 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB    _u(3)
13205 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
13206 // -----------------------------------------------------------------------------
13207 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW
13208 // Description : None
13209 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET  _u(0x0)
13210 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
13211 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB    _u(2)
13212 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB    _u(2)
13213 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
13214 // -----------------------------------------------------------------------------
13215 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH
13216 // Description : None
13217 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
13218 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
13219 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB    _u(1)
13220 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB    _u(1)
13221 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
13222 // -----------------------------------------------------------------------------
13223 // Field       : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW
13224 // Description : None
13225 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
13226 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
13227 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB    _u(0)
13228 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB    _u(0)
13229 #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
13230 // =============================================================================
13231 // Register    : IO_BANK0_DORMANT_WAKE_INTF1
13232 // Description : Interrupt Force for dormant_wake
13233 #define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174)
13234 #define IO_BANK0_DORMANT_WAKE_INTF1_BITS   _u(0xffffffff)
13235 #define IO_BANK0_DORMANT_WAKE_INTF1_RESET  _u(0x00000000)
13236 // -----------------------------------------------------------------------------
13237 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH
13238 // Description : None
13239 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
13240 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
13241 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB    _u(31)
13242 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB    _u(31)
13243 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
13244 // -----------------------------------------------------------------------------
13245 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW
13246 // Description : None
13247 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET  _u(0x0)
13248 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
13249 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB    _u(30)
13250 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB    _u(30)
13251 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
13252 // -----------------------------------------------------------------------------
13253 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH
13254 // Description : None
13255 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
13256 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
13257 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB    _u(29)
13258 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB    _u(29)
13259 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
13260 // -----------------------------------------------------------------------------
13261 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW
13262 // Description : None
13263 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
13264 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
13265 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB    _u(28)
13266 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB    _u(28)
13267 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
13268 // -----------------------------------------------------------------------------
13269 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH
13270 // Description : None
13271 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
13272 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
13273 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB    _u(27)
13274 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB    _u(27)
13275 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
13276 // -----------------------------------------------------------------------------
13277 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW
13278 // Description : None
13279 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET  _u(0x0)
13280 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
13281 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB    _u(26)
13282 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB    _u(26)
13283 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
13284 // -----------------------------------------------------------------------------
13285 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH
13286 // Description : None
13287 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
13288 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
13289 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB    _u(25)
13290 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB    _u(25)
13291 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
13292 // -----------------------------------------------------------------------------
13293 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW
13294 // Description : None
13295 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
13296 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
13297 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB    _u(24)
13298 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB    _u(24)
13299 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
13300 // -----------------------------------------------------------------------------
13301 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH
13302 // Description : None
13303 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
13304 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
13305 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB    _u(23)
13306 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB    _u(23)
13307 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
13308 // -----------------------------------------------------------------------------
13309 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW
13310 // Description : None
13311 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET  _u(0x0)
13312 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
13313 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB    _u(22)
13314 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB    _u(22)
13315 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
13316 // -----------------------------------------------------------------------------
13317 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH
13318 // Description : None
13319 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
13320 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
13321 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB    _u(21)
13322 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB    _u(21)
13323 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
13324 // -----------------------------------------------------------------------------
13325 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW
13326 // Description : None
13327 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
13328 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
13329 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB    _u(20)
13330 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB    _u(20)
13331 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
13332 // -----------------------------------------------------------------------------
13333 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH
13334 // Description : None
13335 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
13336 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
13337 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB    _u(19)
13338 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB    _u(19)
13339 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
13340 // -----------------------------------------------------------------------------
13341 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW
13342 // Description : None
13343 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET  _u(0x0)
13344 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
13345 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB    _u(18)
13346 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB    _u(18)
13347 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
13348 // -----------------------------------------------------------------------------
13349 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH
13350 // Description : None
13351 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
13352 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
13353 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB    _u(17)
13354 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB    _u(17)
13355 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
13356 // -----------------------------------------------------------------------------
13357 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW
13358 // Description : None
13359 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
13360 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
13361 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB    _u(16)
13362 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB    _u(16)
13363 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
13364 // -----------------------------------------------------------------------------
13365 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH
13366 // Description : None
13367 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
13368 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
13369 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB    _u(15)
13370 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB    _u(15)
13371 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
13372 // -----------------------------------------------------------------------------
13373 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW
13374 // Description : None
13375 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET  _u(0x0)
13376 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
13377 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB    _u(14)
13378 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB    _u(14)
13379 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
13380 // -----------------------------------------------------------------------------
13381 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH
13382 // Description : None
13383 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
13384 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
13385 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB    _u(13)
13386 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB    _u(13)
13387 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
13388 // -----------------------------------------------------------------------------
13389 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW
13390 // Description : None
13391 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
13392 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
13393 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB    _u(12)
13394 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB    _u(12)
13395 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
13396 // -----------------------------------------------------------------------------
13397 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH
13398 // Description : None
13399 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
13400 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
13401 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB    _u(11)
13402 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB    _u(11)
13403 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
13404 // -----------------------------------------------------------------------------
13405 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW
13406 // Description : None
13407 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET  _u(0x0)
13408 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
13409 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB    _u(10)
13410 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB    _u(10)
13411 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
13412 // -----------------------------------------------------------------------------
13413 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH
13414 // Description : None
13415 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
13416 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
13417 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB    _u(9)
13418 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB    _u(9)
13419 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
13420 // -----------------------------------------------------------------------------
13421 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW
13422 // Description : None
13423 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
13424 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
13425 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB    _u(8)
13426 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB    _u(8)
13427 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
13428 // -----------------------------------------------------------------------------
13429 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH
13430 // Description : None
13431 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
13432 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
13433 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB    _u(7)
13434 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB    _u(7)
13435 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
13436 // -----------------------------------------------------------------------------
13437 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW
13438 // Description : None
13439 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET  _u(0x0)
13440 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
13441 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB    _u(6)
13442 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB    _u(6)
13443 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
13444 // -----------------------------------------------------------------------------
13445 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH
13446 // Description : None
13447 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
13448 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
13449 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB    _u(5)
13450 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB    _u(5)
13451 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
13452 // -----------------------------------------------------------------------------
13453 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW
13454 // Description : None
13455 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
13456 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
13457 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB    _u(4)
13458 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB    _u(4)
13459 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
13460 // -----------------------------------------------------------------------------
13461 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH
13462 // Description : None
13463 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
13464 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
13465 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB    _u(3)
13466 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB    _u(3)
13467 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
13468 // -----------------------------------------------------------------------------
13469 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW
13470 // Description : None
13471 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET  _u(0x0)
13472 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
13473 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB    _u(2)
13474 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB    _u(2)
13475 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
13476 // -----------------------------------------------------------------------------
13477 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH
13478 // Description : None
13479 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
13480 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
13481 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB    _u(1)
13482 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB    _u(1)
13483 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
13484 // -----------------------------------------------------------------------------
13485 // Field       : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW
13486 // Description : None
13487 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
13488 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
13489 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB    _u(0)
13490 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB    _u(0)
13491 #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
13492 // =============================================================================
13493 // Register    : IO_BANK0_DORMANT_WAKE_INTF2
13494 // Description : Interrupt Force for dormant_wake
13495 #define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178)
13496 #define IO_BANK0_DORMANT_WAKE_INTF2_BITS   _u(0xffffffff)
13497 #define IO_BANK0_DORMANT_WAKE_INTF2_RESET  _u(0x00000000)
13498 // -----------------------------------------------------------------------------
13499 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH
13500 // Description : None
13501 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
13502 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
13503 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB    _u(31)
13504 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB    _u(31)
13505 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
13506 // -----------------------------------------------------------------------------
13507 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW
13508 // Description : None
13509 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET  _u(0x0)
13510 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
13511 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB    _u(30)
13512 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB    _u(30)
13513 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
13514 // -----------------------------------------------------------------------------
13515 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH
13516 // Description : None
13517 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
13518 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
13519 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB    _u(29)
13520 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB    _u(29)
13521 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
13522 // -----------------------------------------------------------------------------
13523 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW
13524 // Description : None
13525 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
13526 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
13527 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB    _u(28)
13528 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB    _u(28)
13529 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
13530 // -----------------------------------------------------------------------------
13531 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH
13532 // Description : None
13533 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
13534 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
13535 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB    _u(27)
13536 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB    _u(27)
13537 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
13538 // -----------------------------------------------------------------------------
13539 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW
13540 // Description : None
13541 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET  _u(0x0)
13542 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
13543 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB    _u(26)
13544 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB    _u(26)
13545 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
13546 // -----------------------------------------------------------------------------
13547 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH
13548 // Description : None
13549 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
13550 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
13551 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB    _u(25)
13552 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB    _u(25)
13553 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
13554 // -----------------------------------------------------------------------------
13555 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW
13556 // Description : None
13557 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
13558 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
13559 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB    _u(24)
13560 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB    _u(24)
13561 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
13562 // -----------------------------------------------------------------------------
13563 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH
13564 // Description : None
13565 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
13566 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
13567 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB    _u(23)
13568 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB    _u(23)
13569 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
13570 // -----------------------------------------------------------------------------
13571 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW
13572 // Description : None
13573 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET  _u(0x0)
13574 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
13575 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB    _u(22)
13576 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB    _u(22)
13577 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
13578 // -----------------------------------------------------------------------------
13579 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH
13580 // Description : None
13581 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
13582 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
13583 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB    _u(21)
13584 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB    _u(21)
13585 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
13586 // -----------------------------------------------------------------------------
13587 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW
13588 // Description : None
13589 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
13590 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
13591 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB    _u(20)
13592 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB    _u(20)
13593 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
13594 // -----------------------------------------------------------------------------
13595 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH
13596 // Description : None
13597 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
13598 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
13599 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB    _u(19)
13600 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB    _u(19)
13601 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
13602 // -----------------------------------------------------------------------------
13603 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW
13604 // Description : None
13605 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET  _u(0x0)
13606 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
13607 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB    _u(18)
13608 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB    _u(18)
13609 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
13610 // -----------------------------------------------------------------------------
13611 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH
13612 // Description : None
13613 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
13614 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
13615 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB    _u(17)
13616 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB    _u(17)
13617 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
13618 // -----------------------------------------------------------------------------
13619 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW
13620 // Description : None
13621 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
13622 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
13623 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB    _u(16)
13624 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB    _u(16)
13625 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
13626 // -----------------------------------------------------------------------------
13627 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH
13628 // Description : None
13629 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
13630 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
13631 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB    _u(15)
13632 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB    _u(15)
13633 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
13634 // -----------------------------------------------------------------------------
13635 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW
13636 // Description : None
13637 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET  _u(0x0)
13638 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
13639 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB    _u(14)
13640 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB    _u(14)
13641 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
13642 // -----------------------------------------------------------------------------
13643 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH
13644 // Description : None
13645 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
13646 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
13647 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB    _u(13)
13648 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB    _u(13)
13649 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
13650 // -----------------------------------------------------------------------------
13651 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW
13652 // Description : None
13653 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
13654 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
13655 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB    _u(12)
13656 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB    _u(12)
13657 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
13658 // -----------------------------------------------------------------------------
13659 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH
13660 // Description : None
13661 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
13662 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
13663 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB    _u(11)
13664 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB    _u(11)
13665 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
13666 // -----------------------------------------------------------------------------
13667 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW
13668 // Description : None
13669 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET  _u(0x0)
13670 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
13671 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB    _u(10)
13672 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB    _u(10)
13673 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
13674 // -----------------------------------------------------------------------------
13675 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH
13676 // Description : None
13677 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
13678 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
13679 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB    _u(9)
13680 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB    _u(9)
13681 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
13682 // -----------------------------------------------------------------------------
13683 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW
13684 // Description : None
13685 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
13686 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
13687 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB    _u(8)
13688 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB    _u(8)
13689 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
13690 // -----------------------------------------------------------------------------
13691 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH
13692 // Description : None
13693 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
13694 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
13695 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB    _u(7)
13696 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB    _u(7)
13697 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
13698 // -----------------------------------------------------------------------------
13699 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW
13700 // Description : None
13701 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET  _u(0x0)
13702 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
13703 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB    _u(6)
13704 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB    _u(6)
13705 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
13706 // -----------------------------------------------------------------------------
13707 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH
13708 // Description : None
13709 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
13710 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
13711 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB    _u(5)
13712 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB    _u(5)
13713 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
13714 // -----------------------------------------------------------------------------
13715 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW
13716 // Description : None
13717 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
13718 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
13719 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB    _u(4)
13720 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB    _u(4)
13721 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
13722 // -----------------------------------------------------------------------------
13723 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH
13724 // Description : None
13725 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
13726 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
13727 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB    _u(3)
13728 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB    _u(3)
13729 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
13730 // -----------------------------------------------------------------------------
13731 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW
13732 // Description : None
13733 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET  _u(0x0)
13734 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
13735 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB    _u(2)
13736 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB    _u(2)
13737 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
13738 // -----------------------------------------------------------------------------
13739 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH
13740 // Description : None
13741 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
13742 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
13743 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB    _u(1)
13744 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB    _u(1)
13745 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
13746 // -----------------------------------------------------------------------------
13747 // Field       : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW
13748 // Description : None
13749 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
13750 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
13751 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB    _u(0)
13752 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB    _u(0)
13753 #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
13754 // =============================================================================
13755 // Register    : IO_BANK0_DORMANT_WAKE_INTF3
13756 // Description : Interrupt Force for dormant_wake
13757 #define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c)
13758 #define IO_BANK0_DORMANT_WAKE_INTF3_BITS   _u(0x00ffffff)
13759 #define IO_BANK0_DORMANT_WAKE_INTF3_RESET  _u(0x00000000)
13760 // -----------------------------------------------------------------------------
13761 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH
13762 // Description : None
13763 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
13764 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
13765 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB    _u(23)
13766 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB    _u(23)
13767 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
13768 // -----------------------------------------------------------------------------
13769 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW
13770 // Description : None
13771 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET  _u(0x0)
13772 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
13773 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB    _u(22)
13774 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB    _u(22)
13775 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
13776 // -----------------------------------------------------------------------------
13777 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH
13778 // Description : None
13779 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
13780 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
13781 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB    _u(21)
13782 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB    _u(21)
13783 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
13784 // -----------------------------------------------------------------------------
13785 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW
13786 // Description : None
13787 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
13788 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
13789 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB    _u(20)
13790 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB    _u(20)
13791 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
13792 // -----------------------------------------------------------------------------
13793 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH
13794 // Description : None
13795 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
13796 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
13797 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB    _u(19)
13798 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB    _u(19)
13799 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
13800 // -----------------------------------------------------------------------------
13801 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW
13802 // Description : None
13803 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET  _u(0x0)
13804 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
13805 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB    _u(18)
13806 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB    _u(18)
13807 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
13808 // -----------------------------------------------------------------------------
13809 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH
13810 // Description : None
13811 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
13812 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
13813 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB    _u(17)
13814 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB    _u(17)
13815 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
13816 // -----------------------------------------------------------------------------
13817 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW
13818 // Description : None
13819 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
13820 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
13821 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB    _u(16)
13822 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB    _u(16)
13823 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
13824 // -----------------------------------------------------------------------------
13825 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH
13826 // Description : None
13827 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
13828 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
13829 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB    _u(15)
13830 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB    _u(15)
13831 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
13832 // -----------------------------------------------------------------------------
13833 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW
13834 // Description : None
13835 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET  _u(0x0)
13836 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
13837 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB    _u(14)
13838 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB    _u(14)
13839 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
13840 // -----------------------------------------------------------------------------
13841 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH
13842 // Description : None
13843 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
13844 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
13845 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB    _u(13)
13846 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB    _u(13)
13847 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
13848 // -----------------------------------------------------------------------------
13849 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW
13850 // Description : None
13851 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
13852 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
13853 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB    _u(12)
13854 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB    _u(12)
13855 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
13856 // -----------------------------------------------------------------------------
13857 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH
13858 // Description : None
13859 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
13860 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
13861 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB    _u(11)
13862 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB    _u(11)
13863 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
13864 // -----------------------------------------------------------------------------
13865 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW
13866 // Description : None
13867 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET  _u(0x0)
13868 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
13869 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB    _u(10)
13870 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB    _u(10)
13871 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
13872 // -----------------------------------------------------------------------------
13873 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH
13874 // Description : None
13875 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
13876 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
13877 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB    _u(9)
13878 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB    _u(9)
13879 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
13880 // -----------------------------------------------------------------------------
13881 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW
13882 // Description : None
13883 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
13884 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
13885 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB    _u(8)
13886 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB    _u(8)
13887 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
13888 // -----------------------------------------------------------------------------
13889 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH
13890 // Description : None
13891 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
13892 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
13893 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB    _u(7)
13894 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB    _u(7)
13895 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
13896 // -----------------------------------------------------------------------------
13897 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW
13898 // Description : None
13899 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET  _u(0x0)
13900 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
13901 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB    _u(6)
13902 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB    _u(6)
13903 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
13904 // -----------------------------------------------------------------------------
13905 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH
13906 // Description : None
13907 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
13908 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
13909 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB    _u(5)
13910 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB    _u(5)
13911 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
13912 // -----------------------------------------------------------------------------
13913 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW
13914 // Description : None
13915 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
13916 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
13917 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB    _u(4)
13918 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB    _u(4)
13919 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
13920 // -----------------------------------------------------------------------------
13921 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH
13922 // Description : None
13923 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
13924 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
13925 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB    _u(3)
13926 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB    _u(3)
13927 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
13928 // -----------------------------------------------------------------------------
13929 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW
13930 // Description : None
13931 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET  _u(0x0)
13932 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
13933 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB    _u(2)
13934 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB    _u(2)
13935 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
13936 // -----------------------------------------------------------------------------
13937 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH
13938 // Description : None
13939 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
13940 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
13941 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB    _u(1)
13942 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB    _u(1)
13943 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
13944 // -----------------------------------------------------------------------------
13945 // Field       : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW
13946 // Description : None
13947 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
13948 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
13949 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB    _u(0)
13950 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB    _u(0)
13951 #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
13952 // =============================================================================
13953 // Register    : IO_BANK0_DORMANT_WAKE_INTS0
13954 // Description : Interrupt status after masking & forcing for dormant_wake
13955 #define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180)
13956 #define IO_BANK0_DORMANT_WAKE_INTS0_BITS   _u(0xffffffff)
13957 #define IO_BANK0_DORMANT_WAKE_INTS0_RESET  _u(0x00000000)
13958 // -----------------------------------------------------------------------------
13959 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH
13960 // Description : None
13961 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET  _u(0x0)
13962 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS   _u(0x80000000)
13963 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB    _u(31)
13964 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB    _u(31)
13965 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
13966 // -----------------------------------------------------------------------------
13967 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW
13968 // Description : None
13969 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET  _u(0x0)
13970 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS   _u(0x40000000)
13971 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB    _u(30)
13972 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB    _u(30)
13973 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
13974 // -----------------------------------------------------------------------------
13975 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH
13976 // Description : None
13977 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET  _u(0x0)
13978 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS   _u(0x20000000)
13979 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB    _u(29)
13980 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB    _u(29)
13981 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
13982 // -----------------------------------------------------------------------------
13983 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW
13984 // Description : None
13985 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET  _u(0x0)
13986 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS   _u(0x10000000)
13987 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB    _u(28)
13988 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB    _u(28)
13989 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
13990 // -----------------------------------------------------------------------------
13991 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH
13992 // Description : None
13993 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET  _u(0x0)
13994 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS   _u(0x08000000)
13995 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB    _u(27)
13996 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB    _u(27)
13997 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
13998 // -----------------------------------------------------------------------------
13999 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW
14000 // Description : None
14001 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET  _u(0x0)
14002 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS   _u(0x04000000)
14003 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB    _u(26)
14004 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB    _u(26)
14005 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
14006 // -----------------------------------------------------------------------------
14007 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH
14008 // Description : None
14009 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET  _u(0x0)
14010 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS   _u(0x02000000)
14011 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB    _u(25)
14012 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB    _u(25)
14013 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
14014 // -----------------------------------------------------------------------------
14015 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW
14016 // Description : None
14017 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET  _u(0x0)
14018 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS   _u(0x01000000)
14019 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB    _u(24)
14020 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB    _u(24)
14021 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
14022 // -----------------------------------------------------------------------------
14023 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH
14024 // Description : None
14025 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET  _u(0x0)
14026 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS   _u(0x00800000)
14027 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB    _u(23)
14028 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB    _u(23)
14029 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
14030 // -----------------------------------------------------------------------------
14031 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW
14032 // Description : None
14033 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET  _u(0x0)
14034 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS   _u(0x00400000)
14035 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB    _u(22)
14036 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB    _u(22)
14037 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
14038 // -----------------------------------------------------------------------------
14039 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH
14040 // Description : None
14041 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET  _u(0x0)
14042 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS   _u(0x00200000)
14043 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB    _u(21)
14044 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB    _u(21)
14045 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
14046 // -----------------------------------------------------------------------------
14047 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW
14048 // Description : None
14049 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET  _u(0x0)
14050 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS   _u(0x00100000)
14051 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB    _u(20)
14052 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB    _u(20)
14053 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
14054 // -----------------------------------------------------------------------------
14055 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH
14056 // Description : None
14057 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET  _u(0x0)
14058 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS   _u(0x00080000)
14059 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB    _u(19)
14060 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB    _u(19)
14061 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
14062 // -----------------------------------------------------------------------------
14063 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW
14064 // Description : None
14065 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET  _u(0x0)
14066 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS   _u(0x00040000)
14067 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB    _u(18)
14068 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB    _u(18)
14069 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
14070 // -----------------------------------------------------------------------------
14071 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH
14072 // Description : None
14073 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET  _u(0x0)
14074 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS   _u(0x00020000)
14075 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB    _u(17)
14076 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB    _u(17)
14077 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
14078 // -----------------------------------------------------------------------------
14079 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW
14080 // Description : None
14081 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET  _u(0x0)
14082 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS   _u(0x00010000)
14083 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB    _u(16)
14084 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB    _u(16)
14085 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
14086 // -----------------------------------------------------------------------------
14087 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH
14088 // Description : None
14089 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET  _u(0x0)
14090 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS   _u(0x00008000)
14091 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB    _u(15)
14092 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB    _u(15)
14093 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
14094 // -----------------------------------------------------------------------------
14095 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW
14096 // Description : None
14097 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET  _u(0x0)
14098 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS   _u(0x00004000)
14099 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB    _u(14)
14100 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB    _u(14)
14101 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
14102 // -----------------------------------------------------------------------------
14103 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH
14104 // Description : None
14105 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET  _u(0x0)
14106 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS   _u(0x00002000)
14107 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB    _u(13)
14108 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB    _u(13)
14109 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
14110 // -----------------------------------------------------------------------------
14111 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW
14112 // Description : None
14113 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET  _u(0x0)
14114 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS   _u(0x00001000)
14115 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB    _u(12)
14116 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB    _u(12)
14117 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
14118 // -----------------------------------------------------------------------------
14119 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH
14120 // Description : None
14121 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET  _u(0x0)
14122 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS   _u(0x00000800)
14123 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB    _u(11)
14124 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB    _u(11)
14125 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
14126 // -----------------------------------------------------------------------------
14127 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW
14128 // Description : None
14129 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET  _u(0x0)
14130 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS   _u(0x00000400)
14131 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB    _u(10)
14132 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB    _u(10)
14133 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
14134 // -----------------------------------------------------------------------------
14135 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH
14136 // Description : None
14137 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET  _u(0x0)
14138 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS   _u(0x00000200)
14139 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB    _u(9)
14140 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB    _u(9)
14141 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
14142 // -----------------------------------------------------------------------------
14143 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW
14144 // Description : None
14145 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET  _u(0x0)
14146 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS   _u(0x00000100)
14147 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB    _u(8)
14148 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB    _u(8)
14149 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
14150 // -----------------------------------------------------------------------------
14151 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH
14152 // Description : None
14153 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET  _u(0x0)
14154 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS   _u(0x00000080)
14155 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB    _u(7)
14156 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB    _u(7)
14157 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
14158 // -----------------------------------------------------------------------------
14159 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW
14160 // Description : None
14161 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET  _u(0x0)
14162 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS   _u(0x00000040)
14163 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB    _u(6)
14164 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB    _u(6)
14165 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
14166 // -----------------------------------------------------------------------------
14167 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH
14168 // Description : None
14169 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET  _u(0x0)
14170 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS   _u(0x00000020)
14171 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB    _u(5)
14172 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB    _u(5)
14173 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
14174 // -----------------------------------------------------------------------------
14175 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW
14176 // Description : None
14177 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET  _u(0x0)
14178 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS   _u(0x00000010)
14179 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB    _u(4)
14180 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB    _u(4)
14181 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
14182 // -----------------------------------------------------------------------------
14183 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH
14184 // Description : None
14185 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET  _u(0x0)
14186 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS   _u(0x00000008)
14187 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB    _u(3)
14188 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB    _u(3)
14189 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
14190 // -----------------------------------------------------------------------------
14191 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW
14192 // Description : None
14193 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET  _u(0x0)
14194 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS   _u(0x00000004)
14195 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB    _u(2)
14196 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB    _u(2)
14197 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
14198 // -----------------------------------------------------------------------------
14199 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH
14200 // Description : None
14201 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET  _u(0x0)
14202 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS   _u(0x00000002)
14203 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB    _u(1)
14204 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB    _u(1)
14205 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
14206 // -----------------------------------------------------------------------------
14207 // Field       : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW
14208 // Description : None
14209 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET  _u(0x0)
14210 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS   _u(0x00000001)
14211 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB    _u(0)
14212 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB    _u(0)
14213 #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
14214 // =============================================================================
14215 // Register    : IO_BANK0_DORMANT_WAKE_INTS1
14216 // Description : Interrupt status after masking & forcing for dormant_wake
14217 #define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184)
14218 #define IO_BANK0_DORMANT_WAKE_INTS1_BITS   _u(0xffffffff)
14219 #define IO_BANK0_DORMANT_WAKE_INTS1_RESET  _u(0x00000000)
14220 // -----------------------------------------------------------------------------
14221 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH
14222 // Description : None
14223 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET  _u(0x0)
14224 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS   _u(0x80000000)
14225 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB    _u(31)
14226 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB    _u(31)
14227 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
14228 // -----------------------------------------------------------------------------
14229 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW
14230 // Description : None
14231 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET  _u(0x0)
14232 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS   _u(0x40000000)
14233 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB    _u(30)
14234 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB    _u(30)
14235 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
14236 // -----------------------------------------------------------------------------
14237 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH
14238 // Description : None
14239 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET  _u(0x0)
14240 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS   _u(0x20000000)
14241 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB    _u(29)
14242 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB    _u(29)
14243 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
14244 // -----------------------------------------------------------------------------
14245 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW
14246 // Description : None
14247 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET  _u(0x0)
14248 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS   _u(0x10000000)
14249 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB    _u(28)
14250 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB    _u(28)
14251 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
14252 // -----------------------------------------------------------------------------
14253 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH
14254 // Description : None
14255 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET  _u(0x0)
14256 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS   _u(0x08000000)
14257 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB    _u(27)
14258 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB    _u(27)
14259 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
14260 // -----------------------------------------------------------------------------
14261 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW
14262 // Description : None
14263 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET  _u(0x0)
14264 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS   _u(0x04000000)
14265 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB    _u(26)
14266 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB    _u(26)
14267 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
14268 // -----------------------------------------------------------------------------
14269 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH
14270 // Description : None
14271 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET  _u(0x0)
14272 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS   _u(0x02000000)
14273 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB    _u(25)
14274 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB    _u(25)
14275 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
14276 // -----------------------------------------------------------------------------
14277 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW
14278 // Description : None
14279 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET  _u(0x0)
14280 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS   _u(0x01000000)
14281 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB    _u(24)
14282 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB    _u(24)
14283 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
14284 // -----------------------------------------------------------------------------
14285 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH
14286 // Description : None
14287 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET  _u(0x0)
14288 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS   _u(0x00800000)
14289 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB    _u(23)
14290 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB    _u(23)
14291 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
14292 // -----------------------------------------------------------------------------
14293 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW
14294 // Description : None
14295 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET  _u(0x0)
14296 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS   _u(0x00400000)
14297 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB    _u(22)
14298 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB    _u(22)
14299 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
14300 // -----------------------------------------------------------------------------
14301 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH
14302 // Description : None
14303 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET  _u(0x0)
14304 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS   _u(0x00200000)
14305 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB    _u(21)
14306 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB    _u(21)
14307 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
14308 // -----------------------------------------------------------------------------
14309 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW
14310 // Description : None
14311 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET  _u(0x0)
14312 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS   _u(0x00100000)
14313 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB    _u(20)
14314 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB    _u(20)
14315 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
14316 // -----------------------------------------------------------------------------
14317 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH
14318 // Description : None
14319 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET  _u(0x0)
14320 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS   _u(0x00080000)
14321 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB    _u(19)
14322 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB    _u(19)
14323 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
14324 // -----------------------------------------------------------------------------
14325 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW
14326 // Description : None
14327 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET  _u(0x0)
14328 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS   _u(0x00040000)
14329 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB    _u(18)
14330 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB    _u(18)
14331 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
14332 // -----------------------------------------------------------------------------
14333 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH
14334 // Description : None
14335 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET  _u(0x0)
14336 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS   _u(0x00020000)
14337 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB    _u(17)
14338 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB    _u(17)
14339 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
14340 // -----------------------------------------------------------------------------
14341 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW
14342 // Description : None
14343 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET  _u(0x0)
14344 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS   _u(0x00010000)
14345 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB    _u(16)
14346 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB    _u(16)
14347 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
14348 // -----------------------------------------------------------------------------
14349 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH
14350 // Description : None
14351 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET  _u(0x0)
14352 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS   _u(0x00008000)
14353 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB    _u(15)
14354 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB    _u(15)
14355 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
14356 // -----------------------------------------------------------------------------
14357 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW
14358 // Description : None
14359 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET  _u(0x0)
14360 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS   _u(0x00004000)
14361 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB    _u(14)
14362 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB    _u(14)
14363 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
14364 // -----------------------------------------------------------------------------
14365 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH
14366 // Description : None
14367 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET  _u(0x0)
14368 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS   _u(0x00002000)
14369 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB    _u(13)
14370 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB    _u(13)
14371 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
14372 // -----------------------------------------------------------------------------
14373 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW
14374 // Description : None
14375 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET  _u(0x0)
14376 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS   _u(0x00001000)
14377 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB    _u(12)
14378 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB    _u(12)
14379 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
14380 // -----------------------------------------------------------------------------
14381 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH
14382 // Description : None
14383 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET  _u(0x0)
14384 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS   _u(0x00000800)
14385 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB    _u(11)
14386 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB    _u(11)
14387 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
14388 // -----------------------------------------------------------------------------
14389 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW
14390 // Description : None
14391 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET  _u(0x0)
14392 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS   _u(0x00000400)
14393 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB    _u(10)
14394 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB    _u(10)
14395 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
14396 // -----------------------------------------------------------------------------
14397 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH
14398 // Description : None
14399 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET  _u(0x0)
14400 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS   _u(0x00000200)
14401 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB    _u(9)
14402 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB    _u(9)
14403 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
14404 // -----------------------------------------------------------------------------
14405 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW
14406 // Description : None
14407 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET  _u(0x0)
14408 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS   _u(0x00000100)
14409 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB    _u(8)
14410 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB    _u(8)
14411 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
14412 // -----------------------------------------------------------------------------
14413 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH
14414 // Description : None
14415 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET  _u(0x0)
14416 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS   _u(0x00000080)
14417 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB    _u(7)
14418 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB    _u(7)
14419 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
14420 // -----------------------------------------------------------------------------
14421 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW
14422 // Description : None
14423 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET  _u(0x0)
14424 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS   _u(0x00000040)
14425 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB    _u(6)
14426 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB    _u(6)
14427 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
14428 // -----------------------------------------------------------------------------
14429 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH
14430 // Description : None
14431 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET  _u(0x0)
14432 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS   _u(0x00000020)
14433 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB    _u(5)
14434 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB    _u(5)
14435 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
14436 // -----------------------------------------------------------------------------
14437 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW
14438 // Description : None
14439 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET  _u(0x0)
14440 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS   _u(0x00000010)
14441 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB    _u(4)
14442 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB    _u(4)
14443 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
14444 // -----------------------------------------------------------------------------
14445 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH
14446 // Description : None
14447 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET  _u(0x0)
14448 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS   _u(0x00000008)
14449 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB    _u(3)
14450 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB    _u(3)
14451 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
14452 // -----------------------------------------------------------------------------
14453 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW
14454 // Description : None
14455 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET  _u(0x0)
14456 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS   _u(0x00000004)
14457 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB    _u(2)
14458 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB    _u(2)
14459 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
14460 // -----------------------------------------------------------------------------
14461 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH
14462 // Description : None
14463 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET  _u(0x0)
14464 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS   _u(0x00000002)
14465 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB    _u(1)
14466 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB    _u(1)
14467 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
14468 // -----------------------------------------------------------------------------
14469 // Field       : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW
14470 // Description : None
14471 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET  _u(0x0)
14472 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS   _u(0x00000001)
14473 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB    _u(0)
14474 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB    _u(0)
14475 #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
14476 // =============================================================================
14477 // Register    : IO_BANK0_DORMANT_WAKE_INTS2
14478 // Description : Interrupt status after masking & forcing for dormant_wake
14479 #define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188)
14480 #define IO_BANK0_DORMANT_WAKE_INTS2_BITS   _u(0xffffffff)
14481 #define IO_BANK0_DORMANT_WAKE_INTS2_RESET  _u(0x00000000)
14482 // -----------------------------------------------------------------------------
14483 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH
14484 // Description : None
14485 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET  _u(0x0)
14486 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS   _u(0x80000000)
14487 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB    _u(31)
14488 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB    _u(31)
14489 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
14490 // -----------------------------------------------------------------------------
14491 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW
14492 // Description : None
14493 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET  _u(0x0)
14494 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS   _u(0x40000000)
14495 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB    _u(30)
14496 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB    _u(30)
14497 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
14498 // -----------------------------------------------------------------------------
14499 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH
14500 // Description : None
14501 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET  _u(0x0)
14502 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS   _u(0x20000000)
14503 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB    _u(29)
14504 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB    _u(29)
14505 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
14506 // -----------------------------------------------------------------------------
14507 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW
14508 // Description : None
14509 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET  _u(0x0)
14510 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS   _u(0x10000000)
14511 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB    _u(28)
14512 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB    _u(28)
14513 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
14514 // -----------------------------------------------------------------------------
14515 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH
14516 // Description : None
14517 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET  _u(0x0)
14518 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS   _u(0x08000000)
14519 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB    _u(27)
14520 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB    _u(27)
14521 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
14522 // -----------------------------------------------------------------------------
14523 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW
14524 // Description : None
14525 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET  _u(0x0)
14526 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS   _u(0x04000000)
14527 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB    _u(26)
14528 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB    _u(26)
14529 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
14530 // -----------------------------------------------------------------------------
14531 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH
14532 // Description : None
14533 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET  _u(0x0)
14534 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS   _u(0x02000000)
14535 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB    _u(25)
14536 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB    _u(25)
14537 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
14538 // -----------------------------------------------------------------------------
14539 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW
14540 // Description : None
14541 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET  _u(0x0)
14542 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS   _u(0x01000000)
14543 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB    _u(24)
14544 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB    _u(24)
14545 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
14546 // -----------------------------------------------------------------------------
14547 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH
14548 // Description : None
14549 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET  _u(0x0)
14550 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS   _u(0x00800000)
14551 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB    _u(23)
14552 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB    _u(23)
14553 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
14554 // -----------------------------------------------------------------------------
14555 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW
14556 // Description : None
14557 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET  _u(0x0)
14558 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS   _u(0x00400000)
14559 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB    _u(22)
14560 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB    _u(22)
14561 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
14562 // -----------------------------------------------------------------------------
14563 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH
14564 // Description : None
14565 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET  _u(0x0)
14566 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS   _u(0x00200000)
14567 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB    _u(21)
14568 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB    _u(21)
14569 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
14570 // -----------------------------------------------------------------------------
14571 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW
14572 // Description : None
14573 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET  _u(0x0)
14574 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS   _u(0x00100000)
14575 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB    _u(20)
14576 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB    _u(20)
14577 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
14578 // -----------------------------------------------------------------------------
14579 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH
14580 // Description : None
14581 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET  _u(0x0)
14582 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS   _u(0x00080000)
14583 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB    _u(19)
14584 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB    _u(19)
14585 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
14586 // -----------------------------------------------------------------------------
14587 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW
14588 // Description : None
14589 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET  _u(0x0)
14590 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS   _u(0x00040000)
14591 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB    _u(18)
14592 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB    _u(18)
14593 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
14594 // -----------------------------------------------------------------------------
14595 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH
14596 // Description : None
14597 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET  _u(0x0)
14598 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS   _u(0x00020000)
14599 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB    _u(17)
14600 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB    _u(17)
14601 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
14602 // -----------------------------------------------------------------------------
14603 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW
14604 // Description : None
14605 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET  _u(0x0)
14606 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS   _u(0x00010000)
14607 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB    _u(16)
14608 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB    _u(16)
14609 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
14610 // -----------------------------------------------------------------------------
14611 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH
14612 // Description : None
14613 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET  _u(0x0)
14614 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS   _u(0x00008000)
14615 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB    _u(15)
14616 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB    _u(15)
14617 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
14618 // -----------------------------------------------------------------------------
14619 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW
14620 // Description : None
14621 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET  _u(0x0)
14622 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS   _u(0x00004000)
14623 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB    _u(14)
14624 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB    _u(14)
14625 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
14626 // -----------------------------------------------------------------------------
14627 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH
14628 // Description : None
14629 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET  _u(0x0)
14630 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS   _u(0x00002000)
14631 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB    _u(13)
14632 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB    _u(13)
14633 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
14634 // -----------------------------------------------------------------------------
14635 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW
14636 // Description : None
14637 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET  _u(0x0)
14638 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS   _u(0x00001000)
14639 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB    _u(12)
14640 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB    _u(12)
14641 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
14642 // -----------------------------------------------------------------------------
14643 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH
14644 // Description : None
14645 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET  _u(0x0)
14646 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS   _u(0x00000800)
14647 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB    _u(11)
14648 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB    _u(11)
14649 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
14650 // -----------------------------------------------------------------------------
14651 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW
14652 // Description : None
14653 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET  _u(0x0)
14654 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS   _u(0x00000400)
14655 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB    _u(10)
14656 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB    _u(10)
14657 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
14658 // -----------------------------------------------------------------------------
14659 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH
14660 // Description : None
14661 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET  _u(0x0)
14662 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS   _u(0x00000200)
14663 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB    _u(9)
14664 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB    _u(9)
14665 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
14666 // -----------------------------------------------------------------------------
14667 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW
14668 // Description : None
14669 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET  _u(0x0)
14670 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS   _u(0x00000100)
14671 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB    _u(8)
14672 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB    _u(8)
14673 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
14674 // -----------------------------------------------------------------------------
14675 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH
14676 // Description : None
14677 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET  _u(0x0)
14678 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS   _u(0x00000080)
14679 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB    _u(7)
14680 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB    _u(7)
14681 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
14682 // -----------------------------------------------------------------------------
14683 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW
14684 // Description : None
14685 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET  _u(0x0)
14686 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS   _u(0x00000040)
14687 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB    _u(6)
14688 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB    _u(6)
14689 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
14690 // -----------------------------------------------------------------------------
14691 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH
14692 // Description : None
14693 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET  _u(0x0)
14694 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS   _u(0x00000020)
14695 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB    _u(5)
14696 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB    _u(5)
14697 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
14698 // -----------------------------------------------------------------------------
14699 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW
14700 // Description : None
14701 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET  _u(0x0)
14702 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS   _u(0x00000010)
14703 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB    _u(4)
14704 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB    _u(4)
14705 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
14706 // -----------------------------------------------------------------------------
14707 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH
14708 // Description : None
14709 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET  _u(0x0)
14710 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS   _u(0x00000008)
14711 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB    _u(3)
14712 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB    _u(3)
14713 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
14714 // -----------------------------------------------------------------------------
14715 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW
14716 // Description : None
14717 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET  _u(0x0)
14718 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS   _u(0x00000004)
14719 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB    _u(2)
14720 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB    _u(2)
14721 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
14722 // -----------------------------------------------------------------------------
14723 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH
14724 // Description : None
14725 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET  _u(0x0)
14726 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS   _u(0x00000002)
14727 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB    _u(1)
14728 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB    _u(1)
14729 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
14730 // -----------------------------------------------------------------------------
14731 // Field       : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW
14732 // Description : None
14733 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET  _u(0x0)
14734 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS   _u(0x00000001)
14735 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB    _u(0)
14736 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB    _u(0)
14737 #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
14738 // =============================================================================
14739 // Register    : IO_BANK0_DORMANT_WAKE_INTS3
14740 // Description : Interrupt status after masking & forcing for dormant_wake
14741 #define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c)
14742 #define IO_BANK0_DORMANT_WAKE_INTS3_BITS   _u(0x00ffffff)
14743 #define IO_BANK0_DORMANT_WAKE_INTS3_RESET  _u(0x00000000)
14744 // -----------------------------------------------------------------------------
14745 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH
14746 // Description : None
14747 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET  _u(0x0)
14748 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS   _u(0x00800000)
14749 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB    _u(23)
14750 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB    _u(23)
14751 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
14752 // -----------------------------------------------------------------------------
14753 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW
14754 // Description : None
14755 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET  _u(0x0)
14756 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS   _u(0x00400000)
14757 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB    _u(22)
14758 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB    _u(22)
14759 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
14760 // -----------------------------------------------------------------------------
14761 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH
14762 // Description : None
14763 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET  _u(0x0)
14764 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS   _u(0x00200000)
14765 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB    _u(21)
14766 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB    _u(21)
14767 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
14768 // -----------------------------------------------------------------------------
14769 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW
14770 // Description : None
14771 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET  _u(0x0)
14772 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS   _u(0x00100000)
14773 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB    _u(20)
14774 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB    _u(20)
14775 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
14776 // -----------------------------------------------------------------------------
14777 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH
14778 // Description : None
14779 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET  _u(0x0)
14780 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS   _u(0x00080000)
14781 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB    _u(19)
14782 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB    _u(19)
14783 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
14784 // -----------------------------------------------------------------------------
14785 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW
14786 // Description : None
14787 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET  _u(0x0)
14788 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS   _u(0x00040000)
14789 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB    _u(18)
14790 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB    _u(18)
14791 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
14792 // -----------------------------------------------------------------------------
14793 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH
14794 // Description : None
14795 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET  _u(0x0)
14796 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS   _u(0x00020000)
14797 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB    _u(17)
14798 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB    _u(17)
14799 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
14800 // -----------------------------------------------------------------------------
14801 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW
14802 // Description : None
14803 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET  _u(0x0)
14804 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS   _u(0x00010000)
14805 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB    _u(16)
14806 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB    _u(16)
14807 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
14808 // -----------------------------------------------------------------------------
14809 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH
14810 // Description : None
14811 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET  _u(0x0)
14812 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS   _u(0x00008000)
14813 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB    _u(15)
14814 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB    _u(15)
14815 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
14816 // -----------------------------------------------------------------------------
14817 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW
14818 // Description : None
14819 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET  _u(0x0)
14820 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS   _u(0x00004000)
14821 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB    _u(14)
14822 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB    _u(14)
14823 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
14824 // -----------------------------------------------------------------------------
14825 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH
14826 // Description : None
14827 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET  _u(0x0)
14828 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS   _u(0x00002000)
14829 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB    _u(13)
14830 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB    _u(13)
14831 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
14832 // -----------------------------------------------------------------------------
14833 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW
14834 // Description : None
14835 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET  _u(0x0)
14836 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS   _u(0x00001000)
14837 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB    _u(12)
14838 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB    _u(12)
14839 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
14840 // -----------------------------------------------------------------------------
14841 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH
14842 // Description : None
14843 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET  _u(0x0)
14844 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS   _u(0x00000800)
14845 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB    _u(11)
14846 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB    _u(11)
14847 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
14848 // -----------------------------------------------------------------------------
14849 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW
14850 // Description : None
14851 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET  _u(0x0)
14852 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS   _u(0x00000400)
14853 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB    _u(10)
14854 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB    _u(10)
14855 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
14856 // -----------------------------------------------------------------------------
14857 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH
14858 // Description : None
14859 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET  _u(0x0)
14860 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS   _u(0x00000200)
14861 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB    _u(9)
14862 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB    _u(9)
14863 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
14864 // -----------------------------------------------------------------------------
14865 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW
14866 // Description : None
14867 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET  _u(0x0)
14868 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS   _u(0x00000100)
14869 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB    _u(8)
14870 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB    _u(8)
14871 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
14872 // -----------------------------------------------------------------------------
14873 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH
14874 // Description : None
14875 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET  _u(0x0)
14876 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS   _u(0x00000080)
14877 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB    _u(7)
14878 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB    _u(7)
14879 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
14880 // -----------------------------------------------------------------------------
14881 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW
14882 // Description : None
14883 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET  _u(0x0)
14884 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS   _u(0x00000040)
14885 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB    _u(6)
14886 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB    _u(6)
14887 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
14888 // -----------------------------------------------------------------------------
14889 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH
14890 // Description : None
14891 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET  _u(0x0)
14892 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS   _u(0x00000020)
14893 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB    _u(5)
14894 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB    _u(5)
14895 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
14896 // -----------------------------------------------------------------------------
14897 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW
14898 // Description : None
14899 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET  _u(0x0)
14900 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS   _u(0x00000010)
14901 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB    _u(4)
14902 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB    _u(4)
14903 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
14904 // -----------------------------------------------------------------------------
14905 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH
14906 // Description : None
14907 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET  _u(0x0)
14908 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS   _u(0x00000008)
14909 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB    _u(3)
14910 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB    _u(3)
14911 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
14912 // -----------------------------------------------------------------------------
14913 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW
14914 // Description : None
14915 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET  _u(0x0)
14916 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS   _u(0x00000004)
14917 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB    _u(2)
14918 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB    _u(2)
14919 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
14920 // -----------------------------------------------------------------------------
14921 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH
14922 // Description : None
14923 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET  _u(0x0)
14924 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS   _u(0x00000002)
14925 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB    _u(1)
14926 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB    _u(1)
14927 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
14928 // -----------------------------------------------------------------------------
14929 // Field       : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW
14930 // Description : None
14931 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET  _u(0x0)
14932 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS   _u(0x00000001)
14933 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB    _u(0)
14934 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB    _u(0)
14935 #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
14936 // =============================================================================
14937 #endif // HARDWARE_REGS_IO_BANK0_DEFINED
14938