1 /**
2  * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 // =============================================================================
7 // Register block : CLOCKS
8 // Version        : 1
9 // Bus type       : apb
10 // Description    : None
11 // =============================================================================
12 #ifndef HARDWARE_REGS_CLOCKS_DEFINED
13 #define HARDWARE_REGS_CLOCKS_DEFINED
14 // =============================================================================
15 // Register    : CLOCKS_CLK_GPOUT0_CTRL
16 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
17 #define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000)
18 #define CLOCKS_CLK_GPOUT0_CTRL_BITS   _u(0x00131de0)
19 #define CLOCKS_CLK_GPOUT0_CTRL_RESET  _u(0x00000000)
20 // -----------------------------------------------------------------------------
21 // Field       : CLOCKS_CLK_GPOUT0_CTRL_NUDGE
22 // Description : An edge on this signal shifts the phase of the output by 1
23 //               cycle of the input clock
24 //               This can be done at any time
25 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET  _u(0x0)
26 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS   _u(0x00100000)
27 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB    _u(20)
28 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB    _u(20)
29 #define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW"
30 // -----------------------------------------------------------------------------
31 // Field       : CLOCKS_CLK_GPOUT0_CTRL_PHASE
32 // Description : This delays the enable signal by up to 3 cycles of the input
33 //               clock
34 //               This must be set before the clock is enabled to have any effect
35 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET  _u(0x0)
36 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS   _u(0x00030000)
37 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB    _u(17)
38 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB    _u(16)
39 #define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW"
40 // -----------------------------------------------------------------------------
41 // Field       : CLOCKS_CLK_GPOUT0_CTRL_DC50
42 // Description : Enables duty cycle correction for odd divisors
43 #define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET  _u(0x0)
44 #define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS   _u(0x00001000)
45 #define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB    _u(12)
46 #define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB    _u(12)
47 #define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW"
48 // -----------------------------------------------------------------------------
49 // Field       : CLOCKS_CLK_GPOUT0_CTRL_ENABLE
50 // Description : Starts and stops the clock generator cleanly
51 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET  _u(0x0)
52 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS   _u(0x00000800)
53 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB    _u(11)
54 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB    _u(11)
55 #define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW"
56 // -----------------------------------------------------------------------------
57 // Field       : CLOCKS_CLK_GPOUT0_CTRL_KILL
58 // Description : Asynchronously kills the clock generator
59 #define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET  _u(0x0)
60 #define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS   _u(0x00000400)
61 #define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB    _u(10)
62 #define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB    _u(10)
63 #define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW"
64 // -----------------------------------------------------------------------------
65 // Field       : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC
66 // Description : Selects the auxiliary clock source, will glitch when switching
67 //               0x0 -> clksrc_pll_sys
68 //               0x1 -> clksrc_gpin0
69 //               0x2 -> clksrc_gpin1
70 //               0x3 -> clksrc_pll_usb
71 //               0x4 -> rosc_clksrc
72 //               0x5 -> xosc_clksrc
73 //               0x6 -> clk_sys
74 //               0x7 -> clk_usb
75 //               0x8 -> clk_adc
76 //               0x9 -> clk_rtc
77 //               0xa -> clk_ref
78 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET                _u(0x0)
79 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS                 _u(0x000001e0)
80 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB                  _u(8)
81 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB                  _u(5)
82 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS               "RW"
83 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
84 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
85 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
86 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
87 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    _u(0x4)
88 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
89 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
90 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
91 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
92 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
93 #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
94 // =============================================================================
95 // Register    : CLOCKS_CLK_GPOUT0_DIV
96 // Description : Clock divisor, can be changed on-the-fly
97 #define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004)
98 #define CLOCKS_CLK_GPOUT0_DIV_BITS   _u(0xffffffff)
99 #define CLOCKS_CLK_GPOUT0_DIV_RESET  _u(0x00000100)
100 // -----------------------------------------------------------------------------
101 // Field       : CLOCKS_CLK_GPOUT0_DIV_INT
102 // Description : Integer component of the divisor, 0 -> divide by 2^16
103 #define CLOCKS_CLK_GPOUT0_DIV_INT_RESET  _u(0x000001)
104 #define CLOCKS_CLK_GPOUT0_DIV_INT_BITS   _u(0xffffff00)
105 #define CLOCKS_CLK_GPOUT0_DIV_INT_MSB    _u(31)
106 #define CLOCKS_CLK_GPOUT0_DIV_INT_LSB    _u(8)
107 #define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW"
108 // -----------------------------------------------------------------------------
109 // Field       : CLOCKS_CLK_GPOUT0_DIV_FRAC
110 // Description : Fractional component of the divisor
111 #define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET  _u(0x00)
112 #define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS   _u(0x000000ff)
113 #define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB    _u(7)
114 #define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB    _u(0)
115 #define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW"
116 // =============================================================================
117 // Register    : CLOCKS_CLK_GPOUT0_SELECTED
118 // Description : Indicates which SRC is currently selected by the glitchless mux
119 //               (one-hot).
120 //               This slice does not have a glitchless mux (only the AUX_SRC
121 //               field is present, not SRC) so this register is hardwired to
122 //               0x1.
123 #define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008)
124 #define CLOCKS_CLK_GPOUT0_SELECTED_BITS   _u(0xffffffff)
125 #define CLOCKS_CLK_GPOUT0_SELECTED_RESET  _u(0x00000001)
126 #define CLOCKS_CLK_GPOUT0_SELECTED_MSB    _u(31)
127 #define CLOCKS_CLK_GPOUT0_SELECTED_LSB    _u(0)
128 #define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO"
129 // =============================================================================
130 // Register    : CLOCKS_CLK_GPOUT1_CTRL
131 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
132 #define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c)
133 #define CLOCKS_CLK_GPOUT1_CTRL_BITS   _u(0x00131de0)
134 #define CLOCKS_CLK_GPOUT1_CTRL_RESET  _u(0x00000000)
135 // -----------------------------------------------------------------------------
136 // Field       : CLOCKS_CLK_GPOUT1_CTRL_NUDGE
137 // Description : An edge on this signal shifts the phase of the output by 1
138 //               cycle of the input clock
139 //               This can be done at any time
140 #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET  _u(0x0)
141 #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS   _u(0x00100000)
142 #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB    _u(20)
143 #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB    _u(20)
144 #define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW"
145 // -----------------------------------------------------------------------------
146 // Field       : CLOCKS_CLK_GPOUT1_CTRL_PHASE
147 // Description : This delays the enable signal by up to 3 cycles of the input
148 //               clock
149 //               This must be set before the clock is enabled to have any effect
150 #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET  _u(0x0)
151 #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS   _u(0x00030000)
152 #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB    _u(17)
153 #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB    _u(16)
154 #define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW"
155 // -----------------------------------------------------------------------------
156 // Field       : CLOCKS_CLK_GPOUT1_CTRL_DC50
157 // Description : Enables duty cycle correction for odd divisors
158 #define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET  _u(0x0)
159 #define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS   _u(0x00001000)
160 #define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB    _u(12)
161 #define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB    _u(12)
162 #define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW"
163 // -----------------------------------------------------------------------------
164 // Field       : CLOCKS_CLK_GPOUT1_CTRL_ENABLE
165 // Description : Starts and stops the clock generator cleanly
166 #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET  _u(0x0)
167 #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS   _u(0x00000800)
168 #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB    _u(11)
169 #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB    _u(11)
170 #define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW"
171 // -----------------------------------------------------------------------------
172 // Field       : CLOCKS_CLK_GPOUT1_CTRL_KILL
173 // Description : Asynchronously kills the clock generator
174 #define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET  _u(0x0)
175 #define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS   _u(0x00000400)
176 #define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB    _u(10)
177 #define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB    _u(10)
178 #define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW"
179 // -----------------------------------------------------------------------------
180 // Field       : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC
181 // Description : Selects the auxiliary clock source, will glitch when switching
182 //               0x0 -> clksrc_pll_sys
183 //               0x1 -> clksrc_gpin0
184 //               0x2 -> clksrc_gpin1
185 //               0x3 -> clksrc_pll_usb
186 //               0x4 -> rosc_clksrc
187 //               0x5 -> xosc_clksrc
188 //               0x6 -> clk_sys
189 //               0x7 -> clk_usb
190 //               0x8 -> clk_adc
191 //               0x9 -> clk_rtc
192 //               0xa -> clk_ref
193 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET                _u(0x0)
194 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS                 _u(0x000001e0)
195 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB                  _u(8)
196 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB                  _u(5)
197 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS               "RW"
198 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
199 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
200 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
201 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
202 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    _u(0x4)
203 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
204 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
205 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
206 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
207 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
208 #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
209 // =============================================================================
210 // Register    : CLOCKS_CLK_GPOUT1_DIV
211 // Description : Clock divisor, can be changed on-the-fly
212 #define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010)
213 #define CLOCKS_CLK_GPOUT1_DIV_BITS   _u(0xffffffff)
214 #define CLOCKS_CLK_GPOUT1_DIV_RESET  _u(0x00000100)
215 // -----------------------------------------------------------------------------
216 // Field       : CLOCKS_CLK_GPOUT1_DIV_INT
217 // Description : Integer component of the divisor, 0 -> divide by 2^16
218 #define CLOCKS_CLK_GPOUT1_DIV_INT_RESET  _u(0x000001)
219 #define CLOCKS_CLK_GPOUT1_DIV_INT_BITS   _u(0xffffff00)
220 #define CLOCKS_CLK_GPOUT1_DIV_INT_MSB    _u(31)
221 #define CLOCKS_CLK_GPOUT1_DIV_INT_LSB    _u(8)
222 #define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW"
223 // -----------------------------------------------------------------------------
224 // Field       : CLOCKS_CLK_GPOUT1_DIV_FRAC
225 // Description : Fractional component of the divisor
226 #define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET  _u(0x00)
227 #define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS   _u(0x000000ff)
228 #define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB    _u(7)
229 #define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB    _u(0)
230 #define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW"
231 // =============================================================================
232 // Register    : CLOCKS_CLK_GPOUT1_SELECTED
233 // Description : Indicates which SRC is currently selected by the glitchless mux
234 //               (one-hot).
235 //               This slice does not have a glitchless mux (only the AUX_SRC
236 //               field is present, not SRC) so this register is hardwired to
237 //               0x1.
238 #define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014)
239 #define CLOCKS_CLK_GPOUT1_SELECTED_BITS   _u(0xffffffff)
240 #define CLOCKS_CLK_GPOUT1_SELECTED_RESET  _u(0x00000001)
241 #define CLOCKS_CLK_GPOUT1_SELECTED_MSB    _u(31)
242 #define CLOCKS_CLK_GPOUT1_SELECTED_LSB    _u(0)
243 #define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO"
244 // =============================================================================
245 // Register    : CLOCKS_CLK_GPOUT2_CTRL
246 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
247 #define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018)
248 #define CLOCKS_CLK_GPOUT2_CTRL_BITS   _u(0x00131de0)
249 #define CLOCKS_CLK_GPOUT2_CTRL_RESET  _u(0x00000000)
250 // -----------------------------------------------------------------------------
251 // Field       : CLOCKS_CLK_GPOUT2_CTRL_NUDGE
252 // Description : An edge on this signal shifts the phase of the output by 1
253 //               cycle of the input clock
254 //               This can be done at any time
255 #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET  _u(0x0)
256 #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS   _u(0x00100000)
257 #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB    _u(20)
258 #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB    _u(20)
259 #define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW"
260 // -----------------------------------------------------------------------------
261 // Field       : CLOCKS_CLK_GPOUT2_CTRL_PHASE
262 // Description : This delays the enable signal by up to 3 cycles of the input
263 //               clock
264 //               This must be set before the clock is enabled to have any effect
265 #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET  _u(0x0)
266 #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS   _u(0x00030000)
267 #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB    _u(17)
268 #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB    _u(16)
269 #define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW"
270 // -----------------------------------------------------------------------------
271 // Field       : CLOCKS_CLK_GPOUT2_CTRL_DC50
272 // Description : Enables duty cycle correction for odd divisors
273 #define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET  _u(0x0)
274 #define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS   _u(0x00001000)
275 #define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB    _u(12)
276 #define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB    _u(12)
277 #define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW"
278 // -----------------------------------------------------------------------------
279 // Field       : CLOCKS_CLK_GPOUT2_CTRL_ENABLE
280 // Description : Starts and stops the clock generator cleanly
281 #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET  _u(0x0)
282 #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS   _u(0x00000800)
283 #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB    _u(11)
284 #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB    _u(11)
285 #define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW"
286 // -----------------------------------------------------------------------------
287 // Field       : CLOCKS_CLK_GPOUT2_CTRL_KILL
288 // Description : Asynchronously kills the clock generator
289 #define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET  _u(0x0)
290 #define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS   _u(0x00000400)
291 #define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB    _u(10)
292 #define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB    _u(10)
293 #define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW"
294 // -----------------------------------------------------------------------------
295 // Field       : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC
296 // Description : Selects the auxiliary clock source, will glitch when switching
297 //               0x0 -> clksrc_pll_sys
298 //               0x1 -> clksrc_gpin0
299 //               0x2 -> clksrc_gpin1
300 //               0x3 -> clksrc_pll_usb
301 //               0x4 -> rosc_clksrc_ph
302 //               0x5 -> xosc_clksrc
303 //               0x6 -> clk_sys
304 //               0x7 -> clk_usb
305 //               0x8 -> clk_adc
306 //               0x9 -> clk_rtc
307 //               0xa -> clk_ref
308 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET                _u(0x0)
309 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS                 _u(0x000001e0)
310 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB                  _u(8)
311 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB                  _u(5)
312 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS               "RW"
313 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
314 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
315 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
316 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
317 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
318 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
319 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
320 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
321 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
322 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
323 #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
324 // =============================================================================
325 // Register    : CLOCKS_CLK_GPOUT2_DIV
326 // Description : Clock divisor, can be changed on-the-fly
327 #define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c)
328 #define CLOCKS_CLK_GPOUT2_DIV_BITS   _u(0xffffffff)
329 #define CLOCKS_CLK_GPOUT2_DIV_RESET  _u(0x00000100)
330 // -----------------------------------------------------------------------------
331 // Field       : CLOCKS_CLK_GPOUT2_DIV_INT
332 // Description : Integer component of the divisor, 0 -> divide by 2^16
333 #define CLOCKS_CLK_GPOUT2_DIV_INT_RESET  _u(0x000001)
334 #define CLOCKS_CLK_GPOUT2_DIV_INT_BITS   _u(0xffffff00)
335 #define CLOCKS_CLK_GPOUT2_DIV_INT_MSB    _u(31)
336 #define CLOCKS_CLK_GPOUT2_DIV_INT_LSB    _u(8)
337 #define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW"
338 // -----------------------------------------------------------------------------
339 // Field       : CLOCKS_CLK_GPOUT2_DIV_FRAC
340 // Description : Fractional component of the divisor
341 #define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET  _u(0x00)
342 #define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS   _u(0x000000ff)
343 #define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB    _u(7)
344 #define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB    _u(0)
345 #define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW"
346 // =============================================================================
347 // Register    : CLOCKS_CLK_GPOUT2_SELECTED
348 // Description : Indicates which SRC is currently selected by the glitchless mux
349 //               (one-hot).
350 //               This slice does not have a glitchless mux (only the AUX_SRC
351 //               field is present, not SRC) so this register is hardwired to
352 //               0x1.
353 #define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020)
354 #define CLOCKS_CLK_GPOUT2_SELECTED_BITS   _u(0xffffffff)
355 #define CLOCKS_CLK_GPOUT2_SELECTED_RESET  _u(0x00000001)
356 #define CLOCKS_CLK_GPOUT2_SELECTED_MSB    _u(31)
357 #define CLOCKS_CLK_GPOUT2_SELECTED_LSB    _u(0)
358 #define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO"
359 // =============================================================================
360 // Register    : CLOCKS_CLK_GPOUT3_CTRL
361 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
362 #define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024)
363 #define CLOCKS_CLK_GPOUT3_CTRL_BITS   _u(0x00131de0)
364 #define CLOCKS_CLK_GPOUT3_CTRL_RESET  _u(0x00000000)
365 // -----------------------------------------------------------------------------
366 // Field       : CLOCKS_CLK_GPOUT3_CTRL_NUDGE
367 // Description : An edge on this signal shifts the phase of the output by 1
368 //               cycle of the input clock
369 //               This can be done at any time
370 #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET  _u(0x0)
371 #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS   _u(0x00100000)
372 #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB    _u(20)
373 #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB    _u(20)
374 #define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW"
375 // -----------------------------------------------------------------------------
376 // Field       : CLOCKS_CLK_GPOUT3_CTRL_PHASE
377 // Description : This delays the enable signal by up to 3 cycles of the input
378 //               clock
379 //               This must be set before the clock is enabled to have any effect
380 #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET  _u(0x0)
381 #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS   _u(0x00030000)
382 #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB    _u(17)
383 #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB    _u(16)
384 #define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW"
385 // -----------------------------------------------------------------------------
386 // Field       : CLOCKS_CLK_GPOUT3_CTRL_DC50
387 // Description : Enables duty cycle correction for odd divisors
388 #define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET  _u(0x0)
389 #define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS   _u(0x00001000)
390 #define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB    _u(12)
391 #define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB    _u(12)
392 #define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW"
393 // -----------------------------------------------------------------------------
394 // Field       : CLOCKS_CLK_GPOUT3_CTRL_ENABLE
395 // Description : Starts and stops the clock generator cleanly
396 #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET  _u(0x0)
397 #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS   _u(0x00000800)
398 #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB    _u(11)
399 #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB    _u(11)
400 #define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW"
401 // -----------------------------------------------------------------------------
402 // Field       : CLOCKS_CLK_GPOUT3_CTRL_KILL
403 // Description : Asynchronously kills the clock generator
404 #define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET  _u(0x0)
405 #define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS   _u(0x00000400)
406 #define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB    _u(10)
407 #define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB    _u(10)
408 #define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW"
409 // -----------------------------------------------------------------------------
410 // Field       : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC
411 // Description : Selects the auxiliary clock source, will glitch when switching
412 //               0x0 -> clksrc_pll_sys
413 //               0x1 -> clksrc_gpin0
414 //               0x2 -> clksrc_gpin1
415 //               0x3 -> clksrc_pll_usb
416 //               0x4 -> rosc_clksrc_ph
417 //               0x5 -> xosc_clksrc
418 //               0x6 -> clk_sys
419 //               0x7 -> clk_usb
420 //               0x8 -> clk_adc
421 //               0x9 -> clk_rtc
422 //               0xa -> clk_ref
423 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET                _u(0x0)
424 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS                 _u(0x000001e0)
425 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB                  _u(8)
426 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB                  _u(5)
427 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS               "RW"
428 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
429 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
430 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
431 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
432 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
433 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x5)
434 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x6)
435 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB        _u(0x7)
436 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC        _u(0x8)
437 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC        _u(0x9)
438 #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF        _u(0xa)
439 // =============================================================================
440 // Register    : CLOCKS_CLK_GPOUT3_DIV
441 // Description : Clock divisor, can be changed on-the-fly
442 #define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028)
443 #define CLOCKS_CLK_GPOUT3_DIV_BITS   _u(0xffffffff)
444 #define CLOCKS_CLK_GPOUT3_DIV_RESET  _u(0x00000100)
445 // -----------------------------------------------------------------------------
446 // Field       : CLOCKS_CLK_GPOUT3_DIV_INT
447 // Description : Integer component of the divisor, 0 -> divide by 2^16
448 #define CLOCKS_CLK_GPOUT3_DIV_INT_RESET  _u(0x000001)
449 #define CLOCKS_CLK_GPOUT3_DIV_INT_BITS   _u(0xffffff00)
450 #define CLOCKS_CLK_GPOUT3_DIV_INT_MSB    _u(31)
451 #define CLOCKS_CLK_GPOUT3_DIV_INT_LSB    _u(8)
452 #define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW"
453 // -----------------------------------------------------------------------------
454 // Field       : CLOCKS_CLK_GPOUT3_DIV_FRAC
455 // Description : Fractional component of the divisor
456 #define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET  _u(0x00)
457 #define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS   _u(0x000000ff)
458 #define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB    _u(7)
459 #define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB    _u(0)
460 #define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW"
461 // =============================================================================
462 // Register    : CLOCKS_CLK_GPOUT3_SELECTED
463 // Description : Indicates which SRC is currently selected by the glitchless mux
464 //               (one-hot).
465 //               This slice does not have a glitchless mux (only the AUX_SRC
466 //               field is present, not SRC) so this register is hardwired to
467 //               0x1.
468 #define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c)
469 #define CLOCKS_CLK_GPOUT3_SELECTED_BITS   _u(0xffffffff)
470 #define CLOCKS_CLK_GPOUT3_SELECTED_RESET  _u(0x00000001)
471 #define CLOCKS_CLK_GPOUT3_SELECTED_MSB    _u(31)
472 #define CLOCKS_CLK_GPOUT3_SELECTED_LSB    _u(0)
473 #define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO"
474 // =============================================================================
475 // Register    : CLOCKS_CLK_REF_CTRL
476 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
477 #define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030)
478 #define CLOCKS_CLK_REF_CTRL_BITS   _u(0x00000063)
479 #define CLOCKS_CLK_REF_CTRL_RESET  _u(0x00000000)
480 // -----------------------------------------------------------------------------
481 // Field       : CLOCKS_CLK_REF_CTRL_AUXSRC
482 // Description : Selects the auxiliary clock source, will glitch when switching
483 //               0x0 -> clksrc_pll_usb
484 //               0x1 -> clksrc_gpin0
485 //               0x2 -> clksrc_gpin1
486 #define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET                _u(0x0)
487 #define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS                 _u(0x00000060)
488 #define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB                  _u(6)
489 #define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB                  _u(5)
490 #define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS               "RW"
491 #define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
492 #define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x1)
493 #define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x2)
494 // -----------------------------------------------------------------------------
495 // Field       : CLOCKS_CLK_REF_CTRL_SRC
496 // Description : Selects the clock source glitchlessly, can be changed
497 //               on-the-fly
498 //               0x0 -> rosc_clksrc_ph
499 //               0x1 -> clksrc_clk_ref_aux
500 //               0x2 -> xosc_clksrc
501 #define CLOCKS_CLK_REF_CTRL_SRC_RESET                    "-"
502 #define CLOCKS_CLK_REF_CTRL_SRC_BITS                     _u(0x00000003)
503 #define CLOCKS_CLK_REF_CTRL_SRC_MSB                      _u(1)
504 #define CLOCKS_CLK_REF_CTRL_SRC_LSB                      _u(0)
505 #define CLOCKS_CLK_REF_CTRL_SRC_ACCESS                   "RW"
506 #define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH     _u(0x0)
507 #define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1)
508 #define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC        _u(0x2)
509 // =============================================================================
510 // Register    : CLOCKS_CLK_REF_DIV
511 // Description : Clock divisor, can be changed on-the-fly
512 #define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034)
513 #define CLOCKS_CLK_REF_DIV_BITS   _u(0x00000300)
514 #define CLOCKS_CLK_REF_DIV_RESET  _u(0x00000100)
515 // -----------------------------------------------------------------------------
516 // Field       : CLOCKS_CLK_REF_DIV_INT
517 // Description : Integer component of the divisor, 0 -> divide by 2^16
518 #define CLOCKS_CLK_REF_DIV_INT_RESET  _u(0x1)
519 #define CLOCKS_CLK_REF_DIV_INT_BITS   _u(0x00000300)
520 #define CLOCKS_CLK_REF_DIV_INT_MSB    _u(9)
521 #define CLOCKS_CLK_REF_DIV_INT_LSB    _u(8)
522 #define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW"
523 // =============================================================================
524 // Register    : CLOCKS_CLK_REF_SELECTED
525 // Description : Indicates which SRC is currently selected by the glitchless mux
526 //               (one-hot).
527 //               The glitchless multiplexer does not switch instantaneously (to
528 //               avoid glitches), so software should poll this register to wait
529 //               for the switch to complete. This register contains one decoded
530 //               bit for each of the clock sources enumerated in the CTRL SRC
531 //               field. At most one of these bits will be set at any time,
532 //               indicating that clock is currently present at the output of the
533 //               glitchless mux. Whilst switching is in progress, this register
534 //               may briefly show all-0s.
535 #define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038)
536 #define CLOCKS_CLK_REF_SELECTED_BITS   _u(0xffffffff)
537 #define CLOCKS_CLK_REF_SELECTED_RESET  _u(0x00000001)
538 #define CLOCKS_CLK_REF_SELECTED_MSB    _u(31)
539 #define CLOCKS_CLK_REF_SELECTED_LSB    _u(0)
540 #define CLOCKS_CLK_REF_SELECTED_ACCESS "RO"
541 // =============================================================================
542 // Register    : CLOCKS_CLK_SYS_CTRL
543 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
544 #define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c)
545 #define CLOCKS_CLK_SYS_CTRL_BITS   _u(0x000000e1)
546 #define CLOCKS_CLK_SYS_CTRL_RESET  _u(0x00000000)
547 // -----------------------------------------------------------------------------
548 // Field       : CLOCKS_CLK_SYS_CTRL_AUXSRC
549 // Description : Selects the auxiliary clock source, will glitch when switching
550 //               0x0 -> clksrc_pll_sys
551 //               0x1 -> clksrc_pll_usb
552 //               0x2 -> rosc_clksrc
553 //               0x3 -> xosc_clksrc
554 //               0x4 -> clksrc_gpin0
555 //               0x5 -> clksrc_gpin1
556 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET                _u(0x0)
557 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS                 _u(0x000000e0)
558 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB                  _u(7)
559 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB                  _u(5)
560 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS               "RW"
561 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
562 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1)
563 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC    _u(0x2)
564 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
565 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
566 #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
567 // -----------------------------------------------------------------------------
568 // Field       : CLOCKS_CLK_SYS_CTRL_SRC
569 // Description : Selects the clock source glitchlessly, can be changed
570 //               on-the-fly
571 //               0x0 -> clk_ref
572 //               0x1 -> clksrc_clk_sys_aux
573 #define CLOCKS_CLK_SYS_CTRL_SRC_RESET                    _u(0x0)
574 #define CLOCKS_CLK_SYS_CTRL_SRC_BITS                     _u(0x00000001)
575 #define CLOCKS_CLK_SYS_CTRL_SRC_MSB                      _u(0)
576 #define CLOCKS_CLK_SYS_CTRL_SRC_LSB                      _u(0)
577 #define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS                   "RW"
578 #define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF            _u(0x0)
579 #define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1)
580 // =============================================================================
581 // Register    : CLOCKS_CLK_SYS_DIV
582 // Description : Clock divisor, can be changed on-the-fly
583 #define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040)
584 #define CLOCKS_CLK_SYS_DIV_BITS   _u(0xffffffff)
585 #define CLOCKS_CLK_SYS_DIV_RESET  _u(0x00000100)
586 // -----------------------------------------------------------------------------
587 // Field       : CLOCKS_CLK_SYS_DIV_INT
588 // Description : Integer component of the divisor, 0 -> divide by 2^16
589 #define CLOCKS_CLK_SYS_DIV_INT_RESET  _u(0x000001)
590 #define CLOCKS_CLK_SYS_DIV_INT_BITS   _u(0xffffff00)
591 #define CLOCKS_CLK_SYS_DIV_INT_MSB    _u(31)
592 #define CLOCKS_CLK_SYS_DIV_INT_LSB    _u(8)
593 #define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW"
594 // -----------------------------------------------------------------------------
595 // Field       : CLOCKS_CLK_SYS_DIV_FRAC
596 // Description : Fractional component of the divisor
597 #define CLOCKS_CLK_SYS_DIV_FRAC_RESET  _u(0x00)
598 #define CLOCKS_CLK_SYS_DIV_FRAC_BITS   _u(0x000000ff)
599 #define CLOCKS_CLK_SYS_DIV_FRAC_MSB    _u(7)
600 #define CLOCKS_CLK_SYS_DIV_FRAC_LSB    _u(0)
601 #define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW"
602 // =============================================================================
603 // Register    : CLOCKS_CLK_SYS_SELECTED
604 // Description : Indicates which SRC is currently selected by the glitchless mux
605 //               (one-hot).
606 //               The glitchless multiplexer does not switch instantaneously (to
607 //               avoid glitches), so software should poll this register to wait
608 //               for the switch to complete. This register contains one decoded
609 //               bit for each of the clock sources enumerated in the CTRL SRC
610 //               field. At most one of these bits will be set at any time,
611 //               indicating that clock is currently present at the output of the
612 //               glitchless mux. Whilst switching is in progress, this register
613 //               may briefly show all-0s.
614 #define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044)
615 #define CLOCKS_CLK_SYS_SELECTED_BITS   _u(0xffffffff)
616 #define CLOCKS_CLK_SYS_SELECTED_RESET  _u(0x00000001)
617 #define CLOCKS_CLK_SYS_SELECTED_MSB    _u(31)
618 #define CLOCKS_CLK_SYS_SELECTED_LSB    _u(0)
619 #define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO"
620 // =============================================================================
621 // Register    : CLOCKS_CLK_PERI_CTRL
622 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
623 #define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048)
624 #define CLOCKS_CLK_PERI_CTRL_BITS   _u(0x00000ce0)
625 #define CLOCKS_CLK_PERI_CTRL_RESET  _u(0x00000000)
626 // -----------------------------------------------------------------------------
627 // Field       : CLOCKS_CLK_PERI_CTRL_ENABLE
628 // Description : Starts and stops the clock generator cleanly
629 #define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET  _u(0x0)
630 #define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS   _u(0x00000800)
631 #define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB    _u(11)
632 #define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB    _u(11)
633 #define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW"
634 // -----------------------------------------------------------------------------
635 // Field       : CLOCKS_CLK_PERI_CTRL_KILL
636 // Description : Asynchronously kills the clock generator
637 #define CLOCKS_CLK_PERI_CTRL_KILL_RESET  _u(0x0)
638 #define CLOCKS_CLK_PERI_CTRL_KILL_BITS   _u(0x00000400)
639 #define CLOCKS_CLK_PERI_CTRL_KILL_MSB    _u(10)
640 #define CLOCKS_CLK_PERI_CTRL_KILL_LSB    _u(10)
641 #define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW"
642 // -----------------------------------------------------------------------------
643 // Field       : CLOCKS_CLK_PERI_CTRL_AUXSRC
644 // Description : Selects the auxiliary clock source, will glitch when switching
645 //               0x0 -> clk_sys
646 //               0x1 -> clksrc_pll_sys
647 //               0x2 -> clksrc_pll_usb
648 //               0x3 -> rosc_clksrc_ph
649 //               0x4 -> xosc_clksrc
650 //               0x5 -> clksrc_gpin0
651 //               0x6 -> clksrc_gpin1
652 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET                _u(0x0)
653 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS                 _u(0x000000e0)
654 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB                  _u(7)
655 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB                  _u(5)
656 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS               "RW"
657 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS        _u(0x0)
658 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
659 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2)
660 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3)
661 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x4)
662 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x5)
663 #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x6)
664 // =============================================================================
665 // Register    : CLOCKS_CLK_PERI_SELECTED
666 // Description : Indicates which SRC is currently selected by the glitchless mux
667 //               (one-hot).
668 //               This slice does not have a glitchless mux (only the AUX_SRC
669 //               field is present, not SRC) so this register is hardwired to
670 //               0x1.
671 #define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050)
672 #define CLOCKS_CLK_PERI_SELECTED_BITS   _u(0xffffffff)
673 #define CLOCKS_CLK_PERI_SELECTED_RESET  _u(0x00000001)
674 #define CLOCKS_CLK_PERI_SELECTED_MSB    _u(31)
675 #define CLOCKS_CLK_PERI_SELECTED_LSB    _u(0)
676 #define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO"
677 // =============================================================================
678 // Register    : CLOCKS_CLK_USB_CTRL
679 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
680 #define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054)
681 #define CLOCKS_CLK_USB_CTRL_BITS   _u(0x00130ce0)
682 #define CLOCKS_CLK_USB_CTRL_RESET  _u(0x00000000)
683 // -----------------------------------------------------------------------------
684 // Field       : CLOCKS_CLK_USB_CTRL_NUDGE
685 // Description : An edge on this signal shifts the phase of the output by 1
686 //               cycle of the input clock
687 //               This can be done at any time
688 #define CLOCKS_CLK_USB_CTRL_NUDGE_RESET  _u(0x0)
689 #define CLOCKS_CLK_USB_CTRL_NUDGE_BITS   _u(0x00100000)
690 #define CLOCKS_CLK_USB_CTRL_NUDGE_MSB    _u(20)
691 #define CLOCKS_CLK_USB_CTRL_NUDGE_LSB    _u(20)
692 #define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW"
693 // -----------------------------------------------------------------------------
694 // Field       : CLOCKS_CLK_USB_CTRL_PHASE
695 // Description : This delays the enable signal by up to 3 cycles of the input
696 //               clock
697 //               This must be set before the clock is enabled to have any effect
698 #define CLOCKS_CLK_USB_CTRL_PHASE_RESET  _u(0x0)
699 #define CLOCKS_CLK_USB_CTRL_PHASE_BITS   _u(0x00030000)
700 #define CLOCKS_CLK_USB_CTRL_PHASE_MSB    _u(17)
701 #define CLOCKS_CLK_USB_CTRL_PHASE_LSB    _u(16)
702 #define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW"
703 // -----------------------------------------------------------------------------
704 // Field       : CLOCKS_CLK_USB_CTRL_ENABLE
705 // Description : Starts and stops the clock generator cleanly
706 #define CLOCKS_CLK_USB_CTRL_ENABLE_RESET  _u(0x0)
707 #define CLOCKS_CLK_USB_CTRL_ENABLE_BITS   _u(0x00000800)
708 #define CLOCKS_CLK_USB_CTRL_ENABLE_MSB    _u(11)
709 #define CLOCKS_CLK_USB_CTRL_ENABLE_LSB    _u(11)
710 #define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW"
711 // -----------------------------------------------------------------------------
712 // Field       : CLOCKS_CLK_USB_CTRL_KILL
713 // Description : Asynchronously kills the clock generator
714 #define CLOCKS_CLK_USB_CTRL_KILL_RESET  _u(0x0)
715 #define CLOCKS_CLK_USB_CTRL_KILL_BITS   _u(0x00000400)
716 #define CLOCKS_CLK_USB_CTRL_KILL_MSB    _u(10)
717 #define CLOCKS_CLK_USB_CTRL_KILL_LSB    _u(10)
718 #define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW"
719 // -----------------------------------------------------------------------------
720 // Field       : CLOCKS_CLK_USB_CTRL_AUXSRC
721 // Description : Selects the auxiliary clock source, will glitch when switching
722 //               0x0 -> clksrc_pll_usb
723 //               0x1 -> clksrc_pll_sys
724 //               0x2 -> rosc_clksrc_ph
725 //               0x3 -> xosc_clksrc
726 //               0x4 -> clksrc_gpin0
727 //               0x5 -> clksrc_gpin1
728 #define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET                _u(0x0)
729 #define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS                 _u(0x000000e0)
730 #define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB                  _u(7)
731 #define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB                  _u(5)
732 #define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS               "RW"
733 #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
734 #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
735 #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
736 #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
737 #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
738 #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
739 // =============================================================================
740 // Register    : CLOCKS_CLK_USB_DIV
741 // Description : Clock divisor, can be changed on-the-fly
742 #define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058)
743 #define CLOCKS_CLK_USB_DIV_BITS   _u(0x00000300)
744 #define CLOCKS_CLK_USB_DIV_RESET  _u(0x00000100)
745 // -----------------------------------------------------------------------------
746 // Field       : CLOCKS_CLK_USB_DIV_INT
747 // Description : Integer component of the divisor, 0 -> divide by 2^16
748 #define CLOCKS_CLK_USB_DIV_INT_RESET  _u(0x1)
749 #define CLOCKS_CLK_USB_DIV_INT_BITS   _u(0x00000300)
750 #define CLOCKS_CLK_USB_DIV_INT_MSB    _u(9)
751 #define CLOCKS_CLK_USB_DIV_INT_LSB    _u(8)
752 #define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW"
753 // =============================================================================
754 // Register    : CLOCKS_CLK_USB_SELECTED
755 // Description : Indicates which SRC is currently selected by the glitchless mux
756 //               (one-hot).
757 //               This slice does not have a glitchless mux (only the AUX_SRC
758 //               field is present, not SRC) so this register is hardwired to
759 //               0x1.
760 #define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c)
761 #define CLOCKS_CLK_USB_SELECTED_BITS   _u(0xffffffff)
762 #define CLOCKS_CLK_USB_SELECTED_RESET  _u(0x00000001)
763 #define CLOCKS_CLK_USB_SELECTED_MSB    _u(31)
764 #define CLOCKS_CLK_USB_SELECTED_LSB    _u(0)
765 #define CLOCKS_CLK_USB_SELECTED_ACCESS "RO"
766 // =============================================================================
767 // Register    : CLOCKS_CLK_ADC_CTRL
768 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
769 #define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060)
770 #define CLOCKS_CLK_ADC_CTRL_BITS   _u(0x00130ce0)
771 #define CLOCKS_CLK_ADC_CTRL_RESET  _u(0x00000000)
772 // -----------------------------------------------------------------------------
773 // Field       : CLOCKS_CLK_ADC_CTRL_NUDGE
774 // Description : An edge on this signal shifts the phase of the output by 1
775 //               cycle of the input clock
776 //               This can be done at any time
777 #define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET  _u(0x0)
778 #define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS   _u(0x00100000)
779 #define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB    _u(20)
780 #define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB    _u(20)
781 #define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW"
782 // -----------------------------------------------------------------------------
783 // Field       : CLOCKS_CLK_ADC_CTRL_PHASE
784 // Description : This delays the enable signal by up to 3 cycles of the input
785 //               clock
786 //               This must be set before the clock is enabled to have any effect
787 #define CLOCKS_CLK_ADC_CTRL_PHASE_RESET  _u(0x0)
788 #define CLOCKS_CLK_ADC_CTRL_PHASE_BITS   _u(0x00030000)
789 #define CLOCKS_CLK_ADC_CTRL_PHASE_MSB    _u(17)
790 #define CLOCKS_CLK_ADC_CTRL_PHASE_LSB    _u(16)
791 #define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW"
792 // -----------------------------------------------------------------------------
793 // Field       : CLOCKS_CLK_ADC_CTRL_ENABLE
794 // Description : Starts and stops the clock generator cleanly
795 #define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET  _u(0x0)
796 #define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS   _u(0x00000800)
797 #define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB    _u(11)
798 #define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB    _u(11)
799 #define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW"
800 // -----------------------------------------------------------------------------
801 // Field       : CLOCKS_CLK_ADC_CTRL_KILL
802 // Description : Asynchronously kills the clock generator
803 #define CLOCKS_CLK_ADC_CTRL_KILL_RESET  _u(0x0)
804 #define CLOCKS_CLK_ADC_CTRL_KILL_BITS   _u(0x00000400)
805 #define CLOCKS_CLK_ADC_CTRL_KILL_MSB    _u(10)
806 #define CLOCKS_CLK_ADC_CTRL_KILL_LSB    _u(10)
807 #define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW"
808 // -----------------------------------------------------------------------------
809 // Field       : CLOCKS_CLK_ADC_CTRL_AUXSRC
810 // Description : Selects the auxiliary clock source, will glitch when switching
811 //               0x0 -> clksrc_pll_usb
812 //               0x1 -> clksrc_pll_sys
813 //               0x2 -> rosc_clksrc_ph
814 //               0x3 -> xosc_clksrc
815 //               0x4 -> clksrc_gpin0
816 //               0x5 -> clksrc_gpin1
817 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET                _u(0x0)
818 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS                 _u(0x000000e0)
819 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB                  _u(7)
820 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB                  _u(5)
821 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS               "RW"
822 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
823 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
824 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
825 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
826 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
827 #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
828 // =============================================================================
829 // Register    : CLOCKS_CLK_ADC_DIV
830 // Description : Clock divisor, can be changed on-the-fly
831 #define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064)
832 #define CLOCKS_CLK_ADC_DIV_BITS   _u(0x00000300)
833 #define CLOCKS_CLK_ADC_DIV_RESET  _u(0x00000100)
834 // -----------------------------------------------------------------------------
835 // Field       : CLOCKS_CLK_ADC_DIV_INT
836 // Description : Integer component of the divisor, 0 -> divide by 2^16
837 #define CLOCKS_CLK_ADC_DIV_INT_RESET  _u(0x1)
838 #define CLOCKS_CLK_ADC_DIV_INT_BITS   _u(0x00000300)
839 #define CLOCKS_CLK_ADC_DIV_INT_MSB    _u(9)
840 #define CLOCKS_CLK_ADC_DIV_INT_LSB    _u(8)
841 #define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW"
842 // =============================================================================
843 // Register    : CLOCKS_CLK_ADC_SELECTED
844 // Description : Indicates which SRC is currently selected by the glitchless mux
845 //               (one-hot).
846 //               This slice does not have a glitchless mux (only the AUX_SRC
847 //               field is present, not SRC) so this register is hardwired to
848 //               0x1.
849 #define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068)
850 #define CLOCKS_CLK_ADC_SELECTED_BITS   _u(0xffffffff)
851 #define CLOCKS_CLK_ADC_SELECTED_RESET  _u(0x00000001)
852 #define CLOCKS_CLK_ADC_SELECTED_MSB    _u(31)
853 #define CLOCKS_CLK_ADC_SELECTED_LSB    _u(0)
854 #define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO"
855 // =============================================================================
856 // Register    : CLOCKS_CLK_RTC_CTRL
857 // Description : Clock control, can be changed on-the-fly (except for auxsrc)
858 #define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c)
859 #define CLOCKS_CLK_RTC_CTRL_BITS   _u(0x00130ce0)
860 #define CLOCKS_CLK_RTC_CTRL_RESET  _u(0x00000000)
861 // -----------------------------------------------------------------------------
862 // Field       : CLOCKS_CLK_RTC_CTRL_NUDGE
863 // Description : An edge on this signal shifts the phase of the output by 1
864 //               cycle of the input clock
865 //               This can be done at any time
866 #define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET  _u(0x0)
867 #define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS   _u(0x00100000)
868 #define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB    _u(20)
869 #define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB    _u(20)
870 #define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW"
871 // -----------------------------------------------------------------------------
872 // Field       : CLOCKS_CLK_RTC_CTRL_PHASE
873 // Description : This delays the enable signal by up to 3 cycles of the input
874 //               clock
875 //               This must be set before the clock is enabled to have any effect
876 #define CLOCKS_CLK_RTC_CTRL_PHASE_RESET  _u(0x0)
877 #define CLOCKS_CLK_RTC_CTRL_PHASE_BITS   _u(0x00030000)
878 #define CLOCKS_CLK_RTC_CTRL_PHASE_MSB    _u(17)
879 #define CLOCKS_CLK_RTC_CTRL_PHASE_LSB    _u(16)
880 #define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW"
881 // -----------------------------------------------------------------------------
882 // Field       : CLOCKS_CLK_RTC_CTRL_ENABLE
883 // Description : Starts and stops the clock generator cleanly
884 #define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET  _u(0x0)
885 #define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS   _u(0x00000800)
886 #define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB    _u(11)
887 #define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB    _u(11)
888 #define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW"
889 // -----------------------------------------------------------------------------
890 // Field       : CLOCKS_CLK_RTC_CTRL_KILL
891 // Description : Asynchronously kills the clock generator
892 #define CLOCKS_CLK_RTC_CTRL_KILL_RESET  _u(0x0)
893 #define CLOCKS_CLK_RTC_CTRL_KILL_BITS   _u(0x00000400)
894 #define CLOCKS_CLK_RTC_CTRL_KILL_MSB    _u(10)
895 #define CLOCKS_CLK_RTC_CTRL_KILL_LSB    _u(10)
896 #define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW"
897 // -----------------------------------------------------------------------------
898 // Field       : CLOCKS_CLK_RTC_CTRL_AUXSRC
899 // Description : Selects the auxiliary clock source, will glitch when switching
900 //               0x0 -> clksrc_pll_usb
901 //               0x1 -> clksrc_pll_sys
902 //               0x2 -> rosc_clksrc_ph
903 //               0x3 -> xosc_clksrc
904 //               0x4 -> clksrc_gpin0
905 //               0x5 -> clksrc_gpin1
906 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET                _u(0x0)
907 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS                 _u(0x000000e0)
908 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB                  _u(7)
909 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB                  _u(5)
910 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS               "RW"
911 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
912 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
913 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
914 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC    _u(0x3)
915 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0   _u(0x4)
916 #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1   _u(0x5)
917 // =============================================================================
918 // Register    : CLOCKS_CLK_RTC_DIV
919 // Description : Clock divisor, can be changed on-the-fly
920 #define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070)
921 #define CLOCKS_CLK_RTC_DIV_BITS   _u(0xffffffff)
922 #define CLOCKS_CLK_RTC_DIV_RESET  _u(0x00000100)
923 // -----------------------------------------------------------------------------
924 // Field       : CLOCKS_CLK_RTC_DIV_INT
925 // Description : Integer component of the divisor, 0 -> divide by 2^16
926 #define CLOCKS_CLK_RTC_DIV_INT_RESET  _u(0x000001)
927 #define CLOCKS_CLK_RTC_DIV_INT_BITS   _u(0xffffff00)
928 #define CLOCKS_CLK_RTC_DIV_INT_MSB    _u(31)
929 #define CLOCKS_CLK_RTC_DIV_INT_LSB    _u(8)
930 #define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW"
931 // -----------------------------------------------------------------------------
932 // Field       : CLOCKS_CLK_RTC_DIV_FRAC
933 // Description : Fractional component of the divisor
934 #define CLOCKS_CLK_RTC_DIV_FRAC_RESET  _u(0x00)
935 #define CLOCKS_CLK_RTC_DIV_FRAC_BITS   _u(0x000000ff)
936 #define CLOCKS_CLK_RTC_DIV_FRAC_MSB    _u(7)
937 #define CLOCKS_CLK_RTC_DIV_FRAC_LSB    _u(0)
938 #define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW"
939 // =============================================================================
940 // Register    : CLOCKS_CLK_RTC_SELECTED
941 // Description : Indicates which SRC is currently selected by the glitchless mux
942 //               (one-hot).
943 //               This slice does not have a glitchless mux (only the AUX_SRC
944 //               field is present, not SRC) so this register is hardwired to
945 //               0x1.
946 #define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074)
947 #define CLOCKS_CLK_RTC_SELECTED_BITS   _u(0xffffffff)
948 #define CLOCKS_CLK_RTC_SELECTED_RESET  _u(0x00000001)
949 #define CLOCKS_CLK_RTC_SELECTED_MSB    _u(31)
950 #define CLOCKS_CLK_RTC_SELECTED_LSB    _u(0)
951 #define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO"
952 // =============================================================================
953 // Register    : CLOCKS_CLK_SYS_RESUS_CTRL
954 // Description : None
955 #define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078)
956 #define CLOCKS_CLK_SYS_RESUS_CTRL_BITS   _u(0x000111ff)
957 #define CLOCKS_CLK_SYS_RESUS_CTRL_RESET  _u(0x000000ff)
958 // -----------------------------------------------------------------------------
959 // Field       : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR
960 // Description : For clearing the resus after the fault that triggered it has
961 //               been corrected
962 #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET  _u(0x0)
963 #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS   _u(0x00010000)
964 #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB    _u(16)
965 #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB    _u(16)
966 #define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW"
967 // -----------------------------------------------------------------------------
968 // Field       : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE
969 // Description : Force a resus, for test purposes only
970 #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET  _u(0x0)
971 #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS   _u(0x00001000)
972 #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB    _u(12)
973 #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB    _u(12)
974 #define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW"
975 // -----------------------------------------------------------------------------
976 // Field       : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE
977 // Description : Enable resus
978 #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET  _u(0x0)
979 #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS   _u(0x00000100)
980 #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB    _u(8)
981 #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB    _u(8)
982 #define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW"
983 // -----------------------------------------------------------------------------
984 // Field       : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT
985 // Description : This is expressed as a number of clk_ref cycles
986 //               and must be >= 2x clk_ref_freq/min_clk_tst_freq
987 #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET  _u(0xff)
988 #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS   _u(0x000000ff)
989 #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB    _u(7)
990 #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB    _u(0)
991 #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW"
992 // =============================================================================
993 // Register    : CLOCKS_CLK_SYS_RESUS_STATUS
994 // Description : None
995 #define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c)
996 #define CLOCKS_CLK_SYS_RESUS_STATUS_BITS   _u(0x00000001)
997 #define CLOCKS_CLK_SYS_RESUS_STATUS_RESET  _u(0x00000000)
998 // -----------------------------------------------------------------------------
999 // Field       : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED
1000 // Description : Clock has been resuscitated, correct the error then send
1001 //               ctrl_clear=1
1002 #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET  _u(0x0)
1003 #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS   _u(0x00000001)
1004 #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB    _u(0)
1005 #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB    _u(0)
1006 #define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO"
1007 // =============================================================================
1008 // Register    : CLOCKS_FC0_REF_KHZ
1009 // Description : Reference clock frequency in kHz
1010 #define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080)
1011 #define CLOCKS_FC0_REF_KHZ_BITS   _u(0x000fffff)
1012 #define CLOCKS_FC0_REF_KHZ_RESET  _u(0x00000000)
1013 #define CLOCKS_FC0_REF_KHZ_MSB    _u(19)
1014 #define CLOCKS_FC0_REF_KHZ_LSB    _u(0)
1015 #define CLOCKS_FC0_REF_KHZ_ACCESS "RW"
1016 // =============================================================================
1017 // Register    : CLOCKS_FC0_MIN_KHZ
1018 // Description : Minimum pass frequency in kHz. This is optional. Set to 0 if
1019 //               you are not using the pass/fail flags
1020 #define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084)
1021 #define CLOCKS_FC0_MIN_KHZ_BITS   _u(0x01ffffff)
1022 #define CLOCKS_FC0_MIN_KHZ_RESET  _u(0x00000000)
1023 #define CLOCKS_FC0_MIN_KHZ_MSB    _u(24)
1024 #define CLOCKS_FC0_MIN_KHZ_LSB    _u(0)
1025 #define CLOCKS_FC0_MIN_KHZ_ACCESS "RW"
1026 // =============================================================================
1027 // Register    : CLOCKS_FC0_MAX_KHZ
1028 // Description : Maximum pass frequency in kHz. This is optional. Set to
1029 //               0x1ffffff if you are not using the pass/fail flags
1030 #define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088)
1031 #define CLOCKS_FC0_MAX_KHZ_BITS   _u(0x01ffffff)
1032 #define CLOCKS_FC0_MAX_KHZ_RESET  _u(0x01ffffff)
1033 #define CLOCKS_FC0_MAX_KHZ_MSB    _u(24)
1034 #define CLOCKS_FC0_MAX_KHZ_LSB    _u(0)
1035 #define CLOCKS_FC0_MAX_KHZ_ACCESS "RW"
1036 // =============================================================================
1037 // Register    : CLOCKS_FC0_DELAY
1038 // Description : Delays the start of frequency counting to allow the mux to
1039 //               settle
1040 //               Delay is measured in multiples of the reference clock period
1041 #define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c)
1042 #define CLOCKS_FC0_DELAY_BITS   _u(0x00000007)
1043 #define CLOCKS_FC0_DELAY_RESET  _u(0x00000001)
1044 #define CLOCKS_FC0_DELAY_MSB    _u(2)
1045 #define CLOCKS_FC0_DELAY_LSB    _u(0)
1046 #define CLOCKS_FC0_DELAY_ACCESS "RW"
1047 // =============================================================================
1048 // Register    : CLOCKS_FC0_INTERVAL
1049 // Description : The test interval is 0.98us * 2**interval, but let's call it
1050 //               1us * 2**interval
1051 //               The default gives a test interval of 250us
1052 #define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090)
1053 #define CLOCKS_FC0_INTERVAL_BITS   _u(0x0000000f)
1054 #define CLOCKS_FC0_INTERVAL_RESET  _u(0x00000008)
1055 #define CLOCKS_FC0_INTERVAL_MSB    _u(3)
1056 #define CLOCKS_FC0_INTERVAL_LSB    _u(0)
1057 #define CLOCKS_FC0_INTERVAL_ACCESS "RW"
1058 // =============================================================================
1059 // Register    : CLOCKS_FC0_SRC
1060 // Description : Clock sent to frequency counter, set to 0 when not required
1061 //               Writing to this register initiates the frequency count
1062 //               0x00 -> NULL
1063 //               0x01 -> pll_sys_clksrc_primary
1064 //               0x02 -> pll_usb_clksrc_primary
1065 //               0x03 -> rosc_clksrc
1066 //               0x04 -> rosc_clksrc_ph
1067 //               0x05 -> xosc_clksrc
1068 //               0x06 -> clksrc_gpin0
1069 //               0x07 -> clksrc_gpin1
1070 //               0x08 -> clk_ref
1071 //               0x09 -> clk_sys
1072 //               0x0a -> clk_peri
1073 //               0x0b -> clk_usb
1074 //               0x0c -> clk_adc
1075 //               0x0d -> clk_rtc
1076 #define CLOCKS_FC0_SRC_OFFSET                       _u(0x00000094)
1077 #define CLOCKS_FC0_SRC_BITS                         _u(0x000000ff)
1078 #define CLOCKS_FC0_SRC_RESET                        _u(0x00000000)
1079 #define CLOCKS_FC0_SRC_MSB                          _u(7)
1080 #define CLOCKS_FC0_SRC_LSB                          _u(0)
1081 #define CLOCKS_FC0_SRC_ACCESS                       "RW"
1082 #define CLOCKS_FC0_SRC_VALUE_NULL                   _u(0x00)
1083 #define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01)
1084 #define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02)
1085 #define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC            _u(0x03)
1086 #define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH         _u(0x04)
1087 #define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC            _u(0x05)
1088 #define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0           _u(0x06)
1089 #define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1           _u(0x07)
1090 #define CLOCKS_FC0_SRC_VALUE_CLK_REF                _u(0x08)
1091 #define CLOCKS_FC0_SRC_VALUE_CLK_SYS                _u(0x09)
1092 #define CLOCKS_FC0_SRC_VALUE_CLK_PERI               _u(0x0a)
1093 #define CLOCKS_FC0_SRC_VALUE_CLK_USB                _u(0x0b)
1094 #define CLOCKS_FC0_SRC_VALUE_CLK_ADC                _u(0x0c)
1095 #define CLOCKS_FC0_SRC_VALUE_CLK_RTC                _u(0x0d)
1096 // =============================================================================
1097 // Register    : CLOCKS_FC0_STATUS
1098 // Description : Frequency counter status
1099 #define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098)
1100 #define CLOCKS_FC0_STATUS_BITS   _u(0x11111111)
1101 #define CLOCKS_FC0_STATUS_RESET  _u(0x00000000)
1102 // -----------------------------------------------------------------------------
1103 // Field       : CLOCKS_FC0_STATUS_DIED
1104 // Description : Test clock stopped during test
1105 #define CLOCKS_FC0_STATUS_DIED_RESET  _u(0x0)
1106 #define CLOCKS_FC0_STATUS_DIED_BITS   _u(0x10000000)
1107 #define CLOCKS_FC0_STATUS_DIED_MSB    _u(28)
1108 #define CLOCKS_FC0_STATUS_DIED_LSB    _u(28)
1109 #define CLOCKS_FC0_STATUS_DIED_ACCESS "RO"
1110 // -----------------------------------------------------------------------------
1111 // Field       : CLOCKS_FC0_STATUS_FAST
1112 // Description : Test clock faster than expected, only valid when status_done=1
1113 #define CLOCKS_FC0_STATUS_FAST_RESET  _u(0x0)
1114 #define CLOCKS_FC0_STATUS_FAST_BITS   _u(0x01000000)
1115 #define CLOCKS_FC0_STATUS_FAST_MSB    _u(24)
1116 #define CLOCKS_FC0_STATUS_FAST_LSB    _u(24)
1117 #define CLOCKS_FC0_STATUS_FAST_ACCESS "RO"
1118 // -----------------------------------------------------------------------------
1119 // Field       : CLOCKS_FC0_STATUS_SLOW
1120 // Description : Test clock slower than expected, only valid when status_done=1
1121 #define CLOCKS_FC0_STATUS_SLOW_RESET  _u(0x0)
1122 #define CLOCKS_FC0_STATUS_SLOW_BITS   _u(0x00100000)
1123 #define CLOCKS_FC0_STATUS_SLOW_MSB    _u(20)
1124 #define CLOCKS_FC0_STATUS_SLOW_LSB    _u(20)
1125 #define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO"
1126 // -----------------------------------------------------------------------------
1127 // Field       : CLOCKS_FC0_STATUS_FAIL
1128 // Description : Test failed
1129 #define CLOCKS_FC0_STATUS_FAIL_RESET  _u(0x0)
1130 #define CLOCKS_FC0_STATUS_FAIL_BITS   _u(0x00010000)
1131 #define CLOCKS_FC0_STATUS_FAIL_MSB    _u(16)
1132 #define CLOCKS_FC0_STATUS_FAIL_LSB    _u(16)
1133 #define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO"
1134 // -----------------------------------------------------------------------------
1135 // Field       : CLOCKS_FC0_STATUS_WAITING
1136 // Description : Waiting for test clock to start
1137 #define CLOCKS_FC0_STATUS_WAITING_RESET  _u(0x0)
1138 #define CLOCKS_FC0_STATUS_WAITING_BITS   _u(0x00001000)
1139 #define CLOCKS_FC0_STATUS_WAITING_MSB    _u(12)
1140 #define CLOCKS_FC0_STATUS_WAITING_LSB    _u(12)
1141 #define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO"
1142 // -----------------------------------------------------------------------------
1143 // Field       : CLOCKS_FC0_STATUS_RUNNING
1144 // Description : Test running
1145 #define CLOCKS_FC0_STATUS_RUNNING_RESET  _u(0x0)
1146 #define CLOCKS_FC0_STATUS_RUNNING_BITS   _u(0x00000100)
1147 #define CLOCKS_FC0_STATUS_RUNNING_MSB    _u(8)
1148 #define CLOCKS_FC0_STATUS_RUNNING_LSB    _u(8)
1149 #define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO"
1150 // -----------------------------------------------------------------------------
1151 // Field       : CLOCKS_FC0_STATUS_DONE
1152 // Description : Test complete
1153 #define CLOCKS_FC0_STATUS_DONE_RESET  _u(0x0)
1154 #define CLOCKS_FC0_STATUS_DONE_BITS   _u(0x00000010)
1155 #define CLOCKS_FC0_STATUS_DONE_MSB    _u(4)
1156 #define CLOCKS_FC0_STATUS_DONE_LSB    _u(4)
1157 #define CLOCKS_FC0_STATUS_DONE_ACCESS "RO"
1158 // -----------------------------------------------------------------------------
1159 // Field       : CLOCKS_FC0_STATUS_PASS
1160 // Description : Test passed
1161 #define CLOCKS_FC0_STATUS_PASS_RESET  _u(0x0)
1162 #define CLOCKS_FC0_STATUS_PASS_BITS   _u(0x00000001)
1163 #define CLOCKS_FC0_STATUS_PASS_MSB    _u(0)
1164 #define CLOCKS_FC0_STATUS_PASS_LSB    _u(0)
1165 #define CLOCKS_FC0_STATUS_PASS_ACCESS "RO"
1166 // =============================================================================
1167 // Register    : CLOCKS_FC0_RESULT
1168 // Description : Result of frequency measurement, only valid when status_done=1
1169 #define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c)
1170 #define CLOCKS_FC0_RESULT_BITS   _u(0x3fffffff)
1171 #define CLOCKS_FC0_RESULT_RESET  _u(0x00000000)
1172 // -----------------------------------------------------------------------------
1173 // Field       : CLOCKS_FC0_RESULT_KHZ
1174 // Description : None
1175 #define CLOCKS_FC0_RESULT_KHZ_RESET  _u(0x0000000)
1176 #define CLOCKS_FC0_RESULT_KHZ_BITS   _u(0x3fffffe0)
1177 #define CLOCKS_FC0_RESULT_KHZ_MSB    _u(29)
1178 #define CLOCKS_FC0_RESULT_KHZ_LSB    _u(5)
1179 #define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO"
1180 // -----------------------------------------------------------------------------
1181 // Field       : CLOCKS_FC0_RESULT_FRAC
1182 // Description : None
1183 #define CLOCKS_FC0_RESULT_FRAC_RESET  _u(0x00)
1184 #define CLOCKS_FC0_RESULT_FRAC_BITS   _u(0x0000001f)
1185 #define CLOCKS_FC0_RESULT_FRAC_MSB    _u(4)
1186 #define CLOCKS_FC0_RESULT_FRAC_LSB    _u(0)
1187 #define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO"
1188 // =============================================================================
1189 // Register    : CLOCKS_WAKE_EN0
1190 // Description : enable clock in wake mode
1191 #define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0)
1192 #define CLOCKS_WAKE_EN0_BITS   _u(0xffffffff)
1193 #define CLOCKS_WAKE_EN0_RESET  _u(0xffffffff)
1194 // -----------------------------------------------------------------------------
1195 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3
1196 // Description : None
1197 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET  _u(0x1)
1198 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS   _u(0x80000000)
1199 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB    _u(31)
1200 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB    _u(31)
1201 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW"
1202 // -----------------------------------------------------------------------------
1203 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2
1204 // Description : None
1205 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET  _u(0x1)
1206 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS   _u(0x40000000)
1207 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB    _u(30)
1208 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB    _u(30)
1209 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW"
1210 // -----------------------------------------------------------------------------
1211 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1
1212 // Description : None
1213 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET  _u(0x1)
1214 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS   _u(0x20000000)
1215 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB    _u(29)
1216 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB    _u(29)
1217 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW"
1218 // -----------------------------------------------------------------------------
1219 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0
1220 // Description : None
1221 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET  _u(0x1)
1222 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS   _u(0x10000000)
1223 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB    _u(28)
1224 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB    _u(28)
1225 #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW"
1226 // -----------------------------------------------------------------------------
1227 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SPI1
1228 // Description : None
1229 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET  _u(0x1)
1230 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS   _u(0x08000000)
1231 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB    _u(27)
1232 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB    _u(27)
1233 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW"
1234 // -----------------------------------------------------------------------------
1235 // Field       : CLOCKS_WAKE_EN0_CLK_PERI_SPI1
1236 // Description : None
1237 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET  _u(0x1)
1238 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS   _u(0x04000000)
1239 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB    _u(26)
1240 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB    _u(26)
1241 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW"
1242 // -----------------------------------------------------------------------------
1243 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SPI0
1244 // Description : None
1245 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET  _u(0x1)
1246 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS   _u(0x02000000)
1247 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB    _u(25)
1248 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB    _u(25)
1249 #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW"
1250 // -----------------------------------------------------------------------------
1251 // Field       : CLOCKS_WAKE_EN0_CLK_PERI_SPI0
1252 // Description : None
1253 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET  _u(0x1)
1254 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS   _u(0x01000000)
1255 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB    _u(24)
1256 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB    _u(24)
1257 #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW"
1258 // -----------------------------------------------------------------------------
1259 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_SIO
1260 // Description : None
1261 #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET  _u(0x1)
1262 #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS   _u(0x00800000)
1263 #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB    _u(23)
1264 #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB    _u(23)
1265 #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW"
1266 // -----------------------------------------------------------------------------
1267 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_RTC
1268 // Description : None
1269 #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET  _u(0x1)
1270 #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS   _u(0x00400000)
1271 #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB    _u(22)
1272 #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB    _u(22)
1273 #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW"
1274 // -----------------------------------------------------------------------------
1275 // Field       : CLOCKS_WAKE_EN0_CLK_RTC_RTC
1276 // Description : None
1277 #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET  _u(0x1)
1278 #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS   _u(0x00200000)
1279 #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB    _u(21)
1280 #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB    _u(21)
1281 #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW"
1282 // -----------------------------------------------------------------------------
1283 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_ROSC
1284 // Description : None
1285 #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET  _u(0x1)
1286 #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS   _u(0x00100000)
1287 #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB    _u(20)
1288 #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB    _u(20)
1289 #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW"
1290 // -----------------------------------------------------------------------------
1291 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_ROM
1292 // Description : None
1293 #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET  _u(0x1)
1294 #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS   _u(0x00080000)
1295 #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB    _u(19)
1296 #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB    _u(19)
1297 #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW"
1298 // -----------------------------------------------------------------------------
1299 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_RESETS
1300 // Description : None
1301 #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET  _u(0x1)
1302 #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS   _u(0x00040000)
1303 #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB    _u(18)
1304 #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB    _u(18)
1305 #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW"
1306 // -----------------------------------------------------------------------------
1307 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PWM
1308 // Description : None
1309 #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET  _u(0x1)
1310 #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS   _u(0x00020000)
1311 #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB    _u(17)
1312 #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB    _u(17)
1313 #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW"
1314 // -----------------------------------------------------------------------------
1315 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PSM
1316 // Description : None
1317 #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET  _u(0x1)
1318 #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS   _u(0x00010000)
1319 #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB    _u(16)
1320 #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB    _u(16)
1321 #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW"
1322 // -----------------------------------------------------------------------------
1323 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB
1324 // Description : None
1325 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET  _u(0x1)
1326 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS   _u(0x00008000)
1327 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB    _u(15)
1328 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB    _u(15)
1329 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
1330 // -----------------------------------------------------------------------------
1331 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS
1332 // Description : None
1333 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET  _u(0x1)
1334 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS   _u(0x00004000)
1335 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB    _u(14)
1336 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB    _u(14)
1337 #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
1338 // -----------------------------------------------------------------------------
1339 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PIO1
1340 // Description : None
1341 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET  _u(0x1)
1342 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS   _u(0x00002000)
1343 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB    _u(13)
1344 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB    _u(13)
1345 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW"
1346 // -----------------------------------------------------------------------------
1347 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PIO0
1348 // Description : None
1349 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET  _u(0x1)
1350 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS   _u(0x00001000)
1351 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB    _u(12)
1352 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB    _u(12)
1353 #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW"
1354 // -----------------------------------------------------------------------------
1355 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_PADS
1356 // Description : None
1357 #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET  _u(0x1)
1358 #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS   _u(0x00000800)
1359 #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB    _u(11)
1360 #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB    _u(11)
1361 #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW"
1362 // -----------------------------------------------------------------------------
1363 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET
1364 // Description : None
1365 #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET  _u(0x1)
1366 #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS   _u(0x00000400)
1367 #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB    _u(10)
1368 #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB    _u(10)
1369 #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
1370 // -----------------------------------------------------------------------------
1371 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_JTAG
1372 // Description : None
1373 #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET  _u(0x1)
1374 #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS   _u(0x00000200)
1375 #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB    _u(9)
1376 #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB    _u(9)
1377 #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW"
1378 // -----------------------------------------------------------------------------
1379 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_IO
1380 // Description : None
1381 #define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET  _u(0x1)
1382 #define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS   _u(0x00000100)
1383 #define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB    _u(8)
1384 #define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB    _u(8)
1385 #define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW"
1386 // -----------------------------------------------------------------------------
1387 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_I2C1
1388 // Description : None
1389 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET  _u(0x1)
1390 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS   _u(0x00000080)
1391 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB    _u(7)
1392 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB    _u(7)
1393 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW"
1394 // -----------------------------------------------------------------------------
1395 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_I2C0
1396 // Description : None
1397 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET  _u(0x1)
1398 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS   _u(0x00000040)
1399 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB    _u(6)
1400 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB    _u(6)
1401 #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW"
1402 // -----------------------------------------------------------------------------
1403 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_DMA
1404 // Description : None
1405 #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET  _u(0x1)
1406 #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS   _u(0x00000020)
1407 #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB    _u(5)
1408 #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB    _u(5)
1409 #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW"
1410 // -----------------------------------------------------------------------------
1411 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC
1412 // Description : None
1413 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET  _u(0x1)
1414 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS   _u(0x00000010)
1415 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB    _u(4)
1416 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB    _u(4)
1417 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
1418 // -----------------------------------------------------------------------------
1419 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL
1420 // Description : None
1421 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET  _u(0x1)
1422 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS   _u(0x00000008)
1423 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB    _u(3)
1424 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB    _u(3)
1425 #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
1426 // -----------------------------------------------------------------------------
1427 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_ADC
1428 // Description : None
1429 #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET  _u(0x1)
1430 #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS   _u(0x00000004)
1431 #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB    _u(2)
1432 #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB    _u(2)
1433 #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW"
1434 // -----------------------------------------------------------------------------
1435 // Field       : CLOCKS_WAKE_EN0_CLK_ADC_ADC
1436 // Description : None
1437 #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET  _u(0x1)
1438 #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS   _u(0x00000002)
1439 #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB    _u(1)
1440 #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB    _u(1)
1441 #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW"
1442 // -----------------------------------------------------------------------------
1443 // Field       : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS
1444 // Description : None
1445 #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET  _u(0x1)
1446 #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS   _u(0x00000001)
1447 #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB    _u(0)
1448 #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB    _u(0)
1449 #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
1450 // =============================================================================
1451 // Register    : CLOCKS_WAKE_EN1
1452 // Description : enable clock in wake mode
1453 #define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4)
1454 #define CLOCKS_WAKE_EN1_BITS   _u(0x00007fff)
1455 #define CLOCKS_WAKE_EN1_RESET  _u(0x00007fff)
1456 // -----------------------------------------------------------------------------
1457 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_XOSC
1458 // Description : None
1459 #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET  _u(0x1)
1460 #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS   _u(0x00004000)
1461 #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB    _u(14)
1462 #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB    _u(14)
1463 #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW"
1464 // -----------------------------------------------------------------------------
1465 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_XIP
1466 // Description : None
1467 #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET  _u(0x1)
1468 #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS   _u(0x00002000)
1469 #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB    _u(13)
1470 #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB    _u(13)
1471 #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW"
1472 // -----------------------------------------------------------------------------
1473 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG
1474 // Description : None
1475 #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET  _u(0x1)
1476 #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS   _u(0x00001000)
1477 #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB    _u(12)
1478 #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB    _u(12)
1479 #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
1480 // -----------------------------------------------------------------------------
1481 // Field       : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL
1482 // Description : None
1483 #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET  _u(0x1)
1484 #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS   _u(0x00000800)
1485 #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB    _u(11)
1486 #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB    _u(11)
1487 #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW"
1488 // -----------------------------------------------------------------------------
1489 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL
1490 // Description : None
1491 #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET  _u(0x1)
1492 #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS   _u(0x00000400)
1493 #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB    _u(10)
1494 #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB    _u(10)
1495 #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
1496 // -----------------------------------------------------------------------------
1497 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_UART1
1498 // Description : None
1499 #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET  _u(0x1)
1500 #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS   _u(0x00000200)
1501 #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB    _u(9)
1502 #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB    _u(9)
1503 #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW"
1504 // -----------------------------------------------------------------------------
1505 // Field       : CLOCKS_WAKE_EN1_CLK_PERI_UART1
1506 // Description : None
1507 #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET  _u(0x1)
1508 #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS   _u(0x00000100)
1509 #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB    _u(8)
1510 #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB    _u(8)
1511 #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW"
1512 // -----------------------------------------------------------------------------
1513 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_UART0
1514 // Description : None
1515 #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET  _u(0x1)
1516 #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS   _u(0x00000080)
1517 #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB    _u(7)
1518 #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB    _u(7)
1519 #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW"
1520 // -----------------------------------------------------------------------------
1521 // Field       : CLOCKS_WAKE_EN1_CLK_PERI_UART0
1522 // Description : None
1523 #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET  _u(0x1)
1524 #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS   _u(0x00000040)
1525 #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB    _u(6)
1526 #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB    _u(6)
1527 #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW"
1528 // -----------------------------------------------------------------------------
1529 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_TIMER
1530 // Description : None
1531 #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET  _u(0x1)
1532 #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS   _u(0x00000020)
1533 #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB    _u(5)
1534 #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB    _u(5)
1535 #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW"
1536 // -----------------------------------------------------------------------------
1537 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN
1538 // Description : None
1539 #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET  _u(0x1)
1540 #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS   _u(0x00000010)
1541 #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB    _u(4)
1542 #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB    _u(4)
1543 #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW"
1544 // -----------------------------------------------------------------------------
1545 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO
1546 // Description : None
1547 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET  _u(0x1)
1548 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS   _u(0x00000008)
1549 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB    _u(3)
1550 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB    _u(3)
1551 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
1552 // -----------------------------------------------------------------------------
1553 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG
1554 // Description : None
1555 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET  _u(0x1)
1556 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS   _u(0x00000004)
1557 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB    _u(2)
1558 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB    _u(2)
1559 #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
1560 // -----------------------------------------------------------------------------
1561 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5
1562 // Description : None
1563 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET  _u(0x1)
1564 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS   _u(0x00000002)
1565 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB    _u(1)
1566 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB    _u(1)
1567 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW"
1568 // -----------------------------------------------------------------------------
1569 // Field       : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4
1570 // Description : None
1571 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET  _u(0x1)
1572 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS   _u(0x00000001)
1573 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB    _u(0)
1574 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB    _u(0)
1575 #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW"
1576 // =============================================================================
1577 // Register    : CLOCKS_SLEEP_EN0
1578 // Description : enable clock in sleep mode
1579 #define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8)
1580 #define CLOCKS_SLEEP_EN0_BITS   _u(0xffffffff)
1581 #define CLOCKS_SLEEP_EN0_RESET  _u(0xffffffff)
1582 // -----------------------------------------------------------------------------
1583 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3
1584 // Description : None
1585 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET  _u(0x1)
1586 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS   _u(0x80000000)
1587 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB    _u(31)
1588 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB    _u(31)
1589 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW"
1590 // -----------------------------------------------------------------------------
1591 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2
1592 // Description : None
1593 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET  _u(0x1)
1594 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS   _u(0x40000000)
1595 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB    _u(30)
1596 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB    _u(30)
1597 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW"
1598 // -----------------------------------------------------------------------------
1599 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1
1600 // Description : None
1601 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET  _u(0x1)
1602 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS   _u(0x20000000)
1603 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB    _u(29)
1604 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB    _u(29)
1605 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW"
1606 // -----------------------------------------------------------------------------
1607 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0
1608 // Description : None
1609 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET  _u(0x1)
1610 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS   _u(0x10000000)
1611 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB    _u(28)
1612 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB    _u(28)
1613 #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW"
1614 // -----------------------------------------------------------------------------
1615 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1
1616 // Description : None
1617 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET  _u(0x1)
1618 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS   _u(0x08000000)
1619 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB    _u(27)
1620 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB    _u(27)
1621 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW"
1622 // -----------------------------------------------------------------------------
1623 // Field       : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1
1624 // Description : None
1625 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET  _u(0x1)
1626 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS   _u(0x04000000)
1627 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB    _u(26)
1628 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB    _u(26)
1629 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW"
1630 // -----------------------------------------------------------------------------
1631 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0
1632 // Description : None
1633 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET  _u(0x1)
1634 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS   _u(0x02000000)
1635 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB    _u(25)
1636 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB    _u(25)
1637 #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW"
1638 // -----------------------------------------------------------------------------
1639 // Field       : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0
1640 // Description : None
1641 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET  _u(0x1)
1642 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS   _u(0x01000000)
1643 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB    _u(24)
1644 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB    _u(24)
1645 #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW"
1646 // -----------------------------------------------------------------------------
1647 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_SIO
1648 // Description : None
1649 #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET  _u(0x1)
1650 #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS   _u(0x00800000)
1651 #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB    _u(23)
1652 #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB    _u(23)
1653 #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW"
1654 // -----------------------------------------------------------------------------
1655 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_RTC
1656 // Description : None
1657 #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET  _u(0x1)
1658 #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS   _u(0x00400000)
1659 #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB    _u(22)
1660 #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB    _u(22)
1661 #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW"
1662 // -----------------------------------------------------------------------------
1663 // Field       : CLOCKS_SLEEP_EN0_CLK_RTC_RTC
1664 // Description : None
1665 #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET  _u(0x1)
1666 #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS   _u(0x00200000)
1667 #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB    _u(21)
1668 #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB    _u(21)
1669 #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW"
1670 // -----------------------------------------------------------------------------
1671 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC
1672 // Description : None
1673 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET  _u(0x1)
1674 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS   _u(0x00100000)
1675 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB    _u(20)
1676 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB    _u(20)
1677 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW"
1678 // -----------------------------------------------------------------------------
1679 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_ROM
1680 // Description : None
1681 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET  _u(0x1)
1682 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS   _u(0x00080000)
1683 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB    _u(19)
1684 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB    _u(19)
1685 #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW"
1686 // -----------------------------------------------------------------------------
1687 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS
1688 // Description : None
1689 #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET  _u(0x1)
1690 #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS   _u(0x00040000)
1691 #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB    _u(18)
1692 #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB    _u(18)
1693 #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW"
1694 // -----------------------------------------------------------------------------
1695 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PWM
1696 // Description : None
1697 #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET  _u(0x1)
1698 #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS   _u(0x00020000)
1699 #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB    _u(17)
1700 #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB    _u(17)
1701 #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW"
1702 // -----------------------------------------------------------------------------
1703 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PSM
1704 // Description : None
1705 #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET  _u(0x1)
1706 #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS   _u(0x00010000)
1707 #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB    _u(16)
1708 #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB    _u(16)
1709 #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW"
1710 // -----------------------------------------------------------------------------
1711 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB
1712 // Description : None
1713 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET  _u(0x1)
1714 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS   _u(0x00008000)
1715 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB    _u(15)
1716 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB    _u(15)
1717 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
1718 // -----------------------------------------------------------------------------
1719 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS
1720 // Description : None
1721 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET  _u(0x1)
1722 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS   _u(0x00004000)
1723 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB    _u(14)
1724 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB    _u(14)
1725 #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
1726 // -----------------------------------------------------------------------------
1727 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1
1728 // Description : None
1729 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET  _u(0x1)
1730 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS   _u(0x00002000)
1731 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB    _u(13)
1732 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB    _u(13)
1733 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW"
1734 // -----------------------------------------------------------------------------
1735 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0
1736 // Description : None
1737 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET  _u(0x1)
1738 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS   _u(0x00001000)
1739 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB    _u(12)
1740 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB    _u(12)
1741 #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW"
1742 // -----------------------------------------------------------------------------
1743 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_PADS
1744 // Description : None
1745 #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET  _u(0x1)
1746 #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS   _u(0x00000800)
1747 #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB    _u(11)
1748 #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB    _u(11)
1749 #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW"
1750 // -----------------------------------------------------------------------------
1751 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET
1752 // Description : None
1753 #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET  _u(0x1)
1754 #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS   _u(0x00000400)
1755 #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB    _u(10)
1756 #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB    _u(10)
1757 #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
1758 // -----------------------------------------------------------------------------
1759 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG
1760 // Description : None
1761 #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET  _u(0x1)
1762 #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS   _u(0x00000200)
1763 #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB    _u(9)
1764 #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB    _u(9)
1765 #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW"
1766 // -----------------------------------------------------------------------------
1767 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_IO
1768 // Description : None
1769 #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET  _u(0x1)
1770 #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS   _u(0x00000100)
1771 #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB    _u(8)
1772 #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB    _u(8)
1773 #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW"
1774 // -----------------------------------------------------------------------------
1775 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1
1776 // Description : None
1777 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET  _u(0x1)
1778 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS   _u(0x00000080)
1779 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB    _u(7)
1780 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB    _u(7)
1781 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW"
1782 // -----------------------------------------------------------------------------
1783 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0
1784 // Description : None
1785 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET  _u(0x1)
1786 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS   _u(0x00000040)
1787 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB    _u(6)
1788 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB    _u(6)
1789 #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW"
1790 // -----------------------------------------------------------------------------
1791 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_DMA
1792 // Description : None
1793 #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET  _u(0x1)
1794 #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS   _u(0x00000020)
1795 #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB    _u(5)
1796 #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB    _u(5)
1797 #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW"
1798 // -----------------------------------------------------------------------------
1799 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC
1800 // Description : None
1801 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET  _u(0x1)
1802 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS   _u(0x00000010)
1803 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB    _u(4)
1804 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB    _u(4)
1805 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
1806 // -----------------------------------------------------------------------------
1807 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL
1808 // Description : None
1809 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET  _u(0x1)
1810 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS   _u(0x00000008)
1811 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB    _u(3)
1812 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB    _u(3)
1813 #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
1814 // -----------------------------------------------------------------------------
1815 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_ADC
1816 // Description : None
1817 #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET  _u(0x1)
1818 #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS   _u(0x00000004)
1819 #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB    _u(2)
1820 #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB    _u(2)
1821 #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW"
1822 // -----------------------------------------------------------------------------
1823 // Field       : CLOCKS_SLEEP_EN0_CLK_ADC_ADC
1824 // Description : None
1825 #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET  _u(0x1)
1826 #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS   _u(0x00000002)
1827 #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB    _u(1)
1828 #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB    _u(1)
1829 #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW"
1830 // -----------------------------------------------------------------------------
1831 // Field       : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS
1832 // Description : None
1833 #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET  _u(0x1)
1834 #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS   _u(0x00000001)
1835 #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB    _u(0)
1836 #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB    _u(0)
1837 #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
1838 // =============================================================================
1839 // Register    : CLOCKS_SLEEP_EN1
1840 // Description : enable clock in sleep mode
1841 #define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac)
1842 #define CLOCKS_SLEEP_EN1_BITS   _u(0x00007fff)
1843 #define CLOCKS_SLEEP_EN1_RESET  _u(0x00007fff)
1844 // -----------------------------------------------------------------------------
1845 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC
1846 // Description : None
1847 #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET  _u(0x1)
1848 #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS   _u(0x00004000)
1849 #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB    _u(14)
1850 #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB    _u(14)
1851 #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW"
1852 // -----------------------------------------------------------------------------
1853 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_XIP
1854 // Description : None
1855 #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET  _u(0x1)
1856 #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS   _u(0x00002000)
1857 #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB    _u(13)
1858 #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB    _u(13)
1859 #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW"
1860 // -----------------------------------------------------------------------------
1861 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG
1862 // Description : None
1863 #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET  _u(0x1)
1864 #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS   _u(0x00001000)
1865 #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB    _u(12)
1866 #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB    _u(12)
1867 #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
1868 // -----------------------------------------------------------------------------
1869 // Field       : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL
1870 // Description : None
1871 #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET  _u(0x1)
1872 #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS   _u(0x00000800)
1873 #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB    _u(11)
1874 #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB    _u(11)
1875 #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW"
1876 // -----------------------------------------------------------------------------
1877 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL
1878 // Description : None
1879 #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET  _u(0x1)
1880 #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS   _u(0x00000400)
1881 #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB    _u(10)
1882 #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB    _u(10)
1883 #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
1884 // -----------------------------------------------------------------------------
1885 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_UART1
1886 // Description : None
1887 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET  _u(0x1)
1888 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS   _u(0x00000200)
1889 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB    _u(9)
1890 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB    _u(9)
1891 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW"
1892 // -----------------------------------------------------------------------------
1893 // Field       : CLOCKS_SLEEP_EN1_CLK_PERI_UART1
1894 // Description : None
1895 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET  _u(0x1)
1896 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS   _u(0x00000100)
1897 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB    _u(8)
1898 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB    _u(8)
1899 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW"
1900 // -----------------------------------------------------------------------------
1901 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_UART0
1902 // Description : None
1903 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET  _u(0x1)
1904 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS   _u(0x00000080)
1905 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB    _u(7)
1906 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB    _u(7)
1907 #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW"
1908 // -----------------------------------------------------------------------------
1909 // Field       : CLOCKS_SLEEP_EN1_CLK_PERI_UART0
1910 // Description : None
1911 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET  _u(0x1)
1912 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS   _u(0x00000040)
1913 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB    _u(6)
1914 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB    _u(6)
1915 #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW"
1916 // -----------------------------------------------------------------------------
1917 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER
1918 // Description : None
1919 #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET  _u(0x1)
1920 #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS   _u(0x00000020)
1921 #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB    _u(5)
1922 #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB    _u(5)
1923 #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW"
1924 // -----------------------------------------------------------------------------
1925 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN
1926 // Description : None
1927 #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET  _u(0x1)
1928 #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS   _u(0x00000010)
1929 #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB    _u(4)
1930 #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB    _u(4)
1931 #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW"
1932 // -----------------------------------------------------------------------------
1933 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO
1934 // Description : None
1935 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET  _u(0x1)
1936 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS   _u(0x00000008)
1937 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB    _u(3)
1938 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB    _u(3)
1939 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
1940 // -----------------------------------------------------------------------------
1941 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG
1942 // Description : None
1943 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET  _u(0x1)
1944 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS   _u(0x00000004)
1945 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB    _u(2)
1946 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB    _u(2)
1947 #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
1948 // -----------------------------------------------------------------------------
1949 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5
1950 // Description : None
1951 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET  _u(0x1)
1952 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS   _u(0x00000002)
1953 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB    _u(1)
1954 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB    _u(1)
1955 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW"
1956 // -----------------------------------------------------------------------------
1957 // Field       : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4
1958 // Description : None
1959 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET  _u(0x1)
1960 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS   _u(0x00000001)
1961 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB    _u(0)
1962 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB    _u(0)
1963 #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW"
1964 // =============================================================================
1965 // Register    : CLOCKS_ENABLED0
1966 // Description : indicates the state of the clock enable
1967 #define CLOCKS_ENABLED0_OFFSET _u(0x000000b0)
1968 #define CLOCKS_ENABLED0_BITS   _u(0xffffffff)
1969 #define CLOCKS_ENABLED0_RESET  _u(0x00000000)
1970 // -----------------------------------------------------------------------------
1971 // Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM3
1972 // Description : None
1973 #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET  _u(0x0)
1974 #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS   _u(0x80000000)
1975 #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB    _u(31)
1976 #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB    _u(31)
1977 #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO"
1978 // -----------------------------------------------------------------------------
1979 // Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM2
1980 // Description : None
1981 #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET  _u(0x0)
1982 #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS   _u(0x40000000)
1983 #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB    _u(30)
1984 #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB    _u(30)
1985 #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO"
1986 // -----------------------------------------------------------------------------
1987 // Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM1
1988 // Description : None
1989 #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET  _u(0x0)
1990 #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS   _u(0x20000000)
1991 #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB    _u(29)
1992 #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB    _u(29)
1993 #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO"
1994 // -----------------------------------------------------------------------------
1995 // Field       : CLOCKS_ENABLED0_CLK_SYS_SRAM0
1996 // Description : None
1997 #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET  _u(0x0)
1998 #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS   _u(0x10000000)
1999 #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB    _u(28)
2000 #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB    _u(28)
2001 #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO"
2002 // -----------------------------------------------------------------------------
2003 // Field       : CLOCKS_ENABLED0_CLK_SYS_SPI1
2004 // Description : None
2005 #define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET  _u(0x0)
2006 #define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS   _u(0x08000000)
2007 #define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB    _u(27)
2008 #define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB    _u(27)
2009 #define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO"
2010 // -----------------------------------------------------------------------------
2011 // Field       : CLOCKS_ENABLED0_CLK_PERI_SPI1
2012 // Description : None
2013 #define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET  _u(0x0)
2014 #define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS   _u(0x04000000)
2015 #define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB    _u(26)
2016 #define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB    _u(26)
2017 #define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO"
2018 // -----------------------------------------------------------------------------
2019 // Field       : CLOCKS_ENABLED0_CLK_SYS_SPI0
2020 // Description : None
2021 #define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET  _u(0x0)
2022 #define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS   _u(0x02000000)
2023 #define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB    _u(25)
2024 #define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB    _u(25)
2025 #define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO"
2026 // -----------------------------------------------------------------------------
2027 // Field       : CLOCKS_ENABLED0_CLK_PERI_SPI0
2028 // Description : None
2029 #define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET  _u(0x0)
2030 #define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS   _u(0x01000000)
2031 #define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB    _u(24)
2032 #define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB    _u(24)
2033 #define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO"
2034 // -----------------------------------------------------------------------------
2035 // Field       : CLOCKS_ENABLED0_CLK_SYS_SIO
2036 // Description : None
2037 #define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET  _u(0x0)
2038 #define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS   _u(0x00800000)
2039 #define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB    _u(23)
2040 #define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB    _u(23)
2041 #define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO"
2042 // -----------------------------------------------------------------------------
2043 // Field       : CLOCKS_ENABLED0_CLK_SYS_RTC
2044 // Description : None
2045 #define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET  _u(0x0)
2046 #define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS   _u(0x00400000)
2047 #define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB    _u(22)
2048 #define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB    _u(22)
2049 #define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO"
2050 // -----------------------------------------------------------------------------
2051 // Field       : CLOCKS_ENABLED0_CLK_RTC_RTC
2052 // Description : None
2053 #define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET  _u(0x0)
2054 #define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS   _u(0x00200000)
2055 #define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB    _u(21)
2056 #define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB    _u(21)
2057 #define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO"
2058 // -----------------------------------------------------------------------------
2059 // Field       : CLOCKS_ENABLED0_CLK_SYS_ROSC
2060 // Description : None
2061 #define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET  _u(0x0)
2062 #define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS   _u(0x00100000)
2063 #define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB    _u(20)
2064 #define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB    _u(20)
2065 #define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO"
2066 // -----------------------------------------------------------------------------
2067 // Field       : CLOCKS_ENABLED0_CLK_SYS_ROM
2068 // Description : None
2069 #define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET  _u(0x0)
2070 #define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS   _u(0x00080000)
2071 #define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB    _u(19)
2072 #define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB    _u(19)
2073 #define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO"
2074 // -----------------------------------------------------------------------------
2075 // Field       : CLOCKS_ENABLED0_CLK_SYS_RESETS
2076 // Description : None
2077 #define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET  _u(0x0)
2078 #define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS   _u(0x00040000)
2079 #define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB    _u(18)
2080 #define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB    _u(18)
2081 #define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO"
2082 // -----------------------------------------------------------------------------
2083 // Field       : CLOCKS_ENABLED0_CLK_SYS_PWM
2084 // Description : None
2085 #define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET  _u(0x0)
2086 #define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS   _u(0x00020000)
2087 #define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB    _u(17)
2088 #define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB    _u(17)
2089 #define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO"
2090 // -----------------------------------------------------------------------------
2091 // Field       : CLOCKS_ENABLED0_CLK_SYS_PSM
2092 // Description : None
2093 #define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET  _u(0x0)
2094 #define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS   _u(0x00010000)
2095 #define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB    _u(16)
2096 #define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB    _u(16)
2097 #define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO"
2098 // -----------------------------------------------------------------------------
2099 // Field       : CLOCKS_ENABLED0_CLK_SYS_PLL_USB
2100 // Description : None
2101 #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET  _u(0x0)
2102 #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS   _u(0x00008000)
2103 #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB    _u(15)
2104 #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB    _u(15)
2105 #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO"
2106 // -----------------------------------------------------------------------------
2107 // Field       : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS
2108 // Description : None
2109 #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET  _u(0x0)
2110 #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS   _u(0x00004000)
2111 #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB    _u(14)
2112 #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB    _u(14)
2113 #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO"
2114 // -----------------------------------------------------------------------------
2115 // Field       : CLOCKS_ENABLED0_CLK_SYS_PIO1
2116 // Description : None
2117 #define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET  _u(0x0)
2118 #define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS   _u(0x00002000)
2119 #define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB    _u(13)
2120 #define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB    _u(13)
2121 #define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO"
2122 // -----------------------------------------------------------------------------
2123 // Field       : CLOCKS_ENABLED0_CLK_SYS_PIO0
2124 // Description : None
2125 #define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET  _u(0x0)
2126 #define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS   _u(0x00001000)
2127 #define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB    _u(12)
2128 #define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB    _u(12)
2129 #define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO"
2130 // -----------------------------------------------------------------------------
2131 // Field       : CLOCKS_ENABLED0_CLK_SYS_PADS
2132 // Description : None
2133 #define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET  _u(0x0)
2134 #define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS   _u(0x00000800)
2135 #define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB    _u(11)
2136 #define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB    _u(11)
2137 #define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO"
2138 // -----------------------------------------------------------------------------
2139 // Field       : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET
2140 // Description : None
2141 #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET  _u(0x0)
2142 #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS   _u(0x00000400)
2143 #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB    _u(10)
2144 #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB    _u(10)
2145 #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO"
2146 // -----------------------------------------------------------------------------
2147 // Field       : CLOCKS_ENABLED0_CLK_SYS_JTAG
2148 // Description : None
2149 #define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET  _u(0x0)
2150 #define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS   _u(0x00000200)
2151 #define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB    _u(9)
2152 #define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB    _u(9)
2153 #define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO"
2154 // -----------------------------------------------------------------------------
2155 // Field       : CLOCKS_ENABLED0_CLK_SYS_IO
2156 // Description : None
2157 #define CLOCKS_ENABLED0_CLK_SYS_IO_RESET  _u(0x0)
2158 #define CLOCKS_ENABLED0_CLK_SYS_IO_BITS   _u(0x00000100)
2159 #define CLOCKS_ENABLED0_CLK_SYS_IO_MSB    _u(8)
2160 #define CLOCKS_ENABLED0_CLK_SYS_IO_LSB    _u(8)
2161 #define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO"
2162 // -----------------------------------------------------------------------------
2163 // Field       : CLOCKS_ENABLED0_CLK_SYS_I2C1
2164 // Description : None
2165 #define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET  _u(0x0)
2166 #define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS   _u(0x00000080)
2167 #define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB    _u(7)
2168 #define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB    _u(7)
2169 #define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO"
2170 // -----------------------------------------------------------------------------
2171 // Field       : CLOCKS_ENABLED0_CLK_SYS_I2C0
2172 // Description : None
2173 #define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET  _u(0x0)
2174 #define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS   _u(0x00000040)
2175 #define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB    _u(6)
2176 #define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB    _u(6)
2177 #define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO"
2178 // -----------------------------------------------------------------------------
2179 // Field       : CLOCKS_ENABLED0_CLK_SYS_DMA
2180 // Description : None
2181 #define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET  _u(0x0)
2182 #define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS   _u(0x00000020)
2183 #define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB    _u(5)
2184 #define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB    _u(5)
2185 #define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO"
2186 // -----------------------------------------------------------------------------
2187 // Field       : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC
2188 // Description : None
2189 #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET  _u(0x0)
2190 #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS   _u(0x00000010)
2191 #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB    _u(4)
2192 #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB    _u(4)
2193 #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO"
2194 // -----------------------------------------------------------------------------
2195 // Field       : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL
2196 // Description : None
2197 #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET  _u(0x0)
2198 #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS   _u(0x00000008)
2199 #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB    _u(3)
2200 #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB    _u(3)
2201 #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO"
2202 // -----------------------------------------------------------------------------
2203 // Field       : CLOCKS_ENABLED0_CLK_SYS_ADC
2204 // Description : None
2205 #define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET  _u(0x0)
2206 #define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS   _u(0x00000004)
2207 #define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB    _u(2)
2208 #define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB    _u(2)
2209 #define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO"
2210 // -----------------------------------------------------------------------------
2211 // Field       : CLOCKS_ENABLED0_CLK_ADC_ADC
2212 // Description : None
2213 #define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET  _u(0x0)
2214 #define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS   _u(0x00000002)
2215 #define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB    _u(1)
2216 #define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB    _u(1)
2217 #define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO"
2218 // -----------------------------------------------------------------------------
2219 // Field       : CLOCKS_ENABLED0_CLK_SYS_CLOCKS
2220 // Description : None
2221 #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET  _u(0x0)
2222 #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS   _u(0x00000001)
2223 #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB    _u(0)
2224 #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB    _u(0)
2225 #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO"
2226 // =============================================================================
2227 // Register    : CLOCKS_ENABLED1
2228 // Description : indicates the state of the clock enable
2229 #define CLOCKS_ENABLED1_OFFSET _u(0x000000b4)
2230 #define CLOCKS_ENABLED1_BITS   _u(0x00007fff)
2231 #define CLOCKS_ENABLED1_RESET  _u(0x00000000)
2232 // -----------------------------------------------------------------------------
2233 // Field       : CLOCKS_ENABLED1_CLK_SYS_XOSC
2234 // Description : None
2235 #define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET  _u(0x0)
2236 #define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS   _u(0x00004000)
2237 #define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB    _u(14)
2238 #define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB    _u(14)
2239 #define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO"
2240 // -----------------------------------------------------------------------------
2241 // Field       : CLOCKS_ENABLED1_CLK_SYS_XIP
2242 // Description : None
2243 #define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET  _u(0x0)
2244 #define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS   _u(0x00002000)
2245 #define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB    _u(13)
2246 #define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB    _u(13)
2247 #define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO"
2248 // -----------------------------------------------------------------------------
2249 // Field       : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG
2250 // Description : None
2251 #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET  _u(0x0)
2252 #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS   _u(0x00001000)
2253 #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB    _u(12)
2254 #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB    _u(12)
2255 #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO"
2256 // -----------------------------------------------------------------------------
2257 // Field       : CLOCKS_ENABLED1_CLK_USB_USBCTRL
2258 // Description : None
2259 #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET  _u(0x0)
2260 #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS   _u(0x00000800)
2261 #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB    _u(11)
2262 #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB    _u(11)
2263 #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO"
2264 // -----------------------------------------------------------------------------
2265 // Field       : CLOCKS_ENABLED1_CLK_SYS_USBCTRL
2266 // Description : None
2267 #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET  _u(0x0)
2268 #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS   _u(0x00000400)
2269 #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB    _u(10)
2270 #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB    _u(10)
2271 #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO"
2272 // -----------------------------------------------------------------------------
2273 // Field       : CLOCKS_ENABLED1_CLK_SYS_UART1
2274 // Description : None
2275 #define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET  _u(0x0)
2276 #define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS   _u(0x00000200)
2277 #define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB    _u(9)
2278 #define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB    _u(9)
2279 #define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO"
2280 // -----------------------------------------------------------------------------
2281 // Field       : CLOCKS_ENABLED1_CLK_PERI_UART1
2282 // Description : None
2283 #define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET  _u(0x0)
2284 #define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS   _u(0x00000100)
2285 #define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB    _u(8)
2286 #define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB    _u(8)
2287 #define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO"
2288 // -----------------------------------------------------------------------------
2289 // Field       : CLOCKS_ENABLED1_CLK_SYS_UART0
2290 // Description : None
2291 #define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET  _u(0x0)
2292 #define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS   _u(0x00000080)
2293 #define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB    _u(7)
2294 #define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB    _u(7)
2295 #define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO"
2296 // -----------------------------------------------------------------------------
2297 // Field       : CLOCKS_ENABLED1_CLK_PERI_UART0
2298 // Description : None
2299 #define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET  _u(0x0)
2300 #define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS   _u(0x00000040)
2301 #define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB    _u(6)
2302 #define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB    _u(6)
2303 #define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO"
2304 // -----------------------------------------------------------------------------
2305 // Field       : CLOCKS_ENABLED1_CLK_SYS_TIMER
2306 // Description : None
2307 #define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET  _u(0x0)
2308 #define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS   _u(0x00000020)
2309 #define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB    _u(5)
2310 #define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB    _u(5)
2311 #define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO"
2312 // -----------------------------------------------------------------------------
2313 // Field       : CLOCKS_ENABLED1_CLK_SYS_TBMAN
2314 // Description : None
2315 #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET  _u(0x0)
2316 #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS   _u(0x00000010)
2317 #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB    _u(4)
2318 #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB    _u(4)
2319 #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO"
2320 // -----------------------------------------------------------------------------
2321 // Field       : CLOCKS_ENABLED1_CLK_SYS_SYSINFO
2322 // Description : None
2323 #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET  _u(0x0)
2324 #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS   _u(0x00000008)
2325 #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB    _u(3)
2326 #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB    _u(3)
2327 #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO"
2328 // -----------------------------------------------------------------------------
2329 // Field       : CLOCKS_ENABLED1_CLK_SYS_SYSCFG
2330 // Description : None
2331 #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET  _u(0x0)
2332 #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS   _u(0x00000004)
2333 #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB    _u(2)
2334 #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB    _u(2)
2335 #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO"
2336 // -----------------------------------------------------------------------------
2337 // Field       : CLOCKS_ENABLED1_CLK_SYS_SRAM5
2338 // Description : None
2339 #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET  _u(0x0)
2340 #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS   _u(0x00000002)
2341 #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB    _u(1)
2342 #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB    _u(1)
2343 #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO"
2344 // -----------------------------------------------------------------------------
2345 // Field       : CLOCKS_ENABLED1_CLK_SYS_SRAM4
2346 // Description : None
2347 #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET  _u(0x0)
2348 #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS   _u(0x00000001)
2349 #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB    _u(0)
2350 #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB    _u(0)
2351 #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO"
2352 // =============================================================================
2353 // Register    : CLOCKS_INTR
2354 // Description : Raw Interrupts
2355 #define CLOCKS_INTR_OFFSET _u(0x000000b8)
2356 #define CLOCKS_INTR_BITS   _u(0x00000001)
2357 #define CLOCKS_INTR_RESET  _u(0x00000000)
2358 // -----------------------------------------------------------------------------
2359 // Field       : CLOCKS_INTR_CLK_SYS_RESUS
2360 // Description : None
2361 #define CLOCKS_INTR_CLK_SYS_RESUS_RESET  _u(0x0)
2362 #define CLOCKS_INTR_CLK_SYS_RESUS_BITS   _u(0x00000001)
2363 #define CLOCKS_INTR_CLK_SYS_RESUS_MSB    _u(0)
2364 #define CLOCKS_INTR_CLK_SYS_RESUS_LSB    _u(0)
2365 #define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO"
2366 // =============================================================================
2367 // Register    : CLOCKS_INTE
2368 // Description : Interrupt Enable
2369 #define CLOCKS_INTE_OFFSET _u(0x000000bc)
2370 #define CLOCKS_INTE_BITS   _u(0x00000001)
2371 #define CLOCKS_INTE_RESET  _u(0x00000000)
2372 // -----------------------------------------------------------------------------
2373 // Field       : CLOCKS_INTE_CLK_SYS_RESUS
2374 // Description : None
2375 #define CLOCKS_INTE_CLK_SYS_RESUS_RESET  _u(0x0)
2376 #define CLOCKS_INTE_CLK_SYS_RESUS_BITS   _u(0x00000001)
2377 #define CLOCKS_INTE_CLK_SYS_RESUS_MSB    _u(0)
2378 #define CLOCKS_INTE_CLK_SYS_RESUS_LSB    _u(0)
2379 #define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW"
2380 // =============================================================================
2381 // Register    : CLOCKS_INTF
2382 // Description : Interrupt Force
2383 #define CLOCKS_INTF_OFFSET _u(0x000000c0)
2384 #define CLOCKS_INTF_BITS   _u(0x00000001)
2385 #define CLOCKS_INTF_RESET  _u(0x00000000)
2386 // -----------------------------------------------------------------------------
2387 // Field       : CLOCKS_INTF_CLK_SYS_RESUS
2388 // Description : None
2389 #define CLOCKS_INTF_CLK_SYS_RESUS_RESET  _u(0x0)
2390 #define CLOCKS_INTF_CLK_SYS_RESUS_BITS   _u(0x00000001)
2391 #define CLOCKS_INTF_CLK_SYS_RESUS_MSB    _u(0)
2392 #define CLOCKS_INTF_CLK_SYS_RESUS_LSB    _u(0)
2393 #define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW"
2394 // =============================================================================
2395 // Register    : CLOCKS_INTS
2396 // Description : Interrupt status after masking & forcing
2397 #define CLOCKS_INTS_OFFSET _u(0x000000c4)
2398 #define CLOCKS_INTS_BITS   _u(0x00000001)
2399 #define CLOCKS_INTS_RESET  _u(0x00000000)
2400 // -----------------------------------------------------------------------------
2401 // Field       : CLOCKS_INTS_CLK_SYS_RESUS
2402 // Description : None
2403 #define CLOCKS_INTS_CLK_SYS_RESUS_RESET  _u(0x0)
2404 #define CLOCKS_INTS_CLK_SYS_RESUS_BITS   _u(0x00000001)
2405 #define CLOCKS_INTS_CLK_SYS_RESUS_MSB    _u(0)
2406 #define CLOCKS_INTS_CLK_SYS_RESUS_LSB    _u(0)
2407 #define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO"
2408 // =============================================================================
2409 #endif // HARDWARE_REGS_CLOCKS_DEFINED
2410