1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup GLCDC 9 * @{ 10 **********************************************************************************************************************/ 11 12 #ifndef R_GLCDC_H 13 #define R_GLCDC_H 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include "r_display_api.h" 20 21 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 22 FSP_HEADER 23 24 /*********************************************************************************************************************** 25 * Macro definitions 26 **********************************************************************************************************************/ 27 28 /*********************************************************************************************************************** 29 * Typedef definitions 30 **********************************************************************************************************************/ 31 32 /** Display control block. DO NOT INITIALIZE. */ 33 typedef struct st_glcdc_instance_ctrl 34 { 35 display_state_t state; // Status of GLCDC module 36 37 /* Parameters to Event processing for display devices */ 38 void (* p_callback)(display_callback_args_t * p_args); // Pointer to callback function 39 void const * p_context; // Pointer to the higher level device context 40 const display_cfg_t * p_cfg; // Pointer to initial configurations 41 } glcdc_instance_ctrl_t; 42 43 /** Clock source select */ 44 typedef enum e_glcdc_clk_src 45 { 46 GLCDC_CLK_SRC_INTERNAL, ///< Internal 47 GLCDC_CLK_SRC_EXTERNAL, ///< External 48 } glcdc_clk_src_t; 49 50 /** Clock frequency division ratio */ 51 typedef enum e_glcdc_panel_clk_div 52 { 53 GLCDC_PANEL_CLK_DIVISOR_1 = 1, ///< Division Ratio 1/1 54 GLCDC_PANEL_CLK_DIVISOR_2 = 2, ///< Division Ratio 1/2 55 GLCDC_PANEL_CLK_DIVISOR_3 = 3, ///< Division Ratio 1/3 56 GLCDC_PANEL_CLK_DIVISOR_4 = 4, ///< Division Ratio 1/4 57 GLCDC_PANEL_CLK_DIVISOR_5 = 5, ///< Division Ratio 1/5 58 GLCDC_PANEL_CLK_DIVISOR_6 = 6, ///< Division Ratio 1/6 59 GLCDC_PANEL_CLK_DIVISOR_7 = 7, ///< Division Ratio 1/7 60 GLCDC_PANEL_CLK_DIVISOR_8 = 8, ///< Division Ratio 1/8 61 GLCDC_PANEL_CLK_DIVISOR_9 = 9, ///< Division Ratio 1/9 62 GLCDC_PANEL_CLK_DIVISOR_12 = 12, ///< Division Ratio 1/12 63 GLCDC_PANEL_CLK_DIVISOR_16 = 16, ///< Division Ratio 1/16 64 GLCDC_PANEL_CLK_DIVISOR_24 = 24, ///< Division Ratio 1/24 65 GLCDC_PANEL_CLK_DIVISOR_32 = 32, ///< Division Ratio 1/32 66 } glcdc_panel_clk_div_t; 67 68 /** LCD TCON output pin select */ 69 typedef enum e_glcdc_tcon_pin 70 { 71 GLCDC_TCON_PIN_NONE = -1, ///< No output 72 GLCDC_TCON_PIN_0, ///< LCD_TCON0 73 GLCDC_TCON_PIN_1, ///< LCD_TCON1 74 GLCDC_TCON_PIN_2, ///< LCD_TCON2 75 GLCDC_TCON_PIN_3, ///< LCD_TCON3 76 } glcdc_tcon_pin_t; 77 78 /** Bus Arbitration setting */ 79 typedef enum e_glcdc_bus_arbitraion 80 { 81 GLCDC_BUS_ARBITRATION_ROUNDROBIN, ///< Round robin 82 GLCDC_BUS_ARBITRATION_FIX_PRIORITY ///< Fixed 83 } glcdc_bus_arbitration_t; 84 85 /** Correction circuit sequence control */ 86 typedef enum e_glcdc_correction_proc_order 87 { 88 GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA, ///< Brightness -> contrast -> gamma correction 89 GLCDC_CORRECTION_PROC_ORDER_GAMMA2BRIGHTNESS_CONTRAST ///< Gamma correction -> brightness -> contrast 90 } glcdc_correction_proc_order_t; 91 92 /** Timing signals for driving the LCD panel */ 93 typedef enum e_glcdc_tcon_signal_select 94 { 95 GLCDC_TCON_SIGNAL_SELECT_STVA_VS = 0, ///< STVA/VS 96 GLCDC_TCON_SIGNAL_SELECT_STVB_VE = 1, ///< STVB/VE 97 GLCDC_TCON_SIGNAL_SELECT_STHA_HS = 2, ///< STH/SP/HS 98 GLCDC_TCON_SIGNAL_SELECT_STHB_HE = 3, ///< STB/LP/HE 99 GLCDC_TCON_SIGNAL_SELECT_DE = 7 ///< DE 100 } glcdc_tcon_signal_select_t; 101 102 /** Clock phase adjustment for serial RGB output */ 103 typedef enum e_glcdc_clut_plane 104 { 105 GLCDC_CLUT_PLANE_0 = 0, ///< GLCDC CLUT plane 0 106 GLCDC_CLUT_PLANE_1 = 1, ///< GLCDC CLUT plane 1 107 } glcdc_clut_plane_t; 108 109 /** Dithering mode */ 110 typedef enum e_glcdc_dithering_mode 111 { 112 GLCDC_DITHERING_MODE_TRUNCATE = 0, ///< No dithering (truncate) 113 GLCDC_DITHERING_MODE_ROUND_OFF = 1, ///< Dithering with round off 114 GLCDC_DITHERING_MODE_2X2PATTERN = 2, ///< Dithering with 2x2 pattern 115 GLCDC_DITHERING_MODE_SETTING_MAX 116 } glcdc_dithering_mode_t; 117 118 /** Dithering mode */ 119 typedef enum e_glcdc_dithering_pattern 120 { 121 GLCDC_DITHERING_PATTERN_00 = 0, ///< 2x2 pattern '00' 122 GLCDC_DITHERING_PATTERN_01 = 1, ///< 2x2 pattern '01' 123 GLCDC_DITHERING_PATTERN_10 = 2, ///< 2x2 pattern '10' 124 GLCDC_DITHERING_PATTERN_11 = 3, ///< 2x2 pattern '11' 125 } glcdc_dithering_pattern_t; 126 127 /** Output interface format */ 128 typedef enum e_glcdc_input_interface_format 129 { 130 GLCDC_INPUT_INTERFACE_FORMAT_RGB565 = 0, ///< Input interface format RGB565 131 GLCDC_INPUT_INTERFACE_FORMAT_RGB888 = 1, ///< Input interface format RGB888 132 GLCDC_INPUT_INTERFACE_FORMAT_ARGB1555 = 2, ///< Input interface format ARGB1555 133 GLCDC_INPUT_INTERFACE_FORMAT_ARGB4444 = 3, ///< Input interface format ARGB4444 134 GLCDC_INPUT_INTERFACE_FORMAT_ARGB8888 = 4, ///< Input interface format ARGB8888 135 GLCDC_INPUT_INTERFACE_FORMAT_CLUT8 = 5, ///< Input interface format CLUT8 136 GLCDC_INPUT_INTERFACE_FORMAT_CLUT4 = 6, ///< Input interface format CLUT4 137 GLCDC_INPUT_INTERFACE_FORMAT_CLUT1 = 7, ///< Input interface format CLUT1 138 } glcdc_input_interface_format_t; 139 140 /** Output interface format */ 141 typedef enum e_glcdc_output_interface_format 142 { 143 GLCDC_OUTPUT_INTERFACE_FORMAT_RGB888 = 0, ///< Output interface format RGB888 144 GLCDC_OUTPUT_INTERFACE_FORMAT_RGB666 = 1, ///< Output interface format RGB666 145 GLCDC_OUTPUT_INTERFACE_FORMAT_RGB565 = 2, ///< Output interface format RGB565 146 GLCDC_OUTPUT_INTERFACE_FORMAT_SERIAL_RGB = 3, ///< Output interface format Serial RGB 147 } glcdc_output_interface_format_t; 148 149 /** Dithering output format */ 150 typedef enum e_glcdc_dithering_output_format 151 { 152 GLCDC_DITHERING_OUTPUT_FORMAT_RGB888 = 0, ///< Dithering output format RGB888 153 GLCDC_DITHERING_OUTPUT_FORMAT_RGB666 = 1, ///< Dithering output format RGB666 154 GLCDC_DITHERING_OUTPUT_FORMAT_RGB565 = 2, ///< Dithering output format RGB565 155 } glcdc_dithering_output_format_t; 156 157 /** GLCDC hardware specific configuration */ 158 typedef struct st_glcdc_extended_cfg 159 { 160 glcdc_tcon_pin_t tcon_hsync; ///< GLCDC TCON output pin select 161 glcdc_tcon_pin_t tcon_vsync; ///< GLCDC TCON output pin select 162 glcdc_tcon_pin_t tcon_de; ///< GLCDC TCON output pin select 163 glcdc_correction_proc_order_t correction_proc_order; ///< Correction control route select 164 glcdc_clk_src_t clksrc; ///< Clock Source selection 165 glcdc_panel_clk_div_t clock_div_ratio; ///< Clock divide ratio for dot clock 166 glcdc_dithering_mode_t dithering_mode; ///< Dithering mode 167 glcdc_dithering_pattern_t dithering_pattern_A; ///< Dithering pattern A 168 glcdc_dithering_pattern_t dithering_pattern_B; ///< Dithering pattern B 169 glcdc_dithering_pattern_t dithering_pattern_C; ///< Dithering pattern C 170 glcdc_dithering_pattern_t dithering_pattern_D; ///< Dithering pattern D 171 void * phy_layer; ///< Alternate PHY layer, such as MIPI DSI. 172 } glcdc_extended_cfg_t; 173 174 /* GLCDC hardware specific control block */ 175 typedef struct st_glcdc_ctrl 176 { 177 display_coordinate_t back_porch; ///< Zero coordinate for graphics plane(Back porch end) 178 uint16_t hsize; ///< Horizontal pixel size in a line 179 uint16_t vsize; ///< Vertical pixel size in a frame 180 void * p_context; ///< Pointer to the function level device context 181 // (e.g. display_ctrl_t type data) 182 } glcdc_ctrl_t; 183 184 /********************************************************************************************************************** 185 * Exported global variables 186 **********************************************************************************************************************/ 187 188 /* @cond INC_HEADER_DEFS_SEC */ 189 /* Filled in Interface API structure for this Instance. */ 190 extern const display_api_t g_display_on_glcdc; 191 192 /* @endcond */ 193 194 /********************************************************************************************************************** 195 * Public APIs 196 **********************************************************************************************************************/ 197 198 fsp_err_t R_GLCDC_Open(display_ctrl_t * const p_api_ctrl, display_cfg_t const * const p_cfg); 199 fsp_err_t R_GLCDC_Close(display_ctrl_t * const p_api_ctrl); 200 fsp_err_t R_GLCDC_Start(display_ctrl_t * const p_api_ctrl); 201 fsp_err_t R_GLCDC_Stop(display_ctrl_t * const p_api_ctrl); 202 fsp_err_t R_GLCDC_LayerChange(display_ctrl_t const * const p_api_ctrl, 203 display_runtime_cfg_t const * const p_cfg, 204 display_frame_layer_t layer); 205 fsp_err_t R_GLCDC_BufferChange(display_ctrl_t const * const p_api_ctrl, 206 uint8_t * const framebuffer, 207 display_frame_layer_t layer); 208 fsp_err_t R_GLCDC_ColorCorrection(display_ctrl_t const * const p_api_ctrl, 209 display_correction_t const * const p_correction); 210 fsp_err_t R_GLCDC_ClutUpdate(display_ctrl_t const * const p_api_ctrl, 211 display_clut_cfg_t const * const p_clut_cfg, 212 display_frame_layer_t layer); 213 fsp_err_t R_GLCDC_ClutEdit(display_ctrl_t const * const p_api_ctrl, 214 display_frame_layer_t layer, 215 uint8_t index, 216 uint32_t color); 217 fsp_err_t R_GLCDC_ColorKeySet(display_ctrl_t const * const p_api_ctrl, 218 display_colorkeying_layer_t key_cfg, 219 display_frame_layer_t layer); 220 fsp_err_t R_GLCDC_StatusGet(display_ctrl_t const * const p_api_ctrl, display_status_t * const status); 221 222 /*******************************************************************************************************************//** 223 * @} (end defgroup GLCDC) 224 **********************************************************************************************************************/ 225 226 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 227 FSP_FOOTER 228 229 #endif 230
