Searched refs:source_div (Results 1 – 6 of 6) sorted by relevance
746 FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_8); in r_agt_open_param_checking()747 FSP_ASSERT(p_cfg->source_div != TIMER_SOURCE_DIV_4); in r_agt_open_param_checking()752 FSP_ASSERT(p_cfg->source_div == TIMER_SOURCE_DIV_1); in r_agt_open_param_checking()757 FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128); in r_agt_open_param_checking()815 if (TIMER_SOURCE_DIV_1 != p_cfg->source_div) in r_agt_hardware_cfg()818 count_source_int = p_cfg->source_div ^ 2U; in r_agt_hardware_cfg()847 agtmr2 = p_cfg->source_div; in r_agt_hardware_cfg()
182 FSP_ASSERT(p_cfg->source_div <= 10U); in R_GPT_Open()184 FSP_ASSERT((p_cfg->source_div != 7U) && (p_cfg->source_div != 9U) && (p_cfg->source_div <= 10)); in R_GPT_Open()187 FSP_ASSERT((0U == (p_cfg->source_div % 2U)) && (p_cfg->source_div <= 10)); in R_GPT_Open()1252 uint32_t gtcr_tpcs = p_cfg->source_div >> BSP_FEATURE_GPT_TPCS_SHIFT; in gpt_hardware_initialize()
204 FSP_ASSERT(p_cfg->source_div <= 10U); in R_GPT_Open()206 FSP_ASSERT((p_cfg->source_div != 7U) && (p_cfg->source_div != 9U) && (p_cfg->source_div <= 10)); in R_GPT_Open()209 FSP_ASSERT((0U == (p_cfg->source_div % 2U)) && (p_cfg->source_div <= 10)); in R_GPT_Open()1312 uint32_t gtcr_tpcs = p_cfg->source_div >> BSP_FEATURE_GPT_TPCS_SHIFT; in gpt_hardware_initialize()
575 FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_128); in r_ulpt_open_param_checking()587 FSP_ASSERT(p_cfg->source_div <= TIMER_SOURCE_DIV_1); in r_ulpt_open_param_checking()653 ulptmr2 |= p_cfg->source_div & R_ULPT0_ULPTMR2_CKS_Msk; in r_ulpt_hardware_cfg()
166 timer_source_div_t source_div; ///< Source clock divider member
176 timer_source_div_t source_div; ///< Source clock divider member
