1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup BSP_MCU_RZN2L 9 * @{ 10 **********************************************************************************************************************/ 11 12 /** @} (end addtogroup BSP_MCU_RZN2L) */ 13 14 #ifndef BSP_OVERRIDE_H 15 #define BSP_OVERRIDE_H 16 17 /*********************************************************************************************************************** 18 * Includes <System Includes> , "Project Includes" 19 **********************************************************************************************************************/ 20 21 /* BSP Common Includes. */ 22 #include "bsp_common.h" 23 24 /* BSP MPU Specific Includes. */ 25 #include "bsp_register_protection.h" 26 #include "bsp_irq.h" 27 #include "bsp_io.h" 28 #include "bsp_clocks.h" 29 #include "bsp_module_stop.h" 30 #include "bsp_semaphore.h" 31 #include "bsp_reset.h" 32 #include "bsp_cache.h" 33 34 /* Factory MPU information. */ 35 #include "fsp_features.h" 36 37 /* BSP Common Includes (Other than bsp_common.h) */ 38 #include "bsp_delay.h" 39 #include "bsp_mcu_api.h" 40 41 /* BSP TFU Includes. */ 42 #if BSP_FEATURE_TFU_SUPPORTED 43 #include "bsp_tfu.h" 44 #endif 45 46 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 47 FSP_HEADER 48 49 /*********************************************************************************************************************** 50 * Macro definitions 51 **********************************************************************************************************************/ 52 53 /* Define overrides required for this MPU. */ 54 #define BSP_OVERRIDE_ADC_CHANNEL_T 55 #define BSP_OVERRIDE_CGC_CLOCK_T 56 #define BSP_OVERRIDE_CGC_PLL_CFG_T 57 #define BSP_OVERRIDE_CGC_DIVIDER_CFG_T 58 #define BSP_OVERRIDE_CGC_CLOCK_CHANGE_T 59 #define BSP_OVERRIDE_CGC_CLOCKS_CFG_T 60 #define BSP_OVERRIDE_ELC_PERIPHERAL_T 61 #define BSP_OVERRIDE_ERROR_EVENT_T 62 #define BSP_OVERRIDE_ETHER_EVENT_T 63 #define BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T 64 #define BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T 65 #define BSP_OVERRIDE_ETHER_SWITCH_CALLBACK_ARGS_T 66 #define BSP_OVERRIDE_POE3_STATE_T 67 #define BSP_OVERRIDE_POEG_STATE_T 68 #define BSP_OVERRIDE_POEG_TRIGGER_T 69 #define BSP_OVERRIDE_TRANSFER_MODE_T 70 #define BSP_OVERRIDE_TRANSFER_SIZE_T 71 #define BSP_OVERRIDE_TRANSFER_ADDR_MODE_T 72 #define BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T 73 #define BSP_OVERRIDE_TRANSFER_INFO_T 74 75 /* Override definitions. */ 76 77 #define ELC_PERIPHERAL_NUM (55U) 78 79 /* Private definition to set enumeration values. */ 80 #define IOPORT_P_OFFSET (0U) 81 #define IOPORT_PM_OFFSET (1U) 82 #define IOPORT_PMC_OFFSET (3U) 83 #define IOPORT_PFC_OFFSET (4U) 84 #define IOPORT_DRCTL_OFFSET (8U) 85 #define IOPORT_RSELP_OFFSET (14U) 86 87 /*********************************************************************************************************************** 88 * Typedef definitions 89 **********************************************************************************************************************/ 90 91 /*============================================== 92 * ADC API Overrides 93 *==============================================*/ 94 95 /** ADC channels */ 96 typedef enum e_adc_channel 97 { 98 ADC_CHANNEL_0 = 0, ///< ADC channel 0 99 ADC_CHANNEL_1 = 1, ///< ADC channel 1 100 ADC_CHANNEL_2 = 2, ///< ADC channel 2 101 ADC_CHANNEL_3 = 3, ///< ADC channel 3 102 ADC_CHANNEL_4 = 4, ///< ADC channel 4 103 ADC_CHANNEL_5 = 5, ///< ADC channel 5 104 ADC_CHANNEL_6 = 6, ///< ADC channel 6 105 ADC_CHANNEL_7 = 7, ///< ADC channel 7 106 ADC_CHANNEL_8 = 8, ///< ADC channel 8 107 ADC_CHANNEL_9 = 9, ///< ADC channel 9 108 ADC_CHANNEL_10 = 10, ///< ADC channel 10 109 ADC_CHANNEL_11 = 11, ///< ADC channel 11 110 ADC_CHANNEL_12 = 12, ///< ADC channel 12 111 ADC_CHANNEL_13 = 13, ///< ADC channel 13 112 ADC_CHANNEL_14 = 14, ///< ADC channel 14 113 ADC_CHANNEL_15 = 15, ///< ADC channel 15 114 ADC_CHANNEL_16 = 16, ///< ADC channel 16 115 ADC_CHANNEL_17 = 17, ///< ADC channel 17 116 ADC_CHANNEL_18 = 18, ///< ADC channel 18 117 ADC_CHANNEL_19 = 19, ///< ADC channel 19 118 ADC_CHANNEL_20 = 20, ///< ADC channel 20 119 ADC_CHANNEL_21 = 21, ///< ADC channel 21 120 ADC_CHANNEL_22 = 22, ///< ADC channel 22 121 ADC_CHANNEL_23 = 23, ///< ADC channel 23 122 ADC_CHANNEL_24 = 24, ///< ADC channel 24 123 ADC_CHANNEL_25 = 25, ///< ADC channel 25 124 ADC_CHANNEL_26 = 26, ///< ADC channel 26 125 ADC_CHANNEL_27 = 27, ///< ADC channel 27 126 ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A 127 ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B 128 ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register 129 ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output 130 ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage 131 ADC_CHANNEL_0_DSMIF_CAPTURE_A = 0x100, ///< ADC channel 0 Capture Current Data Register A 132 ADC_CHANNEL_0_DSMIF_CAPTURE_B = 0x200, ///< ADC channel 0 Capture Current Data Register B 133 ADC_CHANNEL_1_DSMIF_CAPTURE_A = 0x101, ///< ADC channel 1 Capture Current Data Register A 134 ADC_CHANNEL_1_DSMIF_CAPTURE_B = 0x201, ///< ADC channel 1 Capture Current Data Register B 135 ADC_CHANNEL_2_DSMIF_CAPTURE_A = 0x102, ///< ADC channel 2 Capture Current Data Register A 136 ADC_CHANNEL_2_DSMIF_CAPTURE_B = 0x202, ///< ADC channel 2 Capture Current Data Register B 137 } adc_channel_t; 138 139 /*============================================== 140 * CGC API Overrides 141 *==============================================*/ 142 143 /** Divider values of clock provided to xSPI */ 144 typedef enum e_cgc_fsel_xspi_clock_div 145 { 146 CGC_FSEL_XSPI_CLOCK_DIV_6 = 0x02, ///< XSPI_CLKn 133.3MHz (XSPI base clock divided by 3) 147 CGC_FSEL_XSPI_CLOCK_DIV_8 = 0x03, ///< XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4) 148 CGC_FSEL_XSPI_CLOCK_DIV_16 = 0x04, ///< XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4) 149 CGC_FSEL_XSPI_CLOCK_DIV_32 = 0x05, ///< XSPI_CLKn 25.0MHz (XSPI base clock divided by 3) 150 CGC_FSEL_XSPI_CLOCK_DIV_64 = 0x06, ///< XSPI_CLKn 12.5MHz (XSPI base clock divided by 3) 151 } cgc_fsel_xspi_clock_div_t; 152 153 /** Divider values of base clock generated for xSPI */ 154 typedef enum e_cgc_divsel_xspi_clock_div 155 { 156 CGC_DIVSEL_XSPI_CLOCK_DIV_3 = 0x00, ///< XSPI base clock divided by 3 157 CGC_DIVSEL_XSPI_CLOCK_DIV_4 = 0x01, ///< XSPI base clock divided by 4 158 } cgc_divsel_xspi_clock_div_t; 159 160 /** Clock output divider values */ 161 typedef enum e_cgc_clock_out_clock_div 162 { 163 CGC_CLOCK_OUT_CLOCK_DIV_2 = 0, ///< CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4) 164 CGC_CLOCK_OUT_CLOCK_DIV_3 = 1, ///< CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4) 165 CGC_CLOCK_OUT_CLOCK_DIV_4 = 2, ///< CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4) 166 CGC_CLOCK_OUT_CLOCK_DIV_5 = 3, ///< CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4) 167 CGC_CLOCK_OUT_CLOCK_DIV_6 = 4, ///< CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4) 168 CGC_CLOCK_OUT_CLOCK_DIV_7 = 5, ///< CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4) 169 CGC_CLOCK_OUT_CLOCK_DIV_8 = 6, ///< CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4) 170 } cgc_clock_out_clock_div_t; 171 172 /** CANFD clock divider values */ 173 typedef enum e_cgc_canfd_clock_div 174 { 175 CGC_CANFD_CLOCK_DIV_10 = 0, ///< CANFD clock 80.0MHz 176 CGC_CANFD_CLOCK_DIV_20 = 1, ///< CANFD clock 40.0MHz 177 } cgc_canfd_clock_div_t; 178 179 /** PHY clock source identifiers */ 180 typedef enum e_cgc_phy_clock 181 { 182 CGC_PHY_CLOCK_PLL1 = 0, ///< PLL1 divider clock 183 CGC_PHY_CLOCK_MAIN_OSC = 1, ///< Main clock oscillator 184 } cgc_phy_clock_t; 185 186 /** SPI asynchronous serial clock frequency */ 187 typedef enum e_cgc_spi_async_clock 188 { 189 CGC_SPI_ASYNC_CLOCK_75MHZ = 0, ///< SPI asynchronous serial clock 75MHz 190 CGC_SPI_ASYNC_CLOCK_96MHZ = 1, ///< SPI asynchronous serial clock 96MHz 191 } cgc_spi_async_clock_t; 192 193 /** SCI asynchronous serial clock frequency */ 194 typedef enum e_cgc_sci_async_clock 195 { 196 CGC_SCI_ASYNC_CLOCK_75MHZ = 0, ///< SCI asynchronous serial clock 75MHz 197 CGC_SCI_ASYNC_CLOCK_96MHZ = 1, ///< SCI asynchronous serial clock 96MHz 198 } cgc_sci_async_clock_t; 199 200 /** CPU clock divider values */ 201 typedef enum e_cgc_cpu_clock_div 202 { 203 CGC_CPU_CLOCK_DIV_2 = 0, ///< CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4) 204 CGC_CPU_CLOCK_DIV_1 = 1, ///< CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4) 205 } cgc_cpu_clock_div_t; 206 207 /** Base clock divider values */ 208 typedef enum e_cgc_baseclock_div 209 { 210 CGC_BASECLOCK_DIV_3 = 0, ///< Base clock divided by 3 (ICLK=200.0MHz etc.) 211 CGC_BASECLOCK_DIV_4 = 1, ///< Base clock divided by 4 (ICLK=150.0MHz etc.) 212 } cgc_baseclock_div_t; 213 214 /** System clock source identifiers */ 215 typedef enum e_cgc_clock 216 { 217 CGC_CLOCK_LOCO = 0, ///< The low speed on chip oscillator 218 CGC_CLOCK_PLL0 = 1, ///< The PLL0 oscillator 219 CGC_CLOCK_PLL1 = 2, ///< The PLL1 oscillator 220 } cgc_clock_t; 221 222 /** Clock configuration structure - Dummy definition because it is not used in this MPU. 223 * Set NULL as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ 224 typedef struct st_cgc_pll_cfg 225 { 226 uint32_t dummy; /* Dummy. */ 227 } cgc_pll_cfg_t; 228 229 /** Clock configuration structure */ 230 typedef struct st_cgc_divider_cfg 231 { 232 union 233 { 234 uint32_t sckcr_w; ///< System Clock Control Register 235 236 struct 237 { 238 cgc_fsel_xspi_clock_div_t fselxspi0 : 3; ///< Divider value for XSPI_CLK0 239 uint32_t : 3; 240 cgc_divsel_xspi_clock_div_t divselxspi0 : 1; ///< Divider base value for XSPI_CLK0 241 uint32_t : 1; 242 cgc_fsel_xspi_clock_div_t fselxspi1 : 3; ///< Divider value for XSPI_CLK1 243 uint32_t : 3; 244 cgc_divsel_xspi_clock_div_t divselxspi1 : 1; ///< Divider base value for XSPI_CLK1 245 uint32_t : 1; 246 cgc_clock_out_clock_div_t ckio_div : 3; ///< Divider value for CKIO 247 uint32_t : 1; 248 cgc_canfd_clock_div_t fselcanfd_div : 1; ///< Divider value for CANFD clock 249 cgc_phy_clock_t phy_sel : 1; ///< Ethernet PHY reference clock output 250 uint32_t : 2; 251 cgc_spi_async_clock_t spi0_async_sel : 1; ///< SPI0 asynchronous serial clock 252 cgc_spi_async_clock_t spi1_async_sel : 1; ///< SPI1 asynchronous serial clock 253 cgc_spi_async_clock_t spi2_async_sel : 1; ///< SPI2 asynchronous serial clock 254 cgc_sci_async_clock_t sci0_async_sel : 1; ///< SCI0 asynchronous serial clock 255 cgc_sci_async_clock_t sci1_async_sel : 1; ///< SCI1 asynchronous serial clock 256 cgc_sci_async_clock_t sci2_async_sel : 1; ///< SCI2 asynchronous serial clock 257 cgc_sci_async_clock_t sci3_async_sel : 1; ///< SCI3 asynchronous serial clock 258 cgc_sci_async_clock_t sci4_async_sel : 1; ///< SCI4 asynchronous serial clock 259 } sckcr_b; 260 }; 261 262 union 263 { 264 uint32_t sckcr2_w; ///< System Clock Control Register 2 265 266 struct 267 { 268 cgc_cpu_clock_div_t fsel0cr52 : 1; ///< Divider value for Cortex-R52 CPU0 269 uint32_t : 4; 270 cgc_baseclock_div_t div_sub_sel : 1; ///< Divider value for base clock 271 uint32_t : 18; 272 cgc_spi_async_clock_t spi3_async_sel : 1; ///< SPI3 asynchronous serial clock 273 cgc_sci_async_clock_t sci5_async_sel : 1; ///< SCI5 asynchronous serial clock 274 uint32_t : 6; 275 } sckcr2_b; 276 }; 277 } cgc_divider_cfg_t; 278 279 /** Clock options */ 280 typedef enum e_cgc_clock_change 281 { 282 CGC_CLOCK_CHANGE_START = 0, ///< Start the clock 283 CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock 284 CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock 285 } cgc_clock_change_t; 286 287 /** Clock configuration */ 288 typedef struct st_cgc_clocks_cfg 289 { 290 cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure 291 cgc_clock_change_t loco_state; ///< State of LOCO 292 cgc_clock_change_t pll1_state; ///< State of PLL1 293 } cgc_clocks_cfg_t; 294 295 /*============================================== 296 * ELC API Overrides 297 *==============================================*/ 298 299 /** Possible peripherals to be linked to event signals (not all available on all MPUs) */ 300 typedef enum e_elc_peripheral 301 { 302 ELC_PERIPHERAL_MTU0 = (0), 303 ELC_PERIPHERAL_MTU3 = (1), 304 ELC_PERIPHERAL_MTU4 = (2), 305 ELC_PERIPHERAL_LLPPGPT_A = (3), 306 ELC_PERIPHERAL_LLPPGPT_B = (4), 307 ELC_PERIPHERAL_LLPPGPT_C = (5), 308 ELC_PERIPHERAL_LLPPGPT_D = (6), 309 ELC_PERIPHERAL_LLPPGPT_E = (7), 310 ELC_PERIPHERAL_LLPPGPT_F = (8), 311 ELC_PERIPHERAL_LLPPGPT_G = (9), 312 ELC_PERIPHERAL_LLPPGPT_H = (10), 313 ELC_PERIPHERAL_NONSAFTYGPT_A = (11), 314 ELC_PERIPHERAL_NONSAFTYGPT_B = (12), 315 ELC_PERIPHERAL_NONSAFTYGPT_C = (13), 316 ELC_PERIPHERAL_NONSAFTYGPT_D = (14), 317 ELC_PERIPHERAL_NONSAFTYGPT_E = (15), 318 ELC_PERIPHERAL_NONSAFTYGPT_F = (16), 319 ELC_PERIPHERAL_NONSAFTYGPT_G = (17), 320 ELC_PERIPHERAL_NONSAFTYGPT_H = (18), 321 ELC_PERIPHERAL_ADC0_A = (19), 322 ELC_PERIPHERAL_ADC0_B = (20), 323 ELC_PERIPHERAL_ADC1_A = (21), 324 ELC_PERIPHERAL_ADC1_B = (22), 325 ELC_PERIPHERAL_DSMIF0_CAP0 = (23), 326 ELC_PERIPHERAL_DSMIF0_CAP1 = (24), 327 ELC_PERIPHERAL_DSMIF0_CAP2 = (25), 328 ELC_PERIPHERAL_DSMIF0_CAP3 = (26), 329 ELC_PERIPHERAL_DSMIF0_CAP4 = (27), 330 ELC_PERIPHERAL_DSMIF0_CAP5 = (28), 331 ELC_PERIPHERAL_DSMIF0_CDCNT0 = (29), 332 ELC_PERIPHERAL_DSMIF0_CDCNT1 = (30), 333 ELC_PERIPHERAL_DSMIF0_CDCNT2 = (31), 334 ELC_PERIPHERAL_DSMIF1_CAP0 = (32), 335 ELC_PERIPHERAL_DSMIF1_CAP1 = (33), 336 ELC_PERIPHERAL_DSMIF1_CAP2 = (34), 337 ELC_PERIPHERAL_DSMIF1_CAP3 = (35), 338 ELC_PERIPHERAL_DSMIF1_CAP4 = (36), 339 ELC_PERIPHERAL_DSMIF1_CAP5 = (37), 340 ELC_PERIPHERAL_DSMIF1_CDCNT0 = (38), 341 ELC_PERIPHERAL_DSMIF1_CDCNT1 = (39), 342 ELC_PERIPHERAL_DSMIF1_CDCNT2 = (40), 343 ELC_PERIPHERAL_ESC0 = (43), 344 ELC_PERIPHERAL_ESC1 = (44), 345 ELC_PERIPHERAL_GMA0 = (45), 346 ELC_PERIPHERAL_GMA1 = (46), 347 ELC_PERIPHERAL_OUTPORTGR1 = (47), 348 ELC_PERIPHERAL_OUTPORTGR2 = (48), 349 ELC_PERIPHERAL_INPORTGR1 = (49), 350 ELC_PERIPHERAL_INPORTGR2 = (50), 351 ELC_PERIPHERAL_SINGLEPORT0 = (51), 352 ELC_PERIPHERAL_SINGLEPORT1 = (52), 353 ELC_PERIPHERAL_SINGLEPORT2 = (53), 354 ELC_PERIPHERAL_SINGLEPORT3 = (54), 355 } elc_peripheral_t; 356 357 /*============================================== 358 * ERROR API Overrides 359 *==============================================*/ 360 361 /** Error event source. */ 362 typedef enum e_error_event 363 { 364 ERROR_EVENT_CPU0, ///< Error event from CPU0 365 ERROR_EVENT_PERIPHERAL_0, ///< Error event from Peripheral 0 366 ERROR_EVENT_PERIPHERAL_1, ///< Error event from Peripheral 1 367 } error_event_t; 368 369 /*============================================== 370 * ETHER API Overrides 371 *==============================================*/ 372 373 /** Event code of callback function */ 374 typedef enum e_ether_event 375 { 376 ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event 377 ETHER_EVENT_LINK_ON, ///< Link up detection event 378 ETHER_EVENT_LINK_OFF, ///< Link down detection event 379 ETHER_EVENT_SBD_INTERRUPT, ///< SBD Interrupt event 380 ETHER_EVENT_PMT_INTERRUPT ///< PMT Interrupt event 381 } ether_event_t; 382 383 /** Ether Callback function parameter data */ 384 typedef struct st_ether_callback_args 385 { 386 uint32_t channel; ///< Device channel number 387 ether_event_t event; ///< Event code 388 389 uint32_t status_ether; ///< Interrupt status of SDB or PMT 390 uint32_t status_link; ///< Link status 391 392 void const * p_context; ///< Placeholder for user data. 393 } ether_callback_args_t; 394 395 /*============================================== 396 * ETHER PHY API Overrides 397 *==============================================*/ 398 399 /** Phy LSI */ 400 typedef enum e_ether_phy_lsi_type 401 { 402 ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. 403 ETHER_PHY_LSI_TYPE_VSC8541 = 1, ///< Select configuration forVSC8541 404 ETHER_PHY_LSI_TYPE_KSZ9131 = 2, ///< Select configuration forKSZ9131 405 ETHER_PHY_LSI_TYPE_KSZ9031 = 3, ///< Select configuration forKSZ9031 406 ETHER_PHY_LSI_TYPE_KSZ8081 = 4, ///< Select configuration forKSZ8081 407 ETHER_PHY_LSI_TYPE_KSZ8041 = 5, ///< Select configuration forKSZ8041 408 ETHER_PHY_LSI_TYPE_CUSTOM = 0xFFU, ///< Select configuration for User custom. 409 } ether_phy_lsi_type_t; 410 411 /*============================================== 412 * ETHER SWITCH API Overrides 413 *==============================================*/ 414 415 /** Ether Switch Event code of callback function */ 416 typedef enum e_ether_switch_event 417 { 418 ETHER_SWITCH_EVENT_LINK_CHANGE ///< Change Link status 419 } ether_switch_event_t; 420 421 /** Ether Switch Callback function parameter data */ 422 typedef struct st_ether_switch_callback_args 423 { 424 uint32_t channel; ///< Device channel number 425 ether_switch_event_t event; ///< Event code 426 427 uint32_t status_link; ///< Link status bit0:port0. bit1:port1. bit2:port2, bit3:port3 428 429 void const * p_context; ///< Placeholder for user data. 430 } ether_switch_callback_args_t; 431 432 /*============================================== 433 * IOPORT API Overrides 434 *==============================================*/ 435 436 /** Superset of all peripheral functions. */ 437 typedef enum e_ioport_pin_pfc 438 { 439 IOPORT_PIN_P000_PFC_00_ETH2_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_0 / ETHER_ETHn / ETH2_RXD3 440 IOPORT_PIN_P000_PFC_02_D15 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_0 / BSC / D15 441 IOPORT_PIN_P000_PFC_03_SCK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / SCK2 442 IOPORT_PIN_P000_PFC_04_DE2 = (0x04U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / DE2 443 IOPORT_PIN_P000_PFC_05_HD15 = (0x05U << IOPORT_PFC_OFFSET), ///< P00_0 / PHOSTIF / HD15 444 IOPORT_PIN_P001_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_1 / IRQ / IRQ0 445 IOPORT_PIN_P001_PFC_01_ETH2_RXDV = (0x01U << IOPORT_PFC_OFFSET), ///< P00_1 / ETHER_ETHn / ETH2_RXDV 446 IOPORT_PIN_P001_PFC_03_A13 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_1 / BSC / A13 447 IOPORT_PIN_P001_PFC_04_MTIC5U = (0x04U << IOPORT_PFC_OFFSET), ///< P00_1 / MTU3n / MTIC5U 448 IOPORT_PIN_P001_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P00_1 / SCIn / RXD2_SCL2_MISO2 449 IOPORT_PIN_P002_PFC_00_ETH2_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P00_2 / ETHER_ETHn / ETH2_TXEN 450 IOPORT_PIN_P002_PFC_02_RD = (0x02U << IOPORT_PFC_OFFSET), ///< P00_2 / BSC / RD 451 IOPORT_PIN_P002_PFC_03_MTIC5V = (0x03U << IOPORT_PFC_OFFSET), ///< P00_2 / MTU3n / MTIC5V 452 IOPORT_PIN_P002_PFC_04_TXD2_SDA2_MOSI2 = (0x04U << IOPORT_PFC_OFFSET), ///< P00_2 / SCIn / TXD2_SDA2_MOSI2 453 IOPORT_PIN_P002_PFC_05_USB_OVRCUR = (0x05U << IOPORT_PFC_OFFSET), ///< P00_2 / USB_HS / USB_OVRCUR 454 IOPORT_PIN_P003_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_3 / IRQ / IRQ1 455 IOPORT_PIN_P003_PFC_01_ETH2_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / ETH2_REFCLK 456 IOPORT_PIN_P003_PFC_02_RMII2_REFCLK = (0x02U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / RMII2_REFCLK 457 IOPORT_PIN_P003_PFC_04_RD_WR = (0x04U << IOPORT_PFC_OFFSET), ///< P00_3 / BSC / RD_WR 458 IOPORT_PIN_P003_PFC_05_MTIC5W = (0x05U << IOPORT_PFC_OFFSET), ///< P00_3 / MTU3n / MTIC5W 459 IOPORT_PIN_P003_PFC_06_SS2_CTS2_RTS2 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_3 / SCIn / SS2_CTS2_RTS2 460 IOPORT_PIN_P004_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_4 / IRQ / IRQ13 461 IOPORT_PIN_P004_PFC_01_ETH2_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P00_4 / ETHER_ETHn / ETH2_RXER 462 IOPORT_PIN_P004_PFC_03_WAIT = (0x03U << IOPORT_PFC_OFFSET), ///< P00_4 / BSC / WAIT 463 IOPORT_PIN_P004_PFC_04_MTIOC3A = (0x04U << IOPORT_PFC_OFFSET), ///< P00_4 / MTU3n / MTIOC3A 464 IOPORT_PIN_P004_PFC_05_GTIOC0A = (0x05U << IOPORT_PFC_OFFSET), ///< P00_4 / GPTn / GTIOC0A 465 IOPORT_PIN_P004_PFC_06_MCLK0 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_4 / DSMIFn / MCLK0 466 IOPORT_PIN_P004_PFC_07_HWAIT = (0x07U << IOPORT_PFC_OFFSET), ///< P00_4 / PHOSTIF / HWAIT 467 IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK2 468 IOPORT_PIN_P005_PFC_02_CS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_5 / BSC / CS0 469 IOPORT_PIN_P005_PFC_03_ESC_PHYLINK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK2 470 IOPORT_PIN_P005_PFC_04_MTIOC3C = (0x04U << IOPORT_PFC_OFFSET), ///< P00_5 / MTU3n / MTIOC3C 471 IOPORT_PIN_P005_PFC_05_GTIOC0B = (0x05U << IOPORT_PFC_OFFSET), ///< P00_5 / GPTn / GTIOC0B 472 IOPORT_PIN_P005_PFC_06_MDAT0 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_5 / DSMIFn / MDAT0 473 IOPORT_PIN_P005_PFC_07_ETHSW_PHYLINK0 = (0x07U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK0 474 IOPORT_PIN_P005_PFC_08_ESC_PHYLINK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK0 475 IOPORT_PIN_P006_PFC_00_ETH2_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P00_6 / ETHER_ETHn / ETH2_TXCLK 476 IOPORT_PIN_P006_PFC_01_CS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P00_6 / BSC / CS5 477 IOPORT_PIN_P006_PFC_02_MTIOC3B = (0x02U << IOPORT_PFC_OFFSET), ///< P00_6 / MTU3n / MTIOC3B 478 IOPORT_PIN_P006_PFC_03_GTIOC1A = (0x03U << IOPORT_PFC_OFFSET), ///< P00_6 / GPTn / GTIOC1A 479 IOPORT_PIN_P007_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_7 / IRQ / IRQ13 480 IOPORT_PIN_P007_PFC_01_RAS = (0x01U << IOPORT_PFC_OFFSET), ///< P00_7 / BSC / RAS 481 IOPORT_PIN_P007_PFC_02_MTIOC4A = (0x02U << IOPORT_PFC_OFFSET), ///< P00_7 / MTU3n / MTIOC4A 482 IOPORT_PIN_P007_PFC_03_GTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P00_7 / GPTn / GTIOC2A 483 IOPORT_PIN_P010_PFC_00_GMAC_MDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_GMAC / GMAC_MDIO 484 IOPORT_PIN_P010_PFC_01_ETHSW_MDIO = (0x01U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ETHSW / ETHSW_MDIO 485 IOPORT_PIN_P010_PFC_02_CAS = (0x02U << IOPORT_PFC_OFFSET), ///< P01_0 / BSC / CAS 486 IOPORT_PIN_P010_PFC_03_ESC_MDIO = (0x03U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ESC / ESC_MDIO 487 IOPORT_PIN_P010_PFC_04_MTIOC4C = (0x04U << IOPORT_PFC_OFFSET), ///< P01_0 / MTU3n / MTIOC4C 488 IOPORT_PIN_P010_PFC_05_GTIOC3A = (0x05U << IOPORT_PFC_OFFSET), ///< P01_0 / GPTn / GTIOC3A 489 IOPORT_PIN_P010_PFC_06_CTS2 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_0 / SCIn / CTS2 490 IOPORT_PIN_P010_PFC_07_MCLK1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_0 / DSMIFn / MCLK1 491 IOPORT_PIN_P011_PFC_00_GMAC_MDC = (0x00U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_GMAC / GMAC_MDC 492 IOPORT_PIN_P011_PFC_01_ETHSW_MDC = (0x01U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ETHSW / ETHSW_MDC 493 IOPORT_PIN_P011_PFC_02_CKE = (0x02U << IOPORT_PFC_OFFSET), ///< P01_1 / BSC / CKE 494 IOPORT_PIN_P011_PFC_03_ESC_MDC = (0x03U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ESC / ESC_MDC 495 IOPORT_PIN_P011_PFC_04_MTIOC3D = (0x04U << IOPORT_PFC_OFFSET), ///< P01_1 / MTU3n / MTIOC3D 496 IOPORT_PIN_P011_PFC_05_GTIOC1B = (0x05U << IOPORT_PFC_OFFSET), ///< P01_1 / GPTn / GTIOC1B 497 IOPORT_PIN_P011_PFC_06_DE2 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_1 / SCIn / DE2 498 IOPORT_PIN_P011_PFC_07_MDAT1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_1 / DSMIFn / MDAT1 499 IOPORT_PIN_P012_PFC_00_IRQ2 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_2 / IRQ / IRQ2 500 IOPORT_PIN_P012_PFC_01_ETH2_TXD3 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_2 / ETHER_ETHn / ETH2_TXD3 501 IOPORT_PIN_P012_PFC_02_CS2 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_2 / BSC / CS2 502 IOPORT_PIN_P012_PFC_03_MTIOC4B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_2 / MTU3n / MTIOC4B 503 IOPORT_PIN_P012_PFC_04_GTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P01_2 / GPTn / GTIOC2B 504 IOPORT_PIN_P013_PFC_00_ETH2_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_3 / ETHER_ETHn / ETH2_TXD2 505 IOPORT_PIN_P013_PFC_01_AH = (0x01U << IOPORT_PFC_OFFSET), ///< P01_3 / BSC / AH 506 IOPORT_PIN_P013_PFC_02_MTIOC4D = (0x02U << IOPORT_PFC_OFFSET), ///< P01_3 / MTU3n / MTIOC4D 507 IOPORT_PIN_P013_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_3 / GPTn / GTIOC3B 508 IOPORT_PIN_P014_PFC_00_IRQ3 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_4 / IRQ / IRQ3 509 IOPORT_PIN_P014_PFC_01_ETH2_TXD1 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_4 / ETHER_ETHn / ETH2_TXD1 510 IOPORT_PIN_P014_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P01_4 / BSC / WE1_DQMLU 511 IOPORT_PIN_P014_PFC_03_POE0 = (0x03U << IOPORT_PFC_OFFSET), ///< P01_4 / MTU_POE3 / POE0 512 IOPORT_PIN_P015_PFC_00_ETH2_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_5 / ETHER_ETHn / ETH2_TXD0 513 IOPORT_PIN_P015_PFC_01_WE0_DQMLL = (0x01U << IOPORT_PFC_OFFSET), ///< P01_5 / BSC / WE0_DQMLL 514 IOPORT_PIN_P016_PFC_00_GMAC_PTPTRG1 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_GMAC / GMAC_PTPTRG1 515 IOPORT_PIN_P016_PFC_01_TRACEDATA0 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_6 / TRACE / TRACEDATA0 516 IOPORT_PIN_P016_PFC_02_A20 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_6 / BSC / A20 517 IOPORT_PIN_P016_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH1 518 IOPORT_PIN_P016_PFC_04_ESC_LATCH0 = (0x04U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH0 519 IOPORT_PIN_P016_PFC_05_MTIOC1A = (0x05U << IOPORT_PFC_OFFSET), ///< P01_6 / MTU3n / MTIOC1A 520 IOPORT_PIN_P016_PFC_06_GTIOC9A = (0x06U << IOPORT_PFC_OFFSET), ///< P01_6 / GPTn / GTIOC9A 521 IOPORT_PIN_P016_PFC_07_CTS1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_6 / SCIn / CTS1 522 IOPORT_PIN_P016_PFC_08_CANTXDP1 = (0x08U << IOPORT_PFC_OFFSET), ///< P01_6 / CANFDn / CANTXDP1 523 IOPORT_PIN_P016_PFC_0A_HA20 = (0x0AU << IOPORT_PFC_OFFSET), ///< P01_6 / PHOSTIF / HA20 524 IOPORT_PIN_P017_PFC_00_ETHSW_LPI1 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_7 / ETHER_ETHSW / ETHSW_LPI1 525 IOPORT_PIN_P017_PFC_01_TRACEDATA1 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_7 / TRACE / TRACEDATA1 526 IOPORT_PIN_P017_PFC_02_A19 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_7 / BSC / A19 527 IOPORT_PIN_P017_PFC_03_MTIOC1B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_7 / MTU3n / MTIOC1B 528 IOPORT_PIN_P017_PFC_04_GTIOC9B = (0x04U << IOPORT_PFC_OFFSET), ///< P01_7 / GPTn / GTIOC9B 529 IOPORT_PIN_P017_PFC_05_ADTRG0 = (0x05U << IOPORT_PFC_OFFSET), ///< P01_7 / ADCn / ADTRG0 530 IOPORT_PIN_P017_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_7 / SCIn / SCK1 531 IOPORT_PIN_P017_PFC_07_SPI_RSPCK3 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_7 / SPIn / SPI_RSPCK3 532 IOPORT_PIN_P017_PFC_08_CANRX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P01_7 / CANFDn / CANRX0 533 IOPORT_PIN_P017_PFC_0A_HA19 = (0x0AU << IOPORT_PFC_OFFSET), ///< P01_7 / PHOSTIF / HA19 534 IOPORT_PIN_P020_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_0 / IRQ / IRQ4 535 IOPORT_PIN_P020_PFC_01_ETHSW_LPI2 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_0 / ETHER_ETHSW / ETHSW_LPI2 536 IOPORT_PIN_P020_PFC_02_TRACEDATA2 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_0 / TRACE / TRACEDATA2 537 IOPORT_PIN_P020_PFC_03_A18 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_0 / BSC / A18 538 IOPORT_PIN_P020_PFC_04_GTADSML0 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_0 / GPT / GTADSML0 539 IOPORT_PIN_P020_PFC_05_RXD1_SCL1_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_0 / SCIn / RXD1_SCL1_MISO1 540 IOPORT_PIN_P020_PFC_06_SPI_MISO3 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_0 / SPIn / SPI_MISO3 541 IOPORT_PIN_P020_PFC_07_CANTX1 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_0 / CANFDn / CANTX1 542 IOPORT_PIN_P020_PFC_08_USB_OTGID = (0x08U << IOPORT_PFC_OFFSET), ///< P02_0 / USB_HS / USB_OTGID 543 IOPORT_PIN_P020_PFC_0A_HA18 = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_0 / PHOSTIF / HA18 544 IOPORT_PIN_P021_PFC_00_ETHSW_PTPOUT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ETHSW / ETHSW_PTPOUT1 545 IOPORT_PIN_P021_PFC_01_A17 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_1 / BSC / A17 546 IOPORT_PIN_P021_PFC_02_ESC_SYNC1 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC1 547 IOPORT_PIN_P021_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC0 548 IOPORT_PIN_P021_PFC_04_DE1 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_1 / SCIn / DE1 549 IOPORT_PIN_P021_PFC_05_HA17 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_1 / PHOSTIF / HA17 550 IOPORT_PIN_P022_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_2 / IRQ / IRQ14 551 IOPORT_PIN_P022_PFC_01_ETHSW_TDMAOUT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_2 / ETHER_ETHSW / ETHSW_TDMAOUT0 552 IOPORT_PIN_P022_PFC_02_A16 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_2 / BSC / A16 553 IOPORT_PIN_P022_PFC_03_MTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU3n / MTIOC2A 554 IOPORT_PIN_P022_PFC_04_GTIOC10A = (0x04U << IOPORT_PFC_OFFSET), ///< P02_2 / GPTn / GTIOC10A 555 IOPORT_PIN_P022_PFC_05_POE10 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU_POE3 / POE10 556 IOPORT_PIN_P022_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_2 / SCIn / TXD1_SDA1_MOSI1 557 IOPORT_PIN_P022_PFC_07_SPI_MOSI3 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_2 / SPIn / SPI_MOSI3 558 IOPORT_PIN_P022_PFC_08_CANTX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P02_2 / CANFDn / CANTX0 559 IOPORT_PIN_P022_PFC_0A_RTCAT1HZ = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_2 / RTC / RTCAT1HZ 560 IOPORT_PIN_P022_PFC_0B_HA16 = (0x0BU << IOPORT_PFC_OFFSET), ///< P02_2 / PHOSTIF / HA16 561 IOPORT_PIN_P023_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_3 / IRQ / IRQ15 562 IOPORT_PIN_P023_PFC_01_ETHSW_TDMAOUT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_3 / ETHER_ETHSW / ETHSW_TDMAOUT1 563 IOPORT_PIN_P023_PFC_02_A15 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / A15 564 IOPORT_PIN_P023_PFC_03_AH = (0x03U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / AH 565 IOPORT_PIN_P023_PFC_04_MTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU3n / MTIOC2B 566 IOPORT_PIN_P023_PFC_05_GTIOC10B = (0x05U << IOPORT_PFC_OFFSET), ///< P02_3 / GPTn / GTIOC10B 567 IOPORT_PIN_P023_PFC_06_POE11 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU_POE3 / POE11 568 IOPORT_PIN_P023_PFC_07_SS1_CTS1_RTS1 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_3 / SCIn / SS1_CTS1_RTS1 569 IOPORT_PIN_P023_PFC_08_SPI_SSL30 = (0x08U << IOPORT_PFC_OFFSET), ///< P02_3 / SPIn / SPI_SSL30 570 IOPORT_PIN_P023_PFC_09_CANRX1 = (0x09U << IOPORT_PFC_OFFSET), ///< P02_3 / CANFDn / CANRX1 571 IOPORT_PIN_P023_PFC_0B_HA15 = (0x0BU << IOPORT_PFC_OFFSET), ///< P02_3 / PHOSTIF / HA15 572 IOPORT_PIN_P024_PFC_00_TDO = (0x00U << IOPORT_PFC_OFFSET), ///< P02_4 / JTAG/SWD / TDO 573 IOPORT_PIN_P024_PFC_01_WE0_DQMLL = (0x01U << IOPORT_PFC_OFFSET), ///< P02_4 / BSC / WE0_DQMLL 574 IOPORT_PIN_P024_PFC_02_DE1 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_4 / SCIn / DE1 575 IOPORT_PIN_P024_PFC_03_SPI_SSL33 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_4 / SPIn / SPI_SSL33 576 IOPORT_PIN_P025_PFC_00_ETHSW_TDMAOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_5 / ETHER_ETHSW / ETHSW_TDMAOUT3 577 IOPORT_PIN_P025_PFC_01_TDI = (0x01U << IOPORT_PFC_OFFSET), ///< P02_5 / JTAG/SWD / TDI 578 IOPORT_PIN_P025_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P02_5 / BSC / WE1_DQMLU 579 IOPORT_PIN_P025_PFC_03_SCK5 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_5 / SCIn / SCK5 580 IOPORT_PIN_P025_PFC_04_SPI_SSL31 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_5 / SPIn / SPI_SSL31 581 IOPORT_PIN_P026_PFC_00_TMS_SWDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P02_6 / JTAG/SWD / TMS_SWDIO 582 IOPORT_PIN_P026_PFC_01_RXD5_SCL5_MISO5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_6 / SCIn / RXD5_SCL5_MISO5 583 IOPORT_PIN_P027_PFC_00_TCK_SWCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P02_7 / JTAG/SWD / TCK_SWCLK 584 IOPORT_PIN_P027_PFC_01_TXD5_SDA5_MOSI5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_7 / SCIn / TXD5_SDA5_MOSI5 585 IOPORT_PIN_P030_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_0 / IRQ / IRQ14 586 IOPORT_PIN_P030_PFC_01_TRACEDATA3 = (0x01U << IOPORT_PFC_OFFSET), ///< P03_0 / TRACE / TRACEDATA3 587 IOPORT_PIN_P030_PFC_02_A14 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / A14 588 IOPORT_PIN_P030_PFC_03_CS5 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / CS5 589 IOPORT_PIN_P030_PFC_04_GTADSML1 = (0x04U << IOPORT_PFC_OFFSET), ///< P03_0 / GPT / GTADSML1 590 IOPORT_PIN_P030_PFC_05_SCK2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_0 / SCIn / SCK2 591 IOPORT_PIN_P030_PFC_06_SPI_SSL32 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_0 / SPIn / SPI_SSL32 592 IOPORT_PIN_P030_PFC_07_CANTXDP1 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_0 / CANFDn / CANTXDP1 593 IOPORT_PIN_P030_PFC_09_HA14 = (0x09U << IOPORT_PFC_OFFSET), ///< P03_0 / PHOSTIF / HA14 594 IOPORT_PIN_P035_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_5 / IRQ / IRQ5 595 IOPORT_PIN_P035_PFC_01_ETH2_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P03_5 / ETHER_ETHn / ETH2_CRS 596 IOPORT_PIN_P035_PFC_02_A12 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_5 / BSC / A12 597 IOPORT_PIN_P035_PFC_03_MTIOC3A = (0x03U << IOPORT_PFC_OFFSET), ///< P03_5 / MTU3n / MTIOC3A 598 IOPORT_PIN_P035_PFC_04_GTIOC4A = (0x04U << IOPORT_PFC_OFFSET), ///< P03_5 / GPTn / GTIOC4A 599 IOPORT_PIN_P035_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_5 / SCIn / RXD2_SCL2_MISO2 600 IOPORT_PIN_P035_PFC_06_MCLK2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_5 / DSMIFn / MCLK2 601 IOPORT_PIN_P035_PFC_07_HA12 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_5 / PHOSTIF / HA12 602 IOPORT_PIN_P036_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_6 / IRQ / IRQ8 603 IOPORT_PIN_P036_PFC_01_ETH2_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P03_6 / ETHER_ETHn / ETH2_COL 604 IOPORT_PIN_P036_PFC_02_TRACEDATA4 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_6 / TRACE / TRACEDATA4 605 IOPORT_PIN_P036_PFC_03_A11 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_6 / BSC / A11 606 IOPORT_PIN_P036_PFC_04_MTIOC3B = (0x04U << IOPORT_PFC_OFFSET), ///< P03_6 / MTU3n / MTIOC3B 607 IOPORT_PIN_P036_PFC_05_GTIOC4B = (0x05U << IOPORT_PFC_OFFSET), ///< P03_6 / GPTn / GTIOC4B 608 IOPORT_PIN_P036_PFC_06_TXD2_SDA2_MOSI2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_6 / SCIn / TXD2_SDA2_MOSI2 609 IOPORT_PIN_P036_PFC_07_SPI_SSL13 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_6 / SPIn / SPI_SSL13 610 IOPORT_PIN_P036_PFC_08_MDAT2 = (0x08U << IOPORT_PFC_OFFSET), ///< P03_6 / DSMIFn / MDAT2 611 IOPORT_PIN_P036_PFC_09_HA11 = (0x09U << IOPORT_PFC_OFFSET), ///< P03_6 / PHOSTIF / HA11 612 IOPORT_PIN_P037_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_7 / IRQ / IRQ9 613 IOPORT_PIN_P037_PFC_01_ETH2_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P03_7 / ETHER_ETHn / ETH2_TXER 614 IOPORT_PIN_P037_PFC_02_TRACEDATA5 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_7 / TRACE / TRACEDATA5 615 IOPORT_PIN_P037_PFC_03_A10 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_7 / BSC / A10 616 IOPORT_PIN_P037_PFC_04_MTIOC3C = (0x04U << IOPORT_PFC_OFFSET), ///< P03_7 / MTU3n / MTIOC3C 617 IOPORT_PIN_P037_PFC_05_GTIOC5A = (0x05U << IOPORT_PFC_OFFSET), ///< P03_7 / GPTn / GTIOC5A 618 IOPORT_PIN_P037_PFC_06_SCK3 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_7 / SCIn / SCK3 619 IOPORT_PIN_P037_PFC_07_HA10 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_7 / PHOSTIF / HA10 620 IOPORT_PIN_P040_PFC_00_TRACEDATA6 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_0 / TRACE / TRACEDATA6 621 IOPORT_PIN_P040_PFC_01_A9 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_0 / BSC / A9 622 IOPORT_PIN_P040_PFC_02_MTIOC3D = (0x02U << IOPORT_PFC_OFFSET), ///< P04_0 / MTU3n / MTIOC3D 623 IOPORT_PIN_P040_PFC_03_GTIOC5B = (0x03U << IOPORT_PFC_OFFSET), ///< P04_0 / GPTn / GTIOC5B 624 IOPORT_PIN_P040_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_0 / SCIn / RXD3_SCL3_MISO3 625 IOPORT_PIN_P040_PFC_05_HA9 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_0 / PHOSTIF / HA9 626 IOPORT_PIN_P041_PFC_00_CKIO = (0x00U << IOPORT_PFC_OFFSET), ///< P04_1 / BSC / CKIO 627 IOPORT_PIN_P041_PFC_01_TXD3_SDA3_MOSI3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_1 / SCIn / TXD3_SDA3_MOSI3 628 IOPORT_PIN_P041_PFC_02_SPI_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_1 / SPIn / SPI_MOSI0 629 IOPORT_PIN_P041_PFC_03_IIC_SDA2 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_1 / IICn / IIC_SDA2 630 IOPORT_PIN_P041_PFC_04_HCKIO = (0x04U << IOPORT_PFC_OFFSET), ///< P04_1 / PHOSTIF / HCKIO 631 IOPORT_PIN_P044_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_4 / IRQ / IRQ10 632 IOPORT_PIN_P044_PFC_01_TRACEDATA7 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_4 / TRACE / TRACEDATA7 633 IOPORT_PIN_P044_PFC_02_A8 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_4 / BSC / A8 634 IOPORT_PIN_P044_PFC_03_GTADSMP0 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_4 / GPT / GTADSMP0 635 IOPORT_PIN_P044_PFC_04_POE10 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_4 / MTU_POE3 / POE10 636 IOPORT_PIN_P044_PFC_05_CTS3 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_4 / SCIn / CTS3 637 IOPORT_PIN_P044_PFC_06_SPI_RSPCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P04_4 / SPIn / SPI_RSPCK1 638 IOPORT_PIN_P044_PFC_08_HA8 = (0x08U << IOPORT_PFC_OFFSET), ///< P04_4 / PHOSTIF / HA8 639 IOPORT_PIN_P045_PFC_00_A7 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_5 / BSC / A7 640 IOPORT_PIN_P045_PFC_01_DE3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_5 / SCIn / DE3 641 IOPORT_PIN_P045_PFC_02_ETHSW_PTPOUT0 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ETHSW / ETHSW_PTPOUT0 642 IOPORT_PIN_P045_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ESC / ESC_SYNC0 643 IOPORT_PIN_P045_PFC_04_ESC_SYNC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ESC / ESC_SYNC1 644 IOPORT_PIN_P045_PFC_05_HA7 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_5 / PHOSTIF / HA7 645 IOPORT_PIN_P046_PFC_00_ETH1_TXER = (0x00U << IOPORT_PFC_OFFSET), ///< P04_6 / ETHER_ETHn / ETH1_TXER 646 IOPORT_PIN_P046_PFC_01_A6 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_6 / BSC / A6 647 IOPORT_PIN_P046_PFC_02_DACK = (0x02U << IOPORT_PFC_OFFSET), ///< P04_6 / DMAC / DACK 648 IOPORT_PIN_P046_PFC_03_RTCAT1HZ = (0x03U << IOPORT_PFC_OFFSET), ///< P04_6 / RTC / RTCAT1HZ 649 IOPORT_PIN_P046_PFC_04_HA6 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_6 / PHOSTIF / HA6 650 IOPORT_PIN_P047_PFC_00_ETH0_TXER = (0x00U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH0_TXER 651 IOPORT_PIN_P047_PFC_01_A5 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_7 / BSC / A5 652 IOPORT_PIN_P047_PFC_02_SPI_SSL21 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_7 / SPIn / SPI_SSL21 653 IOPORT_PIN_P047_PFC_03_ETH2_TXER = (0x03U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH2_TXER 654 IOPORT_PIN_P047_PFC_04_HA5 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_7 / PHOSTIF / HA5 655 IOPORT_PIN_P050_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_0 / IRQ / IRQ12 656 IOPORT_PIN_P050_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P05_0 / ETHER_ETHn / ETH1_CRS 657 IOPORT_PIN_P050_PFC_02_A4 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_0 / BSC / A4 658 IOPORT_PIN_P050_PFC_03_MTIOC4A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_0 / MTU3n / MTIOC4A 659 IOPORT_PIN_P050_PFC_04_GTIOC6A = (0x04U << IOPORT_PFC_OFFSET), ///< P05_0 / GPTn / GTIOC6A 660 IOPORT_PIN_P050_PFC_05_CMTW0_TOC0 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_0 / CMTWn / CMTW0_TOC0 661 IOPORT_PIN_P050_PFC_06_SS5_CTS5_RTS5 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_0 / SCIn / SS5_CTS5_RTS5 662 IOPORT_PIN_P050_PFC_07_CANTXDP0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_0 / CANFDn / CANTXDP0 663 IOPORT_PIN_P050_PFC_08_USB_VBUSEN = (0x08U << IOPORT_PFC_OFFSET), ///< P05_0 / USB_HS / USB_VBUSEN 664 IOPORT_PIN_P050_PFC_09_MCLK3 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_0 / DSMIFn / MCLK3 665 IOPORT_PIN_P050_PFC_0B_HA4 = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_0 / PHOSTIF / HA4 666 IOPORT_PIN_P051_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_1 / IRQ / IRQ13 667 IOPORT_PIN_P051_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P05_1 / ETHER_ETHn / ETH1_COL 668 IOPORT_PIN_P051_PFC_02_A3 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_1 / BSC / A3 669 IOPORT_PIN_P051_PFC_03_MTIOC4B = (0x03U << IOPORT_PFC_OFFSET), ///< P05_1 / MTU3n / MTIOC4B 670 IOPORT_PIN_P051_PFC_04_GTIOC6B = (0x04U << IOPORT_PFC_OFFSET), ///< P05_1 / GPTn / GTIOC6B 671 IOPORT_PIN_P051_PFC_05_CMTW0_TIC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_1 / CMTWn / CMTW0_TIC1 672 IOPORT_PIN_P051_PFC_06_CTS5 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_1 / SCIn / CTS5 673 IOPORT_PIN_P051_PFC_07_CANRXDP0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_1 / CANFDn / CANRXDP0 674 IOPORT_PIN_P051_PFC_08_USB_EXICEN = (0x08U << IOPORT_PFC_OFFSET), ///< P05_1 / USB_HS / USB_EXICEN 675 IOPORT_PIN_P051_PFC_09_MDAT3 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_1 / DSMIFn / MDAT3 676 IOPORT_PIN_P051_PFC_0B_HA3 = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_1 / PHOSTIF / HA3 677 IOPORT_PIN_P052_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_2 / IRQ / IRQ14 678 IOPORT_PIN_P052_PFC_01_ETH0_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P05_2 / ETHER_ETHn / ETH0_CRS 679 IOPORT_PIN_P052_PFC_02_A2 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_2 / BSC / A2 680 IOPORT_PIN_P052_PFC_03_MTIOC4C = (0x03U << IOPORT_PFC_OFFSET), ///< P05_2 / MTU3n / MTIOC4C 681 IOPORT_PIN_P052_PFC_04_GTETRGSA = (0x04U << IOPORT_PFC_OFFSET), ///< P05_2 / GPT_POEG / GTETRGSA 682 IOPORT_PIN_P052_PFC_05_GTIOC7A = (0x05U << IOPORT_PFC_OFFSET), ///< P05_2 / GPTn / GTIOC7A 683 IOPORT_PIN_P052_PFC_06_CMTW0_TOC0 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_2 / CMTWn / CMTW0_TOC0 684 IOPORT_PIN_P052_PFC_07_DE5 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_2 / SCIn / DE5 685 IOPORT_PIN_P052_PFC_08_IIC_SCL1 = (0x08U << IOPORT_PFC_OFFSET), ///< P05_2 / IICn / IIC_SCL1 686 IOPORT_PIN_P052_PFC_09_CANRX0 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_2 / CANFDn / CANRX0 687 IOPORT_PIN_P052_PFC_0A_DREQ = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_2 / DMAC / DREQ 688 IOPORT_PIN_P052_PFC_0B_USB_VBUSEN = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_2 / USB_HS / USB_VBUSEN 689 IOPORT_PIN_P052_PFC_0D_HA2 = (0x0DU << IOPORT_PFC_OFFSET), ///< P05_2 / PHOSTIF / HA2 690 IOPORT_PIN_P053_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_3 / IRQ / IRQ15 691 IOPORT_PIN_P053_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P05_3 / ETHER_ETHn / ETH0_COL 692 IOPORT_PIN_P053_PFC_02_A1 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_3 / BSC / A1 693 IOPORT_PIN_P053_PFC_03_MTIOC4D = (0x03U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU3n / MTIOC4D 694 IOPORT_PIN_P053_PFC_04_GTETRGSB = (0x04U << IOPORT_PFC_OFFSET), ///< P05_3 / GPT_POEG / GTETRGSB 695 IOPORT_PIN_P053_PFC_05_GTIOC7B = (0x05U << IOPORT_PFC_OFFSET), ///< P05_3 / GPTn / GTIOC7B 696 IOPORT_PIN_P053_PFC_06_POE11 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU_POE3 / POE11 697 IOPORT_PIN_P053_PFC_07_CMTW0_TIC0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_3 / CMTWn / CMTW0_TIC0 698 IOPORT_PIN_P053_PFC_08_SCK4 = (0x08U << IOPORT_PFC_OFFSET), ///< P05_3 / SCIn / SCK4 699 IOPORT_PIN_P053_PFC_09_IIC_SDA1 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_3 / IICn / IIC_SDA1 700 IOPORT_PIN_P053_PFC_0A_CANTX0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_3 / CANFDn / CANTX0 701 IOPORT_PIN_P053_PFC_0B_USB_EXICEN = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_3 / USB_HS / USB_EXICEN 702 IOPORT_PIN_P053_PFC_0D_HA1 = (0x0DU << IOPORT_PFC_OFFSET), ///< P05_3 / PHOSTIF / HA1 703 IOPORT_PIN_P054_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_4 / IRQ / IRQ12 704 IOPORT_PIN_P054_PFC_01_ETHSW_LPI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P05_4 / ETHER_ETHSW / ETHSW_LPI0 705 IOPORT_PIN_P054_PFC_02_A0 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_4 / BSC / A0 706 IOPORT_PIN_P054_PFC_03_GTIOC14A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_4 / GPTn / GTIOC14A 707 IOPORT_PIN_P054_PFC_04_RXD4_SCL4_MISO4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_4 / SCIn / RXD4_SCL4_MISO4 708 IOPORT_PIN_P054_PFC_05_SPI_SSL00 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_4 / SPIn / SPI_SSL00 709 IOPORT_PIN_P054_PFC_06_CANTXDP0 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_4 / CANFDn / CANTXDP0 710 IOPORT_PIN_P054_PFC_07_DACK = (0x07U << IOPORT_PFC_OFFSET), ///< P05_4 / DMAC / DACK 711 IOPORT_PIN_P054_PFC_08_USB_OVRCUR = (0x08U << IOPORT_PFC_OFFSET), ///< P05_4 / USB_HS / USB_OVRCUR 712 IOPORT_PIN_P054_PFC_0A_HA0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_4 / PHOSTIF / HA0 713 IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ETHSW / ETHSW_PHYLINK1 714 IOPORT_PIN_P055_PFC_02_ESC_PHYLINK1 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ESC / ESC_PHYLINK1 715 IOPORT_PIN_P055_PFC_03_GTIOC14B = (0x03U << IOPORT_PFC_OFFSET), ///< P05_5 / GPTn / GTIOC14B 716 IOPORT_PIN_P055_PFC_04_CMTW0_TOC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_5 / CMTWn / CMTW0_TOC1 717 IOPORT_PIN_P055_PFC_05_SPI_RSPCK2 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_5 / SPIn / SPI_RSPCK2 718 IOPORT_PIN_P056_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_6 / IRQ / IRQ12 719 IOPORT_PIN_P056_PFC_01_ETH1_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P05_6 / ETHER_ETHn / ETH1_RXER 720 IOPORT_PIN_P056_PFC_03_GTIOC15A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_6 / GPTn / GTIOC15A 721 IOPORT_PIN_P056_PFC_04_CMTW1_TIC0 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_6 / CMTWn / CMTW1_TIC0 722 IOPORT_PIN_P056_PFC_05_SPI_SSL22 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_6 / SPIn / SPI_SSL22 723 IOPORT_PIN_P057_PFC_00_ETH1_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_7 / ETHER_ETHn / ETH1_TXD2 724 IOPORT_PIN_P057_PFC_02_GTIOC15B = (0x02U << IOPORT_PFC_OFFSET), ///< P05_7 / GPTn / GTIOC15B 725 IOPORT_PIN_P057_PFC_03_CMTW1_TOC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P05_7 / CMTWn / CMTW1_TOC1 726 IOPORT_PIN_P057_PFC_04_TXD4_SDA4_MOSI4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_7 / SCIn / TXD4_SDA4_MOSI4 727 IOPORT_PIN_P057_PFC_05_SPI_SSL23 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_7 / SPIn / SPI_SSL23 728 IOPORT_PIN_P060_PFC_00_ETH1_TXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_0 / ETHER_ETHn / ETH1_TXD3 729 IOPORT_PIN_P060_PFC_02_GTIOC16A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_0 / GPTn / GTIOC16A 730 IOPORT_PIN_P060_PFC_03_CMTW1_TOC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_0 / CMTWn / CMTW1_TOC0 731 IOPORT_PIN_P060_PFC_04_SS4_CTS4_RTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_0 / SCIn / SS4_CTS4_RTS4 732 IOPORT_PIN_P060_PFC_05_SPI_SSL23 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_0 / SPIn / SPI_SSL23 733 IOPORT_PIN_P060_PFC_06_CANRX1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_0 / CANFDn / CANRX1 734 IOPORT_PIN_P061_PFC_00_ETH1_REFCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / ETH1_REFCLK 735 IOPORT_PIN_P061_PFC_01_RMII1_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / RMII1_REFCLK 736 IOPORT_PIN_P061_PFC_03_GTIOC16B = (0x03U << IOPORT_PFC_OFFSET), ///< P06_1 / GPTn / GTIOC16B 737 IOPORT_PIN_P061_PFC_04_CTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_1 / SCIn / CTS4 738 IOPORT_PIN_P061_PFC_05_SPI_SSL22 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_1 / SPIn / SPI_SSL22 739 IOPORT_PIN_P061_PFC_06_CANTX1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_1 / CANFDn / CANTX1 740 IOPORT_PIN_P062_PFC_00_ETH1_TXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_2 / ETHER_ETHn / ETH1_TXD1 741 IOPORT_PIN_P062_PFC_02_GTIOC17A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_2 / GPTn / GTIOC17A 742 IOPORT_PIN_P062_PFC_03_CANRXDP1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_2 / CANFDn / CANRXDP1 743 IOPORT_PIN_P063_PFC_00_ETH1_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_3 / ETHER_ETHn / ETH1_TXD0 744 IOPORT_PIN_P063_PFC_02_GTIOC17B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_3 / GPTn / GTIOC17B 745 IOPORT_PIN_P063_PFC_03_CMTW1_TIC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_3 / CMTWn / CMTW1_TIC1 746 IOPORT_PIN_P063_PFC_04_DE4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_3 / SCIn / DE4 747 IOPORT_PIN_P063_PFC_05_SPI_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_3 / SPIn / SPI_MISO1 748 IOPORT_PIN_P063_PFC_06_CANTXDP1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_3 / CANFDn / CANTXDP1 749 IOPORT_PIN_P064_PFC_00_ETH1_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P06_4 / ETHER_ETHn / ETH1_TXCLK 750 IOPORT_PIN_P064_PFC_02_GTIOC11A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_4 / GPTn / GTIOC11A 751 IOPORT_PIN_P064_PFC_03_SPI_MOSI1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_4 / SPIn / SPI_MOSI1 752 IOPORT_PIN_P065_PFC_00_ETH1_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P06_5 / ETHER_ETHn / ETH1_TXEN 753 IOPORT_PIN_P065_PFC_02_GTIOC11B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_5 / GPTn / GTIOC11B 754 IOPORT_PIN_P066_PFC_00_ETH1_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_6 / ETHER_ETHn / ETH1_RXD0 755 IOPORT_PIN_P066_PFC_02_GTIOC12A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_6 / GPTn / GTIOC12A 756 IOPORT_PIN_P066_PFC_03_SPI_SSL10 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_6 / SPIn / SPI_SSL10 757 IOPORT_PIN_P067_PFC_00_ETH1_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_7 / ETHER_ETHn / ETH1_RXD1 758 IOPORT_PIN_P067_PFC_02_GTIOC12B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_7 / GPTn / GTIOC12B 759 IOPORT_PIN_P067_PFC_03_SPI_SSL11 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_7 / SPIn / SPI_SSL11 760 IOPORT_PIN_P070_PFC_00_ETH1_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_0 / ETHER_ETHn / ETH1_RXD2 761 IOPORT_PIN_P070_PFC_02_GTIOC13A = (0x02U << IOPORT_PFC_OFFSET), ///< P07_0 / GPTn / GTIOC13A 762 IOPORT_PIN_P071_PFC_00_ETH1_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_1 / ETHER_ETHn / ETH1_RXD3 763 IOPORT_PIN_P071_PFC_02_GTIOC13B = (0x02U << IOPORT_PFC_OFFSET), ///< P07_1 / GPTn / GTIOC13B 764 IOPORT_PIN_P072_PFC_00_ETH1_RXDV = (0x00U << IOPORT_PFC_OFFSET), ///< P07_2 / ETHER_ETHn / ETH1_RXDV 765 IOPORT_PIN_P073_PFC_00_ETH1_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P07_3 / ETHER_ETHn / ETH1_RXCLK 766 IOPORT_PIN_P074_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_4 / IRQ / IRQ1 767 IOPORT_PIN_P074_PFC_01_ADTRG0 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_4 / ADCn / ADTRG0 768 IOPORT_PIN_P074_PFC_02_USB_VBUSIN = (0x02U << IOPORT_PFC_OFFSET), ///< P07_4 / USB_HS / USB_VBUSIN 769 IOPORT_PIN_P084_PFC_00_ETH0_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_4 / ETHER_ETHn / ETH0_RXD3 770 IOPORT_PIN_P084_PFC_02_MTIOC6A = (0x02U << IOPORT_PFC_OFFSET), ///< P08_4 / MTU3n / MTIOC6A 771 IOPORT_PIN_P085_PFC_00_ETH0_RXDV = (0x00U << IOPORT_PFC_OFFSET), ///< P08_5 / ETHER_ETHn / ETH0_RXDV 772 IOPORT_PIN_P085_PFC_01_MTIOC6B = (0x01U << IOPORT_PFC_OFFSET), ///< P08_5 / MTU3n / MTIOC6B 773 IOPORT_PIN_P086_PFC_00_ETH0_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P08_6 / ETHER_ETHn / ETH0_RXCLK 774 IOPORT_PIN_P086_PFC_01_MTIOC6C = (0x01U << IOPORT_PFC_OFFSET), ///< P08_6 / MTU3n / MTIOC6C 775 IOPORT_PIN_P087_PFC_00_GMAC_MDC = (0x00U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_GMAC / GMAC_MDC 776 IOPORT_PIN_P087_PFC_01_ETHSW_MDC = (0x01U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ETHSW / ETHSW_MDC 777 IOPORT_PIN_P087_PFC_03_ESC_MDC = (0x03U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ESC / ESC_MDC 778 IOPORT_PIN_P087_PFC_04_MTIOC6D = (0x04U << IOPORT_PFC_OFFSET), ///< P08_7 / MTU3n / MTIOC6D 779 IOPORT_PIN_P090_PFC_00_GMAC_MDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_GMAC / GMAC_MDIO 780 IOPORT_PIN_P090_PFC_01_ETHSW_MDIO = (0x01U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ETHSW / ETHSW_MDIO 781 IOPORT_PIN_P090_PFC_03_ESC_MDIO = (0x03U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ESC / ESC_MDIO 782 IOPORT_PIN_P090_PFC_04_MTIOC7A = (0x04U << IOPORT_PFC_OFFSET), ///< P09_0 / MTU3n / MTIOC7A 783 IOPORT_PIN_P091_PFC_00_ETH0_REFCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / ETH0_REFCLK 784 IOPORT_PIN_P091_PFC_01_RMII0_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / RMII0_REFCLK 785 IOPORT_PIN_P091_PFC_02_MTIOC7B = (0x02U << IOPORT_PFC_OFFSET), ///< P09_1 / MTU3n / MTIOC7B 786 IOPORT_PIN_P092_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_2 / IRQ / IRQ0 787 IOPORT_PIN_P092_PFC_01_ETH0_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P09_2 / ETHER_ETHn / ETH0_RXER 788 IOPORT_PIN_P092_PFC_03_MTIOC7C = (0x03U << IOPORT_PFC_OFFSET), ///< P09_2 / MTU3n / MTIOC7C 789 IOPORT_PIN_P093_PFC_00_ETH0_TXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_3 / ETHER_ETHn / ETH0_TXD3 790 IOPORT_PIN_P093_PFC_01_MTIOC7D = (0x01U << IOPORT_PFC_OFFSET), ///< P09_3 / MTU3n / MTIOC7D 791 IOPORT_PIN_P094_PFC_00_ETH0_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_4 / ETHER_ETHn / ETH0_TXD2 792 IOPORT_PIN_P095_PFC_00_ETH0_TXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_5 / ETHER_ETHn / ETH0_TXD1 793 IOPORT_PIN_P096_PFC_00_ETH0_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_6 / ETHER_ETHn / ETH0_TXD0 794 IOPORT_PIN_P097_PFC_00_ETH0_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P09_7 / ETHER_ETHn / ETH0_TXCLK 795 IOPORT_PIN_P100_PFC_00_ETH0_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P10_0 / ETHER_ETHn / ETH0_TXEN 796 IOPORT_PIN_P101_PFC_00_ETH0_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_1 / ETHER_ETHn / ETH0_RXD0 797 IOPORT_PIN_P102_PFC_00_ETH0_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_2 / ETHER_ETHn / ETH0_RXD1 798 IOPORT_PIN_P103_PFC_00_ETH0_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_3 / ETHER_ETHn / ETH0_RXD2 799 IOPORT_PIN_P103_PFC_01_RTCAT1HZ = (0x01U << IOPORT_PFC_OFFSET), ///< P10_3 / RTC / RTCAT1HZ 800 IOPORT_PIN_P104_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_4 / IRQ / IRQ11 801 IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ETHSW / ETHSW_PHYLINK0 802 IOPORT_PIN_P104_PFC_03_ESC_PHYLINK0 = (0x03U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ESC / ESC_PHYLINK0 803 IOPORT_PIN_P124_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P12_4 / ETHER_ETHn / ETH1_CRS 804 IOPORT_PIN_P124_PFC_02_TRACEDATA0 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_4 / TRACE / TRACEDATA0 805 IOPORT_PIN_P124_PFC_03_D15 = (0x03U << IOPORT_PFC_OFFSET), ///< P12_4 / BSC / D15 806 IOPORT_PIN_P124_PFC_04_MTIOC8B = (0x04U << IOPORT_PFC_OFFSET), ///< P12_4 / MTU3n / MTIOC8B 807 IOPORT_PIN_P124_PFC_05_GTIOC8B = (0x05U << IOPORT_PFC_OFFSET), ///< P12_4 / GPTn / GTIOC8B 808 IOPORT_PIN_P124_PFC_06_SPI_SSL01 = (0x06U << IOPORT_PFC_OFFSET), ///< P12_4 / SPIn / SPI_SSL01 809 IOPORT_PIN_P124_PFC_08_MBX_HINT = (0x08U << IOPORT_PFC_OFFSET), ///< P12_4 / MBXSEM / MBX_HINT 810 IOPORT_PIN_P132_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_2 / IRQ / IRQ5 811 IOPORT_PIN_P132_PFC_02_ETHSW_PTPOUT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ETHSW / ETHSW_PTPOUT2 812 IOPORT_PIN_P132_PFC_03_TRACEDATA6 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_2 / TRACE / TRACEDATA6 813 IOPORT_PIN_P132_PFC_04_D9 = (0x04U << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / D9 814 IOPORT_PIN_P132_PFC_05_ESC_I2CCLK = (0x05U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ESC / ESC_I2CCLK 815 IOPORT_PIN_P132_PFC_06_MTIOC0A = (0x06U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU3n / MTIOC0A 816 IOPORT_PIN_P132_PFC_07_GTIOC10A = (0x07U << IOPORT_PFC_OFFSET), ///< P13_2 / GPTn / GTIOC10A 817 IOPORT_PIN_P132_PFC_08_POE8 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU_POE3 / POE8 818 IOPORT_PIN_P132_PFC_09_SS1_CTS1_RTS1 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_2 / SCIn / SS1_CTS1_RTS1 819 IOPORT_PIN_P132_PFC_0A_SPI_MISO0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_2 / SPIn / SPI_MISO0 820 IOPORT_PIN_P132_PFC_0B_IIC_SCL0 = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_2 / IICn / IIC_SCL0 821 IOPORT_PIN_P132_PFC_0C_MCLK4 = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_2 / DSMIFn / MCLK4 822 IOPORT_PIN_P132_PFC_0E_A13 = (0x0EU << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / A13 823 IOPORT_PIN_P133_PFC_01_ETHSW_PTPOUT3 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ETHSW / ETHSW_PTPOUT3 824 IOPORT_PIN_P133_PFC_02_TRACEDATA7 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_3 / TRACE / TRACEDATA7 825 IOPORT_PIN_P133_PFC_03_D8 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / D8 826 IOPORT_PIN_P133_PFC_04_ESC_I2CDATA = (0x04U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ESC / ESC_I2CDATA 827 IOPORT_PIN_P133_PFC_05_MTIOC0C = (0x05U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0C 828 IOPORT_PIN_P133_PFC_06_MTIOC0B = (0x06U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0B 829 IOPORT_PIN_P133_PFC_07_GTIOC10B = (0x07U << IOPORT_PFC_OFFSET), ///< P13_3 / GPTn / GTIOC10B 830 IOPORT_PIN_P133_PFC_08_CMTW1_TOC0 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_3 / CMTWn / CMTW1_TOC0 831 IOPORT_PIN_P133_PFC_09_CTS1 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_3 / SCIn / CTS1 832 IOPORT_PIN_P133_PFC_0A_SPI_RSPCK0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_3 / SPIn / SPI_RSPCK0 833 IOPORT_PIN_P133_PFC_0B_IIC_SDA0 = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_3 / IICn / IIC_SDA0 834 IOPORT_PIN_P133_PFC_0C_MDAT4 = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_3 / DSMIFn / MDAT4 835 IOPORT_PIN_P133_PFC_0E_RD = (0x0EU << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / RD 836 IOPORT_PIN_P134_PFC_01_ESC_RESETOUT = (0x01U << IOPORT_PFC_OFFSET), ///< P13_4 / ETHER_ESC / ESC_RESETOUT 837 IOPORT_PIN_P134_PFC_02_MTIOC0D = (0x02U << IOPORT_PFC_OFFSET), ///< P13_4 / MTU3n / MTIOC0D 838 IOPORT_PIN_P134_PFC_03_GTIOC8B = (0x03U << IOPORT_PFC_OFFSET), ///< P13_4 / GPTn / GTIOC8B 839 IOPORT_PIN_P134_PFC_05_A0 = (0x05U << IOPORT_PFC_OFFSET), ///< P13_4 / BSC / A0 840 IOPORT_PIN_P135_PFC_00_XSPI0_WP1 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_5 / XSPIn / XSPI0_WP1 841 IOPORT_PIN_P135_PFC_01_GMAC_PTPTRG0 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_GMAC / GMAC_PTPTRG0 842 IOPORT_PIN_P135_PFC_02_ESC_LATCH0 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH0 843 IOPORT_PIN_P135_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH1 844 IOPORT_PIN_P135_PFC_04_MTCLKA = (0x04U << IOPORT_PFC_OFFSET), ///< P13_5 / MTU3 / MTCLKA 845 IOPORT_PIN_P135_PFC_05_SPI_RSPCK1 = (0x05U << IOPORT_PFC_OFFSET), ///< P13_5 / SPIn / SPI_RSPCK1 846 IOPORT_PIN_P135_PFC_06_IIC_SCL2 = (0x06U << IOPORT_PFC_OFFSET), ///< P13_5 / IICn / IIC_SCL2 847 IOPORT_PIN_P136_PFC_00_XSPI0_WP0 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_6 / XSPIn / XSPI0_WP0 848 IOPORT_PIN_P136_PFC_01_ETHSW_PTPOUT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ETHSW / ETHSW_PTPOUT0 849 IOPORT_PIN_P136_PFC_02_ESC_SYNC0 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC0 850 IOPORT_PIN_P136_PFC_03_ESC_SYNC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC1 851 IOPORT_PIN_P136_PFC_04_MTCLKB = (0x04U << IOPORT_PFC_OFFSET), ///< P13_6 / MTU3 / MTCLKB 852 IOPORT_PIN_P137_PFC_00_XSPI0_ECS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_7 / XSPIn / XSPI0_ECS1 853 IOPORT_PIN_P137_PFC_01_GMAC_PTPTRG1 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_GMAC / GMAC_PTPTRG1 854 IOPORT_PIN_P137_PFC_02_ESC_LATCH1 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH1 855 IOPORT_PIN_P137_PFC_03_ESC_LATCH0 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH0 856 IOPORT_PIN_P137_PFC_04_MTCLKC = (0x04U << IOPORT_PFC_OFFSET), ///< P13_7 / MTU3 / MTCLKC 857 IOPORT_PIN_P137_PFC_05_MBX_HINT = (0x05U << IOPORT_PFC_OFFSET), ///< P13_7 / MBXSEM / MBX_HINT 858 IOPORT_PIN_P140_PFC_00_XSPI0_INT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_0 / XSPIn / XSPI0_INT0 859 IOPORT_PIN_P140_PFC_01_ETHSW_PTPOUT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ETHSW / ETHSW_PTPOUT1 860 IOPORT_PIN_P140_PFC_02_ESC_SYNC1 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC1 861 IOPORT_PIN_P140_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC0 862 IOPORT_PIN_P140_PFC_04_MTCLKD = (0x04U << IOPORT_PFC_OFFSET), ///< P14_0 / MTU3 / MTCLKD 863 IOPORT_PIN_P141_PFC_00_XSPI0_INT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_1 / XSPIn / XSPI0_INT1 864 IOPORT_PIN_P141_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ETHn / ETH1_COL 865 IOPORT_PIN_P141_PFC_03_MTIOC8A = (0x03U << IOPORT_PFC_OFFSET), ///< P14_1 / MTU3n / MTIOC8A 866 IOPORT_PIN_P141_PFC_04_GTIOC8A = (0x04U << IOPORT_PFC_OFFSET), ///< P14_1 / GPTn / GTIOC8A 867 IOPORT_PIN_P141_PFC_06_GMAC_PTPTRG1 = (0x06U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_GMAC / GMAC_PTPTRG1 868 IOPORT_PIN_P141_PFC_07_ESC_LATCH0 = (0x07U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ESC / ESC_LATCH0 869 IOPORT_PIN_P141_PFC_08_ESC_LATCH1 = (0x08U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ESC / ESC_LATCH1 870 IOPORT_PIN_P141_PFC_09_HSPI_IO0 = (0x09U << IOPORT_PFC_OFFSET), ///< P14_1 / SHOSTIF / HSPI_IO0 871 IOPORT_PIN_P142_PFC_00_IRQ6 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_2 / IRQ / IRQ6 872 IOPORT_PIN_P142_PFC_01_XSPI0_ECS0 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_2 / XSPIn / XSPI0_ECS0 873 IOPORT_PIN_P142_PFC_02_ETH0_CRS = (0x02U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH0_CRS 874 IOPORT_PIN_P142_PFC_04_MTIOC8B = (0x04U << IOPORT_PFC_OFFSET), ///< P14_2 / MTU3n / MTIOC8B 875 IOPORT_PIN_P142_PFC_05_GTIOC8B = (0x05U << IOPORT_PFC_OFFSET), ///< P14_2 / GPTn / GTIOC8B 876 IOPORT_PIN_P142_PFC_07_ETH2_CRS = (0x07U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH2_CRS 877 IOPORT_PIN_P142_PFC_08_HSPI_CK = (0x08U << IOPORT_PFC_OFFSET), ///< P14_2 / SHOSTIF / HSPI_CK 878 IOPORT_PIN_P143_PFC_00_XSPI0_RSTO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_3 / XSPIn / XSPI0_RSTO1 879 IOPORT_PIN_P143_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH0_COL 880 IOPORT_PIN_P143_PFC_04_MTIOC0A = (0x04U << IOPORT_PFC_OFFSET), ///< P14_3 / MTU3n / MTIOC0A 881 IOPORT_PIN_P143_PFC_06_ETH2_COL = (0x06U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH2_COL 882 IOPORT_PIN_P143_PFC_07_HSPI_IO1 = (0x07U << IOPORT_PFC_OFFSET), ///< P14_3 / SHOSTIF / HSPI_IO1 883 IOPORT_PIN_P144_PFC_00_XSPI0_DS = (0x00U << IOPORT_PFC_OFFSET), ///< P14_4 / XSPIn / XSPI0_DS 884 IOPORT_PIN_P144_PFC_01_BS = (0x01U << IOPORT_PFC_OFFSET), ///< P14_4 / BSC / BS 885 IOPORT_PIN_P144_PFC_02_ESC_IRQ = (0x02U << IOPORT_PFC_OFFSET), ///< P14_4 / ETHER_ESC / ESC_IRQ 886 IOPORT_PIN_P144_PFC_03_MTIOC0B = (0x03U << IOPORT_PFC_OFFSET), ///< P14_4 / MTU3n / MTIOC0B 887 IOPORT_PIN_P144_PFC_04_HBS = (0x04U << IOPORT_PFC_OFFSET), ///< P14_4 / PHOSTIF / HBS 888 IOPORT_PIN_P145_PFC_00_XSPI0_CKN = (0x00U << IOPORT_PFC_OFFSET), ///< P14_5 / XSPIn / XSPI0_CKN 889 IOPORT_PIN_P145_PFC_01_CS3 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_5 / BSC / CS3 890 IOPORT_PIN_P145_PFC_02_POE8 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_5 / MTU_POE3 / POE8 891 IOPORT_PIN_P145_PFC_03_HSPI_INT = (0x03U << IOPORT_PFC_OFFSET), ///< P14_5 / SHOSTIF / HSPI_INT 892 IOPORT_PIN_P146_PFC_00_XSPI0_CKP = (0x00U << IOPORT_PFC_OFFSET), ///< P14_6 / XSPIn / XSPI0_CKP 893 IOPORT_PIN_P146_PFC_01_A21 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_6 / BSC / A21 894 IOPORT_PIN_P147_PFC_00_XSPI0_IO0 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_7 / XSPIn / XSPI0_IO0 895 IOPORT_PIN_P147_PFC_01_A22 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / A22 896 IOPORT_PIN_P147_PFC_02_SCK5 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_7 / SCIn / SCK5 897 IOPORT_PIN_P147_PFC_03_SPI_MISO1 = (0x03U << IOPORT_PFC_OFFSET), ///< P14_7 / SPIn / SPI_MISO1 898 IOPORT_PIN_P147_PFC_04_BS = (0x04U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / BS 899 IOPORT_PIN_P150_PFC_00_XSPI0_IO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_0 / XSPIn / XSPI0_IO1 900 IOPORT_PIN_P150_PFC_01_A23 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / A23 901 IOPORT_PIN_P150_PFC_02_RXD5_SCL5_MISO5 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_0 / SCIn / RXD5_SCL5_MISO5 902 IOPORT_PIN_P150_PFC_03_SPI_MOSI1 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_0 / SPIn / SPI_MOSI1 903 IOPORT_PIN_P150_PFC_04_CKE = (0x04U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / CKE 904 IOPORT_PIN_P151_PFC_00_XSPI0_IO2 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_1 / XSPIn / XSPI0_IO2 905 IOPORT_PIN_P151_PFC_01_A24 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / A24 906 IOPORT_PIN_P151_PFC_02_MTIOC0C = (0x02U << IOPORT_PFC_OFFSET), ///< P15_1 / MTU3n / MTIOC0C 907 IOPORT_PIN_P151_PFC_03_TXD5_SDA5_MOSI5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_1 / SCIn / TXD5_SDA5_MOSI5 908 IOPORT_PIN_P151_PFC_04_SPI_SSL10 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_1 / SPIn / SPI_SSL10 909 IOPORT_PIN_P151_PFC_05_CAS = (0x05U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / CAS 910 IOPORT_PIN_P152_PFC_00_XSPI0_IO3 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_2 / XSPIn / XSPI0_IO3 911 IOPORT_PIN_P152_PFC_01_A25 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / A25 912 IOPORT_PIN_P152_PFC_02_MTIOC0D = (0x02U << IOPORT_PFC_OFFSET), ///< P15_2 / MTU3n / MTIOC0D 913 IOPORT_PIN_P152_PFC_03_SS5_CTS5_RTS5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_2 / SCIn / SS5_CTS5_RTS5 914 IOPORT_PIN_P152_PFC_04_SPI_SSL11 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_2 / SPIn / SPI_SSL11 915 IOPORT_PIN_P152_PFC_05_RAS = (0x05U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / RAS 916 IOPORT_PIN_P153_PFC_00_XSPI0_IO4 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_3 / XSPIn / XSPI0_IO4 917 IOPORT_PIN_P153_PFC_01_MTIOC8C = (0x01U << IOPORT_PFC_OFFSET), ///< P15_3 / MTU3n / MTIOC8C 918 IOPORT_PIN_P153_PFC_02_MCLK1 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_3 / DSMIFn / MCLK1 919 IOPORT_PIN_P153_PFC_03_D11 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_3 / BSC / D11 920 IOPORT_PIN_P154_PFC_00_XSPI0_IO5 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_4 / XSPIn / XSPI0_IO5 921 IOPORT_PIN_P154_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P15_4 / MTU3n / MTIOC8D 922 IOPORT_PIN_P154_PFC_02_MDAT1 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_4 / DSMIFn / MDAT1 923 IOPORT_PIN_P154_PFC_03_D12 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_4 / BSC / D12 924 IOPORT_PIN_P155_PFC_00_XSPI0_IO6 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_5 / XSPIn / XSPI0_IO6 925 IOPORT_PIN_P155_PFC_01_MCLK2 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_5 / DSMIFn / MCLK2 926 IOPORT_PIN_P155_PFC_02_D13 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_5 / BSC / D13 927 IOPORT_PIN_P156_PFC_00_XSPI0_IO7 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_6 / XSPIn / XSPI0_IO7 928 IOPORT_PIN_P156_PFC_01_SPI_SSL12 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_6 / SPIn / SPI_SSL12 929 IOPORT_PIN_P156_PFC_02_MDAT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_6 / DSMIFn / MDAT2 930 IOPORT_PIN_P156_PFC_03_D14 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_6 / BSC / D14 931 IOPORT_PIN_P157_PFC_00_XSPI0_CS0 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_7 / XSPIn / XSPI0_CS0 932 IOPORT_PIN_P157_PFC_01_CTS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_7 / SCIn / CTS5 933 IOPORT_PIN_P157_PFC_02_SPI_SSL13 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_7 / SPIn / SPI_SSL13 934 IOPORT_PIN_P157_PFC_03_TEND = (0x03U << IOPORT_PFC_OFFSET), ///< P15_7 / DMAC / TEND 935 IOPORT_PIN_P160_PFC_00_XSPI0_CS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_0 / XSPIn / XSPI0_CS1 936 IOPORT_PIN_P160_PFC_01_ETH0_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH0_TXER 937 IOPORT_PIN_P160_PFC_02_TXD0_SDA0_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_0 / SCIn / TXD0_SDA0_MOSI0 938 IOPORT_PIN_P160_PFC_03_SPI_MOSI3 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_0 / SPIn / SPI_MOSI3 939 IOPORT_PIN_P160_PFC_04_MCLK3 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_0 / DSMIFn / MCLK3 940 IOPORT_PIN_P160_PFC_06_ETH2_REFCLK = (0x06U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH2_REFCLK 941 IOPORT_PIN_P160_PFC_07_HSPI_CS = (0x07U << IOPORT_PFC_OFFSET), ///< P16_0 / SHOSTIF / HSPI_CS 942 IOPORT_PIN_P161_PFC_00_XSPI0_RESET0 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_1 / XSPIn / XSPI0_RESET0 943 IOPORT_PIN_P161_PFC_01_CMTW0_TOC1 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_1 / CMTWn / CMTW0_TOC1 944 IOPORT_PIN_P161_PFC_02_ADTRG0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_1 / ADCn / ADTRG0 945 IOPORT_PIN_P161_PFC_03_RXD0_SCL0_MISO0 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_1 / SCIn / RXD0_SCL0_MISO0 946 IOPORT_PIN_P161_PFC_04_SPI_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_1 / SPIn / SPI_MISO3 947 IOPORT_PIN_P161_PFC_05_MDAT3 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_1 / DSMIFn / MDAT3 948 IOPORT_PIN_P161_PFC_07_CS2 = (0x07U << IOPORT_PFC_OFFSET), ///< P16_1 / BSC / CS2 949 IOPORT_PIN_P161_PFC_08_HCS1 = (0x08U << IOPORT_PFC_OFFSET), ///< P16_1 / PHOSTIF / HCS1 950 IOPORT_PIN_P162_PFC_00_NMI = (0x00U << IOPORT_PFC_OFFSET), ///< P16_2 / IRQ / NMI 951 IOPORT_PIN_P162_PFC_01_XSPI0_RESET1 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_2 / XSPIn / XSPI0_RESET1 952 IOPORT_PIN_P162_PFC_02_CTS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_2 / SCIn / CTS0 953 IOPORT_PIN_P162_PFC_03_SPI_RSPCK3 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_2 / SPIn / SPI_RSPCK3 954 IOPORT_PIN_P162_PFC_04_USB_EXICEN = (0x04U << IOPORT_PFC_OFFSET), ///< P16_2 / USB_HS / USB_EXICEN 955 IOPORT_PIN_P162_PFC_06_HSPI_IO2 = (0x06U << IOPORT_PFC_OFFSET), ///< P16_2 / SHOSTIF / HSPI_IO2 956 IOPORT_PIN_P162_PFC_07_HERROUT = (0x07U << IOPORT_PFC_OFFSET), ///< P16_2 / PHOSTIF / HERROUT 957 IOPORT_PIN_P163_PFC_00_IRQ7 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_3 / IRQ / IRQ7 958 IOPORT_PIN_P163_PFC_01_XSPI0_RSTO0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_3 / XSPIn / XSPI0_RSTO0 959 IOPORT_PIN_P163_PFC_02_ETH1_TXER = (0x02U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_TXER 960 IOPORT_PIN_P163_PFC_03_GTADSMP1 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_3 / GPT / GTADSMP1 961 IOPORT_PIN_P163_PFC_04_SCK0 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_3 / SCIn / SCK0 962 IOPORT_PIN_P163_PFC_05_SPI_SSL30 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_3 / SPIn / SPI_SSL30 963 IOPORT_PIN_P163_PFC_07_ETH1_CRS = (0x07U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_CRS 964 IOPORT_PIN_P163_PFC_08_CS3 = (0x08U << IOPORT_PFC_OFFSET), ///< P16_3 / BSC / CS3 965 IOPORT_PIN_P163_PFC_09_HSPI_IO3 = (0x09U << IOPORT_PFC_OFFSET), ///< P16_3 / SHOSTIF / HSPI_IO3 966 IOPORT_PIN_P165_PFC_00_MTIC5U = (0x00U << IOPORT_PFC_OFFSET), ///< P16_5 / MTU3n / MTIC5U 967 IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_5 / SCIn / TXD0_SDA0_MOSI0 968 IOPORT_PIN_P165_PFC_02_A15 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_5 / BSC / A15 969 IOPORT_PIN_P165_PFC_03_HSPI_IO4 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_5 / SHOSTIF / HSPI_IO4 970 IOPORT_PIN_P166_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_6 / IRQ / IRQ8 971 IOPORT_PIN_P166_PFC_01_MTIC5V = (0x01U << IOPORT_PFC_OFFSET), ///< P16_6 / MTU3n / MTIC5V 972 IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_6 / SCIn / RXD0_SCL0_MISO0 973 IOPORT_PIN_P166_PFC_03_CS0 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_6 / BSC / CS0 974 IOPORT_PIN_P166_PFC_04_HSPI_IO5 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_6 / SHOSTIF / HSPI_IO5 975 IOPORT_PIN_P166_PFC_05_HCS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_6 / PHOSTIF / HCS0 976 IOPORT_PIN_P167_PFC_00_MTIC5W = (0x00U << IOPORT_PFC_OFFSET), ///< P16_7 / MTU3n / MTIC5W 977 IOPORT_PIN_P167_PFC_01_SCK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_7 / SCIn / SCK0 978 IOPORT_PIN_P167_PFC_02_XSPI1_IO0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_7 / XSPIn / XSPI1_IO0 979 IOPORT_PIN_P167_PFC_03_A13 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_7 / BSC / A13 980 IOPORT_PIN_P167_PFC_04_HA13 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_7 / PHOSTIF / HA13 981 IOPORT_PIN_P170_PFC_00_ESC_IRQ = (0x00U << IOPORT_PFC_OFFSET), ///< P17_0 / ETHER_ESC / ESC_IRQ 982 IOPORT_PIN_P170_PFC_01_SS0_CTS0_RTS0 = (0x01U << IOPORT_PFC_OFFSET), ///< P17_0 / SCIn / SS0_CTS0_RTS0 983 IOPORT_PIN_P170_PFC_02_XSPI1_IO1 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_0 / XSPIn / XSPI1_IO1 984 IOPORT_PIN_P173_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P17_3 / TRACE / TRACECTL 985 IOPORT_PIN_P173_PFC_01_GTETRGA = (0x01U << IOPORT_PFC_OFFSET), ///< P17_3 / GPT_POEG / GTETRGA 986 IOPORT_PIN_P173_PFC_02_POE0 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_3 / MTU_POE3 / POE0 987 IOPORT_PIN_P173_PFC_03_ADTRG1 = (0x03U << IOPORT_PFC_OFFSET), ///< P17_3 / ADCn / ADTRG1 988 IOPORT_PIN_P173_PFC_04_SPI_SSL31 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_3 / SPIn / SPI_SSL31 989 IOPORT_PIN_P173_PFC_05_DREQ = (0x05U << IOPORT_PFC_OFFSET), ///< P17_3 / DMAC / DREQ 990 IOPORT_PIN_P173_PFC_07_XSPI1_IO2 = (0x07U << IOPORT_PFC_OFFSET), ///< P17_3 / XSPIn / XSPI1_IO2 991 IOPORT_PIN_P174_PFC_00_TRACECLK = (0x00U << IOPORT_PFC_OFFSET), ///< P17_4 / TRACE / TRACECLK 992 IOPORT_PIN_P174_PFC_01_MTIOC3C = (0x01U << IOPORT_PFC_OFFSET), ///< P17_4 / MTU3n / MTIOC3C 993 IOPORT_PIN_P174_PFC_02_GTETRGB = (0x02U << IOPORT_PFC_OFFSET), ///< P17_4 / GPT_POEG / GTETRGB 994 IOPORT_PIN_P174_PFC_03_GTIOC0A = (0x03U << IOPORT_PFC_OFFSET), ///< P17_4 / GPTn / GTIOC0A 995 IOPORT_PIN_P174_PFC_04_CTS3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_4 / SCIn / CTS3 996 IOPORT_PIN_P174_PFC_05_SPI_SSL32 = (0x05U << IOPORT_PFC_OFFSET), ///< P17_4 / SPIn / SPI_SSL32 997 IOPORT_PIN_P174_PFC_07_XSPI1_IO3 = (0x07U << IOPORT_PFC_OFFSET), ///< P17_4 / XSPIn / XSPI1_IO3 998 IOPORT_PIN_P174_PFC_08_DACK = (0x08U << IOPORT_PFC_OFFSET), ///< P17_4 / DMAC / DACK 999 IOPORT_PIN_P175_PFC_01_MTIOC3A = (0x01U << IOPORT_PFC_OFFSET), ///< P17_5 / MTU3n / MTIOC3A 1000 IOPORT_PIN_P175_PFC_02_GTETRGC = (0x02U << IOPORT_PFC_OFFSET), ///< P17_5 / GPT_POEG / GTETRGC 1001 IOPORT_PIN_P175_PFC_03_GTIOC0B = (0x03U << IOPORT_PFC_OFFSET), ///< P17_5 / GPTn / GTIOC0B 1002 IOPORT_PIN_P175_PFC_04_TEND = (0x04U << IOPORT_PFC_OFFSET), ///< P17_5 / DMAC / TEND 1003 IOPORT_PIN_P175_PFC_05_USB_OVRCUR = (0x05U << IOPORT_PFC_OFFSET), ///< P17_5 / USB_HS / USB_OVRCUR 1004 IOPORT_PIN_P176_PFC_00_MTIOC3B = (0x00U << IOPORT_PFC_OFFSET), ///< P17_6 / MTU3n / MTIOC3B 1005 IOPORT_PIN_P176_PFC_01_GTIOC1A = (0x01U << IOPORT_PFC_OFFSET), ///< P17_6 / GPTn / GTIOC1A 1006 IOPORT_PIN_P176_PFC_02_SCK3 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_6 / SCIn / SCK3 1007 IOPORT_PIN_P176_PFC_04_XSPI1_DS = (0x04U << IOPORT_PFC_OFFSET), ///< P17_6 / XSPIn / XSPI1_DS 1008 IOPORT_PIN_P176_PFC_05_RD_WR = (0x05U << IOPORT_PFC_OFFSET), ///< P17_6 / BSC / RD_WR 1009 IOPORT_PIN_P176_PFC_06_HWRSTB = (0x06U << IOPORT_PFC_OFFSET), ///< P17_6 / PHOSTIF / HWRSTB 1010 IOPORT_PIN_P177_PFC_00_MTIOC4A = (0x00U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4A 1011 IOPORT_PIN_P177_PFC_01_MTIOC4C = (0x01U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4C 1012 IOPORT_PIN_P177_PFC_02_GTIOC2A = (0x02U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC2A 1013 IOPORT_PIN_P177_PFC_03_GTIOC3A = (0x03U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC3A 1014 IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_7 / SCIn / RXD3_SCL3_MISO3 1015 IOPORT_PIN_P177_PFC_05_DACK = (0x05U << IOPORT_PFC_OFFSET), ///< P17_7 / DMAC / DACK 1016 IOPORT_PIN_P177_PFC_07_XSPI1_CKP = (0x07U << IOPORT_PFC_OFFSET), ///< P17_7 / XSPIn / XSPI1_CKP 1017 IOPORT_PIN_P177_PFC_08_RD = (0x08U << IOPORT_PFC_OFFSET), ///< P17_7 / BSC / RD 1018 IOPORT_PIN_P177_PFC_09_HRD = (0x09U << IOPORT_PFC_OFFSET), ///< P17_7 / PHOSTIF / HRD 1019 IOPORT_PIN_P180_PFC_00_MTIOC4C = (0x00U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4C 1020 IOPORT_PIN_P180_PFC_01_MTIOC4A = (0x01U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4A 1021 IOPORT_PIN_P180_PFC_02_GTIOC3A = (0x02U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC3A 1022 IOPORT_PIN_P180_PFC_03_GTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC2A 1023 IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_0 / SCIn / TXD3_SDA3_MOSI3 1024 IOPORT_PIN_P180_PFC_05_WE0_DQMLL = (0x05U << IOPORT_PFC_OFFSET), ///< P18_0 / BSC / WE0_DQMLL 1025 IOPORT_PIN_P180_PFC_06_HSPI_IO6 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_0 / SHOSTIF / HSPI_IO6 1026 IOPORT_PIN_P180_PFC_07_HWR0 = (0x07U << IOPORT_PFC_OFFSET), ///< P18_0 / PHOSTIF / HWR0 1027 IOPORT_PIN_P181_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_1 / IRQ / IRQ10 1028 IOPORT_PIN_P181_PFC_01_MTIOC3D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_1 / MTU3n / MTIOC3D 1029 IOPORT_PIN_P181_PFC_02_GTIOC1B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_1 / GPTn / GTIOC1B 1030 IOPORT_PIN_P181_PFC_03_ADTRG1 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_1 / ADCn / ADTRG1 1031 IOPORT_PIN_P181_PFC_04_SS3_CTS3_RTS3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_1 / SCIn / SS3_CTS3_RTS3 1032 IOPORT_PIN_P181_PFC_06_WE1_DQMLU = (0x06U << IOPORT_PFC_OFFSET), ///< P18_1 / BSC / WE1_DQMLU 1033 IOPORT_PIN_P181_PFC_07_HSPI_IO7 = (0x07U << IOPORT_PFC_OFFSET), ///< P18_1 / SHOSTIF / HSPI_IO7 1034 IOPORT_PIN_P181_PFC_08_HWR1 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_1 / PHOSTIF / HWR1 1035 IOPORT_PIN_P182_PFC_00_MTIOC4B = (0x00U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4B 1036 IOPORT_PIN_P182_PFC_01_MTIOC4D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4D 1037 IOPORT_PIN_P182_PFC_02_GTIOC2B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC2B 1038 IOPORT_PIN_P182_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC3B 1039 IOPORT_PIN_P182_PFC_05_XSPI1_CS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_2 / XSPIn / XSPI1_CS0 1040 IOPORT_PIN_P182_PFC_06_ETH1_COL = (0x06U << IOPORT_PFC_OFFSET), ///< P18_2 / ETHER_ETHn / ETH1_COL 1041 IOPORT_PIN_P182_PFC_07_BS = (0x07U << IOPORT_PFC_OFFSET), ///< P18_2 / BSC / BS 1042 IOPORT_PIN_P182_PFC_08_SCK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_2 / SCIn / SCK0 1043 IOPORT_PIN_P182_PFC_09_IIC_SDA2 = (0x09U << IOPORT_PFC_OFFSET), ///< P18_2 / IICn / IIC_SDA2 1044 IOPORT_PIN_P183_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_3 / IRQ / IRQ0 1045 IOPORT_PIN_P183_PFC_01_MTIOC4D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4D 1046 IOPORT_PIN_P183_PFC_02_MTIOC4B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4B 1047 IOPORT_PIN_P183_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC3B 1048 IOPORT_PIN_P183_PFC_04_GTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC2B 1049 IOPORT_PIN_P183_PFC_05_CMTW1_TIC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_3 / CMTWn / CMTW1_TIC1 1050 IOPORT_PIN_P183_PFC_06_CANRXDP1 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_3 / CANFDn / CANRXDP1 1051 IOPORT_PIN_P183_PFC_08_XSPI1_IO4 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_3 / XSPIn / XSPI1_IO4 1052 IOPORT_PIN_P183_PFC_09_ETH2_CRS = (0x09U << IOPORT_PFC_OFFSET), ///< P18_3 / ETHER_ETHn / ETH2_CRS 1053 IOPORT_PIN_P183_PFC_0A_CKE = (0x0AU << IOPORT_PFC_OFFSET), ///< P18_3 / BSC / CKE 1054 IOPORT_PIN_P184_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_4 / IRQ / IRQ1 1055 IOPORT_PIN_P184_PFC_01_MTIC5U = (0x01U << IOPORT_PFC_OFFSET), ///< P18_4 / MTU3n / MTIC5U 1056 IOPORT_PIN_P184_PFC_02_TXD4_SDA4_MOSI4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_4 / SCIn / TXD4_SDA4_MOSI4 1057 IOPORT_PIN_P184_PFC_03_SPI_RSPCK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_4 / SPIn / SPI_RSPCK2 1058 IOPORT_PIN_P184_PFC_05_XSPI1_IO5 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_4 / XSPIn / XSPI1_IO5 1059 IOPORT_PIN_P184_PFC_06_ETH1_CRS = (0x06U << IOPORT_PFC_OFFSET), ///< P18_4 / ETHER_ETHn / ETH1_CRS 1060 IOPORT_PIN_P184_PFC_07_CAS = (0x07U << IOPORT_PFC_OFFSET), ///< P18_4 / BSC / CAS 1061 IOPORT_PIN_P184_PFC_08_CANTX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_4 / CANFDn / CANTX0 1062 IOPORT_PIN_P185_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P18_5 / TRACE / TRACECTL 1063 IOPORT_PIN_P185_PFC_01_MTIC5V = (0x01U << IOPORT_PFC_OFFSET), ///< P18_5 / MTU3n / MTIC5V 1064 IOPORT_PIN_P185_PFC_02_RXD4_SCL4_MISO4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_5 / SCIn / RXD4_SCL4_MISO4 1065 IOPORT_PIN_P185_PFC_03_SPI_MOSI2 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_5 / SPIn / SPI_MOSI2 1066 IOPORT_PIN_P185_PFC_05_XSPI1_IO6 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_5 / XSPIn / XSPI1_IO6 1067 IOPORT_PIN_P185_PFC_06_ETH2_COL = (0x06U << IOPORT_PFC_OFFSET), ///< P18_5 / ETHER_ETHn / ETH2_COL 1068 IOPORT_PIN_P185_PFC_07_RAS = (0x07U << IOPORT_PFC_OFFSET), ///< P18_5 / BSC / RAS 1069 IOPORT_PIN_P185_PFC_08_CANRX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_5 / CANFDn / CANRX0 1070 IOPORT_PIN_P186_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_6 / IRQ / IRQ11 1071 IOPORT_PIN_P186_PFC_01_TRACECLK = (0x01U << IOPORT_PFC_OFFSET), ///< P18_6 / TRACE / TRACECLK 1072 IOPORT_PIN_P186_PFC_02_MTIC5W = (0x02U << IOPORT_PFC_OFFSET), ///< P18_6 / MTU3n / MTIC5W 1073 IOPORT_PIN_P186_PFC_03_ADTRG0 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_6 / ADCn / ADTRG0 1074 IOPORT_PIN_P186_PFC_04_SCK4 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / SCK4 1075 IOPORT_PIN_P186_PFC_05_SPI_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_6 / SPIn / SPI_MISO2 1076 IOPORT_PIN_P186_PFC_06_IIC_SCL2 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_6 / IICn / IIC_SCL2 1077 IOPORT_PIN_P186_PFC_08_XSPI1_IO7 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_6 / XSPIn / XSPI1_IO7 1078 IOPORT_PIN_P186_PFC_09_ETH1_COL = (0x09U << IOPORT_PFC_OFFSET), ///< P18_6 / ETHER_ETHn / ETH1_COL 1079 IOPORT_PIN_P186_PFC_0A_DE4 = (0x0AU << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / DE4 1080 IOPORT_PIN_P190_PFC_00_USB_VBUSEN = (0x00U << IOPORT_PFC_OFFSET), ///< P19_0 / USB_HS / USB_VBUSEN 1081 IOPORT_PIN_P201_PFC_00_ETHSW_TDMAOUT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_TDMAOUT0 1082 IOPORT_PIN_P201_PFC_01_ESC_LINKACT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ESC / ESC_LINKACT0 1083 IOPORT_PIN_P201_PFC_02_ETHSW_PTPOUT3 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_PTPOUT3 1084 IOPORT_PIN_P202_PFC_00_ETHSW_TDMAOUT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_TDMAOUT1 1085 IOPORT_PIN_P202_PFC_01_ESC_LEDRUN = (0x01U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDRUN 1086 IOPORT_PIN_P202_PFC_02_ESC_LEDSTER = (0x02U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDSTER 1087 IOPORT_PIN_P202_PFC_03_DE3 = (0x03U << IOPORT_PFC_OFFSET), ///< P20_2 / SCIn / DE3 1088 IOPORT_PIN_P202_PFC_04_ETHSW_PTPOUT2 = (0x04U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_PTPOUT2 1089 IOPORT_PIN_P203_PFC_00_ETHSW_TDMAOUT2 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_TDMAOUT2 1090 IOPORT_PIN_P203_PFC_01_ESC_LEDERR = (0x01U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ESC / ESC_LEDERR 1091 IOPORT_PIN_P203_PFC_02_ETHSW_PTPOUT1 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_PTPOUT1 1092 IOPORT_PIN_P204_PFC_00_ETHSW_TDMAOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_TDMAOUT3 1093 IOPORT_PIN_P204_PFC_01_ESC_LINKACT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ESC / ESC_LINKACT1 1094 IOPORT_PIN_P204_PFC_02_ETHSW_PTPOUT0 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_PTPOUT0 1095 IOPORT_PIN_P211_PFC_00_TRACEDATA0 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_1 / TRACE / TRACEDATA0 1096 IOPORT_PIN_P211_PFC_01_D0 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_1 / BSC / D0 1097 IOPORT_PIN_P211_PFC_02_MTIOC6A = (0x02U << IOPORT_PFC_OFFSET), ///< P21_1 / MTU3n / MTIOC6A 1098 IOPORT_PIN_P211_PFC_03_GTIOC14A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_1 / GPTn / GTIOC14A 1099 IOPORT_PIN_P211_PFC_04_CMTW0_TIC0 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_1 / CMTWn / CMTW0_TIC0 1100 IOPORT_PIN_P211_PFC_05_SCK5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_1 / SCIn / SCK5 1101 IOPORT_PIN_P211_PFC_06_SPI_SSL20 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_1 / SPIn / SPI_SSL20 1102 IOPORT_PIN_P211_PFC_07_IIC_SCL1 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_1 / IICn / IIC_SCL1 1103 IOPORT_PIN_P211_PFC_08_MCLK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_1 / DSMIFn / MCLK0 1104 IOPORT_PIN_P211_PFC_0A_ESC_SYNC0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_1 / ETHER_ESC / ESC_SYNC0 1105 IOPORT_PIN_P211_PFC_0B_ESC_SYNC1 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_1 / ETHER_ESC / ESC_SYNC1 1106 IOPORT_PIN_P211_PFC_0C_HSPI_INT = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_1 / SHOSTIF / HSPI_INT 1107 IOPORT_PIN_P211_PFC_0D_HD0 = (0x0DU << IOPORT_PFC_OFFSET), ///< P21_1 / PHOSTIF / HD0 1108 IOPORT_PIN_P212_PFC_00_TRACEDATA1 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_2 / TRACE / TRACEDATA1 1109 IOPORT_PIN_P212_PFC_01_D1 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_2 / BSC / D1 1110 IOPORT_PIN_P212_PFC_02_MTIOC6B = (0x02U << IOPORT_PFC_OFFSET), ///< P21_2 / MTU3n / MTIOC6B 1111 IOPORT_PIN_P212_PFC_03_GTIOC14B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_2 / GPTn / GTIOC14B 1112 IOPORT_PIN_P212_PFC_04_CMTW0_TIC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_2 / CMTWn / CMTW0_TIC1 1113 IOPORT_PIN_P212_PFC_05_RXD5_SCL5_MISO5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_2 / SCIn / RXD5_SCL5_MISO5 1114 IOPORT_PIN_P212_PFC_06_SPI_MISO2 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_2 / SPIn / SPI_MISO2 1115 IOPORT_PIN_P212_PFC_07_IIC_SDA1 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_2 / IICn / IIC_SDA1 1116 IOPORT_PIN_P212_PFC_08_MDAT0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_2 / DSMIFn / MDAT0 1117 IOPORT_PIN_P212_PFC_0A_ESC_SYNC0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_2 / ETHER_ESC / ESC_SYNC0 1118 IOPORT_PIN_P212_PFC_0B_ESC_SYNC1 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_2 / ETHER_ESC / ESC_SYNC1 1119 IOPORT_PIN_P212_PFC_0C_HD1 = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_2 / PHOSTIF / HD1 1120 IOPORT_PIN_P213_PFC_00_TRACEDATA2 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_3 / TRACE / TRACEDATA2 1121 IOPORT_PIN_P213_PFC_01_D2 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_3 / BSC / D2 1122 IOPORT_PIN_P213_PFC_02_MTIOC6C = (0x02U << IOPORT_PFC_OFFSET), ///< P21_3 / MTU3n / MTIOC6C 1123 IOPORT_PIN_P213_PFC_03_GTIOC15A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_3 / GPTn / GTIOC15A 1124 IOPORT_PIN_P213_PFC_04_TXD5_SDA5_MOSI5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_3 / SCIn / TXD5_SDA5_MOSI5 1125 IOPORT_PIN_P213_PFC_05_SPI_SSL33 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_3 / SPIn / SPI_SSL33 1126 IOPORT_PIN_P213_PFC_06_MCLK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_3 / DSMIFn / MCLK1 1127 IOPORT_PIN_P213_PFC_08_NMI = (0x08U << IOPORT_PFC_OFFSET), ///< P21_3 / IRQ / NMI 1128 IOPORT_PIN_P213_PFC_09_HD2 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_3 / PHOSTIF / HD2 1129 IOPORT_PIN_P214_PFC_00_TRACEDATA3 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_4 / TRACE / TRACEDATA3 1130 IOPORT_PIN_P214_PFC_01_D3 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_4 / BSC / D3 1131 IOPORT_PIN_P214_PFC_02_MTIOC6D = (0x02U << IOPORT_PFC_OFFSET), ///< P21_4 / MTU3n / MTIOC6D 1132 IOPORT_PIN_P214_PFC_03_GTIOC15B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_4 / GPTn / GTIOC15B 1133 IOPORT_PIN_P214_PFC_04_SS5_CTS5_RTS5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_4 / SCIn / SS5_CTS5_RTS5 1134 IOPORT_PIN_P214_PFC_05_SPI_SSL02 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_4 / SPIn / SPI_SSL02 1135 IOPORT_PIN_P214_PFC_06_MDAT1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_4 / DSMIFn / MDAT1 1136 IOPORT_PIN_P214_PFC_08_ETHSW_PTPOUT1 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ETHSW / ETHSW_PTPOUT1 1137 IOPORT_PIN_P214_PFC_09_ESC_SYNC0 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ESC / ESC_SYNC0 1138 IOPORT_PIN_P214_PFC_0A_ESC_SYNC1 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ESC / ESC_SYNC1 1139 IOPORT_PIN_P214_PFC_0B_HD3 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_4 / PHOSTIF / HD3 1140 IOPORT_PIN_P214_PFC_0C_MBX_HINT = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_4 / MBXSEM / MBX_HINT 1141 IOPORT_PIN_P215_PFC_00_IRQ6 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_5 / IRQ / IRQ6 1142 IOPORT_PIN_P215_PFC_01_TRACEDATA4 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_5 / TRACE / TRACEDATA4 1143 IOPORT_PIN_P215_PFC_02_D4 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_5 / BSC / D4 1144 IOPORT_PIN_P215_PFC_03_MTIOC7A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_5 / MTU3n / MTIOC7A 1145 IOPORT_PIN_P215_PFC_04_GTIOC16A = (0x04U << IOPORT_PFC_OFFSET), ///< P21_5 / GPTn / GTIOC16A 1146 IOPORT_PIN_P215_PFC_05_CMTW1_TOC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_5 / CMTWn / CMTW1_TOC1 1147 IOPORT_PIN_P215_PFC_06_ADTRG1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_5 / ADCn / ADTRG1 1148 IOPORT_PIN_P215_PFC_07_CTS5 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_5 / SCIn / CTS5 1149 IOPORT_PIN_P215_PFC_08_SPI_MISO0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_5 / SPIn / SPI_MISO0 1150 IOPORT_PIN_P215_PFC_09_MCLK2 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_5 / DSMIFn / MCLK2 1151 IOPORT_PIN_P215_PFC_0B_HD4 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_5 / PHOSTIF / HD4 1152 IOPORT_PIN_P216_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_6 / IRQ / IRQ9 1153 IOPORT_PIN_P216_PFC_01_TRACEDATA5 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_6 / TRACE / TRACEDATA5 1154 IOPORT_PIN_P216_PFC_02_D5 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_6 / BSC / D5 1155 IOPORT_PIN_P216_PFC_03_MTIOC7B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_6 / MTU3n / MTIOC7B 1156 IOPORT_PIN_P216_PFC_04_GTIOC16B = (0x04U << IOPORT_PFC_OFFSET), ///< P21_6 / GPTn / GTIOC16B 1157 IOPORT_PIN_P216_PFC_05_CTS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_6 / SCIn / CTS0 1158 IOPORT_PIN_P216_PFC_06_TEND = (0x06U << IOPORT_PFC_OFFSET), ///< P21_6 / DMAC / TEND 1159 IOPORT_PIN_P216_PFC_07_MDAT2 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_6 / DSMIFn / MDAT2 1160 IOPORT_PIN_P216_PFC_08_HD5 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_6 / PHOSTIF / HD5 1161 IOPORT_PIN_P217_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_7 / IRQ / IRQ10 1162 IOPORT_PIN_P217_PFC_01_TRACEDATA6 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_7 / TRACE / TRACEDATA6 1163 IOPORT_PIN_P217_PFC_02_D6 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_7 / BSC / D6 1164 IOPORT_PIN_P217_PFC_03_MTIOC7C = (0x03U << IOPORT_PFC_OFFSET), ///< P21_7 / MTU3n / MTIOC7C 1165 IOPORT_PIN_P217_PFC_04_GTIOC17A = (0x04U << IOPORT_PFC_OFFSET), ///< P21_7 / GPTn / GTIOC17A 1166 IOPORT_PIN_P217_PFC_05_DE0 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_7 / SCIn / DE0 1167 IOPORT_PIN_P217_PFC_06_DREQ = (0x06U << IOPORT_PFC_OFFSET), ///< P21_7 / DMAC / DREQ 1168 IOPORT_PIN_P217_PFC_07_MCLK3 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_7 / DSMIFn / MCLK3 1169 IOPORT_PIN_P217_PFC_08_HD6 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_7 / PHOSTIF / HD6 1170 IOPORT_PIN_P220_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_0 / IRQ / IRQ15 1171 IOPORT_PIN_P220_PFC_01_TRACEDATA7 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_0 / TRACE / TRACEDATA7 1172 IOPORT_PIN_P220_PFC_02_D7 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_0 / BSC / D7 1173 IOPORT_PIN_P220_PFC_03_MTIOC7D = (0x03U << IOPORT_PFC_OFFSET), ///< P22_0 / MTU3n / MTIOC7D 1174 IOPORT_PIN_P220_PFC_04_GTIOC17B = (0x04U << IOPORT_PFC_OFFSET), ///< P22_0 / GPTn / GTIOC17B 1175 IOPORT_PIN_P220_PFC_05_DE5 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_0 / SCIn / DE5 1176 IOPORT_PIN_P220_PFC_06_MDAT3 = (0x06U << IOPORT_PFC_OFFSET), ///< P22_0 / DSMIFn / MDAT3 1177 IOPORT_PIN_P220_PFC_07_HD7 = (0x07U << IOPORT_PFC_OFFSET), ///< P22_0 / PHOSTIF / HD7 1178 IOPORT_PIN_P221_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P22_1 / TRACE / TRACECTL 1179 IOPORT_PIN_P221_PFC_01_D8 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_1 / BSC / D8 1180 IOPORT_PIN_P221_PFC_02_ESC_LINKACT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_1 / ETHER_ESC / ESC_LINKACT2 1181 IOPORT_PIN_P221_PFC_03_POE4 = (0x03U << IOPORT_PFC_OFFSET), ///< P22_1 / MTU_POE3 / POE4 1182 IOPORT_PIN_P221_PFC_04_SS4_CTS4_RTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P22_1 / SCIn / SS4_CTS4_RTS4 1183 IOPORT_PIN_P221_PFC_05_HD8 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_1 / PHOSTIF / HD8 1184 IOPORT_PIN_P221_PFC_06_GTETRGB = (0x06U << IOPORT_PFC_OFFSET), ///< P22_1 / GPT_POEG / GTETRGB 1185 IOPORT_PIN_P222_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_2 / IRQ / IRQ4 1186 IOPORT_PIN_P222_PFC_01_TRACECLK = (0x01U << IOPORT_PFC_OFFSET), ///< P22_2 / TRACE / TRACECLK 1187 IOPORT_PIN_P222_PFC_02_D9 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_2 / BSC / D9 1188 IOPORT_PIN_P222_PFC_03_MTIOC8C = (0x03U << IOPORT_PFC_OFFSET), ///< P22_2 / MTU3n / MTIOC8C 1189 IOPORT_PIN_P222_PFC_04_GTETRGSA = (0x04U << IOPORT_PFC_OFFSET), ///< P22_2 / GPT_POEG / GTETRGSA 1190 IOPORT_PIN_P222_PFC_05_SPI_SSL12 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_2 / SPIn / SPI_SSL12 1191 IOPORT_PIN_P222_PFC_07_HD9 = (0x07U << IOPORT_PFC_OFFSET), ///< P22_2 / PHOSTIF / HD9 1192 IOPORT_PIN_P222_PFC_08_MCLK1 = (0x08U << IOPORT_PFC_OFFSET), ///< P22_2 / DSMIFn / MCLK1 1193 IOPORT_PIN_P223_PFC_00_D10 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_3 / BSC / D10 1194 IOPORT_PIN_P223_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P22_3 / MTU3n / MTIOC8D 1195 IOPORT_PIN_P223_PFC_02_GTETRGSB = (0x02U << IOPORT_PFC_OFFSET), ///< P22_3 / GPT_POEG / GTETRGSB 1196 IOPORT_PIN_P223_PFC_04_RXD5_SCL5_MISO5 = (0x04U << IOPORT_PFC_OFFSET), ///< P22_3 / SCIn / RXD5_SCL5_MISO5 1197 IOPORT_PIN_P223_PFC_05_HD10 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_3 / PHOSTIF / HD10 1198 IOPORT_PIN_P237_PFC_00_ETH2_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_7 / ETHER_ETHn / ETH2_RXD0 1199 IOPORT_PIN_P237_PFC_02_D11 = (0x02U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / D11 1200 IOPORT_PIN_P237_PFC_03_BS = (0x03U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / BS 1201 IOPORT_PIN_P237_PFC_04_MTIOC0A = (0x04U << IOPORT_PFC_OFFSET), ///< P23_7 / MTU3n / MTIOC0A 1202 IOPORT_PIN_P237_PFC_05_GTETRGA = (0x05U << IOPORT_PFC_OFFSET), ///< P23_7 / GPT_POEG / GTETRGA 1203 IOPORT_PIN_P237_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P23_7 / SCIn / SCK1 1204 IOPORT_PIN_P237_PFC_07_MCLK4 = (0x07U << IOPORT_PFC_OFFSET), ///< P23_7 / DSMIFn / MCLK4 1205 IOPORT_PIN_P237_PFC_09_HD11 = (0x09U << IOPORT_PFC_OFFSET), ///< P23_7 / PHOSTIF / HD11 1206 IOPORT_PIN_P240_PFC_00_ETH2_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P24_0 / ETHER_ETHn / ETH2_RXD1 1207 IOPORT_PIN_P240_PFC_02_D12 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / D12 1208 IOPORT_PIN_P240_PFC_03_CKE = (0x03U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / CKE 1209 IOPORT_PIN_P240_PFC_04_MTIOC0B = (0x04U << IOPORT_PFC_OFFSET), ///< P24_0 / MTU3n / MTIOC0B 1210 IOPORT_PIN_P240_PFC_05_GTETRGB = (0x05U << IOPORT_PFC_OFFSET), ///< P24_0 / GPT_POEG / GTETRGB 1211 IOPORT_PIN_P240_PFC_06_RXD1_SCL1_MISO1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_0 / SCIn / RXD1_SCL1_MISO1 1212 IOPORT_PIN_P240_PFC_07_DREQ = (0x07U << IOPORT_PFC_OFFSET), ///< P24_0 / DMAC / DREQ 1213 IOPORT_PIN_P240_PFC_08_MDAT4 = (0x08U << IOPORT_PFC_OFFSET), ///< P24_0 / DSMIFn / MDAT4 1214 IOPORT_PIN_P240_PFC_0A_HD12 = (0x0AU << IOPORT_PFC_OFFSET), ///< P24_0 / PHOSTIF / HD12 1215 IOPORT_PIN_P241_PFC_00_ETH2_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P24_1 / ETHER_ETHn / ETH2_RXCLK 1216 IOPORT_PIN_P241_PFC_02_D13 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / D13 1217 IOPORT_PIN_P241_PFC_03_CAS = (0x03U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / CAS 1218 IOPORT_PIN_P241_PFC_04_MTIOC0C = (0x04U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU3n / MTIOC0C 1219 IOPORT_PIN_P241_PFC_05_GTETRGC = (0x05U << IOPORT_PFC_OFFSET), ///< P24_1 / GPT_POEG / GTETRGC 1220 IOPORT_PIN_P241_PFC_06_POE8 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU_POE3 / POE8 1221 IOPORT_PIN_P241_PFC_07_MCLK5 = (0x07U << IOPORT_PFC_OFFSET), ///< P24_1 / DSMIFn / MCLK5 1222 IOPORT_PIN_P241_PFC_09_HD13 = (0x09U << IOPORT_PFC_OFFSET), ///< P24_1 / PHOSTIF / HD13 1223 IOPORT_PIN_P242_PFC_00_ETH2_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P24_2 / ETHER_ETHn / ETH2_RXD2 1224 IOPORT_PIN_P242_PFC_02_D14 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / D14 1225 IOPORT_PIN_P242_PFC_03_RAS = (0x03U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / RAS 1226 IOPORT_PIN_P242_PFC_04_MTIOC0D = (0x04U << IOPORT_PFC_OFFSET), ///< P24_2 / MTU3n / MTIOC0D 1227 IOPORT_PIN_P242_PFC_05_GTETRGD = (0x05U << IOPORT_PFC_OFFSET), ///< P24_2 / GPT_POEG / GTETRGD 1228 IOPORT_PIN_P242_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_2 / SCIn / TXD1_SDA1_MOSI1 1229 IOPORT_PIN_P242_PFC_07_MDAT5 = (0x07U << IOPORT_PFC_OFFSET), ///< P24_2 / DSMIFn / MDAT5 1230 IOPORT_PIN_P242_PFC_09_HD14 = (0x09U << IOPORT_PFC_OFFSET), ///< P24_2 / PHOSTIF / HD14 1231 1232 /** Marks end of enum - used by parameter checking */ 1233 IOPORT_PERIPHERAL_END 1234 } ioport_pin_pfc_t; 1235 1236 /** Options to configure pin functions */ 1237 typedef enum e_ioport_cfg_options 1238 { 1239 IOPORT_CFG_PORT_DIRECTION_HIZ = 0x00000000 << IOPORT_PM_OFFSET, ///< Sets the pin direction to Hi-Z 1240 IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000001 << IOPORT_PM_OFFSET, ///< Sets the pin direction to input (default) 1241 IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000002 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output 1242 IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x00000003 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output (data is input to input buffer) 1243 IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000 << IOPORT_P_OFFSET, ///< Sets the pin level to low 1244 IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001 << IOPORT_P_OFFSET, ///< Sets the pin level to high 1245 IOPORT_CFG_PORT_GPIO = 0x00000000 << IOPORT_PMC_OFFSET, ///< Enables pin to operate as an GPIO pin 1246 IOPORT_CFG_PORT_PERI = 0x00000001 << IOPORT_PMC_OFFSET, ///< Enables pin to operate as a peripheral pin 1247 IOPORT_CFG_DRIVE_LOW = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to low 1248 IOPORT_CFG_DRIVE_MID = 0x00000001 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to medium 1249 IOPORT_CFG_DRIVE_HIGH = 0x00000002 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to high 1250 IOPORT_CFG_DRIVE_UHIGH = 0x00000003 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to ultra high 1251 IOPORT_CFG_PULLUP_DOWN_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Disables the pin's pull-up / pull-down 1252 IOPORT_CFG_PULLUP_ENABLE = 0x00000004 << IOPORT_DRCTL_OFFSET, ///< Enables the pin's internal pull-up 1253 IOPORT_CFG_PULLDOWN_ENABLE = 0x00000008 << IOPORT_DRCTL_OFFSET, ///< Enables the pin's pull-down 1254 IOPORT_CFG_SCHMITT_TRIGGER_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Disables schmitt trigger input 1255 IOPORT_CFG_SCHMITT_TRIGGER_ENABLE = 0x00000010 << IOPORT_DRCTL_OFFSET, ///< Enables schmitt trigger input 1256 IOPORT_CFG_SLEW_RATE_SLOW = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Sets the slew rate to slow 1257 IOPORT_CFG_SLEW_RATE_FAST = 0x00000020 << IOPORT_DRCTL_OFFSET, ///< Sets the slew rate to fast 1258 IOPORT_CFG_REGION_SAFETY = 0x00000000 << IOPORT_RSELP_OFFSET, ///< Selects safety region 1259 IOPORT_CFG_REGION_NSAFETY = 0x00000001 << IOPORT_RSELP_OFFSET, ///< Selects non safety region 1260 IOPORT_CFG_PIM_TTL = 0x00000020, ///< This macro has been unsupported 1261 IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< This macro has been unsupported 1262 IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< This macro has been unsupported 1263 IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< This macro has been unsupported 1264 IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< This macro has been unsupported 1265 IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< This macro has been unsupported 1266 IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< This macro has been unsupported 1267 IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< This macro has been unsupported 1268 IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< This macro has been unsupported 1269 IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< This macro has been unsupported 1270 IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< This macro has been unsupported 1271 } ioport_cfg_options_t; 1272 1273 /*============================================== 1274 * POE3 API Overrides 1275 *==============================================*/ 1276 1277 /** POE3 states. */ 1278 typedef enum e_poe3_state 1279 { 1280 POE3_STATE_NO_DISABLE_REQUEST = 0, ///< Timer output is not disabled by POE3 1281 POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST = 1U, ///< Timer output disabled due to POE0# pin 1282 POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST = 1U << 1, ///< Timer output disabled due to POE4# pin 1283 POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST = 1U << 2, ///< Timer output disabled due to POE8# pin 1284 POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST = 1U << 3, ///< Timer output disabled due to POE10# pin 1285 POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST = 1U << 4, ///< Timer output disabled due to POE11# pin 1286 1287 POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 5, ///< Timer output disabled due to poe3_api_t::outputDisable() 1288 POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 6, ///< Timer output disabled due to main oscillator stop 1289 1290 POE3_STATE_DSMIF0_ERROR_REQUEST = 1U << 7, ///< Timer output disabled due to DSMIF0 error 1291 POE3_STATE_DSMIF1_ERROR_REQUEST = 1U << 8, ///< Timer output disabled due to DSMIF1 error 1292 1293 POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST = 1U << 9, ///< Timer output disabled due to output short circuit 1 1294 POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST = 1U << 10, ///< Timer output disabled due to output short circuit 2 1295 } poe3_state_t; 1296 1297 /*============================================== 1298 * POEG API Overrides 1299 *==============================================*/ 1300 1301 /** POEG states. */ 1302 typedef enum e_poeg_state 1303 { 1304 POEG_STATE_NO_DISABLE_REQUEST = 0, ///< GPT output is not disabled by POEG 1305 POEG_STATE_PIN_DISABLE_REQUEST = 1U << 0, ///< GPT output disabled due to GTETRG pin level 1306 POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST = 1U << 1, ///< GPT output disabled due to high speed analog comparator or GPT 1307 POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 2, ///< GPT output disabled due to main oscillator stop 1308 POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 3, ///< GPT output disabled due to poeg_api_t::outputDisable() 1309 1310 /** GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of 1311 * the filtered input. */ 1312 POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE = 1U << 16, 1313 POEG_STATE_DSMIF0_DISABLE_REQUEST = 1U << 24, ///< GPT output disabled due to DSMIF0 error 0 1314 POEG_STATE_DSMIF1_DISABLE_REQUEST = 1U << 25, ///< GPT output disabled due to DSMIF1 error 0 1315 } poeg_state_t; 1316 1317 /** Triggers that will disable GPT output pins. */ 1318 typedef enum e_poeg_trigger 1319 { 1320 /** Software disable is always supported with POEG. Select this option if no other triggers are used. */ 1321 POEG_TRIGGER_SOFTWARE = 0U, 1322 POEG_TRIGGER_PIN = 1U << 0, ///< Disable GPT output based on GTETRG input level 1323 POEG_TRIGGER_GPT_OUTPUT_LEVEL = 1U << 1, ///< Disable GPT output based on GPT output pin levels 1324 POEG_TRIGGER_OSCILLATION_STOP = 1U << 2, ///< Disable GPT output based on main oscillator stop 1325 POEG_TRIGGER_ACMPHS0 = 1U << 4, ///< Disable GPT output based on ACMPHS0 comparator result 1326 POEG_TRIGGER_ACMPHS1 = 1U << 5, ///< Disable GPT output based on ACMPHS1 comparator result 1327 POEG_TRIGGER_ACMPHS2 = 1U << 6, ///< Disable GPT output based on ACMPHS2 comparator result 1328 POEG_TRIGGER_ACMPHS3 = 1U << 7, ///< Disable GPT output based on ACMPHS3 comparator result 1329 POEG_TRIGGER_ACMPHS4 = 1U << 8, ///< Disable GPT output based on ACMPHS4 comparator result 1330 POEG_TRIGGER_ACMPHS5 = 1U << 9, ///< Disable GPT output based on ACMPHS5 comparator result 1331 1332 /** The GPT output pins can be disabled when DSMIF error occurs (LLPP only). */ 1333 POEG_TRIGGER_DERR0E = 1U << 22, ///< Permit output disabled by DSMIF0 error detection 1334 POEG_TRIGGER_DERR1E = 1U << 23, ///< Permit output disabled by DSMIF1 error detection 1335 } poeg_trigger_t; 1336 1337 /*============================================== 1338 * Transfer API Overrides 1339 *==============================================*/ 1340 1341 /** Events that can trigger a callback function. */ 1342 typedef enum e_transfer_event 1343 { 1344 TRANSFER_EVENT_TRANSFER_END = 0, ///< Transfer has completed. 1345 TRANSFER_EVENT_TRANSFER_ERROR = 1, ///< Transfer error has occurred. 1346 } transfer_event_t; 1347 1348 /** Transfer mode describes what will happen when a transfer request occurs. */ 1349 typedef enum e_transfer_mode 1350 { 1351 /** Normal mode. */ 1352 TRANSFER_MODE_NORMAL = 0, 1353 1354 /** Block mode. */ 1355 TRANSFER_MODE_BLOCK = 1 1356 } transfer_mode_t; 1357 1358 /** Transfer size specifies the size of each individual transfer. */ 1359 typedef enum e_transfer_size 1360 { 1361 TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value 1362 TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value 1363 TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value 1364 TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value 1365 TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value 1366 TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value 1367 TRANSFER_SIZE_64_BYTE = 6 ///< Each transfer transfers a 512-bit value 1368 } transfer_size_t; 1369 1370 /** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ 1371 typedef enum e_transfer_addr_mode 1372 { 1373 /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ 1374 TRANSFER_ADDR_MODE_INCREMENTED = 0, 1375 1376 /** Address pointer remains fixed after each transfer. */ 1377 TRANSFER_ADDR_MODE_FIXED = 1 1378 } transfer_addr_mode_t; 1379 1380 /** Callback function parameter data. */ 1381 typedef struct st_transfer_callback_args_t 1382 { 1383 transfer_event_t event; ///< Event code 1384 void const * p_context; ///< Placeholder for user data. Set in transfer_api_t::open function in ::transfer_cfg_t. 1385 } transfer_callback_args_t; 1386 1387 /** This structure specifies the properties of the transfer. */ 1388 typedef struct st_transfer_info 1389 { 1390 /** Select what happens to destination pointer after each transfer. */ 1391 transfer_addr_mode_t dest_addr_mode; 1392 1393 /** Select what happens to source pointer after each transfer. */ 1394 transfer_addr_mode_t src_addr_mode; 1395 1396 /** Select mode from @ref transfer_mode_t. */ 1397 transfer_mode_t mode; 1398 1399 /** Source pointer. */ 1400 void const * volatile p_src; 1401 1402 /** Destination pointer. */ 1403 void * volatile p_dest; 1404 1405 /** Length of each transfer. */ 1406 volatile uint32_t length; 1407 1408 /** Select number of source bytes to transfer at once. */ 1409 transfer_size_t src_size; 1410 1411 /** Select number of destination bytes to transfer at once. */ 1412 transfer_size_t dest_size; 1413 1414 /** Next1 Register set settings */ 1415 void const * p_next1_src; 1416 void * p_next1_dest; 1417 uint32_t next1_length; 1418 } transfer_info_t; 1419 1420 /*********************************************************************************************************************** 1421 * Exported global variables 1422 **********************************************************************************************************************/ 1423 1424 /*********************************************************************************************************************** 1425 * Exported global functions (to be accessed by other files) 1426 **********************************************************************************************************************/ 1427 1428 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 1429 FSP_FOOTER 1430 1431 #endif 1432
