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Searched refs:input (Results 1 – 6 of 6) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/r_sce/aes2/
Daes2_gcm_mode.c19 fsp_err_t hw_gcm_calculation (uint8_t * input, in hw_gcm_calculation() argument
42 bool src_unaligned = !HW_32BIT_ALIGNED((uint32_t) &input[0]); in hw_gcm_calculation()
44 uint8_t * buf_in = input; in hw_gcm_calculation()
46 uint8_t * p_in = input; in hw_gcm_calculation()
154 ptr = input; in hw_gcm_calculation()
/hal_renesas-latest/drivers/ra/fsp/src/r_glcdc/
Dr_glcdc.c387 …r_glcdc_graphics_layer_set(&(p_cfg->input[layer]), &(p_cfg->layer[layer]), (display_frame_layer_t)… in R_GLCDC_Open()
617 r_glcdc_graphics_layer_set(&p_cfg->input, &p_cfg->layer, layer); in R_GLCDC_LayerChange()
999 …FSP_ERROR_RETURN(0U == ((uint32_t) (p_cfg->input[layer].p_base) % GLCDC_PRV_ADDRESS_ALIGNMENT_64B), in r_glcdc_param_check_layer_setting_alignment()
1002 (((p_cfg->input[layer].hstride * in r_glcdc_param_check_layer_setting_alignment()
1003 … r_glcdc_get_bit_size(p_cfg->input[layer].format)) >> 3) % GLCDC_PRV_ADDRESS_ALIGNMENT_64B), in r_glcdc_param_check_layer_setting_alignment()
1106 if (p_cfg->input[i].p_base) in r_glcdc_open_param_check_layer_setting()
1115 uint16_t vline_size = p_cfg->input[i].vsize; in r_glcdc_open_param_check_layer_setting()
1116 if (p_cfg->input[i].lines_repeat_enable) in r_glcdc_open_param_check_layer_setting()
1118 vline_size = (uint16_t) (vline_size * p_cfg->input[i].lines_repeat_times); in r_glcdc_open_param_check_layer_setting()
1125 …FSP_ERROR_RETURN((uint16_t) 0 == ((p_cfg->input[i].hsize) % (uint16_t) 2), FSP_ERR_INVALID_LAYER_S… in r_glcdc_open_param_check_layer_setting()
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/hal_renesas-latest/drivers/ra/fsp/inc/api/
Dr_display_api.h310 display_input_cfg_t input[2]; ///< Graphics input frame setting member
332 display_input_cfg_t input; ///< Graphics input frame setting member
/hal_renesas-latest/drivers/ra/fsp/src/r_sce/aes2/adaptors/
Dhw_sce_ra_private.h157 void hw_aes_start(uint8_t * input, uint8_t * output, uint32_t block);
158 void hw_aes_ccm_mode_start(uint8_t * input, uint8_t * output, uint32_t block);
159 fsp_err_t hw_gcm_calculation(uint8_t * input,
Dr_sce_AES_adapt.c178 void hw_aes_start (uint8_t * input, uint8_t * output, uint32_t block) in hw_aes_start() argument
184 ptr = input; in hw_aes_start()
220 void hw_aes_ccm_mode_start (uint8_t * input, uint8_t * output, uint32_t block) in hw_aes_ccm_mode_start() argument
230 if (NULL != input) in hw_aes_ccm_mode_start()
232 hw_aes_set_plaintext(input); in hw_aes_ccm_mode_start()
243 input += SIZE_AES_BLOCK_BYTES; in hw_aes_ccm_mode_start()
/hal_renesas-latest/drivers/ra/
DREADME77 … Add phy_lsi_address to Ethernet phy instance control to allow the control of phy address as input.