Searched refs:iclk (Results 1 – 21 of 21) sorted by relevance
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/ |
| D | bsp_clock_cfg.h | 32 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/ |
| D | bsp_clock_cfg.h | 32 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/ |
| D | bsp_clock_cfg.h | 42 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/ |
| D | bsp_clock_cfg.h | 40 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/ |
| D | bsp_clock_cfg.h | 40 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/ |
| D | bsp_clock_cfg.h | 42 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/ |
| D | bsp_clock_cfg.h | 40 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/ |
| D | bsp_clock_cfg.h | 50 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/ |
| D | bsp_clock_cfg.h | 50 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/ |
| D | bsp_clock_cfg.h | 50 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/ |
| D | bsp_clock_cfg.h | 50 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/ |
| D | bsp_clock_cfg.h | 39 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/ |
| D | bsp_clock_cfg.h | 40 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/ |
| D | bsp_clock_cfg.h | 48 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/ |
| D | bsp_clock_cfg.h | 16 #define BSP_CFG_CLOCK_ICLK_HZ DT_PROP_OR(DT_NODELABEL(iclk), clock_frequency, 1100000000)…
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/ |
| D | bsp_clock_cfg.h | 50 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/ |
| D | bsp_clock_cfg.h | 50 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/ |
| D | bsp_clock_cfg.h | 70 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/ |
| D | bsp_clock_cfg.h | 71 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/ |
| D | bsp_clock_cfg.h | 71 #define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
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| /hal_renesas-latest/drivers/ra/fsp/src/r_iic_master/ |
| D | r_iic_master.c | 826 uint32_t iclk = sysdiccr >> 24U; in iic_master_run_hw_master() local
827 uint32_t timeout_count = ((1U << (pclkb - iclk)) * p_ctrl->p_reg->ICBRL) >> 2U; in iic_master_run_hw_master()
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