1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @ingroup RENESAS_POWER_INTERFACES 9 * @defgroup LPM_API Low Power Modes Interface 10 * @brief Interface for accessing low power modes. 11 * 12 * @section LPM_API_SUMMARY Summary 13 * This section defines the API for the LPM (Low Power Mode) Driver. 14 * The LPM Driver provides functions for controlling power consumption by configuring 15 * and transitioning to a low power mode. 16 * The LPM driver supports configuration of MCU low power modes using the LPM hardware 17 * peripheral. The LPM driver supports low power modes deep standby, standby, sleep, and snooze. 18 * 19 * @note Not all low power modes are available on all MCUs. 20 * 21 * 22 * @{ 23 **********************************************************************************************************************/ 24 #ifndef R_LPM_API_H 25 #define R_LPM_API_H 26 27 /*********************************************************************************************************************** 28 * Includes 29 **********************************************************************************************************************/ 30 31 /* Register definitions, common services and error codes. */ 32 #include "bsp_api.h" 33 34 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 35 FSP_HEADER 36 37 /********************************************************************************************************************** 38 * Macro definitions 39 **********************************************************************************************************************/ 40 41 /********************************************************************************************************************** 42 * Typedef definitions 43 **********************************************************************************************************************/ 44 45 /** Low power modes */ 46 typedef enum e_lpm_mode 47 { 48 LPM_MODE_SLEEP, ///< Sleep mode 49 LPM_MODE_DEEP_SLEEP, ///< Deep Sleep mode 50 LPM_MODE_STANDBY, ///< Software Standby mode 51 LPM_MODE_STANDBY_SNOOZE, ///< Software Standby mode with Snooze mode enabled 52 LPM_MODE_DEEP, ///< Deep Software Standby mode 53 } lpm_mode_t; 54 55 #ifndef BSP_OVERRIDE_LPM_SNOOZE_REQUEST_T 56 57 /** Snooze request sources */ 58 typedef enum e_lpm_snooze_request 59 { 60 LPM_SNOOZE_REQUEST_RXD0_FALLING = 0x00000000ULL, ///< Enable RXD0 falling edge snooze request 61 LPM_SNOOZE_REQUEST_IRQ0 = 0x00000001ULL, ///< Enable IRQ0 pin snooze request 62 LPM_SNOOZE_REQUEST_IRQ1 = 0x00000002ULL, ///< Enable IRQ1 pin snooze request 63 LPM_SNOOZE_REQUEST_IRQ2 = 0x00000004ULL, ///< Enable IRQ2 pin snooze request 64 LPM_SNOOZE_REQUEST_IRQ3 = 0x00000008ULL, ///< Enable IRQ3 pin snooze request 65 LPM_SNOOZE_REQUEST_IRQ4 = 0x00000010ULL, ///< Enable IRQ4 pin snooze request 66 LPM_SNOOZE_REQUEST_IRQ5 = 0x00000020ULL, ///< Enable IRQ5 pin snooze request 67 LPM_SNOOZE_REQUEST_IRQ6 = 0x00000040ULL, ///< Enable IRQ6 pin snooze request 68 LPM_SNOOZE_REQUEST_IRQ7 = 0x00000080ULL, ///< Enable IRQ7 pin snooze request 69 LPM_SNOOZE_REQUEST_IRQ8 = 0x00000100ULL, ///< Enable IRQ8 pin snooze request 70 LPM_SNOOZE_REQUEST_IRQ9 = 0x00000200ULL, ///< Enable IRQ9 pin snooze request 71 LPM_SNOOZE_REQUEST_IRQ10 = 0x00000400ULL, ///< Enable IRQ10 pin snooze request 72 LPM_SNOOZE_REQUEST_IRQ11 = 0x00000800ULL, ///< Enable IRQ11 pin snooze request 73 LPM_SNOOZE_REQUEST_IRQ12 = 0x00001000ULL, ///< Enable IRQ12 pin snooze request 74 LPM_SNOOZE_REQUEST_IRQ13 = 0x00002000ULL, ///< Enable IRQ13 pin snooze request 75 LPM_SNOOZE_REQUEST_IRQ14 = 0x00004000ULL, ///< Enable IRQ14 pin snooze request 76 LPM_SNOOZE_REQUEST_IRQ15 = 0x00008000ULL, ///< Enable IRQ15 pin snooze request 77 LPM_SNOOZE_REQUEST_KEY = 0x00020000ULL, ///< Enable KR snooze request 78 LPM_SNOOZE_REQUEST_ACMPHS0 = 0x00400000ULL, ///< Enable High-speed analog comparator 0 snooze request 79 LPM_SNOOZE_REQUEST_RTC_ALARM1 = 0x00800000ULL, ///< Enable RTC alarm 1 snooze request 80 LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000ULL, ///< Enable RTC alarm snooze request 81 LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000ULL, ///< Enable RTC period snooze request 82 LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000ULL, ///< Enable AGT1 underflow snooze request 83 LPM_SNOOZE_REQUEST_AGTW1_UNDERFLOW = 0x10000000ULL, ///< Enable AGTW1 underflow snooze request 84 LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000ULL, ///< Enable AGT1 compare match A snooze request 85 LPM_SNOOZE_REQUEST_AGTW1_COMPARE_A = 0x20000000ULL, ///< Enable AGTW1 compare match A snooze request 86 LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000ULL, ///< Enable AGT1 compare match B snooze request 87 LPM_SNOOZE_REQUEST_AGTW1_COMPARE_B = 0x40000000ULL, ///< Enable AGTW1 compare match B snooze request 88 LPM_SNOOZE_REQUEST_AGT3_UNDERFLOW = 0x100000000ULL, ///< Enable AGT3 underflow snooze request 89 LPM_SNOOZE_REQUEST_AGT3_COMPARE_A = 0x200000000ULL, ///< Enable AGT3 compare match A snooze request 90 LPM_SNOOZE_REQUEST_AGT3_COMPARE_B = 0x400000000ULL, ///< Enable AGT3 compare match B snooze request 91 } lpm_snooze_request_t; 92 #endif 93 94 #ifndef BSP_OVERRIDE_LPM_SNOOZE_END_T 95 96 /** Snooze end control */ 97 typedef enum e_lpm_snooze_end 98 { 99 LPM_SNOOZE_END_STANDBY_WAKE_SOURCES = 0x00U, ///< Transition from Snooze to Normal mode directly 100 LPM_SNOOZE_END_AGT1_UNDERFLOW = 0x01U, ///< AGT1 underflow 101 LPM_SNOOZE_END_AGTW1_UNDERFLOW = 0x01U, ///< AGTW1 underflow 102 LPM_SNOOZE_END_DTC_TRANS_COMPLETE = 0x02U, ///< Last DTC transmission completion 103 LPM_SNOOZE_END_DTC_TRANS_COMPLETE_NEGATED = 0x04U, ///< Not Last DTC transmission completion 104 LPM_SNOOZE_END_ADC0_COMPARE_MATCH = 0x08U, ///< ADC Channel 0 compare match 105 LPM_SNOOZE_END_ADC0_COMPARE_MISMATCH = 0x10U, ///< ADC Channel 0 compare mismatch 106 LPM_SNOOZE_END_ADC1_COMPARE_MATCH = 0x20U, ///< ADC 1 compare match 107 LPM_SNOOZE_END_ADC1_COMPARE_MISMATCH = 0x40U, ///< ADC 1 compare mismatch 108 LPM_SNOOZE_END_SCI0_ADDRESS_MATCH = 0x80U, ///< SCI0 address mismatch 109 LPM_SNOOZE_END_AGT3_UNDERFLOW = 0x100U, ///< AGT3 underflow 110 } lpm_snooze_end_t; 111 112 typedef uint16_t lpm_snooze_end_bits_t; 113 #endif 114 115 #ifndef BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T 116 117 /** Snooze cancel control */ 118 typedef enum e_lpm_snooze_cancel 119 { 120 LPM_SNOOZE_CANCEL_SOURCE_NONE = ELC_EVENT_NONE, ///< No snooze cancel source 121 LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPM = ELC_EVENT_ADC0_COMPARE_MATCH, ///< ADC Channel 0 window compare match 122 #if (2U != BSP_FEATURE_ELC_VERSION) 123 LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPUM = ELC_EVENT_ADC0_COMPARE_MISMATCH, ///< ADC Channel 0 window compare mismatch 124 #endif 125 #if BSP_FEATURE_ADC_VALID_UNIT_MASK & (1U << 1) // If ADC has unit 1 126 LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPM = ELC_EVENT_ADC1_COMPARE_MATCH, ///< ADC Channel 1 window compare match 127 #if (2U != BSP_FEATURE_ELC_VERSION) 128 LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPUM = ELC_EVENT_ADC1_COMPARE_MISMATCH, ///< ADC Channel 1 window compare mismatch 129 #endif 130 #endif 131 #if (BSP_FEATURE_SCI_CHANNELS & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0 132 LPM_SNOOZE_CANCEL_SOURCE_SCI0_AM = ELC_EVENT_SCI0_AM, ///< SCI0 address match event 133 LPM_SNOOZE_CANCEL_SOURCE_SCI0_RXI_OR_ERI = ELC_EVENT_SCI0_RXI_OR_ERI, ///< SCI0 receive error 134 #endif 135 LPM_SNOOZE_CANCEL_SOURCE_DTC_COMPLETE = ELC_EVENT_DTC_COMPLETE, ///< DTC transfer completion 136 LPM_SNOOZE_CANCEL_SOURCE_DOC_DOPCI = ELC_EVENT_DOC_INT, ///< Data operation circuit interrupt 137 #if BSP_FEATURE_CTSU_VERSION 138 LPM_SNOOZE_CANCEL_SOURCE_CTSU_CTSUFN = ELC_EVENT_CTSU_END, ///< CTSU measurement end interrupt 139 #endif 140 } lpm_snooze_cancel_t; 141 #endif 142 143 /** DTC Enable in Snooze Mode */ 144 typedef enum e_lpm_snooze_dtc 145 { 146 LPM_SNOOZE_DTC_DISABLE = 0U, ///< Disable DTC operation 147 LPM_SNOOZE_DTC_ENABLE = 1U, ///< Enable DTC operation 148 } lpm_snooze_dtc_t; 149 150 #ifndef BSP_OVERRIDE_LPM_STANDBY_WAKE_SOURCE_T 151 152 /** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ 153 typedef enum e_lpm_standby_wake_source 154 { 155 LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 156 LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 157 LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 158 LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 159 LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 160 LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 161 LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 162 LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 163 LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 164 LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 165 LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 166 LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 167 LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 168 LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 169 LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 170 LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 171 LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt 172 LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt 173 LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt 174 LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt 175 LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt 176 LPM_STANDBY_WAKE_SOURCE_VRTC = 0x00200000ULL, ///< LVDVRTC interrupt 177 LPM_STANDBY_WAKE_SOURCE_EXLVD = 0x00400000ULL, ///< LVDEXLVD interrupt 178 LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt 179 LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt 180 LPM_STANDBY_WAKE_SOURCE_RTCALM1 = 0x00800000ULL, ///< RTC Alarm interrupt 1 181 LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt 182 LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt 183 LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt 184 LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt 185 LPM_STANDBY_WAKE_SOURCE_AGTW0UD = 0x08000000ULL, ///< AGTW0 Underflow interrupt 186 LPM_STANDBY_WAKE_SOURCE_AGTW1UD = 0x10000000ULL, ///< AGTW1 Underflow interrupt 187 LPM_STANDBY_WAKE_SOURCE_AGTW1CA = 0x20000000ULL, ///< AGTW1 Compare Match A interrupt 188 LPM_STANDBY_WAKE_SOURCE_AGTW1CB = 0x40000000ULL, ///< AGTW1 Compare Match B interrupt 189 LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 Underflow interrupt 190 LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 Compare Match A interrupt 191 LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 Compare Match B interrupt 192 LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt 193 LPM_STANDBY_WAKE_SOURCE_AGT0UD = 0x100000000ULL, ///< AGT0 Underflow interrupt 194 LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 Underflow interrupt 195 LPM_STANDBY_WAKE_SOURCE_AGT1UD_S = 0x200000000ULL, ///< AGT1 Underflow interrupt for specific board 196 LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 Compare Match A interrupt 197 LPM_STANDBY_WAKE_SOURCE_AGT2UD = 0x400000000ULL, ///< AGT2 Underflow interrupt 198 LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 Compare Match B interrupt 199 LPM_STANDBY_WAKE_SOURCE_AGT3UD_S = 0x800000000ULL, ///< AGT3 Underflow interrupt for specific board 200 LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt 201 LPM_STANDBY_WAKE_SOURCE_AGT4UD = 0x1000000000ULL, ///< AGT4 Underflow interrupt 202 LPM_STANDBY_WAKE_SOURCE_AGT5UD = 0x2000000000ULL, ///< AGT5 Underflow interrupt 203 LPM_STANDBY_WAKE_SOURCE_AGT6UD = 0x4000000000ULL, ///< AGT6 Underflow interrupt 204 LPM_STANDBY_WAKE_SOURCE_AGT7UD = 0x8000000000ULL, ///< AGT7 Underflow interrupt 205 LPM_STANDBY_WAKE_SOURCE_SOSTD = 0x10000000000ULL, ///< SOSTD interrupt 206 LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt 207 LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt 208 LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt 209 LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL, ///< I3C0 address match interrupt 210 LPM_STANDBY_WAKE_SOURCE_ULP1U = 0x100000000000ULL, ///< ULPT1 Underflow Interrupt 211 LPM_STANDBY_WAKE_SOURCE_ULP1A = 0x200000000000ULL, ///< ULPT1 Compare Match A Interrupt 212 LPM_STANDBY_WAKE_SOURCE_ULP1B = 0x400000000000ULL, ///< ULPT1 Compare Match B Interrupt 213 } lpm_standby_wake_source_t; 214 215 typedef uint64_t lpm_standby_wake_source_bits_t; 216 #endif 217 218 /** I/O port state after Deep Software Standby mode */ 219 typedef enum e_lpm_io_port 220 { 221 /** 222 * When the Deep Software Standby mode is canceled, the I/O ports are in the reset state 223 */ 224 LPM_IO_PORT_RESET = 0U, 225 226 /** 227 * When the Deep Software Standby mode is canceled, the I/O ports are in the same state as 228 * in the Deep Software Standby mode 229 */ 230 LPM_IO_PORT_NO_CHANGE = 1U, 231 } lpm_io_port_t; 232 233 /** Power supply control */ 234 typedef enum e_lpm_power_supply 235 { 236 /** 237 * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume 238 * detecting unit is supplied in deep software standby mode 239 */ 240 LPM_POWER_SUPPLY_DEEPCUT0 = 0U, 241 242 /** 243 * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume 244 * detecting unit is not supplied in deep software standby mode 245 */ 246 LPM_POWER_SUPPLY_DEEPCUT1 = 1U, 247 248 /** 249 * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume 250 * detecting unit is not supplied in deep software standby mode. In addition, LVD is 251 * disabled and the low power function in a poweron reset circuit is enabled 252 */ 253 LPM_POWER_SUPPLY_DEEPCUT3 = 3UL, 254 255 /** 256 * Power to the standby RAM, Low-speed on-chip oscillator, Programmable Voltage Detection Unit 0, 257 * and USBFS/HS resume detecting unit is supplied in deep software standby mode. 258 */ 259 LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1 = 0U, 260 261 /** 262 * Power to standby RAM, USBFS/HS resume detecting unit, Low-speed on-chip oscillator, and IWDT is 263 * disabled in deep software standby mode. Power to the Programmable Voltage Detection Unit 0 is 264 * supplied in deep software standby mode. 265 */ 266 LPM_POWER_SUPPLY_DEEP_STANDBY_MODE2 = 1U, 267 268 /** 269 * Power to standby RAM, Programmable Voltage Detection Unit 0, USBFS/HS resume detecting unit, 270 * Low-speed on-chip oscillator, and IWDT is disabled in deep software standby mode. 271 */ 272 LPM_POWER_SUPPLY_DEEP_STANDBY_MODE3 = 2U, 273 } lpm_power_supply_t; 274 275 /** Deep Standby Interrupt Edge */ 276 typedef enum e_lpm_deep_standby_cancel_edge 277 { 278 LPM_DEEP_STANDBY_CANCEL_SOURCE_EDGE_NONE = 0U, ///< No options for a deep standby cancel source 279 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0_RISING = 0x00000001U, ///< IRQ0-DS Pin Rising Edge 280 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0_FALLING = 0U, ///< IRQ0-DS Pin Falling Edge 281 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1_RISING = 0x00000002U, ///< IRQ1-DS Pin Rising Edge 282 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1_FALLING = 0U, ///< IRQ1-DS Pin Falling Edge 283 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2_RISING = 0x00000004U, ///< IRQ2-DS Pin Rising Edge 284 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2_FALLING = 0U, ///< IRQ2-DS Pin Falling Edge 285 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3_RISING = 0x00000008U, ///< IRQ3-DS Pin Rising Edge 286 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3_FALLING = 0U, ///< IRQ3-DS Pin Falling Edge 287 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4_RISING = 0x00000010U, ///< IRQ4-DS Pin Rising Edge 288 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4_FALLING = 0U, ///< IRQ4-DS Pin Falling Edge 289 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5_RISING = 0x00000020U, ///< IRQ5-DS Pin Rising Edge 290 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5_FALLING = 0U, ///< IRQ5-DS Pin Falling Edge 291 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6_RISING = 0x00000040U, ///< IRQ6-DS Pin Rising Edge 292 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6_FALLING = 0U, ///< IRQ6-DS Pin Falling Edge 293 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7_RISING = 0x00000080U, ///< IRQ7-DS Pin Rising Edge 294 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7_FALLING = 0U, ///< IRQ7-DS Pin Falling Edge 295 296 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8_RISING = 0x00000100U, ///< IRQ8-DS Pin Rising Edge 297 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8_FALLING = 0U, ///< IRQ8-DS Pin Falling Edge 298 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9_RISING = 0x00000200U, ///< IRQ9-DS Pin Rising Edge 299 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9_FALLING = 0U, ///< IRQ9-DS Pin Falling Edge 300 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10_RISING = 0x00000400U, ///< IRQ10-DS Pin Rising Edge 301 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10_FALLING = 0U, ///< IRQ10-DS Pin Falling Edge 302 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11_RISING = 0x00000800U, ///< IRQ11-DS Pin Rising Edge 303 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11_FALLING = 0U, ///< IRQ11-DS Pin Falling Edge 304 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12_RISING = 0x00001000U, ///< IRQ12-DS Pin Rising Edge 305 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12_FALLING = 0U, ///< IRQ12-DS Pin Falling Edge 306 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_RISING = 0x00002000U, ///< IRQ13-DS Pin Rising Edge 307 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_FALLING = 0U, ///< IRQ13-DS Pin Falling Edge 308 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_RISING = 0x00004000U, ///< IRQ14-DS Pin Rising Edge 309 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_FALLING = 0U, ///< IRQ14-DS Pin Falling Edge 310 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_RISING = 0x00008000U, ///< IRQ14-DS Pin Rising Edge 311 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_FALLING = 0U, ///< IRQ14-DS Pin Falling Edge 312 313 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_RISING = 0x00010000U, ///< LVD1 Rising Slope 314 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_FALLING = 0U, ///< LVD1 Falling Slope 315 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2_RISING = 0x00020000U, ///< LVD2 Rising Slope 316 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2_FALLING = 0U, ///< LVD2 Falling Slope 317 LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI_RISING = 0x00100000U, ///< NMI Pin Rising Edge 318 LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI_FALLING = 0U, ///< NMI Pin Falling Edge 319 } lpm_deep_standby_cancel_edge_t; 320 321 typedef uint32_t lpm_deep_standby_cancel_edge_bits_t; 322 323 #ifndef BSP_OVERRIDE_LPM_DEEP_STANDBY_WAKE_SOURCE_T 324 325 /** Deep Standby cancel sources */ 326 typedef enum e_lpm_deep_standby_cancel_source 327 { 328 LPM_DEEP_STANDBY_CANCEL_SOURCE_RESET_ONLY = 0U, ///< Cancel deep standby only by reset 329 330 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0 = 0x00000001U, ///< IRQ0 331 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1 = 0x00000002U, ///< IRQ1 332 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2 = 0x00000004U, ///< IRQ2 333 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3 = 0x00000008U, ///< IRQ3 334 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4 = 0x00000010U, ///< IRQ4 335 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5 = 0x00000020U, ///< IRQ5 336 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6 = 0x00000040U, ///< IRQ6 337 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7 = 0x00000080U, ///< IRQ7 338 339 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8 = 0x00000100U, ///< IRQ8 340 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9 = 0x00000200U, ///< IRQ9 341 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10 = 0x00000400U, ///< IRQ10 342 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11 = 0x00000800U, ///< IRQ11 343 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12 = 0x00001000U, ///< IRQ12 344 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13 = 0x00002000U, ///< IRQ13 345 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14 = 0x00004000U, ///< IRQ14 346 LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15 = 0x00008000U, ///< IRQ15 347 348 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1 = 0x00010000U, ///< LVD1 349 LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2 = 0x00020000U, ///< LVD2 350 LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_INTERVAL = 0x00040000U, ///< RTC Interval Interrupt 351 LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_ALARM = 0x00080000U, ///< RTC Alarm Interrupt 352 LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI = 0x00100000U, ///< NMI 353 354 LPM_DEEP_STANDBY_CANCEL_SOURCE_USBFS = 0x01000000U, ///< USBFS Suspend/Resume 355 LPM_DEEP_STANDBY_CANCEL_SOURCE_USBHS = 0x02000000U, ///< USBHS Suspend/Resume 356 LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT1 = 0x04000000U, ///< AGT1 Underflow 357 LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT3 = 0x08000000U, ///< AGT3 Underflow 358 LPM_DEEP_STANDBY_CANCEL_SOURCE_ULPT0 = 0x04000000U, ///< ULPT0 Overflow 359 LPM_DEEP_STANDBY_CANCEL_SOURCE_ULPT1 = 0x08000000U, ///< ULPT1 Overflow 360 LPM_DEEP_STANDBY_CANCEL_SOURCE_IWDT = 0x20000000U, ///< IWDT Underflow 361 LPM_DEEP_STANDBY_CANCEL_SOURCE_VBATT = 0x80000000U, ///< VBATT Tamper Detection 362 } lpm_deep_standby_cancel_source_t; 363 #endif 364 365 typedef uint32_t lpm_deep_standby_cancel_source_bits_t; 366 367 /** Output port enable */ 368 typedef enum e_lpm_output_port_enable 369 { 370 /** 371 * 0: In Software Standby Mode or Deep Software Standby Mode, the 372 * address output pins, data output pins, and other bus control signal 373 * output pins are set to the high-impedance state. In Snooze, the 374 * status of the address bus and bus control signals are same as 375 * before entering Software Standby Mode. 376 */ 377 LPM_OUTPUT_PORT_ENABLE_HIGH_IMPEDANCE = 0U, 378 379 /** 380 * 1: In Software Standby Mode, the address output pins, data output 381 * pins, and other bus control signal output pins retain the 382 * output state. 383 */ 384 LPM_OUTPUT_PORT_ENABLE_RETAIN = 1U, 385 } lpm_output_port_enable_t; 386 387 /** Configure the behavior of an oscillator's LDO in standby mode. */ 388 typedef enum e_lpm_ldo_standby_operation 389 { 390 /** The LDO is disabled in standby mode. */ 391 LPM_LDO_STANDBY_OPERATION_DISABLED, 392 393 /** The LDO state is retained during standby mode. */ 394 LPM_LDO_STANDBY_OPERATION_RETAINED, 395 } lpm_ldo_standby_operation_t; 396 397 #if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP 398 399 /** RAM Retention Configuration for deep sleep and standby modes. */ 400 typedef struct s_lpm_ram_retention 401 { 402 #if BSP_FEATURE_LPM_HAS_PDRAMSCR 403 404 /** Configure RAM retention in software standby mode. */ 405 uint16_t ram_retention; 406 407 /** Enable or disable TCM retention in deep sleep and software standby modes. */ 408 bool tcm_retention; 409 #endif 410 #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP 411 412 /** Enable Standby RAM retention in software standby and deep software standby modes. */ 413 bool standby_ram_retention; 414 #endif 415 } lpm_ram_retention_t; 416 #endif 417 418 /** Flash operating mode select. */ 419 typedef enum e_lpm_flash_mode_select 420 { 421 LPM_FLASH_MODE_SELECT_ACTIVE = 0U, ///< Flash active 422 LPM_FLASH_MODE_SELECT_STOP = 1U, ///< Flash stop 423 } lpm_flash_mode_select_t; 424 425 /** Starting the high-speed on-chip oscillator at the times of release from SSTBY mode and of transitions to SNOOZE mode. */ 426 typedef enum e_lpm_hoco_startup_speed 427 { 428 LPM_HOCO_STARTUP_SPEED_NORMAL_SPEED = 0U, ///< Starting of the high-speed on-chip oscillator is at normal speed 429 LPM_HOCO_STARTUP_SPEED_HIGH_SPEED = 1U, ///< Starting of the high-speed on-chip oscillator is at high speed 430 } lpm_hoco_startup_speed_t; 431 432 /** SOSC setting in SSTBY mode or in SNOOZE mode. */ 433 typedef enum e_lpm_standby_sosc 434 { 435 LPM_STANDBY_SOSC_ENABLE = 0U, ///< Enables supply of SOSC clock to peripheral functions 436 LPM_STANDBY_SOSC_DISABLE = 1U, ///< Stops supply SOSC clock to peripheral functions other than the Realtime clock. 437 } lpm_standby_sosc_t; 438 439 /** Configure LDO operation in standby mode. */ 440 typedef struct lpm_ldo_standby_cfg_s 441 { 442 lpm_ldo_standby_operation_t pll1_ldo; ///< Configure the state of PLL1 LDO in standby mode. 443 lpm_ldo_standby_operation_t pll2_ldo; ///< Configure the state of PLL2 LDO in standby mode. 444 lpm_ldo_standby_operation_t hoco_ldo; ///< Configure the state of HOCO LDO in standby mode. 445 } lpm_ldo_standby_cfg_t; 446 447 /** User configuration structure, used in open function */ 448 typedef struct st_lpm_cfg 449 { 450 /** Low Power Mode */ 451 lpm_mode_t low_power_mode; 452 453 /** Bitwise list of sources to wake from deep sleep and standby mode */ 454 lpm_standby_wake_source_bits_t standby_wake_sources; 455 456 #if BSP_FEATURE_LPM_HAS_SNOOZE 457 458 /** Snooze request source */ 459 lpm_snooze_request_t snooze_request_source; 460 461 /** Bitwise list of snooze end sources */ 462 lpm_snooze_end_bits_t snooze_end_sources; 463 464 #ifndef BSP_OVERRIDE_LPM_SNOOZE_CANCEL_T 465 466 /** List of snooze cancel sources */ 467 lpm_snooze_cancel_t snooze_cancel_sources; 468 #else 469 lpm_snooze_cancel_source_bits_t snooze_cancel_sources; 470 #endif 471 #endif 472 473 /** State of DTC in snooze mode, enabled or disabled */ 474 lpm_snooze_dtc_t dtc_state_in_snooze; 475 #if BSP_FEATURE_LPM_HAS_SBYCR_OPE 476 477 /** Output port enabled/disabled in standby and deep standby */ 478 lpm_output_port_enable_t output_port_enable; 479 #endif 480 #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY 481 482 /** IO port state in deep standby (maintained or reset) */ 483 lpm_io_port_t io_port_state; 484 485 /** Internal power supply state in standby and deep standby (deepcut) */ 486 lpm_power_supply_t power_supply_state; 487 488 /** Sources that can trigger exit from deep standby */ 489 lpm_deep_standby_cancel_source_bits_t deep_standby_cancel_source; 490 491 /** Signal edges for the sources that can trigger exit from deep standby */ 492 lpm_deep_standby_cancel_edge_bits_t deep_standby_cancel_edge; 493 #endif 494 495 #if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP 496 497 /** RAM retention configuration for deep sleep and standby modes. */ 498 lpm_ram_retention_t ram_retention_cfg; 499 #endif 500 501 #if BSP_FEATURE_LPM_HAS_LDO_CONTROL 502 503 /** Configure LDOs that are disabled in standby mode. */ 504 lpm_ldo_standby_cfg_t ldo_standby_cfg; 505 #endif 506 507 #if BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT 508 509 /** Flash mode in sleep mode or in snooze mode. */ 510 lpm_flash_mode_select_t lpm_flash_mode_select; 511 #endif 512 513 #if BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE 514 515 /** Startup speed of high-speed on-chip oscillator when exiting software standby mode or entering snooze mode. */ 516 lpm_hoco_startup_speed_t lpm_hoco_startup_speed; 517 #endif 518 519 #if BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT 520 521 /** SOSC setting in SSTBY mode or in SNOOZE mode. */ 522 lpm_standby_sosc_t lpm_standby_sosc; 523 #endif 524 525 /** Placeholder for extension. */ 526 void const * p_extend; 527 } lpm_cfg_t; 528 529 /** LPM control block. Allocate an instance specific control block to pass into the LPM API calls. 530 */ 531 typedef void lpm_ctrl_t; 532 533 /** LPM driver structure. General LPM functions implemented at the HAL layer will follow this API. */ 534 typedef struct st_lpm_api 535 { 536 /** Initialization function 537 **/ 538 539 fsp_err_t (* open)(lpm_ctrl_t * const p_ctrl, lpm_cfg_t const * const p_cfg); 540 541 /** Initialization function 542 **/ 543 fsp_err_t (* close)(lpm_ctrl_t * const p_ctrl); 544 545 /** Configure a low power mode. 546 * 547 * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. 548 **/ 549 fsp_err_t (* lowPowerReconfigure)(lpm_ctrl_t * const p_ctrl, lpm_cfg_t const * const p_cfg); 550 551 /** Enter low power mode (sleep/standby/deep standby) using WFI macro. 552 * Function will return after waking from low power mode. 553 **/ 554 fsp_err_t (* lowPowerModeEnter)(lpm_ctrl_t * const p_ctrl); 555 556 /** Clear the IOKEEP bit after deep software standby. 557 **/ 558 fsp_err_t (* ioKeepClear)(lpm_ctrl_t * const p_ctrl); 559 } lpm_api_t; 560 561 /** This structure encompasses everything that is needed to use an instance of this interface. */ 562 typedef struct st_lpm_instance 563 { 564 lpm_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 565 lpm_cfg_t const * const p_cfg; ///< Pointer to the configuration structure for this instance 566 lpm_api_t const * const p_api; ///< Pointer to the API structure for this instance 567 } lpm_instance_t; 568 569 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 570 FSP_FOOTER 571 572 #endif 573 574 /*******************************************************************************************************************//** 575 * @} (end defgroup LPM_API) 576 **********************************************************************************************************************/ 577
