Searched refs:clk_phase (Results 1 – 5 of 5) sorted by relevance
158 spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge member
171 spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge member
168 FSP_ERROR_RETURN(SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase, FSP_ERR_UNSUPPORTED); in R_SPI_Open()560 spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI0_SPCMD0_CPHA_Pos; in r_spi_hw_config()
525 spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI_B0_SPCMD0_CPHA_Pos; in r_spi_b_hw_config()
540 if (SPI_CLK_PHASE_EDGE_EVEN == p_ctrl->p_cfg->clk_phase) in r_rspi_hw_config()
