1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * @file     ./out/R7FA6M3AH.h
7  * @brief    CMSIS HeaderFile
8  * @version  1.2
9  */
10 
11 /** @addtogroup Renesas
12  * @{
13  */
14 
15 /** @addtogroup R7FA6M3AH
16  * @{
17  */
18 
19 #ifndef R7FA6M3AH_H
20  #define R7FA6M3AH_H
21 
22  #ifdef __cplusplus
23 extern "C" {
24  #endif
25 
26 /** @addtogroup Configuration_of_CMSIS
27  * @{
28  */
29 
30 /* =========================================================================================================================== */
31 /* ================                                Interrupt Number Definition                                ================ */
32 /* =========================================================================================================================== */
33 
34 /* =========================================================================================================================== */
35 /* ================                           Processor and Core Peripheral Section                           ================ */
36 /* =========================================================================================================================== */
37 
38 /* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
39  #define __CM4_REV                 0x0001U /*!< CM4 Core Revision                                                         */
40  #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
41  #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
42  #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
43  #define __MPU_PRESENT             1       /*!< MPU present                                                               */
44  #define __FPU_PRESENT             1       /*!< FPU present                                                               */
45 
46 /** @} */ /* End of group Configuration_of_CMSIS */
47 
48  #include "core_cm4.h"                     /*!< ARM Cortex-M4 processor and core peripherals                              */
49  #include "system.h"                       /*!< R7FA6M3AH System                                                          */
50 
51  #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
52   #define __IM     __I
53  #endif
54  #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
55   #define __OM     __O
56  #endif
57  #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
58   #define __IOM    __IO
59  #endif
60 
61 /* ========================================  Start of section using anonymous unions  ======================================== */
62  #if defined(__CC_ARM)
63   #pragma push
64   #pragma anon_unions
65  #elif defined(__ICCARM__)
66   #pragma language=extended
67  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
68   #pragma clang diagnostic push
69   #pragma clang diagnostic ignored "-Wc11-extensions"
70   #pragma clang diagnostic ignored "-Wreserved-id-macro"
71   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
72   #pragma clang diagnostic ignored "-Wnested-anon-types"
73  #elif defined(__GNUC__)
74 
75 /* anonymous unions are enabled by default */
76  #elif defined(__TMS470__)
77 
78 /* anonymous unions are enabled by default */
79  #elif defined(__TASKING__)
80   #pragma warning 586
81  #elif defined(__CSMC__)
82 
83 /* anonymous unions are enabled by default */
84  #else
85   #warning Not supported compiler type
86  #endif
87 
88 /* =========================================================================================================================== */
89 /* ================                              Device Specific Cluster Section                              ================ */
90 /* =========================================================================================================================== */
91 
92 /** @addtogroup Device_Peripheral_clusters
93  * @{
94  */
95 
96 /**
97  * @brief R_BUS_CSa [CSa] (CS Registers)
98  */
99 typedef struct
100 {
101     __IM uint16_t RESERVED;
102 
103     union
104     {
105         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
106 
107         struct
108         {
109             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
110             uint16_t             : 2;
111             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
112             uint16_t             : 4;
113             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
114             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
115             uint16_t             : 5;
116             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
117         } MOD_b;
118     };
119 
120     union
121     {
122         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
123 
124         struct
125         {
126             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
127             uint32_t                : 5;
128             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
129             uint32_t                : 5;
130             __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
131             uint32_t                : 3;
132             __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
133             uint32_t                : 3;
134         } WCR1_b;
135     };
136 
137     union
138     {
139         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
140 
141         struct
142         {
143             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
144             uint32_t              : 1;
145             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
146             uint32_t              : 1;
147             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
148             uint32_t              : 1;
149             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
150             uint32_t              : 2;
151             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
152             uint32_t              : 1;
153             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
154             uint32_t              : 1;
155             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
156             uint32_t              : 1;
157             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
158             uint32_t              : 1;
159         } WCR2_b;
160     };
161     __IM uint32_t RESERVED1;
162 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
163 
164 /**
165  * @brief R_BUS_CSb [CSb] (CS Registers)
166  */
167 typedef struct
168 {
169     __IM uint16_t RESERVED;
170 
171     union
172     {
173         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
174 
175         struct
176         {
177             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
178             uint16_t             : 3;
179             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
180             uint16_t             : 2;
181             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
182             uint16_t             : 3;
183             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
184             uint16_t             : 3;
185         } CR_b;
186     };
187     __IM uint16_t RESERVED1[3];
188 
189     union
190     {
191         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
192 
193         struct
194         {
195             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
196             uint16_t            : 4;
197             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
198             uint16_t            : 4;
199         } REC_b;
200     };
201     __IM uint16_t RESERVED2[2];
202 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
203 
204 /**
205  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
206  */
207 typedef struct
208 {
209     union
210     {
211         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
212 
213         struct
214         {
215             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
216             uint8_t             : 3;
217             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
218             uint8_t             : 2;
219         } SDCCR_b;
220     };
221 
222     union
223     {
224         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
225 
226         struct
227         {
228             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
229             uint8_t             : 7;
230         } SDCMOD_b;
231     };
232 
233     union
234     {
235         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
236 
237         struct
238         {
239             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
240             uint8_t          : 7;
241         } SDAMOD_b;
242     };
243     __IM uint8_t  RESERVED;
244     __IM uint32_t RESERVED1[3];
245 
246     union
247     {
248         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
249 
250         struct
251         {
252             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
253             uint8_t            : 7;
254         } SDSELF_b;
255     };
256     __IM uint8_t  RESERVED2;
257     __IM uint16_t RESERVED3;
258 
259     union
260     {
261         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
262 
263         struct
264         {
265             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
266             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
267                                         *   Setting. ( REFW+1 Cycles )                                                */
268         } SDRFCR_b;
269     };
270 
271     union
272     {
273         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
274 
275         struct
276         {
277             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
278             uint8_t            : 7;
279         } SDRFEN_b;
280     };
281     __IM uint8_t  RESERVED4;
282     __IM uint32_t RESERVED5[2];
283 
284     union
285     {
286         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
287 
288         struct
289         {
290             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
291             uint8_t             : 7;
292         } SDICR_b;
293     };
294     __IM uint8_t  RESERVED6;
295     __IM uint16_t RESERVED7;
296 
297     union
298     {
299         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
300 
301         struct
302         {
303             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
304             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
305             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
306                                         *   )                                                                         */
307             uint16_t : 5;
308         } SDIR_b;
309     };
310     __IM uint16_t RESERVED8;
311     __IM uint32_t RESERVED9[6];
312 
313     union
314     {
315         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
316 
317         struct
318         {
319             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
320             uint8_t           : 6;
321         } SDADR_b;
322     };
323     __IM uint8_t  RESERVED10;
324     __IM uint16_t RESERVED11;
325 
326     union
327     {
328         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
329 
330         struct
331         {
332             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
333             uint32_t           : 5;
334             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
335             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
336             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
337             uint32_t           : 2;
338             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
339             uint32_t           : 13;
340         } SDTR_b;
341     };
342 
343     union
344     {
345         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
346 
347         struct
348         {
349             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
350             uint16_t          : 1;
351         } SDMOD_b;
352     };
353     __IM uint16_t RESERVED12;
354     __IM uint32_t RESERVED13;
355 
356     union
357     {
358         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
359 
360         struct
361         {
362             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
363             uint8_t            : 2;
364             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
365             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
366             uint8_t            : 3;
367         } SDSR_b;
368     };
369     __IM uint8_t  RESERVED14;
370     __IM uint16_t RESERVED15;
371 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
372 
373 /**
374  * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
375  */
376 typedef struct
377 {
378     union
379     {
380         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
381 
382         struct
383         {
384             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
385         } ADD_b;
386     };
387 
388     union
389     {
390         union
391         {
392             __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */
393 
394             struct
395             {
396                 __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
397                 uint8_t              : 6;
398                 __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
399             } STAT_b;
400         };
401 
402         union
403         {
404             __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */
405 
406             struct
407             {
408                 __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
409                 uint8_t             : 7;
410             } RW_b;
411         };
412     };
413     __IM uint8_t  RESERVED;
414     __IM uint16_t RESERVED1;
415     __IM uint32_t RESERVED2[2];
416 } R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */
417 
418 /**
419  * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
420  */
421 typedef struct
422 {
423     union
424     {
425         __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */
426 
427         struct
428         {
429             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
430         } ADD_b;
431     };
432 
433     union
434     {
435         __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */
436 
437         struct
438         {
439             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
440             uint8_t              : 7;
441         } RW_b;
442     };
443     __IM uint8_t  RESERVED;
444     __IM uint16_t RESERVED1;
445     __IM uint32_t RESERVED2[2];
446 } R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */
447 
448 /**
449  * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
450  */
451 typedef struct
452 {
453     union
454     {
455         __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */
456 
457         struct
458         {
459             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
460             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
461             uint8_t                : 1;
462             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
463             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
464             __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
465             uint8_t                : 2;
466         } STAT_b;
467     };
468     __IM uint8_t RESERVED[7];
469 
470     union
471     {
472         __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */
473 
474         struct
475         {
476             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
477             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
478             uint8_t                : 1;
479             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
480             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
481             __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
482             uint8_t                : 2;
483         } CLR_b;
484     };
485     __IM uint8_t RESERVED1[7];
486 } R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */
487 
488 /**
489  * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
490  */
491 typedef struct
492 {
493     __IM uint8_t RESERVED[36];
494 
495     union
496     {
497         __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */
498 
499         struct
500         {
501             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
502             uint8_t                : 7;
503         } STAT_b;
504     };
505     __IM uint8_t RESERVED1[7];
506 
507     union
508     {
509         __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */
510 
511         struct
512         {
513             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
514             uint8_t                : 7;
515         } CLR_b;
516     };
517 } R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */
518 
519 /**
520  * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
521  */
522 typedef struct
523 {
524     __IM uint32_t RESERVED[2];
525 
526     union
527     {
528         __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */
529 
530         struct
531         {
532             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
533             uint32_t            : 31;
534         } MRE0BI_b;
535     };
536     __IM uint32_t RESERVED1;
537 
538     union
539     {
540         __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */
541 
542         struct
543         {
544             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
545             uint32_t            : 31;
546         } FLBI_b;
547     };
548     __IM uint32_t RESERVED2[3];
549 
550     union
551     {
552         __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
553 
554         struct
555         {
556             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
557             uint32_t            : 31;
558         } S0BI_b;
559     };
560     __IM uint32_t RESERVED3;
561 
562     union
563     {
564         __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */
565 
566         struct
567         {
568             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
569             uint32_t            : 31;
570         } S1BI_b;
571     };
572     __IM uint32_t RESERVED4;
573 
574     union
575     {
576         __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */
577 
578         struct
579         {
580             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
581             uint32_t            : 31;
582         } S2BI_b;
583     };
584     __IM uint32_t RESERVED5;
585 
586     union
587     {
588         __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */
589 
590         struct
591         {
592             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
593             uint32_t            : 31;
594         } S3BI_b;
595     };
596     __IM uint32_t RESERVED6[3];
597 
598     union
599     {
600         __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */
601 
602         struct
603         {
604             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
605             uint32_t            : 31;
606         } STBYSBI_b;
607     };
608     __IM uint32_t RESERVED7;
609 
610     union
611     {
612         union
613         {
614             __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
615 
616             struct
617             {
618                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
619                 uint32_t            : 31;
620             } ECBI_b;
621         };
622 
623         union
624         {
625             __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
626 
627             struct
628             {
629                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
630                 uint32_t            : 31;
631             } SPI0BI_b;
632         };
633     };
634     __IM uint32_t RESERVED8;
635 
636     union
637     {
638         union
639         {
640             __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
641 
642             struct
643             {
644                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
645                 uint32_t            : 31;
646             } EOBI_b;
647         };
648 
649         union
650         {
651             __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
652 
653             struct
654             {
655                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
656                 uint32_t            : 31;
657             } SPI1BI_b;
658         };
659     };
660     __IM uint32_t RESERVED9;
661 
662     union
663     {
664         __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */
665 
666         struct
667         {
668             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
669             uint32_t            : 31;
670         } PBBI_b;
671     };
672     __IM uint32_t RESERVED10;
673 
674     union
675     {
676         union
677         {
678             __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
679 
680             struct
681             {
682                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
683                 uint32_t            : 31;
684             } PABI_b;
685         };
686 
687         union
688         {
689             __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
690 
691             struct
692             {
693                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
694                 uint32_t            : 31;
695             } CPU0SAHBI_b;
696         };
697     };
698     __IM uint32_t RESERVED11;
699 
700     union
701     {
702         union
703         {
704             __IOM uint32_t PIBI;         /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
705 
706             struct
707             {
708                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
709                 uint32_t            : 31;
710             } PIBI_b;
711         };
712 
713         union
714         {
715             __IOM uint32_t CPU1TCMBI;    /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
716 
717             struct
718             {
719                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
720                 uint32_t            : 31;
721             } CPU1TCMBI_b;
722         };
723     };
724     __IM uint32_t RESERVED12;
725 
726     union
727     {
728         __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */
729 
730         struct
731         {
732             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
733             uint32_t            : 31;
734         } PSBI_b;
735     };
736 } R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */
737 
738 /**
739  * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
740  */
741 typedef struct
742 {
743     union
744     {
745         union
746         {
747             __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
748 
749             struct
750             {
751                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
752                 uint32_t            : 30;
753             } FHBI_b;
754         };
755 
756         union
757         {
758             __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
759 
760             struct
761             {
762                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
763                 uint32_t            : 30;
764             } MRC0BI_b;
765         };
766     };
767     __IM uint32_t RESERVED[5];
768 
769     union
770     {
771         __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */
772 
773         struct
774         {
775             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
776             uint32_t            : 30;
777         } S0BI_b;
778     };
779     __IM uint32_t RESERVED1;
780 
781     union
782     {
783         __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
784 
785         struct
786         {
787             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
788             uint32_t            : 30;
789         } S1BI_b;
790     };
791 } R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */
792 
793 /**
794  * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
795  */
796 typedef struct
797 {
798     union
799     {
800         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */
801 
802         struct
803         {
804             __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
805         } ADD_b;
806     };
807 
808     union
809     {
810         __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
811                                          *                  Write.                                                     */
812 
813         struct
814         {
815             __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
816                                          *   Status.                                                                   */
817             uint8_t : 7;
818         } RW_b;
819     };
820     __IM uint8_t  RESERVED;
821     __IM uint16_t RESERVED1;
822     __IM uint32_t RESERVED2[2];
823 } R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */
824 
825 /**
826  * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
827  */
828 typedef struct
829 {
830     union
831     {
832         __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */
833 
834         struct
835         {
836             __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
837             __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
838             __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
839             uint16_t                : 13;
840         } BUSOAD_b;
841     };
842     __IM uint16_t RESERVED;
843 
844     union
845     {
846         __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */
847 
848         struct
849         {
850             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
851             uint16_t               : 7;
852             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
853         } BUSOADPT_b;
854     };
855     __IM uint16_t RESERVED1[5];
856 
857     union
858     {
859         __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
860                                         *                  Register.                                                  */
861 
862         struct
863         {
864             __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
865             uint16_t           : 7;
866             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
867         } MSAOAD_b;
868     };
869     __IM uint16_t RESERVED2;
870 
871     union
872     {
873         __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */
874 
875         struct
876         {
877             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
878             uint16_t               : 7;
879             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
880         } MSAPT_b;
881     };
882 } R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */
883 
884 /**
885  * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
886  */
887 typedef struct
888 {
889     union
890     {
891         __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */
892 
893         struct
894         {
895             __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
896             __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
897             __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
898             __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
899             __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
900             __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
901             __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
902             __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
903             __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
904             __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
905             __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
906             __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
907             __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
908             __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
909             __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
910             __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
911             __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
912             __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
913             __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
914             __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
915             __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
916             __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
917             __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
918             __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
919             __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
920             __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
921             __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
922             __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
923             __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
924             __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
925             __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
926             __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
927         } STAT_b;
928     };
929     __IM uint32_t RESERVED;
930 
931     union
932     {
933         __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */
934 
935         struct
936         {
937             __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
938             __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
939             __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
940             __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
941             __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
942             __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
943             __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
944             __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
945             __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
946             __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
947             __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
948             __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
949             __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
950             __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
951             __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
952             __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
953             __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
954             __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
955             __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
956             __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
957             __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
958             __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
959             __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
960             __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
961             __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
962             __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
963             __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
964             __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
965             __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
966             __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
967             __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
968             __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
969         } CLR_b;
970     };
971 } R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */
972 
973 /**
974  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
975  */
976 typedef struct
977 {
978     union
979     {
980         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
981 
982         struct
983         {
984             uint16_t             : 15;
985             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
986         } CNT_b;
987     };
988     __IM uint16_t RESERVED;
989 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
990 
991 /**
992  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
993  */
994 typedef struct
995 {
996     union
997     {
998         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
999 
1000         struct
1001         {
1002             __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
1003             uint16_t              : 2;
1004             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
1005             uint16_t              : 10;
1006         } CNT_b;
1007     };
1008     __IM uint16_t RESERVED;
1009 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
1010 
1011 /**
1012  * @brief R_CAN0_MB [MB] (Mailbox)
1013  */
1014 typedef struct
1015 {
1016     union
1017     {
1018         __IOM uint32_t ID;             /*!< (@ 0x00000000) Mailbox ID Register                                        */
1019 
1020         struct
1021         {
1022             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
1023             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
1024             uint32_t           : 1;
1025             __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
1026             __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
1027         } ID_b;
1028     };
1029 
1030     union
1031     {
1032         __IOM uint16_t DL;             /*!< (@ 0x00000004) Mailbox DLC Register                                       */
1033 
1034         struct
1035         {
1036             __IOM uint16_t DLC : 4;    /*!< [3..0] Data Length Code                                                   */
1037             uint16_t           : 12;
1038         } DL_b;
1039     };
1040 
1041     union
1042     {
1043         __IOM uint8_t D[8];            /*!< (@ 0x00000006) Mailbox Data Register                                      */
1044 
1045         struct
1046         {
1047             __IOM uint8_t DATA : 8;    /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN
1048                                         *   message data. Transmission or reception starts from DATA0.
1049                                         *   The bit order on the CAN bus is MSB-first, and transmission
1050                                         *   or reception starts from bit 7                                            */
1051         } D_b[8];
1052     };
1053 
1054     union
1055     {
1056         __IOM uint16_t TS;             /*!< (@ 0x0000000E) Mailbox Timestamp Register                                 */
1057 
1058         struct
1059         {
1060             __IOM uint16_t TSL : 8;    /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter
1061                                         *   value of the time stamp when received messages are stored
1062                                         *   in the mailbox.                                                           */
1063             __IOM uint16_t TSH : 8;    /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter
1064                                         *   value of the time stamp when received messages are stored
1065                                         *   in the mailbox.                                                           */
1066         } TS_b;
1067     };
1068 } R_CAN0_MB_Type;                      /*!< Size = 16 (0x10)                                                          */
1069 
1070 /**
1071  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1072  */
1073 typedef struct
1074 {
1075     union
1076     {
1077         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1078 
1079         struct
1080         {
1081             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1082             uint8_t          : 5;
1083             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1084             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1085         } BY_b;
1086     };
1087     __IM uint8_t RESERVED;
1088 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1089 
1090 /**
1091  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
1092  */
1093 typedef struct
1094 {
1095     union
1096     {
1097         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1098 
1099         struct
1100         {
1101             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1102             uint16_t           : 7;
1103         } HA_b;
1104     };
1105     __IM uint16_t RESERVED;
1106 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1107 
1108 /**
1109  * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers)
1110  */
1111 typedef struct
1112 {
1113     union
1114     {
1115         __IOM uint32_t STTRU;            /*!< (@ 0x00000000) Timer Start Time Setting Register                          */
1116 
1117         struct
1118         {
1119             __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
1120                                           *   bits of the start time of the pulse output timer in nanoseconds.          */
1121         } STTRU_b;
1122     };
1123 
1124     union
1125     {
1126         __IOM uint32_t STTRL;            /*!< (@ 0x00000004) Timer Start Time Setting Register                          */
1127 
1128         struct
1129         {
1130             __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
1131                                           *   of the start time of the pulse output timer in nanoseconds.               */
1132         } STTRL_b;
1133     };
1134 
1135     union
1136     {
1137         __IOM uint32_t CYCR;            /*!< (@ 0x00000008) Timer Cycle Setting Registers                              */
1138 
1139         struct
1140         {
1141             __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in
1142                                          *   nanoseconds. Set a value that is equivalent to at least
1143                                          *   four cycles of the STCA clock.                                            */
1144             uint32_t : 2;
1145         } CYCR_b;
1146     };
1147 
1148     union
1149     {
1150         __IOM uint32_t PLSR;            /*!< (@ 0x0000000C) Timer Pulse Width Setting Register                         */
1151 
1152         struct
1153         {
1154             __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse
1155                                          *   signal from the timer in nanoseconds. Set a value that
1156                                          *   is equivalent to at least two cycles of the STCA clock.                   */
1157             uint32_t : 3;
1158         } PLSR_b;
1159     };
1160 } R_ETHERC_EPTPC_COMMON_TM_Type;        /*!< Size = 16 (0x10)                                                          */
1161 
1162 /**
1163  * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers)
1164  */
1165 typedef struct
1166 {
1167     union
1168     {
1169         __IOM uint32_t MACRU;            /*!< (@ 0x00000000) Channel Local MAC Address Register                         */
1170 
1171         struct
1172         {
1173             __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
1174                                           *   bits of the local MAC address for Ethernet port 0.                        */
1175             uint32_t : 8;
1176         } MACRU_b;
1177     };
1178 
1179     union
1180     {
1181         __IOM uint32_t MACRL;            /*!< (@ 0x00000004) Channel Local MAC Address Register                         */
1182 
1183         struct
1184         {
1185             __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
1186                                           *   bits of the local MAC address for Ethernet port 0.                        */
1187             uint32_t : 8;
1188         } MACRL_b;
1189     };
1190 } R_ETHERC_EPTPC_COMMON_PR_Type;         /*!< Size = 8 (0x8)                                                            */
1191 
1192 /**
1193  * @brief R_GLCDC_BG [BG] (Background Registers)
1194  */
1195 typedef struct
1196 {
1197     union
1198     {
1199         __IOM uint32_t EN;             /*!< (@ 0x00000000) Background Plane Setting Operation Control Register        */
1200 
1201         struct
1202         {
1203             __IOM uint32_t EN  : 1;    /*!< [0..0] Background plane generation module operation enable                */
1204             uint32_t           : 7;
1205             __IOM uint32_t VEN : 1;    /*!< [8..8] Control of LCDC internal register value reflection to
1206                                         *   internal operations                                                       */
1207             uint32_t             : 7;
1208             __IOM uint32_t SWRST : 1;  /*!< [16..16] Entire module SW reset control                                   */
1209             uint32_t             : 15;
1210         } EN_b;
1211     };
1212 
1213     union
1214     {
1215         __IOM uint32_t PERI;           /*!< (@ 0x00000004) Background Plane Setting Free-Running Period
1216                                         *                  Register                                                   */
1217 
1218         struct
1219         {
1220             __IOM uint32_t FH : 11;    /*!< [10..0] Background plane horizontal synchronization signal period
1221                                         *   on the basis of pixel clock (PXCLK).                                      */
1222             uint32_t          : 5;
1223             __IOM uint32_t FV : 11;    /*!< [26..16] Background plane vertical synchronization signal period
1224                                         *   on the basis of line.                                                     */
1225             uint32_t : 5;
1226         } PERI_b;
1227     };
1228 
1229     union
1230     {
1231         __IOM uint32_t SYNC;           /*!< (@ 0x00000008) Background Plane Setting Synchronization Position
1232                                         *                  Register                                                   */
1233 
1234         struct
1235         {
1236             __IOM uint32_t HP : 4;     /*!< [3..0] Background plane horizontal synchronization signal assertion
1237                                         *   position on the basis of pixel clock (PXCLK).                             */
1238             uint32_t          : 12;
1239             __IOM uint32_t VP : 4;     /*!< [19..16] Background plane vertical synchronization signal assertion
1240                                         *   position on the basis of line.                                            */
1241             uint32_t : 12;
1242         } SYNC_b;
1243     };
1244 
1245     union
1246     {
1247         __IOM uint32_t VSIZE;          /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical
1248                                         *                  Size Register                                              */
1249 
1250         struct
1251         {
1252             __IOM uint32_t VW : 11;    /*!< [10..0] Background plane vertical valid pixel width on the basis
1253                                         *   of line                                                                   */
1254             uint32_t          : 5;
1255             __IOM uint32_t VP : 11;    /*!< [26..16] Background plane vertical valid pixel start position
1256                                         *   on the basis of line                                                      */
1257             uint32_t : 5;
1258         } VSIZE_b;
1259     };
1260 
1261     union
1262     {
1263         __IOM uint32_t HSIZE;          /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal
1264                                         *                  Size Register                                              */
1265 
1266         struct
1267         {
1268             __IOM uint32_t HW : 11;    /*!< [10..0] Background plane horizontall valid pixel width on the
1269                                         *   basis of pixel clock (PXCLK) Note: When serial RGB is selected
1270                                         *   as the output format for the output control block, add
1271                                         *   two to the horizontal enable signal width and set the resulting
1272                                         *   value to this field.                                                      */
1273             uint32_t          : 5;
1274             __IOM uint32_t HP : 11;    /*!< [26..16] Background plane horizontal valid pixel start position
1275                                         *   on the basis of pixel clock (PXCLK).                                      */
1276             uint32_t : 5;
1277         } HSIZE_b;
1278     };
1279 
1280     union
1281     {
1282         __IOM uint32_t BGC;            /*!< (@ 0x00000014) Background Plane Setting Background Color Register         */
1283 
1284         struct
1285         {
1286             __IOM uint32_t B : 8;      /*!< [7..0] B value for background plane valid pixel area Unsigned;
1287                                         *   8-bit integer                                                             */
1288             __IOM uint32_t G : 8;      /*!< [15..8] G value for background plane valid pixel area Unsigned;
1289                                         *   8-bit integer                                                             */
1290             __IOM uint32_t R : 8;      /*!< [23..16] R value for background plane valid pixel area. Unsigned;
1291                                         *   8-bit integer.                                                            */
1292             uint32_t : 8;
1293         } BGC_b;
1294     };
1295 
1296     union
1297     {
1298         __IM uint32_t MON;             /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register           */
1299 
1300         struct
1301         {
1302             __IM uint32_t EN  : 1;     /*!< [0..0] Background plane generation module operation state monitor.        */
1303             uint32_t          : 7;
1304             __IM uint32_t VEN : 1;     /*!< [8..8] Entire module internal operation reflection control signal
1305                                         *   monitor. The signal state for controlling reflection of
1306                                         *   the register values to the internal operations upon assertion
1307                                         *   of the vertical synchronization signal.                                   */
1308             uint32_t            : 7;
1309             __IM uint32_t SWRST : 1;   /*!< [16..16] Entire module SW reset state monitor.                            */
1310             uint32_t            : 15;
1311         } MON_b;
1312     };
1313 } R_GLCDC_BG_Type;                     /*!< Size = 28 (0x1c)                                                          */
1314 
1315 /**
1316  * @brief R_GLCDC_GR [GR] (Layer Registers)
1317  */
1318 typedef struct
1319 {
1320     union
1321     {
1322         __IOM uint32_t VEN;            /*!< (@ 0x00000000) Graphics Register Update Control Register                  */
1323 
1324         struct
1325         {
1326             __IOM uint32_t PVEN : 1;   /*!< [0..0] Control of graphics n module register value reflection
1327                                         *   to internal operations. Reflection of the register values
1328                                         *   to the internal operation at the assertion of the vertical
1329                                         *   synchronization signal (VS).                                              */
1330             uint32_t : 31;
1331         } VEN_b;
1332     };
1333 
1334     union
1335     {
1336         __IOM uint32_t FLMRD;          /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register                */
1337 
1338         struct
1339         {
1340             __IOM uint32_t RENB : 1;   /*!< [0..0] Graphics data (frame buffer data) read enable.                     */
1341             uint32_t            : 31;
1342         } FLMRD_b;
1343     };
1344 
1345     union
1346     {
1347         __IM uint32_t FLM1;            /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1                   */
1348 
1349         struct
1350         {
1351             __IM uint32_t BSTMD : 2;   /*!< [1..0] Burst transfer control for graphics data (frame buffer
1352                                         *   data) access                                                              */
1353             uint32_t : 30;
1354         } FLM1_b;
1355     };
1356 
1357     union
1358     {
1359         __IOM uint32_t FLM2;           /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2                   */
1360 
1361         struct
1362         {
1363             __IOM uint32_t BASE : 32;  /*!< [31..0] Base address for accessing graphics data (frame buffer
1364                                         *   data) Set the head address in the frame buffer where graphics
1365                                         *   data is to be stored. GRn_FLM2.BASE[5:0] should be fixed
1366                                         *   to 0 during 64-byte burst transfer.                                       */
1367         } FLM2_b;
1368     };
1369 
1370     union
1371     {
1372         __IOM uint32_t FLM3;           /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3                   */
1373 
1374         struct
1375         {
1376             uint32_t             : 16;
1377             __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data
1378                                         *   (frame buffer data) Signed; 16-bit integer                                */
1379         } FLM3_b;
1380     };
1381     __IM uint32_t RESERVED;
1382 
1383     union
1384     {
1385         __IOM uint32_t FLM5;             /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5                   */
1386 
1387         struct
1388         {
1389             __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing
1390                                           *   graphics data (frame buffer data), where one transfer is
1391                                           *   defined as 16-beat burst access (64-byte boundary)                        */
1392             __IOM uint32_t LNNUM : 11;   /*!< [26..16] Number of lines per frame for accessing graphics data
1393                                           *   (frame buffer data).                                                      */
1394             uint32_t : 5;
1395         } FLM5_b;
1396     };
1397 
1398     union
1399     {
1400         __IOM uint32_t FLM6;           /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6                   */
1401 
1402         struct
1403         {
1404             uint32_t              : 28;
1405             __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer
1406                                         *   data).                                                                    */
1407             uint32_t : 1;
1408         } FLM6_b;
1409     };
1410 
1411     union
1412     {
1413         __IOM uint32_t AB1;               /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1                 */
1414 
1415         struct
1416         {
1417             __IOM uint32_t DISPSEL   : 2; /*!< [1..0] Graphics display plane control.                                    */
1418             uint32_t                 : 2;
1419             __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control.                        */
1420             uint32_t                 : 3;
1421             __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area
1422                                            *   alpha blending.                                                           */
1423             uint32_t             : 3;
1424             __IOM uint32_t ARCON : 1;     /*!< [12..12] Rectangular area alpha blending control.                         */
1425             uint32_t             : 19;
1426         } AB1_b;
1427     };
1428 
1429     union
1430     {
1431         __IOM uint32_t AB2;            /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2                 */
1432 
1433         struct
1434         {
1435             __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area.                            */
1436             uint32_t             : 5;
1437             __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area.                  */
1438             uint32_t             : 5;
1439         } AB2_b;
1440     };
1441 
1442     union
1443     {
1444         __IOM uint32_t AB3;            /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3                 */
1445 
1446         struct
1447         {
1448             __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area.                          */
1449             uint32_t             : 5;
1450             __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area.                */
1451             uint32_t             : 5;
1452         } AB3_b;
1453     };
1454 
1455     union
1456     {
1457         __IOM uint32_t AB4;            /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4                 */
1458 
1459         struct
1460         {
1461             __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image
1462                                         *   area.                                                                     */
1463             uint32_t             : 5;
1464             __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending
1465                                         *   image area                                                                */
1466             uint32_t : 5;
1467         } AB4_b;
1468     };
1469 
1470     union
1471     {
1472         __IOM uint32_t AB5;            /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5                 */
1473 
1474         struct
1475         {
1476             __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending
1477                                         *   image area.                                                               */
1478             uint32_t             : 5;
1479             __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha
1480                                         *   blending image area.                                                      */
1481             uint32_t : 5;
1482         } AB5_b;
1483     };
1484 
1485     union
1486     {
1487         __IOM uint32_t AB6;             /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6                 */
1488 
1489         struct
1490         {
1491             __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area.                 */
1492             uint32_t               : 8;
1493             __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular
1494                                          *   area (-255 to 255). [8]: Sign (0: addition, 1: subtraction)
1495                                          *   [7:0]: Variation (absolute value)                                         */
1496             uint32_t : 7;
1497         } AB6_b;
1498     };
1499 
1500     union
1501     {
1502         __IOM uint32_t AB7;            /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7                 */
1503 
1504         struct
1505         {
1506             __IOM uint32_t CKON   : 1; /*!< [0..0] RGB-index chroma-key processing control.                           */
1507             uint32_t              : 15;
1508             __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular
1509                                         *   area.                                                                     */
1510             uint32_t : 8;
1511         } AB7_b;
1512     };
1513 
1514     union
1515     {
1516         __IOM uint32_t AB8;            /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8                 */
1517 
1518         struct
1519         {
1520             __IOM uint32_t CKKR : 8;   /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned;
1521                                         *   8 bits.                                                                   */
1522             __IOM uint32_t CKKB : 8;   /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned;
1523                                         *   8 bits.                                                                   */
1524             __IOM uint32_t CKKG : 8;   /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned;
1525                                         *   8 bits.                                                                   */
1526             uint32_t : 8;
1527         } AB8_b;
1528     };
1529 
1530     union
1531     {
1532         __IOM uint32_t AB9;            /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9                 */
1533 
1534         struct
1535         {
1536             __IOM uint32_t CKR : 8;    /*!< [7..0] R value after RGB-index chroma-key processing replacement
1537                                         *   Unsigned; 8 bits.                                                         */
1538             __IOM uint32_t CKB : 8;    /*!< [15..8] B value after RGB-index chroma-key processing replacement
1539                                         *   Unsigned; 8 bits.                                                         */
1540             __IOM uint32_t CKG : 8;    /*!< [23..16] G value after RGB-index chroma-key processing replacement
1541                                         *   Unsigned; 8 bits.                                                         */
1542             __IOM uint32_t CKA : 8;    /*!< [31..24] A value after RGB-index chroma-key processing replacement.       */
1543         } AB9_b;
1544     };
1545     __IM uint32_t RESERVED1[2];
1546 
1547     union
1548     {
1549         __IOM uint32_t BASE;           /*!< (@ 0x0000004C) Graphics Background Color Control Register                 */
1550 
1551         struct
1552         {
1553             __IOM uint32_t R : 8;      /*!< [7..0] Background color R value Unsigned; 8 bits                          */
1554             __IOM uint32_t B : 8;      /*!< [15..8] Background color B value Unsigned; 8 bits                         */
1555             __IOM uint32_t G : 8;      /*!< [23..16] Background color G value Unsigned; 8 bits                        */
1556             uint32_t         : 8;
1557         } BASE_b;
1558     };
1559 
1560     union
1561     {
1562         __IOM uint32_t CLUTINT;        /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register             */
1563 
1564         struct
1565         {
1566             __IOM uint32_t LINE : 11;  /*!< [10..0] Number of detection lines                                         */
1567             uint32_t            : 5;
1568             __IOM uint32_t SEL  : 1;   /*!< [16..16] CLUT table control                                               */
1569             uint32_t            : 15;
1570         } CLUTINT_b;
1571     };
1572 
1573     union
1574     {
1575         __IM uint32_t MON;             /*!< (@ 0x00000054) Graphics Status Monitor Register                           */
1576 
1577         struct
1578         {
1579             __IM uint32_t ARCST   : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area              */
1580             uint32_t              : 15;
1581             __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow                                     */
1582             uint32_t              : 15;
1583         } MON_b;
1584     };
1585     __IM uint32_t RESERVED2[42];
1586 } R_GLCDC_GR_Type;                     /*!< Size = 256 (0x100)                                                        */
1587 
1588 /**
1589  * @brief R_GLCDC_GAM [GAM] (Gamma Settings)
1590  */
1591 typedef struct
1592 {
1593     union
1594     {
1595         __IOM uint32_t LATCH;          /*!< (@ 0x00000000) Gamma Register Update Control Register                     */
1596 
1597         struct
1598         {
1599             __IOM uint32_t VEN : 1;    /*!< [0..0] Control of gamma correction x module register value reflection
1600                                         *   to internal operations. The register values to be reflected
1601                                         *   to the internal operations at the assertion of the vertical
1602                                         *   synchronization signal (VS).                                              */
1603             uint32_t : 31;
1604         } LATCH_b;
1605     };
1606 
1607     union
1608     {
1609         __IOM uint32_t GAM_SW;         /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register            */
1610 
1611         struct
1612         {
1613             __IOM uint32_t GAMON : 1;  /*!< [0..0] Gamma correction on/off control                                    */
1614             uint32_t             : 31;
1615         } GAM_SW_b;
1616     };
1617 
1618     union
1619     {
1620         __IOM uint32_t LUT[8];         /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register              */
1621 
1622         struct
1623         {
1624             __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point.                */
1625             uint32_t             : 5;
1626             __IOM uint32_t _LOW  : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point.               */
1627             uint32_t             : 5;
1628         } LUT_b[8];
1629     };
1630 
1631     union
1632     {
1633         __IOM uint32_t AREA[5];        /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register               */
1634 
1635         struct
1636         {
1637             __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer                  */
1638             __IOM uint32_t _MID  : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer                */
1639             __IOM uint32_t _LOW  : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer                */
1640             uint32_t             : 2;
1641         } AREA_b[5];
1642     };
1643     __IM uint32_t RESERVED;
1644 } R_GLCDC_GAM_Type;                    /*!< Size = 64 (0x40)                                                          */
1645 
1646 /**
1647  * @brief R_GLCDC_OUT [OUT] (Output Control Registers)
1648  */
1649 typedef struct
1650 {
1651     union
1652     {
1653         __IOM uint32_t VLATCH;         /*!< (@ 0x00000000) Output Control Block Register Update Control
1654                                         *                  Register                                                   */
1655 
1656         struct
1657         {
1658             __IOM uint32_t VEN : 1;    /*!< [0..0] Control of output control module register value reflection
1659                                         *   to internal operations. The register values to be reflected
1660                                         *   to the internal operations at the assertion of the vertical
1661                                         *   synchronization signal (VS).                                              */
1662             uint32_t : 31;
1663         } VLATCH_b;
1664     };
1665 
1666     union
1667     {
1668         __IOM uint32_t SET;              /*!< (@ 0x00000004) Output Control Block Output Interface Register             */
1669 
1670         struct
1671         {
1672             __IOM uint32_t PHASE    : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK)                  */
1673             uint32_t                : 2;
1674             __IOM uint32_t DIRSEL   : 1; /*!< [4..4] Invalid data position control in serial RGB format                 */
1675             uint32_t                : 3;
1676             __IOM uint32_t FRQSEL   : 2; /*!< [9..8] Clock frequency division control                                   */
1677             uint32_t                : 2;
1678             __IOM uint32_t FORMAT   : 2; /*!< [13..12] Output format select                                             */
1679             uint32_t                : 10;
1680             __IOM uint32_t SWAPON   : 1; /*!< [24..24] Pixel order control                                              */
1681             uint32_t                : 3;
1682             __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control                                        */
1683             uint32_t                : 3;
1684         } SET_b;
1685     };
1686 
1687     union
1688     {
1689         __IOM uint32_t BRIGHT1;        /*!< (@ 0x00000008) Output Control Block Brightness Correction Register
1690                                         *                  1                                                          */
1691 
1692         struct
1693         {
1694             __IOM uint32_t BRTG : 10;  /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits;
1695                                         +512 with offset; integer                                                 */
1696             uint32_t : 22;
1697         } BRIGHT1_b;
1698     };
1699 
1700     union
1701     {
1702         __IOM uint32_t BRIGHT2;        /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register
1703                                         *                  2                                                          */
1704 
1705         struct
1706         {
1707             __IOM uint32_t BRTR : 10;  /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits;
1708                                         +512 with offset; integer                                                 */
1709             uint32_t            : 6;
1710             __IOM uint32_t BRTB : 10;  /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10
1711                                         *   bits; +512 with offset; integer                                           */
1712             uint32_t : 6;
1713         } BRIGHT2_b;
1714     };
1715 
1716     union
1717     {
1718         __IOM uint32_t CONTRAST;       /*!< (@ 0x00000010) Output Control Block Contrast Correction Register          */
1719 
1720         struct
1721         {
1722             __IOM uint32_t CONTR : 8;  /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits
1723                                         *   fixed point                                                               */
1724             __IOM uint32_t CONTB : 8;  /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits
1725                                         *   fixed point                                                               */
1726             __IOM uint32_t CONTG : 8;  /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8
1727                                         *   bits fixed point.                                                         */
1728             uint32_t : 8;
1729         } CONTRAST_b;
1730     };
1731 
1732     union
1733     {
1734         __IOM uint32_t PDTHA;          /*!< (@ 0x00000014) Output Control Block Panel Dither Correction
1735                                         *                  Register                                                   */
1736 
1737         struct
1738         {
1739             __IOM uint32_t PD : 2;     /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit
1740                                         *   integer                                                                   */
1741             uint32_t          : 2;
1742             __IOM uint32_t PC : 2;     /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit
1743                                         *   integer                                                                   */
1744             uint32_t          : 2;
1745             __IOM uint32_t PB : 2;     /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit
1746                                         *   integer                                                                   */
1747             uint32_t          : 2;
1748             __IOM uint32_t PA : 2;     /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned
1749                                         *   2-bit integer                                                             */
1750             uint32_t            : 2;
1751             __IOM uint32_t FORM : 2;   /*!< [17..16] Output format select                                             */
1752             uint32_t            : 2;
1753             __IOM uint32_t SEL  : 2;   /*!< [21..20] Operation mode                                                   */
1754             uint32_t            : 10;
1755         } PDTHA_b;
1756     };
1757     __IM uint32_t RESERVED[3];
1758 
1759     union
1760     {
1761         __IOM uint32_t CLKPHASE;       /*!< (@ 0x00000024) Output Control Block Output Phase Control Register         */
1762 
1763         struct
1764         {
1765             uint32_t                 : 3;
1766             __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control                                     */
1767             __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control                                     */
1768             __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control                                     */
1769             __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control                                     */
1770             uint32_t                 : 1;
1771             __IOM uint32_t LCDEDGE   : 1; /*!< [8..8] LCD_DATA Output Phase Control                                      */
1772             uint32_t                 : 3;
1773             __IOM uint32_t FRONTGAM  : 1; /*!< [12..12] Correction control                                               */
1774             uint32_t                 : 19;
1775         } CLKPHASE_b;
1776     };
1777 } R_GLCDC_OUT_Type;                       /*!< Size = 40 (0x28)                                                          */
1778 
1779 /**
1780  * @brief R_GLCDC_TCON [TCON] (Timing Control Registers)
1781  */
1782 typedef struct
1783 {
1784     __IM uint32_t RESERVED;
1785 
1786     union
1787     {
1788         __IOM uint32_t TIM;             /*!< (@ 0x00000004) TCON Reference Timing Setting Register                     */
1789 
1790         struct
1791         {
1792             __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference
1793                                          *   timing Sets the offset from the assertion of the internal
1794                                          *   horizontal synchronization signal in terms of pixels.                     */
1795             uint32_t            : 5;
1796             __IOM uint32_t HALF : 11;   /*!< [26..16] Vertical synchronization signal generation change timing
1797                                          *   Sets the delay from the assertion of the internal horizontal
1798                                          *   synchronization signal in terms of pixels.                                */
1799             uint32_t : 5;
1800         } TIM_b;
1801     };
1802 
1803     union
1804     {
1805         __IOM uint32_t STVA1;          /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1                   */
1806 
1807         struct
1808         {
1809             __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
1810                                         *   width.                                                                    */
1811             uint32_t          : 5;
1812             __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
1813             uint32_t          : 5;
1814         } STVA1_b;
1815     };
1816 
1817     union
1818     {
1819         __IOM uint32_t STVA2;          /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2                   */
1820 
1821         struct
1822         {
1823             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
1824                                         *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
1825                                         *   register) pin                                                             */
1826             uint32_t           : 1;
1827             __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
1828             uint32_t           : 27;
1829         } STVA2_b;
1830     };
1831 
1832     union
1833     {
1834         __IOM uint32_t STVB1;          /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1                   */
1835 
1836         struct
1837         {
1838             __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
1839                                         *   width.                                                                    */
1840             uint32_t          : 5;
1841             __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
1842             uint32_t          : 5;
1843         } STVB1_b;
1844     };
1845 
1846     union
1847     {
1848         __IOM uint32_t STVB2;          /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2                   */
1849 
1850         struct
1851         {
1852             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
1853                                         *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
1854                                         *   register) pin                                                             */
1855             uint32_t           : 1;
1856             __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
1857             uint32_t           : 27;
1858         } STVB2_b;
1859     };
1860 
1861     union
1862     {
1863         __IOM uint32_t STHA1;          /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1              */
1864 
1865         struct
1866         {
1867             __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
1868                                         *   width.                                                                    */
1869             uint32_t          : 5;
1870             __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
1871             uint32_t          : 5;
1872         } STHA1_b;
1873     };
1874 
1875     union
1876     {
1877         __IOM uint32_t STHA2;          /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2              */
1878 
1879         struct
1880         {
1881             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
1882                                         *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
1883                                         *   register) pin.                                                            */
1884             uint32_t             : 1;
1885             __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
1886             uint32_t             : 3;
1887             __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
1888             uint32_t             : 23;
1889         } STHA2_b;
1890     };
1891 
1892     union
1893     {
1894         __IOM uint32_t STHB1;          /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1              */
1895 
1896         struct
1897         {
1898             __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
1899                                         *   width.                                                                    */
1900             uint32_t          : 5;
1901             __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
1902             uint32_t          : 5;
1903         } STHB1_b;
1904     };
1905 
1906     union
1907     {
1908         __IOM uint32_t STHB2;          /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2              */
1909 
1910         struct
1911         {
1912             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
1913                                         *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
1914                                         *   register) pin.                                                            */
1915             uint32_t             : 1;
1916             __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
1917             uint32_t             : 3;
1918             __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
1919             uint32_t             : 23;
1920         } STHB2_b;
1921     };
1922 
1923     union
1924     {
1925         __IOM uint32_t DE;             /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register                 */
1926 
1927         struct
1928         {
1929             __IOM uint32_t INV : 1;    /*!< [0..0] DE signal polarity inversion control.                              */
1930             uint32_t           : 31;
1931         } DE_b;
1932     };
1933 } R_GLCDC_TCON_Type;                   /*!< Size = 44 (0x2c)                                                          */
1934 
1935 /**
1936  * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers)
1937  */
1938 typedef struct
1939 {
1940     union
1941     {
1942         __IOM uint32_t DTCTEN;            /*!< (@ 0x00000000) System control block State Detection Control
1943                                            *                  Register                                                   */
1944 
1945         struct
1946         {
1947             __IOM uint32_t VPOSDTC   : 1; /*!< [0..0] Specified line detection control                                   */
1948             __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control                             */
1949             __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control                             */
1950             uint32_t                 : 29;
1951         } DTCTEN_b;
1952     };
1953 
1954     union
1955     {
1956         __IOM uint32_t INTEN;               /*!< (@ 0x00000004) System control block Interrupt Request Enable
1957                                              *                  Control Register                                           */
1958 
1959         struct
1960         {
1961             __IOM uint32_t VPOSINTEN   : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control.                */
1962             __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control.              */
1963             __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control.              */
1964             uint32_t                   : 29;
1965         } INTEN_b;
1966     };
1967 
1968     union
1969     {
1970         __IOM uint32_t STCLR;             /*!< (@ 0x00000008) System control block Status Clear Register                 */
1971 
1972         struct
1973         {
1974             __IOM uint32_t VPOSCLR   : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field               */
1975             __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field                    */
1976             __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field                    */
1977             uint32_t                 : 29;
1978         } STCLR_b;
1979     };
1980 
1981     union
1982     {
1983         __IM uint32_t STMON;           /*!< (@ 0x0000000C) System control block Status Monitor Register               */
1984 
1985         struct
1986         {
1987             __IM uint32_t VPOS   : 1;  /*!< [0..0] Graphics 2 specified line detection flag                           */
1988             __IM uint32_t L1UNDF : 1;  /*!< [1..1] Graphics 1 underflow detection flag                                */
1989             __IM uint32_t L2UNDF : 1;  /*!< [2..2] Graphics 2 underflow detection flag                                */
1990             uint32_t             : 29;
1991         } STMON_b;
1992     };
1993 
1994     union
1995     {
1996         __IOM uint32_t PANEL_CLK;      /*!< (@ 0x00000010) System control block Version and Panel Clock
1997                                         *                  Control Register                                           */
1998 
1999         struct
2000         {
2001             __IOM uint32_t DCDR : 6;   /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1
2002                                         *   for details about setting value. Note: Settings that are
2003                                         *   not listed in table 2.7.1 are prohibited.                                 */
2004             __IOM uint32_t CLKEN : 1;  /*!< [6..6] Panel clock output enable control Note: Before changing
2005                                         *   the PIXSEL,CLKSEL or DCDR bit, this bit must be set to
2006                                         *   0.                                                                        */
2007             uint32_t              : 1;
2008             __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select                                   */
2009             uint32_t              : 3;
2010             __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same
2011                                         *   value as OUT_SET.FRQSEL[1].                                               */
2012             uint32_t          : 3;
2013             __IM uint32_t VER : 16;    /*!< [31..16] Version information Version information of the GLCDC             */
2014         } PANEL_CLK_b;
2015     };
2016 } R_GLCDC_SYSCNT_Type;                 /*!< Size = 20 (0x14)                                                          */
2017 
2018 /**
2019  * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING)
2020  */
2021 typedef struct
2022 {
2023     union
2024     {
2025         __IOM uint16_t A;              /*!< (@ 0x00000000) GTIOCA Output Delay Register                               */
2026 
2027         struct
2028         {
2029             __IOM uint16_t DLY : 5;    /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting                           */
2030             uint16_t           : 11;
2031         } A_b;
2032     };
2033 
2034     union
2035     {
2036         __IOM uint16_t B;              /*!< (@ 0x00000002) GTIOCB Output Delay Register                               */
2037 
2038         struct
2039         {
2040             __IOM uint16_t DLY : 5;    /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting                           */
2041             uint16_t           : 11;
2042         } B_b;
2043     };
2044 } R_GPT_ODC_GTDLYR_Type;               /*!< Size = 4 (0x4)                                                            */
2045 
2046 /**
2047  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
2048  */
2049 typedef struct
2050 {
2051     union
2052     {
2053         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
2054 
2055         struct
2056         {
2057             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
2058                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
2059         } L_b;
2060     };
2061 
2062     union
2063     {
2064         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
2065 
2066         struct
2067         {
2068             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
2069             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
2070             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
2071             uint8_t            : 5;
2072         } U_b;
2073     };
2074 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
2075 
2076 /**
2077  * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers)
2078  */
2079 typedef struct
2080 {
2081     union
2082     {
2083         __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */
2084 
2085         struct
2086         {
2087             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
2088             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
2089             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
2090             uint16_t              : 13;
2091         } AC_b;
2092     };
2093     __IM uint16_t RESERVED;
2094 
2095     union
2096     {
2097         __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */
2098 
2099         struct
2100         {
2101             __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
2102                                         *   NOTE: Some low-order bits are fixed to 0.                                 */
2103         } S_b;
2104     };
2105 
2106     union
2107     {
2108         __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */
2109 
2110         struct
2111         {
2112             __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
2113                                         *   end, for use in region determination. NOTE: Some low-order
2114                                         *   bits are fixed to 1.                                                      */
2115         } E_b;
2116     };
2117     __IM uint32_t RESERVED1;
2118 } R_MPU_MMPU_MMPU_REGION_Type;         /*!< Size = 16 (0x10)                                                          */
2119 
2120 /**
2121  * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers)
2122  */
2123 typedef struct
2124 {
2125     union
2126     {
2127         __IOM uint16_t CTL;            /*!< (@ 0x00000000) Bus Master MPU Control Register                            */
2128 
2129         struct
2130         {
2131             __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable                                                */
2132             __IOM uint16_t OAD    : 1; /*!< [1..1] Operation after detection                                          */
2133             uint16_t              : 6;
2134             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2135                                         *   stored.                                                                   */
2136         } CTL_b;
2137     };
2138     __IM uint16_t RESERVED;
2139     __IM uint32_t RESERVED1[63];
2140     __IM uint16_t RESERVED2;
2141 
2142     union
2143     {
2144         __IOM uint16_t PT;                        /*!< (@ 0x00000102) Protection of Register                                     */
2145 
2146         struct
2147         {
2148             __IOM uint16_t PROTECT : 1;           /*!< [0..0] Protection of region register                                      */
2149             uint16_t               : 7;
2150             __OM uint16_t KEY      : 8;           /*!< [15..8] Write Keyword The data written to these bits are not
2151                                                    *   stored.                                                                   */
2152         } PT_b;
2153     };
2154     __IM uint32_t RESERVED3[63];
2155     __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers                                   */
2156 } R_MPU_MMPU_MMPU_Type;                           /*!< Size = 1024 (0x400)                                                       */
2157 
2158 /**
2159  * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU)
2160  */
2161 typedef struct
2162 {
2163     union
2164     {
2165         __IOM uint16_t R;              /*!< (@ 0x00000000) Access Control Register for MBIU                           */
2166 
2167         struct
2168         {
2169             uint16_t              : 2;
2170             __IOM uint16_t RPGRPA : 1;   /*!< [2..2] Master Group A Read protection                                     */
2171             __IOM uint16_t WPGRPA : 1;   /*!< [3..3] Master Group A Write protection                                    */
2172             __IOM uint16_t RPGRPB : 1;   /*!< [4..4] Master Group B Read protection                                     */
2173             __IOM uint16_t WPGRPB : 1;   /*!< [5..5] Master Group B Write protection                                    */
2174             __IOM uint16_t RPGRPC : 1;   /*!< [6..6] Master Group C Read protection                                     */
2175             __IOM uint16_t WPGRPC : 1;   /*!< [7..7] Master Group C Write protection                                    */
2176             uint16_t              : 4;
2177             __IOM uint16_t RPFLI  : 1;   /*!< [12..12] Code Flash Memory Read Protection                                */
2178             __IOM uint16_t WPFLI  : 1;   /*!< [13..13] Code Flash Memory Write Protection (Note: This bit
2179                                           *   is read as 1. The write value should be 1.)                               */
2180             __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection                                           */
2181             __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection                                          */
2182         } R_b;
2183     };
2184     __IM uint16_t RESERVED;
2185 } R_MPU_SMPU_SMPU_Type;                  /*!< Size = 4 (0x4)                                                            */
2186 
2187 /**
2188  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
2189  */
2190 typedef struct
2191 {
2192     union
2193     {
2194         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
2195                                         *                  Register                                                   */
2196 
2197         struct
2198         {
2199             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
2200             uint16_t           : 7;
2201             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
2202                                         *   stored.                                                                   */
2203         } OAD_b;
2204     };
2205     __IM uint16_t RESERVED;
2206 
2207     union
2208     {
2209         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
2210 
2211         struct
2212         {
2213             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
2214             uint16_t              : 7;
2215             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
2216             uint16_t              : 7;
2217         } CTL_b;
2218     };
2219 
2220     union
2221     {
2222         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
2223 
2224         struct
2225         {
2226             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
2227             uint16_t               : 7;
2228             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2229                                          *   stored.                                                                   */
2230         } PT_b;
2231     };
2232 
2233     union
2234     {
2235         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
2236 
2237         struct
2238         {
2239             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
2240                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
2241                                            *   The low-order 2 bits are fixed to 0.                                      */
2242         } SA_b;
2243     };
2244 
2245     union
2246     {
2247         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
2248 
2249         struct
2250         {
2251             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
2252                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
2253                                            *   The low-order 2 bits are fixed to 1.                                      */
2254         } EA_b;
2255     };
2256 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
2257 
2258 /**
2259  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
2260  */
2261 typedef struct
2262 {
2263     union
2264     {
2265         union
2266         {
2267             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
2268 
2269             struct
2270             {
2271                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2272                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2273                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2274                 uint32_t             : 1;
2275                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2276                 __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
2277                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2278                 uint32_t             : 3;
2279                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
2280                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
2281                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
2282                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
2283                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
2284                 uint32_t             : 7;
2285                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
2286                                            *   function. For individual pin functions, see the MPC table                 */
2287                 uint32_t : 3;
2288             } PmnPFS_b;
2289         };
2290 
2291         struct
2292         {
2293             union
2294             {
2295                 struct
2296                 {
2297                     __IM uint16_t RESERVED;
2298 
2299                     union
2300                     {
2301                         __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
2302 
2303                         struct
2304                         {
2305                             __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2306                             __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2307                             __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2308                             uint16_t             : 1;
2309                             __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2310                             __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
2311                             __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2312                             uint16_t             : 3;
2313                             __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
2314                             __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
2315                             __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
2316                             __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
2317                         } PmnPFS_HA_b;
2318                     };
2319                 };
2320 
2321                 struct
2322                 {
2323                     __IM uint16_t RESERVED1;
2324                     __IM uint8_t  RESERVED2;
2325 
2326                     union
2327                     {
2328                         __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
2329 
2330                         struct
2331                         {
2332                             __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2333                             __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2334                             __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2335                             uint8_t             : 1;
2336                             __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2337                             __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
2338                             __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2339                             uint8_t             : 1;
2340                         } PmnPFS_BY_b;
2341                     };
2342                 };
2343             };
2344         };
2345     };
2346 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
2347 
2348 /**
2349  * @brief R_PFS_PORT [PORT] (Port [0..14])
2350  */
2351 typedef struct
2352 {
2353     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
2354 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
2355 
2356 /**
2357  * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
2358  */
2359 typedef struct
2360 {
2361     __IM uint8_t RESERVED[389];
2362 
2363     union
2364     {
2365         __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
2366 
2367         struct
2368         {
2369             __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
2370             uint8_t             : 7;
2371         } VL1SEL_b;
2372     };
2373 } R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
2374 
2375 /**
2376  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
2377  */
2378 typedef struct
2379 {
2380     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
2381 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
2382 
2383 /**
2384  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
2385  */
2386 typedef struct
2387 {
2388     union
2389     {
2390         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
2391 
2392         struct
2393         {
2394             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
2395             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
2396             uint8_t            : 1;
2397             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
2398             uint8_t            : 1;
2399             __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
2400         } RTCCR_b;
2401     };
2402     __IM uint8_t RESERVED;
2403 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
2404 
2405 /**
2406  * @brief R_RTC_CP [CP] (Capture registers)
2407  */
2408 typedef struct
2409 {
2410     __IM uint8_t RESERVED[2];
2411 
2412     union
2413     {
2414         union
2415         {
2416             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
2417 
2418             struct
2419             {
2420                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
2421                                          *   seconds                                                                   */
2422                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
2423                                          *   seconds                                                                   */
2424                 uint8_t : 1;
2425             } RSEC_b;
2426         };
2427 
2428         union
2429         {
2430             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
2431 
2432             struct
2433             {
2434                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
2435                                            *   value when a time capture event is detected.                              */
2436             } BCNT0_b;
2437         };
2438     };
2439     __IM uint8_t RESERVED1;
2440 
2441     union
2442     {
2443         union
2444         {
2445             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
2446 
2447             struct
2448             {
2449                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
2450                                          *   minutes                                                                   */
2451                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
2452                                          *   minutes                                                                   */
2453                 uint8_t : 1;
2454             } RMIN_b;
2455         };
2456 
2457         union
2458         {
2459             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
2460 
2461             struct
2462             {
2463                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
2464                                            *   value when a time capture event is detected.                              */
2465             } BCNT1_b;
2466         };
2467     };
2468     __IM uint8_t RESERVED2;
2469 
2470     union
2471     {
2472         union
2473         {
2474             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
2475 
2476             struct
2477             {
2478                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
2479                                         *   minutes                                                                   */
2480                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
2481                                         *   minutes                                                                   */
2482                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
2483                 uint8_t         : 1;
2484             } RHR_b;
2485         };
2486 
2487         union
2488         {
2489             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
2490 
2491             struct
2492             {
2493                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
2494                                            *   value when a time capture event is detected.                              */
2495             } BCNT2_b;
2496         };
2497     };
2498     __IM uint8_t RESERVED3[3];
2499 
2500     union
2501     {
2502         union
2503         {
2504             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
2505 
2506             struct
2507             {
2508                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
2509                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
2510                 uint8_t             : 2;
2511             } RDAY_b;
2512         };
2513 
2514         union
2515         {
2516             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
2517 
2518             struct
2519             {
2520                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
2521                                            *   value when a time capture event is detected.                              */
2522             } BCNT3_b;
2523         };
2524     };
2525     __IM uint8_t RESERVED4;
2526 
2527     union
2528     {
2529         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
2530 
2531         struct
2532         {
2533             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
2534             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
2535                                         *   months                                                                    */
2536             uint8_t : 3;
2537         } RMON_b;
2538     };
2539     __IM uint8_t RESERVED5[3];
2540 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
2541 
2542 /**
2543  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2544  */
2545 typedef struct
2546 {
2547     union
2548     {
2549         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
2550 
2551         struct
2552         {
2553             uint16_t             : 8;
2554             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
2555             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
2556             uint16_t             : 6;
2557         } E_b;
2558     };
2559 
2560     union
2561     {
2562         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
2563 
2564         struct
2565         {
2566             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
2567         } N_b;
2568     };
2569 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2570 
2571 /**
2572  * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2573  */
2574 typedef struct
2575 {
2576     union
2577     {
2578         __IOM uint16_t E;              /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register                   */
2579 
2580         struct
2581         {
2582             uint16_t             : 8;
2583             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows
2584                                         *   clearing the transaction counter to 0.                                    */
2585             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter EnableEnables or disables the transaction
2586                                         *   counter function.                                                         */
2587             uint16_t : 6;
2588         } E_b;
2589     };
2590 
2591     union
2592     {
2593         __IOM uint16_t N;               /*!< (@ 0x00000002) PIPE Transaction Counter Register                          */
2594 
2595         struct
2596         {
2597             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number
2598                                          *   of total packets (number of transactions) to be received
2599                                          *   by the relevant PIPE.When read from: When TRENB = 0: Indicate
2600                                          *   the specified number of transactions.When TRENB = 1: Indicate
2601                                          *   the number of currently counted transactions.                             */
2602         } N_b;
2603     };
2604 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2605 
2606 /**
2607  * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
2608  */
2609 typedef struct
2610 {
2611     union
2612     {
2613         __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
2614 
2615         struct
2616         {
2617             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
2618             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
2619             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
2620             uint8_t              : 1;
2621             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
2622             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
2623             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
2624             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
2625         } AGTCR_b;
2626     };
2627 
2628     union
2629     {
2630         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
2631 
2632         struct
2633         {
2634             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
2635             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
2636             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
2637             uint8_t              : 1;
2638         } AGTMR1_b;
2639     };
2640 
2641     union
2642     {
2643         __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
2644 
2645         struct
2646         {
2647             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
2648                                         *   ratio                                                                     */
2649             uint8_t           : 4;
2650             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
2651         } AGTMR2_b;
2652     };
2653 
2654     union
2655     {
2656         __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
2657 
2658         struct
2659         {
2660             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2661             uint8_t            : 2;
2662             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2663             uint8_t            : 3;
2664         } AGTIOSEL_ALT_b;
2665     };
2666 
2667     union
2668     {
2669         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
2670 
2671         struct
2672         {
2673             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
2674                                         *   mode.                                                                     */
2675             uint8_t             : 1;
2676             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
2677             uint8_t             : 1;
2678             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
2679             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
2680         } AGTIOC_b;
2681     };
2682 
2683     union
2684     {
2685         __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
2686 
2687         struct
2688         {
2689             uint8_t            : 2;
2690             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
2691             uint8_t            : 5;
2692         } AGTISR_b;
2693     };
2694 
2695     union
2696     {
2697         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
2698 
2699         struct
2700         {
2701             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
2702             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
2703             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
2704             uint8_t              : 1;
2705             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
2706             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
2707             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
2708             uint8_t              : 1;
2709         } AGTCMSR_b;
2710     };
2711 
2712     union
2713     {
2714         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
2715 
2716         struct
2717         {
2718             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2719             uint8_t            : 2;
2720             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2721             uint8_t            : 3;
2722         } AGTIOSEL_b;
2723     };
2724 } R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
2725 
2726 /**
2727  * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
2728  */
2729 typedef struct
2730 {
2731     union
2732     {
2733         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
2734 
2735         struct
2736         {
2737             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
2738                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2739                                         *   counter is forcibly stopped and set to FFFFH.                             */
2740         } AGT_b;
2741     };
2742 
2743     union
2744     {
2745         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
2746 
2747         struct
2748         {
2749             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
2750                                          *   written to the TSTOP bit in the AGTCRn register, set to
2751                                          *   FFFFH                                                                     */
2752         } AGTCMA_b;
2753     };
2754 
2755     union
2756     {
2757         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
2758 
2759         struct
2760         {
2761             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
2762                                          *   written to the TSTOP bit in the AGTCR register, set to
2763                                          *   FFFFH                                                                     */
2764         } AGTCMB_b;
2765     };
2766     __IM uint16_t                 RESERVED;
2767     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
2768 } R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
2769 
2770 /**
2771  * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
2772  */
2773 typedef struct
2774 {
2775     union
2776     {
2777         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
2778 
2779         struct
2780         {
2781             __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
2782                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2783                                         *   counter is forcibly stopped and set to FFFFH.                             */
2784         } AGT_b;
2785     };
2786 
2787     union
2788     {
2789         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
2790 
2791         struct
2792         {
2793             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
2794                                          *   written to the TSTOP bit in the AGTCRn register, set to
2795                                          *   FFFFH                                                                     */
2796         } AGTCMA_b;
2797     };
2798 
2799     union
2800     {
2801         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
2802 
2803         struct
2804         {
2805             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
2806                                          *   written to the TSTOP bit in the AGTCR register, set to
2807                                          *   FFFFH                                                                     */
2808         } AGTCMB_b;
2809     };
2810     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
2811 } R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
2812 
2813 /** @} */ /* End of group Device_Peripheral_clusters */
2814 
2815 /* =========================================================================================================================== */
2816 /* ================                            Device Specific Peripheral Section                             ================ */
2817 /* =========================================================================================================================== */
2818 
2819 /** @addtogroup Device_Peripheral_peripherals
2820  * @{
2821  */
2822 
2823 /* =========================================================================================================================== */
2824 /* ================                                         R_ACMPHS0                                         ================ */
2825 /* =========================================================================================================================== */
2826 
2827 /**
2828  * @brief High-Speed Analog Comparator (R_ACMPHS0)
2829  */
2830 
2831 typedef struct                         /*!< (@ 0x40085000) R_ACMPHS0 Structure                                        */
2832 {
2833     union
2834     {
2835         __IOM uint8_t CMPCTL;          /*!< (@ 0x00000000) Comparator Control Register                                */
2836 
2837         struct
2838         {
2839             __IOM uint8_t CINV   : 1;  /*!< [0..0] Comparator output polarity selection                               */
2840             __IOM uint8_t COE    : 1;  /*!< [1..1] Comparator output enable                                           */
2841             __IOM uint8_t CSTEN  : 1;  /*!< [2..2] Interrupt Select                                                   */
2842             __IOM uint8_t CEG    : 2;  /*!< [4..3] Selection of valid edge (Edge selector)                            */
2843             __IOM uint8_t CDFS   : 2;  /*!< [6..5] Noise filter selection                                             */
2844             __IOM uint8_t HCMPON : 1;  /*!< [7..7] Comparator operation control                                       */
2845         } CMPCTL_b;
2846     };
2847     __IM uint8_t RESERVED[3];
2848 
2849     union
2850     {
2851         __IOM uint8_t CMPSEL0;         /*!< (@ 0x00000004) Comparator Input Select Register                           */
2852 
2853         struct
2854         {
2855             __IOM uint8_t CMPSEL : 4;  /*!< [3..0] Comparator Input Selection                                         */
2856             uint8_t              : 4;
2857         } CMPSEL0_b;
2858     };
2859     __IM uint8_t RESERVED1[3];
2860 
2861     union
2862     {
2863         __IOM uint8_t CMPSEL1;         /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
2864 
2865         struct
2866         {
2867             __IOM uint8_t CRVS : 6;    /*!< [5..0] Reference Voltage Selection                                        */
2868             uint8_t            : 2;
2869         } CMPSEL1_b;
2870     };
2871     __IM uint8_t RESERVED2[3];
2872 
2873     union
2874     {
2875         __IM uint8_t CMPMON;           /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
2876 
2877         struct
2878         {
2879             __IM uint8_t CMPMON : 1;   /*!< [0..0] Comparator output monitor                                          */
2880             uint8_t             : 7;
2881         } CMPMON_b;
2882     };
2883     __IM uint8_t RESERVED3[3];
2884 
2885     union
2886     {
2887         __IOM uint8_t CPIOC;           /*!< (@ 0x00000010) Comparator Output Control Register                         */
2888 
2889         struct
2890         {
2891             __IOM uint8_t CPOE   : 1;  /*!< [0..0] Comparator output selection                                        */
2892             uint8_t              : 6;
2893             __IOM uint8_t VREFEN : 1;  /*!< [7..7] Internal Vref enable                                               */
2894         } CPIOC_b;
2895     };
2896 } R_ACMPHS0_Type;                      /*!< Size = 17 (0x11)                                                          */
2897 
2898 /* =========================================================================================================================== */
2899 /* ================                                          R_ADC0                                           ================ */
2900 /* =========================================================================================================================== */
2901 
2902 /**
2903  * @brief A/D Converter (R_ADC0)
2904  */
2905 
2906 typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure                                           */
2907 {
2908     union
2909     {
2910         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
2911 
2912         struct
2913         {
2914             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
2915                                         *   input channel for double triggered operation. The setting
2916                                         *   is only effective while double trigger mode is selected.                  */
2917             uint16_t              : 1;
2918             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
2919             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
2920             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
2921             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
2922             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
2923             uint16_t              : 1;
2924             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
2925             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
2926             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
2927         } ADCSR_b;
2928     };
2929 
2930     union
2931     {
2932         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
2933 
2934         struct
2935         {
2936             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
2937                                         *   '1' while scanning.                                                       */
2938             uint8_t              : 6;
2939             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
2940         } ADREF_b;
2941     };
2942 
2943     union
2944     {
2945         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
2946 
2947         struct
2948         {
2949             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
2950             uint8_t             : 7;
2951         } ADEXREF_b;
2952     };
2953 
2954     union
2955     {
2956         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
2957 
2958         struct
2959         {
2960             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
2961             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
2962             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
2963             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
2964             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
2965             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
2966             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
2967             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
2968             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
2969             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
2970             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
2971             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
2972             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
2973             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
2974             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
2975             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
2976         } ADANSA_b[2];
2977     };
2978 
2979     union
2980     {
2981         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
2982                                         *                  Select Register                                            */
2983 
2984         struct
2985         {
2986             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
2987             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
2988             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
2989             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
2990             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
2991             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
2992             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
2993             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
2994             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
2995             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
2996             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
2997             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
2998             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
2999             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
3000             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
3001             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
3002         } ADADS_b[2];
3003     };
3004 
3005     union
3006     {
3007         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
3008                                         *                  Register                                                   */
3009 
3010         struct
3011         {
3012             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
3013                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
3014                                         *   average mode is selected by setting the ADADC.AVEE bit
3015                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
3016                                         *   = 010b)                                                                   */
3017             uint8_t            : 4;
3018             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
3019                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
3020                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
3021                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
3022                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
3023                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
3024                                         *   bit to 1, do not set the addition count to three times
3025                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
3026         } ADADC_b;
3027     };
3028     __IM uint8_t RESERVED;
3029 
3030     union
3031     {
3032         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
3033 
3034         struct
3035         {
3036             uint16_t               : 1;
3037             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
3038             uint16_t               : 1;
3039             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
3040             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
3041             uint16_t               : 2;
3042             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
3043             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
3044             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
3045             uint16_t               : 2;
3046             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
3047             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
3048         } ADCER_b;
3049     };
3050 
3051     union
3052     {
3053         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
3054 
3055         struct
3056         {
3057             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
3058                                         *   the A/D conversion start trigger for group B in group scan
3059                                         *   mode.                                                                     */
3060             uint16_t            : 2;
3061             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
3062                                         *   start trigger in single scan mode and continuous mode.
3063                                         *   In group scan mode, the A/D conversion start trigger for
3064                                         *   group A is selected.                                                      */
3065             uint16_t : 2;
3066         } ADSTRGR_b;
3067     };
3068 
3069     union
3070     {
3071         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
3072 
3073         struct
3074         {
3075             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
3076                                         *   Mode Select                                                               */
3077             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
3078                                         *   Mode Select                                                               */
3079             uint16_t            : 6;
3080             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
3081             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
3082             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
3083                                         *   Group B in group scan mode.                                               */
3084             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
3085                                         *   Group B in group scan mode.                                               */
3086             uint16_t             : 2;
3087             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
3088             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
3089         } ADEXICR_b;
3090     };
3091 
3092     union
3093     {
3094         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
3095 
3096         struct
3097         {
3098             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
3099             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
3100             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
3101             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
3102             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
3103             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
3104             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
3105             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
3106             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
3107             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
3108             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
3109             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
3110             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
3111             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
3112             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
3113             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
3114         } ADANSB_b[2];
3115     };
3116 
3117     union
3118     {
3119         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
3120 
3121         struct
3122         {
3123             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3124                                          *   result of A/D conversion in response to the second trigger
3125                                          *   in double trigger mode.                                                   */
3126         } ADDBLDR_b;
3127     };
3128 
3129     union
3130     {
3131         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
3132 
3133         struct
3134         {
3135             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3136                                         *   A/D conversion result of temperature sensor output.                       */
3137         } ADTSDR_b;
3138     };
3139 
3140     union
3141     {
3142         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
3143 
3144         struct
3145         {
3146             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3147                                         *   A/D result of internal reference voltage.                                 */
3148         } ADOCDR_b;
3149     };
3150 
3151     union
3152     {
3153         union
3154         {
3155             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
3156 
3157             struct
3158             {
3159                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
3160                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
3161                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
3162             } ADRD_RIGHT_b;
3163         };
3164 
3165         union
3166         {
3167             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
3168 
3169             struct
3170             {
3171                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
3172                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
3173                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
3174             } ADRD_LEFT_b;
3175         };
3176     };
3177 
3178     union
3179     {
3180         __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
3181 
3182         struct
3183         {
3184             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
3185                                         *   storing the result of A/D conversion.                                     */
3186         } ADDR_b[29];
3187     };
3188     __IM uint16_t RESERVED1;
3189     __IM uint32_t RESERVED2;
3190     __IM uint16_t RESERVED3;
3191 
3192     union
3193     {
3194         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
3195 
3196         struct
3197         {
3198             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
3199         } ADAMPOFF_b;
3200     };
3201 
3202     union
3203     {
3204         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
3205 
3206         struct
3207         {
3208             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
3209             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
3210             uint8_t            : 6;
3211         } ADTSTPR_b;
3212     };
3213 
3214     union
3215     {
3216         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
3217 
3218         struct
3219         {
3220             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
3221             uint16_t              : 3;
3222             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
3223             uint16_t              : 2;
3224             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
3225         } ADDDACER_b;
3226     };
3227 
3228     union
3229     {
3230         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
3231 
3232         struct
3233         {
3234             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
3235                                         *   Setting Set the sampling time (4 to 255 states)                           */
3236             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
3237             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
3238             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
3239             uint16_t              : 5;
3240         } ADSHCR_b;
3241     };
3242 
3243     union
3244     {
3245         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
3246 
3247         struct
3248         {
3249             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
3250                                         *   only for channel.                                                         */
3251             uint16_t             : 1;
3252             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
3253             uint16_t             : 2;
3254             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
3255                                         *   for adjustment to hardening of process.                                   */
3256             uint16_t              : 1;
3257             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
3258                                         *   power save bit for A/D hard macro to hardening of process.                */
3259             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
3260                                         *   bit for A/D hard macro to hardening of process.                           */
3261             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
3262                                         *   bit for A/D hard macro to hardening of process.                           */
3263         } ADEXTSTR_b;
3264     };
3265 
3266     union
3267     {
3268         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
3269 
3270         struct
3271         {
3272             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
3273             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
3274                                            *   amplifier test.Refreshing the pressure switch that opens
3275                                            *   for the DAC output voltage charge period when the amplifier
3276                                            *   of the S&H circuit is tested only for the channel is set.                 */
3277             uint16_t            : 1;
3278             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
3279                                            *   bit.                                                                      */
3280             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
3281                                            *   bit                                                                       */
3282             uint16_t                 : 1;
3283             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
3284                                            *   module Details are described to the bit explanation.                      */
3285             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
3286                                            *   bit explanation.                                                          */
3287         } ADTSTRA_b;
3288     };
3289 
3290     union
3291     {
3292         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
3293 
3294         struct
3295         {
3296             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
3297                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
3298             uint16_t : 1;
3299         } ADTSTRB_b;
3300     };
3301 
3302     union
3303     {
3304         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
3305 
3306         struct
3307         {
3308             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
3309                                          *   analog module.                                                            */
3310             uint16_t               : 4;
3311             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
3312             uint16_t               : 3;
3313         } ADTSTRC_b;
3314     };
3315 
3316     union
3317     {
3318         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
3319 
3320         struct
3321         {
3322             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
3323                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
3324             uint16_t : 15;
3325         } ADTSTRD_b;
3326     };
3327 
3328     union
3329     {
3330         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
3331 
3332         struct
3333         {
3334             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
3335             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
3336             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
3337             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
3338             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
3339             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
3340             uint16_t              : 10;
3341         } ADSWTSTR0_b;
3342     };
3343 
3344     union
3345     {
3346         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
3347 
3348         struct
3349         {
3350             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
3351             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
3352             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
3353             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
3354             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
3355             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
3356             uint16_t              : 10;
3357         } ADSWTSTR1_b;
3358     };
3359 
3360     union
3361     {
3362         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
3363 
3364         struct
3365         {
3366             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
3367                                           *   (ANEX0 switch)                                                            */
3368             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
3369                                           *   (ANEX1 switch).                                                           */
3370             uint16_t                : 2;
3371             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
3372             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
3373             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
3374             uint16_t                : 1;
3375             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
3376             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
3377             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
3378             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
3379             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
3380             uint16_t                : 3;
3381         } ADSWTSTR2_b;
3382     };
3383     __IM uint16_t RESERVED4;
3384 
3385     union
3386     {
3387         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
3388 
3389         struct
3390         {
3391             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
3392             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
3393             uint8_t              : 3;
3394         } ADDISCR_b;
3395     };
3396 
3397     union
3398     {
3399         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
3400 
3401         struct
3402         {
3403             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
3404                                         *   the pressure switch in A/D analog module is set.                          */
3405             uint8_t               : 1;
3406             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
3407             uint8_t               : 1;
3408         } ADSWCR_b;
3409     };
3410 
3411     union
3412     {
3413         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
3414 
3415         struct
3416         {
3417             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
3418                                         *   Select                                                                    */
3419             uint8_t : 7;
3420         } ADSHMSR_b;
3421     };
3422 
3423     union
3424     {
3425         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
3426 
3427         struct
3428         {
3429             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
3430             uint8_t            : 6;
3431         } ADICR_b;
3432     };
3433 
3434     union
3435     {
3436         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
3437 
3438         struct
3439         {
3440             uint8_t             : 1;
3441             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
3442             uint8_t             : 6;
3443         } ADACSR_b;
3444     };
3445     __IM uint8_t RESERVED5;
3446 
3447     union
3448     {
3449         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
3450 
3451         struct
3452         {
3453             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
3454                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
3455                                          *   set to 01b (group scan mode). If the bits are set to any
3456                                          *   other values, proper operation is not guaranteed.                         */
3457             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
3458                                          *   when PGS = 0.)                                                            */
3459             uint16_t               : 6;
3460             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
3461             uint16_t               : 6;
3462             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
3463                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
3464                                          *   has been set to 1, single scan is performed continuously
3465                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
3466         } ADGSPCR_b;
3467     };
3468 
3469     union
3470     {
3471         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
3472                                         *                  Scan)                                                      */
3473 
3474         struct
3475         {
3476             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
3477             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
3478         } ADGSCS_b;
3479     };
3480 
3481     union
3482     {
3483         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
3484 
3485         struct
3486         {
3487             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
3488                                           *   the result of A/D conversion in response to the respective
3489                                           *   triggers during extended operation in double trigger mode.                */
3490         } ADDBLDRA_b;
3491     };
3492 
3493     union
3494     {
3495         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
3496 
3497         struct
3498         {
3499             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
3500                                           *   the result of A/D conversion in response to the respective
3501                                           *   triggers during extended operation in double trigger mode.                */
3502         } ADDBLDRB_b;
3503     };
3504 
3505     union
3506     {
3507         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
3508 
3509         struct
3510         {
3511             uint8_t             : 7;
3512             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
3513         } ADSER_b;
3514     };
3515     __IM uint8_t RESERVED6;
3516 
3517     union
3518     {
3519         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
3520                                         *                  Control Register                                           */
3521 
3522         struct
3523         {
3524             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
3525             uint8_t             : 2;
3526             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
3527             uint8_t             : 2;
3528             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
3529         } ADHVREFCNT_b;
3530     };
3531     __IM uint8_t RESERVED7;
3532 
3533     union
3534     {
3535         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
3536                                         *                  Register                                                   */
3537 
3538         struct
3539         {
3540             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
3541                                         *   result.This bit is valid when both window A operation and
3542                                         *   window B operation are enabled.                                           */
3543             uint8_t              : 3;
3544             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
3545             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
3546             uint8_t              : 2;
3547         } ADWINMON_b;
3548     };
3549     __IM uint8_t  RESERVED8;
3550     __IM uint16_t RESERVED9;
3551 
3552     union
3553     {
3554         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
3555 
3556         struct
3557         {
3558             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
3559                                         *   are valid when both window A and window B are enabled (CMPAE
3560                                         *   = 1 and CMPBE = 1).                                                       */
3561             uint16_t              : 7;
3562             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
3563             uint16_t              : 1;
3564             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
3565             uint16_t              : 1;
3566             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
3567             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
3568             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
3569         } ADCMPCR_b;
3570     };
3571 
3572     union
3573     {
3574         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
3575                                         *                  Select Register                                            */
3576 
3577         struct
3578         {
3579             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
3580             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
3581             uint8_t              : 6;
3582         } ADCMPANSER_b;
3583     };
3584 
3585     union
3586     {
3587         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
3588                                         *                  Comparison Condition Setting Register                      */
3589 
3590         struct
3591         {
3592             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
3593                                         *   Condition Select                                                          */
3594             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
3595                                         *   Select                                                                    */
3596             uint8_t : 6;
3597         } ADCMPLER_b;
3598     };
3599 
3600     union
3601     {
3602         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
3603                                           *                  Register                                                   */
3604 
3605         struct
3606         {
3607             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
3608             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
3609             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
3610             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
3611             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
3612             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
3613             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
3614             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
3615             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
3616             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
3617             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
3618             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
3619             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
3620             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
3621             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
3622             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
3623         } ADCMPANSR_b[2];
3624     };
3625 
3626     union
3627     {
3628         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
3629                                            *                  Setting Register                                           */
3630 
3631         struct
3632         {
3633             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
3634             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
3635             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
3636             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
3637             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
3638             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
3639             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
3640             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
3641             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
3642             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
3643             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
3644             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
3645             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
3646             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
3647             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
3648             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
3649         } ADCMPLR_b[2];
3650     };
3651 
3652     union
3653     {
3654         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
3655                                            *                  Setting Register                                           */
3656 
3657         struct
3658         {
3659             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
3660                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
3661                                            *   level of window A.                                                        */
3662         } ADCMPDR0_b;
3663     };
3664 
3665     union
3666     {
3667         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
3668                                            *                  Setting Register                                           */
3669 
3670         struct
3671         {
3672             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
3673                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
3674                                            *   level of window A..                                                       */
3675         } ADCMPDR1_b;
3676     };
3677 
3678     union
3679     {
3680         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
3681                                             *                  Register                                                   */
3682 
3683         struct
3684         {
3685             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
3686             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
3687             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
3688             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
3689             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
3690             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
3691             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
3692             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
3693             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
3694             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
3695             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
3696             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
3697             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
3698             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
3699             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
3700             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
3701         } ADCMPSR_b[2];
3702     };
3703 
3704     union
3705     {
3706         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
3707                                          *                  Channel Status Register                                    */
3708 
3709         struct
3710         {
3711             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
3712                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3713                                          *   this bit indicates the temperature sensor output comparison
3714                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3715                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3716                                          *   time.                                                                     */
3717             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
3718                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3719                                          *   this bit indicates the temperature sensor output comparison
3720                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3721                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3722                                          *   time.                                                                     */
3723             uint8_t : 6;
3724         } ADCMPSER_b;
3725     };
3726     __IM uint8_t RESERVED10;
3727 
3728     union
3729     {
3730         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
3731                                         *                  Register                                                   */
3732 
3733         struct
3734         {
3735             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
3736                                         *   compares it on the condition of compare window B is selected.             */
3737             uint8_t             : 1;
3738             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
3739         } ADCMPBNSR_b;
3740     };
3741     __IM uint8_t RESERVED11;
3742 
3743     union
3744     {
3745         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
3746                                            *                  Setting Register                                           */
3747 
3748         struct
3749         {
3750             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
3751                                            *   used to set the lower level of the window B.                              */
3752         } ADWINLLB_b;
3753     };
3754 
3755     union
3756     {
3757         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
3758                                            *                  Setting Register                                           */
3759 
3760         struct
3761         {
3762             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
3763                                            *   used to set the higher level of the window B.                             */
3764         } ADWINULB_b;
3765     };
3766 
3767     union
3768     {
3769         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
3770 
3771         struct
3772         {
3773             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
3774                                         *   the comparative result of CH (AN000-AN027, temperature
3775                                         *   sensor, and internal reference voltage) made the object
3776                                         *   of window B relation condition.                                           */
3777             uint8_t : 7;
3778         } ADCMPBSR_b;
3779     };
3780     __IM uint8_t  RESERVED12;
3781     __IM uint16_t RESERVED13;
3782 
3783     union
3784     {
3785         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
3786 
3787         struct
3788         {
3789             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3790                                         *   registers that sequentially store all A/D converted values.
3791                                         *   The automatic clear function is not applied to these registers.           */
3792         } ADBUF0_b;
3793     };
3794 
3795     union
3796     {
3797         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
3798 
3799         struct
3800         {
3801             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3802                                         *   registers that sequentially store all A/D converted values.
3803                                         *   The automatic clear function is not applied to these registers.           */
3804         } ADBUF1_b;
3805     };
3806 
3807     union
3808     {
3809         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
3810 
3811         struct
3812         {
3813             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3814                                         *   registers that sequentially store all A/D converted values.
3815                                         *   The automatic clear function is not applied to these registers.           */
3816         } ADBUF2_b;
3817     };
3818 
3819     union
3820     {
3821         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
3822 
3823         struct
3824         {
3825             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3826                                         *   registers that sequentially store all A/D converted values.
3827                                         *   The automatic clear function is not applied to these registers.           */
3828         } ADBUF3_b;
3829     };
3830 
3831     union
3832     {
3833         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
3834 
3835         struct
3836         {
3837             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3838                                         *   registers that sequentially store all A/D converted values.
3839                                         *   The automatic clear function is not applied to these registers.           */
3840         } ADBUF4_b;
3841     };
3842 
3843     union
3844     {
3845         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
3846 
3847         struct
3848         {
3849             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3850                                         *   registers that sequentially store all A/D converted values.
3851                                         *   The automatic clear function is not applied to these registers.           */
3852         } ADBUF5_b;
3853     };
3854 
3855     union
3856     {
3857         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
3858 
3859         struct
3860         {
3861             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3862                                         *   registers that sequentially store all A/D converted values.
3863                                         *   The automatic clear function is not applied to these registers.           */
3864         } ADBUF6_b;
3865     };
3866 
3867     union
3868     {
3869         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
3870 
3871         struct
3872         {
3873             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3874                                         *   registers that sequentially store all A/D converted values.
3875                                         *   The automatic clear function is not applied to these registers.           */
3876         } ADBUF7_b;
3877     };
3878 
3879     union
3880     {
3881         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
3882 
3883         struct
3884         {
3885             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3886                                         *   registers that sequentially store all A/D converted values.
3887                                         *   The automatic clear function is not applied to these registers.           */
3888         } ADBUF8_b;
3889     };
3890 
3891     union
3892     {
3893         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
3894 
3895         struct
3896         {
3897             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3898                                         *   registers that sequentially store all A/D converted values.
3899                                         *   The automatic clear function is not applied to these registers.           */
3900         } ADBUF9_b;
3901     };
3902 
3903     union
3904     {
3905         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
3906 
3907         struct
3908         {
3909             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3910                                         *   registers that sequentially store all A/D converted values.
3911                                         *   The automatic clear function is not applied to these registers.           */
3912         } ADBUF10_b;
3913     };
3914 
3915     union
3916     {
3917         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
3918 
3919         struct
3920         {
3921             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3922                                         *   registers that sequentially store all A/D converted values.
3923                                         *   The automatic clear function is not applied to these registers.           */
3924         } ADBUF11_b;
3925     };
3926 
3927     union
3928     {
3929         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
3930 
3931         struct
3932         {
3933             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3934                                         *   registers that sequentially store all A/D converted values.
3935                                         *   The automatic clear function is not applied to these registers.           */
3936         } ADBUF12_b;
3937     };
3938 
3939     union
3940     {
3941         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
3942 
3943         struct
3944         {
3945             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3946                                         *   registers that sequentially store all A/D converted values.
3947                                         *   The automatic clear function is not applied to these registers.           */
3948         } ADBUF13_b;
3949     };
3950 
3951     union
3952     {
3953         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
3954 
3955         struct
3956         {
3957             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3958                                         *   registers that sequentially store all A/D converted values.
3959                                         *   The automatic clear function is not applied to these registers.           */
3960         } ADBUF14_b;
3961     };
3962 
3963     union
3964     {
3965         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
3966 
3967         struct
3968         {
3969             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3970                                         *   registers that sequentially store all A/D converted values.
3971                                         *   The automatic clear function is not applied to these registers.           */
3972         } ADBUF15_b;
3973     };
3974 
3975     union
3976     {
3977         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
3978 
3979         struct
3980         {
3981             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
3982             uint8_t             : 7;
3983         } ADBUFEN_b;
3984     };
3985     __IM uint8_t RESERVED14;
3986 
3987     union
3988     {
3989         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
3990 
3991         struct
3992         {
3993             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
3994                                         *   data buffer to which the next A/D converted data is transferred.          */
3995             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
3996             uint8_t             : 3;
3997         } ADBUFPTR_b;
3998     };
3999     __IM uint8_t  RESERVED15;
4000     __IM uint32_t RESERVED16[2];
4001     __IM uint8_t  RESERVED17;
4002 
4003     union
4004     {
4005         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
4006 
4007         struct
4008         {
4009             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
4010         } ADSSTRL_b;
4011     };
4012 
4013     union
4014     {
4015         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
4016 
4017         struct
4018         {
4019             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
4020         } ADSSTRT_b;
4021     };
4022 
4023     union
4024     {
4025         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
4026 
4027         struct
4028         {
4029             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
4030         } ADSSTRO_b;
4031     };
4032 
4033     union
4034     {
4035         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
4036 
4037         struct
4038         {
4039             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
4040         } ADSSTR_b[16];
4041     };
4042 
4043     union
4044     {
4045         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
4046 
4047         struct
4048         {
4049             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
4050             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
4051             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
4052             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
4053             uint16_t             : 12;
4054         } ADANIM_b;
4055     };
4056 
4057     union
4058     {
4059         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
4060 
4061         struct
4062         {
4063             uint8_t              : 6;
4064             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
4065             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
4066         } ADCALEXE_b;
4067     };
4068     __IM uint8_t RESERVED18;
4069 
4070     union
4071     {
4072         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
4073                                           *                  Register                                                   */
4074 
4075         struct
4076         {
4077             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
4078             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
4079             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
4080             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
4081             uint8_t                 : 2;
4082             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
4083         } VREFAMPCNT_b;
4084     };
4085     __IM uint8_t  RESERVED19;
4086     __IM uint16_t RESERVED20;
4087 
4088     union
4089     {
4090         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
4091 
4092         struct
4093         {
4094             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
4095         } ADRD_b;
4096     };
4097 
4098     union
4099     {
4100         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
4101 
4102         struct
4103         {
4104             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
4105             uint8_t             : 6;
4106         } ADRST_b;
4107     };
4108     __IM uint8_t  RESERVED21;
4109     __IM uint32_t RESERVED22[41];
4110 
4111     union
4112     {
4113         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
4114 
4115         struct
4116         {
4117             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
4118             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
4119             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
4120             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
4121             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
4122             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
4123             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
4124             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
4125             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
4126             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
4127             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
4128             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
4129             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
4130             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
4131             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
4132             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
4133         } ADPGACR_b;
4134     };
4135 
4136     union
4137     {
4138         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
4139                                           *                  Register 0                                                 */
4140 
4141         struct
4142         {
4143             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
4144                                           *   b) when the shingle end is input and each PGA P000 is set.
4145                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
4146                                           *   sets the gain magnification when the differential motion
4147                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
4148             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
4149                                           *   b) when the shingle end is input and each PGA P001 is set.
4150                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
4151                                           *   sets the gain magnification when the differential motion
4152                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
4153             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
4154                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
4155                                           *   each PGA P002 is set. When the differential motion is input,
4156                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
4157                                           *   the differential motion is input by the combination with
4158                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
4159             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
4160                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
4161                                           *   each PGA P003 is set. When the differential motion is input,
4162                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
4163                                           *   the differential motion is input by the combination with
4164                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
4165         } ADPGAGS0_b;
4166     };
4167     __IM uint32_t RESERVED23[3];
4168 
4169     union
4170     {
4171         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
4172                                          *                  Input Control Register                                     */
4173 
4174         struct
4175         {
4176             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
4177                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
4178             uint16_t               : 1;
4179             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
4180             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
4181                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
4182             uint16_t               : 1;
4183             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
4184             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
4185                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
4186             uint16_t               : 1;
4187             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
4188             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
4189                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
4190             uint16_t               : 1;
4191             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
4192         } ADPGADCR0_b;
4193     };
4194     __IM uint16_t RESERVED24;
4195 
4196     union
4197     {
4198         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
4199                                         *                  Input Bias Select Register 0                               */
4200 
4201         struct
4202         {
4203             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
4204                                         *   SelectNOTE: This bit selects the input bias voltage value
4205                                         *   when differential inputs are used.                                        */
4206             uint8_t : 7;
4207         } ADPGADBS0_b;
4208     };
4209 
4210     union
4211     {
4212         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
4213                                         *                  Input Bias Select Register 1                               */
4214 
4215         struct
4216         {
4217             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
4218                                         *   This bit selects the input bias voltage value when differential
4219                                         *   inputs are used.                                                          */
4220             uint8_t : 7;
4221         } ADPGADBS1_b;
4222     };
4223     __IM uint16_t RESERVED25;
4224     __IM uint32_t RESERVED26[10];
4225 
4226     union
4227     {
4228         __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
4229 
4230         struct
4231         {
4232             __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
4233             uint32_t              : 13;
4234             __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
4235             uint32_t              : 12;
4236         } ADREFMON_b;
4237     };
4238 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
4239 
4240 /* =========================================================================================================================== */
4241 /* ================                                           R_BUS                                           ================ */
4242 /* =========================================================================================================================== */
4243 
4244 /**
4245  * @brief Bus Interface (R_BUS)
4246  */
4247 
4248 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
4249 {
4250     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
4251     __IM uint32_t        RESERVED[480];
4252     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
4253 
4254     union
4255     {
4256         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
4257 
4258         struct
4259         {
4260             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
4261             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
4262             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
4263             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
4264             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
4265             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
4266             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
4267             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
4268             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
4269             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
4270             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4271             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4272             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4273             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4274             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4275             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4276         } CSRECEN_b;
4277     };
4278     __IM uint16_t          RESERVED1;
4279     __IM uint32_t          RESERVED2[223];
4280     __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
4281     __IM uint32_t          RESERVED3[235];
4282 
4283     union
4284     {
4285         __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
4286         __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
4287     };
4288     __IM uint32_t RESERVED4[58];
4289 
4290     union
4291     {
4292         union
4293         {
4294             __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */
4295 
4296             struct
4297             {
4298                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
4299                 uint32_t            : 31;
4300             } BUSMABT_b;
4301         };
4302         __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
4303     };
4304     __IM uint32_t RESERVED5[46];
4305 
4306     union
4307     {
4308         __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
4309         __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
4310     };
4311     __IM uint32_t RESERVED6[33];
4312 
4313     union
4314     {
4315         __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */
4316 
4317         struct
4318         {
4319             __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
4320             uint32_t                : 2;
4321             __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
4322             uint32_t                : 12;
4323             __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
4324             uint32_t                : 15;
4325         } BUSDIVBYP_b;
4326     };
4327     __IM uint32_t            RESERVED7[319];
4328     __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
4329     __IM uint32_t            RESERVED8[16];
4330 
4331     union
4332     {
4333         __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
4334         __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
4335                                               *                  and Read/Write Status registers.                           */
4336     };
4337     __IM uint32_t RESERVED9[28];
4338 
4339     union
4340     {
4341         __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
4342         __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
4343     };
4344     __IM uint32_t           RESERVED10[16];
4345     __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
4346     __IM uint32_t           RESERVED11[5];
4347     __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
4348 } R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */
4349 
4350 /* =========================================================================================================================== */
4351 /* ================                                           R_CAC                                           ================ */
4352 /* =========================================================================================================================== */
4353 
4354 /**
4355  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
4356  */
4357 
4358 typedef struct                         /*!< (@ 0x40044600) R_CAC Structure                                            */
4359 {
4360     union
4361     {
4362         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
4363 
4364         struct
4365         {
4366             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
4367             uint8_t            : 7;
4368         } CACR0_b;
4369     };
4370 
4371     union
4372     {
4373         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
4374 
4375         struct
4376         {
4377             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
4378             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
4379             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
4380             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
4381         } CACR1_b;
4382     };
4383 
4384     union
4385     {
4386         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
4387 
4388         struct
4389         {
4390             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
4391             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
4392             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
4393                                         *   Select                                                                    */
4394             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
4395         } CACR2_b;
4396     };
4397 
4398     union
4399     {
4400         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
4401 
4402         struct
4403         {
4404             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
4405             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
4406             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
4407             uint8_t              : 1;
4408             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
4409             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
4410             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
4411             uint8_t              : 1;
4412         } CAICR_b;
4413     };
4414 
4415     union
4416     {
4417         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
4418 
4419         struct
4420         {
4421             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
4422             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
4423             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
4424             uint8_t            : 5;
4425         } CASTR_b;
4426     };
4427     __IM uint8_t RESERVED;
4428 
4429     union
4430     {
4431         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
4432 
4433         struct
4434         {
4435             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
4436                                          *   the upper-limit value of the frequency.                                   */
4437         } CAULVR_b;
4438     };
4439 
4440     union
4441     {
4442         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
4443 
4444         struct
4445         {
4446             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
4447                                          *   the lower-limit value of the frequency.                                   */
4448         } CALLVR_b;
4449     };
4450 
4451     union
4452     {
4453         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
4454 
4455         struct
4456         {
4457             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
4458                                          *   the counter value at the time a valid reference signal
4459                                          *   edge is input                                                             */
4460         } CACNTBR_b;
4461     };
4462 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
4463 
4464 /* =========================================================================================================================== */
4465 /* ================                                          R_CAN0                                           ================ */
4466 /* =========================================================================================================================== */
4467 
4468 /**
4469  * @brief Controller Area Network (CAN) Module (R_CAN0)
4470  */
4471 
4472 typedef struct                         /*!< (@ 0x40050000) R_CAN0 Structure                                           */
4473 {
4474     __IM uint32_t        RESERVED[128];
4475     __IOM R_CAN0_MB_Type MB[32];       /*!< (@ 0x00000200) Mailbox                                                    */
4476 
4477     union
4478     {
4479         __IOM uint32_t MKR[8];         /*!< (@ 0x00000400) Mask Register                                              */
4480 
4481         struct
4482         {
4483             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
4484             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
4485             uint32_t           : 3;
4486         } MKR_b[8];
4487     };
4488 
4489     union
4490     {
4491         __IOM uint32_t FIDCR[2];       /*!< (@ 0x00000420) FIFO Received ID Compare Registers                         */
4492 
4493         struct
4494         {
4495             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
4496             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
4497             uint32_t           : 1;
4498             __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
4499             __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
4500         } FIDCR_b[2];
4501     };
4502 
4503     union
4504     {
4505         __IOM uint32_t MKIVLR;         /*!< (@ 0x00000428) Mask Invalid Register                                      */
4506 
4507         struct
4508         {
4509             __IOM uint32_t MB0  : 1;   /*!< [0..0] mailbox 0 Mask Invalid                                             */
4510             __IOM uint32_t MB1  : 1;   /*!< [1..1] mailbox 1 Mask Invalid                                             */
4511             __IOM uint32_t MB2  : 1;   /*!< [2..2] mailbox 2 Mask Invalid                                             */
4512             __IOM uint32_t MB3  : 1;   /*!< [3..3] mailbox 3 Mask Invalid                                             */
4513             __IOM uint32_t MB4  : 1;   /*!< [4..4] mailbox 4 Mask Invalid                                             */
4514             __IOM uint32_t MB5  : 1;   /*!< [5..5] mailbox 5 Mask Invalid                                             */
4515             __IOM uint32_t MB6  : 1;   /*!< [6..6] mailbox 6 Mask Invalid                                             */
4516             __IOM uint32_t MB7  : 1;   /*!< [7..7] mailbox 7 Mask Invalid                                             */
4517             __IOM uint32_t MB8  : 1;   /*!< [8..8] mailbox 8 Mask Invalid                                             */
4518             __IOM uint32_t MB9  : 1;   /*!< [9..9] mailbox 9 Mask Invalid                                             */
4519             __IOM uint32_t MB10 : 1;   /*!< [10..10] mailbox 10 Mask Invalid                                          */
4520             __IOM uint32_t MB11 : 1;   /*!< [11..11] mailbox 11 Mask Invalid                                          */
4521             __IOM uint32_t MB12 : 1;   /*!< [12..12] mailbox 12 Mask Invalid                                          */
4522             __IOM uint32_t MB13 : 1;   /*!< [13..13] mailbox 13 Mask Invalid                                          */
4523             __IOM uint32_t MB14 : 1;   /*!< [14..14] mailbox 14 Mask Invalid                                          */
4524             __IOM uint32_t MB15 : 1;   /*!< [15..15] mailbox 15 Mask Invalid                                          */
4525             __IOM uint32_t MB16 : 1;   /*!< [16..16] mailbox 16 Mask Invalid                                          */
4526             __IOM uint32_t MB17 : 1;   /*!< [17..17] mailbox 17 Mask Invalid                                          */
4527             __IOM uint32_t MB18 : 1;   /*!< [18..18] mailbox 18 Mask Invalid                                          */
4528             __IOM uint32_t MB19 : 1;   /*!< [19..19] mailbox 19 Mask Invalid                                          */
4529             __IOM uint32_t MB20 : 1;   /*!< [20..20] mailbox 20 Mask Invalid                                          */
4530             __IOM uint32_t MB21 : 1;   /*!< [21..21] mailbox 21 Mask Invalid                                          */
4531             __IOM uint32_t MB22 : 1;   /*!< [22..22] mailbox 22 Mask Invalid                                          */
4532             __IOM uint32_t MB23 : 1;   /*!< [23..23] mailbox 23 Mask Invalid                                          */
4533             __IOM uint32_t MB24 : 1;   /*!< [24..24] mailbox 24 Mask Invalid                                          */
4534             __IOM uint32_t MB25 : 1;   /*!< [25..25] mailbox 25 Mask Invalid                                          */
4535             __IOM uint32_t MB26 : 1;   /*!< [26..26] mailbox 26 Mask Invalid                                          */
4536             __IOM uint32_t MB27 : 1;   /*!< [27..27] mailbox 27 Mask Invalid                                          */
4537             __IOM uint32_t MB28 : 1;   /*!< [28..28] mailbox 28 Mask Invalid                                          */
4538             __IOM uint32_t MB29 : 1;   /*!< [29..29] mailbox 29 Mask Invalid                                          */
4539             __IOM uint32_t MB30 : 1;   /*!< [30..30] mailbox 30 Mask Invalid                                          */
4540             __IOM uint32_t MB31 : 1;   /*!< [31..31] mailbox 31 Mask Invalid                                          */
4541         } MKIVLR_b;
4542     };
4543 
4544     union
4545     {
4546         union
4547         {
4548             __IOM uint32_t MIER;         /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register                          */
4549 
4550             struct
4551             {
4552                 __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
4553                 __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
4554                 __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
4555                 __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
4556                 __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
4557                 __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
4558                 __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
4559                 __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
4560                 __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
4561                 __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
4562                 __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
4563                 __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
4564                 __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
4565                 __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
4566                 __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
4567                 __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
4568                 __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
4569                 __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
4570                 __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
4571                 __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
4572                 __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
4573                 __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
4574                 __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
4575                 __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
4576                 __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable                                      */
4577                 __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable                                      */
4578                 __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable                                      */
4579                 __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable                                      */
4580                 __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable                                      */
4581                 __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable                                      */
4582                 __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable                                      */
4583                 __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable                                      */
4584             } MIER_b;
4585         };
4586 
4587         union
4588         {
4589             __IOM uint32_t MIER_FIFO;    /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox
4590                                           *                  Mode                                                       */
4591 
4592             struct
4593             {
4594                 __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
4595                 __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
4596                 __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
4597                 __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
4598                 __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
4599                 __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
4600                 __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
4601                 __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
4602                 __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
4603                 __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
4604                 __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
4605                 __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
4606                 __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
4607                 __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
4608                 __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
4609                 __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
4610                 __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
4611                 __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
4612                 __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
4613                 __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
4614                 __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
4615                 __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
4616                 __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
4617                 __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
4618                 __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable                                   */
4619                 __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control                */
4620                 uint32_t            : 2;
4621                 __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable                                    */
4622                 __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control                 */
4623                 uint32_t            : 2;
4624             } MIER_FIFO_b;
4625         };
4626     };
4627     __IM uint32_t RESERVED1[252];
4628 
4629     union
4630     {
4631         union
4632         {
4633             __IOM uint8_t MCTL_TX[32];       /*!< (@ 0x00000820) Message Control Register for Transmit                      */
4634 
4635             struct
4636             {
4637                 __IOM uint8_t SENTDATA  : 1; /*!< [0..0] Transmission Complete Flag                                         */
4638                 __IM uint8_t  TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox
4639                                               *   setting enabled)                                                          */
4640                 __IOM uint8_t TRMABT : 1;    /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting
4641                                               *   enabled)                                                                  */
4642                 uint8_t               : 1;
4643                 __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
4644                 uint8_t               : 1;
4645                 __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
4646                 __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
4647             } MCTL_TX_b[32];
4648         };
4649 
4650         union
4651         {
4652             __IOM uint8_t MCTL_RX[32];       /*!< (@ 0x00000820) Message Control Register for Receive                       */
4653 
4654             struct
4655             {
4656                 __IOM uint8_t NEWDATA   : 1; /*!< [0..0] Reception Complete Flag                                            */
4657                 __IM uint8_t  INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting
4658                                               *   enabled)                                                                  */
4659                 __IOM uint8_t MSGLOST : 1;   /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled)                 */
4660                 uint8_t               : 1;
4661                 __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
4662                 uint8_t               : 1;
4663                 __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
4664                 __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
4665             } MCTL_RX_b[32];
4666         };
4667     };
4668 
4669     union
4670     {
4671         __IOM uint16_t CTLR;           /*!< (@ 0x00000840) Control Register                                           */
4672 
4673         struct
4674         {
4675             __IOM uint16_t MBM  : 1;   /*!< [0..0] CAN Mailbox Mode Select                                            */
4676             __IOM uint16_t IDFM : 2;   /*!< [2..1] ID Format Mode Select                                              */
4677             __IOM uint16_t MLM  : 1;   /*!< [3..3] Message Lost Mode Select                                           */
4678             __IOM uint16_t TPM  : 1;   /*!< [4..4] Transmission Priority Mode Select                                  */
4679             __IOM uint16_t TSRC : 1;   /*!< [5..5] Time Stamp Counter Reset Command                                   */
4680             __IOM uint16_t TSPS : 2;   /*!< [7..6] Time Stamp Prescaler Select                                        */
4681             __IOM uint16_t CANM : 2;   /*!< [9..8] CAN Operating Mode Select                                          */
4682             __IOM uint16_t SLPM : 1;   /*!< [10..10] CAN Sleep Mode                                                   */
4683             __IOM uint16_t BOM  : 2;   /*!< [12..11] Bus-Off Recovery Mode by a program request                       */
4684             __IOM uint16_t RBOC : 1;   /*!< [13..13] Forcible Return From Bus-Off                                     */
4685             uint16_t            : 2;
4686         } CTLR_b;
4687     };
4688 
4689     union
4690     {
4691         __IM uint16_t STR;             /*!< (@ 0x00000842) Status Register                                            */
4692 
4693         struct
4694         {
4695             __IM uint16_t NDST  : 1;   /*!< [0..0] NEWDATA Status Flag                                                */
4696             __IM uint16_t SDST  : 1;   /*!< [1..1] SENTDATA Status Flag                                               */
4697             __IM uint16_t RFST  : 1;   /*!< [2..2] Receive FIFO Status Flag                                           */
4698             __IM uint16_t TFST  : 1;   /*!< [3..3] Transmit FIFO Status Flag                                          */
4699             __IM uint16_t NMLST : 1;   /*!< [4..4] Normal Mailbox Message Lost Status Flag                            */
4700             __IM uint16_t FMLST : 1;   /*!< [5..5] FIFO Mailbox Message Lost Status Flag                              */
4701             __IM uint16_t TABST : 1;   /*!< [6..6] Transmission Abort Status Flag                                     */
4702             __IM uint16_t EST   : 1;   /*!< [7..7] Error Status Flag                                                  */
4703             __IM uint16_t RSTST : 1;   /*!< [8..8] CAN Reset Status Flag                                              */
4704             __IM uint16_t HLTST : 1;   /*!< [9..9] CAN Halt Status Flag                                               */
4705             __IM uint16_t SLPST : 1;   /*!< [10..10] CAN Sleep Status Flag                                            */
4706             __IM uint16_t EPST  : 1;   /*!< [11..11] Error-Passive Status Flag                                        */
4707             __IM uint16_t BOST  : 1;   /*!< [12..12] Bus-Off Status Flag                                              */
4708             __IM uint16_t TRMST : 1;   /*!< [13..13] Transmit Status Flag (transmitter)                               */
4709             __IM uint16_t RECST : 1;   /*!< [14..14] Receive Status Flag (receiver)                                   */
4710             uint16_t            : 1;
4711         } STR_b;
4712     };
4713 
4714     union
4715     {
4716         __IOM uint32_t BCR;            /*!< (@ 0x00000844) Bit Configuration Register                                 */
4717 
4718         struct
4719         {
4720             __IOM uint32_t CCLKS : 1;  /*!< [0..0] CAN Clock Source Selection                                         */
4721             uint32_t             : 7;
4722             __IOM uint32_t TSEG2 : 3;  /*!< [10..8] Time Segment 2 Control                                            */
4723             uint32_t             : 1;
4724             __IOM uint32_t SJW   : 2;  /*!< [13..12] Resynchronization Jump Width Control                             */
4725             uint32_t             : 2;
4726             __IOM uint32_t BRP   : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the
4727                                         *   frequency of the CAN communication clock (fCANCLK).                       */
4728             uint32_t             : 2;
4729             __IOM uint32_t TSEG1 : 4;  /*!< [31..28] Time Segment 1 Control                                           */
4730         } BCR_b;
4731     };
4732 
4733     union
4734     {
4735         __IOM uint8_t RFCR;            /*!< (@ 0x00000848) Receive FIFO Control Register                              */
4736 
4737         struct
4738         {
4739             __IOM uint8_t RFE   : 1;   /*!< [0..0] Receive FIFO Enable                                                */
4740             __IM uint8_t  RFUST : 3;   /*!< [3..1] Receive FIFO Unread Message Number Status                          */
4741             __IOM uint8_t RFMLF : 1;   /*!< [4..4] Receive FIFO Message Lost Flag                                     */
4742             __IM uint8_t  RFFST : 1;   /*!< [5..5] Receive FIFO Full Status Flag                                      */
4743             __IM uint8_t  RFWST : 1;   /*!< [6..6] Receive FIFO Buffer Warning Status Flag                            */
4744             __IM uint8_t  RFEST : 1;   /*!< [7..7] Receive FIFO Empty Status Flag                                     */
4745         } RFCR_b;
4746     };
4747 
4748     union
4749     {
4750         __OM uint8_t RFPCR;            /*!< (@ 0x00000849) Receive FIFO Pointer Control Register                      */
4751 
4752         struct
4753         {
4754             __OM uint8_t RFPCR : 8;    /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented
4755                                         *   by writing FFh to RFPCR.                                                  */
4756         } RFPCR_b;
4757     };
4758 
4759     union
4760     {
4761         __IOM uint8_t TFCR;            /*!< (@ 0x0000084A) Transmit FIFO Control Register                             */
4762 
4763         struct
4764         {
4765             __IOM uint8_t TFE   : 1;   /*!< [0..0] Transmit FIFO Enable                                               */
4766             __IM uint8_t  TFUST : 3;   /*!< [3..1] Transmit FIFO Unsent Message Number Status                         */
4767             uint8_t             : 2;
4768             __IM uint8_t TFFST  : 1;   /*!< [6..6] Transmit FIFO Full Status                                          */
4769             __IM uint8_t TFEST  : 1;   /*!< [7..7] Transmit FIFO Empty Status                                         */
4770         } TFCR_b;
4771     };
4772 
4773     union
4774     {
4775         __OM uint8_t TFPCR;            /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register                     */
4776 
4777         struct
4778         {
4779             __OM uint8_t TFPCR : 8;    /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented
4780                                         *   by writing FFh to TFPCR.                                                  */
4781         } TFPCR_b;
4782     };
4783 
4784     union
4785     {
4786         __IOM uint8_t EIER;            /*!< (@ 0x0000084C) Error Interrupt Enable Register                            */
4787 
4788         struct
4789         {
4790             __IOM uint8_t BEIE  : 1;   /*!< [0..0] Bus Error Interrupt Enable                                         */
4791             __IOM uint8_t EWIE  : 1;   /*!< [1..1] Error-Warning Interrupt Enable                                     */
4792             __IOM uint8_t EPIE  : 1;   /*!< [2..2] Error-Passive Interrupt Enable                                     */
4793             __IOM uint8_t BOEIE : 1;   /*!< [3..3] Bus-Off Entry Interrupt Enable                                     */
4794             __IOM uint8_t BORIE : 1;   /*!< [4..4] Bus-Off Recovery Interrupt Enable                                  */
4795             __IOM uint8_t ORIE  : 1;   /*!< [5..5] Overrun Interrupt Enable                                           */
4796             __IOM uint8_t OLIE  : 1;   /*!< [6..6] Overload Frame Transmit Interrupt Enable                           */
4797             __IOM uint8_t BLIE  : 1;   /*!< [7..7] Bus Lock Interrupt Enable                                          */
4798         } EIER_b;
4799     };
4800 
4801     union
4802     {
4803         __IOM uint8_t EIFR;            /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register                      */
4804 
4805         struct
4806         {
4807             __IOM uint8_t BEIF  : 1;   /*!< [0..0] Bus Error Detect Flag                                              */
4808             __IOM uint8_t EWIF  : 1;   /*!< [1..1] Error-Warning Detect Flag                                          */
4809             __IOM uint8_t EPIF  : 1;   /*!< [2..2] Error-Passive Detect Flag                                          */
4810             __IOM uint8_t BOEIF : 1;   /*!< [3..3] Bus-Off Entry Detect Flag                                          */
4811             __IOM uint8_t BORIF : 1;   /*!< [4..4] Bus-Off Recovery Detect Flag                                       */
4812             __IOM uint8_t ORIF  : 1;   /*!< [5..5] Receive Overrun Detect Flag                                        */
4813             __IOM uint8_t OLIF  : 1;   /*!< [6..6] Overload Frame Transmission Detect Flag                            */
4814             __IOM uint8_t BLIF  : 1;   /*!< [7..7] Bus Lock Detect Flag                                               */
4815         } EIFR_b;
4816     };
4817 
4818     union
4819     {
4820         __IM uint8_t RECR;             /*!< (@ 0x0000084E) Receive Error Count Register                               */
4821 
4822         struct
4823         {
4824             __IM uint8_t RECR : 8;     /*!< [7..0] Receive error count functionRECR increments or decrements
4825                                         *   the counter value according to the error status of the
4826                                         *   CAN module during reception.                                              */
4827         } RECR_b;
4828     };
4829 
4830     union
4831     {
4832         __IM uint8_t TECR;             /*!< (@ 0x0000084F) Transmit Error Count Register                              */
4833 
4834         struct
4835         {
4836             __IM uint8_t TECR : 8;     /*!< [7..0] Transmit error count functionTECR increments or decrements
4837                                         *   the counter value according to the error status of the
4838                                         *   CAN module during transmission.                                           */
4839         } TECR_b;
4840     };
4841 
4842     union
4843     {
4844         __IOM uint8_t ECSR;            /*!< (@ 0x00000850) Error Code Store Register                                  */
4845 
4846         struct
4847         {
4848             __IOM uint8_t SEF  : 1;    /*!< [0..0] Stuff Error Flag                                                   */
4849             __IOM uint8_t FEF  : 1;    /*!< [1..1] Form Error Flag                                                    */
4850             __IOM uint8_t AEF  : 1;    /*!< [2..2] ACK Error Flag                                                     */
4851             __IOM uint8_t CEF  : 1;    /*!< [3..3] CRC Error Flag                                                     */
4852             __IOM uint8_t BE1F : 1;    /*!< [4..4] Bit Error (recessive) Flag                                         */
4853             __IOM uint8_t BE0F : 1;    /*!< [5..5] Bit Error (dominant) Flag                                          */
4854             __IOM uint8_t ADEF : 1;    /*!< [6..6] ACK Delimiter Error Flag                                           */
4855             __IOM uint8_t EDPM : 1;    /*!< [7..7] Error Display Mode Select                                          */
4856         } ECSR_b;
4857     };
4858 
4859     union
4860     {
4861         __IOM uint8_t CSSR;            /*!< (@ 0x00000851) Channel Search Support Register                            */
4862 
4863         struct
4864         {
4865             __IOM uint8_t CSSR : 8;    /*!< [7..0] When the value for the channel search is input, the channel
4866                                         *   number is output to MSSR.                                                 */
4867         } CSSR_b;
4868     };
4869 
4870     union
4871     {
4872         __IM uint8_t MSSR;             /*!< (@ 0x00000852) Mailbox Search Status Register                             */
4873 
4874         struct
4875         {
4876             __IM uint8_t MBNST : 5;    /*!< [4..0] Search Result Mailbox Number Status These bits output
4877                                         *   the smallest mailbox number that is searched in each mode
4878                                         *   of MSMR.                                                                  */
4879             uint8_t           : 2;
4880             __IM uint8_t SEST : 1;     /*!< [7..7] Search Result Status                                               */
4881         } MSSR_b;
4882     };
4883 
4884     union
4885     {
4886         __IOM uint8_t MSMR;            /*!< (@ 0x00000853) Mailbox Search Mode Register                               */
4887 
4888         struct
4889         {
4890             __IOM uint8_t MBSM : 2;    /*!< [1..0] Mailbox Search Mode Select                                         */
4891             uint8_t            : 6;
4892         } MSMR_b;
4893     };
4894 
4895     union
4896     {
4897         __IM uint16_t TSR;             /*!< (@ 0x00000854) Time Stamp Register                                        */
4898 
4899         struct
4900         {
4901             __IM uint16_t TSR : 16;    /*!< [15..0] Free-running counter value for the time stamp function            */
4902         } TSR_b;
4903     };
4904 
4905     union
4906     {
4907         __IOM uint16_t AFSR;           /*!< (@ 0x00000856) Acceptance Filter Support Register                         */
4908 
4909         struct
4910         {
4911             __IOM uint16_t AFSR : 16;  /*!< [15..0] After the standard ID of a received message is written,
4912                                         *   the value converted for data table search can be read.                    */
4913         } AFSR_b;
4914     };
4915 
4916     union
4917     {
4918         __IOM uint8_t TCR;             /*!< (@ 0x00000858) Test Control Register                                      */
4919 
4920         struct
4921         {
4922             __IOM uint8_t TSTE : 1;    /*!< [0..0] CAN Test Mode Enable                                               */
4923             __IOM uint8_t TSTM : 2;    /*!< [2..1] CAN Test Mode Select                                               */
4924             uint8_t            : 5;
4925         } TCR_b;
4926     };
4927     __IM uint8_t  RESERVED2;
4928     __IM uint16_t RESERVED3;
4929 } R_CAN0_Type;                         /*!< Size = 2140 (0x85c)                                                       */
4930 
4931 /* =========================================================================================================================== */
4932 /* ================                                           R_CRC                                           ================ */
4933 /* =========================================================================================================================== */
4934 
4935 /**
4936  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
4937  */
4938 
4939 typedef struct                         /*!< (@ 0x40074000) R_CRC Structure                                            */
4940 {
4941     union
4942     {
4943         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
4944 
4945         struct
4946         {
4947             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
4948             uint8_t              : 3;
4949             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
4950             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
4951         } CRCCR0_b;
4952     };
4953 
4954     union
4955     {
4956         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
4957 
4958         struct
4959         {
4960             uint8_t              : 6;
4961             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
4962             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
4963         } CRCCR1_b;
4964     };
4965     __IM uint16_t RESERVED;
4966 
4967     union
4968     {
4969         union
4970         {
4971             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
4972 
4973             struct
4974             {
4975                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
4976             } CRCDIR_b;
4977         };
4978 
4979         union
4980         {
4981             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
4982 
4983             struct
4984             {
4985                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
4986                                               *   )                                                                         */
4987             } CRCDIR_BY_b;
4988         };
4989     };
4990 
4991     union
4992     {
4993         union
4994         {
4995             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
4996 
4997             struct
4998             {
4999                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
5000             } CRCDOR_b;
5001         };
5002 
5003         union
5004         {
5005             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
5006 
5007             struct
5008             {
5009                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
5010                                                 *   )                                                                         */
5011             } CRCDOR_HA_b;
5012         };
5013 
5014         union
5015         {
5016             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
5017 
5018             struct
5019             {
5020                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
5021             } CRCDOR_BY_b;
5022         };
5023     };
5024 
5025     union
5026     {
5027         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
5028 
5029         struct
5030         {
5031             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
5032             uint16_t             : 2;
5033         } CRCSAR_b;
5034     };
5035     __IM uint16_t RESERVED1;
5036 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
5037 
5038 /* =========================================================================================================================== */
5039 /* ================                                          R_CTSU                                           ================ */
5040 /* =========================================================================================================================== */
5041 
5042 /**
5043  * @brief Capacitive Touch Sensing Unit (R_CTSU)
5044  */
5045 
5046 typedef struct                            /*!< (@ 0x40081000) R_CTSU Structure                                           */
5047 {
5048     union
5049     {
5050         __IOM uint8_t CTSUCR0;            /*!< (@ 0x00000000) CTSU Control Register 0                                    */
5051 
5052         struct
5053         {
5054             __IOM uint8_t CTSUSTRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
5055             __IOM uint8_t CTSUCAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
5056             __IOM uint8_t CTSUSNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
5057             __IOM uint8_t CTSUIOC    : 1; /*!< [3..3] CTSU Transmit Pin Control                                          */
5058             __IOM uint8_t CTSUINIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
5059             uint8_t                  : 2;
5060             __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection                           */
5061         } CTSUCR0_b;
5062     };
5063 
5064     union
5065     {
5066         __IOM uint8_t CTSUCR1;            /*!< (@ 0x00000001) CTSU Control Register 1                                    */
5067 
5068         struct
5069         {
5070             __IOM uint8_t CTSUPON    : 1; /*!< [0..0] CTSU Power Supply Enable                                           */
5071             __IOM uint8_t CTSUCSW    : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control                              */
5072             __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting                           */
5073             __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment                              */
5074             __IOM uint8_t CTSUCLK    : 2; /*!< [5..4] CTSU Operating Clock Select                                        */
5075             __IOM uint8_t CTSUMD     : 2; /*!< [7..6] CTSU Measurement Mode Select                                       */
5076         } CTSUCR1_b;
5077     };
5078 
5079     union
5080     {
5081         __IOM uint8_t CTSUSDPRS;           /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register          */
5082 
5083         struct
5084         {
5085             __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
5086                                             *   setting: 3 (0011b)                                                        */
5087             __IOM uint8_t CTSUPRMODE : 2;  /*!< [5..4] CTSU Base Period and Pulse Count Setting                           */
5088             __IOM uint8_t CTSUSOFF   : 1;  /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting                */
5089             uint8_t                  : 1;
5090         } CTSUSDPRS_b;
5091     };
5092 
5093     union
5094     {
5095         __IOM uint8_t CTSUSST;         /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register            */
5096 
5097         struct
5098         {
5099             __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
5100                                         *   of these bits should be fixed to 00010000b.                               */
5101         } CTSUSST_b;
5102     };
5103 
5104     union
5105     {
5106         __IOM uint8_t CTSUMCH0;         /*!< (@ 0x00000004) CTSU Measurement Channel Register 0                        */
5107 
5108         struct
5109         {
5110             __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
5111                                          *   is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
5112                                          *   bits = 00b).Note2: If the value of CTSUMCH0 was set to
5113                                          *   b'111111 in mode other than self-capacitor single scan
5114                                          *   mode, the measurement is stopped.                                         */
5115             uint8_t : 2;
5116         } CTSUMCH0_b;
5117     };
5118 
5119     union
5120     {
5121         __IOM uint8_t CTSUMCH1;        /*!< (@ 0x00000005) CTSU Measurement Channel Register 1                        */
5122 
5123         struct
5124         {
5125             __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
5126                                         *   was set to b'111111, the measurement is stopped.                          */
5127             uint8_t : 2;
5128         } CTSUMCH1_b;
5129     };
5130 
5131     union
5132     {
5133         __IOM uint8_t CTSUCHAC[5];     /*!< (@ 0x00000006) CTSU Channel Enable Control Register                       */
5134 
5135         struct
5136         {
5137             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Enable Control                                        */
5138             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Enable Control                                        */
5139             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Enable Control                                        */
5140             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Enable Control                                        */
5141             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Enable Control                                        */
5142             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Enable Control                                        */
5143             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Enable Control                                        */
5144             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Enable Control                                        */
5145         } CTSUCHAC_b[5];
5146     };
5147 
5148     union
5149     {
5150         __IOM uint8_t CTSUCHTRC[5];    /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register             */
5151 
5152         struct
5153         {
5154             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Transmit/Receive Control                              */
5155             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Transmit/Receive Control                              */
5156             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Transmit/Receive Control                              */
5157             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Transmit/Receive Control                              */
5158             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Transmit/Receive Control                              */
5159             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Transmit/Receive Control                              */
5160             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Transmit/Receive Control                              */
5161             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Transmit/Receive Control                              */
5162         } CTSUCHTRC_b[5];
5163     };
5164 
5165     union
5166     {
5167         __IOM uint8_t CTSUDCLKC;         /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register            */
5168 
5169         struct
5170         {
5171             __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
5172                                           *   be set to 00b.                                                            */
5173             uint8_t                 : 2;
5174             __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
5175                                           *   be set to 11b.                                                            */
5176             uint8_t : 2;
5177         } CTSUDCLKC_b;
5178     };
5179 
5180     union
5181     {
5182         __IOM uint8_t CTSUST;           /*!< (@ 0x00000011) CTSU Status Register                                       */
5183 
5184         struct
5185         {
5186             __IM uint8_t CTSUSTC   : 3; /*!< [2..0] CTSU Measurement Status Counter                                    */
5187             uint8_t                : 1;
5188             __IM uint8_t  CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag                                     */
5189             __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag                                  */
5190             __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag                               */
5191             __IM uint8_t  CTSUPS   : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag                                */
5192         } CTSUST_b;
5193     };
5194 
5195     union
5196     {
5197         __IOM uint16_t CTSUSSC;        /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
5198                                         *                  Control Register                                           */
5199 
5200         struct
5201         {
5202             uint16_t                 : 8;
5203             __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting                */
5204             uint16_t                 : 4;
5205         } CTSUSSC_b;
5206     };
5207 
5208     union
5209     {
5210         __IOM uint16_t CTSUSO0;          /*!< (@ 0x00000014) CTSU Sensor Offset Register 0                              */
5211 
5212         struct
5213         {
5214             __IOM uint16_t CTSUSO : 10;  /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
5215                                           *   CTSUSO ( 0 to 1023 )                                                      */
5216             __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting                                   */
5217         } CTSUSO0_b;
5218     };
5219 
5220     union
5221     {
5222         __IOM uint16_t CTSUSO1;           /*!< (@ 0x00000016) CTSU Sensor Offset Register 1                              */
5223 
5224         struct
5225         {
5226             __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
5227                                            *   is CTSUSO ( 0 to 255 )                                                    */
5228             __IOM uint16_t CTSUSDPA : 5;  /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
5229                                            *   CTSUSDPA + 1 ) x 2                                                        */
5230             __IOM uint16_t CTSUICOG : 2;  /*!< [14..13] CTSU ICO Gain Adjustment                                         */
5231             uint16_t                : 1;
5232         } CTSUSO1_b;
5233     };
5234 
5235     union
5236     {
5237         __IM uint16_t CTSUSC;          /*!< (@ 0x00000018) CTSU Sensor Counter                                        */
5238 
5239         struct
5240         {
5241             __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
5242                                         *   result of the CTSU. These bits indicate FFFFh when an overflow
5243                                         *   occurs.                                                                   */
5244         } CTSUSC_b;
5245     };
5246 
5247     union
5248     {
5249         __IM uint16_t CTSURC;          /*!< (@ 0x0000001A) CTSU Reference Counter                                     */
5250 
5251         struct
5252         {
5253             __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
5254                                         *   result of the reference ICO.These bits indicate FFFFh when
5255                                         *   an overflow occurs.                                                       */
5256         } CTSURC_b;
5257     };
5258 
5259     union
5260     {
5261         __IM uint16_t CTSUERRS;             /*!< (@ 0x0000001C) CTSU Error Status Register                                 */
5262 
5263         struct
5264         {
5265             __IOM uint16_t CTSUSPMD    : 2; /*!< [1..0] Calibration Mode                                                   */
5266             __IOM uint16_t CTSUTSOD    : 1; /*!< [2..2] TS Pin Fixed Output                                                */
5267             __IOM uint16_t CTSUDRV     : 1; /*!< [3..3] Calibration Setting 1                                              */
5268             uint16_t                   : 2;
5269             __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3                                              */
5270             __IOM uint16_t CTSUTSOC    : 1; /*!< [7..7] Calibration Setting 2                                              */
5271             uint16_t                   : 7;
5272             __IM uint16_t CTSUICOMP    : 1; /*!< [15..15] TSCAP Voltage Error Monitor                                      */
5273         } CTSUERRS_b;
5274     };
5275     __IM uint16_t RESERVED;
5276     __IOM uint8_t CTSUTRMR;                 /*!< (@ 0x00000020) CTSU Reference Current Calibration Register                */
5277     __IM uint8_t  RESERVED1;
5278     __IM uint16_t RESERVED2;
5279 } R_CTSU_Type;                              /*!< Size = 36 (0x24)                                                          */
5280 
5281 /* =========================================================================================================================== */
5282 /* ================                                           R_DAC                                           ================ */
5283 /* =========================================================================================================================== */
5284 
5285 /**
5286  * @brief D/A Converter (R_DAC)
5287  */
5288 
5289 typedef struct                         /*!< (@ 0x4005E000) R_DAC Structure                                            */
5290 {
5291     union
5292     {
5293         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
5294 
5295         struct
5296         {
5297             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
5298                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
5299                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
5300                                         *   format.                                                                   */
5301         } DADR_b[2];
5302     };
5303 
5304     union
5305     {
5306         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
5307 
5308         struct
5309         {
5310             uint8_t             : 5;
5311             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
5312             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
5313             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
5314         } DACR_b;
5315     };
5316 
5317     union
5318     {
5319         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
5320 
5321         struct
5322         {
5323             uint8_t             : 7;
5324             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
5325         } DADPR_b;
5326     };
5327 
5328     union
5329     {
5330         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
5331 
5332         struct
5333         {
5334             uint8_t              : 7;
5335             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
5336         } DAADSCR_b;
5337     };
5338 
5339     union
5340     {
5341         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
5342 
5343         struct
5344         {
5345             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
5346             uint8_t           : 5;
5347         } DAVREFCR_b;
5348     };
5349 
5350     union
5351     {
5352         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
5353 
5354         struct
5355         {
5356             uint8_t              : 6;
5357             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
5358             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
5359         } DAAMPCR_b;
5360     };
5361 
5362     union
5363     {
5364         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
5365 
5366         struct
5367         {
5368             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
5369             uint8_t              : 7;
5370         } DAPC_b;
5371     };
5372     __IM uint16_t RESERVED[9];
5373 
5374     union
5375     {
5376         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
5377 
5378         struct
5379         {
5380             uint8_t              : 6;
5381             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
5382                                         *   to wait for stabilization of the output amplifier of D/A
5383                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
5384                                         *   but the conversion result D/A is not output from channel
5385                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
5386                                         *   stops, and the D/A conversion result of channel 0 is output
5387                                         *   through the output amplifier.                                             */
5388             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
5389                                         *   to wait for stabilization of the output amplifier of D/A
5390                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
5391                                         *   but the conversion result D/A is not output from channel
5392                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
5393                                         *   stops, and the D/A conversion result of channel 1 is output
5394                                         *   through the output amplifier.                                             */
5395         } DAASWCR_b;
5396     };
5397     __IM uint8_t  RESERVED1;
5398     __IM uint16_t RESERVED2[2129];
5399 
5400     union
5401     {
5402         __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
5403 
5404         struct
5405         {
5406             __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
5407                                          *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
5408                                          *   select unit 0 as the target synchronous unit for the MCU.
5409                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5410                                          *   conversions, select the target unit in this register in
5411                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5412                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5413                                          *   is set to 0.                                                              */
5414             __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
5415                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
5416                                          *   select unit 1 as the target synchronous unit for the MCU.
5417                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5418                                          *   conversions, select the target unit in this register in
5419                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5420                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5421                                          *   is set to 0.                                                              */
5422             uint8_t : 6;
5423         } DAADUSR_b;
5424     };
5425     __IM uint8_t  RESERVED3;
5426     __IM uint16_t RESERVED4;
5427 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
5428 
5429 /* =========================================================================================================================== */
5430 /* ================                                          R_DEBUG                                          ================ */
5431 /* =========================================================================================================================== */
5432 
5433 /**
5434  * @brief Debug Function (R_DEBUG)
5435  */
5436 
5437 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
5438 {
5439     union
5440     {
5441         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
5442 
5443         struct
5444         {
5445             uint32_t                   : 28;
5446             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
5447             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
5448             uint32_t                   : 2;
5449         } DBGSTR_b;
5450     };
5451     __IM uint32_t RESERVED[3];
5452 
5453     union
5454     {
5455         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
5456 
5457         struct
5458         {
5459             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
5460             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
5461             uint32_t                     : 12;
5462             __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
5463             __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
5464             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
5465             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
5466             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
5467             uint32_t                     : 5;
5468             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
5469             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
5470             uint32_t                     : 5;
5471             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
5472         } DBGSTOPCR_b;
5473     };
5474     __IM uint32_t RESERVED1[123];
5475 
5476     union
5477     {
5478         __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */
5479 
5480         struct
5481         {
5482             __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
5483             __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
5484             uint32_t              : 6;
5485             __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
5486             uint32_t              : 21;
5487         } FSBLSTAT_b;
5488     };
5489 } R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */
5490 
5491 /* =========================================================================================================================== */
5492 /* ================                                           R_DMA                                           ================ */
5493 /* =========================================================================================================================== */
5494 
5495 /**
5496  * @brief DMA Controller Common (R_DMA)
5497  */
5498 
5499 typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
5500 {
5501     union
5502     {
5503         __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
5504 
5505         struct
5506         {
5507             __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
5508             uint8_t            : 7;
5509         } DMAST_b;
5510     };
5511     __IM uint8_t  RESERVED;
5512     __IM uint16_t RESERVED1;
5513     __IM uint32_t RESERVED2[15];
5514 
5515     union
5516     {
5517         __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
5518 
5519         struct
5520         {
5521             __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
5522             uint32_t               : 5;
5523             __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
5524             uint32_t               : 7;
5525             __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
5526             uint32_t               : 15;
5527         } DMECHR_b;
5528     };
5529     __IM uint32_t RESERVED3[15];
5530 
5531     union
5532     {
5533         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
5534 
5535         struct
5536         {
5537             __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
5538             uint32_t            : 7;
5539             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
5540                                         *   IR flag is prohibited.                                                    */
5541             uint32_t : 15;
5542         } DELSR_b[8];
5543     };
5544 } R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
5545 
5546 /* =========================================================================================================================== */
5547 /* ================                                          R_DMAC0                                          ================ */
5548 /* =========================================================================================================================== */
5549 
5550 /**
5551  * @brief DMA Controller (R_DMAC0)
5552  */
5553 
5554 typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
5555 {
5556     union
5557     {
5558         __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
5559 
5560         struct
5561         {
5562             __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
5563         } DMSAR_b;
5564     };
5565 
5566     union
5567     {
5568         __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
5569 
5570         struct
5571         {
5572             __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
5573         } DMDAR_b;
5574     };
5575 
5576     union
5577     {
5578         __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
5579 
5580         struct
5581         {
5582             __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
5583             __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
5584             uint32_t              : 6;
5585         } DMCRA_b;
5586     };
5587 
5588     union
5589     {
5590         __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
5591 
5592         struct
5593         {
5594             __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
5595                                          *   transfer counter.                                                         */
5596             __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
5597                                          *   repeat transfer operations.                                               */
5598         } DMCRB_b;
5599     };
5600 
5601     union
5602     {
5603         __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
5604 
5605         struct
5606         {
5607             __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
5608             uint16_t            : 6;
5609             __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
5610             __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
5611             uint16_t            : 1;
5612             __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
5613             __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
5614         } DMTMD_b;
5615     };
5616     __IM uint8_t RESERVED;
5617 
5618     union
5619     {
5620         __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
5621 
5622         struct
5623         {
5624             __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
5625                                         *   Enable                                                                    */
5626             __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
5627                                         *   Enable                                                                    */
5628             __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
5629             __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
5630             __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
5631             uint8_t             : 3;
5632         } DMINT_b;
5633     };
5634 
5635     union
5636     {
5637         __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
5638 
5639         struct
5640         {
5641             __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
5642                                         *   extended repeat area on the destination address. For details
5643                                         *   on the settings.                                                          */
5644             __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
5645             __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
5646             __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
5647                                         *   repeat area on the source address. For details on the settings.           */
5648             __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
5649             __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
5650         } DMAMD_b;
5651     };
5652     __IM uint16_t RESERVED1;
5653 
5654     union
5655     {
5656         __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
5657 
5658         struct
5659         {
5660             __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
5661                                         *   as the address update mode for transfer source or destination.            */
5662         } DMOFR_b;
5663     };
5664 
5665     union
5666     {
5667         __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
5668 
5669         struct
5670         {
5671             __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
5672             uint8_t           : 7;
5673         } DMCNT_b;
5674     };
5675 
5676     union
5677     {
5678         __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
5679 
5680         struct
5681         {
5682             __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
5683             uint8_t             : 3;
5684             __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
5685             uint8_t             : 3;
5686         } DMREQ_b;
5687     };
5688 
5689     union
5690     {
5691         __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
5692 
5693         struct
5694         {
5695             __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
5696             uint8_t            : 3;
5697             __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
5698             uint8_t            : 2;
5699             __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
5700         } DMSTS_b;
5701     };
5702     __IM uint8_t   RESERVED2;
5703     __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
5704     __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
5705 
5706     union
5707     {
5708         __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
5709 
5710         struct
5711         {
5712             __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
5713                                          *   mode                                                                      */
5714             __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
5715                                          *   mode                                                                      */
5716         } DMSBS_b;
5717     };
5718 
5719     union
5720     {
5721         __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
5722 
5723         struct
5724         {
5725             __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
5726                                          *   mode                                                                      */
5727             __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
5728                                          *   mode                                                                      */
5729         } DMDBS_b;
5730     };
5731 
5732     union
5733     {
5734         __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
5735 
5736         struct
5737         {
5738             __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
5739             uint8_t           : 7;
5740         } DMBWR_b;
5741     };
5742     __IM uint8_t  RESERVED3;
5743     __IM uint16_t RESERVED4;
5744 } R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
5745 
5746 /* =========================================================================================================================== */
5747 /* ================                                           R_DOC                                           ================ */
5748 /* =========================================================================================================================== */
5749 
5750 /**
5751  * @brief Data Operation Circuit (R_DOC)
5752  */
5753 
5754 typedef struct                         /*!< (@ 0x40054100) R_DOC Structure                                            */
5755 {
5756     union
5757     {
5758         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
5759 
5760         struct
5761         {
5762             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
5763             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
5764             uint8_t               : 2;
5765             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
5766             __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
5767             uint8_t               : 1;
5768         } DOCR_b;
5769     };
5770     __IM uint8_t RESERVED;
5771 
5772     union
5773     {
5774         __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
5775 
5776         struct
5777         {
5778             __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
5779                                         *   use in the operations are stored.                                         */
5780         } DODIR_b;
5781     };
5782 
5783     union
5784     {
5785         __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
5786 
5787         struct
5788         {
5789             __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
5790                                         *   in data comparison mode. This register also stores the
5791                                         *   results of operations in data addition and data subtraction
5792                                         *   modes.                                                                    */
5793         } DODSR_b;
5794     };
5795 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
5796 
5797 /* =========================================================================================================================== */
5798 /* ================                                           R_DRW                                           ================ */
5799 /* =========================================================================================================================== */
5800 
5801 /**
5802  * @brief 2D Drawing Engine (R_DRW)
5803  */
5804 
5805 typedef struct                         /*!< (@ 0x400E4000) R_DRW Structure                                            */
5806 {
5807     union
5808     {
5809         union
5810         {
5811             __OM uint32_t CONTROL;               /*!< (@ 0x00000000) Geometry Control Register                                  */
5812 
5813             struct
5814             {
5815                 __OM uint32_t LIM1ENABLE    : 1; /*!< [0..0] Enable limiter 1                                                   */
5816                 __OM uint32_t LIM2ENABLE    : 1; /*!< [1..1] Enable limiter 2                                                   */
5817                 __OM uint32_t LIM3ENABLE    : 1; /*!< [2..2] Enable limiter 3                                                   */
5818                 __OM uint32_t LIM4ENABLE    : 1; /*!< [3..3] Enable limiter 4                                                   */
5819                 __OM uint32_t LIM5ENABLE    : 1; /*!< [4..4] Enable limiter 5                                                   */
5820                 __OM uint32_t LIM6ENABLE    : 1; /*!< [5..5] Enable limiter 6                                                   */
5821                 __OM uint32_t QUAD1ENABLE   : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2                      */
5822                 __OM uint32_t QUAD2ENABLE   : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4                      */
5823                 __OM uint32_t QUAD3ENABLE   : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6                      */
5824                 __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode                                    */
5825                 __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode                                  */
5826                 __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode                                  */
5827                 __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode                                  */
5828                 __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode                                  */
5829                 __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode                                  */
5830                 __OM uint32_t BAND1ENABLE   : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND)               */
5831                 __OM uint32_t BAND2ENABLE   : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND)               */
5832                 __OM uint32_t UNION12       : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A)               */
5833                 __OM uint32_t UNION34       : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B)               */
5834                 __OM uint32_t UNION56       : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D)               */
5835                 __OM uint32_t UNIONAB       : 1; /*!< [20..20] Combine outputs A & B as union (output is called C)              */
5836                 __OM uint32_t UNIONCD       : 1; /*!< [21..21] Combine outputs C & D as union (output is final)                 */
5837                 __OM uint32_t SPANABORT     : 1; /*!< [22..22] Shape is horizontally convex, only a single span per
5838                                                   *   scanline                                                                  */
5839                 __OM uint32_t SPANSTORE : 1;     /*!< [23..23] Nextline span start is always equal or left to current-line
5840                                                   *   span start                                                                */
5841                 uint32_t : 8;
5842             } CONTROL_b;
5843         };
5844 
5845         union
5846         {
5847             __IM uint32_t STATUS;               /*!< (@ 0x00000000) Status Control Register                                    */
5848 
5849             struct
5850             {
5851                 __IM uint32_t BUSYENUM     : 1; /*!< [0..0] Enumeration unit status                                            */
5852                 __IM uint32_t BUSYWRITE    : 1; /*!< [1..1] Framebuffer writeback status                                       */
5853                 __IM uint32_t CACHEDIRTY   : 1; /*!< [2..2] Framebuffer cache status                                           */
5854                 __IM uint32_t DLISTACTIVE  : 1; /*!< [3..3] Display list reader status                                         */
5855                 __IM uint32_t ENUMIRQ      : 1; /*!< [4..4] enumeration finished interrupt triggered                           */
5856                 __IM uint32_t DLISTIRQ     : 1; /*!< [5..5] display list finished interrupt triggered                          */
5857                 __IM uint32_t BUSIRQ       : 1; /*!< [6..6] bus error interrupt triggered                                      */
5858                 uint32_t                   : 1;
5859                 __IM uint32_t BUSERRMFB    : 1; /*!< [8..8] framebuffer bus error interrupt triggered                          */
5860                 __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered                              */
5861                 __IM uint32_t BUSERRMDL    : 1; /*!< [10..10] display list bus error interrupt triggered                       */
5862                 uint32_t                   : 21;
5863             } STATUS_b;
5864         };
5865     };
5866 
5867     union
5868     {
5869         union
5870         {
5871             __OM uint32_t CONTROL2;                /*!< (@ 0x00000004) Surface Control Register                                   */
5872 
5873             struct
5874             {
5875                 __OM uint32_t PATTERNENABLE : 1;   /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and
5876                                                     *   COLOR2 depending on PATTERN and pattern index)                            */
5877                 __OM uint32_t TEXTUREENABLE : 1;   /*!< [1..1] Pixel source is read from texture and used as an alpha
5878                                                     *   to blend between COLOR1 and COLOR2                                        */
5879                 __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default
5880                                                     *   U limiter.Limiter 5 can be combined with limiter 6 to form
5881                                                     *   a quadratic limiter which can be used to make quadratic
5882                                                     *   pattern functions to draw radial patterns.                                */
5883                 __OM uint32_t USEACB       : 1;    /*!< [3..3] Alpha blend mode                                                   */
5884                 __OM uint32_t READFORMAT32 : 2;    /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT
5885                                                     *   above for description                                                     */
5886                 __OM uint32_t BSFA : 1;            /*!< [6..6] Blend source factor for alpha channel in alpha channel
5887                                                     *   blending mode (USEACB = 1)                                                */
5888                 __OM uint32_t BDFA : 1;            /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel
5889                                                     *   blending mode (USEACB = 1)                                                */
5890                 __OM uint32_t WRITEFORMAT2 : 1;    /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above
5891                                                     *   description.                                                              */
5892                 __OM uint32_t BSF : 1;             /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per
5893                                                     *   default)                                                                  */
5894                 __OM uint32_t BDF : 1;             /*!< [10..10] Blend destination factordst factor is alpha (factor
5895                                                     *   is 1 per default)                                                         */
5896                 __OM uint32_t BSI : 1;             /*!< [11..11] Blend source factor is invertedsrc factor will be inverted
5897                                                     *   (meaning 1-a or 1-1 depending on BSF)                                     */
5898                 __OM uint32_t BDI : 1;             /*!< [12..12] Blend destination factor is inverteddst factor will
5899                                                     *   be inverted (meaning 1-a or 1-1 depending on BDF)                         */
5900                 __OM uint32_t BC2           : 1;   /*!< [13..13] Blend color 2 instead of framebuffer pixel                       */
5901                 __OM uint32_t TEXTURECLAMPX : 1;   /*!< [14..14] Calculating U limiter outside use textureThe bit describes
5902                                                     *   what happens if the U limiter (x direction in texture space)
5903                                                     *   calculates a U value outside of the used texture                          */
5904                 __OM uint32_t TEXTURECLAMPY : 1;   /*!< [15..15] Calculating V limiter outside use textureThe bit describes
5905                                                     *   what happens if the V limiter (y direction in texture space)
5906                                                     *   calculates a V value outside of the used texture                          */
5907                 __OM uint32_t TEXTUREFILTERX : 1;  /*!< [16..16] Linear filtering on texture U axis                               */
5908                 __OM uint32_t TEXTUREFILTERY : 1;  /*!< [17..17] Linear filtering on texture V axis                               */
5909                 __OM uint32_t READFORMAT10   : 2;  /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000:
5910                                                     *   8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011:
5911                                                     *   16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44)
5912                                                     *   4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8),
5913                                                     *   8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4),
5914                                                     *   4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2),
5915                                                     *   2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1),
5916                                                     *   1 bit indexed color/luminance                                             */
5917                 __OM uint32_t WRITEFORMAT10 : 2;   /*!< [21..20] Pixel format of the framebuffer                                  */
5918                 __OM uint32_t WRITEALPHA    : 2;   /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha
5919                                                     *   source' for the framebuffer(USEACB = 0)Blend alpha in color
5920                                                     *   2 instead of framebuffer alpha((USEACB = 1))In not alpha
5921                                                     *   channel blending mode (USEACB = 0):Set the 'alpha source'
5922                                                     *   for the framebuffer.In alpha channel blending mode (USEACB
5923                                                     *   = 1):Blend alpha in color 2 instead of framebuffer alpha00B:
5924                                                     *   BC2A = 1: use alpha from framebuffer as destination (DST_A)else:
5925                                                     *   BC2A = 0: use alpha in color 2 as destination (DST_A)                     */
5926                 __OM uint32_t RLEENABLE    : 1;    /*!< [24..24] RLE enable                                                       */
5927                 __OM uint32_t CLUTENABLE   : 1;    /*!< [25..25] CLUT enable                                                      */
5928                 __OM uint32_t COLKEYENABLE : 1;    /*!< [26..26] color keying enable                                              */
5929                 __OM uint32_t CLUTFORMAT   : 1;    /*!< [27..27] Format of the CLUT                                               */
5930                 __OM uint32_t BSIA         : 1;    /*!< [28..28] Blend source factor inverted in alpha channel (USEACB
5931                                                     *   = 1)                                                                      */
5932                 __OM uint32_t BDIA : 1;            /*!< [29..29] Blend destination factor inverted in alpha channel
5933                                                     *   (USEACB = 1)                                                              */
5934                 __OM uint32_t RLEPIXELWIDTH : 2;   /*!< [31..30] Texel width for RLE unit                                         */
5935             } CONTROL2_b;
5936         };
5937 
5938         union
5939         {
5940             __IM uint32_t HWREVISION;          /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register               */
5941 
5942             struct
5943             {
5944                 __IM uint32_t REV        : 12; /*!< [11..0] Revision number                                                   */
5945                 uint32_t                 : 5;
5946                 __IM uint32_t DLR        : 1;  /*!< [17..17] Display list reader feature                                      */
5947                 __IM uint32_t FBCACHE    : 1;  /*!< [18..18] Framebuffer cache feature                                        */
5948                 __IM uint32_t TXCACHE    : 1;  /*!< [19..19] Texture cache feature                                            */
5949                 __IM uint32_t PERFCOUNT  : 1;  /*!< [20..20] Two performance counter feature                                  */
5950                 __IM uint32_t TEXCLU     : 1;  /*!< [21..21] Texture CLUT with 16 or 256 entries feature                      */
5951                 uint32_t                 : 1;
5952                 __IM uint32_t RLEUNIT    : 1;  /*!< [23..23] RLE unit feature                                                 */
5953                 __IM uint32_t TEXCLUT256 : 1;  /*!< [24..24] Texture CLUT feature                                             */
5954                 __IM uint32_t COLORKEY   : 1;  /*!< [25..25] Colorkey feature                                                 */
5955                 uint32_t                 : 1;
5956                 __IM uint32_t ACBLEND    : 1;  /*!< [27..27] Alpha channel blending feature                                   */
5957                 uint32_t                 : 4;
5958             } HWREVISION_b;
5959         };
5960     };
5961     __IM uint32_t RESERVED[2];
5962 
5963     union
5964     {
5965         __OM uint32_t L1START;         /*!< (@ 0x00000010) Limiter 1 Start Value Register                             */
5966 
5967         struct
5968         {
5969             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
5970         } L1START_b;
5971     };
5972 
5973     union
5974     {
5975         __OM uint32_t L2START;         /*!< (@ 0x00000014) Limiter 2 Start Value Register                             */
5976 
5977         struct
5978         {
5979             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
5980         } L2START_b;
5981     };
5982 
5983     union
5984     {
5985         __OM uint32_t L3START;         /*!< (@ 0x00000018) Limiter 3 Start Value Register                             */
5986 
5987         struct
5988         {
5989             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
5990         } L3START_b;
5991     };
5992 
5993     union
5994     {
5995         __OM uint32_t L4START;         /*!< (@ 0x0000001C) Limiter 4 Start Value Register                             */
5996 
5997         struct
5998         {
5999             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6000         } L4START_b;
6001     };
6002 
6003     union
6004     {
6005         __OM uint32_t L5START;         /*!< (@ 0x00000020) Limiter 5 Start Value Register                             */
6006 
6007         struct
6008         {
6009             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6010         } L5START_b;
6011     };
6012 
6013     union
6014     {
6015         __OM uint32_t L6START;         /*!< (@ 0x00000024) Limiter 6 Start Value Register                             */
6016 
6017         struct
6018         {
6019             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6020         } L6START_b;
6021     };
6022 
6023     union
6024     {
6025         __OM uint32_t L1XADD;          /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register                        */
6026 
6027         struct
6028         {
6029             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6030         } L1XADD_b;
6031     };
6032 
6033     union
6034     {
6035         __OM uint32_t L2XADD;          /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register                        */
6036 
6037         struct
6038         {
6039             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6040         } L2XADD_b;
6041     };
6042 
6043     union
6044     {
6045         __OM uint32_t L3XADD;          /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register                        */
6046 
6047         struct
6048         {
6049             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6050         } L3XADD_b;
6051     };
6052 
6053     union
6054     {
6055         __OM uint32_t L4XADD;          /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register                        */
6056 
6057         struct
6058         {
6059             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6060         } L4XADD_b;
6061     };
6062 
6063     union
6064     {
6065         __OM uint32_t L5XADD;          /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register                        */
6066 
6067         struct
6068         {
6069             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6070         } L5XADD_b;
6071     };
6072 
6073     union
6074     {
6075         __OM uint32_t L6XADD;          /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register                        */
6076 
6077         struct
6078         {
6079             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6080         } L6XADD_b;
6081     };
6082 
6083     union
6084     {
6085         __OM uint32_t L1YADD;          /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register                        */
6086 
6087         struct
6088         {
6089             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6090         } L1YADD_b;
6091     };
6092 
6093     union
6094     {
6095         __OM uint32_t L2YADD;          /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register                        */
6096 
6097         struct
6098         {
6099             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6100         } L2YADD_b;
6101     };
6102 
6103     union
6104     {
6105         __OM uint32_t L3YADD;          /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register                        */
6106 
6107         struct
6108         {
6109             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6110         } L3YADD_b;
6111     };
6112 
6113     union
6114     {
6115         __OM uint32_t L4YADD;          /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register                        */
6116 
6117         struct
6118         {
6119             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6120         } L4YADD_b;
6121     };
6122 
6123     union
6124     {
6125         __OM uint32_t L5YADD;          /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register                        */
6126 
6127         struct
6128         {
6129             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6130         } L5YADD_b;
6131     };
6132 
6133     union
6134     {
6135         __OM uint32_t L6YADD;          /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register                        */
6136 
6137         struct
6138         {
6139             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6140         } L6YADD_b;
6141     };
6142 
6143     union
6144     {
6145         __OM uint32_t L1BAND;          /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register                    */
6146 
6147         struct
6148         {
6149             __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
6150         } L1BAND_b;
6151     };
6152 
6153     union
6154     {
6155         __OM uint32_t L2BAND;          /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register                    */
6156 
6157         struct
6158         {
6159             __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
6160         } L2BAND_b;
6161     };
6162     __IM uint32_t RESERVED1;
6163 
6164     union
6165     {
6166         __OM uint32_t COLOR1;          /*!< (@ 0x00000064) Base Color Register                                        */
6167 
6168         struct
6169         {
6170             __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1                                            */
6171             __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1                                          */
6172             __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1                                           */
6173             __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF:
6174                                         *   opaque)                                                                   */
6175         } COLOR1_b;
6176     };
6177 
6178     union
6179     {
6180         __OM uint32_t COLOR2;          /*!< (@ 0x00000068) Secondary Color Register                                   */
6181 
6182         struct
6183         {
6184             __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2                                            */
6185             __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2                                          */
6186             __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2                                           */
6187             __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF:
6188                                         *   opaque)                                                                   */
6189         } COLOR2_b;
6190     };
6191     __IM uint32_t RESERVED2[2];
6192 
6193     union
6194     {
6195         __OM uint32_t PATTERN;         /*!< (@ 0x00000074) Pattern Register                                           */
6196 
6197         struct
6198         {
6199             __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern                                              */
6200             uint32_t              : 24;
6201         } PATTERN_b;
6202     };
6203 
6204     union
6205     {
6206         __OM uint32_t SIZE;            /*!< (@ 0x00000078) Bounding Box Dimension Register                            */
6207 
6208         struct
6209         {
6210             __OM uint32_t SIZEX : 16;  /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
6211                                         *   1024                                                                      */
6212             __OM uint32_t SIZEY : 16;  /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
6213                                         *   to 1024                                                                   */
6214         } SIZE_b;
6215     };
6216 
6217     union
6218     {
6219         __OM uint32_t PITCH;           /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register             */
6220 
6221         struct
6222         {
6223             __OM uint32_t PITCH : 16;  /*!< [15..0] pitch of the framebuffer. A negative width can be used
6224                                         *   to render bottom-up instead of top-down                                   */
6225             __OM uint32_t SSD : 16;    /*!< [31..16] Spanstore delay                                                  */
6226         } PITCH_b;
6227     };
6228 
6229     union
6230     {
6231         __OM uint32_t ORIGIN;          /*!< (@ 0x00000080) Framebuffer Base Address Register                          */
6232 
6233         struct
6234         {
6235             __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer                         */
6236         } ORIGIN_b;
6237     };
6238     __IM uint32_t RESERVED3[3];
6239 
6240     union
6241     {
6242         __OM uint32_t LUSTART;          /*!< (@ 0x00000090) U Limiter Start Value Register                             */
6243 
6244         struct
6245         {
6246             __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value                                             */
6247         } LUSTART_b;
6248     };
6249 
6250     union
6251     {
6252         __OM uint32_t LUXADD;          /*!< (@ 0x00000094) U Limiter X-Axis Increment Register                        */
6253 
6254         struct
6255         {
6256             __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment                                        */
6257         } LUXADD_b;
6258     };
6259 
6260     union
6261     {
6262         __OM uint32_t LUYADD;          /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register                        */
6263 
6264         struct
6265         {
6266             __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment                                        */
6267         } LUYADD_b;
6268     };
6269 
6270     union
6271     {
6272         __OM uint32_t LVSTARTI;          /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register                */
6273 
6274         struct
6275         {
6276             __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part                                */
6277         } LVSTARTI_b;
6278     };
6279 
6280     union
6281     {
6282         __OM uint32_t LVSTARTF;          /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register             */
6283 
6284         struct
6285         {
6286             __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part                             */
6287             uint32_t               : 16;
6288         } LVSTARTF_b;
6289     };
6290 
6291     union
6292     {
6293         __OM uint32_t LVXADDI;          /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register           */
6294 
6295         struct
6296         {
6297             __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part                           */
6298         } LVXADDI_b;
6299     };
6300 
6301     union
6302     {
6303         __OM uint32_t LVYADDI;          /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register           */
6304 
6305         struct
6306         {
6307             __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part                           */
6308         } LVYADDI_b;
6309     };
6310 
6311     union
6312     {
6313         __OM uint32_t LVYXADDF;         /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register              */
6314 
6315         struct
6316         {
6317             __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part                              */
6318             __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part                            */
6319         } LVYXADDF_b;
6320     };
6321     __IM uint32_t RESERVED4;
6322 
6323     union
6324     {
6325         __OM uint32_t TEXPITCH;          /*!< (@ 0x000000B4) Texels Per Texture Line Register                           */
6326 
6327         struct
6328         {
6329             __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048                     */
6330         } TEXPITCH_b;
6331     };
6332 
6333     union
6334     {
6335         __OM uint32_t TEXMASK;           /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register              */
6336 
6337         struct
6338         {
6339             __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture
6340                                           *   wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width
6341                                           *   must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX
6342                                           *   = 1):all widths up to 2048 are allowed.                                   */
6343             __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height
6344                                           *   - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY =
6345                                           *   0): texture_height must be a power of 2In texture clamping
6346                                           *   mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024
6347                                           *   are allowed.                                                              */
6348         } TEXMASK_b;
6349     };
6350 
6351     union
6352     {
6353         __OM uint32_t TEXORIGIN;          /*!< (@ 0x000000BC) Texture Base Address Register                              */
6354 
6355         struct
6356         {
6357             __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address                                              */
6358         } TEXORIGIN_b;
6359     };
6360 
6361     union
6362     {
6363         __OM uint32_t IRQCTL;              /*!< (@ 0x000000C0) Interrupt Control Register                                 */
6364 
6365         struct
6366         {
6367             __OM uint32_t ENUMIRQEN   : 1; /*!< [0..0] ENUMIRQ interrupt mask enable                                      */
6368             __OM uint32_t DLISTIRQEN  : 1; /*!< [1..1] DLISTIRQ interrupt mask enable                                     */
6369             __OM uint32_t ENUMIRQCLR  : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ                                */
6370             __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ                              */
6371             __OM uint32_t BUSIRQEN    : 1; /*!< [4..4] BUSIRQ interrupt mask enable                                       */
6372             __OM uint32_t BUSIRQCLR   : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ                                   */
6373             uint32_t                  : 26;
6374         } IRQCTL_b;
6375     };
6376 
6377     union
6378     {
6379         __OM uint32_t CACHECTL;          /*!< (@ 0x000000C4) Cache Control Register                                     */
6380 
6381         struct
6382         {
6383             __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable                                           */
6384             __OM uint32_t CFLUSHFX  : 1; /*!< [1..1] Flush framebuffer cache                                            */
6385             __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable                                               */
6386             __OM uint32_t CFLUSHTX  : 1; /*!< [3..3] Flush texture cache                                                */
6387             uint32_t                : 28;
6388         } CACHECTL_b;
6389     };
6390 
6391     union
6392     {
6393         __OM uint32_t DLISTSTART;          /*!< (@ 0x000000C8) Display List Start Address Register                        */
6394 
6395         struct
6396         {
6397             __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address                                        */
6398         } DLISTSTART_b;
6399     };
6400 
6401     union
6402     {
6403         __IOM uint32_t PERFCOUNT1;         /*!< (@ 0x000000CC) Performance Counter 1                                      */
6404 
6405         struct
6406         {
6407             __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
6408                                             *   = 0000 0000H.                                                             */
6409         } PERFCOUNT1_b;
6410     };
6411 
6412     union
6413     {
6414         __IOM uint32_t PERFCOUNT2;         /*!< (@ 0x000000D0) Performance Counter 2                                      */
6415 
6416         struct
6417         {
6418             __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
6419                                             *   = 0000 0000H.                                                             */
6420         } PERFCOUNT2_b;
6421     };
6422 
6423     union
6424     {
6425         __OM uint32_t PERFTRIGGER;           /*!< (@ 0x000000D4) Performance Counters Control Register                      */
6426 
6427         struct
6428         {
6429             __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1
6430                                               *   register.                                                                 */
6431             __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2
6432                                               *   register                                                                  */
6433         } PERFTRIGGER_b;
6434     };
6435     __IM uint32_t RESERVED5;
6436 
6437     union
6438     {
6439         __OM uint32_t TEXCLADDR;       /*!< (@ 0x000000DC) CLUT Start Address Register                                */
6440 
6441         struct
6442         {
6443             __OM uint32_t CLADDR : 8;  /*!< [7..0] Texture CLUT start address for indexed texture format              */
6444             uint32_t             : 24;
6445         } TEXCLADDR_b;
6446     };
6447 
6448     union
6449     {
6450         __OM uint32_t TEXCLDATA;       /*!< (@ 0x000000E0) CLUT Data Register                                         */
6451 
6452         struct
6453         {
6454             __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format                      */
6455         } TEXCLDATA_b;
6456     };
6457 
6458     union
6459     {
6460         __OM uint32_t TEXCLOFFSET;      /*!< (@ 0x000000E4) CLUT Offset Register                                       */
6461 
6462         struct
6463         {
6464             __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0]
6465                                          *   is or'ed with the original index                                          */
6466             uint32_t : 24;
6467         } TEXCLOFFSET_b;
6468     };
6469 
6470     union
6471     {
6472         __OM uint32_t COLKEY;          /*!< (@ 0x000000E8) Color Key Register                                         */
6473 
6474         struct
6475         {
6476             __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key                                          */
6477             __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key                                        */
6478             __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key                                         */
6479             uint32_t              : 8;
6480         } COLKEY_b;
6481     };
6482 } R_DRW_Type;                          /*!< Size = 236 (0xec)                                                         */
6483 
6484 /* =========================================================================================================================== */
6485 /* ================                                           R_DTC                                           ================ */
6486 /* =========================================================================================================================== */
6487 
6488 /**
6489  * @brief Data Transfer Controller (R_DTC)
6490  */
6491 
6492 typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
6493 {
6494     union
6495     {
6496         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
6497 
6498         struct
6499         {
6500             uint8_t           : 4;
6501             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
6502             uint8_t           : 3;
6503         } DTCCR_b;
6504     };
6505     __IM uint8_t  RESERVED;
6506     __IM uint16_t RESERVED1;
6507 
6508     union
6509     {
6510         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
6511 
6512         struct
6513         {
6514             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
6515                                          *   in the lower-order 10 bits. These bits are fixed to 0.                    */
6516         } DTCVBR_b;
6517     };
6518     __IM uint32_t RESERVED2;
6519 
6520     union
6521     {
6522         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
6523 
6524         struct
6525         {
6526             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
6527             uint8_t             : 7;
6528         } DTCST_b;
6529     };
6530     __IM uint8_t RESERVED3;
6531 
6532     union
6533     {
6534         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
6535 
6536         struct
6537         {
6538             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
6539                                         *   the vector number for the activating source when DTC transfer
6540                                         *   is in progress.The value is only valid if DTC transfer
6541                                         *   is in progress (the value of the ACT flag is 1)                           */
6542             uint16_t          : 7;
6543             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
6544         } DTCSTS_b;
6545     };
6546 
6547     union
6548     {
6549         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
6550 
6551         struct
6552         {
6553             uint8_t            : 4;
6554             __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
6555             uint8_t            : 3;
6556         } DTCCR_SEC_b;
6557     };
6558     __IM uint8_t   RESERVED4;
6559     __IM uint16_t  RESERVED5;
6560     __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
6561     __IM uint32_t  RESERVED6[2];
6562 
6563     union
6564     {
6565         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
6566 
6567         struct
6568         {
6569             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
6570             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
6571             uint32_t              : 7;
6572             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
6573             uint32_t              : 15;
6574         } DTEVR_b;
6575     };
6576 } R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
6577 
6578 /* =========================================================================================================================== */
6579 /* ================                                           R_ELC                                           ================ */
6580 /* =========================================================================================================================== */
6581 
6582 /**
6583  * @brief Event Link Controller (R_ELC)
6584  */
6585 
6586 typedef struct                         /*!< (@ 0x40041000) R_ELC Structure                                            */
6587 {
6588     union
6589     {
6590         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
6591 
6592         struct
6593         {
6594             uint8_t             : 7;
6595             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
6596         } ELCR_b;
6597     };
6598     __IM uint8_t            RESERVED;
6599     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
6600     __IM uint16_t           RESERVED1[5];
6601     __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
6602     __IM uint16_t           RESERVED2[4];
6603 
6604     union
6605     {
6606         __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
6607                                          *                  A                                                          */
6608 
6609         struct
6610         {
6611             __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
6612             __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
6613                                          *   Attribution                                                               */
6614             __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
6615                                          *   Attribution                                                               */
6616             uint16_t : 13;
6617         } ELCSARA_b;
6618     };
6619     __IM uint16_t RESERVED3;
6620 
6621     union
6622     {
6623         __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
6624                                         *                  B                                                          */
6625 
6626         struct
6627         {
6628             __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
6629             __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
6630             __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
6631             __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
6632             __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
6633             __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
6634             __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
6635             __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
6636             __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
6637             __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
6638             __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
6639             __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
6640             __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
6641             __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
6642             __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
6643             __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
6644         } ELCSARB_b;
6645     };
6646     __IM uint16_t RESERVED4;
6647 
6648     union
6649     {
6650         __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
6651                                         *                  C                                                          */
6652 
6653         struct
6654         {
6655             __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
6656             __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
6657             __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
6658             uint16_t              : 13;
6659         } ELCSARC_b;
6660     };
6661 } R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
6662 
6663 /* =========================================================================================================================== */
6664 /* ================                                         R_ETHERC0                                         ================ */
6665 /* =========================================================================================================================== */
6666 
6667 /**
6668  * @brief Ethernet MAC Controller (R_ETHERC0)
6669  */
6670 
6671 typedef struct                         /*!< (@ 0x40064100) R_ETHERC0 Structure                                        */
6672 {
6673     union
6674     {
6675         __IOM uint32_t ECMR;           /*!< (@ 0x00000000) ETHERC Mode Register                                       */
6676 
6677         struct
6678         {
6679             __IOM uint32_t PRM   : 1;  /*!< [0..0] Promiscuous Mode                                                   */
6680             __IOM uint32_t DM    : 1;  /*!< [1..1] Duplex Mode                                                        */
6681             __IOM uint32_t RTM   : 1;  /*!< [2..2] Bit Rate                                                           */
6682             __IOM uint32_t ILB   : 1;  /*!< [3..3] Internal Loopback Mode                                             */
6683             uint32_t             : 1;
6684             __IOM uint32_t TE    : 1;  /*!< [5..5] Transmission Enable                                                */
6685             __IOM uint32_t RE    : 1;  /*!< [6..6] Reception Enable                                                   */
6686             uint32_t             : 2;
6687             __IOM uint32_t MPDE  : 1;  /*!< [9..9] Magic Packet Detection Enable                                      */
6688             uint32_t             : 2;
6689             __IOM uint32_t PRCEF : 1;  /*!< [12..12] CRC Error Frame Receive Mode                                     */
6690             uint32_t             : 3;
6691             __IOM uint32_t TXF   : 1;  /*!< [16..16] Transmit Flow Control Operating Mode                             */
6692             __IOM uint32_t RXF   : 1;  /*!< [17..17] Receive Flow Control Operating Mode                              */
6693             __IOM uint32_t PFR   : 1;  /*!< [18..18] PAUSE Frame Receive Mode                                         */
6694             __IOM uint32_t ZPF   : 1;  /*!< [19..19] 0 Time PAUSE Frame Enable                                        */
6695             __IOM uint32_t TPC   : 1;  /*!< [20..20] PAUSE Frame Transmit                                             */
6696             uint32_t             : 11;
6697         } ECMR_b;
6698     };
6699     __IM uint32_t RESERVED;
6700 
6701     union
6702     {
6703         __IOM uint32_t RFLR;           /*!< (@ 0x00000008) Receive Frame Maximum Length Register                      */
6704 
6705         struct
6706         {
6707             __IOM uint32_t RFL : 12;   /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
6708                                         *   maximum frame length. The minimum value that can be set
6709                                         *   is 1,518 bytes, and the maximum value that can be set is
6710                                         *   2,048 bytes. Values that are less than 1,518 bytes are
6711                                         *   regarded as 1,518 bytes, and values larger than 2,048 bytes
6712                                         *   are regarded as 2,048 bytes.                                              */
6713             uint32_t : 20;
6714         } RFLR_b;
6715     };
6716     __IM uint32_t RESERVED1;
6717 
6718     union
6719     {
6720         __IOM uint32_t ECSR;           /*!< (@ 0x00000010) ETHERC Status Register                                     */
6721 
6722         struct
6723         {
6724             __IOM uint32_t ICD   : 1;  /*!< [0..0] False Carrier Detect Flag                                          */
6725             __IOM uint32_t MPD   : 1;  /*!< [1..1] Magic Packet Detect Flag                                           */
6726             __IOM uint32_t LCHNG : 1;  /*!< [2..2] LCHNG Link Signal Change Flag                                      */
6727             uint32_t             : 1;
6728             __IOM uint32_t PSRTO : 1;  /*!< [4..4] PAUSE Frame Retransmit Over Flag                                   */
6729             __IOM uint32_t BFR   : 1;  /*!< [5..5] Continuous Broadcast Frame Reception Flag                          */
6730             uint32_t             : 26;
6731         } ECSR_b;
6732     };
6733     __IM uint32_t RESERVED2;
6734 
6735     union
6736     {
6737         __IOM uint32_t ECSIPR;          /*!< (@ 0x00000018) ETHERC Interrupt Enable Register                           */
6738 
6739         struct
6740         {
6741             __IOM uint32_t ICDIP   : 1; /*!< [0..0] False Carrier Detect Interrupt Enable                              */
6742             __IOM uint32_t MPDIP   : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable                               */
6743             __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable                                */
6744             uint32_t               : 1;
6745             __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable                       */
6746             __IOM uint32_t BFSIPR  : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable              */
6747             uint32_t               : 26;
6748         } ECSIPR_b;
6749     };
6750     __IM uint32_t RESERVED3;
6751 
6752     union
6753     {
6754         __IOM uint32_t PIR;            /*!< (@ 0x00000020) PHY Interface Register                                     */
6755 
6756         struct
6757         {
6758             __IOM uint32_t MDC : 1;    /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
6759                                         *   from the ETn_MDC pin to supply the management data clock
6760                                         *   to the MII or RMII.                                                       */
6761             __IOM uint32_t MMD : 1;    /*!< [1..1] MII/RMII Management Mode                                           */
6762             __IOM uint32_t MDO : 1;    /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
6763                                         *   from the ETn_MDIO pin when the MMD bit is 1 (write). The
6764                                         *   value is not output when the MMD bit is 0 (read).                         */
6765             __IM uint32_t MDI : 1;     /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
6766                                         *   of the ETn_MDIO pin. The write value should be 0.                         */
6767             uint32_t : 28;
6768         } PIR_b;
6769     };
6770     __IM uint32_t RESERVED4;
6771 
6772     union
6773     {
6774         __IM uint32_t PSR;             /*!< (@ 0x00000028) PHY Status Register                                        */
6775 
6776         struct
6777         {
6778             __IM uint32_t LMON : 1;    /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
6779                                         *   by connecting the link signal output from the PHY-LSI to
6780                                         *   the ETn_LINKSTA pin. For details on the polarity, refer
6781                                         *   to the specifications of the connected PHY-LSI.                           */
6782             uint32_t : 31;
6783         } PSR_b;
6784     };
6785     __IM uint32_t RESERVED5[5];
6786 
6787     union
6788     {
6789         __IOM uint32_t RDMLR;          /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
6790                                         *                  Setting Register                                           */
6791 
6792         struct
6793         {
6794             __IOM uint32_t RMD : 20;   /*!< [19..0] Random Number Generation Counter                                  */
6795             uint32_t           : 12;
6796         } RDMLR_b;
6797     };
6798     __IM uint32_t RESERVED6[3];
6799 
6800     union
6801     {
6802         __IOM uint32_t IPGR;           /*!< (@ 0x00000050) IPG Register                                               */
6803 
6804         struct
6805         {
6806             __IOM uint32_t IPG : 5;    /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)'       */
6807             uint32_t           : 27;
6808         } IPGR_b;
6809     };
6810 
6811     union
6812     {
6813         __IOM uint32_t APR;            /*!< (@ 0x00000054) Automatic PAUSE Frame Register                             */
6814 
6815         struct
6816         {
6817             __IOM uint32_t AP : 16;    /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
6818                                         *   of the pause_time parameter for a PAUSE frame that is automatically
6819                                         *   transmitted. Transmission is not performed until the set
6820                                         *   value multiplied by 512 bit time has elapsed.                             */
6821             uint32_t : 16;
6822         } APR_b;
6823     };
6824 
6825     union
6826     {
6827         __OM uint32_t MPR;             /*!< (@ 0x00000058) Manual PAUSE Frame Register                                */
6828 
6829         struct
6830         {
6831             __OM uint32_t MP : 16;     /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
6832                                         *   the pause_time parameter for a PAUSE frame that is manually
6833                                         *   transmitted. Transmission is not performed until the set
6834                                         *   value multiplied by 512 bit time has elapsed. The read
6835                                         *   value is undefined.                                                       */
6836             uint32_t : 16;
6837         } MPR_b;
6838     };
6839     __IM uint32_t RESERVED7;
6840 
6841     union
6842     {
6843         __IM uint32_t RFCF;            /*!< (@ 0x00000060) Received PAUSE Frame Counter                               */
6844 
6845         struct
6846         {
6847             __IM uint32_t RPAUSE : 8;  /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames          */
6848             uint32_t             : 24;
6849         } RFCF_b;
6850     };
6851 
6852     union
6853     {
6854         __IOM uint32_t TPAUSER;         /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register              */
6855 
6856         struct
6857         {
6858             __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting                          */
6859             uint32_t              : 16;
6860         } TPAUSER_b;
6861     };
6862     __IM uint32_t TPAUSECR;             /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter                             */
6863 
6864     union
6865     {
6866         __IOM uint32_t BCFRR;           /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register             */
6867 
6868         struct
6869         {
6870             __IOM uint32_t BCF : 16;    /*!< [15..0] Broadcast Frame Continuous Receive Count Setting                  */
6871             uint32_t           : 16;
6872         } BCFRR_b;
6873     };
6874     __IM uint32_t RESERVED8[20];
6875 
6876     union
6877     {
6878         __IOM uint32_t MAHR;           /*!< (@ 0x000000C0) MAC Address Upper Bit Register                             */
6879 
6880         struct
6881         {
6882             __IOM uint32_t MAHR : 32;  /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
6883                                         *   the upper 32 bits (b47 to b16) of the 48-bit MAC address.                 */
6884         } MAHR_b;
6885     };
6886     __IM uint32_t RESERVED9;
6887 
6888     union
6889     {
6890         __IOM uint32_t MALR;           /*!< (@ 0x000000C8) MAC Address Lower Bit Register                             */
6891 
6892         struct
6893         {
6894             __IOM uint32_t MALR : 16;  /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
6895                                         *   the lower 16 bits of the 48-bit MAC address.                              */
6896             uint32_t : 16;
6897         } MALR_b;
6898     };
6899     __IM uint32_t RESERVED10;
6900 
6901     union
6902     {
6903         __IOM uint32_t TROCR;          /*!< (@ 0x000000D0) Transmit Retry Over Counter Register                       */
6904 
6905         struct
6906         {
6907             __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
6908                                         *   is a counter indicating the number of frames that fail
6909                                         *   to be retransmitted.                                                      */
6910         } TROCR_b;
6911     };
6912     __IOM uint32_t CDCR;               /*!< (@ 0x000000D4) Late Collision Detect Counter Register                     */
6913 
6914     union
6915     {
6916         __IOM uint32_t LCCR;           /*!< (@ 0x000000D8) Lost Carrier Counter Register                              */
6917 
6918         struct
6919         {
6920             __IOM uint32_t LCCR : 32;  /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
6921                                         *   counter indicating the number of times a loss of carrier
6922                                         *   is detected during frame transmission.                                    */
6923         } LCCR_b;
6924     };
6925 
6926     union
6927     {
6928         __IOM uint32_t CNDCR;          /*!< (@ 0x000000DC) Carrier Not Detect Counter Register                        */
6929 
6930         struct
6931         {
6932             __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
6933                                         *   is a counter indicating the number of times a carrier is
6934                                         *   not detected during preamble transmission.                                */
6935         } CNDCR_b;
6936     };
6937     __IM uint32_t RESERVED11;
6938 
6939     union
6940     {
6941         __IOM uint32_t CEFCR;          /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register                   */
6942 
6943         struct
6944         {
6945             __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
6946                                         *   is a counter indicating the number of received frames where
6947                                         *   a CRC error has been detected.                                            */
6948         } CEFCR_b;
6949     };
6950 
6951     union
6952     {
6953         __IOM uint32_t FRECR;          /*!< (@ 0x000000E8) Frame Receive Error Counter Register                       */
6954 
6955         struct
6956         {
6957             __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
6958                                         *   is a counter indicating the number of times a frame receive
6959                                         *   error has occurred.                                                       */
6960         } FRECR_b;
6961     };
6962 
6963     union
6964     {
6965         __IOM uint32_t TSFRCR;          /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register                   */
6966 
6967         struct
6968         {
6969             __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
6970                                          *   is a counter indicating the number of times a short frame
6971                                          *   that is shorter than 64 bytes has been received.                          */
6972         } TSFRCR_b;
6973     };
6974 
6975     union
6976     {
6977         __IOM uint32_t TLFRCR;          /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register                    */
6978 
6979         struct
6980         {
6981             __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
6982                                          *   is a counter indicating the number of times a long frame
6983                                          *   that is longer than the RFLR register value has been received.            */
6984         } TLFRCR_b;
6985     };
6986 
6987     union
6988     {
6989         __IOM uint32_t RFCR;           /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register            */
6990 
6991         struct
6992         {
6993             __IOM uint32_t RFCR : 32;  /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
6994                                         *   register is a counter indicating the number of times a
6995                                         *   frame has been received with the alignment error (frame
6996                                         *   is not an integral number of octets).                                     */
6997         } RFCR_b;
6998     };
6999 
7000     union
7001     {
7002         __IOM uint32_t MAFCR;          /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register           */
7003 
7004         struct
7005         {
7006             __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
7007                                         *   MAFCR register is a counter indicating the number of times
7008                                         *   a frame where the multicast address is set has been received.             */
7009         } MAFCR_b;
7010     };
7011 } R_ETHERC0_Type;                      /*!< Size = 252 (0xfc)                                                         */
7012 
7013 /* =========================================================================================================================== */
7014 /* ================                                      R_ETHERC_EDMAC                                       ================ */
7015 /* =========================================================================================================================== */
7016 
7017 /**
7018  * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
7019  */
7020 
7021 typedef struct                         /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure                                   */
7022 {
7023     union
7024     {
7025         __IOM uint32_t EDMR;           /*!< (@ 0x00000000) EDMAC Mode Register                                        */
7026 
7027         struct
7028         {
7029             __OM uint32_t SWR : 1;     /*!< [0..0] Software Reset                                                     */
7030             uint32_t          : 3;
7031             __IOM uint32_t DL : 2;     /*!< [5..4] Transmit/Receive DescriptorLength                                  */
7032             __IOM uint32_t DE : 1;     /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
7033                                         *   applies to data for the transmit/receive buffer. It does
7034                                         *   not apply to transmit/receive descriptors and registers.                  */
7035             uint32_t : 25;
7036         } EDMR_b;
7037     };
7038     __IM uint32_t RESERVED;
7039 
7040     union
7041     {
7042         __IOM uint32_t EDTRR;          /*!< (@ 0x00000008) EDMAC Transmit Request Register                            */
7043 
7044         struct
7045         {
7046             __OM uint32_t TR : 1;      /*!< [0..0] Transmit Request                                                   */
7047             uint32_t         : 31;
7048         } EDTRR_b;
7049     };
7050     __IM uint32_t RESERVED1;
7051 
7052     union
7053     {
7054         __IOM uint32_t EDRRR;          /*!< (@ 0x00000010) EDMAC Receive Request Register                             */
7055 
7056         struct
7057         {
7058             __IOM uint32_t RR : 1;     /*!< [0..0] Receive Request                                                    */
7059             uint32_t          : 31;
7060         } EDRRR_b;
7061     };
7062     __IM uint32_t RESERVED2;
7063 
7064     union
7065     {
7066         __IOM uint32_t TDLAR;          /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register            */
7067 
7068         struct
7069         {
7070             __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
7071                                         *   set. Set the start address according to the descriptor
7072                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
7073                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
7074                                         *   boundary: Lower 6 bits = 000000b                                          */
7075         } TDLAR_b;
7076     };
7077     __IM uint32_t RESERVED3;
7078 
7079     union
7080     {
7081         __IOM uint32_t RDLAR;          /*!< (@ 0x00000020) Receive Descriptor List Start Address Register             */
7082 
7083         struct
7084         {
7085             __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
7086                                         *   set. Set the start address according to the descriptor
7087                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
7088                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
7089                                         *   boundary: Lower 6 bits = 000000b                                          */
7090         } RDLAR_b;
7091     };
7092     __IM uint32_t RESERVED4;
7093 
7094     union
7095     {
7096         __IOM uint32_t EESR;           /*!< (@ 0x00000028) ETHERC/EDMAC Status Register                               */
7097 
7098         struct
7099         {
7100             __IOM uint32_t CERF : 1;   /*!< [0..0] CRC Error Flag                                                     */
7101             __IOM uint32_t PRE  : 1;   /*!< [1..1] PHY-LSI Receive Error Flag                                         */
7102             __IOM uint32_t RTSF : 1;   /*!< [2..2] Frame-Too-Short Error Flag                                         */
7103             __IOM uint32_t RTLF : 1;   /*!< [3..3] Frame-Too-Long Error Flag                                          */
7104             __IOM uint32_t RRF  : 1;   /*!< [4..4] Alignment Error Flag                                               */
7105             uint32_t            : 2;
7106             __IOM uint32_t RMAF : 1;   /*!< [7..7] Multicast Address Frame Receive Flag                               */
7107             __IOM uint32_t TRO  : 1;   /*!< [8..8] Transmit Retry Over Flag                                           */
7108             __IOM uint32_t CD   : 1;   /*!< [9..9] Late Collision Detect Flag                                         */
7109             __IOM uint32_t DLC  : 1;   /*!< [10..10] Loss of Carrier Detect Flag                                      */
7110             __IOM uint32_t CND  : 1;   /*!< [11..11] Carrier Not Detect Flag                                          */
7111             uint32_t            : 4;
7112             __IOM uint32_t RFOF : 1;   /*!< [16..16] Receive FIFO Overflow Flag                                       */
7113             __IOM uint32_t RDE  : 1;   /*!< [17..17] Receive Descriptor Empty Flag                                    */
7114             __IOM uint32_t FR   : 1;   /*!< [18..18] Frame Receive Flag                                               */
7115             __IOM uint32_t TFUF : 1;   /*!< [19..19] Transmit FIFO Underflow Flag                                     */
7116             __IOM uint32_t TDE  : 1;   /*!< [20..20] Transmit Descriptor Empty Flag                                   */
7117             __IOM uint32_t TC   : 1;   /*!< [21..21] Frame Transfer Complete Flag                                     */
7118             __IM uint32_t  ECI  : 1;   /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
7119                                         *   in the ETHERCn.ECSR register is cleared, the ECI flag is
7120                                         *   also cleared.                                                             */
7121             __IOM uint32_t ADE   : 1;  /*!< [23..23] Address Error Flag                                               */
7122             __IOM uint32_t RFCOF : 1;  /*!< [24..24] Receive Frame Counter Overflow Flag                              */
7123             __IOM uint32_t RABT  : 1;  /*!< [25..25] Receive Abort Detect Flag                                        */
7124             __IOM uint32_t TABT  : 1;  /*!< [26..26] Transmit Abort Detect Flag                                       */
7125             uint32_t             : 3;
7126             __IOM uint32_t TWB   : 1;  /*!< [30..30] Write-Back Complete Flag                                         */
7127             uint32_t             : 1;
7128         } EESR_b;
7129     };
7130     __IM uint32_t RESERVED5;
7131 
7132     union
7133     {
7134         __IOM uint32_t EESIPR;          /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register              */
7135 
7136         struct
7137         {
7138             __IOM uint32_t CERFIP  : 1; /*!< [0..0] CRC Error Interrupt Request Enable                                 */
7139             __IOM uint32_t PREIP   : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable                     */
7140             __IOM uint32_t RTSFIP  : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable                     */
7141             __IOM uint32_t RTLFIP  : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable                      */
7142             __IOM uint32_t RRFIP   : 1; /*!< [4..4] Alignment Error Interrupt Request Enable                           */
7143             uint32_t               : 2;
7144             __IOM uint32_t RMAFIP  : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable           */
7145             __IOM uint32_t TROIP   : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable                       */
7146             __IOM uint32_t CDIP    : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable                     */
7147             __IOM uint32_t DLCIP   : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable                  */
7148             __IOM uint32_t CNDIP   : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable                      */
7149             uint32_t               : 4;
7150             __IOM uint32_t RFOFIP  : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable                   */
7151             __IOM uint32_t RDEIP   : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable                */
7152             __IOM uint32_t FRIP    : 1; /*!< [18..18] Frame Receive Interrupt Request Enable                           */
7153             __IOM uint32_t TFUFIP  : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable                 */
7154             __IOM uint32_t TDEIP   : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable               */
7155             __IOM uint32_t TCIP    : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable                 */
7156             __IOM uint32_t ECIIP   : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable           */
7157             __IOM uint32_t ADEIP   : 1; /*!< [23..23] Address Error Interrupt Request Enable                           */
7158             __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable          */
7159             __IOM uint32_t RABTIP  : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable                    */
7160             __IOM uint32_t TABTIP  : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable                   */
7161             uint32_t               : 3;
7162             __IOM uint32_t TWBIP   : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable                     */
7163             uint32_t               : 1;
7164         } EESIPR_b;
7165     };
7166     __IM uint32_t RESERVED6;
7167 
7168     union
7169     {
7170         __IOM uint32_t TRSCER;         /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
7171                                         *                  Register                                                   */
7172 
7173         struct
7174         {
7175             uint32_t              : 4;
7176             __IOM uint32_t RRFCE  : 1; /*!< [4..4] RRF Flag Copy Enable                                               */
7177             uint32_t              : 2;
7178             __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable                                              */
7179             uint32_t              : 24;
7180         } TRSCER_b;
7181     };
7182     __IM uint32_t RESERVED7;
7183 
7184     union
7185     {
7186         __IOM uint32_t RMFCR;          /*!< (@ 0x00000040) Missed-Frame Counter Register                              */
7187 
7188         struct
7189         {
7190             __IOM uint32_t MFC : 16;   /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
7191                                         *   frames that are discarded and not transferred to the receive
7192                                         *   buffer during reception.                                                  */
7193             uint32_t : 16;
7194         } RMFCR_b;
7195     };
7196     __IM uint32_t RESERVED8;
7197 
7198     union
7199     {
7200         __IOM uint32_t TFTR;           /*!< (@ 0x00000048) Transmit FIFO Threshold Register                           */
7201 
7202         struct
7203         {
7204             __IOM uint32_t TFT : 11;   /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
7205                                         *   the set value multiplied by 4. Example: 00Dh: 52 bytes
7206                                         *   040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes                         */
7207             uint32_t : 21;
7208         } TFTR_b;
7209     };
7210     __IM uint32_t RESERVED9;
7211 
7212     union
7213     {
7214         __IOM uint32_t FDR;            /*!< (@ 0x00000050) Transmit FIFO Threshold Register                           */
7215 
7216         struct
7217         {
7218             __IOM uint32_t RFD : 5;    /*!< [4..0] Transmit FIFO Depth                                                */
7219             uint32_t           : 3;
7220             __IOM uint32_t TFD : 5;    /*!< [12..8] Receive FIFO Depth                                                */
7221             uint32_t           : 19;
7222         } FDR_b;
7223     };
7224     __IM uint32_t RESERVED10;
7225 
7226     union
7227     {
7228         __IOM uint32_t RMCR;           /*!< (@ 0x00000058) Receive Method Control Register                            */
7229 
7230         struct
7231         {
7232             __IOM uint32_t RNR : 1;    /*!< [0..0] Receive Request Reset                                              */
7233             uint32_t           : 31;
7234         } RMCR_b;
7235     };
7236     __IM uint32_t RESERVED11[2];
7237 
7238     union
7239     {
7240         __IOM uint32_t TFUCR;          /*!< (@ 0x00000064) Transmit FIFO Underflow Counter                            */
7241 
7242         struct
7243         {
7244             __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
7245                                         *   many times the transmit FIFO has underflowed. The counter
7246                                         *   stops when the counter value reaches FFFFh.                               */
7247             uint32_t : 16;
7248         } TFUCR_b;
7249     };
7250 
7251     union
7252     {
7253         __IOM uint32_t RFOCR;          /*!< (@ 0x00000068) Receive FIFO Overflow Counter                              */
7254 
7255         struct
7256         {
7257             __IOM uint32_t OVER : 16;  /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
7258                                         *   times the receive FIFO has overflowed. The counter stops
7259                                         *   when the counter value reaches FFFFh.                                     */
7260             uint32_t : 16;
7261         } RFOCR_b;
7262     };
7263 
7264     union
7265     {
7266         __IOM uint32_t IOSR;           /*!< (@ 0x0000006C) Independent Output Signal Setting Register                 */
7267 
7268         struct
7269         {
7270             __IOM uint32_t ELB : 1;    /*!< [0..0] External Loopback Mode                                             */
7271             uint32_t           : 31;
7272         } IOSR_b;
7273     };
7274 
7275     union
7276     {
7277         __IOM uint32_t FCFTR;          /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register         */
7278 
7279         struct
7280         {
7281             __IOM uint32_t RFDO : 3;   /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
7282                                         *   bytes of data is stored in the receive FIFO.)                             */
7283             uint32_t            : 13;
7284             __IOM uint32_t RFFO : 3;   /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
7285                                         *   receive frames have been stored in the receive FIFO.)                     */
7286             uint32_t : 13;
7287         } FCFTR_b;
7288     };
7289     __IM uint32_t RESERVED12;
7290 
7291     union
7292     {
7293         __IOM uint32_t RPADIR;         /*!< (@ 0x00000078) Receive Data Padding Insert Register                       */
7294 
7295         struct
7296         {
7297             __IOM uint32_t PADR : 6;   /*!< [5..0] Padding Slot                                                       */
7298             uint32_t            : 10;
7299             __IOM uint32_t PADS : 2;   /*!< [17..16] Padding Size                                                     */
7300             uint32_t            : 14;
7301         } RPADIR_b;
7302     };
7303 
7304     union
7305     {
7306         __IOM uint32_t TRIMD;          /*!< (@ 0x0000007C) Transmit Interrupt Setting Register                        */
7307 
7308         struct
7309         {
7310             __IOM uint32_t TIS : 1;    /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
7311                                         *   the mode selected by the TIM bit to notify an interrupt.                  */
7312             uint32_t           : 3;
7313             __IOM uint32_t TIM : 1;    /*!< [4..4] Transmit Interrupt Mode                                            */
7314             uint32_t           : 27;
7315         } TRIMD_b;
7316     };
7317     __IM uint32_t RESERVED13[18];
7318 
7319     union
7320     {
7321         __IOM uint32_t RBWAR;          /*!< (@ 0x000000C8) Receive Buffer Write Address Register                      */
7322 
7323         struct
7324         {
7325             __IM uint32_t RBWAR : 32;  /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
7326                                         *   indicates the last address that the EDMAC has written data
7327                                         *   to when writing to the receive buffer.Refer to the address
7328                                         *   indicated by the RBWAR register to recognize which address
7329                                         *   in the receive buffer the EDMAC is writing data to. Note
7330                                         *   that the address that the EDMAC is outputting to the receive
7331                                         *   buffer may not match the read value of the RBWAR register
7332                                         *   during data reception.                                                    */
7333         } RBWAR_b;
7334     };
7335 
7336     union
7337     {
7338         __IOM uint32_t RDFAR;          /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register                  */
7339 
7340         struct
7341         {
7342             __IM uint32_t RDFAR : 32;  /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
7343                                         *   indicates the start address of the last fetched receive
7344                                         *   descriptor when the EDMAC fetches descriptor information
7345                                         *   from the receive descriptor.Refer to the address indicated
7346                                         *   by the RDFAR register to recognize which receive descriptor
7347                                         *   information the EDMAC is using for the current processing.
7348                                         *   Note that the address of the receive descriptor that the
7349                                         *   EDMAC fetches may not match the read value of the RDFAR
7350                                         *   register during data reception.                                           */
7351         } RDFAR_b;
7352     };
7353     __IM uint32_t RESERVED14;
7354 
7355     union
7356     {
7357         __IOM uint32_t TBRAR;          /*!< (@ 0x000000D4) Transmit Buffer Read Address Register                      */
7358 
7359         struct
7360         {
7361             __IM uint32_t TBRAR : 32;  /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
7362                                         *   indicates the last address that the EDMAC has read data
7363                                         *   from when reading data from the transmit buffer.Refer to
7364                                         *   the address indicated by the TBRAR register to recognize
7365                                         *   which address in the transmit buffer the EDMAC is reading
7366                                         *   from. Note that the address that the EDMAC is outputting
7367                                         *   to the transmit buffer may not match the read value of
7368                                         *   the TBRAR register.                                                       */
7369         } TBRAR_b;
7370     };
7371 
7372     union
7373     {
7374         __IM uint32_t TDFAR;           /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register                 */
7375 
7376         struct
7377         {
7378             __IM uint32_t TDFAR : 32;  /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
7379                                         *   register indicates the start address of the last fetched
7380                                         *   transmit descriptor when the EDMAC fetches descriptor information
7381                                         *   from the transmit descriptor.Refer to the address indicated
7382                                         *   by the TDFAR register to recognize which transmit descriptor
7383                                         *   information the EDMAC is using for the current processing.
7384                                         *   Note that the address of the transmit descriptor that the
7385                                         *   EDMAC fetches may not match the read value of the TDFAR
7386                                         *   register.                                                                 */
7387         } TDFAR_b;
7388     };
7389 } R_ETHERC_EDMAC_Type;                 /*!< Size = 220 (0xdc)                                                         */
7390 
7391 /* =========================================================================================================================== */
7392 /* ================                                      R_ETHERC_EPTPC                                       ================ */
7393 /* =========================================================================================================================== */
7394 
7395 /**
7396  * @brief Ethernet PTP Controller (R_ETHERC_EPTPC)
7397  */
7398 
7399 typedef struct                         /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure                                   */
7400 {
7401     union
7402     {
7403         __IOM uint32_t SYSR;           /*!< (@ 0x00000000) SYNFP Status Register                                      */
7404 
7405         struct
7406         {
7407             __IOM uint32_t OFMUD  : 1; /*!< [0..0] offsetFromMaster Value Update Flag                                 */
7408             __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag             */
7409             __IOM uint32_t MPDUD  : 1; /*!< [2..2] meanPathDelay Value Update Flag                                    */
7410             uint32_t              : 1;
7411             __IOM uint32_t DRPTO  : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag            */
7412             __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag                 */
7413             __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag                   */
7414             uint32_t              : 5;
7415             __IOM uint32_t RECLP  : 1; /*!< [12..12] Loop Reception Detection Flag                                    */
7416             uint32_t              : 1;
7417             __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag                   */
7418             uint32_t              : 1;
7419             __IOM uint32_t RESDN  : 1; /*!< [16..16] Response Stop Completion Detection Flag                          */
7420             __IOM uint32_t GENDN  : 1; /*!< [17..17] Generation Stop Completion Detection Flag                        */
7421             uint32_t              : 14;
7422         } SYSR_b;
7423     };
7424 
7425     union
7426     {
7427         __IOM uint32_t SYIPR;          /*!< (@ 0x00000004) SYNFP Status Notification Permission Register              */
7428 
7429         struct
7430         {
7431             __IOM uint32_t OFMUD  : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission                          */
7432             __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission                         */
7433             __IOM uint32_t MPDUD  : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission                          */
7434             uint32_t              : 1;
7435             __IOM uint32_t DRPTO  : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission                          */
7436             __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission                         */
7437             __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission                         */
7438             uint32_t              : 5;
7439             __IOM uint32_t RECLP  : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission                        */
7440             uint32_t              : 1;
7441             __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission                       */
7442             uint32_t              : 1;
7443             __IOM uint32_t RESDN  : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission                        */
7444             __IOM uint32_t GENDN  : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission                        */
7445             uint32_t              : 14;
7446         } SYIPR_b;
7447     };
7448     __IM uint32_t RESERVED[2];
7449 
7450     union
7451     {
7452         __IOM uint32_t SYMACRU;          /*!< (@ 0x00000010) SYNFP MAC Address Registers                                */
7453 
7454         struct
7455         {
7456             __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
7457                                           *   bits of the local MAC address.                                            */
7458             uint32_t : 8;
7459         } SYMACRU_b;
7460     };
7461 
7462     union
7463     {
7464         __IOM uint32_t SYMACRL;          /*!< (@ 0x00000014) SYNFP MAC Address Registers                                */
7465 
7466         struct
7467         {
7468             __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
7469                                           *   of the local MAC address.                                                 */
7470             uint32_t : 8;
7471         } SYMACRL_b;
7472     };
7473 
7474     union
7475     {
7476         __IOM uint32_t SYLLCCTLR;      /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register                               */
7477 
7478         struct
7479         {
7480             __IOM uint32_t CTL : 8;    /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the
7481                                         *   control field in the LLC sublayer when generating IEEE802.3
7482                                         *   frames.                                                                   */
7483             uint32_t : 24;
7484         } SYLLCCTLR_b;
7485     };
7486 
7487     union
7488     {
7489         __IOM uint32_t SYIPADDRR;          /*!< (@ 0x0000001C) SYNFP Local IP Address Register                            */
7490 
7491         struct
7492         {
7493             __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address.             */
7494         } SYIPADDRR_b;
7495     };
7496     __IM uint32_t RESERVED1[8];
7497 
7498     union
7499     {
7500         __IOM uint32_t SYSPVRR;        /*!< (@ 0x00000040) SYNFP Specification Version Setting Register               */
7501 
7502         struct
7503         {
7504             __IOM uint32_t VER : 4;    /*!< [3..0] versionPTP Field ValueThese bits are used to set the
7505                                         *   versionPTP field value of the PTP v2 header.When a message
7506                                         *   is received, this value is compared with the versionPTP
7507                                         *   field of the received frame.In generating messages, the
7508                                         *   value is used for the versionPTP field of the frame for
7509                                         *   transmission.Set these bits to 0010b (PTP v2).                            */
7510             __IOM uint32_t TRSP : 4;   /*!< [7..4] transportSpecific Field ValueThese bits are used to set
7511                                         *   the transportSpecific field value of the PTP v2 header.When
7512                                         *   a message is received, this value is compared with the
7513                                         *   transportSpecific field of the received frame.In generating
7514                                         *   messages, the value is used for the transportSpecific field
7515                                         *   of the frame for transmission.Set these bits to 0000b (IEEE
7516                                         *   1588).                                                                    */
7517             uint32_t : 24;
7518         } SYSPVRR_b;
7519     };
7520 
7521     union
7522     {
7523         __IOM uint32_t SYDOMR;         /*!< (@ 0x00000044) SYNFP Domain Number Setting Register                       */
7524 
7525         struct
7526         {
7527             __IOM uint32_t DNUM : 8;   /*!< [7..0] domainNumber Field Value SettingThese bits are used to
7528                                         *   set the domainNumber field value of the PTP v2 header.When
7529                                         *   a message is received, this value is compared with the
7530                                         *   domainNumber field of the received frame as a condition
7531                                         *   for PTP reception processing.In generating messages, the
7532                                         *   value is used for the domainNumber field of the frame for
7533                                         *   transmission.                                                             */
7534             uint32_t : 24;
7535         } SYDOMR_b;
7536     };
7537     __IM uint32_t RESERVED2[2];
7538 
7539     union
7540     {
7541         __IOM uint32_t ANFR;           /*!< (@ 0x00000050) Announce Message Flag Field Setting Register               */
7542 
7543         struct
7544         {
7545             __IOM uint32_t FLAG0 : 1;  /*!< [0..0] leap61This bit is used to set the logical value of the
7546                                         *   leap61 member of timePropertiesDS.                                        */
7547             __IOM uint32_t FLAG1 : 1;  /*!< [1..1] leap59This bit is used to set the logical value of the
7548                                         *   leap59 member of timePropertiesDS.                                        */
7549             __IOM uint32_t FLAG2 : 1;  /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical
7550                                         *   value of the currentUtcOffsetValid member of timePropertiesDS.            */
7551             __IOM uint32_t FLAG3 : 1;  /*!< [3..3] ptpTimescaleThis bit is used to set the logical value
7552                                         *   of the ptpTimescale member of timePropertiesDS.                           */
7553             __IOM uint32_t FLAG4 : 1;  /*!< [4..4] timeTraceableThis bit is used to set the logical value
7554                                         *   of the timeTraceable member of timePropertiesDS.                          */
7555             __IOM uint32_t FLAG5 : 1;  /*!< [5..5] frequencyTraceableThis bit is used to set the logical
7556                                         *   value of the frequencyTraceable member of timePropertiesDS.               */
7557             uint32_t              : 2;
7558             __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
7559             uint32_t              : 1;
7560             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
7561             uint32_t              : 2;
7562             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
7563             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
7564             uint32_t              : 17;
7565         } ANFR_b;
7566     };
7567 
7568     union
7569     {
7570         __IOM uint32_t SYNFR;          /*!< (@ 0x00000054) Sync Message Flag Field Setting Register                   */
7571 
7572         struct
7573         {
7574             uint32_t              : 8;
7575             __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
7576             __IOM uint32_t FLAG9  : 1; /*!< [9..9] twoStepFlag                                                        */
7577             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
7578             uint32_t              : 2;
7579             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
7580             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
7581             uint32_t              : 17;
7582         } SYNFR_b;
7583     };
7584 
7585     union
7586     {
7587         __IOM uint32_t DYRQFR;         /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register              */
7588 
7589         struct
7590         {
7591             uint32_t              : 10;
7592             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
7593             uint32_t              : 2;
7594             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
7595             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
7596             uint32_t              : 17;
7597         } DYRQFR_b;
7598     };
7599 
7600     union
7601     {
7602         __IOM uint32_t DYRPFR;         /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register             */
7603 
7604         struct
7605         {
7606             uint32_t              : 8;
7607             __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
7608             __IOM uint32_t FLAG9  : 1; /*!< [9..9] woStepFlag                                                         */
7609             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
7610             uint32_t              : 2;
7611             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
7612             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
7613             uint32_t              : 17;
7614         } DYRPFR_b;
7615     };
7616 
7617     union
7618     {
7619         __IOM uint32_t SYCIDRU;          /*!< (@ 0x00000060) SYNFP Local Clock ID Registers                             */
7620 
7621         struct
7622         {
7623             __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
7624                                           *   bits of the clock-ID of your port.                                        */
7625         } SYCIDRU_b;
7626     };
7627 
7628     union
7629     {
7630         __IOM uint32_t SYCIDRL;          /*!< (@ 0x00000064) SYNFP Local Clock ID Registers                             */
7631 
7632         struct
7633         {
7634             __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
7635                                           *   of the clock-ID of your port.                                             */
7636         } SYCIDRL_b;
7637     };
7638 
7639     union
7640     {
7641         __IOM uint32_t SYPNUMR;        /*!< (@ 0x00000068) SYNFP Local Port Number Register                           */
7642 
7643         struct
7644         {
7645             __IOM uint32_t PNUM : 16;  /*!< [15..0] Local Port Number SettingThese bits hold the setting
7646                                         *   for the port number of the local port.                                    */
7647             uint32_t : 16;
7648         } SYPNUMR_b;
7649     };
7650     __IM uint32_t RESERVED3[5];
7651 
7652     union
7653     {
7654         __OM uint32_t SYRVLDR;         /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register               */
7655 
7656         struct
7657         {
7658             __OM uint32_t BMUP : 1;    /*!< [0..0] BMC Update                                                         */
7659             __OM uint32_t STUP : 1;    /*!< [1..1] State Update                                                       */
7660             __OM uint32_t ANUP : 1;    /*!< [2..2] Announce Message Generation Information Update                     */
7661             uint32_t           : 29;
7662         } SYRVLDR_b;
7663     };
7664     __IM uint32_t RESERVED4[3];
7665 
7666     union
7667     {
7668         __IOM uint32_t SYRFL1R;        /*!< (@ 0x00000090) SYNFP Reception Filter Register 1                          */
7669 
7670         struct
7671         {
7672             __IOM uint32_t ANCE0  : 1; /*!< [0..0] Announce Message Processing                                        */
7673             __IOM uint32_t ANCE1  : 1; /*!< [1..1] Announce Message Processing                                        */
7674             uint32_t              : 2;
7675             __IOM uint32_t SYNC0  : 1; /*!< [4..4] Sync Message Processing                                            */
7676             __IOM uint32_t SYNC1  : 1; /*!< [5..5] Sync Message Processing                                            */
7677             __IOM uint32_t SYNC2  : 1; /*!< [6..6] Sync Message Processing                                            */
7678             uint32_t              : 1;
7679             __IOM uint32_t FUP0   : 1; /*!< [8..8] Follow_Up Message Processing                                       */
7680             __IOM uint32_t FUP1   : 1; /*!< [9..9] Follow_Up Message Processing                                       */
7681             __IOM uint32_t FUP2   : 1; /*!< [10..10] Follow_Up Message Processing                                     */
7682             uint32_t              : 1;
7683             __IOM uint32_t DRQ0   : 1; /*!< [12..12] Delay_Req Message Processing                                     */
7684             __IOM uint32_t DRQ1   : 1; /*!< [13..13] Delay_Req Message Processing                                     */
7685             __IOM uint32_t DRQ2   : 1; /*!< [14..14] Delay_Req Message Processing                                     */
7686             uint32_t              : 1;
7687             __IOM uint32_t DRP0   : 1; /*!< [16..16] Delay_Resp Message Processing                                    */
7688             __IOM uint32_t DRP1   : 1; /*!< [17..17] Delay_Resp Message Processing                                    */
7689             __IOM uint32_t DRP2   : 1; /*!< [18..18] Delay_Resp Message Processing                                    */
7690             uint32_t              : 1;
7691             __IOM uint32_t PDRQ0  : 1; /*!< [20..20] Pdelay_Req Message Processing                                    */
7692             __IOM uint32_t PDRQ1  : 1; /*!< [21..21] Pdelay_Req Message Processing                                    */
7693             __IOM uint32_t PDRQ2  : 1; /*!< [22..22] Pdelay_Req Message Processing                                    */
7694             uint32_t              : 1;
7695             __IOM uint32_t PDRP0  : 1; /*!< [24..24] Pdelay_Resp Message Processing                                   */
7696             __IOM uint32_t PDRP1  : 1; /*!< [25..25] Pdelay_Resp Message Processing                                   */
7697             __IOM uint32_t PDRP2  : 1; /*!< [26..26] Pdelay_Resp Message Processing                                   */
7698             uint32_t              : 1;
7699             __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing                         */
7700             __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing                         */
7701             __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing                         */
7702             uint32_t              : 1;
7703         } SYRFL1R_b;
7704     };
7705 
7706     union
7707     {
7708         __IOM uint32_t SYRFL2R;        /*!< (@ 0x00000094) SYNFP Reception Filter Register 2                          */
7709 
7710         struct
7711         {
7712             __IOM uint32_t MAN0 : 1;   /*!< [0..0] Management Message Processing Setting                              */
7713             __IOM uint32_t MAN1 : 1;   /*!< [1..1] Management Message Processing Setting                              */
7714             uint32_t            : 2;
7715             __IOM uint32_t SIG0 : 1;   /*!< [4..4] Signaling Message Processing Setting                               */
7716             __IOM uint32_t SIG1 : 1;   /*!< [5..5] Signaling Message Processing Setting                               */
7717             uint32_t            : 22;
7718             __IOM uint32_t ILL0 : 1;   /*!< [28..28] Illegal Message Processing Setting                               */
7719             __IOM uint32_t ILL1 : 1;   /*!< [29..29] Illegal Message Processing Setting                               */
7720             uint32_t            : 2;
7721         } SYRFL2R_b;
7722     };
7723 
7724     union
7725     {
7726         __IOM uint32_t SYTRENR;        /*!< (@ 0x00000098) SYNFP Transmission Enable Register                         */
7727 
7728         struct
7729         {
7730             __IOM uint32_t ANCE : 1;   /*!< [0..0] Announce Message Transmission Enable                               */
7731             uint32_t            : 3;
7732             __IOM uint32_t SYNC : 1;   /*!< [4..4] Sync Message Transmission Enable                                   */
7733             uint32_t            : 3;
7734             __IOM uint32_t DRQ  : 1;   /*!< [8..8] Delay_Req Message Transmission Enable                              */
7735             uint32_t            : 3;
7736             __IOM uint32_t PDRQ : 1;   /*!< [12..12] Pdelay_Req Message Transmission Enable                           */
7737             uint32_t            : 19;
7738         } SYTRENR_b;
7739     };
7740     __IM uint32_t RESERVED5;
7741 
7742     union
7743     {
7744         __IOM uint32_t MTCIDU;          /*!< (@ 0x000000A0) Master Clock ID Registers                                  */
7745 
7746         struct
7747         {
7748             __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
7749                                          *   bits of the clock-ID of the master clock.                                 */
7750         } MTCIDU_b;
7751     };
7752 
7753     union
7754     {
7755         __IOM uint32_t MTCIDL;          /*!< (@ 0x000000A4) Master Clock ID Registers                                  */
7756 
7757         struct
7758         {
7759             __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
7760                                          *   of the clock-ID of the master clock.                                      */
7761         } MTCIDL_b;
7762     };
7763 
7764     union
7765     {
7766         __IOM uint32_t MTPID;          /*!< (@ 0x000000A8) Master clock port number register                          */
7767 
7768         struct
7769         {
7770             __IOM uint32_t PNUM : 16;  /*!< [15..0] Master Clock Port Number SettingThese bits hold the
7771                                         *   setting for the port number of the master clock.                          */
7772             uint32_t : 16;
7773         } MTPID_b;
7774     };
7775     __IM uint32_t RESERVED6[5];
7776 
7777     union
7778     {
7779         __IOM uint32_t SYTLIR;         /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register               */
7780 
7781         struct
7782         {
7783             __IOM uint32_t ANCE : 8;   /*!< [7..0] Announce Message Transmission Interval SettingThese bits
7784                                         *   set the interval for the transmission of Announce messages.               */
7785             __IOM uint32_t SYNC : 8;   /*!< [15..8] Sync Message Transmission Interval SettingThese bits
7786                                         *   set the interval for the transmission of Sync messages.
7787                                         *   The setting is also placed in the logMessageInterval field
7788                                         *   of transmitted Sync messages.                                             */
7789             __IOM uint32_t DREQ : 8;   /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req
7790                                         *   Transmission Interval SettingThe bits set the average interval
7791                                         *   for the transmission of Delay_Req messages and the interval
7792                                         *   for the transmission of Pdelay_Req messages.The setting
7793                                         *   is also placed in the logMessageInterval field of Delay_Resp
7794                                         *   messages.                                                                 */
7795             uint32_t : 8;
7796         } SYTLIR_b;
7797     };
7798 
7799     union
7800     {
7801         __IM uint32_t SYRLIR;          /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication
7802                                         *                  Register                                                   */
7803 
7804         struct
7805         {
7806             __IM uint32_t ANCE : 8;    /*!< [7..0] Announce Message logMessageInterval Field IndicationThese
7807                                         *   bits indicate the logMessageInterval field value of a received
7808                                         *   Announce message.                                                         */
7809             __IM uint32_t SYNC : 8;    /*!< [15..8] Sync Message logMessageInterval Field IndicationThese
7810                                         *   bits indicate the logMessageInterval field value of a received
7811                                         *   Sync message.                                                             */
7812             __IM uint32_t DRESP : 8;   /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese
7813                                         *   bits indicate the logMessageInterval field value of a received
7814                                         *   Delay_Resp message.                                                       */
7815             uint32_t : 8;
7816         } SYRLIR_b;
7817     };
7818 
7819     union
7820     {
7821         __IM uint32_t OFMRU;           /*!< (@ 0x000000C8) offsetFromMaster Value Registers                           */
7822 
7823         struct
7824         {
7825             __IM uint32_t OFMRU : 32;  /*!< [31..0] These bits indicate the higher-order 32 bits of the
7826                                         *   calculated offsetFromMaster value.                                        */
7827         } OFMRU_b;
7828     };
7829 
7830     union
7831     {
7832         __IM uint32_t OFMRL;           /*!< (@ 0x000000CC) offsetFromMaster Value Registers                           */
7833 
7834         struct
7835         {
7836             __IM uint32_t OFMRL : 32;  /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
7837                                         *   offsetFromMaster value.                                                   */
7838         } OFMRL_b;
7839     };
7840 
7841     union
7842     {
7843         __IM uint32_t MPDRU;           /*!< (@ 0x000000D0) meanPathDelay Value Registers                              */
7844 
7845         struct
7846         {
7847             __IM uint32_t MPDRU : 32;  /*!< [31..0] These bits indicate the higher-order 32 bits of the
7848                                         *   calculated meanPathDelay value.                                           */
7849         } MPDRU_b;
7850     };
7851 
7852     union
7853     {
7854         __IM uint32_t MPDRL;           /*!< (@ 0x000000D4) meanPathDelay Value Registers                              */
7855 
7856         struct
7857         {
7858             __IM uint32_t MPDRL : 32;  /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
7859                                         *   meanPathDelay value.                                                      */
7860         } MPDRL_b;
7861     };
7862     __IM uint32_t RESERVED7[2];
7863 
7864     union
7865     {
7866         __IOM uint32_t GMPR;           /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register                 */
7867 
7868         struct
7869         {
7870             __IOM uint32_t GMPR2 : 8;  /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are
7871                                         *   used to set the value of the grandmasterPriority2 fields
7872                                         *   of Announce messages.                                                     */
7873             uint32_t             : 8;
7874             __IOM uint32_t GMPR1 : 8;  /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits
7875                                         *   are used to set the value of the grandmasterPriority1 fields
7876                                         *   of Announce messages.                                                     */
7877             uint32_t : 8;
7878         } GMPR_b;
7879     };
7880 
7881     union
7882     {
7883         __IOM uint32_t GMCQR;          /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register             */
7884 
7885         struct
7886         {
7887             __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality
7888                                         *   fields of Announce messages. The correspondence between
7889                                         *   bits and the grandmasterClockQuality fields is as listed
7890                                         *   below.b31 to b24: clockClassb23 to b16: clockAccuracyb15
7891                                         *   to b0: offsetScaledLogVariance                                            */
7892         } GMCQR_b;
7893     };
7894 
7895     union
7896     {
7897         __IOM uint32_t GMIDRU;          /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers                */
7898 
7899         struct
7900         {
7901             __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
7902                                          *   bits of the value of the grandmasterIdentity fields of
7903                                          *   Announce messages.                                                        */
7904         } GMIDRU_b;
7905     };
7906 
7907     union
7908     {
7909         __IOM uint32_t GMIDRL;          /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers                */
7910 
7911         struct
7912         {
7913             __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
7914                                          *   of the value of the grandmasterIdentity fields of Announce
7915                                          *   messages.                                                                 */
7916         } GMIDRL_b;
7917     };
7918 
7919     union
7920     {
7921         __IOM uint32_t CUOTSR;         /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register         */
7922 
7923         struct
7924         {
7925             __IOM uint32_t TSRC : 8;   /*!< [7..0] timeSource Field SettingThese bits set the value of the
7926                                         *   timeSource fields of Announce messages.                                   */
7927             uint32_t            : 8;
7928             __IOM uint32_t CUTO : 16;  /*!< [31..16] currentUtcOffset Field SettingThese bits set the value
7929                                         *   of the currentUtcOffset fields of Announce messages.                      */
7930         } CUOTSR_b;
7931     };
7932 
7933     union
7934     {
7935         __IOM uint32_t SRR;            /*!< (@ 0x000000F4) stepsRemoved Field Setting Register                        */
7936 
7937         struct
7938         {
7939             __IOM uint32_t SRMV : 16;  /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value
7940                                         *   of the stepsRemoved fields of Announce messages.                          */
7941             uint32_t : 16;
7942         } SRR_b;
7943     };
7944     __IM uint32_t RESERVED8[2];
7945 
7946     union
7947     {
7948         __IOM uint32_t PPMACRU;          /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting
7949                                           *                  Registers                                                  */
7950 
7951         struct
7952         {
7953             __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
7954                                           *   bits of the destination MAC address for PTP-primary messages.             */
7955             uint32_t : 8;
7956         } PPMACRU_b;
7957     };
7958 
7959     union
7960     {
7961         __IOM uint32_t PPMACRL;          /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting
7962                                           *                  Registers                                                  */
7963 
7964         struct
7965         {
7966             __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
7967                                           *   of the destination MAC address for PTP-primary messages.                  */
7968             uint32_t : 8;
7969         } PPMACRL_b;
7970     };
7971 
7972     union
7973     {
7974         __IOM uint32_t PDMACRU;          /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers           */
7975 
7976         struct
7977         {
7978             __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
7979                                           *   bits of the destination MAC address for PTP-pdelay messages.              */
7980             uint32_t : 8;
7981         } PDMACRU_b;
7982     };
7983 
7984     union
7985     {
7986         __IOM uint32_t PDMACRL;          /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers           */
7987 
7988         struct
7989         {
7990             __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
7991                                           *   of the destination MAC address for PTP-pdelay messages.                   */
7992             uint32_t : 8;
7993         } PDMACRL_b;
7994     };
7995 
7996     union
7997     {
7998         __IOM uint32_t PETYPER;        /*!< (@ 0x00000110) PTP Message EtherType Setting Register                     */
7999 
8000         struct
8001         {
8002             __IOM uint32_t TYPE : 16;  /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the
8003                                         *   setting for the EtherType field value for frames in the
8004                                         *   Ethernet II format.                                                       */
8005             uint32_t : 16;
8006         } PETYPER_b;
8007     };
8008     __IM uint32_t RESERVED9[3];
8009 
8010     union
8011     {
8012         __IOM uint32_t PPIPR;          /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting
8013                                         *                  Register                                                   */
8014 
8015         struct
8016         {
8017             __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
8018                                         *   for PTPprimary messages.                                                  */
8019         } PPIPR_b;
8020     };
8021 
8022     union
8023     {
8024         __IOM uint32_t PDIPR;          /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting
8025                                         *                  Register                                                   */
8026 
8027         struct
8028         {
8029             __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
8030                                         *   for PTPpdelay messages.                                                   */
8031         } PDIPR_b;
8032     };
8033 
8034     union
8035     {
8036         __IOM uint32_t PETOSR;         /*!< (@ 0x00000128) PTP Event Message TOS Setting Register                     */
8037 
8038         struct
8039         {
8040             __IOM uint32_t EVTO : 8;   /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold
8041                                         *   the setting for the value of the TOS field within the IPv4
8042                                         *   headers of PTP event messages.                                            */
8043             uint32_t : 24;
8044         } PETOSR_b;
8045     };
8046 
8047     union
8048     {
8049         __IOM uint32_t PGTOSR;         /*!< (@ 0x0000012C) PTP general Message TOS Setting Register                   */
8050 
8051         struct
8052         {
8053             __IOM uint32_t GETO : 8;   /*!< [7..0] PTP general Message TOS Field Value SettingThese bits
8054                                         *   hold the setting for the value of the TOS field within
8055                                         *   the IPv4 headers of PTP general messages.                                 */
8056             uint32_t : 24;
8057         } PGTOSR_b;
8058     };
8059 
8060     union
8061     {
8062         __IOM uint32_t PPTTLR;         /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register                   */
8063 
8064         struct
8065         {
8066             __IOM uint32_t PRTL : 8;   /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits
8067                                         *   hold the setting for the value of the TTL field within
8068                                         *   the IPv4 headers of PTP-primary messages.                                 */
8069             uint32_t : 24;
8070         } PPTTLR_b;
8071     };
8072 
8073     union
8074     {
8075         __IOM uint32_t PDTTLR;         /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register                    */
8076 
8077         struct
8078         {
8079             __IOM uint32_t PDTL : 8;   /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the
8080                                         *   setting for the value of the TTL field within the IPv4
8081                                         *   headers of PTP-pdelay messages.                                           */
8082             uint32_t : 24;
8083         } PDTTLR_b;
8084     };
8085 
8086     union
8087     {
8088         __IOM uint32_t PEUDPR;         /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number
8089                                         *                  Setting Register                                           */
8090 
8091         struct
8092         {
8093             __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese
8094                                         *   bits hold the setting for the value of the destination
8095                                         *   port number field within the UDP headers of PTP event messages.           */
8096             uint32_t : 16;
8097         } PEUDPR_b;
8098     };
8099 
8100     union
8101     {
8102         __IOM uint32_t PGUDPR;         /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number
8103                                         *                  Setting Register                                           */
8104 
8105         struct
8106         {
8107             __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits
8108                                         *   hold the setting for the value of the destination port
8109                                         *   number field within the UDP headers of PTP general messages.              */
8110             uint32_t : 16;
8111         } PGUDPR_b;
8112     };
8113 
8114     union
8115     {
8116         __IOM uint32_t FFLTR;          /*!< (@ 0x00000140) Frame Reception Filter Setting Register                    */
8117 
8118         struct
8119         {
8120             __IOM uint32_t SEL : 1;    /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these
8121                                         *   bits is only effective when EXTPRM=0, ENB=1and RPT=1.                     */
8122             __IOM uint32_t PRT : 1;    /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits
8123                                         *   is only effective when EXTPRM=0 and ENB=1.                                */
8124             __IOM uint32_t ENB : 1;    /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits
8125                                         *   is only effective when EXTPRM=0.                                          */
8126             uint32_t              : 13;
8127             __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting                                 */
8128             uint32_t              : 15;
8129         } FFLTR_b;
8130     };
8131     __IM uint32_t RESERVED10[7];
8132 
8133     union
8134     {
8135         __IOM uint32_t FMAC0RU;          /*!< (@ 0x00000160) Frame Reception Filter MAC Address 0 Setting
8136                                           *                  Register Upper                                             */
8137 
8138         struct
8139         {
8140             __IOM uint32_t FMAC0RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination
8141                                           *   MAC address for received multicast frames.                                */
8142             uint32_t : 8;
8143         } FMAC0RU_b;
8144     };
8145 
8146     union
8147     {
8148         __IOM uint32_t FMAC0RL;          /*!< (@ 0x00000164) Frame Reception Filter MAC Address 0 Setting
8149                                           *                  Register Lower                                             */
8150 
8151         struct
8152         {
8153             __IOM uint32_t FMAC0RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination
8154                                           *   MAC address for received multicast frames.                                */
8155             uint32_t : 8;
8156         } FMAC0RL_b;
8157     };
8158 
8159     union
8160     {
8161         __IOM uint32_t FMAC1RU;          /*!< (@ 0x00000168) Frame Reception Filter MAC Address 1 Setting
8162                                           *                  Register Upper                                             */
8163 
8164         struct
8165         {
8166             __IOM uint32_t FMAC1RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination
8167                                           *   MAC address for received multicast frames.                                */
8168             uint32_t : 8;
8169         } FMAC1RU_b;
8170     };
8171 
8172     union
8173     {
8174         __IOM uint32_t FMAC1RL;          /*!< (@ 0x0000016C) Frame Reception Filter MAC Address 1 Setting
8175                                           *                  Register Lower                                             */
8176 
8177         struct
8178         {
8179             __IOM uint32_t FMAC1RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination
8180                                           *   MAC address for received multicast frames.                                */
8181             uint32_t : 8;
8182         } FMAC1RL_b;
8183     };
8184     __IM uint32_t RESERVED11[20];
8185 
8186     union
8187     {
8188         __IOM uint32_t DASYMRU;          /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers                         */
8189 
8190         struct
8191         {
8192             __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
8193                                           *   bits of the asymmetric delay value.                                       */
8194             uint32_t : 16;
8195         } DASYMRU_b;
8196     };
8197 
8198     union
8199     {
8200         __IOM uint32_t DASYMRL;          /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers                         */
8201 
8202         struct
8203         {
8204             __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
8205                                           *   of the asymmetric delay value.                                            */
8206         } DASYMRL_b;
8207     };
8208 
8209     union
8210     {
8211         __IOM uint32_t TSLATR;         /*!< (@ 0x000001C8) Timestamp Latency Setting Register                         */
8212 
8213         struct
8214         {
8215             __IOM uint32_t EGP : 16;   /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold
8216                                         *   the setting for the time stamp latency (ns) for the input
8217                                         *   ports.                                                                    */
8218             __IOM uint32_t INGP : 16;  /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold
8219                                         *   the setting for the time stamp latency (ns) for the output
8220                                         *   ports.                                                                    */
8221         } TSLATR_b;
8222     };
8223 
8224     union
8225     {
8226         __IOM uint32_t SYCONFR;        /*!< (@ 0x000001CC) SYNFP Operation Setting Register                           */
8227 
8228         struct
8229         {
8230             __IOM uint32_t TCYC : 8;   /*!< [7..0] PTP Message Transmission Interval SettingThese bits are
8231                                         *   used to set the time from the completion of one transmission
8232                                         *   to the start of the next in cycles of the transmission
8233                                         *   clock. A value n in these bits means that a transmission
8234                                         *   interval of n cycles will be secured.No interval is secured
8235                                         *   if the setting is 00h.We recommend the setting 28h (40
8236                                         *   cycles).                                                                  */
8237             uint32_t              : 4;
8238             __IOM uint32_t SBDIS  : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable             */
8239             uint32_t              : 3;
8240             __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable                      */
8241             uint32_t              : 3;
8242             __IOM uint32_t TCMOD  : 1; /*!< [20..20] TC Mode Setting                                                  */
8243             uint32_t              : 11;
8244         } SYCONFR_b;
8245     };
8246 
8247     union
8248     {
8249         __IOM uint32_t SYFORMR;        /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register                        */
8250 
8251         struct
8252         {
8253             __IOM uint32_t FORM0 : 1;  /*!< [0..0] Ethernet/UDP Encapsulation                                         */
8254             __IOM uint32_t FORM1 : 1;  /*!< [1..1] Ethernet Frame Format Setting                                      */
8255             uint32_t             : 30;
8256         } SYFORMR_b;
8257     };
8258 
8259     union
8260     {
8261         __IOM uint32_t RSTOUTR;          /*!< (@ 0x000001D4) Response Message Reception Timeout Register                */
8262 
8263         struct
8264         {
8265             __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response
8266                                           *   message not being received within n x 1024 (ns), where
8267                                           *   n is the setting, is judged to represent a timeout.                       */
8268         } RSTOUTR_b;
8269     };
8270 } R_ETHERC_EPTPC_Type;                   /*!< Size = 472 (0x1d8)                                                        */
8271 
8272 /* =========================================================================================================================== */
8273 /* ================                                    R_ETHERC_EPTPC_CFG                                     ================ */
8274 /* =========================================================================================================================== */
8275 
8276 /**
8277  * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG)
8278  */
8279 
8280 typedef struct                         /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure                               */
8281 {
8282     union
8283     {
8284         __IOM uint32_t PTRSTR;         /*!< (@ 0x00000000) EPTPC Reset Register                                       */
8285 
8286         struct
8287         {
8288             __IOM uint32_t RESET : 1;  /*!< [0..0] EPTPC Software Reset                                               */
8289             uint32_t             : 31;
8290         } PTRSTR_b;
8291     };
8292 
8293     union
8294     {
8295         __IOM uint32_t STCSELR;         /*!< (@ 0x00000004) STCA Clock Select Register                                 */
8296 
8297         struct
8298         {
8299             __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division                                     */
8300             uint32_t               : 5;
8301             __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select                                                 */
8302             uint32_t               : 21;
8303         } STCSELR_b;
8304     };
8305 
8306     union
8307     {
8308         __IOM uint32_t BYPASS;          /*!< (@ 0x00000008) Bypass 1588 module Register                                */
8309 
8310         struct
8311         {
8312             __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch                                   */
8313             uint32_t               : 15;
8314             __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch                                 */
8315             uint32_t               : 15;
8316         } BYPASS_b;
8317     };
8318 } R_ETHERC_EPTPC_CFG_Type;              /*!< Size = 12 (0xc)                                                           */
8319 
8320 /* =========================================================================================================================== */
8321 /* ================                                   R_ETHERC_EPTPC_COMMON                                   ================ */
8322 /* =========================================================================================================================== */
8323 
8324 /**
8325  * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON)
8326  */
8327 
8328 typedef struct                         /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure                            */
8329 {
8330     union
8331     {
8332         __IOM uint32_t MIESR;          /*!< (@ 0x00000000) MINT Interrupt Source Status Register                      */
8333 
8334         struct
8335         {
8336             __IM uint32_t ST    : 1;   /*!< [0..0] STCA Status Flag                                                   */
8337             __IM uint32_t SY0   : 1;   /*!< [1..1] SYNFP0 Status Flag                                                 */
8338             __IM uint32_t SY1   : 1;   /*!< [2..2] SYNFP1 Status Flag                                                 */
8339             __IM uint32_t PRC   : 1;   /*!< [3..3] PRC-TC Status Flag                                                 */
8340             uint32_t            : 12;
8341             __IOM uint32_t CYC0 : 1;   /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag                  */
8342             __IOM uint32_t CYC1 : 1;   /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag                  */
8343             __IOM uint32_t CYC2 : 1;   /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag                  */
8344             __IOM uint32_t CYC3 : 1;   /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag                  */
8345             __IOM uint32_t CYC4 : 1;   /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag                  */
8346             __IOM uint32_t CYC5 : 1;   /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag                  */
8347             uint32_t            : 10;
8348         } MIESR_b;
8349     };
8350 
8351     union
8352     {
8353         __IOM uint32_t MIEIPR;         /*!< (@ 0x00000004) MINT Interrupt Request Permission Register                 */
8354 
8355         struct
8356         {
8357             __IOM uint32_t ST   : 1;   /*!< [0..0] STCA Status Interrupt Request Permission                           */
8358             __IOM uint32_t SY0  : 1;   /*!< [1..1] SYNFP0 Status Interrupt Request Permission                         */
8359             __IOM uint32_t SY1  : 1;   /*!< [2..2] SYNFP1 Status Interrupt Request Permission                         */
8360             __IOM uint32_t PRC  : 1;   /*!< [3..3] PRC-TC Status Interrupt Request Permission                         */
8361             uint32_t            : 12;
8362             __IOM uint32_t CYC0 : 1;   /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt
8363                                         *   Request Permission                                                        */
8364             __IOM uint32_t CYC1 : 1;   /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt
8365                                         *   Request Permission                                                        */
8366             __IOM uint32_t CYC2 : 1;   /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt
8367                                         *   Request Permission                                                        */
8368             __IOM uint32_t CYC3 : 1;   /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt
8369                                         *   Request Permission                                                        */
8370             __IOM uint32_t CYC4 : 1;   /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt
8371                                         *   Request Permission                                                        */
8372             __IOM uint32_t CYC5 : 1;   /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt
8373                                         *   Request Permission                                                        */
8374             uint32_t : 10;
8375         } MIEIPR_b;
8376     };
8377     __IM uint32_t RESERVED[2];
8378 
8379     union
8380     {
8381         __IOM uint32_t ELIPPR;         /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission
8382                                         *                  Register                                                   */
8383 
8384         struct
8385         {
8386             __IOM uint32_t CYCP0 : 1;  /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output
8387                                         *   Enable                                                                    */
8388             __IOM uint32_t CYCP1 : 1;  /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output
8389                                         *   Enable                                                                    */
8390             __IOM uint32_t CYCP2 : 1;  /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output
8391                                         *   Enable                                                                    */
8392             __IOM uint32_t CYCP3 : 1;  /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output
8393                                         *   Enable                                                                    */
8394             __IOM uint32_t CYCP4 : 1;  /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output
8395                                         *   Enable                                                                    */
8396             __IOM uint32_t CYCP5 : 1;  /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output
8397                                         *   Enable                                                                    */
8398             uint32_t             : 2;
8399             __IOM uint32_t CYCN0 : 1;  /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output
8400                                         *   Enable                                                                    */
8401             __IOM uint32_t CYCN1 : 1;  /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output
8402                                         *   Enable                                                                    */
8403             __IOM uint32_t CYCN2 : 1;  /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output
8404                                         *   Enable                                                                    */
8405             __IOM uint32_t CYCN3 : 1;  /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output
8406                                         *   Enable                                                                    */
8407             __IOM uint32_t CYCN4 : 1;  /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output
8408                                         *   Enable                                                                    */
8409             __IOM uint32_t CYCN5 : 1;  /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output
8410                                         *   Enable                                                                    */
8411             uint32_t            : 2;
8412             __IOM uint32_t PLSP : 1;   /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt
8413                                         *   Request Permission                                                        */
8414             uint32_t            : 7;
8415             __IOM uint32_t PLSN : 1;   /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt
8416                                         *   Request Permission                                                        */
8417             uint32_t : 7;
8418         } ELIPPR_b;
8419     };
8420 
8421     union
8422     {
8423         __IOM uint32_t ELIPACR;        /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic
8424                                         *                  Clearing Register                                          */
8425 
8426         struct
8427         {
8428             __IOM uint32_t CYCP0 : 1;  /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing                                */
8429             __IOM uint32_t CYCP1 : 1;  /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing                                */
8430             __IOM uint32_t CYCP2 : 1;  /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing                                */
8431             __IOM uint32_t CYCP3 : 1;  /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing                                */
8432             __IOM uint32_t CYCP4 : 1;  /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing                                */
8433             __IOM uint32_t CYCP5 : 1;  /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing                                */
8434             uint32_t             : 2;
8435             __IOM uint32_t CYCN0 : 1;  /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing                                */
8436             __IOM uint32_t CYCN1 : 1;  /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing                                */
8437             __IOM uint32_t CYCN2 : 1;  /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing                              */
8438             __IOM uint32_t CYCN3 : 1;  /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing                              */
8439             __IOM uint32_t CYCN4 : 1;  /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing                              */
8440             __IOM uint32_t CYCN5 : 1;  /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing                              */
8441             uint32_t             : 2;
8442             __IOM uint32_t PLSP  : 1;  /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing                               */
8443             uint32_t             : 7;
8444             __IOM uint32_t PLSN  : 1;  /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing                               */
8445             uint32_t             : 7;
8446         } ELIPACR_b;
8447     };
8448     __IM uint32_t RESERVED1[10];
8449 
8450     union
8451     {
8452         __IOM uint32_t STSR;            /*!< (@ 0x00000040) STCA Status Register                                       */
8453 
8454         struct
8455         {
8456             __IOM uint32_t SYNC    : 1; /*!< [0..0] Synchronized State Detection Flag                                  */
8457             __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag                                */
8458             uint32_t               : 1;
8459             __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag                      */
8460             __IOM uint32_t W10D    : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag                               */
8461             uint32_t               : 27;
8462         } STSR_b;
8463     };
8464 
8465     union
8466     {
8467         __IOM uint32_t STIPR;           /*!< (@ 0x00000044) STCA Status Notification Permission Register               */
8468 
8469         struct
8470         {
8471             __IOM uint32_t SYNC    : 1; /*!< [0..0] SYNC Status Notification Enable                                    */
8472             __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable                                 */
8473             uint32_t               : 1;
8474             __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable                                 */
8475             __IOM uint32_t W10D    : 1; /*!< [4..4] W10D Status Notification Enable                                    */
8476             uint32_t               : 27;
8477         } STIPR_b;
8478     };
8479     __IM uint32_t RESERVED2[2];
8480 
8481     union
8482     {
8483         __IOM uint32_t STCFR;          /*!< (@ 0x00000050) STCA Clock Frequency Setting Register                      */
8484 
8485         struct
8486         {
8487             __IOM uint32_t STCF : 2;   /*!< [1..0] STCA Clock Frequency                                               */
8488             uint32_t            : 30;
8489         } STCFR_b;
8490     };
8491 
8492     union
8493     {
8494         __IOM uint32_t STMR;           /*!< (@ 0x00000054) STCA Operating Mode Register                               */
8495 
8496         struct
8497         {
8498             __IOM uint32_t WINT  : 8;  /*!< [7..0] Worst 10 Acquisition Time                                          */
8499             uint32_t             : 5;
8500             __IOM uint32_t CMOD  : 1;  /*!< [13..13] Time Synchronization Correction Mode                             */
8501             uint32_t             : 1;
8502             __IOM uint32_t W10S  : 1;  /*!< [15..15] Worst 10 Acquisition Control Select                              */
8503             __IOM uint32_t SYTH  : 4;  /*!< [19..16] Synchronized State Detection Threshold Setting                   */
8504             __IOM uint32_t DVTH  : 4;  /*!< [23..20] Synchronization Loss Detection Threshold Setting                 */
8505             uint32_t             : 4;
8506             __IOM uint32_t ALEN0 : 1;  /*!< [28..28] Alarm Detection Enable 0                                         */
8507             __IOM uint32_t ALEN1 : 1;  /*!< [29..29] Alarm Detection Enable 1                                         */
8508             uint32_t             : 2;
8509         } STMR_b;
8510     };
8511 
8512     union
8513     {
8514         __IOM uint32_t SYNTOR;          /*!< (@ 0x00000058) Sync Message Reception Timeout Register                    */
8515 
8516         struct
8517         {
8518             __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns),
8519                                          *   where n is the setting, leads to a timeout for reception
8520                                          *   of Sync messages, leading to the STSR.SYNTOUT flag being
8521                                          *   set to 1.                                                                 */
8522         } SYNTOR_b;
8523     };
8524     __IM uint32_t RESERVED3;
8525 
8526     union
8527     {
8528         __IOM uint32_t IPTSELR;         /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register               */
8529 
8530         struct
8531         {
8532             __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select                                        */
8533             __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select                                        */
8534             __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select                                        */
8535             __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select                                        */
8536             __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select                                        */
8537             __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select                                        */
8538             uint32_t               : 26;
8539         } IPTSELR_b;
8540     };
8541 
8542     union
8543     {
8544         __IOM uint32_t MITSELR;         /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register               */
8545 
8546         struct
8547         {
8548             __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable                  */
8549             __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable                  */
8550             __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable                  */
8551             __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable                  */
8552             __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable                  */
8553             __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable                  */
8554             uint32_t               : 26;
8555         } MITSELR_b;
8556     };
8557 
8558     union
8559     {
8560         __IOM uint32_t ELTSELR;         /*!< (@ 0x00000068) ELC Output Timer Select Register                           */
8561 
8562         struct
8563         {
8564             __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable                      */
8565             __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable                      */
8566             __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable                      */
8567             __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable                      */
8568             __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable                      */
8569             __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable                      */
8570             uint32_t               : 26;
8571         } ELTSELR_b;
8572     };
8573 
8574     union
8575     {
8576         __IOM uint32_t STCHSELR;       /*!< (@ 0x0000006C) Time Synchronization Channel Select Register               */
8577 
8578         struct
8579         {
8580             __IOM uint32_t SYSEL : 1;  /*!< [0..0] Timer Information Input SelectNOTE: Do not change the
8581                                         *   value of this bit while the SYNSTARTR.STR bit is 1.                       */
8582             uint32_t : 31;
8583         } STCHSELR_b;
8584     };
8585     __IM uint32_t RESERVED4[4];
8586 
8587     union
8588     {
8589         __IOM uint32_t SYNSTARTR;      /*!< (@ 0x00000080) Slave Time Synchronization Start Register                  */
8590 
8591         struct
8592         {
8593             __IOM uint32_t STR : 1;    /*!< [0..0] Slave Time Synchronization Control                                 */
8594             uint32_t           : 31;
8595         } SYNSTARTR_b;
8596     };
8597 
8598     union
8599     {
8600         __OM uint32_t LCIVLDR;         /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive
8601                                         *                  Register                                                   */
8602 
8603         struct
8604         {
8605             __OM uint32_t LOAD : 1;    /*!< [0..0] Local Time Counter Initial Value Load Directive                    */
8606             uint32_t           : 31;
8607         } LCIVLDR_b;
8608     };
8609     __IM uint32_t RESERVED5[2];
8610 
8611     union
8612     {
8613         __IOM uint32_t SYNTDARU;          /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers         */
8614 
8615         struct
8616         {
8617             __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
8618                                            *   bits of the threshold for detection of loss of synchronization.           */
8619         } SYNTDARU_b;
8620     };
8621 
8622     union
8623     {
8624         __IOM uint32_t SYNTDARL;          /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers         */
8625 
8626         struct
8627         {
8628             __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
8629                                            *   of the threshold for detection of loss of synchronization.                */
8630         } SYNTDARL_b;
8631     };
8632 
8633     union
8634     {
8635         __IOM uint32_t SYNTDBRU;          /*!< (@ 0x00000098) Synchronization Detection Threshold Registers              */
8636 
8637         struct
8638         {
8639             __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
8640                                            *   bits of the threshold for detection of synchronization.                   */
8641         } SYNTDBRU_b;
8642     };
8643 
8644     union
8645     {
8646         __IOM uint32_t SYNTDBRL;          /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers              */
8647 
8648         struct
8649         {
8650             __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
8651                                            *   of the threshold for detection of synchronization.                        */
8652         } SYNTDBRL_b;
8653     };
8654     __IM uint32_t RESERVED6[4];
8655 
8656     union
8657     {
8658         __IOM uint32_t LCIVRU;          /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers                 */
8659 
8660         struct
8661         {
8662             __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
8663                                          *   bits of the integer portion of the initial value for the
8664                                          *   local timer counter.                                                      */
8665             uint32_t : 16;
8666         } LCIVRU_b;
8667     };
8668 
8669     union
8670     {
8671         __IOM uint32_t LCIVRM;          /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers                 */
8672 
8673         struct
8674         {
8675             __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
8676                                          *   of the integer portion of the initial value for the local
8677                                          *   timer counter.                                                            */
8678         } LCIVRM_b;
8679     };
8680 
8681     union
8682     {
8683         __IOM uint32_t LCIVRL;          /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers                 */
8684 
8685         struct
8686         {
8687             __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion
8688                                          *   of the initial value of the local timer counter in nanoseconds.           */
8689         } LCIVRL_b;
8690     };
8691     __IM uint32_t RESERVED7[26];
8692 
8693     union
8694     {
8695         __IOM uint32_t GETW10R;        /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register                    */
8696 
8697         struct
8698         {
8699             __IOM uint32_t GW10 : 1;   /*!< [0..0] Worst 10 Acquisition Directive                                     */
8700             uint32_t            : 31;
8701         } GETW10R_b;
8702     };
8703 
8704     union
8705     {
8706         __IOM uint32_t PLIMITRU;          /*!< (@ 0x00000128) Positive Gradient Limit Registers                          */
8707 
8708         struct
8709         {
8710             __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
8711                                            *   bits of the limit for the positive gradient.                              */
8712             uint32_t : 1;
8713         } PLIMITRU_b;
8714     };
8715 
8716     union
8717     {
8718         __IOM uint32_t PLIMITRM;          /*!< (@ 0x0000012C) Positive Gradient Limit Registers                          */
8719 
8720         struct
8721         {
8722             __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
8723                                            *   bits of the limit for the positive gradient.                              */
8724         } PLIMITRM_b;
8725     };
8726 
8727     union
8728     {
8729         __IOM uint32_t PLIMITRL;          /*!< (@ 0x00000130) Positive Gradient Limit Registers                          */
8730 
8731         struct
8732         {
8733             __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
8734                                            *   of the limit for the positive gradient.                                   */
8735         } PLIMITRL_b;
8736     };
8737 
8738     union
8739     {
8740         __IOM uint32_t MLIMITRU;          /*!< (@ 0x00000134) Negative Gradient Limit Registers                          */
8741 
8742         struct
8743         {
8744             __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
8745                                            *   bits of the limit for the negative gradient.                              */
8746             uint32_t : 1;
8747         } MLIMITRU_b;
8748     };
8749 
8750     union
8751     {
8752         __IOM uint32_t MLIMITRM;          /*!< (@ 0x00000138) Negative Gradient Limit Registers                          */
8753 
8754         struct
8755         {
8756             __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
8757                                            *   bits of the limit for the negative gradient.                              */
8758         } MLIMITRM_b;
8759     };
8760 
8761     union
8762     {
8763         __IOM uint32_t MLIMITRL;          /*!< (@ 0x0000013C) Negative Gradient Limit Registers                          */
8764 
8765         struct
8766         {
8767             __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
8768                                            *   of the limit for the negative gradient.                                   */
8769         } MLIMITRL_b;
8770     };
8771 
8772     union
8773     {
8774         __IOM uint32_t GETINFOR;       /*!< (@ 0x00000140) Statistical Information Retention Control Register         */
8775 
8776         struct
8777         {
8778             __IOM uint32_t INFO : 1;   /*!< [0..0] Information Retention ControlNOTE: Once information fetching
8779                                         *   is directed, values of various statistical information
8780                                         *   read before completion of information fetching are not
8781                                         *   guaranteed.                                                               */
8782             uint32_t : 31;
8783         } GETINFOR_b;
8784     };
8785     __IM uint32_t RESERVED8[11];
8786 
8787     union
8788     {
8789         __IM uint32_t LCCVRU;          /*!< (@ 0x00000170) Local Time Counters                                        */
8790 
8791         struct
8792         {
8793             __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits
8794                                         *   of the integer portion of the local timer counter's value.                */
8795             uint32_t : 16;
8796         } LCCVRU_b;
8797     };
8798 
8799     union
8800     {
8801         __IM uint32_t LCCVRM;          /*!< (@ 0x00000174) Local Time Counters                                        */
8802 
8803         struct
8804         {
8805             __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
8806                                         *   the integer portion of the local timer counter's value.                   */
8807         } LCCVRM_b;
8808     };
8809 
8810     union
8811     {
8812         __IM uint32_t LCCVRL;          /*!< (@ 0x00000178) Local Time Counters                                        */
8813 
8814         struct
8815         {
8816             __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of
8817                                         *   the local timer counter's value (in nanoseconds).                         */
8818         } LCCVRL_b;
8819     };
8820     __IM uint32_t RESERVED9[37];
8821 
8822     union
8823     {
8824         __IM uint32_t PW10VRU;          /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers                 */
8825 
8826         struct
8827         {
8828             __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
8829                                          *   of the positive gradient value.                                           */
8830         } PW10VRU_b;
8831     };
8832 
8833     union
8834     {
8835         __IM uint32_t PW10VRM;          /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers                 */
8836 
8837         struct
8838         {
8839             __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
8840                                          *   of the positive gradient value.                                           */
8841         } PW10VRM_b;
8842     };
8843 
8844     union
8845     {
8846         __IM uint32_t PW10VRL;          /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers                 */
8847 
8848         struct
8849         {
8850             __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
8851                                          *   the positive gradient value.                                              */
8852         } PW10VRL_b;
8853     };
8854     __IM uint32_t RESERVED10[45];
8855 
8856     union
8857     {
8858         __IM uint32_t MW10RU;          /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers                 */
8859 
8860         struct
8861         {
8862             __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
8863                                         *   of the negative gradient value.                                           */
8864         } MW10RU_b;
8865     };
8866 
8867     union
8868     {
8869         __IM uint32_t MW10RM;          /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers                 */
8870 
8871         struct
8872         {
8873             __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
8874                                         *   of the negative gradient value.                                           */
8875         } MW10RM_b;
8876     };
8877 
8878     union
8879     {
8880         __IM uint32_t MW10RL;                  /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers                 */
8881 
8882         struct
8883         {
8884             __IM uint32_t MW10RL : 32;         /*!< [31..0] These bits are for reading the lower-order 32 bits of
8885                                                 *   the negative gradient value.                                              */
8886         } MW10RL_b;
8887     };
8888     __IM uint32_t RESERVED11[9];
8889     __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers                                    */
8890     __IM uint32_t RESERVED12[7];
8891 
8892     union
8893     {
8894         __IOM uint32_t TMSTARTR;       /*!< (@ 0x0000037C) Timer Start Register                                       */
8895 
8896         struct
8897         {
8898             __IOM uint32_t EN0 : 1;    /*!< [0..0] Pulse Output Timer 0 Start                                         */
8899             __IOM uint32_t EN1 : 1;    /*!< [1..1] Pulse Output Timer 1 Start                                         */
8900             __IOM uint32_t EN2 : 1;    /*!< [2..2] Pulse Output Timer 2 Start                                         */
8901             __IOM uint32_t EN3 : 1;    /*!< [3..3] Pulse Output Timer 3 Start                                         */
8902             __IOM uint32_t EN4 : 1;    /*!< [4..4] Pulse Output Timer 4 Start                                         */
8903             __IOM uint32_t EN5 : 1;    /*!< [5..5] Pulse Output Timer 5 Start                                         */
8904             uint32_t           : 26;
8905         } TMSTARTR_b;
8906     };
8907     __IM uint32_t RESERVED13[32];
8908 
8909     union
8910     {
8911         __IOM uint32_t PRSR;           /*!< (@ 0x00000400) PRC-TC Status Register                                     */
8912 
8913         struct
8914         {
8915             __IOM uint32_t OVRE0 : 1;  /*!< [0..0] Relay Packet Overflow Detection Flag 0                             */
8916             __IOM uint32_t OVRE1 : 1;  /*!< [1..1] Relay Packet Overflow Detection Flag 1                             */
8917             __IOM uint32_t OVRE2 : 1;  /*!< [2..2] Relay Packet Overflow Detection Flag 2                             */
8918             __IOM uint32_t OVRE3 : 1;  /*!< [3..3] Relay Packet Overflow Detection Flag 3                             */
8919             uint32_t             : 4;
8920             __IOM uint32_t MACE  : 1;  /*!< [8..8] Originating MAC Address Mismatch Detection Flag                    */
8921             uint32_t             : 19;
8922             __IOM uint32_t URE0  : 1;  /*!< [28..28] Relay Packet Underflow Detection Flag 0                          */
8923             __IOM uint32_t URE1  : 1;  /*!< [29..29] Relay Packet Underflow Detection Flag 1                          */
8924             uint32_t             : 2;
8925         } PRSR_b;
8926     };
8927 
8928     union
8929     {
8930         __IOM uint32_t PRIPR;          /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register             */
8931 
8932         struct
8933         {
8934             __IOM uint32_t OVRE0 : 1;  /*!< [0..0] PRSR.OVRE0 Status Notification Permission                          */
8935             __IOM uint32_t OVRE1 : 1;  /*!< [1..1] PRSR.OVRE1 Status Notification Permission                          */
8936             __IOM uint32_t OVRE2 : 1;  /*!< [2..2] PRSR.OVRE2 Status Notification Permission                          */
8937             __IOM uint32_t OVRE3 : 1;  /*!< [3..3] PRSR.OVRE3 Status Notification Permission                          */
8938             uint32_t             : 4;
8939             __IOM uint32_t MACE  : 1;  /*!< [8..8] PRSR.MACE Status Notification Permission                           */
8940             uint32_t             : 19;
8941             __IOM uint32_t URE0  : 1;  /*!< [28..28] PRSR.URE0 Status Notification Permission                         */
8942             __IOM uint32_t URE1  : 1;  /*!< [29..29] PRSR.URE1 Status Notification Permission                         */
8943             uint32_t             : 2;
8944         } PRIPR_b;
8945     };
8946     __IM uint32_t RESERVED14[2];
8947     __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers                                */
8948 
8949     union
8950     {
8951         __IOM uint32_t TRNDISR;                /*!< (@ 0x00000420) Packet Transmission Control Register                       */
8952 
8953         struct
8954         {
8955             __IOM uint32_t TDIS : 2;           /*!< [1..0] Packet Transmission Control                                        */
8956             uint32_t            : 30;
8957         } TRNDISR_b;
8958     };
8959     __IM uint32_t RESERVED15[3];
8960 
8961     union
8962     {
8963         __IOM uint32_t TRNMR;          /*!< (@ 0x00000430) Relay Mode Register                                        */
8964 
8965         struct
8966         {
8967             __IOM uint32_t MOD  : 1;   /*!< [0..0] Cut-Through Mode                                                   */
8968             uint32_t            : 7;
8969             __IOM uint32_t FWD0 : 1;   /*!< [8..8] Channel 0 Relay Enable                                             */
8970             __IOM uint32_t FWD1 : 1;   /*!< [9..9] Channel 1 Relay Enable                                             */
8971             uint32_t            : 22;
8972         } TRNMR_b;
8973     };
8974 
8975     union
8976     {
8977         __IOM uint32_t TRNCTTDR;       /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register              */
8978 
8979         struct
8980         {
8981             __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read
8982                                         *   data from the relay FIFO in cut-through mode (specified
8983                                         *   as the number of bytes)NOTE1: A value cannot be set in
8984                                         *   the lower-order 2 bits. These bits are fixed to 0.NOTE2:
8985                                         *   A value of less than 96 bytes cannot be set.                              */
8986             uint32_t : 21;
8987         } TRNCTTDR_b;
8988     };
8989 } R_ETHERC_EPTPC_COMMON_Type;          /*!< Size = 1080 (0x438)                                                       */
8990 
8991 /* =========================================================================================================================== */
8992 /* ================                                       R_FACI_HP_CMD                                       ================ */
8993 /* =========================================================================================================================== */
8994 
8995 /**
8996  * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
8997  */
8998 
8999 typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
9000 {
9001     union
9002     {
9003         __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
9004         __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
9005     };
9006 } R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
9007 
9008 /* =========================================================================================================================== */
9009 /* ================                                         R_FACI_HP                                         ================ */
9010 /* =========================================================================================================================== */
9011 
9012 /**
9013  * @brief Flash Application Command Interface (R_FACI_HP)
9014  */
9015 
9016 typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
9017 {
9018     __IM uint32_t RESERVED[4];
9019 
9020     union
9021     {
9022         __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
9023 
9024         struct
9025         {
9026             uint8_t             : 3;
9027             __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
9028             __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
9029             uint8_t             : 2;
9030             __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
9031         } FASTAT_b;
9032     };
9033     __IM uint8_t  RESERVED1;
9034     __IM uint16_t RESERVED2;
9035 
9036     union
9037     {
9038         __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
9039 
9040         struct
9041         {
9042             uint8_t               : 3;
9043             __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
9044             __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
9045             uint8_t               : 2;
9046             __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
9047         } FAEINT_b;
9048     };
9049     __IM uint8_t  RESERVED3;
9050     __IM uint16_t RESERVED4;
9051 
9052     union
9053     {
9054         __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
9055 
9056         struct
9057         {
9058             __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
9059             uint8_t              : 7;
9060         } FRDYIE_b;
9061     };
9062     __IM uint8_t  RESERVED5;
9063     __IM uint16_t RESERVED6;
9064     __IM uint32_t RESERVED7[5];
9065 
9066     union
9067     {
9068         __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
9069 
9070         struct
9071         {
9072             __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
9073                                         *   These bits can be written when FRDY bit of FSTATR register
9074                                         *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
9075         } FSADDR_b;
9076     };
9077 
9078     union
9079     {
9080         __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
9081 
9082         struct
9083         {
9084             __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
9085                                         *   end address of target area in 'Blank Check' command. These
9086                                         *   bits can be written when FRDY bit of FSTATR register is
9087                                         *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
9088         } FEADDR_b;
9089     };
9090     __IM uint32_t RESERVED8[3];
9091 
9092     union
9093     {
9094         __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
9095 
9096         struct
9097         {
9098             __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
9099                                         *   is only possible when the FRDY bit in the FSTATR register
9100                                         *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
9101                                         *   to this bit is only possible when 16 bits are written and
9102                                         *   the value written to the KEY bits is D9h.Written values
9103                                         *   are not retained by these bits (always read as 0x00).Only
9104                                         *   secure access can write to this register. Both secure access
9105                                         *   and non-secure read access are allowed. Non-secure writeaccess
9106                                         *   is denied, but TrustZo                                                    */
9107             uint16_t          : 7;
9108             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
9109         } FMEPROT_b;
9110     };
9111     __IM uint16_t RESERVED9;
9112     __IM uint32_t RESERVED10[12];
9113 
9114     union
9115     {
9116         __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
9117 
9118         struct
9119         {
9120             __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
9121                                         *   written when the FRDY bit in the FSTATR register is 1.
9122                                         *   Writing to this bit is ignored when the FRDY bit is 0.Writing
9123                                         *   to this bit is only possible when 16 bits are written and
9124                                         *   the value written to the KEY[7:0] bits is 0x78.Written
9125                                         *   values are not retained by these bits (always read as 0x00).              */
9126             uint16_t          : 7;
9127             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
9128         } FBPROT0_b;
9129     };
9130     __IM uint16_t RESERVED11;
9131 
9132     union
9133     {
9134         __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
9135 
9136         struct
9137         {
9138             __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
9139                                         *   is only possible when the FRDY bit in the FSTATR register
9140                                         *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
9141                                         *   to this bit is only possible when 16 bits are written and
9142                                         *   the value written to the KEY[7:0] bits is 0xB1.Written
9143                                         *   values are not retained by these bits (always read as 0x00).              */
9144             uint16_t          : 7;
9145             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
9146         } FBPROT1_b;
9147     };
9148     __IM uint16_t RESERVED12;
9149 
9150     union
9151     {
9152         __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
9153 
9154         struct
9155         {
9156             uint32_t                 : 6;
9157             __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
9158             uint32_t                 : 1;
9159             __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
9160             __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
9161             __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
9162             __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
9163             __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
9164             __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
9165             __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
9166             __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
9167             uint32_t                 : 4;
9168             __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
9169             __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
9170             __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
9171             __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
9172             uint32_t                 : 8;
9173         } FSTATR_b;
9174     };
9175 
9176     union
9177     {
9178         __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
9179 
9180         struct
9181         {
9182             __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
9183                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
9184                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
9185                                          *   only when this register is accessed in 16-bit size and
9186                                          *   H'AA is written to KEY bits                                               */
9187             uint16_t               : 6;
9188             __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
9189                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
9190                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
9191                                          *   only when this register is accessed in 16-bit size and
9192                                          *   H'AA is written to KEY bits.                                              */
9193             __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
9194         } FENTRYR_b;
9195     };
9196     __IM uint16_t RESERVED13;
9197     __IM uint32_t RESERVED14;
9198 
9199     union
9200     {
9201         __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
9202 
9203         struct
9204         {
9205             __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
9206                                         *   bit of FSTATR register is '1'. Writing to this bit in FRDY
9207                                         *   = '0' is ignored. Writing to these bits is enabled only
9208                                         *   when this register is accessed in 16-bit size and H'2D
9209                                         *   is written to KEY bits.                                                   */
9210             uint16_t          : 7;
9211             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
9212         } FSUINITR_b;
9213     };
9214     __IM uint16_t RESERVED15;
9215     __IM uint32_t RESERVED16[4];
9216 
9217     union
9218     {
9219         __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
9220 
9221         struct
9222         {
9223             __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
9224             __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
9225         } FCMDR_b;
9226     };
9227     __IM uint16_t RESERVED17;
9228     __IM uint32_t RESERVED18[11];
9229 
9230     union
9231     {
9232         __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
9233 
9234         struct
9235         {
9236             __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
9237             uint8_t             : 7;
9238         } FBCCNT_b;
9239     };
9240     __IM uint8_t  RESERVED19;
9241     __IM uint16_t RESERVED20;
9242 
9243     union
9244     {
9245         __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
9246 
9247         struct
9248         {
9249             __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
9250             uint8_t           : 7;
9251         } FBCSTAT_b;
9252     };
9253     __IM uint8_t  RESERVED21;
9254     __IM uint16_t RESERVED22;
9255 
9256     union
9257     {
9258         __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
9259 
9260         struct
9261         {
9262             __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
9263                                         *   of the first programmed data which is found in 'Blank Check'
9264                                         *   command execution.                                                        */
9265             uint32_t : 13;
9266         } FPSADDR_b;
9267     };
9268 
9269     union
9270     {
9271         __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
9272 
9273         struct
9274         {
9275             __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
9276                                         *   indicate the start sector address for setting the access
9277                                         *   window that is located in the configuration area.                         */
9278             uint32_t           : 4;
9279             __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
9280                                         *   Flag and Temporary Boot Swap Control and 'Config Clear'
9281                                         *   command execution                                                         */
9282             __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
9283                                         *   indicate the end sector address for setting the access
9284                                         *   window that is located in the configuration area.                         */
9285             uint32_t            : 4;
9286             __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
9287         } FAWMON_b;
9288     };
9289 
9290     union
9291     {
9292         __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
9293 
9294         struct
9295         {
9296             __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
9297             uint16_t               : 15;
9298         } FCPSR_b;
9299     };
9300     __IM uint16_t RESERVED23;
9301 
9302     union
9303     {
9304         __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
9305 
9306         struct
9307         {
9308             __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
9309                                         *   can be written when FRDY bit in FSTATR register is '1'.
9310                                         *   Writing to this bit in FRDY = '0' is ignored. Writing to
9311                                         *   these bits is enabled only when this register is accessed
9312                                         *   in 16-bit size and H'1E is written to KEY bits.                           */
9313             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
9314         } FPCKAR_b;
9315     };
9316     __IM uint16_t RESERVED24;
9317 
9318     union
9319     {
9320         __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
9321 
9322         struct
9323         {
9324             __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
9325                                         *   bit in FSTATR register is '1'. Writing to this bit in FRDY
9326                                         *   = '0' is ignored. Writing to these bits is enabled only
9327                                         *   when this register is accessed in 16-bit size and H'66
9328                                         *   is written to KEY bits.                                                   */
9329             uint16_t          : 6;
9330             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
9331         } FSUACR_b;
9332     };
9333     __IM uint16_t RESERVED25;
9334 } R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
9335 
9336 /* =========================================================================================================================== */
9337 /* ================                                         R_FCACHE                                          ================ */
9338 /* =========================================================================================================================== */
9339 
9340 /**
9341  * @brief Flash Memory Cache (R_FCACHE)
9342  */
9343 
9344 typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
9345 {
9346     __IM uint16_t RESERVED[128];
9347 
9348     union
9349     {
9350         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
9351 
9352         struct
9353         {
9354             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
9355             uint16_t                : 15;
9356         } FCACHEE_b;
9357     };
9358     __IM uint16_t RESERVED1;
9359 
9360     union
9361     {
9362         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
9363 
9364         struct
9365         {
9366             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
9367             uint16_t                : 15;
9368         } FCACHEIV_b;
9369     };
9370     __IM uint16_t RESERVED2[11];
9371 
9372     union
9373     {
9374         __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
9375 
9376         struct
9377         {
9378             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
9379             uint8_t            : 5;
9380         } FLWT_b;
9381     };
9382     __IM uint8_t  RESERVED3;
9383     __IM uint16_t RESERVED4[17];
9384 
9385     union
9386     {
9387         __IOM uint16_t FSAR;             /*!< (@ 0x00000140) Flash Security Attribution Register                        */
9388 
9389         struct
9390         {
9391             __IOM uint16_t FLWTSA   : 1; /*!< [0..0] FLWT Security Attribution                                          */
9392             uint16_t                : 7;
9393             __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
9394             uint16_t                : 7;
9395         } FSAR_b;
9396     };
9397 } R_FCACHE_Type;                         /*!< Size = 322 (0x142)                                                        */
9398 
9399 /* =========================================================================================================================== */
9400 /* ================                                          R_GLCDC                                          ================ */
9401 /* =========================================================================================================================== */
9402 
9403 /**
9404  * @brief Graphics LCD Controller (R_GLCDC)
9405  */
9406 
9407 typedef struct                         /*!< (@ 0x400E0000) R_GLCDC Structure                                          */
9408 {
9409     union
9410     {
9411         __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane                 */
9412 
9413         struct
9414         {
9415             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
9416             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
9417             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
9418             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
9419                                         *   m Plane                                                                   */
9420         } GR1_CLUT0_b[256];
9421     };
9422 
9423     union
9424     {
9425         __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane                 */
9426 
9427         struct
9428         {
9429             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
9430             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
9431             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
9432             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
9433                                         *   m Plane                                                                   */
9434         } GR1_CLUT1_b[256];
9435     };
9436 
9437     union
9438     {
9439         __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane                 */
9440 
9441         struct
9442         {
9443             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
9444             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
9445             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
9446             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
9447                                         *   m Plane                                                                   */
9448         } GR2_CLUT0_b[256];
9449     };
9450 
9451     union
9452     {
9453         __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane                 */
9454 
9455         struct
9456         {
9457             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
9458             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
9459             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
9460             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
9461                                         *   m Plane                                                                   */
9462         } GR2_CLUT1_b[256];
9463     };
9464     __IOM R_GLCDC_BG_Type     BG;      /*!< (@ 0x00001000) Background Registers                                       */
9465     __IM uint32_t             RESERVED[57];
9466     __IOM R_GLCDC_GR_Type     GR[2];   /*!< (@ 0x00001100) Layer Registers                                            */
9467     __IOM R_GLCDC_GAM_Type    GAM[3];  /*!< (@ 0x00001300) Gamma Settings                                             */
9468     __IOM R_GLCDC_OUT_Type    OUT;     /*!< (@ 0x000013C0) Output Control Registers                                   */
9469     __IM uint32_t             RESERVED1[6];
9470     __IOM R_GLCDC_TCON_Type   TCON;    /*!< (@ 0x00001400) Timing Control Registers                                   */
9471     __IM uint32_t             RESERVED2[5];
9472     __IOM R_GLCDC_SYSCNT_Type SYSCNT;  /*!< (@ 0x00001440) GLCDC System Control Registers                             */
9473 } R_GLCDC_Type;                        /*!< Size = 5204 (0x1454)                                                      */
9474 
9475 /* =========================================================================================================================== */
9476 /* ================                                          R_GPT0                                           ================ */
9477 /* =========================================================================================================================== */
9478 
9479 /**
9480  * @brief General PWM Timer (R_GPT0)
9481  */
9482 
9483 typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure                                           */
9484 {
9485     union
9486     {
9487         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
9488 
9489         struct
9490         {
9491             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
9492             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
9493             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
9494             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
9495             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
9496             uint32_t             : 3;
9497             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
9498             uint32_t             : 16;
9499         } GTWP_b;
9500     };
9501 
9502     union
9503     {
9504         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
9505 
9506         struct
9507         {
9508             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
9509                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9510                                          *   means counter running.                                                    */
9511             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
9512                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9513                                          *   means counter running.                                                    */
9514             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
9515                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9516                                          *   means counter running.                                                    */
9517             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
9518                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9519                                          *   means counter running.                                                    */
9520             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
9521                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9522                                          *   means counter running.                                                    */
9523             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
9524                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9525                                          *   means counter running.                                                    */
9526             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
9527                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9528                                          *   means counter running.                                                    */
9529             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
9530                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9531                                          *   means counter running.                                                    */
9532             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
9533                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9534                                          *   means counter running.                                                    */
9535             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
9536                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9537                                          *   means counter running.                                                    */
9538             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
9539                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9540                                          *   means counter running.                                                    */
9541             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
9542                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9543                                          *   means counter running.                                                    */
9544             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
9545                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9546                                          *   means counter running.                                                    */
9547             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
9548                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9549                                          *   means counter running.                                                    */
9550             __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
9551                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9552                                          *   means counter running.                                                    */
9553             __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
9554                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9555                                          *   means counter running.                                                    */
9556             __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
9557                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9558                                          *   means counter running.                                                    */
9559             __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
9560                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9561                                          *   means counter running.                                                    */
9562             __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
9563                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9564                                          *   means counter running.                                                    */
9565             __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
9566                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9567                                          *   means counter running.                                                    */
9568             __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
9569                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9570                                          *   means counter running.                                                    */
9571             __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
9572                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9573                                          *   means counter running.                                                    */
9574             __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
9575                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9576                                          *   means counter running.                                                    */
9577             __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
9578                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9579                                          *   means counter running.                                                    */
9580             __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
9581                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9582                                          *   means counter running.                                                    */
9583             __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
9584                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9585                                          *   means counter running.                                                    */
9586             __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
9587                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9588                                          *   means counter running.                                                    */
9589             __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
9590                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9591                                          *   means counter running.                                                    */
9592             __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
9593                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9594                                          *   means counter running.                                                    */
9595             __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
9596                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9597                                          *   means counter running.                                                    */
9598             __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
9599                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9600                                          *   means counter running.                                                    */
9601             __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
9602                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
9603                                          *   means counter running.                                                    */
9604         } GTSTR_b;
9605     };
9606 
9607     union
9608     {
9609         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
9610 
9611         struct
9612         {
9613             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
9614                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9615                                          *   1 means counter stop.                                                     */
9616             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
9617                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9618                                          *   1 means counter stop.                                                     */
9619             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
9620                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9621                                          *   1 means counter stop.                                                     */
9622             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
9623                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9624                                          *   1 means counter stop.                                                     */
9625             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
9626                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9627                                          *   1 means counter stop.                                                     */
9628             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
9629                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9630                                          *   1 means counter stop.                                                     */
9631             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
9632                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9633                                          *   1 means counter stop.                                                     */
9634             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
9635                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9636                                          *   1 means counter stop.                                                     */
9637             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
9638                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9639                                          *   1 means counter stop.                                                     */
9640             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
9641                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9642                                          *   1 means counter stop.                                                     */
9643             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
9644                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9645                                          *   1 means counter stop.                                                     */
9646             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
9647                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9648                                          *   1 means counter stop.                                                     */
9649             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
9650                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9651                                          *   1 means counter stop.                                                     */
9652             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
9653                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9654                                          *   1 means counter stop.                                                     */
9655             __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
9656                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9657                                          *   1 means counter stop.                                                     */
9658             __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
9659                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9660                                          *   1 means counter stop.                                                     */
9661             __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
9662                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9663                                          *   1 means counter stop.                                                     */
9664             __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
9665                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9666                                          *   1 means counter stop.                                                     */
9667             __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
9668                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9669                                          *   1 means counter stop.                                                     */
9670             __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
9671                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9672                                          *   1 means counter stop.                                                     */
9673             __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
9674                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9675                                          *   1 means counter stop.                                                     */
9676             __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
9677                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9678                                          *   1 means counter stop.                                                     */
9679             __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
9680                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9681                                          *   1 means counter stop.                                                     */
9682             __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
9683                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9684                                          *   1 means counter stop.                                                     */
9685             __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
9686                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9687                                          *   1 means counter stop.                                                     */
9688             __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
9689                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9690                                          *   1 means counter stop.                                                     */
9691             __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
9692                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9693                                          *   1 means counter stop.                                                     */
9694             __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
9695                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9696                                          *   1 means counter stop.                                                     */
9697             __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
9698                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9699                                          *   1 means counter stop.                                                     */
9700             __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
9701                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9702                                          *   1 means counter stop.                                                     */
9703             __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
9704                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9705                                          *   1 means counter stop.                                                     */
9706             __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
9707                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9708                                          *   1 means counter stop.                                                     */
9709         } GTSTP_b;
9710     };
9711 
9712     union
9713     {
9714         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
9715 
9716         struct
9717         {
9718             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
9719             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
9720             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
9721             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
9722             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
9723             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
9724             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
9725             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
9726             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
9727             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
9728             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
9729             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
9730             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
9731             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
9732             __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
9733             __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
9734             __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
9735             __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
9736             __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
9737             __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
9738             __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
9739             __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
9740             __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
9741             __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
9742             __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
9743             __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
9744             __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
9745             __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
9746             __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
9747             __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
9748             __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
9749             __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
9750         } GTCLR_b;
9751     };
9752 
9753     union
9754     {
9755         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
9756 
9757         struct
9758         {
9759             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
9760             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
9761             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
9762             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
9763             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
9764             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
9765             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
9766             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
9767             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9768                                           *   Counter Start Enable                                                      */
9769             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9770                                           *   Counter Start Enable                                                      */
9771             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9772                                           *   Counter Start Enable                                                      */
9773             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9774                                           *   Counter Start Enable                                                      */
9775             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9776                                           *   Counter Start Enable                                                      */
9777             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9778                                           *   Counter Start Enable                                                      */
9779             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9780                                           *   Counter Start Enable                                                      */
9781             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9782                                           *   Counter Start Enable                                                      */
9783             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
9784             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
9785             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
9786             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
9787             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
9788             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
9789             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
9790             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
9791             uint32_t              : 7;
9792             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
9793         } GTSSR_b;
9794     };
9795 
9796     union
9797     {
9798         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
9799 
9800         struct
9801         {
9802             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9803             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
9804             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9805             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
9806             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9807             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
9808             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9809             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
9810             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9811                                           *   Counter Stop Enable                                                       */
9812             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9813                                           *   Counter Stop Enable                                                       */
9814             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9815                                           *   Counter Stop Enable                                                       */
9816             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9817                                           *   Counter Stop Enable                                                       */
9818             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9819                                           *   Counter Stop Enable                                                       */
9820             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9821                                           *   Counter Stop Enable                                                       */
9822             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9823                                           *   Counter Stop Enable                                                       */
9824             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9825                                           *   Counter Stop Enable                                                       */
9826             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
9827             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
9828             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
9829             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
9830             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
9831             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
9832             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
9833             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
9834             uint32_t              : 7;
9835             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
9836         } GTPSR_b;
9837     };
9838 
9839     union
9840     {
9841         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
9842 
9843         struct
9844         {
9845             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
9846             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
9847             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
9848             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
9849             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
9850             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
9851             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
9852             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
9853             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9854                                           *   Counter Clear Enable                                                      */
9855             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9856                                           *   Counter Clear Enable                                                      */
9857             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9858                                           *   Counter Clear Enable                                                      */
9859             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9860                                           *   Counter Clear Enable                                                      */
9861             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9862                                           *   Counter Clear Enable                                                      */
9863             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9864                                           *   Counter Clear Enable                                                      */
9865             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9866                                           *   Counter Clear Enable                                                      */
9867             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9868                                           *   Counter Clear Enable                                                      */
9869             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
9870             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
9871             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
9872             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
9873             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
9874             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
9875             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
9876             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
9877             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
9878                                           *   Source Counter Clear Enable.                                              */
9879             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
9880                                           *   Enable (This bit is only available in GPT324 to GPT329.
9881                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
9882                                           *   should be 0.)                                                             */
9883             uint32_t            : 3;
9884             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
9885         } GTCSR_b;
9886     };
9887 
9888     union
9889     {
9890         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
9891 
9892         struct
9893         {
9894             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9895             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9896             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9897             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9898             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9899             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9900             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9901             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9902             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9903                                           *   Counter Count Up Enable                                                   */
9904             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9905                                           *   Counter Count Up Enable                                                   */
9906             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9907                                           *   Counter Count Up Enable                                                   */
9908             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9909                                           *   Counter Count Up Enable                                                   */
9910             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9911                                           *   Counter Count Up Enable                                                   */
9912             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9913                                           *   Counter Count Up Enable                                                   */
9914             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9915                                           *   Counter Count Up Enable                                                   */
9916             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9917                                           *   Counter Count Up Enable                                                   */
9918             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
9919             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
9920             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
9921             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
9922             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
9923             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
9924             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
9925             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
9926             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
9927             uint32_t              : 4;
9928         } GTUPSR_b;
9929     };
9930 
9931     union
9932     {
9933         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
9934 
9935         struct
9936         {
9937             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9938             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9939             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9940             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9941             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9942             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9943             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9944             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9945             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9946                                           *   Counter Count Down Enable                                                 */
9947             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9948                                           *   Counter Count Down Enable                                                 */
9949             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9950                                           *   Counter Count Down Enable                                                 */
9951             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9952                                           *   Counter Count Down Enable                                                 */
9953             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9954                                           *   Counter Count Down Enable                                                 */
9955             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9956                                           *   Counter Count Down Enable                                                 */
9957             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9958                                           *   Counter Count Down Enable                                                 */
9959             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9960                                           *   Counter Count Down Enable                                                 */
9961             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
9962             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
9963             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
9964             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
9965             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
9966             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
9967             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
9968             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
9969             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
9970             uint32_t              : 4;
9971         } GTDNSR_b;
9972     };
9973 
9974     union
9975     {
9976         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
9977                                           *                  Register A                                                 */
9978 
9979         struct
9980         {
9981             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9982             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
9983                                           *   Enable                                                                    */
9984             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9985             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
9986                                           *   Enable                                                                    */
9987             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9988             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
9989                                           *   Enable                                                                    */
9990             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9991             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
9992                                           *   Enable                                                                    */
9993             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9994                                           *   GTCCRA Input Capture Enable                                               */
9995             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9996                                           *   GTCCRA Input Capture Enable                                               */
9997             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9998                                           *   GTCCRA Input Capture Enable                                               */
9999             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
10000                                           *   GTCCRA Input Capture Enable                                               */
10001             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
10002                                           *   GTCCRA Input Capture Enable                                               */
10003             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
10004                                           *   GTCCRA Input Capture Enable                                               */
10005             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
10006                                           *   GTCCRA Input Capture Enable                                               */
10007             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
10008                                           *   GTCCRA Input Capture Enable                                               */
10009             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10010             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10011             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10012             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10013             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10014             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10015             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10016             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
10017             uint32_t              : 8;
10018         } GTICASR_b;
10019     };
10020 
10021     union
10022     {
10023         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
10024                                           *                  Register B                                                 */
10025 
10026         struct
10027         {
10028             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
10029             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
10030                                           *   Enable                                                                    */
10031             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
10032             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
10033                                           *   Enable                                                                    */
10034             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
10035             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
10036                                           *   Enable                                                                    */
10037             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
10038             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
10039                                           *   Enable                                                                    */
10040             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
10041                                           *   GTCCRB Input Capture Enable                                               */
10042             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
10043                                           *   GTCCRB Input Capture Enable                                               */
10044             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
10045                                           *   GTCCRB Input Capture Enable                                               */
10046             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
10047                                           *   GTCCRB Input Capture Enable                                               */
10048             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
10049                                           *   GTCCRB Input Capture Enable                                               */
10050             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
10051                                           *   GTCCRB Input Capture Enable                                               */
10052             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
10053                                           *   GTCCRB Input Capture Enable                                               */
10054             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
10055                                           *   GTCCRB Input Capture Enable                                               */
10056             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10057             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10058             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10059             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10060             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10061             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10062             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10063             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
10064             uint32_t              : 8;
10065         } GTICBSR_b;
10066     };
10067 
10068     union
10069     {
10070         __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
10071 
10072         struct
10073         {
10074             __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
10075             uint32_t               : 7;
10076             __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
10077             __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
10078             __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
10079             __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
10080             uint32_t               : 2;
10081             __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
10082             __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
10083             uint32_t               : 4;
10084             __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
10085             __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
10086             uint32_t               : 3;
10087         } GTCR_b;
10088     };
10089 
10090     union
10091     {
10092         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
10093                                         *                  Register                                                   */
10094 
10095         struct
10096         {
10097             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
10098             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
10099             uint32_t              : 14;
10100             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
10101             __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
10102             __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
10103                                         *   percent Duty Setting                                                      */
10104             uint32_t              : 4;
10105             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
10106             __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
10107             __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
10108                                         *   percent Duty Setting                                                      */
10109             uint32_t : 4;
10110         } GTUDDTYC_b;
10111     };
10112 
10113     union
10114     {
10115         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
10116 
10117         struct
10118         {
10119             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
10120             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
10121                                         *   Clear Disable.(This bit is only available in GPT324 to
10122                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
10123                                         *   write value should be 0.)                                                 */
10124             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
10125             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
10126             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
10127             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
10128             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
10129                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
10130                                         *   GPT323, this bit is read as 0. The write value should be
10131                                         *   0.)                                                                       */
10132             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
10133             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
10134             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
10135             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
10136             uint32_t              : 1;
10137             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
10138             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
10139             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
10140             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
10141             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
10142                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
10143                                         *   GPT323, this bit is read as 0. The write value should be
10144                                         *   0.)                                                                       */
10145             uint32_t             : 1;
10146             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
10147             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
10148         } GTIOR_b;
10149     };
10150 
10151     union
10152     {
10153         __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
10154 
10155         struct
10156         {
10157             uint32_t            : 8;
10158             __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
10159                                           *   Clear Enable                                                              */
10160             __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
10161                                           *   Clear Enable                                                              */
10162             __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
10163                                           *   Synchronous Clear Enable                                                  */
10164             __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
10165                                           *   Synchronous Clear Enable                                                  */
10166             __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
10167                                           *   Synchronous Clear Enable                                                  */
10168             __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
10169                                           *   Synchronous Clear Enable                                                  */
10170             __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
10171             __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
10172             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
10173                                           *   Start Request Enable                                                      */
10174             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
10175                                           *   Conversion Start Request Enable                                           */
10176             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
10177                                           *   Start Request Enable                                                      */
10178             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
10179                                           *   Conversion Start Request Enable                                           */
10180             uint32_t               : 4;
10181             __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
10182             uint32_t               : 2;
10183             __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
10184             __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
10185             __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
10186             __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
10187         } GTINTAD_b;
10188     };
10189 
10190     union
10191     {
10192         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
10193 
10194         struct
10195         {
10196             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
10197             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
10198             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
10199             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
10200             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
10201             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
10202             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
10203             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
10204             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
10205                                          *   for counting the number of times a timer interrupt has
10206                                          *   been skipped.)                                                            */
10207             uint32_t               : 4;
10208             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
10209             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
10210                                          *   Request Interrupt Enable                                                  */
10211             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
10212                                          *   Start Request Flag                                                        */
10213             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
10214                                          *   Request Flag                                                              */
10215             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
10216                                          *   Start Request Flag                                                        */
10217             uint32_t             : 4;
10218             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
10219             uint32_t             : 3;
10220             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
10221             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
10222             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
10223             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
10224         } GTST_b;
10225     };
10226 
10227     union
10228     {
10229         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
10230 
10231         struct
10232         {
10233             __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
10234             __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
10235             __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
10236             __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
10237             uint32_t               : 4;
10238             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
10239             uint32_t               : 1;
10240             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
10241             uint32_t               : 5;
10242             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
10243             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
10244             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
10245             __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
10246                                          *   is read as 0.                                                             */
10247             uint32_t             : 1;
10248             __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
10249                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
10250                                          *   at an underflow (in down-counting) or overflow (in up-counting)
10251                                          *   is performed.                                                             */
10252             __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
10253             uint32_t             : 1;
10254             __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
10255                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
10256                                          *   at an underflow (in down-counting) or overflow (in up-counting)
10257                                          *   is performed.                                                             */
10258             __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
10259             uint32_t             : 1;
10260         } GTBER_b;
10261     };
10262 
10263     union
10264     {
10265         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
10266                                         *                  Start Request Skipping Setting Register                    */
10267 
10268         struct
10269         {
10270             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
10271             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
10272             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
10273             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
10274             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
10275             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
10276             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
10277             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
10278             uint32_t             : 1;
10279             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
10280             uint32_t             : 1;
10281             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
10282             uint32_t             : 17;
10283         } GTITC_b;
10284     };
10285 
10286     union
10287     {
10288         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
10289 
10290         struct
10291         {
10292             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
10293         } GTCNT_b;
10294     };
10295 
10296     union
10297     {
10298         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
10299 
10300         struct
10301         {
10302             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
10303         } GTCCR_b[6];
10304     };
10305 
10306     union
10307     {
10308         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
10309 
10310         struct
10311         {
10312             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
10313         } GTPR_b;
10314     };
10315 
10316     union
10317     {
10318         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
10319 
10320         struct
10321         {
10322             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
10323         } GTPBR_b;
10324     };
10325 
10326     union
10327     {
10328         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
10329                                          *                  Register                                                   */
10330 
10331         struct
10332         {
10333             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
10334         } GTPDBR_b;
10335     };
10336 
10337     union
10338     {
10339         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
10340 
10341         struct
10342         {
10343             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
10344         } GTADTRA_b;
10345     };
10346 
10347     union
10348     {
10349         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
10350                                            *                  A                                                          */
10351 
10352         struct
10353         {
10354             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
10355         } GTADTBRA_b;
10356     };
10357 
10358     union
10359     {
10360         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
10361                                             *                  Register A                                                 */
10362 
10363         struct
10364         {
10365             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
10366                                             *   A                                                                         */
10367         } GTADTDBRA_b;
10368     };
10369 
10370     union
10371     {
10372         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
10373 
10374         struct
10375         {
10376             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
10377         } GTADTRB_b;
10378     };
10379 
10380     union
10381     {
10382         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
10383                                            *                  B                                                          */
10384 
10385         struct
10386         {
10387             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
10388         } GTADTBRB_b;
10389     };
10390 
10391     union
10392     {
10393         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
10394                                             *                  Register B                                                 */
10395 
10396         struct
10397         {
10398             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
10399                                             *   B                                                                         */
10400         } GTADTDBRB_b;
10401     };
10402 
10403     union
10404     {
10405         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
10406 
10407         struct
10408         {
10409             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
10410             uint32_t             : 3;
10411             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
10412             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
10413             uint32_t             : 2;
10414             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
10415             uint32_t             : 23;
10416         } GTDTCR_b;
10417     };
10418 
10419     union
10420     {
10421         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
10422 
10423         struct
10424         {
10425             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
10426         } GTDVU_b;
10427     };
10428 
10429     union
10430     {
10431         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
10432 
10433         struct
10434         {
10435             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
10436         } GTDVD_b;
10437     };
10438 
10439     union
10440     {
10441         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
10442 
10443         struct
10444         {
10445             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
10446         } GTDBU_b;
10447     };
10448 
10449     union
10450     {
10451         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
10452 
10453         struct
10454         {
10455             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
10456         } GTDBD_b;
10457     };
10458 
10459     union
10460     {
10461         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
10462                                         *                  Status Register                                            */
10463 
10464         struct
10465         {
10466             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
10467             uint32_t          : 30;
10468         } GTSOS_b;
10469     };
10470 
10471     union
10472     {
10473         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
10474                                         *                  Temporary Release Register                                 */
10475 
10476         struct
10477         {
10478             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
10479             uint32_t            : 31;
10480         } GTSOTR_b;
10481     };
10482 
10483     union
10484     {
10485         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
10486                                          *                  Signal Monitoring Register                                 */
10487 
10488         struct
10489         {
10490             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
10491             uint32_t               : 6;
10492             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
10493                                          *   Enabling                                                                  */
10494             uint32_t               : 7;
10495             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
10496             uint32_t               : 6;
10497             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
10498                                          *   Enabling                                                                  */
10499             uint32_t : 7;
10500         } GTADSMR_b;
10501     };
10502 
10503     union
10504     {
10505         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
10506                                            *                  Counter Control Register                                   */
10507 
10508         struct
10509         {
10510             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
10511             uint32_t               : 2;
10512             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
10513             uint32_t               : 4;
10514             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
10515             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
10516                                            *   select                                                                    */
10517             uint32_t                 : 2;
10518             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
10519             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
10520             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
10521         } GTEITC_b;
10522     };
10523 
10524     union
10525     {
10526         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
10527                                         *                  Setting Register 1                                         */
10528 
10529         struct
10530         {
10531             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
10532                                         *   Extended Skipping Function Select                                         */
10533             uint32_t             : 1;
10534             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
10535                                         *   Extended Skipping Function Select                                         */
10536             uint32_t             : 1;
10537             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
10538                                         *   Function Select                                                           */
10539             uint32_t             : 1;
10540             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
10541                                         *   Function Select                                                           */
10542             uint32_t             : 1;
10543             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
10544                                         *   Function Select                                                           */
10545             uint32_t             : 1;
10546             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
10547                                         *   Function Select                                                           */
10548             uint32_t             : 1;
10549             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
10550             uint32_t             : 1;
10551             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
10552             uint32_t             : 1;
10553         } GTEITLI1_b;
10554     };
10555 
10556     union
10557     {
10558         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
10559                                         *                  Setting Register 2                                         */
10560 
10561         struct
10562         {
10563             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
10564                                         *   Skipping Function Select                                                  */
10565             uint32_t              : 1;
10566             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
10567                                         *   Skipping Function Select                                                  */
10568             uint32_t : 25;
10569         } GTEITLI2_b;
10570     };
10571 
10572     union
10573     {
10574         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
10575                                          *                  Setting Register                                           */
10576 
10577         struct
10578         {
10579             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
10580                                          *   Select                                                                    */
10581             uint32_t              : 1;
10582             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
10583                                          *   Select                                                                    */
10584             uint32_t              : 1;
10585             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
10586                                          *   Select                                                                    */
10587             uint32_t               : 5;
10588             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
10589                                          *   Function Select                                                           */
10590             uint32_t               : 1;
10591             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
10592                                          *   Function Select                                                           */
10593             uint32_t               : 1;
10594             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
10595                                          *   Select                                                                    */
10596             uint32_t               : 1;
10597             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
10598                                          *   Select                                                                    */
10599             uint32_t : 1;
10600         } GTEITLB_b;
10601     };
10602 
10603     union
10604     {
10605         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
10606                                           *                  Function Setting Register                                  */
10607 
10608         struct
10609         {
10610             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
10611             uint32_t                : 1;
10612             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
10613             uint32_t                : 6;
10614             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
10615             uint32_t                : 1;
10616             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
10617             uint32_t                : 6;
10618         } GTICLF_b;
10619     };
10620 
10621     union
10622     {
10623         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
10624 
10625         struct
10626         {
10627             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
10628             uint32_t            : 7;
10629             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
10630             uint32_t            : 7;
10631             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
10632             uint32_t            : 4;
10633         } GTPC_b;
10634     };
10635     __IM uint32_t RESERVED[4];
10636 
10637     union
10638     {
10639         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
10640                                          *                  Control Channel Select Register                            */
10641 
10642         struct
10643         {
10644             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
10645                                          *   Select                                                                    */
10646             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
10647                                          *   Select                                                                    */
10648             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
10649                                          *   Select                                                                    */
10650             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
10651                                          *   Select                                                                    */
10652             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
10653                                          *   Select                                                                    */
10654             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
10655                                          *   Select                                                                    */
10656             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
10657                                          *   Select                                                                    */
10658             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
10659                                          *   Select                                                                    */
10660             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
10661                                          *   Select                                                                    */
10662             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
10663                                          *   Select                                                                    */
10664             uint32_t : 22;
10665         } GTSECSR_b;
10666     };
10667 
10668     union
10669     {
10670         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
10671                                         *                  Control Register                                           */
10672 
10673         struct
10674         {
10675             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
10676             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
10677             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
10678             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
10679             uint32_t             : 4;
10680             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
10681             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
10682             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
10683             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
10684             uint32_t             : 4;
10685             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
10686             __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
10687             uint32_t             : 6;
10688             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
10689             __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
10690             uint32_t             : 6;
10691         } GTSECR_b;
10692     };
10693     __IM uint32_t RESERVED1[2];
10694 
10695     union
10696     {
10697         __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
10698 
10699         struct
10700         {
10701             __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
10702                                         *   Disable                                                                   */
10703             __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
10704                                         *   Disable                                                                   */
10705             __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
10706             __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
10707                                         *   Disable                                                                   */
10708             __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
10709                                         *   Disable                                                                   */
10710             __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
10711                                         *   Disable                                                                   */
10712             uint32_t             : 2;
10713             __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
10714                                         *   Enable                                                                    */
10715             __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
10716                                         *   Enable                                                                    */
10717             uint32_t              : 1;
10718             __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
10719                                         *   Enable                                                                    */
10720             __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
10721                                         *   Enable                                                                    */
10722             uint32_t             : 1;
10723             __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
10724                                         *   Disable                                                                   */
10725             __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
10726                                         *   Disable                                                                   */
10727             __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
10728                                         *   Disable                                                                   */
10729             __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
10730                                         *   Disable                                                                   */
10731             __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
10732                                         *   Disable                                                                   */
10733             __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
10734                                         *   Transfer Disable                                                          */
10735             uint32_t             : 2;
10736             __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
10737             __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
10738             __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
10739             __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
10740             uint32_t             : 2;
10741         } GTBER2_b;
10742     };
10743 
10744     union
10745     {
10746         __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
10747 
10748         struct
10749         {
10750             __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
10751             uint32_t              : 11;
10752             __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
10753             uint32_t              : 11;
10754         } GTOLBR_b;
10755     };
10756     __IM uint32_t RESERVED2;
10757 
10758     union
10759     {
10760         __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
10761                                         *                  Capture Control Register                                   */
10762 
10763         struct
10764         {
10765             __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
10766                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
10767             __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
10768                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
10769             __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
10770                                         *   Channel GTCCRA Input Capture Source Enable                                */
10771             __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
10772                                         *   Channel GTCCRA Input Capture Source Enable                                */
10773             __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
10774                                         *   Channel GTCCRA Input Capture Source Enable                                */
10775             __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
10776                                         *   Channel GTCCRA Input Capture Source Enable                                */
10777             __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
10778                                         *   Source Enable                                                             */
10779             __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
10780                                         *   Source Enable                                                             */
10781             __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
10782                                         *   Capture Source Enable                                                     */
10783             uint32_t              : 5;
10784             __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
10785             __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
10786                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
10787             __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
10788                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
10789             __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
10790                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
10791             __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
10792                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
10793             __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
10794                                         *   Other Channel GTCCRb Input Capture Source Enable                          */
10795             __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
10796                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
10797             __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
10798                                         *   Source Enable                                                             */
10799             __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
10800                                         *   Capture Source Enable                                                     */
10801             __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
10802                                         *   Capture Source Enable                                                     */
10803             uint32_t              : 5;
10804             __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
10805         } GTICCR_b;
10806     };
10807 } R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
10808 
10809 /* =========================================================================================================================== */
10810 /* ================                                         R_GPT_ODC                                         ================ */
10811 /* =========================================================================================================================== */
10812 
10813 /**
10814  * @brief PWM Delay Generation Circuit (R_GPT_ODC)
10815  */
10816 
10817 typedef struct                         /*!< (@ 0x4007B000) R_GPT_ODC Structure                                        */
10818 {
10819     union
10820     {
10821         __IOM uint16_t GTDLYCR1;       /*!< (@ 0x00000000) PWM Output Delay Control Register1                         */
10822 
10823         struct
10824         {
10825             __IOM uint16_t DLLEN  : 1; /*!< [0..0] DLL Operation Enable                                               */
10826             __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset                                 */
10827             uint16_t              : 6;
10828             __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range                                     */
10829             uint16_t              : 7;
10830         } GTDLYCR1_b;
10831     };
10832 
10833     union
10834     {
10835         __IOM uint16_t GTDLYCR2;         /*!< (@ 0x00000002) PWM Output Delay Control Register2                         */
10836 
10837         struct
10838         {
10839             __IOM uint16_t DLYBS0   : 1; /*!< [0..0] PWM Delay Generation Circuit bypass                                */
10840             __IOM uint16_t DLYBS1   : 1; /*!< [1..1] PWM Delay Generation Circuit bypass                                */
10841             __IOM uint16_t DLYBS2   : 1; /*!< [2..2] PWM Delay Generation Circuit bypass                                */
10842             __IOM uint16_t DLYBS3   : 1; /*!< [3..3] PWM Delay Generation Circuit bypass                                */
10843             uint16_t                : 4;
10844             __IOM uint16_t DLYEN0   : 1; /*!< [8..8] PWM Delay Generation Circuit enable                                */
10845             __IOM uint16_t DLYEN1   : 1; /*!< [9..9] PWM Delay Generation Circuit enable                                */
10846             __IOM uint16_t DLYEN2   : 1; /*!< [10..10] PWM Delay Generation Circuit enable                              */
10847             __IOM uint16_t DLYEN3   : 1; /*!< [11..11] PWM Delay Generation Circuit enable                              */
10848             __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB                */
10849             uint16_t                : 3;
10850         } GTDLYCR2_b;
10851     };
10852     __IM uint16_t               RESERVED[10];
10853     __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING                                           */
10854     __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING                                          */
10855 } R_GPT_ODC_Type;                          /*!< Size = 56 (0x38)                                                          */
10856 
10857 /* =========================================================================================================================== */
10858 /* ================                                         R_GPT_OPS                                         ================ */
10859 /* =========================================================================================================================== */
10860 
10861 /**
10862  * @brief Output Phase Switching for GPT (R_GPT_OPS)
10863  */
10864 
10865 typedef struct                         /*!< (@ 0x40078FF0) R_GPT_OPS Structure                                        */
10866 {
10867     union
10868     {
10869         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
10870 
10871         struct
10872         {
10873             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
10874                                         *   by the software settings.This bit setting is valid when
10875                                         *   the OPSCR.FB bit = 1.                                                     */
10876             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
10877                                         *   by the software settings.This bit setting is valid when
10878                                         *   the OPSCR.FB bit = 1.                                                     */
10879             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
10880                                         *   by the software settings.This bit setting is valid when
10881                                         *   the OPSCR.FB bit = 1.                                                     */
10882             uint32_t        : 1;
10883             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
10884                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
10885                                         *   e settings (UF/VF/WF)                                                     */
10886             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
10887                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
10888                                         *   e settings (UF/VF/WF)                                                     */
10889             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
10890                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
10891                                         *   e settings (UF/VF/WF)                                                     */
10892             uint32_t          : 1;
10893             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
10894             uint32_t          : 7;
10895             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
10896                                         *   input phase from the software settings and external input.                */
10897             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
10898             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
10899             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
10900             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
10901             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
10902             uint32_t             : 2;
10903             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
10904             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
10905             uint32_t             : 2;
10906             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
10907             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
10908                                         *   sampling clock setting of the external input.                             */
10909         } OPSCR_b;
10910     };
10911 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
10912 
10913 /* =========================================================================================================================== */
10914 /* ================                                        R_GPT_POEG0                                        ================ */
10915 /* =========================================================================================================================== */
10916 
10917 /**
10918  * @brief Port Output Enable for GPT (R_GPT_POEG0)
10919  */
10920 
10921 typedef struct                          /*!< (@ 0x40042000) R_GPT_POEG0 Structure                                      */
10922 {
10923     union
10924     {
10925         __IOM uint32_t POEGG;           /*!< (@ 0x00000000) POEG Group Setting Register                                */
10926 
10927         struct
10928         {
10929             __IOM uint32_t PIDF  : 1;   /*!< [0..0] Port Input Detection Flag                                          */
10930             __IOM uint32_t IOCF  : 1;   /*!< [1..1] Real Time Overcurrent Detection Flag                               */
10931             __IOM uint32_t OSTPF : 1;   /*!< [2..2] Oscillation Stop Detection Flag                                    */
10932             __IOM uint32_t SSF   : 1;   /*!< [3..3] Software Stop Flag                                                 */
10933             __IOM uint32_t PIDE  : 1;   /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
10934                                          *   once after a reset.                                                       */
10935             __IOM uint32_t IOCE : 1;    /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
10936                                          *   only once after a reset.                                                  */
10937             __IOM uint32_t OSTPE : 1;   /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
10938                                          *   only once after a reset.                                                  */
10939             uint32_t             : 1;
10940             __IOM uint32_t CDRE0 : 1;   /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
10941                                          *   only once after a reset.                                                  */
10942             __IOM uint32_t CDRE1 : 1;   /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
10943                                          *   only once after a reset.                                                  */
10944             __IOM uint32_t CDRE2 : 1;   /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
10945                                          *   only once after a reset.                                                  */
10946             __IOM uint32_t CDRE3 : 1;   /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
10947                                          *   only once after a reset.                                                  */
10948             __IOM uint32_t CDRE4 : 1;   /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
10949                                          *   only once after a reset.                                                  */
10950             __IOM uint32_t CDRE5 : 1;   /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
10951                                          *   only once after a reset.                                                  */
10952             uint32_t               : 2;
10953             __IM uint32_t ST       : 1; /*!< [16..16] GTETRG Input Status Flag                                         */
10954             uint32_t               : 7;
10955             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag                                      */
10956             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag                                      */
10957             __IOM uint32_t DERR0E  : 1; /*!< [26..26] DSMIF0 Error Detection Enable                                    */
10958             __IOM uint32_t DERR1E  : 1; /*!< [27..27] DSMIF1 Error Detection Enable                                    */
10959             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRG Input Reverse                                             */
10960             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise Filter Enable                                              */
10961             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise Filter Clock Select                                        */
10962         } POEGG_b;
10963     };
10964     __IM uint32_t RESERVED[15];
10965 
10966     union
10967     {
10968         __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
10969                                         *                  Register                                                   */
10970 
10971         struct
10972         {
10973             __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
10974             uint16_t             : 7;
10975             __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
10976         } GTONCWP_b;
10977     };
10978     __IM uint16_t RESERVED1;
10979 
10980     union
10981     {
10982         __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
10983                                         *                  Register                                                   */
10984 
10985         struct
10986         {
10987             __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
10988             uint16_t           : 3;
10989             __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
10990             __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
10991             uint16_t           : 7;
10992         } GTONCCR_b;
10993     };
10994     __IM uint16_t RESERVED2;
10995 } R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */
10996 
10997 /* =========================================================================================================================== */
10998 /* ================                                           R_ICU                                           ================ */
10999 /* =========================================================================================================================== */
11000 
11001 /**
11002  * @brief Interrupt Controller Unit (R_ICU)
11003  */
11004 
11005 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
11006 {
11007     union
11008     {
11009         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
11010 
11011         struct
11012         {
11013             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
11014             uint8_t               : 2;
11015             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
11016             uint8_t               : 1;
11017             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
11018         } IRQCR_b[16];
11019     };
11020     __IM uint32_t RESERVED[60];
11021 
11022     union
11023     {
11024         __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
11025 
11026         struct
11027         {
11028             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
11029             uint8_t                : 3;
11030             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
11031             uint8_t                : 1;
11032             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
11033         } NMICR_b;
11034     };
11035     __IM uint8_t  RESERVED1;
11036     __IM uint16_t RESERVED2;
11037     __IM uint32_t RESERVED3[7];
11038 
11039     union
11040     {
11041         __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
11042 
11043         struct
11044         {
11045             __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
11046             __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
11047             __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
11048             __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
11049             __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
11050             uint16_t               : 1;
11051             __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
11052             __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
11053             __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
11054             __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
11055             __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
11056             __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
11057             __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
11058             __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
11059             uint16_t               : 1;
11060             __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
11061         } NMIER_b;
11062     };
11063     __IM uint16_t RESERVED4;
11064     __IM uint32_t RESERVED5[3];
11065 
11066     union
11067     {
11068         __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
11069 
11070         struct
11071         {
11072             __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
11073             __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
11074             __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
11075             __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
11076             __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
11077             uint16_t               : 1;
11078             __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
11079             __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
11080             __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
11081             __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
11082             __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
11083             __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
11084             __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
11085             __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
11086             uint16_t               : 1;
11087             __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
11088         } NMICLR_b;
11089     };
11090     __IM uint16_t RESERVED6;
11091     __IM uint32_t RESERVED7[3];
11092 
11093     union
11094     {
11095         __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
11096 
11097         struct
11098         {
11099             __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
11100             __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
11101             __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
11102             __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
11103             __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
11104             uint16_t              : 1;
11105             __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
11106             __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
11107             __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
11108             __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
11109             __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
11110             __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
11111             __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
11112             __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
11113             uint16_t              : 1;
11114             __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
11115         } NMISR_b;
11116     };
11117     __IM uint16_t RESERVED8;
11118     __IM uint32_t RESERVED9[23];
11119 
11120     union
11121     {
11122         __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
11123 
11124         struct
11125         {
11126             __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
11127             __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
11128             __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
11129             __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
11130             __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
11131             __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
11132             __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
11133             __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
11134             __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
11135             __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
11136             __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
11137             __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
11138             __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
11139             __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
11140             __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
11141             __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
11142             __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
11143             __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
11144             __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
11145             __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
11146             __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
11147             uint32_t                    : 1;
11148             __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
11149             __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
11150             __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
11151             __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
11152             __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
11153             __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
11154             __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
11155             __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
11156                                               *   enable                                                                    */
11157             __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
11158                                               *   enable                                                                    */
11159             __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
11160         } WUPEN_b;
11161     };
11162 
11163     union
11164     {
11165         __IOM uint32_t WUPEN1;              /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
11166 
11167         struct
11168         {
11169             __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit            */
11170             __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
11171                                              *   bit                                                                       */
11172             __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
11173                                              *   bit                                                                       */
11174             uint32_t : 29;
11175         } WUPEN1_b;
11176     };
11177     __IM uint32_t RESERVED10[6];
11178 
11179     union
11180     {
11181         __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
11182 
11183         struct
11184         {
11185             __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
11186                                          *   = 1)                                                                      */
11187             __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
11188                                          *   LPOPTEN bit = 1)                                                          */
11189             uint8_t : 6;
11190         } IELEN_b;
11191     };
11192     __IM uint8_t  RESERVED11;
11193     __IM uint16_t RESERVED12;
11194     __IM uint32_t RESERVED13[15];
11195 
11196     union
11197     {
11198         __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
11199 
11200         struct
11201         {
11202             __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
11203             uint16_t            : 7;
11204         } SELSR0_b;
11205     };
11206     __IM uint16_t RESERVED14;
11207     __IM uint32_t RESERVED15[31];
11208 
11209     union
11210     {
11211         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
11212 
11213         struct
11214         {
11215             __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
11216             uint32_t            : 7;
11217             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
11218                                         *   IR flag is prohibited.                                                    */
11219             uint32_t : 15;
11220         } DELSR_b[8];
11221     };
11222     __IM uint32_t RESERVED16[24];
11223 
11224     union
11225     {
11226         __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
11227 
11228         struct
11229         {
11230             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
11231                                         *   signal to be linked .                                                     */
11232             uint32_t            : 7;
11233             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
11234             uint32_t            : 7;
11235             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
11236             uint32_t            : 7;
11237         } IELSR_b[96];
11238     };
11239 } R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
11240 
11241 /* =========================================================================================================================== */
11242 /* ================                                          R_IIC0                                           ================ */
11243 /* =========================================================================================================================== */
11244 
11245 /**
11246  * @brief I2C Bus Interface (R_IIC0)
11247  */
11248 
11249 typedef struct                         /*!< (@ 0x40053000) R_IIC0 Structure                                           */
11250 {
11251     union
11252     {
11253         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
11254 
11255         struct
11256         {
11257             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
11258             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
11259             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
11260             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
11261             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
11262             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
11263             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
11264                                         *   is initiated using the IICRST bit for a bus hang-up occurred
11265                                         *   during communication with the master device in slave mode,
11266                                         *   the states may become different between the slave device
11267                                         *   and the master device (due to the difference in the bit
11268                                         *   counter information).                                                     */
11269             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
11270         } ICCR1_b;
11271     };
11272 
11273     union
11274     {
11275         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
11276 
11277         struct
11278         {
11279             uint8_t          : 1;
11280             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
11281                                         *   condition issuance request) when the BBSY flag is set to
11282                                         *   0 (bus free state).                                                       */
11283             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
11284                                         *   RS bit to 1 while issuing a stop condition.                               */
11285             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
11286                                         *   bit is not possible while the setting of the BBSY flag
11287                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
11288                                         *   while a restart condition is being issued.                                */
11289             uint8_t            : 1;
11290             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
11291             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
11292             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
11293         } ICCR2_b;
11294     };
11295 
11296     union
11297     {
11298         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
11299 
11300         struct
11301         {
11302             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
11303             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
11304             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
11305                                         *   / 2^CKS )                                                                 */
11306             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
11307         } ICMR1_b;
11308     };
11309 
11310     union
11311     {
11312         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
11313 
11314         struct
11315         {
11316             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
11317             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
11318             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
11319             uint8_t            : 1;
11320             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
11321             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
11322         } ICMR2_b;
11323     };
11324 
11325     union
11326     {
11327         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
11328 
11329         struct
11330         {
11331             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
11332             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
11333             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
11334             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
11335             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
11336             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
11337                                         *   be sure to read the ICDRR beforehand.                                     */
11338             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
11339         } ICMR3_b;
11340     };
11341 
11342     union
11343     {
11344         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
11345 
11346         struct
11347         {
11348             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
11349             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
11350             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
11351             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
11352             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
11353             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
11354             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
11355             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
11356         } ICFER_b;
11357     };
11358 
11359     union
11360     {
11361         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
11362 
11363         struct
11364         {
11365             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
11366             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
11367             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
11368             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
11369             uint8_t             : 1;
11370             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
11371             uint8_t             : 1;
11372             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
11373         } ICSER_b;
11374     };
11375 
11376     union
11377     {
11378         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
11379 
11380         struct
11381         {
11382             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
11383             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
11384             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
11385             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
11386             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
11387             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
11388             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
11389             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
11390         } ICIER_b;
11391     };
11392 
11393     union
11394     {
11395         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
11396 
11397         struct
11398         {
11399             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
11400             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
11401             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
11402             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
11403             uint8_t            : 1;
11404             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
11405             uint8_t            : 1;
11406             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
11407         } ICSR1_b;
11408     };
11409 
11410     union
11411     {
11412         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
11413 
11414         struct
11415         {
11416             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
11417             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
11418             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
11419             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
11420             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
11421             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
11422             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
11423             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
11424         } ICSR2_b;
11425     };
11426     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
11427 
11428     union
11429     {
11430         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
11431 
11432         struct
11433         {
11434             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
11435             uint8_t           : 3;
11436         } ICBRL_b;
11437     };
11438 
11439     union
11440     {
11441         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
11442 
11443         struct
11444         {
11445             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
11446             uint8_t           : 3;
11447         } ICBRH_b;
11448     };
11449 
11450     union
11451     {
11452         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
11453 
11454         struct
11455         {
11456             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
11457         } ICDRT_b;
11458     };
11459 
11460     union
11461     {
11462         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
11463 
11464         struct
11465         {
11466             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
11467         } ICDRR_b;
11468     };
11469     __IM uint8_t RESERVED[2];
11470 
11471     union
11472     {
11473         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
11474 
11475         struct
11476         {
11477             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
11478             uint8_t             : 3;
11479             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
11480             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
11481             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
11482             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
11483         } ICWUR_b;
11484     };
11485 
11486     union
11487     {
11488         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
11489 
11490         struct
11491         {
11492             __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
11493             __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
11494             __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
11495             uint8_t              : 5;
11496         } ICWUR2_b;
11497     };
11498 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
11499 
11500 /* =========================================================================================================================== */
11501 /* ================                                          R_IRDA                                           ================ */
11502 /* =========================================================================================================================== */
11503 
11504 /**
11505  * @brief IrDA Interface (R_IRDA)
11506  */
11507 
11508 typedef struct                         /*!< (@ 0x40070F00) R_IRDA Structure                                           */
11509 {
11510     union
11511     {
11512         __IOM uint8_t IRCR;            /*!< (@ 0x00000000) IrDA Control Register                                      */
11513 
11514         struct
11515         {
11516             uint8_t               : 2;
11517             __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching                                           */
11518             __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching                                           */
11519             uint8_t               : 3;
11520             __IOM uint8_t IRE     : 1; /*!< [7..7] IrDA Enable                                                        */
11521         } IRCR_b;
11522     };
11523 } R_IRDA_Type;                         /*!< Size = 1 (0x1)                                                            */
11524 
11525 /* =========================================================================================================================== */
11526 /* ================                                          R_IWDT                                           ================ */
11527 /* =========================================================================================================================== */
11528 
11529 /**
11530  * @brief Independent Watchdog Timer (R_IWDT)
11531  */
11532 
11533 typedef struct                         /*!< (@ 0x40044400) R_IWDT Structure                                           */
11534 {
11535     union
11536     {
11537         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
11538 
11539         struct
11540         {
11541             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
11542                                         *   0xFF to this register.                                                    */
11543         } IWDTRR_b;
11544     };
11545     __IM uint8_t RESERVED;
11546 
11547     union
11548     {
11549         __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
11550 
11551         struct
11552         {
11553             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
11554             uint16_t            : 2;
11555             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
11556             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
11557             uint16_t            : 2;
11558             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
11559             uint16_t            : 2;
11560         } IWDTCR_b;
11561     };
11562 
11563     union
11564     {
11565         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
11566 
11567         struct
11568         {
11569             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
11570             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
11571             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
11572         } IWDTSR_b;
11573     };
11574 
11575     union
11576     {
11577         __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
11578 
11579         struct
11580         {
11581             uint8_t               : 7;
11582             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
11583         } IWDTRCR_b;
11584     };
11585     __IM uint8_t RESERVED1;
11586 
11587     union
11588     {
11589         __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
11590 
11591         struct
11592         {
11593             uint8_t              : 7;
11594             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
11595         } IWDTCSTPR_b;
11596     };
11597     __IM uint8_t  RESERVED2;
11598     __IM uint16_t RESERVED3;
11599 } R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
11600 
11601 /* =========================================================================================================================== */
11602 /* ================                                          R_JPEG                                           ================ */
11603 /* =========================================================================================================================== */
11604 
11605 /**
11606  * @brief JPEG Codec (R_JPEG)
11607  */
11608 
11609 typedef struct                         /*!< (@ 0x400E6000) R_JPEG Structure                                           */
11610 {
11611     union
11612     {
11613         __IOM uint8_t JCMOD;           /*!< (@ 0x00000000) JPEG Code Mode Register                                    */
11614 
11615         struct
11616         {
11617             __IOM uint8_t REDU : 3;    /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression.                      */
11618             __IOM uint8_t DSP  : 1;    /*!< [3..3] Compression/Decompression Set Note: When changing between
11619                                         *   processing for compression and for decompression, be sure
11620                                         *   to reset this module in advance by setting the JCUSRST
11621                                         *   bit in the software reset control register 2 (SWRSTCR2)
11622                                         *   of the power-downmodes.                                                   */
11623             uint8_t : 4;
11624         } JCMOD_b;
11625     };
11626 
11627     union
11628     {
11629         __OM uint8_t JCCMD;            /*!< (@ 0x00000001) JPEG Code Command Register                                 */
11630 
11631         struct
11632         {
11633             __OM uint8_t JSRT : 1;     /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing,
11634                                         *   set this bit to 1. Do not write this bit to 1 again while
11635                                         *   this module is in operation.                                              */
11636             __OM uint8_t JRST : 1;     /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped
11637                                         *   state caused by requests to read the image size and pixel
11638                                         *   format (enabled by the INT3 bit in JINTE0), set this bit
11639                                         *   to 1.                                                                     */
11640             __OM uint8_t JEND : 1;     /*!< [2..2] Interrupt Request Clear Command This bit is valid only
11641                                         *   for the interrupt sources corresponding to bits INS6, INS5,
11642                                         *   and INS3 in JINTS0. To clear an interrupt request, set
11643                                         *   this bit to 1                                                             */
11644             uint8_t           : 4;
11645             __OM uint8_t BRST : 1;     /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the
11646                                         *   bus reset command should not be issued.                                   */
11647         } JCCMD_b;
11648     };
11649     __IM uint8_t RESERVED;
11650 
11651     union
11652     {
11653         __IOM uint8_t JCQTN;           /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register               */
11654 
11655         struct
11656         {
11657             __IOM uint8_t QT1 : 2;     /*!< [1..0] Quantization table number for the first color componentNOTE:
11658                                         *   Read-only in Decompression.                                               */
11659             __IOM uint8_t QT2 : 2;     /*!< [3..2] Quantization table number for the second color component
11660                                         *   NOTE: Read-only in Decompression.                                         */
11661             __IOM uint8_t QT3 : 2;     /*!< [5..4] Quantization table number for the third color component
11662                                         *   NOTE: Read-only in Decompression.                                         */
11663             uint8_t : 2;
11664         } JCQTN_b;
11665     };
11666 
11667     union
11668     {
11669         __IOM uint8_t JCHTN;           /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register                    */
11670 
11671         struct
11672         {
11673             __IOM uint8_t HTD1 : 1;    /*!< [0..0] Huffman table number (DC) for the first color component
11674                                         *   NOTE: Read-only in Decompression.                                         */
11675             __IOM uint8_t HTA1 : 1;    /*!< [1..1] Huffman table number (AC) for the first color componentNOTE:
11676                                         *   Read-only in Decompression.                                               */
11677             __IOM uint8_t HTD2 : 1;    /*!< [2..2] Huffman table number (DC) for the second color component
11678                                         *   NOTE: Read-only in Decompression.                                         */
11679             __IOM uint8_t HTA2 : 1;    /*!< [3..3] Huffman table number (AC) for the second color componentNOTE:
11680                                         *   Read-only in Decompression.                                               */
11681             __IOM uint8_t HTD3 : 1;    /*!< [4..4] Huffman table number (DC) for the third color component
11682                                         *   NOTE: Read-only in Decompression.                                         */
11683             __IOM uint8_t HTA3 : 1;    /*!< [5..5] Huffman table number (AC) for the third color componentNOTE:
11684                                         *   Read-only in Decompression.                                               */
11685             uint8_t : 2;
11686         } JCHTN_b;
11687     };
11688 
11689     union
11690     {
11691         __IOM uint8_t JCDRIU;          /*!< (@ 0x00000005) JPEG Code DRI Upper Register                               */
11692 
11693         struct
11694         {
11695             __IOM uint8_t DRIU : 8;    /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper
11696                                         *   and lower bytes are set to 00h, neither a DRI nor an RST
11697                                         *   marker is placed.NOTE: Read-only in Decompression.                        */
11698         } JCDRIU_b;
11699     };
11700 
11701     union
11702     {
11703         __IOM uint8_t JCDRID;          /*!< (@ 0x00000006) JPEG Code DRI Lower Register                               */
11704 
11705         struct
11706         {
11707             __IOM uint8_t DRID : 8;    /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper
11708                                         *   and lower bytes are set to 00h, neither a DRI nor an RST
11709                                         *   marker is placed.NOTE: Read-only in Decompression.                        */
11710         } JCDRID_b;
11711     };
11712 
11713     union
11714     {
11715         __IOM uint8_t JCVSZU;          /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register                     */
11716 
11717         struct
11718         {
11719             __IOM uint8_t VSZU : 8;    /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process,
11720                                         *   a downloaded value from the JPEG coded data is set. NOTE:
11721                                         *   Read-only in Decompression.                                               */
11722         } JCVSZU_b;
11723     };
11724 
11725     union
11726     {
11727         __IOM uint8_t JCVSZD;          /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register                     */
11728 
11729         struct
11730         {
11731             __IOM uint8_t VSZD : 8;    /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process,
11732                                         *   a downloaded value from the JPEG coded data is set. NOTE:
11733                                         *   Read-only in Decompression.                                               */
11734         } JCVSZD_b;
11735     };
11736 
11737     union
11738     {
11739         __IOM uint8_t JCHSZU;          /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register                   */
11740 
11741         struct
11742         {
11743             __IOM uint8_t HSZU : 8;    /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression
11744                                         *   process, a downloaded value from the JPEG coded data is
11745                                         *   set. NOTE: Read-only in Decompression.                                    */
11746         } JCHSZU_b;
11747     };
11748 
11749     union
11750     {
11751         __IOM uint8_t JCHSZD;          /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register                  */
11752 
11753         struct
11754         {
11755             __IOM uint8_t HSZD : 8;    /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression
11756                                         *   process, a downloaded value from the JPEG coded data is
11757                                         *   set. NOTE: Read-only in Decompression.                                    */
11758         } JCHSZD_b;
11759     };
11760 
11761     union
11762     {
11763         __IM uint8_t JCDTCU;           /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register                        */
11764 
11765         struct
11766         {
11767             __IM uint8_t DCU : 8;      /*!< [7..0] Upper bytes of the counted amount of data to be compressed
11768                                         *   The values of this register are reset before compression
11769                                         *   starts.NOTE: Read-only in Decompression.                                  */
11770         } JCDTCU_b;
11771     };
11772 
11773     union
11774     {
11775         __IM uint8_t JCDTCM;           /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register                       */
11776 
11777         struct
11778         {
11779             __IM uint8_t DCM : 8;      /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe
11780                                         *   values of this register are reset before compression starts.
11781                                         *   NOTE: Read-only in Decompression.                                         */
11782         } JCDTCM_b;
11783     };
11784 
11785     union
11786     {
11787         __IM uint8_t JCDTCD;           /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register                        */
11788 
11789         struct
11790         {
11791             __IM uint8_t DCD : 8;      /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe
11792                                         *   values of this register are reset before compression starts.NOTE:
11793                                         *   Read-only in Decompression.                                               */
11794         } JCDTCD_b;
11795     };
11796 
11797     union
11798     {
11799         __IOM uint8_t JINTE0;          /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0                           */
11800 
11801         struct
11802         {
11803             uint8_t            : 3;
11804             __IOM uint8_t INT3 : 1;    /*!< [3..3] This bit enables an interrupt to be generated when it
11805                                         *   has been determined that the image size and the subsampling
11806                                         *   setting of the compressed data can be read through analyzing
11807                                         *   the data.                                                                 */
11808             uint8_t            : 1;
11809             __IOM uint8_t INT5 : 1;    /*!< [5..5] This bit enables an interrupt to be generated when the
11810                                         *   final number of MCU data in the Huffman-coding segment
11811                                         *   is not correct in decompression. When this bit is not set
11812                                         *   to enable interrupt generation, an error code is not returned.            */
11813             __IOM uint8_t INT6 : 1;    /*!< [6..6] This bit enables an interrupt to be generated when the
11814                                         *   total number of data in the Huffman-coding segment is not
11815                                         *   correct in decompression. When this bit is not set to enable
11816                                         *   interrupt generation, an error code is not returned.                      */
11817             __IOM uint8_t INT7 : 1;    /*!< [7..7] This bit enables an interrupt to be generated when the
11818                                         *   number of data in the restart interval of the Huffman-coding
11819                                         *   segment is not correct in decompression.When this bit is
11820                                         *   not set to enable interrupt generation, an error code is
11821                                         *   not returned.                                                             */
11822         } JINTE0_b;
11823     };
11824 
11825     union
11826     {
11827         __IOM uint8_t JINTS0;          /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0                           */
11828 
11829         struct
11830         {
11831             uint8_t            : 3;
11832             __IOM uint8_t INS3 : 1;    /*!< [3..3] This bit is set to 1 when the image size and pixel format
11833                                         *   can be read. When an interrupt occurs, this module stops
11834                                         *   processing and the state is indicated by the JCRST register.
11835                                         *   To make this module resume processing, set the JPEG core
11836                                         *   process stop clear command bit (JRST) in JCCMD.                           */
11837             uint8_t            : 1;
11838             __IOM uint8_t INS5 : 1;    /*!< [5..5] This bit is set to 1 when a compressed data error occurs.          */
11839             __IOM uint8_t INS6 : 1;    /*!< [6..6] This bit is set to 1 when this module completes compression
11840                                         *   process normally.                                                         */
11841             uint8_t : 1;
11842         } JINTS0_b;
11843     };
11844 
11845     union
11846     {
11847         __IOM uint8_t JCDERR;          /*!< (@ 0x00000010) JPEG Code Decode Error Register                            */
11848 
11849         struct
11850         {
11851             __IOM uint8_t ERR : 4;     /*!< [3..0] Error Code (See tables )Identify the type of the error
11852                                         *   which has occurred in the compressed data analysis for
11853                                         *   decompression.                                                            */
11854             uint8_t : 4;
11855         } JCDERR_b;
11856     };
11857 
11858     union
11859     {
11860         __IM uint8_t JCRST;            /*!< (@ 0x00000011) JPEG Code Reset Register                                   */
11861 
11862         struct
11863         {
11864             __IM uint8_t RST : 1;      /*!< [0..0] Operating State                                                    */
11865             uint8_t          : 7;
11866         } JCRST_b;
11867     };
11868     __IM uint16_t RESERVED1;
11869     __IM uint32_t RESERVED2[11];
11870 
11871     union
11872     {
11873         __IOM uint32_t JIFECNT;          /*!< (@ 0x00000040) JPEG Interface Compression Control Register                */
11874 
11875         struct
11876         {
11877             __IOM uint32_t DINSWAP : 3;  /*!< [2..0] Byte/Halfword Swap                                                 */
11878             uint32_t               : 1;
11879             __IOM uint32_t DINLC   : 1;  /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines             */
11880             __OM uint32_t  DINRCMD : 1;  /*!< [5..5] Input Image Data Lines Resume Command This bit is valid
11881                                           *   only when the count mode for stopping the input of image
11882                                           *   data lines is on. Setting this bit to 1 resumes reading
11883                                           *   input image data. This bit is always read as 0.                           */
11884             __IOM uint32_t DINRINI : 1;  /*!< [6..6] Address Initialization when Resuming Input of Image Data
11885                                           *   Lines This bit is only valid when the count mode for stopping
11886                                           *   the input of image data lines is on. Set this bit before
11887                                           *   writing 1 to the data-line resume command bit.                            */
11888             uint32_t                : 1;
11889             __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression
11890                                           *   is swapped.                                                               */
11891             uint32_t : 21;
11892         } JIFECNT_b;
11893     };
11894 
11895     union
11896     {
11897         __IOM uint32_t JIFESA;         /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register         */
11898 
11899         struct
11900         {
11901             __IOM uint32_t ESA : 32;   /*!< [31..0] Input Image Data Source Address (in 8-byte units) The
11902                                         *   lower three bits should be set to 0.                                      */
11903         } JIFESA_b;
11904     };
11905 
11906     union
11907     {
11908         __IOM uint32_t JIFESOFST;      /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register            */
11909 
11910         struct
11911         {
11912             __IOM uint32_t ESMW : 15;  /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower
11913                                         *   three bits should be set to 0.                                            */
11914             uint32_t : 17;
11915         } JIFESOFST_b;
11916     };
11917 
11918     union
11919     {
11920         __IOM uint32_t JIFEDA;         /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address
11921                                         *                  Register                                                   */
11922 
11923         struct
11924         {
11925             __IOM uint32_t EDA : 32;   /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The
11926                                         *   lower three bits should be set to 0.                                      */
11927         } JIFEDA_b;
11928     };
11929 
11930     union
11931     {
11932         __IOM uint32_t JIFESLC;        /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count
11933                                         *                  Register                                                   */
11934 
11935         struct
11936         {
11937             __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line
11938                                         *   units) The lower three bits should be set to 0.                           */
11939             uint32_t : 16;
11940         } JIFESLC_b;
11941     };
11942     __IM uint32_t RESERVED3;
11943 
11944     union
11945     {
11946         __IOM uint32_t JIFDCNT;          /*!< (@ 0x00000058) JPEG Interface Decompression Control Register              */
11947 
11948         struct
11949         {
11950             __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is
11951                                           *   swapped.                                                                  */
11952             uint32_t                : 1;
11953             __IOM uint32_t DOUTLC   : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines                    */
11954             __OM uint32_t  DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid
11955                                           *   only when the count mode for stopping the output of image
11956                                           *   data lines is on. Setting this bit to 1 resumes writing
11957                                           *   image data. This bit is always read as 0.                                 */
11958             __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image
11959                                           *   Data Lines This bit is only valid when the count mode for
11960                                           *   stopping the output of image data lines is on. Set this
11961                                           *   bit before writing 1 to the data-line resume command bit.                 */
11962             uint32_t               : 1;
11963             __IOM uint32_t JINSWAP : 3;  /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression
11964                                           *   is swapped.                                                               */
11965             uint32_t               : 1;
11966             __IOM uint32_t JINC    : 1;  /*!< [12..12] Count Mode Setting for Stopping Input Coded Data                 */
11967             __OM uint32_t  JINRCMD : 1;  /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only
11968                                           *   when the count mode for stopping the input of coded data
11969                                           *   is on. Setting this bit to 1 resumes reading input coded
11970                                           *   data. This bit is always read as 0.                                       */
11971             __IOM uint32_t JINRINI : 1;  /*!< [14..14] Address Initialization when Input Coded Data is Resumed
11972                                           *   This bit is only valid when the count mode for stopping
11973                                           *   the input of coded data is on. Set this bit before writing
11974                                           *   1 to the data resume command bit.                                         */
11975             uint32_t              : 9;
11976             __IOM uint32_t OPF    : 2;   /*!< [25..24] Specifies output image data pixel format.                        */
11977             __IOM uint32_t HINTER : 2;   /*!< [27..26] Horizontal Subsampling Subsamples horizontal output
11978                                           *   image data.                                                               */
11979             __IOM uint32_t VINTER : 2;   /*!< [29..28] Vertical SubsamplingSubsamples vertical output image
11980                                           *   data.                                                                     */
11981             uint32_t : 2;
11982         } JIFDCNT_b;
11983     };
11984 
11985     union
11986     {
11987         __IOM uint32_t JIFDSA;         /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register       */
11988 
11989         struct
11990         {
11991             __IOM uint32_t DSA : 32;   /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source
11992                                         *   Address (in 8-byte units) The lower three bits should be
11993                                         *   set to 0.                                                                 */
11994         } JIFDSA_b;
11995     };
11996 
11997     union
11998     {
11999         __IOM uint32_t JIFDDOFST;      /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register          */
12000 
12001         struct
12002         {
12003             __IOM uint32_t DDMW : 15;  /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The
12004                                         *   lower three bits should be set to 0.                                      */
12005             uint32_t : 17;
12006         } JIFDDOFST_b;
12007     };
12008 
12009     union
12010     {
12011         __IOM uint32_t JIFDDA;         /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address
12012                                         *                  Register                                                   */
12013 
12014         struct
12015         {
12016             __IOM uint32_t DDA : 32;   /*!< [31..0] Output Image Data Destination Address (in 8-byte units)
12017                                         *   The lower three bits should be set to 0.                                  */
12018         } JIFDDA_b;
12019     };
12020 
12021     union
12022     {
12023         __IOM uint32_t JIFDSDC;         /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count
12024                                          *                  Register                                                   */
12025 
12026         struct
12027         {
12028             __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units)
12029                                          *   The lower three bits should be set to 0.                                  */
12030             uint32_t : 16;
12031         } JIFDSDC_b;
12032     };
12033 
12034     union
12035     {
12036         __IOM uint32_t JIFDDLC;        /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line
12037                                         *                  Count Register                                             */
12038 
12039         struct
12040         {
12041             __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three
12042                                         *   bits should be set to 0. These bits are read as0.Number
12043                                         *   of input image data lines to be read, in 8-line units.                    */
12044             uint32_t : 16;
12045         } JIFDDLC_b;
12046     };
12047 
12048     union
12049     {
12050         __IOM uint32_t JIFDADT;        /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register            */
12051 
12052         struct
12053         {
12054             __IOM uint32_t ALPHA : 8;  /*!< [7..0] Setting of the alpha value for output in ARGB8888 format.          */
12055             uint32_t             : 24;
12056         } JIFDADT_b;
12057     };
12058     __IM uint32_t RESERVED4[6];
12059 
12060     union
12061     {
12062         __IOM uint32_t JINTE1;          /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1                           */
12063 
12064         struct
12065         {
12066             __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt
12067                                          *   request (JDTI) when the DOUTLF bit in JINTS1 is set to
12068                                          *   1                                                                         */
12069             __IOM uint32_t JINEN : 1;   /*!< [1..1] Enables or disables a data transfer processing interrupt
12070                                          *   request (JDTI) when the JINF bit in JINTS1 is set to 1.                   */
12071             __IOM uint32_t DBTEN : 1;   /*!< [2..2] Enables or disables a data transfer processing interrupt
12072                                          *   request (JDTI) when the DBTF bit in JINTS1 is set to 1.                   */
12073             uint32_t              : 2;
12074             __IOM uint32_t DINLEN : 1;  /*!< [5..5] Enables or disables a data transfer processing interrupt
12075                                          *   request (JDTI) when the DINLF bit in JINTS1 is set to 1.                  */
12076             __IOM uint32_t CBTEN : 1;   /*!< [6..6] Enables or disables a data transfer processing interrupt
12077                                          *   request (JDTI) when the CBTF bit in JINTS1 is set to 1.                   */
12078             uint32_t : 25;
12079         } JINTE1_b;
12080     };
12081 
12082     union
12083     {
12084         __IOM uint32_t JINTS1;         /*!< (@ 0x00000090) JPEG Interrupt Status Register 1                           */
12085 
12086         struct
12087         {
12088             __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number
12089                                         *   of lines of output image data indicated by JIFDDLC have
12090                                         *   been written. This bit is only valid when the DOUTLC bit
12091                                         *   in JIFDCNT is set to 1.                                                   */
12092             __IOM uint32_t JINF : 1;   /*!< [1..1] This bit is set to 1 when the amount of input coded data
12093                                         *   indicated by JIFDSDC is read in decompression. This bit
12094                                         *   is valid only when the JINC bit in JIFDCNT is set to 1.                   */
12095             __IOM uint32_t DBTF : 1;   /*!< [2..2] This bit is set to 1 when the last output image data
12096                                         *   is written in decompression.                                              */
12097             uint32_t             : 2;
12098             __IOM uint32_t DINLF : 1;  /*!< [5..5] This bit is set to 1 when the number of input image data
12099                                         *   lines indicated by JIFESLC is read in compression. This
12100                                         *   bit is valid only when the DINLC bit in JIFECNT is set
12101                                         *   to 1.                                                                     */
12102             __IOM uint32_t CBTF : 1;   /*!< [6..6] This bit is set to 1 when the last output coded data
12103                                         *   is written in compression.                                                */
12104             uint32_t : 25;
12105         } JINTS1_b;
12106     };
12107     __IM uint32_t RESERVED5[27];
12108     __OM uint8_t  JCQTBL0[64];         /*!< (@ 0x00000100) Quantization Table 0                                       */
12109     __OM uint8_t  JCQTBL1[64];         /*!< (@ 0x00000140) Quantization Table 1                                       */
12110     __OM uint8_t  JCQTBL2[64];         /*!< (@ 0x00000180) Quantization Table 2                                       */
12111     __OM uint8_t  JCQTBL3[64];         /*!< (@ 0x000001C0) Quantization Table 3                                       */
12112     __IOM uint8_t JCHTBD0[28];         /*!< (@ 0x00000200) DC Huffman Table 0                                         */
12113     __IM uint32_t RESERVED6;
12114     __IOM uint8_t JCHTBA0[178];        /*!< (@ 0x00000220) AC Huffman Table 0                                         */
12115     __IM uint16_t RESERVED7;
12116     __IM uint32_t RESERVED8[11];
12117     __IOM uint8_t JCHTBD1[28];         /*!< (@ 0x00000300) DC Huffman Table 1                                         */
12118     __IM uint32_t RESERVED9;
12119     __IOM uint8_t JCHTBA1[178];        /*!< (@ 0x00000320) DC Huffman Table 1                                         */
12120     __IM uint16_t RESERVED10;
12121 } R_JPEG_Type;                         /*!< Size = 980 (0x3d4)                                                        */
12122 
12123 /* =========================================================================================================================== */
12124 /* ================                                          R_KINT                                           ================ */
12125 /* =========================================================================================================================== */
12126 
12127 /**
12128  * @brief Key Interrupt Function (R_KINT)
12129  */
12130 
12131 typedef struct                         /*!< (@ 0x40080000) R_KINT Structure                                           */
12132 {
12133     union
12134     {
12135         __IOM uint8_t KRCTL;           /*!< (@ 0x00000000) KEY Return Control Register                                */
12136 
12137         struct
12138         {
12139             __IOM uint8_t KREG : 1;    /*!< [0..0] Detection Edge Selection (KRF0 to KRF7)                            */
12140             uint8_t            : 6;
12141             __IOM uint8_t KRMD : 1;    /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7)                           */
12142         } KRCTL_b;
12143     };
12144     __IM uint8_t RESERVED[3];
12145 
12146     union
12147     {
12148         __IOM uint8_t KRF;             /*!< (@ 0x00000004) KEY Return Flag Register                                   */
12149 
12150         struct
12151         {
12152             __IOM uint8_t KRF0 : 1;    /*!< [0..0] Key interrupt flag 0                                               */
12153             __IOM uint8_t KRF1 : 1;    /*!< [1..1] Key interrupt flag 1                                               */
12154             __IOM uint8_t KRF2 : 1;    /*!< [2..2] Key interrupt flag 2                                               */
12155             __IOM uint8_t KRF3 : 1;    /*!< [3..3] Key interrupt flag 3                                               */
12156             __IOM uint8_t KRF4 : 1;    /*!< [4..4] Key interrupt flag 4                                               */
12157             __IOM uint8_t KRF5 : 1;    /*!< [5..5] Key interrupt flag 5                                               */
12158             __IOM uint8_t KRF6 : 1;    /*!< [6..6] Key interrupt flag 6                                               */
12159             __IOM uint8_t KRF7 : 1;    /*!< [7..7] Key interrupt flag 7                                               */
12160         } KRF_b;
12161     };
12162     __IM uint8_t RESERVED1[3];
12163 
12164     union
12165     {
12166         __IOM uint8_t KRM;             /*!< (@ 0x00000008) KEY Return Mode Register                                   */
12167 
12168         struct
12169         {
12170             __IOM uint8_t KRM0 : 1;    /*!< [0..0] Key interrupt mode control 0                                       */
12171             __IOM uint8_t KRM1 : 1;    /*!< [1..1] Key interrupt mode control 1                                       */
12172             __IOM uint8_t KRM2 : 1;    /*!< [2..2] Key interrupt mode control 2                                       */
12173             __IOM uint8_t KRM3 : 1;    /*!< [3..3] Key interrupt mode control 3                                       */
12174             __IOM uint8_t KRM4 : 1;    /*!< [4..4] Key interrupt mode control 4                                       */
12175             __IOM uint8_t KRM5 : 1;    /*!< [5..5] Key interrupt mode control 5                                       */
12176             __IOM uint8_t KRM6 : 1;    /*!< [6..6] Key interrupt mode control 6                                       */
12177             __IOM uint8_t KRM7 : 1;    /*!< [7..7] Key interrupt mode control 7                                       */
12178         } KRM_b;
12179     };
12180 } R_KINT_Type;                         /*!< Size = 9 (0x9)                                                            */
12181 
12182 /* =========================================================================================================================== */
12183 /* ================                                           R_MMF                                           ================ */
12184 /* =========================================================================================================================== */
12185 
12186 /**
12187  * @brief Memory Mirror Function (R_MMF)
12188  */
12189 
12190 typedef struct                         /*!< (@ 0x40001000) R_MMF Structure                                            */
12191 {
12192     union
12193     {
12194         __IOM uint32_t MMSFR;          /*!< (@ 0x00000000) MemMirror Special Function Register                        */
12195 
12196         struct
12197         {
12198             uint32_t                  : 7;
12199             __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot
12200                                              *   be set in the low-order 7 bits. These bits are fixed to
12201                                              *   0.                                                                        */
12202             uint32_t          : 1;
12203             __OM uint32_t KEY : 8;          /*!< [31..24] MMSFR Key Code                                                   */
12204         } MMSFR_b;
12205     };
12206 
12207     union
12208     {
12209         __IOM uint32_t MMEN;           /*!< (@ 0x00000004) MemMirror Enable Register                                  */
12210 
12211         struct
12212         {
12213             __IOM uint32_t EN : 1;     /*!< [0..0] Memory Mirror Function Enable                                      */
12214             uint32_t          : 23;
12215             __OM uint32_t KEY : 8;     /*!< [31..24] MMEN Key Code                                                    */
12216         } MMEN_b;
12217     };
12218 } R_MMF_Type;                          /*!< Size = 8 (0x8)                                                            */
12219 
12220 /* =========================================================================================================================== */
12221 /* ================                                        R_MPU_MMPU                                         ================ */
12222 /* =========================================================================================================================== */
12223 
12224 /**
12225  * @brief Bus Master MPU (R_MPU_MMPU)
12226  */
12227 
12228 typedef struct                          /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
12229 {
12230     __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers                                   */
12231 } R_MPU_MMPU_Type;                      /*!< Size = 3072 (0xc00)                                                       */
12232 
12233 /* =========================================================================================================================== */
12234 /* ================                                        R_MPU_SMPU                                         ================ */
12235 /* =========================================================================================================================== */
12236 
12237 /**
12238  * @brief Bus Slave MPU (R_MPU_SMPU)
12239  */
12240 
12241 typedef struct                           /*!< (@ 0x40000C00) R_MPU_SMPU Structure                                       */
12242 {
12243     union
12244     {
12245         __IOM uint16_t SMPUCTL;          /*!< (@ 0x00000000) Slave MPU Control Register                                 */
12246 
12247         struct
12248         {
12249             __IOM uint16_t OAD     : 1;  /*!< [0..0] Master Group enable                                                */
12250             __IOM uint16_t PROTECT : 1;  /*!< [1..1] Protection of register                                             */
12251             uint16_t               : 6;
12252             __OM uint16_t KEY      : 8;  /*!< [15..8] Key Code This bit is used to enable or disable rewriting
12253                                           *   of the PROTECT and OAD bit.                                               */
12254         } SMPUCTL_b;
12255     };
12256     __IM uint16_t              RESERVED[7];
12257     __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU                          */
12258 } R_MPU_SMPU_Type;                       /*!< Size = 56 (0x38)                                                          */
12259 
12260 /* =========================================================================================================================== */
12261 /* ================                                        R_MPU_SPMON                                        ================ */
12262 /* =========================================================================================================================== */
12263 
12264 /**
12265  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
12266  */
12267 
12268 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
12269 {
12270     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
12271 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
12272 
12273 /* =========================================================================================================================== */
12274 /* ================                                          R_MSTP                                           ================ */
12275 /* =========================================================================================================================== */
12276 
12277 /**
12278  * @brief System-Module Stop (R_MSTP)
12279  */
12280 
12281 typedef struct                          /*!< (@ 0x40047000) R_MSTP Structure                                           */
12282 {
12283     union
12284     {
12285         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
12286 
12287         struct
12288         {
12289             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12290             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12291             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12292             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12293             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12294             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12295             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12296             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12297             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12298             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12299             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12300                                          *   usage.                                                                    */
12301             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12302                                          *   usage.                                                                    */
12303             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12304                                          *   usage.                                                                    */
12305             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12306                                          *   usage.                                                                    */
12307             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12308                                          *   usage.                                                                    */
12309             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12310                                          *   usage.                                                                    */
12311             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12312                                          *   usage.                                                                    */
12313             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12314                                          *   usage.                                                                    */
12315             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12316                                          *   usage.                                                                    */
12317             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12318                                          *   usage.                                                                    */
12319             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12320                                          *   usage.                                                                    */
12321             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12322                                          *   usage.                                                                    */
12323             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12324                                          *   usage.                                                                    */
12325             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12326                                          *   usage.                                                                    */
12327             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12328                                          *   usage.                                                                    */
12329             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12330                                          *   usage.                                                                    */
12331             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12332                                          *   usage.                                                                    */
12333             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12334                                          *   usage.                                                                    */
12335             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12336                                          *   usage.                                                                    */
12337             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12338                                          *   usage.                                                                    */
12339             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12340                                          *   usage.                                                                    */
12341             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12342                                          *   usage.                                                                    */
12343         } MSTPCRA_b;
12344     };
12345 
12346     union
12347     {
12348         __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */
12349 
12350         struct
12351         {
12352             __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12353             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12354             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12355             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12356             __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12357             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12358             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12359             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12360             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12361             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12362             __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12363                                          *   usage.                                                                    */
12364             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12365                                          *   usage.                                                                    */
12366             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12367                                          *   usage.                                                                    */
12368             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12369                                          *   usage.                                                                    */
12370             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12371                                          *   usage.                                                                    */
12372             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12373                                          *   usage.                                                                    */
12374             __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12375                                          *   usage.                                                                    */
12376             __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12377                                          *   usage.                                                                    */
12378             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12379                                          *   usage.                                                                    */
12380             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12381                                          *   usage.                                                                    */
12382             __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12383                                          *   usage.                                                                    */
12384             __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12385                                          *   usage.                                                                    */
12386             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12387                                          *   usage.                                                                    */
12388             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12389                                          *   usage.                                                                    */
12390             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12391                                          *   usage.                                                                    */
12392             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12393                                          *   usage.                                                                    */
12394             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12395                                          *   usage.                                                                    */
12396             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12397                                          *   usage.                                                                    */
12398             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12399                                          *   usage.                                                                    */
12400             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12401                                          *   usage.                                                                    */
12402             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12403                                          *   usage.                                                                    */
12404             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12405                                          *   usage.                                                                    */
12406         } MSTPCRB_b;
12407     };
12408 
12409     union
12410     {
12411         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
12412 
12413         struct
12414         {
12415             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12416             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12417             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12418             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12419             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12420             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12421             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12422             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12423             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12424             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12425             __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12426                                          *   usage.                                                                    */
12427             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12428                                          *   usage.                                                                    */
12429             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12430                                          *   usage.                                                                    */
12431             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12432                                          *   usage.                                                                    */
12433             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12434                                          *   usage.                                                                    */
12435             __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12436                                          *   usage.                                                                    */
12437             __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12438                                          *   usage.                                                                    */
12439             __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12440                                          *   usage.                                                                    */
12441             __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12442                                          *   usage.                                                                    */
12443             __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12444                                          *   usage.                                                                    */
12445             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12446                                          *   usage.                                                                    */
12447             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12448                                          *   usage.                                                                    */
12449             __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12450                                          *   usage.                                                                    */
12451             __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12452                                          *   usage.                                                                    */
12453             __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12454                                          *   usage.                                                                    */
12455             __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12456                                          *   usage.                                                                    */
12457             __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12458                                          *   usage.                                                                    */
12459             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12460                                          *   usage.                                                                    */
12461             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12462                                          *   usage.                                                                    */
12463             __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12464                                          *   usage.                                                                    */
12465             __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12466                                          *   usage.                                                                    */
12467             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12468                                          *   usage.                                                                    */
12469         } MSTPCRC_b;
12470     };
12471 
12472     union
12473     {
12474         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
12475 
12476         struct
12477         {
12478             __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12479             __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12480             __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12481             __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12482             __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12483             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12484             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12485             __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12486             __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12487             __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12488             __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12489                                          *   usage.                                                                    */
12490             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12491                                          *   usage.                                                                    */
12492             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12493                                          *   usage.                                                                    */
12494             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12495                                          *   usage.                                                                    */
12496             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12497                                          *   usage.                                                                    */
12498             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12499                                          *   usage.                                                                    */
12500             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12501                                          *   usage.                                                                    */
12502             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12503                                          *   usage.                                                                    */
12504             __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12505                                          *   usage.                                                                    */
12506             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12507                                          *   usage.                                                                    */
12508             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12509                                          *   usage.                                                                    */
12510             __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12511                                          *   usage.                                                                    */
12512             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12513                                          *   usage.                                                                    */
12514             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12515                                          *   usage.                                                                    */
12516             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12517                                          *   usage.                                                                    */
12518             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12519                                          *   usage.                                                                    */
12520             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12521                                          *   usage.                                                                    */
12522             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12523                                          *   usage.                                                                    */
12524             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12525                                          *   usage.                                                                    */
12526             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12527                                          *   usage.                                                                    */
12528             __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12529                                          *   usage.                                                                    */
12530             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12531                                          *   usage.                                                                    */
12532         } MSTPCRD_b;
12533     };
12534 
12535     union
12536     {
12537         union
12538         {
12539             __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */
12540 
12541             struct
12542             {
12543                 __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12544                 __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12545                 __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12546                 __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12547                 __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12548                 __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12549                 __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12550                 __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12551                 __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12552                 __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12553                 __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12554                                              *   usage.                                                                    */
12555                 __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12556                                              *   usage.                                                                    */
12557                 __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12558                                              *   usage.                                                                    */
12559                 __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12560                                              *   usage.                                                                    */
12561                 __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12562                                              *   usage.                                                                    */
12563                 __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12564                                              *   usage.                                                                    */
12565                 __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12566                                              *   usage.                                                                    */
12567                 __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12568                                              *   usage.                                                                    */
12569                 __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12570                                              *   usage.                                                                    */
12571                 __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12572                                              *   usage.                                                                    */
12573                 __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12574                                              *   usage.                                                                    */
12575                 __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12576                                              *   usage.                                                                    */
12577                 __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12578                                              *   usage.                                                                    */
12579                 __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12580                                              *   usage.                                                                    */
12581                 __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12582                                              *   usage.                                                                    */
12583                 __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12584                                              *   usage.                                                                    */
12585                 __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12586                                              *   usage.                                                                    */
12587                 __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12588                                              *   usage.                                                                    */
12589                 __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12590                                              *   usage.                                                                    */
12591                 __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12592                                              *   usage.                                                                    */
12593                 __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12594                                              *   usage.                                                                    */
12595                 __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12596                                              *   usage.                                                                    */
12597             } MSTPCRE_b;
12598         };
12599 
12600         union
12601         {
12602             __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */
12603 
12604             struct
12605             {
12606                 __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
12607                 __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
12608                 __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
12609                 uint16_t                : 4;
12610                 __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
12611                 __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
12612             } LSMRWDIS_b;
12613         };
12614     };
12615 } R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */
12616 
12617 /* =========================================================================================================================== */
12618 /* ================                                           R_PDC                                           ================ */
12619 /* =========================================================================================================================== */
12620 
12621 /**
12622  * @brief Parallel Data Capture Unit (R_PDC)
12623  */
12624 
12625 typedef struct                         /*!< (@ 0x40094000) R_PDC Structure                                            */
12626 {
12627     union
12628     {
12629         __IOM uint32_t PCCR0;          /*!< (@ 0x00000000) PDC Control Register 0                                     */
12630 
12631         struct
12632         {
12633             __IOM uint32_t PCKE   : 1; /*!< [0..0] Channel 0 GTCNT Count Clear                                        */
12634             __IOM uint32_t VPS    : 1; /*!< [1..1] VSYNC Signal Polarity Select                                       */
12635             __IOM uint32_t HPS    : 1; /*!< [2..2] HSYNC Signal Polarity Select                                       */
12636             __OM uint32_t  PRST   : 1; /*!< [3..3] PDC Reset                                                          */
12637             __IOM uint32_t DFIE   : 1; /*!< [4..4] Receive Data Ready Interrupt Enable                                */
12638             __IOM uint32_t FEIE   : 1; /*!< [5..5] Frame End Interrupt Enable                                         */
12639             __IOM uint32_t OVIE   : 1; /*!< [6..6] Overrun Interrupt Enable                                           */
12640             __IOM uint32_t UDRIE  : 1; /*!< [7..7] Underrun Interrupt Enable                                          */
12641             __IOM uint32_t VERIE  : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable                */
12642             __IOM uint32_t HERIE  : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable              */
12643             __IOM uint32_t PCKOE  : 1; /*!< [10..10] PCKO Output Enable                                               */
12644             __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select                             */
12645             __IOM uint32_t EDS    : 1; /*!< [14..14] Endian Select                                                    */
12646             uint32_t              : 17;
12647         } PCCR0_b;
12648     };
12649 
12650     union
12651     {
12652         __IOM uint32_t PCCR1;          /*!< (@ 0x00000004) PDC Control Register 1                                     */
12653 
12654         struct
12655         {
12656             __IOM uint32_t PCE : 1;    /*!< [0..0] PDC Operation Enable                                               */
12657             uint32_t           : 31;
12658         } PCCR1_b;
12659     };
12660 
12661     union
12662     {
12663         __IOM uint32_t PCSR;           /*!< (@ 0x00000008) PDC Status Register                                        */
12664 
12665         struct
12666         {
12667             __IM uint32_t  FBSY  : 1;  /*!< [0..0] Frame Busy Flag                                                    */
12668             __IM uint32_t  FEMPF : 1;  /*!< [1..1] FIFO Empty Flag                                                    */
12669             __IOM uint32_t FEF   : 1;  /*!< [2..2] Frame End Flag                                                     */
12670             __IOM uint32_t OVRF  : 1;  /*!< [3..3] Overrun Flag                                                       */
12671             __IOM uint32_t UDRF  : 1;  /*!< [4..4] Underrun Flag                                                      */
12672             __IOM uint32_t VERF  : 1;  /*!< [5..5] Vertical Line Number Setting Error Flag                            */
12673             __IOM uint32_t HERF  : 1;  /*!< [6..6] Horizontal Byte Number Setting Error Flag                          */
12674             uint32_t             : 25;
12675         } PCSR_b;
12676     };
12677 
12678     union
12679     {
12680         __IM uint32_t PCMONR;          /*!< (@ 0x0000000C) PDC Pin Monitor Register                                   */
12681 
12682         struct
12683         {
12684             __IM uint32_t VSYNC : 1;   /*!< [0..0] VSYNC Signal Status Flag                                           */
12685             __IM uint32_t HSYNC : 1;   /*!< [1..1] HSYNC Signal Status Flag                                           */
12686             uint32_t            : 30;
12687         } PCMONR_b;
12688     };
12689 
12690     union
12691     {
12692         __IM uint32_t PCDR;            /*!< (@ 0x00000010) PDC Receive Data Register                                  */
12693 
12694         struct
12695         {
12696             __IM uint32_t PCDR : 32;   /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the
12697                                         *   storage of captured data. The PCDR register is a 4-byte
12698                                         *   space to which the FIFO is mapped, and four bytes of data
12699                                         *   are read from the PCDR register at a time.                                */
12700         } PCDR_b;
12701     };
12702 
12703     union
12704     {
12705         __IOM uint32_t VCR;            /*!< (@ 0x00000014) Vertical Capture Register                                  */
12706 
12707         struct
12708         {
12709             __IOM uint32_t VST : 12;   /*!< [11..0] Vertical Capture Start Line PositionNumber of the line
12710                                         *   where capture is to start.                                                */
12711             uint32_t           : 4;
12712             __IOM uint32_t VSZ : 12;   /*!< [27..16] Vertical Capture Size Number of lines to be captured.            */
12713             uint32_t           : 4;
12714         } VCR_b;
12715     };
12716 
12717     union
12718     {
12719         __IOM uint32_t HCR;            /*!< (@ 0x00000018) Horizontal Capture Register                                */
12720 
12721         struct
12722         {
12723             __IOM uint32_t HST : 12;   /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position
12724                                         *   in bytes where capture is to start.                                       */
12725             uint32_t           : 4;
12726             __IOM uint32_t HSZ : 12;   /*!< [27..16] Horizontal Capture Size Number of bytes to capture
12727                                         *   horizontally.                                                             */
12728             uint32_t : 4;
12729         } HCR_b;
12730     };
12731 } R_PDC_Type;                          /*!< Size = 28 (0x1c)                                                          */
12732 
12733 /* =========================================================================================================================== */
12734 /* ================                                          R_PORT0                                          ================ */
12735 /* =========================================================================================================================== */
12736 
12737 /**
12738  * @brief I/O Ports (R_PORT0)
12739  */
12740 
12741 typedef struct                         /*!< (@ 0x40040000) R_PORT0 Structure                                          */
12742 {
12743     union
12744     {
12745         union
12746         {
12747             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
12748 
12749             struct
12750             {
12751                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
12752                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
12753             } PCNTR1_b;
12754         };
12755 
12756         struct
12757         {
12758             union
12759             {
12760                 __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
12761 
12762                 struct
12763                 {
12764                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
12765                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
12766                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
12767                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
12768                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
12769                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
12770                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
12771                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
12772                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
12773                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
12774                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
12775                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
12776                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
12777                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
12778                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
12779                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
12780                 } PODR_b;
12781             };
12782 
12783             union
12784             {
12785                 __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
12786 
12787                 struct
12788                 {
12789                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
12790                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
12791                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
12792                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
12793                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
12794                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
12795                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
12796                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
12797                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
12798                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
12799                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
12800                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
12801                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
12802                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
12803                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
12804                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
12805                 } PDR_b;
12806             };
12807         };
12808     };
12809 
12810     union
12811     {
12812         union
12813         {
12814             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
12815 
12816             struct
12817             {
12818                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
12819                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
12820             } PCNTR2_b;
12821         };
12822 
12823         struct
12824         {
12825             union
12826             {
12827                 __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
12828 
12829                 struct
12830                 {
12831                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
12832                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
12833                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
12834                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
12835                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
12836                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
12837                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
12838                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
12839                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
12840                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
12841                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
12842                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
12843                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
12844                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
12845                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
12846                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
12847                 } EIDR_b;
12848             };
12849 
12850             union
12851             {
12852                 __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
12853 
12854                 struct
12855                 {
12856                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
12857                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
12858                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
12859                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
12860                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
12861                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
12862                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
12863                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
12864                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
12865                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
12866                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
12867                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
12868                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
12869                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
12870                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
12871                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
12872                 } PIDR_b;
12873             };
12874         };
12875     };
12876 
12877     union
12878     {
12879         union
12880         {
12881             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
12882 
12883             struct
12884             {
12885                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
12886                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
12887             } PCNTR3_b;
12888         };
12889 
12890         struct
12891         {
12892             union
12893             {
12894                 __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
12895 
12896                 struct
12897                 {
12898                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
12899                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
12900                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
12901                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
12902                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
12903                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
12904                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
12905                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
12906                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
12907                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
12908                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
12909                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
12910                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
12911                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
12912                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
12913                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
12914                 } PORR_b;
12915             };
12916 
12917             union
12918             {
12919                 __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
12920 
12921                 struct
12922                 {
12923                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
12924                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
12925                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
12926                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
12927                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
12928                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
12929                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
12930                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
12931                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
12932                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
12933                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
12934                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
12935                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
12936                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
12937                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
12938                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
12939                 } POSR_b;
12940             };
12941         };
12942     };
12943 
12944     union
12945     {
12946         union
12947         {
12948             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
12949 
12950             struct
12951             {
12952                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
12953                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
12954             } PCNTR4_b;
12955         };
12956 
12957         struct
12958         {
12959             union
12960             {
12961                 __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
12962 
12963                 struct
12964                 {
12965                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
12966                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
12967                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
12968                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
12969                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
12970                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
12971                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
12972                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
12973                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
12974                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
12975                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
12976                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
12977                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
12978                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
12979                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
12980                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
12981                 } EORR_b;
12982             };
12983 
12984             union
12985             {
12986                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
12987 
12988                 struct
12989                 {
12990                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
12991                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
12992                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
12993                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
12994                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
12995                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
12996                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
12997                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
12998                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
12999                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
13000                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
13001                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
13002                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
13003                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
13004                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
13005                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
13006                 } EOSR_b;
13007             };
13008         };
13009     };
13010 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
13011 
13012 /* =========================================================================================================================== */
13013 /* ================                                           R_PFS                                           ================ */
13014 /* =========================================================================================================================== */
13015 
13016 /**
13017  * @brief I/O Ports-PFS (R_PFS)
13018  */
13019 
13020 typedef struct                           /*!< (@ 0x40040800) R_PFS Structure                                            */
13021 {
13022     union
13023     {
13024         __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
13025         __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
13026     };
13027 } R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
13028 
13029 /* =========================================================================================================================== */
13030 /* ================                                          R_PMISC                                          ================ */
13031 /* =========================================================================================================================== */
13032 
13033 /**
13034  * @brief I/O Ports-MISC (R_PMISC)
13035  */
13036 
13037 typedef struct                         /*!< (@ 0x40040D00) R_PMISC Structure                                          */
13038 {
13039     union
13040     {
13041         __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
13042 
13043         struct
13044         {
13045             uint8_t                : 4;
13046             __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
13047             __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
13048             uint8_t                : 2;
13049         } PFENET_b;
13050     };
13051     __IM uint8_t RESERVED[2];
13052 
13053     union
13054     {
13055         __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
13056 
13057         struct
13058         {
13059             uint8_t             : 6;
13060             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
13061             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
13062         } PWPR_b;
13063     };
13064     __IM uint8_t RESERVED1;
13065 
13066     union
13067     {
13068         __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
13069 
13070         struct
13071         {
13072             uint8_t             : 6;
13073             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
13074             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
13075         } PWPRS_b;
13076     };
13077     __IM uint16_t RESERVED2[4];
13078     __IM uint8_t  RESERVED3;
13079 
13080     union
13081     {
13082         __IOM uint8_t PRWCNTR;          /*!< (@ 0x0000000F) Port Read Wait Control Register                            */
13083 
13084         struct
13085         {
13086             __IOM uint8_t WAIT : 2;     /*!< [1..0] Wait Cycle Control                                                 */
13087             uint8_t            : 6;
13088         } PRWCNTR_b;
13089     };
13090     __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
13091 } R_PMISC_Type;                         /*!< Size = 40 (0x28)                                                          */
13092 
13093 /* =========================================================================================================================== */
13094 /* ================                                          R_QSPI                                           ================ */
13095 /* =========================================================================================================================== */
13096 
13097 /**
13098  * @brief Quad Serial Peripheral Interface (R_QSPI)
13099  */
13100 
13101 typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
13102 {
13103     union
13104     {
13105         __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */
13106 
13107         struct
13108         {
13109             __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
13110             uint32_t              : 1;
13111             __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
13112             __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
13113             __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
13114                                         *   other than on byte boundaries                                             */
13115             __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
13116                                         *   input to CFGMD3.                                                          */
13117             __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
13118                                         *   the serial interface                                                      */
13119             __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
13120             __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
13121             uint32_t              : 3;
13122             __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
13123             uint32_t              : 16;
13124         } SFMSMD_b;
13125     };
13126 
13127     union
13128     {
13129         __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */
13130 
13131         struct
13132         {
13133             __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
13134             __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
13135             __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
13136             uint32_t              : 26;
13137         } SFMSSC_b;
13138     };
13139 
13140     union
13141     {
13142         __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */
13143 
13144         struct
13145         {
13146             __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
13147                                         *   to the irregularity.)NOTE: When PCLKA multiplied by an
13148                                         *   odd number is selected, the high-level width of the SCK
13149                                         *   signal is longer than the low-level width by 1 x PCLKA
13150                                         *   before duty ratio correction.                                             */
13151             __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
13152                                         *   SCK signal                                                                */
13153             uint32_t : 26;
13154         } SFMSKC_b;
13155     };
13156 
13157     union
13158     {
13159         __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */
13160 
13161         struct
13162         {
13163             __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
13164                                         *   (No combination other than the above is available.)                       */
13165             uint32_t            : 1;
13166             __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
13167             __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
13168             uint32_t            : 24;
13169         } SFMSST_b;
13170     };
13171 
13172     union
13173     {
13174         __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */
13175 
13176         struct
13177         {
13178             __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
13179                                         *   to and from this port is converted to a SPIbus cycle. This
13180                                         *   port is accessible in the direct communication mode (DCOM=1)
13181                                         *   only.Access to this port is ignored in the ROM access mode.               */
13182             uint32_t : 24;
13183         } SFMCOM_b;
13184     };
13185 
13186     union
13187     {
13188         __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */
13189 
13190         struct
13191         {
13192             __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
13193             uint32_t            : 31;
13194         } SFMCMD_b;
13195     };
13196 
13197     union
13198     {
13199         __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */
13200 
13201         struct
13202         {
13203             __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
13204             uint32_t             : 6;
13205             __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
13206                                         *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
13207                                         *   ignored.                                                                  */
13208             uint32_t : 24;
13209         } SFMCST_b;
13210     };
13211     __IM uint32_t RESERVED;
13212 
13213     union
13214     {
13215         __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */
13216 
13217         struct
13218         {
13219             __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
13220             uint32_t              : 24;
13221         } SFMSIC_b;
13222     };
13223 
13224     union
13225     {
13226         __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */
13227 
13228         struct
13229         {
13230             __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
13231             uint32_t              : 2;
13232             __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
13233                                         *   Interface address width is selected 4 bytes.                              */
13234             uint32_t : 27;
13235         } SFMSAC_b;
13236     };
13237 
13238     union
13239     {
13240         __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */
13241 
13242         struct
13243         {
13244             __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
13245                                         *   instructions                                                              */
13246             uint32_t              : 2;
13247             __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
13248             __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
13249             __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
13250             uint32_t              : 16;
13251         } SFMSDC_b;
13252     };
13253     __IM uint32_t RESERVED1;
13254 
13255     union
13256     {
13257         __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */
13258 
13259         struct
13260         {
13261             __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
13262                                         *   is required to be set by software separately.                             */
13263             uint32_t              : 2;
13264             __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
13265                                         *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
13266             uint32_t : 27;
13267         } SFMSPC_b;
13268     };
13269 
13270     union
13271     {
13272         __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */
13273 
13274         struct
13275         {
13276             uint32_t              : 2;
13277             __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
13278             uint32_t              : 29;
13279         } SFMPMD_b;
13280     };
13281     __IM uint32_t RESERVED2[499];
13282 
13283     union
13284     {
13285         __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */
13286 
13287         struct
13288         {
13289             uint32_t                : 26;
13290             __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
13291                                           *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
13292                                           *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
13293         } SFMCNT1_b;
13294     };
13295 } R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */
13296 
13297 /* =========================================================================================================================== */
13298 /* ================                                           R_RTC                                           ================ */
13299 /* =========================================================================================================================== */
13300 
13301 /**
13302  * @brief Realtime Clock (R_RTC)
13303  */
13304 
13305 typedef struct                         /*!< (@ 0x40044000) R_RTC Structure                                            */
13306 {
13307     union
13308     {
13309         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
13310 
13311         struct
13312         {
13313             __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
13314             __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
13315             __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
13316             __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
13317             __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
13318             __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
13319             __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
13320             uint8_t            : 1;
13321         } R64CNT_b;
13322     };
13323     __IM uint8_t RESERVED;
13324 
13325     union
13326     {
13327         union
13328         {
13329             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
13330 
13331             struct
13332             {
13333                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
13334                                           *   counter b7 to b0.                                                         */
13335             } BCNT0_b;
13336         };
13337 
13338         union
13339         {
13340             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
13341 
13342             struct
13343             {
13344                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
13345                                           *   a carry is generated, 1 is added to the tens place.                       */
13346                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
13347                 uint8_t             : 1;
13348             } RSECCNT_b;
13349         };
13350     };
13351     __IM uint8_t RESERVED1;
13352 
13353     union
13354     {
13355         union
13356         {
13357             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
13358 
13359             struct
13360             {
13361                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
13362                                           *   counter b15 to b8.                                                        */
13363             } BCNT1_b;
13364         };
13365 
13366         union
13367         {
13368             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
13369 
13370             struct
13371             {
13372                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
13373                                           *   a carry is generated, 1 is added to the tens place.                       */
13374                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
13375                 uint8_t             : 1;
13376             } RMINCNT_b;
13377         };
13378     };
13379     __IM uint8_t RESERVED2;
13380 
13381     union
13382     {
13383         union
13384         {
13385             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
13386 
13387             struct
13388             {
13389                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
13390                                           *   counter b23 to b16.                                                       */
13391             } BCNT2_b;
13392         };
13393 
13394         union
13395         {
13396             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
13397 
13398             struct
13399             {
13400                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
13401                                          *   carry is generated, 1 is added to the tens place.                         */
13402                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
13403                                          *   the ones place.                                                           */
13404                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
13405                 uint8_t          : 1;
13406             } RHRCNT_b;
13407         };
13408     };
13409     __IM uint8_t RESERVED3;
13410 
13411     union
13412     {
13413         union
13414         {
13415             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
13416 
13417             struct
13418             {
13419                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
13420                                           *   counter b31 to b24.                                                       */
13421             } BCNT3_b;
13422         };
13423 
13424         union
13425         {
13426             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
13427 
13428             struct
13429             {
13430                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
13431                 uint8_t            : 5;
13432             } RWKCNT_b;
13433         };
13434     };
13435     __IM uint8_t RESERVED4;
13436 
13437     union
13438     {
13439         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
13440 
13441         struct
13442         {
13443             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
13444                                         *   is generated, 1 is added to the tens place.                               */
13445             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
13446                                         *   ones place.                                                               */
13447             uint8_t : 2;
13448         } RDAYCNT_b;
13449     };
13450     __IM uint8_t RESERVED5;
13451 
13452     union
13453     {
13454         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
13455 
13456         struct
13457         {
13458             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
13459                                         *   a carry is generated, 1 is added to the tens place.                       */
13460             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
13461                                         *   the ones place.                                                           */
13462             uint8_t : 3;
13463         } RMONCNT_b;
13464     };
13465     __IM uint8_t RESERVED6;
13466 
13467     union
13468     {
13469         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
13470 
13471         struct
13472         {
13473             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
13474                                         *   carry is generated, 1 is added to the tens place.                         */
13475             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
13476                                         *   ones place. When a carry is generated in the tens place,
13477                                         *   1 is added to the hundreds place.                                         */
13478             uint16_t : 8;
13479         } RYRCNT_b;
13480     };
13481 
13482     union
13483     {
13484         union
13485         {
13486             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
13487 
13488             struct
13489             {
13490                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
13491                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
13492             } BCNT0AR_b;
13493         };
13494 
13495         union
13496         {
13497             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
13498 
13499             struct
13500             {
13501                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
13502                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
13503                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
13504             } RSECAR_b;
13505         };
13506     };
13507     __IM uint8_t RESERVED7;
13508 
13509     union
13510     {
13511         union
13512         {
13513             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
13514 
13515             struct
13516             {
13517                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
13518                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
13519             } BCNT1AR_b;
13520         };
13521 
13522         union
13523         {
13524             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
13525 
13526             struct
13527             {
13528                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
13529                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
13530                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
13531             } RMINAR_b;
13532         };
13533     };
13534     __IM uint8_t RESERVED8;
13535 
13536     union
13537     {
13538         union
13539         {
13540             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
13541 
13542             struct
13543             {
13544                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
13545                                             *   counter b23 to b16.                                                       */
13546             } BCNT2AR_b;
13547         };
13548 
13549         union
13550         {
13551             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
13552 
13553             struct
13554             {
13555                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
13556                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
13557                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
13558                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
13559             } RHRAR_b;
13560         };
13561     };
13562     __IM uint8_t RESERVED9;
13563 
13564     union
13565     {
13566         union
13567         {
13568             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
13569 
13570             struct
13571             {
13572                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
13573                                             *   counter b31 to b24.                                                       */
13574             } BCNT3AR_b;
13575         };
13576 
13577         union
13578         {
13579             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
13580 
13581             struct
13582             {
13583                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
13584                 uint8_t            : 4;
13585                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
13586             } RWKAR_b;
13587         };
13588     };
13589     __IM uint8_t RESERVED10;
13590 
13591     union
13592     {
13593         union
13594         {
13595             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
13596 
13597             struct
13598             {
13599                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
13600                                         *   for setting the alarm enable corresponding to 32-bit binary
13601                                         *   counter b7 to b0.                                                         */
13602             } BCNT0AER_b;
13603         };
13604 
13605         union
13606         {
13607             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
13608 
13609             struct
13610             {
13611                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
13612                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
13613                 uint8_t              : 1;
13614                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
13615             } RDAYAR_b;
13616         };
13617     };
13618     __IM uint8_t RESERVED11;
13619 
13620     union
13621     {
13622         union
13623         {
13624             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
13625 
13626             struct
13627             {
13628                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
13629                                         *   for setting the alarm enable corresponding to 32-bit binary
13630                                         *   counter b15 to b8.                                                        */
13631             } BCNT1AER_b;
13632         };
13633 
13634         union
13635         {
13636             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
13637 
13638             struct
13639             {
13640                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
13641                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
13642                 uint8_t             : 2;
13643                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
13644             } RMONAR_b;
13645         };
13646     };
13647     __IM uint8_t RESERVED12;
13648 
13649     union
13650     {
13651         union
13652         {
13653             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
13654 
13655             struct
13656             {
13657                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
13658                                          *   for setting the alarm enable corresponding to 32-bit binary
13659                                          *   counter b23 to b16.                                                       */
13660                 uint16_t : 8;
13661             } BCNT2AER_b;
13662         };
13663 
13664         union
13665         {
13666             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
13667 
13668             struct
13669             {
13670                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
13671                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
13672                 uint16_t            : 8;
13673             } RYRAR_b;
13674         };
13675     };
13676 
13677     union
13678     {
13679         union
13680         {
13681             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
13682 
13683             struct
13684             {
13685                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
13686                                         *   for setting the alarm enable corresponding to 32-bit binary
13687                                         *   counter b31 to b24.                                                       */
13688             } BCNT3AER_b;
13689         };
13690 
13691         union
13692         {
13693             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
13694 
13695             struct
13696             {
13697                 uint8_t           : 7;
13698                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
13699             } RYRAREN_b;
13700         };
13701     };
13702     __IM uint8_t  RESERVED13;
13703     __IM uint16_t RESERVED14;
13704 
13705     union
13706     {
13707         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
13708 
13709         struct
13710         {
13711             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
13712             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
13713             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
13714             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
13715             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
13716         } RCR1_b;
13717     };
13718     __IM uint8_t RESERVED15;
13719 
13720     union
13721     {
13722         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
13723 
13724         struct
13725         {
13726             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
13727             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
13728             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
13729             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
13730             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
13731                                         *   the setting of this bit is disabled.)                                     */
13732             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
13733                                         *   is selected, the setting of this bit is disabled.)                        */
13734             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
13735             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
13736         } RCR2_b;
13737     };
13738     __IM uint8_t  RESERVED16;
13739     __IM uint16_t RESERVED17;
13740 
13741     union
13742     {
13743         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
13744 
13745         struct
13746         {
13747             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
13748             uint8_t              : 6;
13749             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
13750         } RCR4_b;
13751     };
13752     __IM uint8_t RESERVED18;
13753 
13754     union
13755     {
13756         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
13757 
13758         struct
13759         {
13760             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
13761                                         *   clock from the LOCOclock, this bit sets the comparison
13762                                         *   value of the 128-Hz clock cycle.                                          */
13763             uint16_t : 15;
13764         } RFRH_b;
13765     };
13766 
13767     union
13768     {
13769         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
13770 
13771         struct
13772         {
13773             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
13774                                         *   clock from the main clock, this bit sets the comparison
13775                                         *   value of the 128-Hz clock cycle.                                          */
13776         } RFRL_b;
13777     };
13778 
13779     union
13780     {
13781         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
13782 
13783         struct
13784         {
13785             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
13786                                         *   from the prescaler.                                                       */
13787             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
13788         } RADJ_b;
13789     };
13790     __IM uint8_t           RESERVED19;
13791     __IM uint16_t          RESERVED20[8];
13792     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
13793     __IM uint16_t          RESERVED21[5];
13794     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
13795 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
13796 
13797 /* =========================================================================================================================== */
13798 /* ================                                          R_SCI0                                           ================ */
13799 /* =========================================================================================================================== */
13800 
13801 /**
13802  * @brief Serial Communications Interface (R_SCI0)
13803  */
13804 
13805 typedef struct                         /*!< (@ 0x40070000) R_SCI0 Structure                                           */
13806 {
13807     union
13808     {
13809         union
13810         {
13811             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
13812 
13813             struct
13814             {
13815                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
13816                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
13817                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
13818                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
13819                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
13820                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
13821                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
13822             } SMR_b;
13823         };
13824 
13825         union
13826         {
13827             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
13828 
13829             struct
13830             {
13831                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
13832                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
13833                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
13834                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
13835                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
13836                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
13837             } SMR_SMCI_b;
13838         };
13839     };
13840 
13841     union
13842     {
13843         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
13844 
13845         struct
13846         {
13847             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
13848         } BRR_b;
13849     };
13850 
13851     union
13852     {
13853         union
13854         {
13855             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
13856 
13857             struct
13858             {
13859                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
13860                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
13861                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
13862                                          *   mode when SMR.MP = 1)                                                     */
13863                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
13864                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
13865                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
13866                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
13867             } SCR_b;
13868         };
13869 
13870         union
13871         {
13872             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
13873 
13874             struct
13875             {
13876                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
13877                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
13878                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
13879                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
13880                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
13881                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
13882                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
13883             } SCR_SMCI_b;
13884         };
13885     };
13886 
13887     union
13888     {
13889         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
13890 
13891         struct
13892         {
13893             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
13894         } TDR_b;
13895     };
13896 
13897     union
13898     {
13899         union
13900         {
13901             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
13902 
13903             struct
13904             {
13905                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
13906                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
13907                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
13908                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
13909                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
13910                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
13911                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
13912                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
13913             } SSR_b;
13914         };
13915 
13916         union
13917         {
13918             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
13919 
13920             struct
13921             {
13922                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
13923                                          *   multi-processor) and FIFO selected)                                       */
13924                 uint8_t            : 1;
13925                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
13926                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
13927                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
13928                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
13929                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
13930                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
13931             } SSR_FIFO_b;
13932         };
13933 
13934         union
13935         {
13936             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
13937 
13938             struct
13939             {
13940                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
13941                                          *   card interface mode.                                                      */
13942                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
13943                                          *   mode.                                                                     */
13944                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
13945                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
13946                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
13947                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
13948                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
13949                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
13950             } SSR_SMCI_b;
13951         };
13952     };
13953 
13954     union
13955     {
13956         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
13957 
13958         struct
13959         {
13960             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
13961         } RDR_b;
13962     };
13963 
13964     union
13965     {
13966         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
13967 
13968         struct
13969         {
13970             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
13971             uint8_t            : 1;
13972             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
13973                                         *   operation is to be in simple I2C mode.                                    */
13974             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
13975                                         *   setting is invalid and a fixed data length of 8 bits is
13976                                         *   used in modes other than asynchronous mode.Set this bit
13977                                         *   to 1 if operation is to be in simple I2C mode.                            */
13978             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
13979             uint8_t            : 2;
13980             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
13981                                         *   in combination with the SMR.BCP[1:0] bits                                 */
13982         } SCMR_b;
13983     };
13984 
13985     union
13986     {
13987         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
13988 
13989         struct
13990         {
13991             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
13992                                         *   asynchronous mode).                                                       */
13993             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
13994                                         *   mode).                                                                    */
13995             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
13996             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
13997                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
13998             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
13999                                         *   mode)                                                                     */
14000             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
14001                                         *   be 0 without simple I2C mode and asynchronous mode.)In
14002                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
14003                                         *   for RXDn/TxDn input.                                                      */
14004             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
14005                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
14006             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
14007                                         *   in asynchronous mode)                                                     */
14008         } SEMR_b;
14009     };
14010 
14011     union
14012     {
14013         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
14014 
14015         struct
14016         {
14017             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
14018             uint8_t            : 5;
14019         } SNFR_b;
14020     };
14021 
14022     union
14023     {
14024         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
14025 
14026         struct
14027         {
14028             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
14029             uint8_t             : 2;
14030             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
14031                                         *   signal from the on-chip baud rate generator.                              */
14032         } SIMR1_b;
14033     };
14034 
14035     union
14036     {
14037         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
14038 
14039         struct
14040         {
14041             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
14042             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
14043             uint8_t               : 3;
14044             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
14045             uint8_t               : 2;
14046         } SIMR2_b;
14047     };
14048 
14049     union
14050     {
14051         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
14052 
14053         struct
14054         {
14055             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
14056             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
14057             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
14058             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
14059                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
14060             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
14061             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
14062         } SIMR3_b;
14063     };
14064 
14065     union
14066     {
14067         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
14068 
14069         struct
14070         {
14071             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
14072             uint8_t              : 7;
14073         } SISR_b;
14074     };
14075 
14076     union
14077     {
14078         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
14079 
14080         struct
14081         {
14082             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
14083             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
14084             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
14085             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
14086             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
14087             uint8_t              : 1;
14088             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
14089             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
14090         } SPMR_b;
14091     };
14092 
14093     union
14094     {
14095         union
14096         {
14097             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
14098 
14099             struct
14100             {
14101                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
14102             } TDRHL_b;
14103         };
14104 
14105         union
14106         {
14107             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
14108 
14109             struct
14110             {
14111                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
14112                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
14113                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
14114                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
14115                 uint16_t : 6;
14116             } FTDRHL_b;
14117         };
14118 
14119         struct
14120         {
14121             union
14122             {
14123                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
14124 
14125                 struct
14126                 {
14127                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
14128                                              *   mode(including multi-processor) or clock synchronous mode,
14129                                              *   and FIFO selected)                                                        */
14130                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
14131                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
14132                     uint8_t : 6;
14133                 } FTDRH_b;
14134             };
14135 
14136             union
14137             {
14138                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
14139 
14140                 struct
14141                 {
14142                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
14143                                              *   mode(including multi-processor) or clock synchronous mode,
14144                                              *   and FIFO selected)                                                        */
14145                 } FTDRL_b;
14146             };
14147         };
14148     };
14149 
14150     union
14151     {
14152         union
14153         {
14154             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
14155 
14156             struct
14157             {
14158                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
14159             } RDRHL_b;
14160         };
14161 
14162         union
14163         {
14164             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
14165 
14166             struct
14167             {
14168                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
14169                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
14170                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
14171                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
14172                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
14173                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
14174                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
14175                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
14176                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
14177                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
14178                 uint16_t           : 1;
14179             } FRDRHL_b;
14180         };
14181 
14182         struct
14183         {
14184             union
14185             {
14186                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
14187 
14188                 struct
14189                 {
14190                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
14191                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
14192                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
14193                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
14194                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
14195                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
14196                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
14197                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
14198                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
14199                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
14200                     uint8_t           : 1;
14201                 } FRDRH_b;
14202             };
14203 
14204             union
14205             {
14206                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
14207 
14208                 struct
14209                 {
14210                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
14211                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
14212                                              *   When reading both of FRDRH register and FRDRL register,
14213                                              *   please read by an order of the FRDRH register and the FRDRL
14214                                              *   register.                                                                 */
14215                 } FRDRL_b;
14216             };
14217         };
14218     };
14219 
14220     union
14221     {
14222         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
14223 
14224         struct
14225         {
14226             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
14227         } MDDR_b;
14228     };
14229 
14230     union
14231     {
14232         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
14233 
14234         struct
14235         {
14236             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
14237             uint8_t             : 2;
14238             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
14239             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
14240             uint8_t             : 1;
14241             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
14242                                         *   multi-processor)                                                          */
14243             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
14244                                         *   mode(including multi-processor)                                           */
14245         } DCCR_b;
14246     };
14247 
14248     union
14249     {
14250         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
14251 
14252         struct
14253         {
14254             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
14255                                         *   multi-processor) or clock synchronous mode)                               */
14256             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
14257             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
14258             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
14259                                         *   reception data ready, the interrupt request is selected.)                 */
14260             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
14261                                         *   mode(including multi-processor) or clock synchronous mode)                */
14262             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
14263                                         *   mode(including multi-processor) or clock synchronous mode)                */
14264             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
14265                                         *   in asynchronous mode(including multi-processor) or clock
14266                                         *   synchronous mode)                                                         */
14267         } FCR_b;
14268     };
14269 
14270     union
14271     {
14272         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
14273 
14274         struct
14275         {
14276             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
14277                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
14278                                         *   mode(including multi-processor) or clock synchronous mode,
14279                                         *   while FCR.FM=1)                                                           */
14280             uint16_t        : 3;
14281             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
14282                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
14283                                         *   mode(including multi-processor) or clock synchronous mode,
14284                                         *   while FCR.FM=1)                                                           */
14285             uint16_t : 3;
14286         } FDR_b;
14287     };
14288 
14289     union
14290     {
14291         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
14292 
14293         struct
14294         {
14295             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
14296                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
14297             uint16_t           : 1;
14298             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
14299                                         *   a framing error among the receive data stored in the receive
14300                                         *   FIFO data register (FRDRH and FRDRL).                                     */
14301             uint16_t           : 1;
14302             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
14303                                         *   a parity error among the receive data stored in the receive
14304                                         *   FIFO data register (FRDRH and FRDRL).                                     */
14305             uint16_t : 3;
14306         } LSR_b;
14307     };
14308 
14309     union
14310     {
14311         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
14312 
14313         struct
14314         {
14315             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
14316                                         *   wake-up function                                                          */
14317             uint16_t : 7;
14318         } CDR_b;
14319     };
14320 
14321     union
14322     {
14323         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
14324 
14325         struct
14326         {
14327             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
14328                                         *   is shown.)                                                                */
14329             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
14330                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
14331             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
14332                                         *   of SPB2DT is output to TxD terminal.)                                     */
14333             uint8_t            : 1;
14334             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
14335             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
14336             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
14337             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
14338         } SPTR_b;
14339     };
14340 
14341     union
14342     {
14343         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
14344 
14345         struct
14346         {
14347             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
14348             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
14349             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
14350             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
14351         } ACTR_b;
14352     };
14353     __IM uint16_t RESERVED;
14354 
14355     union
14356     {
14357         __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
14358 
14359         struct
14360         {
14361             __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
14362             uint8_t            : 7;
14363         } ESMER_b;
14364     };
14365 
14366     union
14367     {
14368         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
14369 
14370         struct
14371         {
14372             uint8_t             : 1;
14373             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
14374             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
14375             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
14376             uint8_t             : 4;
14377         } CR0_b;
14378     };
14379 
14380     union
14381     {
14382         __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
14383 
14384         struct
14385         {
14386             __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
14387             __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
14388             __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
14389             __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
14390             __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
14391         } CR1_b;
14392     };
14393 
14394     union
14395     {
14396         __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
14397 
14398         struct
14399         {
14400             __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
14401             uint8_t            : 1;
14402             __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
14403             __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
14404         } CR2_b;
14405     };
14406 
14407     union
14408     {
14409         __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
14410 
14411         struct
14412         {
14413             __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
14414             uint8_t            : 7;
14415         } CR3_b;
14416     };
14417 
14418     union
14419     {
14420         __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
14421 
14422         struct
14423         {
14424             __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
14425             __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
14426             uint8_t              : 2;
14427             __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
14428             uint8_t              : 3;
14429         } PCR_b;
14430     };
14431 
14432     union
14433     {
14434         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
14435 
14436         struct
14437         {
14438             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
14439             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
14440             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
14441             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
14442             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
14443             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
14444             uint8_t              : 2;
14445         } ICR_b;
14446     };
14447 
14448     union
14449     {
14450         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
14451 
14452         struct
14453         {
14454             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
14455             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
14456             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
14457             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
14458             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
14459             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
14460             uint8_t            : 2;
14461         } STR_b;
14462     };
14463 
14464     union
14465     {
14466         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
14467 
14468         struct
14469         {
14470             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
14471             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
14472             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
14473             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
14474             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
14475             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
14476             uint8_t              : 2;
14477         } STCR_b;
14478     };
14479     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
14480 
14481     union
14482     {
14483         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
14484 
14485         struct
14486         {
14487             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
14488             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
14489             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
14490             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
14491             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
14492             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
14493             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
14494             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
14495         } CF0CR_b;
14496     };
14497     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
14498     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
14499     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
14500 
14501     union
14502     {
14503         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
14504 
14505         struct
14506         {
14507             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
14508             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
14509             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
14510             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
14511             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
14512             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
14513             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
14514             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
14515         } CF1CR_b;
14516     };
14517     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
14518 
14519     union
14520     {
14521         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
14522 
14523         struct
14524         {
14525             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
14526             uint8_t            : 7;
14527         } TCR_b;
14528     };
14529 
14530     union
14531     {
14532         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
14533 
14534         struct
14535         {
14536             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
14537             uint8_t            : 1;
14538             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
14539             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
14540             uint8_t            : 1;
14541         } TMR_b;
14542     };
14543     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
14544     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
14545 } R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
14546 
14547 /* =========================================================================================================================== */
14548 /* ================                                          R_SDHI0                                          ================ */
14549 /* =========================================================================================================================== */
14550 
14551 /**
14552  * @brief SD/MMC Host Interface (R_SDHI0)
14553  */
14554 
14555 typedef struct                          /*!< (@ 0x40062000) R_SDHI0 Structure                                          */
14556 {
14557     union
14558     {
14559         __IOM uint32_t SD_CMD;          /*!< (@ 0x00000000) Command Type Register                                      */
14560 
14561         struct
14562         {
14563             __IOM uint32_t CMDIDX : 6;  /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
14564                                          *   (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
14565                                          *   SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101              */
14566             __IOM uint32_t ACMD  : 2;   /*!< [7..6] Command Type Select                                                */
14567             __IOM uint32_t RSPTP : 3;   /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
14568                                          *   in normal mode, see section 1.4.10, Example of SD_CMD Register
14569                                          *   Setting to select mode/response type.                                     */
14570             __IOM uint32_t CMDTP : 1;   /*!< [11..11] Data Mode (Command Type)                                         */
14571             __IOM uint32_t CMDRW : 1;   /*!< [12..12] Write/Read Mode (enabled when the command with data
14572                                          *   is handled)                                                               */
14573             __IOM uint32_t TRSTP : 1;   /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
14574                                          *   with data is handled)                                                     */
14575             __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
14576                                          *   transfer)                                                                 */
14577             uint32_t : 16;
14578         } SD_CMD_b;
14579     };
14580     __IM uint32_t RESERVED;
14581 
14582     union
14583     {
14584         __IOM uint32_t SD_ARG;          /*!< (@ 0x00000008) SD Command Argument Register                               */
14585 
14586         struct
14587         {
14588             __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument)              */
14589         } SD_ARG_b;
14590     };
14591 
14592     union
14593     {
14594         __IOM uint32_t SD_ARG1;          /*!< (@ 0x0000000C) SD Command Argument Register 1                             */
14595 
14596         struct
14597         {
14598             __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument)           */
14599             uint32_t               : 16;
14600         } SD_ARG1_b;
14601     };
14602 
14603     union
14604     {
14605         __IOM uint32_t SD_STOP;        /*!< (@ 0x00000010) Data Stop Register                                         */
14606 
14607         struct
14608         {
14609             __IOM uint32_t STP : 1;    /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
14610                                         *   CMD12 is issued to halt the transfer through the SD host
14611                                         *   interface.However, if a command sequence is halted because
14612                                         *   of a communications error or timeout, CMD12 is not issued.
14613                                         *   Although continued buffer access is possible even after
14614                                         *   STP has been set to 1, the buffer access error bit (ERR5
14615                                         *   or ERR4) in SD_INFO2 will be set accordingly.- When STP
14616                                         *   has been set to 1 during transfer for single block write,
14617                                         *   the access end flag is set when SD_BUF becomes emp                        */
14618             uint32_t           : 7;
14619             __IOM uint32_t SEC : 1;    /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
14620                                         *   SD_CMD is set as follows to start the command sequence
14621                                         *   while SEC is set to 1, CMD12 is automatically issued to
14622                                         *   stop multi-block transfer with the number of blocks which
14623                                         *   is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
14624                                         *   = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
14625                                         *   automatically issued, multiple block transfer)When the
14626                                         *   command sequence is halted because of a communications
14627                                         *   error or timeout, CMD12 is not automatically i                            */
14628             uint32_t : 23;
14629         } SD_STOP_b;
14630     };
14631 
14632     union
14633     {
14634         __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000014) Block Count Register                                       */
14635 
14636         struct
14637         {
14638             __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
14639                                             *   of this bit when the CBSY bit in SD_INFO2 is set to 1.                    */
14640         } SD_SECCNT_b;
14641     };
14642 
14643     union
14644     {
14645         __IM uint32_t SD_RSP10;          /*!< (@ 0x00000018) SD Card Response Register 10                               */
14646 
14647         struct
14648         {
14649             __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
14650         } SD_RSP10_b;
14651     };
14652 
14653     union
14654     {
14655         __IM uint32_t SD_RSP1;          /*!< (@ 0x0000001C) SD Card Response Register 1                                */
14656 
14657         struct
14658         {
14659             __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
14660             uint32_t              : 16;
14661         } SD_RSP1_b;
14662     };
14663 
14664     union
14665     {
14666         __IM uint32_t SD_RSP32;          /*!< (@ 0x00000020) SD Card Response Register 32                               */
14667 
14668         struct
14669         {
14670             __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
14671         } SD_RSP32_b;
14672     };
14673 
14674     union
14675     {
14676         __IM uint32_t SD_RSP3;          /*!< (@ 0x00000024) SD Card Response Register 3                                */
14677 
14678         struct
14679         {
14680             __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
14681             uint32_t              : 16;
14682         } SD_RSP3_b;
14683     };
14684 
14685     union
14686     {
14687         __IM uint32_t SD_RSP54;          /*!< (@ 0x00000028) SD Card Response Register 54                               */
14688 
14689         struct
14690         {
14691             __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
14692         } SD_RSP54_b;
14693     };
14694 
14695     union
14696     {
14697         __IM uint32_t SD_RSP5;          /*!< (@ 0x0000002C) SD Card Response Register 5                                */
14698 
14699         struct
14700         {
14701             __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
14702             uint32_t              : 16;
14703         } SD_RSP5_b;
14704     };
14705 
14706     union
14707     {
14708         __IM uint32_t SD_RSP76;          /*!< (@ 0x00000030) SD Card Response Register 76                               */
14709 
14710         struct
14711         {
14712             __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC                           */
14713             uint32_t               : 8;
14714         } SD_RSP76_b;
14715     };
14716 
14717     union
14718     {
14719         __IM uint32_t SD_RSP7;         /*!< (@ 0x00000034) SD Card Response Register 7                                */
14720 
14721         struct
14722         {
14723             __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC                            */
14724             uint32_t              : 24;
14725         } SD_RSP7_b;
14726     };
14727 
14728     union
14729     {
14730         __IOM uint32_t SD_INFO1;        /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1                          */
14731 
14732         struct
14733         {
14734             __IOM uint32_t RSPEND  : 1; /*!< [0..0] Response End Detection                                             */
14735             uint32_t               : 1;
14736             __IOM uint32_t ACEND   : 1; /*!< [2..2] Access End                                                         */
14737             __IOM uint32_t SDCDRM  : 1; /*!< [3..3] SDnCD Card Removal                                                 */
14738             __IOM uint32_t SDCDIN  : 1; /*!< [4..4] SDnCD Card Insertion                                               */
14739             __IM uint32_t  SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state                                          */
14740             uint32_t               : 1;
14741             __IM uint32_t  SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state                                          */
14742             __IOM uint32_t SDD3RM  : 1; /*!< [8..8] SDnDAT3 Card Removal                                               */
14743             __IOM uint32_t SDD3IN  : 1; /*!< [9..9] SDnDAT3 Card Insertion                                             */
14744             __IM uint32_t  SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State                                      */
14745             uint32_t               : 21;
14746         } SD_INFO1_b;
14747     };
14748 
14749     union
14750     {
14751         __IOM uint32_t SD_INFO2;             /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2                          */
14752 
14753         struct
14754         {
14755             __IOM uint32_t CMDE    : 1;      /*!< [0..0] Command Error                                                      */
14756             __IOM uint32_t CRCE    : 1;      /*!< [1..1] CRC Error                                                          */
14757             __IOM uint32_t ENDE    : 1;      /*!< [2..2] END Error                                                          */
14758             __IOM uint32_t DTO     : 1;      /*!< [3..3] Data Timeout                                                       */
14759             __IOM uint32_t ILW     : 1;      /*!< [4..4] SD_BUF Illegal Write Access                                        */
14760             __IOM uint32_t ILR     : 1;      /*!< [5..5] SD_BUF Illegal Read Access                                         */
14761             __IOM uint32_t RSPTO   : 1;      /*!< [6..6] Response Timeout                                                   */
14762             __IM uint32_t  SDD0MON : 1;      /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
14763                                               *   by SD_PORTSEL.                                                            */
14764             __IOM uint32_t BRE          : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
14765             __IOM uint32_t BWE          : 1; /*!< [9..9] SD_BUF Write Enable                                                */
14766             uint32_t                    : 3;
14767             __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
14768                                               *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
14769                                               *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
14770                                               *   cycles of SDCLK have elapsed after setting of the CBSY
14771                                               *   bit to 0 due to completion of the command sequence.                       */
14772             __IM uint32_t  CBSY : 1;         /*!< [14..14] Command Type Register Busy                                       */
14773             __IOM uint32_t ILA  : 1;         /*!< [15..15] Illegal Access Error                                             */
14774             uint32_t            : 16;
14775         } SD_INFO2_b;
14776     };
14777 
14778     union
14779     {
14780         __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register                           */
14781 
14782         struct
14783         {
14784             __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask                                */
14785             uint32_t               : 1;
14786             __IOM uint32_t ACENDM  : 1; /*!< [2..2] Access End Interrupt Request Mask                                  */
14787             __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask                          */
14788             __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask                        */
14789             uint32_t               : 3;
14790             __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask                        */
14791             __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask                      */
14792             uint32_t               : 22;
14793         } SD_INFO1_MASK_b;
14794     };
14795 
14796     union
14797     {
14798         __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register                           */
14799 
14800         struct
14801         {
14802             __IOM uint32_t CMDEM  : 1; /*!< [0..0] Command Error Interrupt Request Mask                               */
14803             __IOM uint32_t CRCEM  : 1; /*!< [1..1] CRC Error Interrupt Request Mask                                   */
14804             __IOM uint32_t ENDEM  : 1; /*!< [2..2] End Bit Error Interrupt Request Mask                               */
14805             __IOM uint32_t DTOM   : 1; /*!< [3..3] Data Timeout Interrupt Request Mask                                */
14806             __IOM uint32_t ILWM   : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask               */
14807             __IOM uint32_t ILRM   : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask                */
14808             __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask                            */
14809             uint32_t              : 1;
14810             __IOM uint32_t BREM   : 1; /*!< [8..8] BRE Interrupt Request Mask                                         */
14811             __IOM uint32_t BWEM   : 1; /*!< [9..9] BWE Interrupt Request Mask                                         */
14812             uint32_t              : 5;
14813             __IOM uint32_t ILAM   : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask                      */
14814             uint32_t              : 16;
14815         } SD_INFO2_MASK_b;
14816     };
14817 
14818     union
14819     {
14820         __IOM uint32_t SD_CLK_CTRL;       /*!< (@ 0x00000048) SD Clock Control Register                                  */
14821 
14822         struct
14823         {
14824             __IOM uint32_t CLKSEL    : 8; /*!< [7..0] SDHI Clock Frequency Select                                        */
14825             __IOM uint32_t CLKEN     : 1; /*!< [8..8] SD/MMC Clock Output Control Enable                                 */
14826             __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable                       */
14827             uint32_t                 : 22;
14828         } SD_CLK_CTRL_b;
14829     };
14830 
14831     union
14832     {
14833         __IOM uint32_t SD_SIZE;        /*!< (@ 0x0000004C) Transfer Data Length Register                              */
14834 
14835         struct
14836         {
14837             __IOM uint32_t LEN : 10;   /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
14838                                         *   and 512 bytes for the transfer of single blocks.In cases
14839                                         *   of multiple block transfer with automatic issuing of CMD12
14840                                         *   (CMD18 and CMD25), the only specifiable transfer data size
14841                                         *   is 512 bytes. Furthermore, in cases of multiple block transfer
14842                                         *   without automatic issuing of CMD12, as well as 512 bytes,
14843                                         *   32, 64, 128, and 256 bytes are specifiable. However, in
14844                                         *   the reading of 32, 64, 128, and 256 bytes for the transfer
14845                                         *   of multiple blocks, this is restricted to mult                            */
14846             uint32_t : 22;
14847         } SD_SIZE_b;
14848     };
14849 
14850     union
14851     {
14852         __IOM uint32_t SD_OPTION;        /*!< (@ 0x00000050) SD Card Access Control Option Register                     */
14853 
14854         struct
14855         {
14856             __IOM uint32_t CTOP     : 4; /*!< [3..0] Card Detect Time Counter                                           */
14857             __IOM uint32_t TOP      : 4; /*!< [7..4] Timeout Counter                                                    */
14858             __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
14859                                           *   timeout, software reset should be executed to terminate
14860                                           *   command sequence.                                                         */
14861             uint32_t              : 4;
14862             __IOM uint32_t WIDTH8 : 1;   /*!< [13..13] Bus Widthsee b15, WIDTH bit                                      */
14863             uint32_t              : 1;
14864             __IOM uint32_t WIDTH  : 1;   /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
14865                                           *   and when the SOFT_RST.SDRST flag is 0.                                    */
14866             uint32_t : 16;
14867         } SD_OPTION_b;
14868     };
14869     __IM uint32_t RESERVED1;
14870 
14871     union
14872     {
14873         __IM uint32_t SD_ERR_STS1;      /*!< (@ 0x00000058) SD Error Status Register 1                                 */
14874 
14875         struct
14876         {
14877             __IM uint32_t CMDE0 : 1;    /*!< [0..0] Command Error 0NOTE: other than a response to a command
14878                                          *   issued within a command sequence                                          */
14879             __IM uint32_t CMDE1 : 1;    /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
14880                                          *   setting a command index in SD_CMD, this is Indicated in
14881                                          *   CMDE0.                                                                    */
14882             __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
14883                                          *   a command issued within a command sequence                                */
14884             __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
14885                                          *   issued by setting a command index in SD_CMD, this is indicated
14886                                          *   in RSPLENE0.                                                              */
14887             __IM uint32_t RDLENE   : 1; /*!< [4..4] Read Data Length Error                                             */
14888             __IM uint32_t CRCLENE  : 1; /*!< [5..5] CRC Status Token Length Error                                      */
14889             uint32_t               : 2;
14890             __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
14891                                          *   command issued within a command sequence                                  */
14892             __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
14893                                          *   by setting a command index in SD_CMD, this is indicated
14894                                          *   in RSPCRCE0.                                                              */
14895             __IM uint32_t RDCRCE : 1;   /*!< [10..10] Read Data CRC Error                                              */
14896             __IM uint32_t CRCTKE : 1;   /*!< [11..11] CRC Status Token Error                                           */
14897             __IM uint32_t CRCTK  : 3;   /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
14898                                          *   value is 010b)                                                            */
14899             uint32_t : 17;
14900         } SD_ERR_STS1_b;
14901     };
14902 
14903     union
14904     {
14905         __IM uint32_t SD_ERR_STS2;      /*!< (@ 0x0000005C) SD Error Status Register 2                                 */
14906 
14907         struct
14908         {
14909             __IM uint32_t RSPTO0   : 1; /*!< [0..0] Response Timeout 0                                                 */
14910             __IM uint32_t RSPTO1   : 1; /*!< [1..1] Response Timeout 1                                                 */
14911             __IM uint32_t BSYTO0   : 1; /*!< [2..2] Busy Timeout 0                                                     */
14912             __IM uint32_t BSYTO1   : 1; /*!< [3..3] Busy Timeout 1                                                     */
14913             __IM uint32_t RDTO     : 1; /*!< [4..4] Read Data Timeout                                                  */
14914             __IM uint32_t CRCTO    : 1; /*!< [5..5] CRC Status Token Timeout                                           */
14915             __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout                                      */
14916             uint32_t               : 25;
14917         } SD_ERR_STS2_b;
14918     };
14919 
14920     union
14921     {
14922         __IOM uint32_t SD_BUF0;         /*!< (@ 0x00000060) SD Buffer Register                                         */
14923 
14924         struct
14925         {
14926             __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
14927                                          *   data is written to this register. When reading from the
14928                                          *   SD card, the read data is read from this register. This
14929                                          *   register is internally connected to two 512-byte buffers.If
14930                                          *   both buffers are not empty when executing multiple block
14931                                          *   read, SD/MMC clock is stopped to suspend receiving data.
14932                                          *   When one of buffers is empty, SD/MMC clock is supplied
14933                                          *   to resume receiving data.                                                 */
14934         } SD_BUF0_b;
14935     };
14936     __IM uint32_t RESERVED2;
14937 
14938     union
14939     {
14940         __IOM uint32_t SDIO_MODE;      /*!< (@ 0x00000068) SDIO Mode Control Register                                 */
14941 
14942         struct
14943         {
14944             __IOM uint32_t INTEN  : 1; /*!< [0..0] SDIO Mode                                                          */
14945             uint32_t              : 1;
14946             __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
14947             uint32_t              : 5;
14948             __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO AbortNOTE: See manual                                         */
14949             __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual                                    */
14950             uint32_t              : 22;
14951         } SDIO_MODE_b;
14952     };
14953 
14954     union
14955     {
14956         __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1                             */
14957 
14958         struct
14959         {
14960             __IOM uint32_t IOIRQ   : 1; /*!< [0..0] SDIO Interrupt Status                                              */
14961             uint32_t               : 13;
14962             __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual                              */
14963             __IOM uint32_t EXWT    : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual                                 */
14964             uint32_t               : 16;
14965         } SDIO_INFO1_b;
14966     };
14967 
14968     union
14969     {
14970         __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register                         */
14971 
14972         struct
14973         {
14974             __IOM uint32_t IOIRQM   : 1; /*!< [0..0] IOIRQ Interrupt Mask Control                                       */
14975             uint32_t                : 13;
14976             __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control                           */
14977             __IOM uint32_t EXWTM    : 1; /*!< [15..15] EXWT Interrupt Request Mask Control                              */
14978             uint32_t                : 16;
14979         } SDIO_INFO1_MASK_b;
14980     };
14981     __IM uint32_t RESERVED3[79];
14982 
14983     union
14984     {
14985         __IOM uint32_t SD_DMAEN;       /*!< (@ 0x000001B0) DMA Mode Enable Register                                   */
14986 
14987         struct
14988         {
14989             uint32_t             : 1;
14990             __IOM uint32_t DMAEN : 1;  /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
14991             uint32_t             : 30;
14992         } SD_DMAEN_b;
14993     };
14994     __IM uint32_t RESERVED4[3];
14995 
14996     union
14997     {
14998         __IOM uint32_t SOFT_RST;       /*!< (@ 0x000001C0) Software Reset Register                                    */
14999 
15000         struct
15001         {
15002             __IOM uint32_t SDRST : 1;  /*!< [0..0] Software Reset of SD I/F Unit                                      */
15003             uint32_t             : 31;
15004         } SOFT_RST_b;
15005     };
15006     __IM uint32_t RESERVED5[2];
15007 
15008     union
15009     {
15010         __IOM uint32_t SDIF_MODE;      /*!< (@ 0x000001CC) SD Interface Mode Setting Register                         */
15011 
15012         struct
15013         {
15014             uint32_t               : 8;
15015             __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands)                             */
15016             uint32_t               : 23;
15017         } SDIF_MODE_b;
15018     };
15019     __IM uint32_t RESERVED6[4];
15020 
15021     union
15022     {
15023         __IOM uint32_t EXT_SWAP;       /*!< (@ 0x000001E0) Swap Control Register                                      */
15024 
15025         struct
15026         {
15027             uint32_t             : 6;
15028             __IOM uint32_t BWSWP : 1;  /*!< [6..6] SD_BUF0 Swap Write                                                 */
15029             __IOM uint32_t BRSWP : 1;  /*!< [7..7] SD_BUF0 Swap Read                                                  */
15030             uint32_t             : 24;
15031         } EXT_SWAP_b;
15032     };
15033 } R_SDHI0_Type;                        /*!< Size = 484 (0x1e4)                                                        */
15034 
15035 /* =========================================================================================================================== */
15036 /* ================                                          R_SPI0                                           ================ */
15037 /* =========================================================================================================================== */
15038 
15039 /**
15040  * @brief Serial Peripheral Interface (R_SPI0)
15041  */
15042 
15043 typedef struct                         /*!< (@ 0x40072000) R_SPI0 Structure                                           */
15044 {
15045     union
15046     {
15047         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
15048 
15049         struct
15050         {
15051             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
15052             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
15053             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
15054             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
15055             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
15056             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
15057             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
15058             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
15059         } SPCR_b;
15060     };
15061 
15062     union
15063     {
15064         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
15065 
15066         struct
15067         {
15068             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
15069             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
15070             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
15071             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
15072             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
15073             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
15074             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
15075             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
15076         } SSLP_b;
15077     };
15078 
15079     union
15080     {
15081         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
15082 
15083         struct
15084         {
15085             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
15086             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
15087             uint8_t             : 2;
15088             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
15089             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
15090             uint8_t             : 2;
15091         } SPPCR_b;
15092     };
15093 
15094     union
15095     {
15096         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
15097 
15098         struct
15099         {
15100             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
15101             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
15102             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
15103             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
15104             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
15105             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
15106             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
15107             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
15108         } SPSR_b;
15109     };
15110 
15111     union
15112     {
15113         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
15114         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
15115         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
15116     };
15117 
15118     union
15119     {
15120         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
15121 
15122         struct
15123         {
15124             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
15125                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
15126                                         *   changed in accordance with the sequence length that is
15127                                         *   set in these bits. The relationship among the setting of
15128                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
15129                                         *   referenced by the RSPI is shown above. However, the RSPI
15130                                         *   in slave mode always references SPCMD0.                                   */
15131             uint8_t : 5;
15132         } SPSCR_b;
15133     };
15134 
15135     union
15136     {
15137         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
15138 
15139         struct
15140         {
15141             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
15142             uint8_t            : 1;
15143             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
15144             uint8_t            : 1;
15145         } SPSSR_b;
15146     };
15147 
15148     union
15149     {
15150         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
15151 
15152         struct
15153         {
15154             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
15155         } SPBR_b;
15156     };
15157 
15158     union
15159     {
15160         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
15161 
15162         struct
15163         {
15164             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
15165             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
15166             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
15167             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
15168             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
15169             uint8_t              : 1;
15170         } SPDCR_b;
15171     };
15172 
15173     union
15174     {
15175         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
15176 
15177         struct
15178         {
15179             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
15180             uint8_t             : 5;
15181         } SPCKD_b;
15182     };
15183 
15184     union
15185     {
15186         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
15187 
15188         struct
15189         {
15190             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
15191             uint8_t             : 5;
15192         } SSLND_b;
15193     };
15194 
15195     union
15196     {
15197         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
15198 
15199         struct
15200         {
15201             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
15202             uint8_t             : 5;
15203         } SPND_b;
15204     };
15205 
15206     union
15207     {
15208         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
15209 
15210         struct
15211         {
15212             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
15213             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
15214             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
15215             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
15216             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
15217             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
15218         } SPCR2_b;
15219     };
15220 
15221     union
15222     {
15223         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
15224 
15225         struct
15226         {
15227             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
15228             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
15229             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
15230             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
15231             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
15232             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
15233             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
15234             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
15235             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
15236             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
15237         } SPCMD_b[8];
15238     };
15239 
15240     union
15241     {
15242         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
15243 
15244         struct
15245         {
15246             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
15247             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
15248             uint8_t            : 6;
15249         } SPDCR2_b;
15250     };
15251 
15252     union
15253     {
15254         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
15255 
15256         struct
15257         {
15258             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
15259             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
15260             uint8_t              : 2;
15261             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
15262             uint8_t              : 3;
15263         } SPCR3_b;
15264     };
15265     __IM uint16_t RESERVED;
15266     __IM uint32_t RESERVED1[6];
15267     __IM uint16_t RESERVED2;
15268 
15269     union
15270     {
15271         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
15272 
15273         struct
15274         {
15275             uint16_t              : 4;
15276             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
15277             uint16_t              : 3;
15278             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
15279             uint16_t              : 1;
15280             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
15281         } SPPR_b;
15282     };
15283 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
15284 
15285 /* =========================================================================================================================== */
15286 /* ================                                          R_SRAM                                           ================ */
15287 /* =========================================================================================================================== */
15288 
15289 /**
15290  * @brief SRAM (R_SRAM)
15291  */
15292 
15293 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
15294 {
15295     union
15296     {
15297         __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
15298 
15299         struct
15300         {
15301             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
15302             uint8_t           : 7;
15303         } PARIOAD_b;
15304     };
15305     __IM uint8_t RESERVED[3];
15306 
15307     union
15308     {
15309         __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
15310 
15311         struct
15312         {
15313             __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
15314             __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
15315         } SRAMPRCR_b;
15316     };
15317     __IM uint8_t  RESERVED1[3];
15318     __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
15319     __IM uint8_t  RESERVED2[3];
15320 
15321     union
15322     {
15323         __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
15324 
15325         struct
15326         {
15327             __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
15328             __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
15329         } SRAMPRCR2_b;
15330     };
15331     __IM uint8_t RESERVED3[179];
15332 
15333     union
15334     {
15335         __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
15336 
15337         struct
15338         {
15339             __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
15340             uint8_t              : 6;
15341         } ECCMODE_b;
15342     };
15343 
15344     union
15345     {
15346         __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
15347 
15348         struct
15349         {
15350             __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
15351             uint8_t               : 7;
15352         } ECC2STS_b;
15353     };
15354 
15355     union
15356     {
15357         __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
15358 
15359         struct
15360         {
15361             __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
15362             uint8_t               : 7;
15363         } ECC1STSEN_b;
15364     };
15365 
15366     union
15367     {
15368         __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
15369 
15370         struct
15371         {
15372             __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
15373             uint8_t               : 7;
15374         } ECC1STS_b;
15375     };
15376 
15377     union
15378     {
15379         __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
15380 
15381         struct
15382         {
15383             __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
15384             __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
15385         } ECCPRCR_b;
15386     };
15387     __IM uint8_t RESERVED4[11];
15388 
15389     union
15390     {
15391         __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
15392 
15393         struct
15394         {
15395             __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
15396             __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
15397         } ECCPRCR2_b;
15398     };
15399     __IM uint8_t RESERVED5[3];
15400 
15401     union
15402     {
15403         __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
15404 
15405         struct
15406         {
15407             __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
15408             uint8_t              : 7;
15409         } ECCETST_b;
15410     };
15411     __IM uint8_t RESERVED6[3];
15412 
15413     union
15414     {
15415         __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
15416 
15417         struct
15418         {
15419             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
15420             uint8_t           : 7;
15421         } ECCOAD_b;
15422     };
15423 } R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
15424 
15425 /* =========================================================================================================================== */
15426 /* ================                                           R_SRC                                           ================ */
15427 /* =========================================================================================================================== */
15428 
15429 /**
15430  * @brief Sampling Rate Converter (R_SRC)
15431  */
15432 
15433 typedef struct                           /*!< (@ 0x40048000) R_SRC Structure                                            */
15434 {
15435     union
15436     {
15437         __IOM uint32_t SRCFCTR[5552];    /*!< (@ 0x00000000) Filter Coefficient Table [0..5551]                         */
15438 
15439         struct
15440         {
15441             __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value.                                */
15442             uint32_t               : 10;
15443         } SRCFCTR_b[5552];
15444     };
15445     __IM uint32_t RESERVED[588];
15446 
15447     union
15448     {
15449         __OM uint32_t SRCID;           /*!< (@ 0x00005FF0) Input Data Register                                        */
15450 
15451         struct
15452         {
15453             __OM uint32_t SRCID : 32;  /*!< [31..0] SRCID is a 32-bit writ-only register that is used to
15454                                         *   input the data before sampling rate conversion. All the
15455                                         *   bits are read as 0.                                                       */
15456         } SRCID_b;
15457     };
15458 
15459     union
15460     {
15461         __IM uint32_t SRCOD;           /*!< (@ 0x00005FF4) Output Data Register                                       */
15462 
15463         struct
15464         {
15465             __IM uint32_t SRCOD : 32;  /*!< [31..0] SRCOD is a 32-bit read-only register used to output
15466                                         *   the data after sampling rate conversion. The data in the
15467                                         *   16-stage output data FIFO is read through SRCOD. When the
15468                                         *   number of data in the output data FIFO is zero after the
15469                                         *   start of conversion, the value previously read is read
15470                                         *   again.                                                                    */
15471         } SRCOD_b;
15472     };
15473 
15474     union
15475     {
15476         __IOM uint16_t SRCIDCTRL;      /*!< (@ 0x00005FF8) Input Data Control Register                                */
15477 
15478         struct
15479         {
15480             __IOM uint16_t IFTRG : 2;  /*!< [1..0] Input FIFO Data Triggering Number                                  */
15481             uint16_t             : 6;
15482             __IOM uint16_t IEN   : 1;  /*!< [8..8] Input FIFO Empty Interrupt Enable                                  */
15483             __IOM uint16_t IED   : 1;  /*!< [9..9] Input Data Endian                                                  */
15484             uint16_t             : 6;
15485         } SRCIDCTRL_b;
15486     };
15487 
15488     union
15489     {
15490         __IOM uint16_t SRCODCTRL;      /*!< (@ 0x00005FFA) Output Data Control Register                               */
15491 
15492         struct
15493         {
15494             __IOM uint16_t OFTRG : 2;  /*!< [1..0] Output FIFO Data Trigger Number                                    */
15495             uint16_t             : 6;
15496             __IOM uint16_t OEN   : 1;  /*!< [8..8] Output Data FIFO Full Interrupt Enable                             */
15497             __IOM uint16_t OED   : 1;  /*!< [9..9] Output Data Endian                                                 */
15498             __IOM uint16_t OCH   : 1;  /*!< [10..10] Output Data Channel Exchange                                     */
15499             uint16_t             : 5;
15500         } SRCODCTRL_b;
15501     };
15502 
15503     union
15504     {
15505         __IOM uint16_t SRCCTRL;        /*!< (@ 0x00005FFC) Control Register                                           */
15506 
15507         struct
15508         {
15509             __IOM uint16_t OFS    : 3; /*!< [2..0] Output Sampling Rate                                               */
15510             uint16_t              : 1;
15511             __IOM uint16_t IFS    : 4; /*!< [7..4] Input Sampling Rate                                                */
15512             __IOM uint16_t CL     : 1; /*!< [8..8] Internal Work Memory Clear                                         */
15513             __IOM uint16_t FL     : 1; /*!< [9..9] Internal Work Memory Flush                                         */
15514             __IOM uint16_t OVEN   : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable                      */
15515             __IOM uint16_t UDEN   : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable                      */
15516             __IOM uint16_t SRCEN  : 1; /*!< [12..12] Module Enable                                                    */
15517             __IOM uint16_t CEEN   : 1; /*!< [13..13] Conversion End Interrupt Enable                                  */
15518             uint16_t              : 1;
15519             __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable                           */
15520         } SRCCTRL_b;
15521     };
15522 
15523     union
15524     {
15525         __IOM uint16_t SRCSTAT;        /*!< (@ 0x00005FFE) Status Register                                            */
15526 
15527         struct
15528         {
15529             __IOM uint16_t OINT : 1;   /*!< [0..0] Output Data FIFO Full Interrupt Request Flag                       */
15530             __IOM uint16_t IINT : 1;   /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag                       */
15531             __IOM uint16_t OVF  : 1;   /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag                  */
15532             __IOM uint16_t UDF  : 1;   /*!< [3..3] Output FIFO Underflow Interrupt Request Flag                       */
15533             __IM uint16_t  FLF  : 1;   /*!< [4..4] Flush Processing Status Flag                                       */
15534             __IOM uint16_t CEF  : 1;   /*!< [5..5] Conversion End Flag                                                */
15535             uint16_t            : 1;
15536             __IOM uint16_t IFDN : 4;   /*!< [10..7] Input FIFO Data CountIndicates the number of data units
15537                                         *   in the input FIFO.                                                        */
15538             __IOM uint16_t OFDN : 5;   /*!< [15..11] Output FIFO Data CountIndicates the number of data
15539                                         *   units in the output FIFO.                                                 */
15540         } SRCSTAT_b;
15541     };
15542 } R_SRC_Type;                          /*!< Size = 24576 (0x6000)                                                     */
15543 
15544 /* =========================================================================================================================== */
15545 /* ================                                          R_SSI0                                           ================ */
15546 /* =========================================================================================================================== */
15547 
15548 /**
15549  * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
15550  */
15551 
15552 typedef struct                         /*!< (@ 0x4004E000) R_SSI0 Structure                                           */
15553 {
15554     union
15555     {
15556         __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
15557 
15558         struct
15559         {
15560             __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
15561             __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
15562             uint32_t            : 1;
15563             __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
15564                                         *   of outputting serial data is rewritten to 0 but data transmission
15565                                         *   is not stopped. Write dummy data to the SSIFTDR not to
15566                                         *   generate a transmit underflow because the number of data
15567                                         *   in the transmit FIFO is decreasing.                                       */
15568             __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
15569             __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
15570             __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
15571             __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
15572             __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
15573             __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
15574             __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
15575             __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
15576                                         *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
15577                                         *   are prohibited.                                                           */
15578             uint32_t           : 1;
15579             __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
15580                                         *   bit clock frequency/2 fs.                                                 */
15581             __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
15582             __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
15583             uint32_t             : 1;
15584             __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
15585             __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
15586             __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
15587             __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
15588             __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
15589             __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
15590             uint32_t             : 1;
15591         } SSICR_b;
15592     };
15593 
15594     union
15595     {
15596         __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
15597 
15598         struct
15599         {
15600             __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
15601             __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
15602             __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
15603             __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
15604             __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
15605             uint32_t             : 18;
15606             __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
15607             __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
15608                                         *   Writable only to clear the flag. Confirm the value is 1
15609                                         *   and then write 0.                                                         */
15610             __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
15611                                         *   Writable only to clear the flag. Confirm the value is 1
15612                                         *   and then write 0.                                                         */
15613             __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
15614                                         *   Writable only to clear the flag. Confirm the value is 1
15615                                         *   and then write 0.                                                         */
15616             __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
15617                                         *   Writable only to clear the flag. Confirm the value is 1
15618                                         *   and then write 0.                                                         */
15619             uint32_t : 2;
15620         } SSISR_b;
15621     };
15622     __IM uint32_t RESERVED[2];
15623 
15624     union
15625     {
15626         __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
15627 
15628         struct
15629         {
15630             __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
15631             __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
15632             __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
15633                                         *   clearing either the RDF flag (see the description of the
15634                                         *   RDF bit for details) or RIE bit.                                          */
15635             __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
15636                                         *   clearing either the TDE flag (see the description of the
15637                                         *   TDE bit for details) or TIE bit.                                          */
15638             __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
15639             __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
15640                                         *   are the number of empty stages in SSIFTDR at which the
15641                                         *   TDE flag is set.                                                          */
15642             uint32_t              : 3;
15643             __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
15644             uint32_t              : 4;
15645             __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
15646             uint32_t              : 14;
15647             __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
15648         } SSIFCR_b;
15649     };
15650 
15651     union
15652     {
15653         __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
15654 
15655         struct
15656         {
15657             __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
15658                                         *   is a 32-byte FIFO register, the maximum number of data
15659                                         *   bytes that can be read from it while the RDF flag is 1
15660                                         *   is indicated in the RDC[3:0] flags. If reading data from
15661                                         *   the SSIFRDR register is continued after all the data is
15662                                         *   read, undefined values will be read.                                      */
15663             uint32_t          : 7;
15664             __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
15665                                         *   units stored in SSIFRDR)                                                  */
15666             uint32_t           : 2;
15667             __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
15668                                         *   is a 32-byte FIFO register, the maximum number of bytes
15669                                         *   that can be written to it while the TDE flag is 1 is 8
15670                                         *   - TDC[3:0]. If writing data to the SSIFTDR register is
15671                                         *   continued after all the data is written, writing will be
15672                                         *   invalid and an overflow occurs.                                           */
15673             uint32_t          : 7;
15674             __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
15675                                         *   data units stored in SSIFTDR)                                             */
15676             uint32_t : 2;
15677         } SSIFSR_b;
15678     };
15679 
15680     union
15681     {
15682         union
15683         {
15684             __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
15685 
15686             struct
15687             {
15688                 __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
15689                                              *   eight stages of 32-bit registers for storing data to be
15690                                              *   serially transmitted. NOTE: that when the SSIFTDR register
15691                                              *   is full of data (32 bytes), the next data cannot be written
15692                                              *   to it. If writing is attempted, it will be ignored and
15693                                              *   an overflow occurs.                                                       */
15694             } SSIFTDR_b;
15695         };
15696         __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
15697         __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
15698     };
15699 
15700     union
15701     {
15702         union
15703         {
15704             __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
15705 
15706             struct
15707             {
15708                 __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
15709                                              *   stages of 32-bit registers for storing serially received
15710                                              *   data.                                                                     */
15711             } SSIFRDR_b;
15712         };
15713         __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
15714         __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
15715     };
15716 
15717     union
15718     {
15719         __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
15720 
15721         struct
15722         {
15723             __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
15724             uint32_t               : 6;
15725             __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
15726             __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
15727                                          *   Idle Status                                                               */
15728             uint32_t : 22;
15729         } SSIOFR_b;
15730     };
15731 
15732     union
15733     {
15734         __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
15735 
15736         struct
15737         {
15738             __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
15739             uint32_t            : 3;
15740             __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
15741             uint32_t            : 19;
15742         } SSISCR_b;
15743     };
15744 } R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
15745 
15746 /* =========================================================================================================================== */
15747 /* ================                                         R_SYSTEM                                          ================ */
15748 /* =========================================================================================================================== */
15749 
15750 /**
15751  * @brief System Pins (R_SYSTEM)
15752  */
15753 
15754 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
15755 {
15756     __IM uint32_t RESERVED[3];
15757 
15758     union
15759     {
15760         __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
15761 
15762         struct
15763         {
15764             uint16_t            : 14;
15765             __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
15766             __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
15767         } SBYCR_b;
15768     };
15769     __IM uint16_t RESERVED1;
15770     __IM uint32_t RESERVED2[3];
15771 
15772     union
15773     {
15774         __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
15775 
15776         struct
15777         {
15778             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage.           */
15779             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage.           */
15780             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage.           */
15781             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage.           */
15782             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage.           */
15783             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage.           */
15784             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage.           */
15785             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage.           */
15786             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage.           */
15787             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage.           */
15788             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for
15789                                          *   usage.                                                                    */
15790             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for
15791                                          *   usage.                                                                    */
15792             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for
15793                                          *   usage.                                                                    */
15794             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for
15795                                          *   usage.                                                                    */
15796             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for
15797                                          *   usage.                                                                    */
15798             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for
15799                                          *   usage.                                                                    */
15800             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for
15801                                          *   usage.                                                                    */
15802             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for
15803                                          *   usage.                                                                    */
15804             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for
15805                                          *   usage.                                                                    */
15806             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for
15807                                          *   usage.                                                                    */
15808             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for
15809                                          *   usage.                                                                    */
15810             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for
15811                                          *   usage.                                                                    */
15812             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for
15813                                          *   usage.                                                                    */
15814             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for
15815                                          *   usage.                                                                    */
15816             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for
15817                                          *   usage.                                                                    */
15818             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for
15819                                          *   usage.                                                                    */
15820             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for
15821                                          *   usage.                                                                    */
15822             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for
15823                                          *   usage.                                                                    */
15824             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for
15825                                          *   usage.                                                                    */
15826             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for
15827                                          *   usage.                                                                    */
15828             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for
15829                                          *   usage.                                                                    */
15830             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for
15831                                          *   usage.                                                                    */
15832         } MSTPCRA_b;
15833     };
15834 
15835     union
15836     {
15837         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
15838 
15839         struct
15840         {
15841             __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
15842             uint32_t            : 1;
15843             __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
15844             uint32_t            : 1;
15845             __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
15846             uint32_t            : 1;
15847             __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
15848             uint32_t            : 1;
15849             __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
15850             uint32_t            : 5;
15851             __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
15852             uint32_t            : 1;
15853             __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
15854             uint32_t            : 1;
15855         } SCKDIVCR_b;
15856     };
15857 
15858     union
15859     {
15860         __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
15861 
15862         struct
15863         {
15864             uint8_t           : 4;
15865             __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
15866             uint8_t           : 1;
15867         } SCKDIVCR2_b;
15868     };
15869     __IM uint8_t RESERVED3;
15870 
15871     union
15872     {
15873         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
15874 
15875         struct
15876         {
15877             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
15878             uint8_t             : 5;
15879         } SCKSCR_b;
15880     };
15881     __IM uint8_t RESERVED4;
15882 
15883     union
15884     {
15885         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
15886 
15887         struct
15888         {
15889             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
15890             uint16_t                : 2;
15891             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
15892             uint16_t                : 3;
15893             __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
15894                                           *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
15895                                           *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
15896                                           *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
15897                                           *   111011: x30.0                                                             */
15898             uint16_t : 2;
15899         } PLLCCR_b;
15900     };
15901 
15902     union
15903     {
15904         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
15905 
15906         struct
15907         {
15908             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
15909             uint8_t              : 7;
15910         } PLLCR_b;
15911     };
15912 
15913     union
15914     {
15915         __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
15916 
15917         struct
15918         {
15919             __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
15920             uint8_t              : 1;
15921             __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
15922         } PLLCCR2_b;
15923     };
15924     __IM uint32_t RESERVED5;
15925 
15926     union
15927     {
15928         __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
15929 
15930         struct
15931         {
15932             __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
15933             uint8_t               : 7;
15934         } BCKCR_b;
15935     };
15936 
15937     union
15938     {
15939         __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
15940 
15941         struct
15942         {
15943             __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
15944                                         *   is prohibited when SCKDIVCR.ICK selects division by 1 and
15945                                         *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
15946                                         *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
15947             uint8_t : 7;
15948         } MEMWAIT_b;
15949     };
15950 
15951     union
15952     {
15953         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
15954 
15955         struct
15956         {
15957             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
15958             uint8_t             : 7;
15959         } MOSCCR_b;
15960     };
15961     __IM uint8_t  RESERVED6;
15962     __IM uint16_t RESERVED7;
15963 
15964     union
15965     {
15966         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
15967 
15968         struct
15969         {
15970             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
15971             uint8_t             : 7;
15972         } HOCOCR_b;
15973     };
15974 
15975     union
15976     {
15977         __IOM uint8_t HOCOCR2;         /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
15978                                         *                  2                                                          */
15979 
15980         struct
15981         {
15982             __IOM uint8_t HCFRQ0 : 2;  /*!< [1..0] HOCO Frequency Setting 0                                           */
15983             uint8_t              : 1;
15984             __IOM uint8_t HCFRQ1 : 3;  /*!< [5..3] HOCO Frequency Setting 1                                           */
15985             uint8_t              : 2;
15986         } HOCOCR2_b;
15987     };
15988 
15989     union
15990     {
15991         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
15992 
15993         struct
15994         {
15995             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
15996             uint8_t             : 7;
15997         } MOCOCR_b;
15998     };
15999 
16000     union
16001     {
16002         __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
16003 
16004         struct
16005         {
16006             __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
16007             uint8_t             : 7;
16008         } FLLCR1_b;
16009     };
16010 
16011     union
16012     {
16013         __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
16014 
16015         struct
16016         {
16017             __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
16018                                           *   FLL reference clock select                                                */
16019             uint16_t : 5;
16020         } FLLCR2_b;
16021     };
16022 
16023     union
16024     {
16025         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
16026 
16027         struct
16028         {
16029             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
16030                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
16031                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
16032             uint8_t             : 2;
16033             __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
16034             uint8_t             : 1;
16035             __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
16036             __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
16037             uint8_t             : 1;
16038         } OSCSF_b;
16039     };
16040     __IM uint8_t RESERVED8;
16041 
16042     union
16043     {
16044         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
16045 
16046         struct
16047         {
16048             __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
16049             uint8_t              : 1;
16050             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
16051             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
16052         } CKOCR_b;
16053     };
16054 
16055     union
16056     {
16057         __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
16058 
16059         struct
16060         {
16061             __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
16062             uint8_t              : 3;
16063             __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
16064         } TRCKCR_b;
16065     };
16066 
16067     union
16068     {
16069         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
16070 
16071         struct
16072         {
16073             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
16074             uint8_t              : 6;
16075             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
16076         } OSTDCR_b;
16077     };
16078 
16079     union
16080     {
16081         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
16082 
16083         struct
16084         {
16085             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
16086             uint8_t             : 7;
16087         } OSTDSR_b;
16088     };
16089     __IM uint16_t RESERVED9;
16090     __IM uint32_t RESERVED10;
16091 
16092     union
16093     {
16094         __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
16095 
16096         struct
16097         {
16098             __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
16099             uint16_t                 : 2;
16100             __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select                                           */
16101             uint16_t                 : 3;
16102             __IOM uint16_t PLL2MUL   : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select                       */
16103             uint16_t                 : 2;
16104         } PLL2CCR_b;
16105     };
16106 
16107     union
16108     {
16109         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
16110 
16111         struct
16112         {
16113             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
16114             uint8_t               : 7;
16115         } PLL2CR_b;
16116     };
16117     __IM uint8_t RESERVED11;
16118 
16119     union
16120     {
16121         __IOM uint8_t LPOPT;             /*!< (@ 0x0000004C) Lower Power Operation Control Register                     */
16122 
16123         struct
16124         {
16125             __IOM uint8_t MPUDIS : 1;    /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
16126                                           *   (valid only when LPOPTEN = 1)                                             */
16127             __IOM uint8_t DCLKDIS   : 2; /*!< [2..1] Debug Clock Disable Control                                        */
16128             __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
16129                                           *   clock (valid only when LPOPT.LPOPTEN = 1)                                 */
16130             uint8_t               : 3;
16131             __IOM uint8_t LPOPTEN : 1;   /*!< [7..7] Lower Power Operation Enable                                       */
16132         } LPOPT_b;
16133     };
16134     __IM uint8_t  RESERVED12;
16135     __IM uint16_t RESERVED13;
16136 
16137     union
16138     {
16139         __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
16140 
16141         struct
16142         {
16143             __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
16144             uint8_t                 : 4;
16145             __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
16146         } SLCDSCKCR_b;
16147     };
16148     __IM uint8_t RESERVED14;
16149 
16150     union
16151     {
16152         __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
16153 
16154         struct
16155         {
16156             __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
16157             uint8_t               : 7;
16158         } EBCKOCR_b;
16159     };
16160 
16161     union
16162     {
16163         __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
16164 
16165         struct
16166         {
16167             __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
16168             uint8_t               : 7;
16169         } SDCKOCR_b;
16170     };
16171     __IM uint32_t RESERVED15[3];
16172     __IM uint8_t  RESERVED16;
16173 
16174     union
16175     {
16176         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
16177 
16178         struct
16179         {
16180             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
16181                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
16182                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
16183                                          +126 0111_1111 : +127These bits are added to original MOCO
16184                                          *   trimming bits                                                             */
16185         } MOCOUTCR_b;
16186     };
16187 
16188     union
16189     {
16190         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
16191 
16192         struct
16193         {
16194             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
16195                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
16196                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
16197                                          +126 0111_1111 : +127These bits are added to original HOCO
16198                                          *   trimming bits                                                             */
16199         } HOCOUTCR_b;
16200     };
16201     __IM uint8_t  RESERVED17;
16202     __IM uint32_t RESERVED18[2];
16203 
16204     union
16205     {
16206         __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB Clock Division Control Register                        */
16207 
16208         struct
16209         {
16210             __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select                                 */
16211             uint8_t                : 5;
16212         } USBCKDIVCR_b;
16213     };
16214 
16215     union
16216     {
16217         union
16218         {
16219             __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register                  */
16220 
16221             struct
16222             {
16223                 __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select                          */
16224                 uint8_t                 : 5;
16225             } OCTACKDIVCR_b;
16226         };
16227 
16228         union
16229         {
16230             __IOM uint8_t SCISPICKDIVCR;       /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register                    */
16231 
16232             struct
16233             {
16234                 __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select                          */
16235                 uint8_t                   : 5;
16236             } SCISPICKDIVCR_b;
16237         };
16238     };
16239 
16240     union
16241     {
16242         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
16243 
16244         struct
16245         {
16246             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
16247             uint8_t                  : 5;
16248         } CANFDCKDIVCR_b;
16249     };
16250 
16251     union
16252     {
16253         union
16254         {
16255             __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000006F) GPT Clock Division Control Register                        */
16256 
16257             struct
16258             {
16259                 __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select                                 */
16260                 uint8_t                : 5;
16261             } GPTCKDIVCR_b;
16262         };
16263 
16264         union
16265         {
16266             __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 Clock Division Control Register                      */
16267 
16268             struct
16269             {
16270                 __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
16271                 uint8_t                  : 5;
16272             } USB60CKDIVCR_b;
16273         };
16274     };
16275 
16276     union
16277     {
16278         union
16279         {
16280             __IOM uint8_t CECCKDIVCR;       /*!< (@ 0x00000070) CEC Clock Division Control Register                        */
16281 
16282             struct
16283             {
16284                 __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select                                 */
16285                 uint8_t                : 5;
16286             } CECCKDIVCR_b;
16287         };
16288 
16289         union
16290         {
16291             __IOM uint8_t IICCKDIVCR;       /*!< (@ 0x00000070) IIC Clock Division Control Register                        */
16292 
16293             struct
16294             {
16295                 __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select                                 */
16296                 uint8_t                : 5;
16297             } IICCKDIVCR_b;
16298         };
16299     };
16300 
16301     union
16302     {
16303         __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
16304 
16305         struct
16306         {
16307             __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
16308             uint8_t                : 5;
16309         } I3CCKDIVCR_b;
16310     };
16311     __IM uint16_t RESERVED19;
16312 
16313     union
16314     {
16315         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
16316 
16317         struct
16318         {
16319             __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
16320             uint8_t                 : 3;
16321             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
16322             __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
16323         } USBCKCR_b;
16324     };
16325 
16326     union
16327     {
16328         union
16329         {
16330             __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI Clock Control Register                           */
16331 
16332             struct
16333             {
16334                 __IOM uint8_t OCTACKSEL  : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select                            */
16335                 uint8_t                  : 3;
16336                 __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request                        */
16337                 __IM uint8_t  OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag               */
16338             } OCTACKCR_b;
16339         };
16340 
16341         union
16342         {
16343             __IOM uint8_t SCISPICKCR;           /*!< (@ 0x00000075) SCI SPI Clock Control Register                             */
16344 
16345             struct
16346             {
16347                 __IOM uint8_t SCISPICKSEL  : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select                            */
16348                 uint8_t                    : 3;
16349                 __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request                        */
16350                 __IM uint8_t  SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag               */
16351             } SCISPICKCR_b;
16352         };
16353     };
16354 
16355     union
16356     {
16357         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
16358 
16359         struct
16360         {
16361             __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
16362             uint8_t                   : 3;
16363             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
16364             __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
16365         } CANFDCKCR_b;
16366     };
16367 
16368     union
16369     {
16370         union
16371         {
16372             __IOM uint8_t GPTCKCR;           /*!< (@ 0x00000077) GPT Clock Control Register                                 */
16373 
16374             struct
16375             {
16376                 __IOM uint8_t GPTCKSEL  : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select                                   */
16377                 uint8_t                 : 3;
16378                 __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request                               */
16379                 __IM uint8_t  GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag                      */
16380             } GPTCKCR_b;
16381         };
16382 
16383         union
16384         {
16385             __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
16386 
16387             struct
16388             {
16389                 __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
16390                 uint8_t                   : 2;
16391                 __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
16392                 __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
16393             } USB60CKCR_b;
16394         };
16395     };
16396 
16397     union
16398     {
16399         union
16400         {
16401             __IOM uint8_t CECCKCR;           /*!< (@ 0x00000078) CEC Clock Control Register                                 */
16402 
16403             struct
16404             {
16405                 __IOM uint8_t CECCKSEL  : 3; /*!< [2..0] CEC clock (CECCLK) Source Select                                   */
16406                 uint8_t                 : 3;
16407                 __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request                               */
16408                 __IM uint8_t  CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag                      */
16409             } CECCKCR_b;
16410         };
16411 
16412         union
16413         {
16414             __IOM uint8_t IICCKCR;           /*!< (@ 0x00000078) IIC Clock Control Register                                 */
16415 
16416             struct
16417             {
16418                 __IOM uint8_t IICCKSEL  : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select                                   */
16419                 uint8_t                 : 3;
16420                 __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request                               */
16421                 __IM uint8_t  IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag                      */
16422             } IICCKCR_b;
16423         };
16424     };
16425 
16426     union
16427     {
16428         __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */
16429 
16430         struct
16431         {
16432             __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
16433             uint8_t                 : 3;
16434             __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
16435             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
16436         } I3CCKCR_b;
16437     };
16438     __IM uint16_t RESERVED20;
16439     __IM uint32_t RESERVED21[3];
16440 
16441     union
16442     {
16443         __IOM uint32_t SNZREQCR1;         /*!< (@ 0x00000088) Snooze Request Control Register 1                          */
16444 
16445         struct
16446         {
16447             __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request                               */
16448             __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request                               */
16449             __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request                               */
16450             uint32_t                 : 29;
16451         } SNZREQCR1_b;
16452     };
16453     __IM uint32_t RESERVED22;
16454     __IM uint16_t RESERVED23;
16455 
16456     union
16457     {
16458         __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
16459 
16460         struct
16461         {
16462             __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
16463                                          *   than in asynchronous mode.                                                */
16464             __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
16465             uint8_t                : 5;
16466             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
16467         } SNZCR_b;
16468     };
16469     __IM uint8_t RESERVED24;
16470 
16471     union
16472     {
16473         __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
16474 
16475         struct
16476         {
16477             __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
16478             __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
16479             __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
16480             __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
16481             __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
16482             __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
16483             __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
16484             __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
16485                                           *   to 1 other than in asynchronous mode.                                     */
16486         } SNZEDCR_b;
16487     };
16488 
16489     union
16490     {
16491         __IOM uint8_t SNZEDCR1;          /*!< (@ 0x00000095) Snooze End Control Register 1                              */
16492 
16493         struct
16494         {
16495             __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable                                   */
16496             uint8_t                 : 7;
16497         } SNZEDCR1_b;
16498     };
16499     __IM uint16_t RESERVED25;
16500 
16501     union
16502     {
16503         __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
16504 
16505         struct
16506         {
16507             __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
16508             __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
16509             __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
16510             __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
16511             __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
16512             __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
16513             __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
16514             __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
16515             __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
16516             __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
16517             __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
16518             __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
16519             __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
16520             __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
16521             __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
16522             __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
16523             uint32_t                  : 1;
16524             __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
16525             uint32_t                  : 4;
16526             __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
16527                                             *   request                                                                   */
16528             __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
16529                                             *   request                                                                   */
16530             __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
16531             __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
16532             uint32_t                  : 2;
16533             __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
16534                                             *   request                                                                   */
16535             __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
16536                                             *   snooze request                                                            */
16537             __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
16538                                             *   snooze request                                                            */
16539             uint32_t : 1;
16540         } SNZREQCR_b;
16541     };
16542     __IM uint16_t RESERVED26;
16543 
16544     union
16545     {
16546         __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
16547 
16548         struct
16549         {
16550             __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
16551             uint8_t              : 3;
16552             __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
16553             uint8_t              : 3;
16554         } FLSTOP_b;
16555     };
16556 
16557     union
16558     {
16559         __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
16560 
16561         struct
16562         {
16563             __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
16564             uint8_t            : 6;
16565         } PSMCR_b;
16566     };
16567 
16568     union
16569     {
16570         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
16571 
16572         struct
16573         {
16574             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
16575             uint8_t              : 2;
16576             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
16577             uint8_t              : 3;
16578         } OPCCR_b;
16579     };
16580     __IM uint8_t RESERVED27;
16581 
16582     union
16583     {
16584         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
16585 
16586         struct
16587         {
16588             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
16589             uint8_t            : 4;
16590         } MOSCWTCR_b;
16591     };
16592     __IM uint8_t RESERVED28[2];
16593 
16594     union
16595     {
16596         __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
16597 
16598         struct
16599         {
16600             __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
16601                                         *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
16602             uint8_t : 5;
16603         } HOCOWTCR_b;
16604     };
16605     __IM uint16_t RESERVED29[2];
16606 
16607     union
16608     {
16609         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
16610 
16611         struct
16612         {
16613             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
16614             uint8_t               : 3;
16615             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
16616             uint8_t               : 3;
16617         } SOPCCR_b;
16618     };
16619     __IM uint8_t  RESERVED30;
16620     __IM uint32_t RESERVED31[5];
16621 
16622     union
16623     {
16624         __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
16625 
16626         struct
16627         {
16628             __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
16629                                         *   only to clear the flag. Confirm the value is 1 and then
16630                                         *   write 0.                                                                  */
16631             __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
16632                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
16633             __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
16634                                         *   the flag. Confirm the value is 1 and then write 0.                        */
16635             uint16_t             : 5;
16636             __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
16637                                         *   to clear the flag. Confirm the value is 1 and then write
16638                                         *   0.                                                                        */
16639             __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
16640                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
16641             __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
16642                                         *   to clear the flag. Confirm the value is 1 and then write
16643                                         *   0.                                                                        */
16644             __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
16645                                         *   to clear the flag. Confirm the value is 1 and then write
16646                                         *   0.                                                                        */
16647             __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
16648                                         *   the flag. Confirm the value is 1 and then write 0.                        */
16649             __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
16650             uint16_t             : 1;
16651             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
16652         } RSTSR1_b;
16653     };
16654     __IM uint16_t RESERVED32;
16655     __IM uint32_t RESERVED33[3];
16656 
16657     union
16658     {
16659         __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
16660 
16661         struct
16662         {
16663             __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
16664                                           *   (UCLK).                                                                   */
16665             uint8_t : 7;
16666         } USBCKCR_ALT_b;
16667     };
16668 
16669     union
16670     {
16671         __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
16672                                            *                  Register                                                   */
16673 
16674         struct
16675         {
16676             __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
16677             uint8_t                  : 6;
16678             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
16679         } SDADCCKCR_b;
16680     };
16681     __IM uint16_t RESERVED34;
16682     __IM uint32_t RESERVED35[3];
16683 
16684     union
16685     {
16686         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
16687 
16688         struct
16689         {
16690             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
16691             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
16692             uint8_t              : 5;
16693         } LVD1CR1_b;
16694     };
16695 
16696     union
16697     {
16698         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
16699 
16700         struct
16701         {
16702             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
16703                                         *   0 can be written to this bit. After writing 0 to this bit,
16704                                         *   it takes 2 system clock cycles for the bit to be read as
16705                                         *   0.                                                                        */
16706             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
16707             uint8_t          : 6;
16708         } LVD1SR_b;
16709     };
16710 
16711     union
16712     {
16713         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
16714 
16715         struct
16716         {
16717             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
16718             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
16719             uint8_t              : 5;
16720         } LVD2CR1_b;
16721     };
16722 
16723     union
16724     {
16725         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
16726 
16727         struct
16728         {
16729             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
16730                                         *   0 can be written to this bit. After writing 0 to this bit,
16731                                         *   it takes 2 system clock cycles for the bit to be read as
16732                                         *   0.                                                                        */
16733             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
16734             uint8_t          : 6;
16735         } LVD2SR_b;
16736     };
16737     __IM uint32_t RESERVED36[183];
16738 
16739     union
16740     {
16741         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
16742                                           *                  Register                                                   */
16743 
16744         struct
16745         {
16746             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
16747             uint32_t                : 1;
16748             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
16749             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
16750             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
16751             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
16752             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
16753             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
16754             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
16755             __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09                                        */
16756             uint32_t                : 1;
16757             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
16758             __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12                                      */
16759             uint32_t                : 3;
16760             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
16761             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
16762             uint32_t                : 14;
16763         } CGFSAR_b;
16764     };
16765     __IM uint32_t RESERVED37;
16766 
16767     union
16768     {
16769         __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
16770 
16771         struct
16772         {
16773             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
16774             uint32_t               : 1;
16775             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
16776             uint32_t               : 1;
16777             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
16778             uint32_t               : 3;
16779             __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
16780             __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
16781             uint32_t               : 22;
16782         } LPMSAR_b;
16783     };
16784 
16785     union
16786     {
16787         union
16788         {
16789             __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
16790 
16791             struct
16792             {
16793                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
16794                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
16795                 uint32_t               : 30;
16796             } LVDSAR_b;
16797         };
16798 
16799         union
16800         {
16801             __IOM uint32_t RSTSAR;          /*!< (@ 0x000003CC) Reset Security Attribution Register                        */
16802 
16803             struct
16804             {
16805                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
16806                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
16807                 __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
16808                 uint32_t               : 29;
16809             } RSTSAR_b;
16810         };
16811     };
16812 
16813     union
16814     {
16815         __IOM uint32_t BBFSAR;           /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
16816 
16817         struct
16818         {
16819             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
16820             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
16821             __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
16822             uint32_t                : 13;
16823             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
16824             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
16825             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
16826             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19                                      */
16827             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
16828             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21                                      */
16829             __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22                                      */
16830             __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23                                      */
16831             uint32_t                : 8;
16832         } BBFSAR_b;
16833     };
16834     __IM uint32_t RESERVED38[3];
16835 
16836     union
16837     {
16838         __IOM uint32_t DPFSAR;          /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
16839                                          *                  Register                                                   */
16840 
16841         struct
16842         {
16843             __IOM uint32_t DPFSA0 : 1;  /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
16844                                          *   0                                                                         */
16845             __IOM uint32_t DPFSA1 : 1;  /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
16846                                          *   1                                                                         */
16847             __IOM uint32_t DPFSA2 : 1;  /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
16848                                          *   2                                                                         */
16849             __IOM uint32_t DPFSA3 : 1;  /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
16850                                          *   3                                                                         */
16851             __IOM uint32_t DPFSA4 : 1;  /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
16852                                          *   4                                                                         */
16853             __IOM uint32_t DPFSA5 : 1;  /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
16854                                          *   5                                                                         */
16855             __IOM uint32_t DPFSA6 : 1;  /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
16856                                          *   6                                                                         */
16857             __IOM uint32_t DPFSA7 : 1;  /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
16858                                          *   7                                                                         */
16859             __IOM uint32_t DPFSA8 : 1;  /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
16860                                          *   8                                                                         */
16861             __IOM uint32_t DPFSA9 : 1;  /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
16862                                          *   9                                                                         */
16863             __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
16864                                          *   10                                                                        */
16865             __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
16866                                          *   11                                                                        */
16867             __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
16868                                          *   12                                                                        */
16869             __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
16870                                          *   13                                                                        */
16871             __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
16872                                          *   14                                                                        */
16873             __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
16874                                          *   15                                                                        */
16875             __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
16876                                          *   16                                                                        */
16877             __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
16878                                          *   17                                                                        */
16879             __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
16880                                          *   18                                                                        */
16881             __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
16882                                          *   19                                                                        */
16883             __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
16884                                          *   20                                                                        */
16885             uint32_t               : 3;
16886             __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
16887                                          *   24                                                                        */
16888             uint32_t               : 1;
16889             __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
16890                                          *   26                                                                        */
16891             __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
16892                                          *   27                                                                        */
16893             uint32_t : 4;
16894         } DPFSAR_b;
16895     };
16896     __IM uint32_t RESERVED39[6];
16897     __IM uint16_t RESERVED40;
16898 
16899     union
16900     {
16901         __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
16902 
16903         struct
16904         {
16905             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
16906                                         *   generation circuit.                                                       */
16907             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
16908                                         *   modes, the low power consumption modes and the battery
16909                                         *   backup function.                                                          */
16910             uint16_t            : 1;
16911             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
16912             __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
16913             uint16_t            : 3;
16914             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
16915         } PRCR_b;
16916     };
16917 
16918     union
16919     {
16920         __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
16921 
16922         struct
16923         {
16924             __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
16925             uint8_t               : 4;
16926             __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
16927             __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
16928         } DPSBYCR_b;
16929     };
16930 
16931     union
16932     {
16933         __IOM uint8_t DPSWCR;          /*!< (@ 0x00000401) Deep Standby Wait Control Register                         */
16934 
16935         struct
16936         {
16937             __IOM uint8_t WTSTS : 6;   /*!< [5..0] Deep Software Wait Standby Time Setting Bit                        */
16938             uint8_t             : 2;
16939         } DPSWCR_b;
16940     };
16941 
16942     union
16943     {
16944         __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
16945 
16946         struct
16947         {
16948             __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
16949             __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
16950             __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
16951             __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
16952             __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
16953             __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
16954             __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
16955             __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
16956         } DPSIER0_b;
16957     };
16958 
16959     union
16960     {
16961         __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
16962 
16963         struct
16964         {
16965             __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
16966             __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
16967             __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
16968             __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
16969             __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
16970             __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
16971             __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
16972             __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
16973         } DPSIER1_b;
16974     };
16975 
16976     union
16977     {
16978         __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
16979 
16980         struct
16981         {
16982             __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
16983             __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
16984             __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
16985             __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
16986             __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
16987             uint8_t                : 3;
16988         } DPSIER2_b;
16989     };
16990 
16991     union
16992     {
16993         __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
16994 
16995         struct
16996         {
16997             __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
16998             __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
16999             __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
17000             __IOM uint8_t DAGT3IE  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable                   */
17001             uint8_t                : 4;
17002         } DPSIER3_b;
17003     };
17004 
17005     union
17006     {
17007         __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
17008 
17009         struct
17010         {
17011             __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
17012             __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
17013             __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
17014             __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
17015             __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
17016             __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
17017             __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
17018             __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
17019         } DPSIFR0_b;
17020     };
17021 
17022     union
17023     {
17024         __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
17025 
17026         struct
17027         {
17028             __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
17029             __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
17030             __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
17031             __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
17032             __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
17033             __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
17034             __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
17035             __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
17036         } DPSIFR1_b;
17037     };
17038 
17039     union
17040     {
17041         __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
17042 
17043         struct
17044         {
17045             __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
17046             __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
17047             __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
17048             __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
17049             __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
17050             uint8_t                : 3;
17051         } DPSIFR2_b;
17052     };
17053 
17054     union
17055     {
17056         __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
17057 
17058         struct
17059         {
17060             __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
17061             __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
17062             __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
17063             __IOM uint8_t DAGT3IF  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag                            */
17064             uint8_t                : 4;
17065         } DPSIFR3_b;
17066     };
17067 
17068     union
17069     {
17070         __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
17071 
17072         struct
17073         {
17074             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
17075             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
17076             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
17077             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
17078             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
17079             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
17080             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
17081             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
17082         } DPSIEGR0_b;
17083     };
17084 
17085     union
17086     {
17087         __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
17088 
17089         struct
17090         {
17091             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
17092             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
17093             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
17094             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
17095             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
17096             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
17097             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
17098             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
17099         } DPSIEGR1_b;
17100     };
17101 
17102     union
17103     {
17104         __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
17105 
17106         struct
17107         {
17108             __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
17109             __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
17110             uint8_t                : 2;
17111             __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
17112             uint8_t                : 3;
17113         } DPSIEGR2_b;
17114     };
17115     __IM uint8_t RESERVED41;
17116 
17117     union
17118     {
17119         __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
17120 
17121         struct
17122         {
17123             __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
17124             uint8_t             : 6;
17125             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
17126         } SYOCDCR_b;
17127     };
17128 
17129     union
17130     {
17131         __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
17132 
17133         struct
17134         {
17135             __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
17136             uint8_t             : 6;
17137         } STCONR_b;
17138     };
17139 
17140     union
17141     {
17142         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
17143 
17144         struct
17145         {
17146             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
17147                                         *   the flag. Confirm the value is 1 and then write 0.                        */
17148             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
17149                                         *   to clear the flag. Confirm the value is 1 and then write
17150                                         *   0.                                                                        */
17151             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
17152                                         *   to clear the flag. Confirm the value is 1 and then write
17153                                         *   0.                                                                        */
17154             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
17155                                         *   to clear the flag. Confirm the value is 1 and then write
17156                                         *   0.                                                                        */
17157             uint8_t               : 3;
17158             __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
17159                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
17160         } RSTSR0_b;
17161     };
17162 
17163     union
17164     {
17165         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
17166 
17167         struct
17168         {
17169             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
17170             uint8_t            : 7;
17171         } RSTSR2_b;
17172     };
17173     __IM uint8_t RESERVED42;
17174 
17175     union
17176     {
17177         __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
17178                                         *                  Register                                                   */
17179 
17180         struct
17181         {
17182             uint8_t                 : 3;
17183             __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
17184             __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
17185             __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
17186             __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
17187                                           *   Enable                                                                    */
17188         } MOMCR_b;
17189     };
17190     __IM uint16_t RESERVED43;
17191 
17192     union
17193     {
17194         __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
17195 
17196         struct
17197         {
17198             __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
17199             uint8_t            : 6;
17200         } FWEPROR_b;
17201     };
17202 
17203     union
17204     {
17205         union
17206         {
17207             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
17208 
17209             struct
17210             {
17211                 uint8_t             : 5;
17212                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
17213                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
17214                 uint8_t             : 1;
17215             } LVCMPCR_b;
17216         };
17217 
17218         union
17219         {
17220             __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
17221 
17222             struct
17223             {
17224                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
17225                                             *   drop in voltage)                                                          */
17226                 uint8_t             : 2;
17227                 __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
17228             } LVD1CMPCR_b;
17229         };
17230     };
17231 
17232     union
17233     {
17234         union
17235         {
17236             __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
17237 
17238             struct
17239             {
17240                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
17241                                             *   fall in voltage)                                                          */
17242                 __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
17243                                             *   fall in voltage)                                                          */
17244             } LVDLVLR_b;
17245         };
17246 
17247         union
17248         {
17249             __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
17250 
17251             struct
17252             {
17253                 __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
17254                                             *   drop in voltage)                                                          */
17255                 uint8_t             : 4;
17256                 __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
17257             } LVD2CMPCR_b;
17258         };
17259     };
17260     __IM uint8_t RESERVED44;
17261 
17262     union
17263     {
17264         __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
17265 
17266         struct
17267         {
17268             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
17269             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
17270             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
17271             uint8_t             : 1;
17272             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
17273             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
17274             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
17275         } LVD1CR0_b;
17276     };
17277 
17278     union
17279     {
17280         __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
17281 
17282         struct
17283         {
17284             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
17285             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
17286             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
17287             uint8_t             : 1;
17288             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
17289             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
17290             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
17291         } LVD2CR0_b;
17292     };
17293     __IM uint8_t RESERVED45;
17294 
17295     union
17296     {
17297         __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
17298                                            *                  Register                                                   */
17299 
17300         struct
17301         {
17302             __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit                       */
17303             uint8_t                  : 7;
17304         } VBATTMNSELR_b;
17305     };
17306 
17307     union
17308     {
17309         __IM uint8_t VBATTMONR;        /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register                    */
17310 
17311         struct
17312         {
17313             __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit                                          */
17314             uint8_t               : 7;
17315         } VBATTMONR_b;
17316     };
17317 
17318     union
17319     {
17320         __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
17321 
17322         struct
17323         {
17324             __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
17325             uint8_t                : 7;
17326         } VBTCR1_b;
17327     };
17328     __IM uint32_t RESERVED46[8];
17329 
17330     union
17331     {
17332         union
17333         {
17334             __IOM uint8_t DCDCCTL;         /*!< (@ 0x00000440) DCDC/LDO Control Register                                  */
17335 
17336             struct
17337             {
17338                 __IOM uint8_t DCDCON  : 1; /*!< [0..0] LDO/DCDC on/off Control bit                                        */
17339                 __IOM uint8_t OCPEN   : 1; /*!< [1..1] DCDC OCP Function Enable bit                                       */
17340                 uint8_t               : 2;
17341                 __IOM uint8_t STOPZA  : 1; /*!< [4..4] DCDC IO Buffer Power Control bit                                   */
17342                 __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit                                       */
17343                 __IOM uint8_t FST     : 1; /*!< [6..6] DCDC Fast Startup                                                  */
17344                 __IOM uint8_t PD      : 1; /*!< [7..7] DCDC VREF Generate Disable bit                                     */
17345             } DCDCCTL_b;
17346         };
17347 
17348         union
17349         {
17350             __IOM uint8_t LDOSCR;          /*!< (@ 0x00000440) LDO Stop Control Register                                  */
17351 
17352             struct
17353             {
17354                 __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop                                                          */
17355                 __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop                                                          */
17356                 uint8_t               : 6;
17357             } LDOSCR_b;
17358         };
17359     };
17360 
17361     union
17362     {
17363         __IOM uint8_t VCCSEL;          /*!< (@ 0x00000441) Voltage Level Selection Control Register                   */
17364 
17365         struct
17366         {
17367             __IOM uint8_t VCCSEL : 2;  /*!< [1..0] DCDC Working Voltage Level Selection                               */
17368             uint8_t              : 6;
17369         } VCCSEL_b;
17370     };
17371     __IM uint16_t RESERVED47;
17372 
17373     union
17374     {
17375         __IOM uint8_t PL2LDOSCR;         /*!< (@ 0x00000444) PLL2-LDO Stop Control Register                             */
17376 
17377         struct
17378         {
17379             __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop                                                          */
17380             uint8_t                 : 7;
17381         } PL2LDOSCR_b;
17382     };
17383     __IM uint8_t  RESERVED48;
17384     __IM uint16_t RESERVED49;
17385     __IM uint32_t RESERVED50[14];
17386 
17387     union
17388     {
17389         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
17390 
17391         struct
17392         {
17393             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
17394             uint8_t             : 7;
17395         } SOSCCR_b;
17396     };
17397 
17398     union
17399     {
17400         __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
17401 
17402         struct
17403         {
17404             __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
17405             uint8_t             : 6;
17406         } SOMCR_b;
17407     };
17408 
17409     union
17410     {
17411         __IOM uint8_t SOMRG;           /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register                 */
17412 
17413         struct
17414         {
17415             __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching                        */
17416             uint8_t               : 6;
17417         } SOMRG_b;
17418     };
17419     __IM uint8_t  RESERVED51;
17420     __IM uint32_t RESERVED52[3];
17421 
17422     union
17423     {
17424         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
17425 
17426         struct
17427         {
17428             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
17429             uint8_t             : 7;
17430         } LOCOCR_b;
17431     };
17432     __IM uint8_t RESERVED53;
17433 
17434     union
17435     {
17436         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
17437 
17438         struct
17439         {
17440             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
17441                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
17442                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
17443                                          +126 0111_1111 : +127These bits are added to original LOCO
17444                                          *   trimming bits                                                             */
17445         } LOCOUTCR_b;
17446     };
17447     __IM uint8_t  RESERVED54;
17448     __IM uint32_t RESERVED55[7];
17449 
17450     union
17451     {
17452         __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
17453 
17454         struct
17455         {
17456             uint8_t                 : 4;
17457             __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
17458             uint8_t                 : 1;
17459             __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
17460         } VBTCR2_b;
17461     };
17462 
17463     union
17464     {
17465         __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
17466 
17467         struct
17468         {
17469             __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
17470             __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
17471             uint8_t               : 2;
17472             __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
17473             uint8_t               : 3;
17474         } VBTSR_b;
17475     };
17476 
17477     union
17478     {
17479         __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
17480 
17481         struct
17482         {
17483             __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
17484             uint8_t               : 7;
17485         } VBTCMPCR_b;
17486     };
17487     __IM uint8_t RESERVED56;
17488 
17489     union
17490     {
17491         __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
17492                                            *                  Register                                                   */
17493 
17494         struct
17495         {
17496             __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
17497             __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
17498             uint8_t                  : 6;
17499         } VBTLVDICR_b;
17500     };
17501     __IM uint8_t RESERVED57;
17502 
17503     union
17504     {
17505         __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
17506 
17507         struct
17508         {
17509             __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
17510             uint8_t            : 7;
17511         } VBTWCTLR_b;
17512     };
17513     __IM uint8_t RESERVED58;
17514 
17515     union
17516     {
17517         __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
17518 
17519         struct
17520         {
17521             uint8_t                  : 1;
17522             __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
17523             __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
17524             __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
17525             __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
17526             __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
17527             uint8_t                  : 2;
17528         } VBTWCH0OTSR_b;
17529     };
17530 
17531     union
17532     {
17533         __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
17534 
17535         struct
17536         {
17537             __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
17538             uint8_t                  : 1;
17539             __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
17540             __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
17541             __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
17542             __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
17543             uint8_t                  : 2;
17544         } VBTWCH1OTSR_b;
17545     };
17546 
17547     union
17548     {
17549         __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
17550 
17551         struct
17552         {
17553             __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
17554             __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
17555             uint8_t                  : 1;
17556             __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
17557             __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
17558             __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
17559             uint8_t                  : 2;
17560         } VBTWCH2OTSR_b;
17561     };
17562 
17563     union
17564     {
17565         __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
17566 
17567         struct
17568         {
17569             __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
17570             __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
17571             __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
17572             uint8_t                : 5;
17573         } VBTICTLR_b;
17574     };
17575 
17576     union
17577     {
17578         __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
17579 
17580         struct
17581         {
17582             __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
17583             __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
17584             __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
17585             __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
17586             __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
17587             __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
17588             uint8_t                 : 2;
17589         } VBTOCTLR_b;
17590     };
17591 
17592     union
17593     {
17594         __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
17595 
17596         struct
17597         {
17598             __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
17599             __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
17600             __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
17601             __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
17602             __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
17603             __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
17604             uint8_t              : 2;
17605         } VBTWTER_b;
17606     };
17607 
17608     union
17609     {
17610         __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
17611 
17612         struct
17613         {
17614             __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
17615             __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
17616             __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
17617             uint8_t              : 5;
17618         } VBTWEGR_b;
17619     };
17620 
17621     union
17622     {
17623         __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
17624 
17625         struct
17626         {
17627             __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
17628             __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
17629             __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
17630             __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
17631             __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
17632             __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
17633             uint8_t              : 2;
17634         } VBTWFR_b;
17635     };
17636 
17637     union
17638     {
17639         __IOM uint8_t VBTBER;          /*!< (@ 0x000004C0) VBATT Backup Enable Register                               */
17640 
17641         struct
17642         {
17643             uint8_t            : 3;
17644             __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
17645             uint8_t            : 4;
17646         } VBTBER_b;
17647     };
17648     __IM uint8_t  RESERVED59;
17649     __IM uint16_t RESERVED60;
17650     __IM uint32_t RESERVED61[15];
17651 
17652     union
17653     {
17654         __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
17655 
17656         struct
17657         {
17658             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
17659                                         *   data powered by VBATT.The value of this register is retained
17660                                         *   even when VCC is not powered but VBATT is powered.VBTBKR
17661                                         *   is initialized by VBATT selected voltage power-on-reset.                  */
17662         } VBTBKR_b[512];
17663     };
17664 } R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
17665 
17666 /* =========================================================================================================================== */
17667 /* ================                                         R_TSN_CAL                                         ================ */
17668 /* =========================================================================================================================== */
17669 
17670 /**
17671  * @brief Temperature Sensor (R_TSN_CAL)
17672  */
17673 
17674 typedef struct                         /*!< (@ 0x407FB17C) R_TSN_CAL Structure                                        */
17675 {
17676     union
17677     {
17678         __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
17679 
17680         struct
17681         {
17682             __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
17683                                         *   calibration converted value.                                              */
17684         } TSCDR_b;
17685     };
17686 } R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
17687 
17688 /* =========================================================================================================================== */
17689 /* ================                                        R_TSN_CTRL                                         ================ */
17690 /* =========================================================================================================================== */
17691 
17692 /**
17693  * @brief Temperature Sensor (R_TSN_CTRL)
17694  */
17695 
17696 typedef struct                         /*!< (@ 0x4005D000) R_TSN_CTRL Structure                                       */
17697 {
17698     union
17699     {
17700         __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
17701 
17702         struct
17703         {
17704             uint8_t            : 4;
17705             __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
17706             uint8_t            : 2;
17707             __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
17708         } TSCR_b;
17709     };
17710 } R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
17711 
17712 /* =========================================================================================================================== */
17713 /* ================                                         R_USB_FS0                                         ================ */
17714 /* =========================================================================================================================== */
17715 
17716 /**
17717  * @brief USB 2.0 Module (R_USB_FS0)
17718  */
17719 
17720 typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
17721 {
17722     union
17723     {
17724         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
17725 
17726         struct
17727         {
17728             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
17729             uint16_t             : 2;
17730             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
17731             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
17732             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
17733             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
17734             uint16_t             : 1;
17735             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
17736             uint16_t             : 1;
17737             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
17738             uint16_t             : 5;
17739         } SYSCFG_b;
17740     };
17741 
17742     union
17743     {
17744         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
17745 
17746         struct
17747         {
17748             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
17749                                         *   access cycles)                                                            */
17750             uint16_t : 12;
17751         } BUSWAIT_b;
17752     };
17753 
17754     union
17755     {
17756         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
17757 
17758         struct
17759         {
17760             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
17761             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
17762             uint16_t            : 2;
17763             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
17764                                         *   Selected.                                                                 */
17765             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
17766             uint16_t             : 7;
17767             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
17768                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
17769                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
17770                                         *   pin.                                                                      */
17771         } SYSSTS0_b;
17772     };
17773 
17774     union
17775     {
17776         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
17777 
17778         struct
17779         {
17780             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
17781             uint16_t              : 15;
17782         } PLLSTA_b;
17783     };
17784 
17785     union
17786     {
17787         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
17788 
17789         struct
17790         {
17791             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
17792             uint16_t               : 1;
17793             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
17794             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
17795             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
17796             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
17797             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
17798             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
17799             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
17800             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
17801                                          *   used when switching from device B to device A while in
17802                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
17803                                          *   control keeps the suspended state until the HNP processing
17804                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
17805                                          *   set.                                                                      */
17806             uint16_t : 4;
17807         } DVSTCTR0_b;
17808     };
17809     __IM uint16_t RESERVED;
17810 
17811     union
17812     {
17813         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
17814 
17815         struct
17816         {
17817             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
17818             uint16_t            : 12;
17819         } TESTMODE_b;
17820     };
17821     __IM uint16_t RESERVED1;
17822     __IM uint32_t RESERVED2;
17823 
17824     union
17825     {
17826         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
17827 
17828         struct
17829         {
17830             union
17831             {
17832                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
17833                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
17834             };
17835 
17836             union
17837             {
17838                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
17839 
17840                 struct
17841                 {
17842                     __IM uint8_t  RESERVED3;
17843                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
17844                 };
17845             };
17846         };
17847     };
17848 
17849     union
17850     {
17851         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
17852 
17853         struct
17854         {
17855             union
17856             {
17857                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
17858                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
17859             };
17860 
17861             union
17862             {
17863                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
17864 
17865                 struct
17866                 {
17867                     __IM uint8_t  RESERVED4;
17868                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
17869                 };
17870             };
17871         };
17872     };
17873 
17874     union
17875     {
17876         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
17877 
17878         struct
17879         {
17880             union
17881             {
17882                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
17883                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
17884             };
17885 
17886             union
17887             {
17888                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
17889 
17890                 struct
17891                 {
17892                     __IM uint8_t  RESERVED5;
17893                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
17894                 };
17895             };
17896         };
17897     };
17898 
17899     union
17900     {
17901         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
17902 
17903         struct
17904         {
17905             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
17906             uint16_t               : 1;
17907             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
17908             uint16_t               : 2;
17909             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
17910             uint16_t               : 1;
17911             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
17912             uint16_t               : 2;
17913             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
17914             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
17915         } CFIFOSEL_b;
17916     };
17917 
17918     union
17919     {
17920         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
17921 
17922         struct
17923         {
17924             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
17925                                         *   data.                                                                     */
17926             uint16_t            : 1;
17927             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
17928             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
17929             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
17930         } CFIFOCTR_b;
17931     };
17932     __IM uint32_t RESERVED6;
17933 
17934     union
17935     {
17936         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
17937 
17938         struct
17939         {
17940             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
17941             uint16_t               : 4;
17942             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
17943             uint16_t               : 1;
17944             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
17945             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
17946             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
17947                                          *   Pipe Data is Read                                                         */
17948             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
17949             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
17950         } D0FIFOSEL_b;
17951     };
17952 
17953     union
17954     {
17955         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
17956 
17957         struct
17958         {
17959             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
17960                                         *   data.                                                                     */
17961             uint16_t            : 1;
17962             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
17963             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
17964             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
17965         } D0FIFOCTR_b;
17966     };
17967 
17968     union
17969     {
17970         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
17971 
17972         struct
17973         {
17974             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
17975             uint16_t               : 4;
17976             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
17977             uint16_t               : 1;
17978             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
17979             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
17980             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
17981                                          *   Pipe Data is Read                                                         */
17982             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
17983             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
17984         } D1FIFOSEL_b;
17985     };
17986 
17987     union
17988     {
17989         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
17990 
17991         struct
17992         {
17993             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
17994                                         *   data.                                                                     */
17995             uint16_t            : 1;
17996             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
17997             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
17998             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
17999         } D1FIFOCTR_b;
18000     };
18001 
18002     union
18003     {
18004         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
18005 
18006         struct
18007         {
18008             uint16_t             : 8;
18009             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
18010             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
18011             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
18012             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
18013             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
18014             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
18015             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
18016             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
18017         } INTENB0_b;
18018     };
18019 
18020     union
18021     {
18022         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
18023 
18024         struct
18025         {
18026             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
18027             uint16_t                  : 3;
18028             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
18029             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
18030             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
18031             uint16_t                  : 4;
18032             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
18033             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
18034             uint16_t                  : 1;
18035             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
18036             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
18037         } INTENB1_b;
18038     };
18039     __IM uint16_t RESERVED7;
18040 
18041     union
18042     {
18043         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
18044 
18045         struct
18046         {
18047             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
18048             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
18049             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
18050             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
18051             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
18052             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
18053             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
18054             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
18055             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
18056             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
18057             uint16_t                  : 6;
18058         } BRDYENB_b;
18059     };
18060 
18061     union
18062     {
18063         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
18064 
18065         struct
18066         {
18067             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
18068             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
18069             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
18070             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
18071             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
18072             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
18073             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
18074             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
18075             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
18076             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
18077             uint16_t                  : 6;
18078         } NRDYENB_b;
18079     };
18080 
18081     union
18082     {
18083         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
18084 
18085         struct
18086         {
18087             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
18088             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
18089             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
18090             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
18091             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
18092             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
18093             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
18094             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
18095             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
18096             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
18097             uint16_t                  : 6;
18098         } BEMPENB_b;
18099     };
18100 
18101     union
18102     {
18103         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
18104 
18105         struct
18106         {
18107             uint16_t                : 4;
18108             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
18109             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
18110             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
18111             uint16_t                : 1;
18112             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
18113             uint16_t                : 7;
18114         } SOFCFG_b;
18115     };
18116 
18117     union
18118     {
18119         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
18120 
18121         struct
18122         {
18123             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
18124             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
18125             uint16_t                : 1;
18126             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
18127             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
18128             uint16_t                : 2;
18129             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
18130             uint16_t                : 1;
18131             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
18132             uint16_t                : 3;
18133             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
18134         } PHYSET_b;
18135     };
18136 
18137     union
18138     {
18139         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
18140 
18141         struct
18142         {
18143             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
18144             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
18145             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
18146             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
18147             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
18148             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
18149             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
18150             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
18151             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
18152             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
18153             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
18154             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
18155         } INTSTS0_b;
18156     };
18157 
18158     union
18159     {
18160         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
18161 
18162         struct
18163         {
18164             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
18165             uint16_t                 : 3;
18166             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
18167             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
18168             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
18169             uint16_t                 : 1;
18170             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
18171             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
18172             uint16_t                 : 1;
18173             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
18174             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
18175             uint16_t                 : 1;
18176             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
18177             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
18178         } INTSTS1_b;
18179     };
18180     __IM uint16_t RESERVED8;
18181 
18182     union
18183     {
18184         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
18185 
18186         struct
18187         {
18188             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
18189             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
18190             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
18191             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
18192             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
18193             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
18194             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
18195             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
18196             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
18197             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
18198             uint16_t                 : 6;
18199         } BRDYSTS_b;
18200     };
18201 
18202     union
18203     {
18204         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
18205 
18206         struct
18207         {
18208             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
18209             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
18210             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
18211             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
18212             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
18213             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
18214             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
18215             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
18216             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
18217             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
18218             uint16_t                 : 6;
18219         } NRDYSTS_b;
18220     };
18221 
18222     union
18223     {
18224         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
18225 
18226         struct
18227         {
18228             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
18229             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
18230             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
18231             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
18232             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
18233             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
18234             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
18235             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
18236             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
18237             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
18238             uint16_t                 : 6;
18239         } BEMPSTS_b;
18240     };
18241 
18242     union
18243     {
18244         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
18245 
18246         struct
18247         {
18248             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
18249             uint16_t            : 3;
18250             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
18251             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
18252         } FRMNUM_b;
18253     };
18254 
18255     union
18256     {
18257         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
18258 
18259         struct
18260         {
18261             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
18262             uint16_t             : 12;
18263             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
18264         } UFRMNUM_b;
18265     };
18266 
18267     union
18268     {
18269         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
18270 
18271         struct
18272         {
18273             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
18274                                            *   the USB address assigned by the host when the USBHS processed
18275                                            *   the SET_ADDRESS request successfully.                                     */
18276             uint16_t                 : 1;
18277             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
18278             uint16_t                 : 5;
18279         } USBADDR_b;
18280     };
18281     __IM uint16_t RESERVED9;
18282 
18283     union
18284     {
18285         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
18286 
18287         struct
18288         {
18289             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
18290                                                *   value.                                                                    */
18291             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
18292         } USBREQ_b;
18293     };
18294 
18295     union
18296     {
18297         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
18298 
18299         struct
18300         {
18301             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
18302         } USBVAL_b;
18303     };
18304 
18305     union
18306     {
18307         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
18308 
18309         struct
18310         {
18311             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
18312         } USBINDX_b;
18313     };
18314 
18315     union
18316     {
18317         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
18318 
18319         struct
18320         {
18321             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
18322         } USBLENG_b;
18323     };
18324 
18325     union
18326     {
18327         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
18328 
18329         struct
18330         {
18331             uint16_t              : 4;
18332             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
18333             uint16_t              : 2;
18334             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
18335             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
18336             uint16_t              : 7;
18337         } DCPCFG_b;
18338     };
18339 
18340     union
18341     {
18342         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
18343 
18344         struct
18345         {
18346             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
18347                                         *   of data (maximum packet size) in payloads for the DCP.                    */
18348             uint16_t              : 5;
18349             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
18350         } DCPMAXP_b;
18351     };
18352 
18353     union
18354     {
18355         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
18356 
18357         struct
18358         {
18359             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
18360             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
18361             uint16_t                : 2;
18362             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
18363             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
18364             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
18365             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
18366             uint16_t                : 2;
18367             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
18368             uint16_t                : 2;
18369             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
18370             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
18371         } DCPCTR_b;
18372     };
18373     __IM uint16_t RESERVED10;
18374 
18375     union
18376     {
18377         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
18378 
18379         struct
18380         {
18381             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
18382             uint16_t               : 12;
18383         } PIPESEL_b;
18384     };
18385     __IM uint16_t RESERVED11;
18386 
18387     union
18388     {
18389         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
18390 
18391         struct
18392         {
18393             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
18394                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
18395             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
18396             uint16_t              : 2;
18397             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
18398             uint16_t              : 1;
18399             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
18400             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
18401             uint16_t              : 3;
18402             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
18403         } PIPECFG_b;
18404     };
18405     __IM uint16_t RESERVED12;
18406 
18407     union
18408     {
18409         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
18410 
18411         struct
18412         {
18413             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
18414                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
18415                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
18416                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
18417                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
18418             uint16_t              : 3;
18419             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
18420         } PIPEMAXP_b;
18421     };
18422 
18423     union
18424     {
18425         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
18426 
18427         struct
18428         {
18429             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
18430                                         *   error detection timing for the selected pipe in terms of
18431                                         *   frames, which is expressed as nth power of 2.                             */
18432             uint16_t            : 9;
18433             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
18434             uint16_t            : 3;
18435         } PIPEPERI_b;
18436     };
18437 
18438     union
18439     {
18440         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
18441 
18442         struct
18443         {
18444             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
18445             uint16_t              : 3;
18446             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
18447             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
18448             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
18449             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
18450             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
18451             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
18452             uint16_t              : 1;
18453             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
18454                                         *   Split Transaction of the relevant pipe                                    */
18455             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
18456                                         *   the CSSTS bit of the relevant pipe                                        */
18457             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
18458             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
18459         } PIPE_CTR_b[9];
18460     };
18461     __IM uint16_t                RESERVED13;
18462     __IM uint32_t                RESERVED14[3];
18463     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
18464     __IM uint32_t                RESERVED15[3];
18465 
18466     union
18467     {
18468         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
18469 
18470         struct
18471         {
18472             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
18473             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
18474             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
18475             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
18476             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
18477             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
18478             uint16_t                  : 1;
18479             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
18480             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
18481             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
18482             uint16_t                  : 6;
18483         } USBBCCTRL0_b;
18484     };
18485     __IM uint16_t RESERVED16;
18486     __IM uint32_t RESERVED17[4];
18487 
18488     union
18489     {
18490         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
18491 
18492         struct
18493         {
18494             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
18495             uint16_t               : 15;
18496         } UCKSEL_b;
18497     };
18498     __IM uint16_t RESERVED18;
18499     __IM uint32_t RESERVED19;
18500 
18501     union
18502     {
18503         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
18504 
18505         struct
18506         {
18507             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
18508             uint16_t               : 6;
18509             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
18510             uint16_t               : 8;
18511         } USBMC_b;
18512     };
18513     __IM uint16_t RESERVED20;
18514 
18515     union
18516     {
18517         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
18518 
18519         struct
18520         {
18521             uint16_t               : 6;
18522             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
18523             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
18524             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
18525             uint16_t               : 1;
18526         } DEVADD_b[10];
18527     };
18528     __IM uint32_t RESERVED21[3];
18529 
18530     union
18531     {
18532         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
18533 
18534         struct
18535         {
18536             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
18537             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
18538             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
18539             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
18540             uint32_t               : 28;
18541         } PHYSLEW_b;
18542     };
18543     __IM uint32_t RESERVED22[3];
18544 
18545     union
18546     {
18547         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
18548 
18549         struct
18550         {
18551             uint16_t             : 7;
18552             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
18553             uint16_t             : 8;
18554         } LPCTRL_b;
18555     };
18556 
18557     union
18558     {
18559         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
18560 
18561         struct
18562         {
18563             uint16_t                : 14;
18564             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
18565             uint16_t                : 1;
18566         } LPSTS_b;
18567     };
18568     __IM uint32_t RESERVED23[15];
18569 
18570     union
18571     {
18572         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
18573 
18574         struct
18575         {
18576             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
18577             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
18578             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
18579             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
18580             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
18581             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
18582             uint16_t                : 2;
18583             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
18584             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
18585             uint16_t                : 6;
18586         } BCCTRL_b;
18587     };
18588     __IM uint16_t RESERVED24;
18589 
18590     union
18591     {
18592         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
18593 
18594         struct
18595         {
18596             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
18597             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
18598             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
18599                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
18600             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
18601                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
18602             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
18603                                           *   value used for L1NEGOMD.The format is the same as the HIRD
18604                                           *   field in HL1CTRL.                                                         */
18605             uint16_t               : 2;
18606             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
18607             uint16_t               : 1;
18608         } PL1CTRL1_b;
18609     };
18610 
18611     union
18612     {
18613         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
18614 
18615         struct
18616         {
18617             uint16_t               : 8;
18618             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
18619             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
18620             uint16_t               : 3;
18621         } PL1CTRL2_b;
18622     };
18623 
18624     union
18625     {
18626         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
18627 
18628         struct
18629         {
18630             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
18631             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
18632             uint16_t                : 13;
18633         } HL1CTRL1_b;
18634     };
18635 
18636     union
18637     {
18638         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
18639 
18640         struct
18641         {
18642             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
18643                                         *   be set in the ADDR field of LPM token.                                    */
18644             uint16_t             : 4;
18645             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
18646             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
18647                                         *   value to be set in the RWE field of LPM token.                            */
18648             uint16_t            : 2;
18649             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
18650                                         *   period at the time of L1 Resume.                                          */
18651         } HL1CTRL2_b;
18652     };
18653     __IM uint32_t RESERVED25[5];
18654 
18655     union
18656     {
18657         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
18658                                         *                  Register                                                   */
18659 
18660         struct
18661         {
18662             uint32_t              : 20;
18663             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
18664                                          *   HS side of USB port.                                                      */
18665             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
18666                                          *   HS side of USB port.                                                      */
18667             uint32_t               : 1;
18668             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
18669                                          *   of USB port.                                                              */
18670             uint32_t : 8;
18671         } DPUSR0R_b;
18672     };
18673 
18674     union
18675     {
18676         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
18677 
18678         struct
18679         {
18680             uint32_t                : 4;
18681             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
18682             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
18683             uint32_t                : 1;
18684             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
18685             uint32_t                : 12;
18686             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
18687             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
18688             uint32_t                : 1;
18689             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
18690             uint32_t                : 8;
18691         } DPUSR1R_b;
18692     };
18693 
18694     union
18695     {
18696         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
18697 
18698         struct
18699         {
18700             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
18701             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
18702             uint16_t            : 2;
18703             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
18704                                         *   port.                                                                     */
18705             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
18706                                         *   port.                                                                     */
18707             uint16_t              : 2;
18708             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
18709             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
18710             uint16_t              : 6;
18711         } DPUSR2R_b;
18712     };
18713 
18714     union
18715     {
18716         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
18717 
18718         struct
18719         {
18720             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
18721             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
18722             uint16_t                : 14;
18723         } DPUSRCR_b;
18724     };
18725     __IM uint32_t RESERVED26[165];
18726 
18727     union
18728     {
18729         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
18730                                          *                  Monitor Register                                           */
18731 
18732         struct
18733         {
18734             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
18735             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
18736             uint32_t               : 1;
18737             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
18738             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
18739             uint32_t               : 11;
18740             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
18741             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
18742             uint32_t               : 2;
18743             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
18744                                          *   of the USB.                                                               */
18745             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
18746                                          *   of the USB.                                                               */
18747             uint32_t              : 1;
18748             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
18749                                          *   USB.                                                                      */
18750             uint32_t : 8;
18751         } DPUSR0R_FS_b;
18752     };
18753 
18754     union
18755     {
18756         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
18757                                            *                  Register                                                   */
18758 
18759         struct
18760         {
18761             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
18762             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
18763             uint32_t                 : 2;
18764             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
18765             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
18766             uint32_t                 : 1;
18767             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
18768             uint32_t                 : 8;
18769             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
18770             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
18771             uint32_t                 : 2;
18772             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
18773             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
18774             uint32_t                 : 1;
18775             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
18776             uint32_t                 : 8;
18777         } DPUSR1R_FS_b;
18778     };
18779 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
18780 
18781 /* =========================================================================================================================== */
18782 /* ================                                           R_WDT                                           ================ */
18783 /* =========================================================================================================================== */
18784 
18785 /**
18786  * @brief Watchdog Timer (R_WDT)
18787  */
18788 
18789 typedef struct                         /*!< (@ 0x40044200) R_WDT Structure                                            */
18790 {
18791     union
18792     {
18793         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
18794 
18795         struct
18796         {
18797             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
18798                                         *   of the WDT.                                                               */
18799         } WDTRR_b;
18800     };
18801     __IM uint8_t RESERVED;
18802 
18803     union
18804     {
18805         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
18806 
18807         struct
18808         {
18809             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
18810             uint16_t            : 2;
18811             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
18812             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
18813             uint16_t            : 2;
18814             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
18815             uint16_t            : 2;
18816         } WDTCR_b;
18817     };
18818 
18819     union
18820     {
18821         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
18822 
18823         struct
18824         {
18825             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
18826             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
18827             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
18828         } WDTSR_b;
18829     };
18830 
18831     union
18832     {
18833         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
18834 
18835         struct
18836         {
18837             uint8_t               : 7;
18838             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
18839         } WDTRCR_b;
18840     };
18841     __IM uint8_t RESERVED1;
18842 
18843     union
18844     {
18845         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
18846 
18847         struct
18848         {
18849             uint8_t              : 7;
18850             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
18851         } WDTCSTPR_b;
18852     };
18853     __IM uint8_t  RESERVED2;
18854     __IM uint16_t RESERVED3;
18855 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
18856 
18857 /* =========================================================================================================================== */
18858 /* ================                                         R_USB_HS0                                         ================ */
18859 /* =========================================================================================================================== */
18860 
18861 /**
18862  * @brief USB 2.0 High-Speed Module (R_USB_HS0)
18863  */
18864 
18865 typedef struct                         /*!< (@ 0x40060000) R_USB_HS0 Structure                                        */
18866 {
18867     union
18868     {
18869         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
18870 
18871         struct
18872         {
18873             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
18874             uint16_t             : 3;
18875             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
18876             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
18877             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
18878             __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                        */
18879             __IOM uint16_t CNEN  : 1;  /*!< [8..8] Single End Receiver Enable                                         */
18880             uint16_t             : 7;
18881         } SYSCFG_b;
18882     };
18883 
18884     union
18885     {
18886         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
18887 
18888         struct
18889         {
18890             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
18891                                         *   access cycles)                                                            */
18892             uint16_t : 12;
18893         } BUSWAIT_b;
18894     };
18895 
18896     union
18897     {
18898         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register                       */
18899 
18900         struct
18901         {
18902             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
18903             __IM uint16_t IDMON : 1;   /*!< [2..2] ID0 Pin Monitor                                                    */
18904             uint16_t            : 2;
18905             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
18906                                         *   Selected.                                                                 */
18907             __IM uint16_t HTACT  : 1;  /*!< [6..6] Host Sequencer Status Monitor                                      */
18908             uint16_t             : 7;
18909             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe
18910                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
18911                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
18912                                         *   pin.                                                                      */
18913         } SYSSTS0_b;
18914     };
18915 
18916     union
18917     {
18918         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
18919 
18920         struct
18921         {
18922             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
18923             uint16_t              : 15;
18924         } PLLSTA_b;
18925     };
18926 
18927     union
18928     {
18929         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
18930 
18931         struct
18932         {
18933             __IM uint16_t RHST    : 3;  /*!< [2..0] USB Bus Reset Status                                               */
18934             uint16_t              : 1;
18935             __IOM uint16_t UACT   : 1;  /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation         */
18936             __IOM uint16_t RESUME : 1;  /*!< [5..5] Resume Signal Output for the Host Controller Operation             */
18937             __IOM uint16_t USBRST : 1;  /*!< [6..6] USB Bus Reset Output for the Host Controller Operation             */
18938             __IOM uint16_t RWUPE  : 1;  /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller
18939                                          *   Operation                                                                 */
18940             __IOM uint16_t WKUP    : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation           */
18941             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control                                    */
18942             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control                                  */
18943             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit
18944                                          *   when switching from device B to device A in OTGmode. If
18945                                          *   the HNPBTOA bit is 1, the internal function controlremains
18946                                          *   in the Suspend state until the HNP processing endseven
18947                                          *   if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.                            */
18948             uint16_t : 4;
18949         } DVSTCTR0_b;
18950     };
18951     __IM uint16_t RESERVED;
18952 
18953     union
18954     {
18955         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
18956 
18957         struct
18958         {
18959             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
18960             uint16_t            : 12;
18961         } TESTMODE_b;
18962     };
18963     __IM uint16_t RESERVED1;
18964     __IM uint32_t RESERVED2;
18965 
18966     union
18967     {
18968         union
18969         {
18970             __IOM uint32_t CFIFO;             /*!< (@ 0x00000014) CFIFO Port Register                                        */
18971 
18972             struct
18973             {
18974                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or
18975                                                *   write transmit data to the FIFO buffer by accessing these
18976                                                *   bits.                                                                     */
18977             } CFIFO_b;
18978         };
18979 
18980         struct
18981         {
18982             union
18983             {
18984                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
18985                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
18986             };
18987 
18988             union
18989             {
18990                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
18991 
18992                 struct
18993                 {
18994                     __IM uint8_t  RESERVED3;
18995                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
18996                 };
18997             };
18998         };
18999     };
19000 
19001     union
19002     {
19003         union
19004         {
19005             __IOM uint32_t D0FIFO;            /*!< (@ 0x00000018) D0FIFO Port Register                                       */
19006 
19007             struct
19008             {
19009                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or
19010                                                *   write transmit data to the FIFO buffer by accessing these
19011                                                *   bits.                                                                     */
19012             } D0FIFO_b;
19013         };
19014 
19015         struct
19016         {
19017             union
19018             {
19019                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
19020                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
19021             };
19022 
19023             union
19024             {
19025                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
19026 
19027                 struct
19028                 {
19029                     __IM uint8_t  RESERVED4;
19030                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
19031                 };
19032             };
19033         };
19034     };
19035 
19036     union
19037     {
19038         union
19039         {
19040             __IOM uint32_t D1FIFO;            /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
19041 
19042             struct
19043             {
19044                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write
19045                                                *   transmit data to the FIFO buffer by accessing these bits.                 */
19046             } D1FIFO_b;
19047         };
19048 
19049         struct
19050         {
19051             union
19052             {
19053                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
19054                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
19055             };
19056 
19057             union
19058             {
19059                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
19060 
19061                 struct
19062                 {
19063                     __IM uint8_t  RESERVED5;
19064                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
19065                 };
19066             };
19067         };
19068     };
19069 
19070     union
19071     {
19072         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
19073 
19074         struct
19075         {
19076             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
19077             uint16_t               : 1;
19078             __IOM uint16_t ISEL    : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected                    */
19079             uint16_t               : 2;
19080             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
19081             uint16_t               : 1;
19082             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
19083             uint16_t               : 2;
19084             __OM uint16_t  REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
19085             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
19086         } CFIFOSEL_b;
19087     };
19088 
19089     union
19090     {
19091         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
19092 
19093         struct
19094         {
19095             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
19096                                         *   data.                                                                     */
19097             uint16_t           : 1;
19098             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
19099                                         *   be accessed.                                                              */
19100             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
19101             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
19102         } CFIFOCTR_b;
19103     };
19104     __IM uint32_t RESERVED6;
19105 
19106     union
19107     {
19108         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
19109 
19110         struct
19111         {
19112             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
19113             uint16_t               : 4;
19114             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
19115             uint16_t               : 1;
19116             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
19117             __IOM uint16_t DREQE   : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable                                 */
19118             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
19119                                          *   Pipe Data is Read                                                         */
19120             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
19121             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
19122         } D0FIFOSEL_b;
19123     };
19124 
19125     union
19126     {
19127         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
19128 
19129         struct
19130         {
19131             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
19132                                         *   data.                                                                     */
19133             uint16_t           : 1;
19134             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
19135                                         *   be accessed.                                                              */
19136             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
19137             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
19138         } D0FIFOCTR_b;
19139     };
19140 
19141     union
19142     {
19143         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
19144 
19145         struct
19146         {
19147             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
19148             uint16_t               : 4;
19149             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
19150             uint16_t               : 1;
19151             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
19152             __IOM uint16_t DREQE   : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable                                 */
19153             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
19154                                          *   Pipe Data is Read                                                         */
19155             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
19156             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
19157         } D1FIFOSEL_b;
19158     };
19159 
19160     union
19161     {
19162         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
19163 
19164         struct
19165         {
19166             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
19167                                         *   data.                                                                     */
19168             uint16_t           : 1;
19169             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
19170                                         *   be accessed.                                                              */
19171             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
19172             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
19173         } D1FIFOCTR_b;
19174     };
19175 
19176     union
19177     {
19178         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
19179 
19180         struct
19181         {
19182             uint16_t             : 8;
19183             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
19184             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
19185             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
19186             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
19187             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
19188             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
19189             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
19190             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
19191         } INTENB0_b;
19192     };
19193 
19194     union
19195     {
19196         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
19197 
19198         struct
19199         {
19200             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
19201             uint16_t                  : 3;
19202             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
19203             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
19204             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
19205             uint16_t                  : 1;
19206             __IOM uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
19207             __IOM uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
19208             uint16_t                  : 1;
19209             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
19210             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
19211             uint16_t                  : 1;
19212             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
19213             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] OVRCRE Interrupt Enable                                          */
19214         } INTENB1_b;
19215     };
19216     __IM uint16_t RESERVED7;
19217 
19218     union
19219     {
19220         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
19221 
19222         struct
19223         {
19224             __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe                                */
19225             uint16_t                 : 6;
19226         } BRDYENB_b;
19227     };
19228 
19229     union
19230     {
19231         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
19232 
19233         struct
19234         {
19235             __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe                                */
19236             uint16_t                 : 6;
19237         } NRDYENB_b;
19238     };
19239 
19240     union
19241     {
19242         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
19243 
19244         struct
19245         {
19246             __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe                                */
19247             uint16_t                 : 6;
19248         } BEMPENB_b;
19249     };
19250 
19251     union
19252     {
19253         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Pin Configuration Register                             */
19254 
19255         struct
19256         {
19257             uint16_t               : 4;
19258             __IM uint16_t  EDGESTS : 1;  /*!< [4..4] Interrupt Edge Processing Status Monitor                           */
19259             __IOM uint16_t INTL    : 1;  /*!< [5..5] Interrupt Output Sense Select                                      */
19260             __IOM uint16_t BRDYM   : 1;  /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be
19261                                           *   set only in the initial setting (before communications).The
19262                                           *   setting cannot be changed once communication starts.                      */
19263             uint16_t                : 1;
19264             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency
19265                                           *   can be improved by setting this bit to 1 if no low-speed
19266                                           *   device is connected directly or via FS-HUB to the USB port.               */
19267             uint16_t : 7;
19268         } SOFCFG_b;
19269     };
19270 
19271     union
19272     {
19273         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
19274 
19275         struct
19276         {
19277             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
19278             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
19279             uint16_t                : 1;
19280             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
19281             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
19282             uint16_t                : 2;
19283             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
19284             uint16_t                : 1;
19285             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
19286             uint16_t                : 3;
19287             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
19288         } PHYSET_b;
19289     };
19290 
19291     union
19292     {
19293         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
19294 
19295         struct
19296         {
19297             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
19298             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
19299             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
19300             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
19301             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
19302             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
19303             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
19304             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
19305             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
19306             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
19307             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
19308             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
19309         } INTSTS0_b;
19310     };
19311 
19312     union
19313     {
19314         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
19315 
19316         struct
19317         {
19318             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status                                   */
19319             uint16_t                 : 3;
19320             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
19321             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
19322             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
19323             uint16_t                 : 1;
19324             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
19325             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
19326             uint16_t                 : 1;
19327             __IOM uint16_t ATTCH     : 1; /*!< [11..11] USB Connection Detection Interrupt Status                        */
19328             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
19329             uint16_t                 : 1;
19330             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
19331             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Interrupt Status                                     */
19332         } INTSTS1_b;
19333     };
19334     __IM uint16_t RESERVED8;
19335 
19336     union
19337     {
19338         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
19339 
19340         struct
19341         {
19342             __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe                                */
19343             uint16_t                : 6;
19344         } BRDYSTS_b;
19345     };
19346 
19347     union
19348     {
19349         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
19350 
19351         struct
19352         {
19353             __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe                                */
19354             uint16_t                : 6;
19355         } NRDYSTS_b;
19356     };
19357 
19358     union
19359     {
19360         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
19361 
19362         struct
19363         {
19364             __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe                                */
19365             uint16_t                : 6;
19366         } BEMPSTS_b;
19367     };
19368 
19369     union
19370     {
19371         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
19372 
19373         struct
19374         {
19375             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame Number.Indicate the latest frame number.                    */
19376             uint16_t            : 3;
19377             __IOM uint16_t CRCE : 1;   /*!< [14..14] CRC Error Detection Status                                       */
19378             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
19379         } FRMNUM_b;
19380     };
19381 
19382     union
19383     {
19384         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
19385 
19386         struct
19387         {
19388             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
19389             uint16_t             : 12;
19390             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
19391         } UFRMNUM_b;
19392     };
19393 
19394     union
19395     {
19396         __IOM uint16_t USBADDR;        /*!< (@ 0x00000050) USB Address Register                                       */
19397 
19398         struct
19399         {
19400             uint16_t                 : 8;
19401             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
19402             uint16_t                 : 5;
19403         } USBADDR_b;
19404     };
19405     __IM uint16_t RESERVED9;
19406 
19407     union
19408     {
19409         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
19410 
19411         struct
19412         {
19413             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected
19414                                                *   : read-only Host controller selected : read-write                         */
19415             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] USB request bRequest value Finction controller selected
19416                                                *   : read-only Host controller selected : read-write                         */
19417         } USBREQ_b;
19418     };
19419 
19420     union
19421     {
19422         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
19423 
19424         struct
19425         {
19426             __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected
19427                                          *   : read-only Host controller selected : read-write                         */
19428         } USBVAL_b;
19429     };
19430 
19431     union
19432     {
19433         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
19434 
19435         struct
19436         {
19437             __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected
19438                                          *   : read-only Host controller selected : read-write                         */
19439         } USBINDX_b;
19440     };
19441 
19442     union
19443     {
19444         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
19445 
19446         struct
19447         {
19448             __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected
19449                                           *   : read-only Host controller selected : read-write                         */
19450         } USBLENG_b;
19451     };
19452 
19453     union
19454     {
19455         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
19456 
19457         struct
19458         {
19459             uint16_t              : 4;
19460             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
19461             uint16_t              : 2;
19462             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer                                   */
19463             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
19464             uint16_t              : 7;
19465         } DCPCFG_b;
19466     };
19467 
19468     union
19469     {
19470         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
19471 
19472         struct
19473         {
19474             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data
19475                                         *   payload (maximum packet size) for the DCP.                                */
19476             uint16_t              : 5;
19477             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
19478                                         *   destination function device for control transfer when the
19479                                         *   host controller function is selected.                                     */
19480         } DCPMAXP_b;
19481     };
19482 
19483     union
19484     {
19485         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
19486 
19487         struct
19488         {
19489             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
19490             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
19491             uint16_t                : 1;
19492             __IOM uint16_t PINGE    : 1; /*!< [4..4] PING Token Issue Enable                                            */
19493             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
19494             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
19495             __IOM uint16_t SQSET    : 1; /*!< [7..7] Toggle Bit Set                                                     */
19496             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Toggle Bit Clear                                                   */
19497             uint16_t                : 2;
19498             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
19499             __IM uint16_t  CSSTS    : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                  */
19500             __IOM uint16_t CSCLR    : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear                            */
19501             __IOM uint16_t SUREQ    : 1; /*!< [14..14] SETUP Token Transmission                                         */
19502             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
19503         } DCPCTR_b;
19504     };
19505     __IM uint16_t  RESERVED10;
19506     __IOM uint16_t PIPESEL;              /*!< (@ 0x00000064) Pipe Window Select Register                                */
19507     __IM uint16_t  RESERVED11;
19508 
19509     union
19510     {
19511         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
19512 
19513         struct
19514         {
19515             __IOM uint16_t EPNUM  : 4; /*!< [3..0] Endpoint Number                                                    */
19516             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
19517             uint16_t              : 2;
19518             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
19519             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
19520             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
19521             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
19522             uint16_t              : 3;
19523             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
19524         } PIPECFG_b;
19525     };
19526 
19527     union
19528     {
19529         __IOM uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Register                                       */
19530 
19531         struct
19532         {
19533             __IOM uint16_t BUFNMB : 8;  /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number
19534                                          *   of the selected pipe (04h to 87h).                                        */
19535             uint16_t               : 2;
19536             __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes         */
19537             uint16_t               : 1;
19538         } PIPEBUF_b;
19539     };
19540 
19541     union
19542     {
19543         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
19544 
19545         struct
19546         {
19547             __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data
19548                                         *   payload (maximum packet size) for the selected pipe.A size
19549                                         *   of 1h to 40h bytes can be set for PIPE6 to PIPE9.                         */
19550             uint16_t              : 1;
19551             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
19552                                         *   peripheral device when the host controller function is
19553                                         *   selected.                                                                 */
19554         } PIPEMAXP_b;
19555     };
19556 
19557     union
19558     {
19559         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
19560 
19561         struct
19562         {
19563             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalThese bits specify the
19564                                         *   transfer interval timing for the selected pipe as n-th
19565                                         *   power of 2 of the frame timing.                                           */
19566             uint16_t            : 9;
19567             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
19568             uint16_t            : 3;
19569         } PIPEPERI_b;
19570     };
19571 
19572     union
19573     {
19574         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) PIPE Control Register                                      */
19575 
19576         struct
19577         {
19578             __IOM uint16_t PID : 2;    /*!< [1..0] Response PIDThese bits specify the response type for
19579                                         *   the next transaction of the relevant pipe.                                */
19580             uint16_t            : 3;
19581             __IM uint16_t PBUSY : 1;   /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe
19582                                         *   is being used for the USB bus                                             */
19583             __IM uint16_t SQMON : 1;   /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected
19584                                         *   value of the sequence toggle bit for the next transaction
19585                                         *   of the relevant pipe                                                      */
19586             __IOM uint16_t SQSET : 1;  /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected
19587                                         *   value of the sequence toggle bit for the next transaction
19588                                         *   of the relevant pipe is set for DATA1                                     */
19589             __IOM uint16_t SQCLR : 1;  /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected
19590                                         *   value of the sequence toggle bit for the next transaction
19591                                         *   of the relevant pipe is cleared to DATA0                                  */
19592             __IOM uint16_t ACLRM : 1;  /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto
19593                                         *   buffer clear mode for the relevant pipe                                   */
19594             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto
19595                                         *   response mode for the relevant pipe.                                      */
19596             uint16_t            : 1;
19597             __IM uint16_t CSSTS : 1;   /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
19598                                         *   Split Transaction of the relevant pipe                                    */
19599             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
19600                                         *   the CSSTS bit of the relevant pipe                                        */
19601             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO
19602                                         *   buffer status for the relevant pipe in the transmitting
19603                                         *   direction.                                                                */
19604             __IM uint16_t BSTS : 1;    /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status
19605                                         *   for the relevant pipe.                                                    */
19606         } PIPE_CTR_b[9];
19607     };
19608     __IM uint16_t                RESERVED12;
19609     __IM uint32_t                RESERVED13[3];
19610     __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
19611     __IM uint32_t                RESERVED14[11];
19612 
19613     union
19614     {
19615         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
19616 
19617         struct
19618         {
19619             uint16_t               : 6;
19620             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
19621             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
19622             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
19623             uint16_t               : 1;
19624         } DEVADD_b[10];
19625     };
19626     __IM uint32_t RESERVED15[7];
19627 
19628     union
19629     {
19630         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
19631 
19632         struct
19633         {
19634             uint16_t             : 7;
19635             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
19636             uint16_t             : 8;
19637         } LPCTRL_b;
19638     };
19639 
19640     union
19641     {
19642         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
19643 
19644         struct
19645         {
19646             uint16_t                : 14;
19647             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
19648             uint16_t                : 1;
19649         } LPSTS_b;
19650     };
19651     __IM uint32_t RESERVED16[15];
19652 
19653     union
19654     {
19655         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
19656 
19657         struct
19658         {
19659             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
19660             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
19661             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
19662             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
19663             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
19664             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
19665             uint16_t                : 2;
19666             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
19667             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
19668             uint16_t                : 6;
19669         } BCCTRL_b;
19670     };
19671     __IM uint16_t RESERVED17;
19672 
19673     union
19674     {
19675         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
19676 
19677         struct
19678         {
19679             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
19680             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
19681             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
19682                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
19683             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
19684                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
19685             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
19686                                           *   value used for L1NEGOMD.The format is the same as the HIRD
19687                                           *   field in HL1CTRL.                                                         */
19688             uint16_t               : 2;
19689             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
19690             uint16_t               : 1;
19691         } PL1CTRL1_b;
19692     };
19693 
19694     union
19695     {
19696         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
19697 
19698         struct
19699         {
19700             uint16_t               : 8;
19701             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
19702             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
19703             uint16_t               : 3;
19704         } PL1CTRL2_b;
19705     };
19706 
19707     union
19708     {
19709         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
19710 
19711         struct
19712         {
19713             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
19714             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
19715             uint16_t                : 13;
19716         } HL1CTRL1_b;
19717     };
19718 
19719     union
19720     {
19721         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
19722 
19723         struct
19724         {
19725             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
19726                                         *   be set in the ADDR field of LPM token.                                    */
19727             uint16_t             : 4;
19728             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
19729             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
19730                                         *   value to be set in the RWE field of LPM token.                            */
19731             uint16_t            : 2;
19732             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
19733                                         *   period at the time of L1 Resume.                                          */
19734         } HL1CTRL2_b;
19735     };
19736     __IM uint32_t RESERVED18;
19737 
19738     union
19739     {
19740         __IOM uint16_t PHYTRIM1;          /*!< (@ 0x00000150) PHY Timing Register 1                                      */
19741 
19742         struct
19743         {
19744             __IOM uint16_t DRISE     : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function              */
19745             __IOM uint16_t DFALL     : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function             */
19746             uint16_t                 : 3;
19747             __IOM uint16_t PCOMPENB  : 1; /*!< [7..7] PVDD Start-up Detection                                            */
19748             __IOM uint16_t HSIUP     : 4; /*!< [11..8] HS Output Level Setting                                           */
19749             __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset
19750                                            *   value for adjusting the terminating resistance.                           */
19751             uint16_t : 1;
19752         } PHYTRIM1_b;
19753     };
19754 
19755     union
19756     {
19757         __IOM uint16_t PHYTRIM2;         /*!< (@ 0x00000152) PHY Timing Register 2                                      */
19758 
19759         struct
19760         {
19761             __IOM uint16_t SQU      : 4; /*!< [3..0] Squelch Detection Level                                            */
19762             uint16_t                : 3;
19763             __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode                                     */
19764             __IOM uint16_t PDR      : 2; /*!< [9..8] HS Output Adjustment Function                                      */
19765             uint16_t                : 2;
19766             __IOM uint16_t DIS      : 3; /*!< [14..12] Disconnect Detection Level                                       */
19767             uint16_t                : 1;
19768         } PHYTRIM2_b;
19769     };
19770     __IM uint32_t RESERVED19[3];
19771 
19772     union
19773     {
19774         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
19775                                         *                  Register                                                   */
19776 
19777         struct
19778         {
19779             uint32_t              : 20;
19780             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
19781                                          *   HS side of USB port.                                                      */
19782             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
19783                                          *   HS side of USB port.                                                      */
19784             uint32_t               : 1;
19785             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
19786                                          *   of USB port.                                                              */
19787             uint32_t : 8;
19788         } DPUSR0R_b;
19789     };
19790 
19791     union
19792     {
19793         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
19794 
19795         struct
19796         {
19797             uint32_t                : 4;
19798             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
19799             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
19800             uint32_t                : 1;
19801             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
19802             uint32_t                : 12;
19803             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
19804             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
19805             uint32_t                : 1;
19806             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
19807             uint32_t                : 8;
19808         } DPUSR1R_b;
19809     };
19810 
19811     union
19812     {
19813         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
19814 
19815         struct
19816         {
19817             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
19818             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
19819             uint16_t            : 2;
19820             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
19821                                         *   port.                                                                     */
19822             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
19823                                         *   port.                                                                     */
19824             uint16_t              : 2;
19825             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
19826             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
19827             uint16_t              : 6;
19828         } DPUSR2R_b;
19829     };
19830 
19831     union
19832     {
19833         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
19834 
19835         struct
19836         {
19837             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
19838             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
19839             uint16_t                : 14;
19840         } DPUSRCR_b;
19841     };
19842 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
19843 
19844 /* =========================================================================================================================== */
19845 /* ================                                          R_AGTX0                                          ================ */
19846 /* =========================================================================================================================== */
19847 
19848 /**
19849  * @brief Asynchronous General Purpose Timer (R_AGTX0)
19850  */
19851 
19852 typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
19853 {
19854     union
19855     {
19856         __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
19857         __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
19858     };
19859 } R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
19860 
19861 /** @} */ /* End of group Device_Peripheral_peripherals */
19862 
19863 /* =========================================================================================================================== */
19864 /* ================                          Device Specific Peripheral Address Map                           ================ */
19865 /* =========================================================================================================================== */
19866 
19867 /** @addtogroup Device_Peripheral_peripheralAddr
19868  * @{
19869  */
19870 
19871  #define R_ACMPHS0_BASE                0x40085000UL
19872  #define R_ACMPHS1_BASE                0x40085100UL
19873  #define R_ACMPHS2_BASE                0x40085200UL
19874  #define R_ACMPHS3_BASE                0x40085300UL
19875  #define R_ACMPHS4_BASE                0x40085400UL
19876  #define R_ACMPHS5_BASE                0x40085500UL
19877  #define R_ADC0_BASE                   0x4005C000UL
19878  #define R_ADC1_BASE                   0x4005C200UL
19879  #define R_BUS_BASE                    0x40003000UL
19880  #define R_CAC_BASE                    0x40044600UL
19881  #define R_CAN0_BASE                   0x40050000UL
19882  #define R_CAN1_BASE                   0x40051000UL
19883  #define R_CRC_BASE                    0x40074000UL
19884  #define R_CTSU_BASE                   0x40081000UL
19885  #define R_DAC_BASE                    0x4005E000UL
19886  #define R_DEBUG_BASE                  0x4001B000UL
19887  #define R_DMA_BASE                    0x40005200UL
19888  #define R_DMAC0_BASE                  0x40005000UL
19889  #define R_DMAC1_BASE                  0x40005040UL
19890  #define R_DMAC2_BASE                  0x40005080UL
19891  #define R_DMAC3_BASE                  0x400050C0UL
19892  #define R_DMAC4_BASE                  0x40005100UL
19893  #define R_DMAC5_BASE                  0x40005140UL
19894  #define R_DMAC6_BASE                  0x40005180UL
19895  #define R_DMAC7_BASE                  0x400051C0UL
19896  #define R_DOC_BASE                    0x40054100UL
19897  #define R_DRW_BASE                    0x400E4000UL
19898  #define R_DTC_BASE                    0x40005400UL
19899  #define R_ELC_BASE                    0x40041000UL
19900  #define R_ETHERC0_BASE                0x40064100UL
19901  #define R_ETHERC_EDMAC_BASE           0x40064000UL
19902  #define R_PTP_EDMAC_BASE              0x40064400UL
19903  #define R_ETHERC_EPTPC_BASE           0x40065800UL
19904  #define R_ETHERC_EPTPC1_BASE          0x40065C00UL
19905  #define R_ETHERC_EPTPC_CFG_BASE       0x40064500UL
19906  #define R_ETHERC_EPTPC_COMMON_BASE    0x40065000UL
19907  #define R_FACI_HP_CMD_BASE            0x407E0000UL
19908  #define R_FACI_HP_BASE                0x407FE000UL
19909  #define R_FCACHE_BASE                 0x4001C000UL
19910  #define R_GLCDC_BASE                  0x400E0000UL
19911  #define R_GPT0_BASE                   0x40078000UL
19912  #define R_GPT1_BASE                   0x40078100UL
19913  #define R_GPT2_BASE                   0x40078200UL
19914  #define R_GPT3_BASE                   0x40078300UL
19915  #define R_GPT4_BASE                   0x40078400UL
19916  #define R_GPT5_BASE                   0x40078500UL
19917  #define R_GPT6_BASE                   0x40078600UL
19918  #define R_GPT7_BASE                   0x40078700UL
19919  #define R_GPT8_BASE                   0x40078800UL
19920  #define R_GPT9_BASE                   0x40078900UL
19921  #define R_GPT10_BASE                  0x40078A00UL
19922  #define R_GPT11_BASE                  0x40078B00UL
19923  #define R_GPT12_BASE                  0x40078C00UL
19924  #define R_GPT13_BASE                  0x40078D00UL
19925  #define R_GPT_ODC_BASE                0x4007B000UL
19926  #define R_GPT_OPS_BASE                0x40078FF0UL
19927  #define R_GPT_POEG0_BASE              0x40042000UL
19928  #define R_GPT_POEG1_BASE              0x40042100UL
19929  #define R_GPT_POEG2_BASE              0x40042200UL
19930  #define R_GPT_POEG3_BASE              0x40042300UL
19931  #define R_ICU_BASE                    0x40006000UL
19932  #define R_IIC0_BASE                   0x40053000UL
19933  #define R_IIC1_BASE                   0x40053100UL
19934  #define R_IIC2_BASE                   0x40053200UL
19935  #define R_IRDA_BASE                   0x40070F00UL
19936  #define R_IWDT_BASE                   0x40044400UL
19937  #define R_JPEG_BASE                   0x400E6000UL
19938  #define R_KINT_BASE                   0x40080000UL
19939  #define R_MMF_BASE                    0x40001000UL
19940  #define R_MPU_MMPU_BASE               0x40000000UL
19941  #define R_MPU_SMPU_BASE               0x40000C00UL
19942  #define R_MPU_SPMON_BASE              0x40000D00UL
19943  #define R_MSTP_BASE                   (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */
19944  #define R_PDC_BASE                    0x40094000UL
19945  #define R_PORT0_BASE                  0x40040000UL
19946  #define R_PORT1_BASE                  0x40040020UL
19947  #define R_PORT2_BASE                  0x40040040UL
19948  #define R_PORT3_BASE                  0x40040060UL
19949  #define R_PORT4_BASE                  0x40040080UL
19950  #define R_PORT5_BASE                  0x400400A0UL
19951  #define R_PORT6_BASE                  0x400400C0UL
19952  #define R_PORT7_BASE                  0x400400E0UL
19953  #define R_PORT8_BASE                  0x40040100UL
19954  #define R_PORT9_BASE                  0x40040120UL
19955  #define R_PORT10_BASE                 0x40040140UL
19956  #define R_PORT11_BASE                 0x40040160UL
19957  #define R_PORT12_BASE                 0x40040180UL
19958  #define R_PORT13_BASE                 0x400401A0UL
19959  #define R_PORT14_BASE                 0x400401C0UL
19960  #define R_PFS_BASE                    0x40040800UL
19961  #define R_PMISC_BASE                  0x40040D00UL
19962  #define R_QSPI_BASE                   0x64000000UL
19963  #define R_RTC_BASE                    0x40044000UL
19964  #define R_SCI0_BASE                   0x40070000UL
19965  #define R_SCI1_BASE                   0x40070020UL
19966  #define R_SCI2_BASE                   0x40070040UL
19967  #define R_SCI3_BASE                   0x40070060UL
19968  #define R_SCI4_BASE                   0x40070080UL
19969  #define R_SCI5_BASE                   0x400700A0UL
19970  #define R_SCI6_BASE                   0x400700C0UL
19971  #define R_SCI7_BASE                   0x400700E0UL
19972  #define R_SCI8_BASE                   0x40070100UL
19973  #define R_SCI9_BASE                   0x40070120UL
19974  #define R_SDHI0_BASE                  0x40062000UL
19975  #define R_SDHI1_BASE                  0x40062400UL
19976  #define R_SPI0_BASE                   0x40072000UL
19977  #define R_SPI1_BASE                   0x40072100UL
19978  #define R_SRAM_BASE                   0x40002000UL
19979  #define R_SRC_BASE                    0x40048000UL
19980  #define R_SSI0_BASE                   0x4004E000UL
19981  #define R_SSI1_BASE                   0x4004E100UL
19982  #define R_SYSTEM_BASE                 0x4001E000UL
19983  #define R_TSN_CAL_BASE                0x407FB17CUL
19984  #define R_TSN_CTRL_BASE               0x4005D000UL
19985  #define R_USB_FS0_BASE                0x40090000UL
19986  #define R_WDT_BASE                    0x40044200UL
19987  #define R_USB_HS0_BASE                0x40060000UL
19988  #define R_AGTX0_BASE                  0x40084000UL
19989  #define R_AGTX1_BASE                  0x40084100UL
19990  #define R_AGTX2_BASE                  0x40084200UL
19991  #define R_AGTX3_BASE                  0x40084300UL
19992  #define R_AGTX4_BASE                  0x40084400UL
19993  #define R_AGTX5_BASE                  0x40084500UL
19994  #define R_AGTX6_BASE                  0x40084600UL
19995  #define R_AGTX7_BASE                  0x40084700UL
19996  #define R_AGTX8_BASE                  0x40084800UL
19997  #define R_AGTX9_BASE                  0x40084900UL
19998 
19999 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
20000 
20001 /* =========================================================================================================================== */
20002 /* ================                                  Peripheral declaration                                   ================ */
20003 /* =========================================================================================================================== */
20004 
20005 /** @addtogroup Device_Peripheral_declaration
20006  * @{
20007  */
20008 
20009  #define R_ACMPHS0                ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
20010  #define R_ACMPHS1                ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
20011  #define R_ACMPHS2                ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
20012  #define R_ACMPHS3                ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
20013  #define R_ACMPHS4                ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
20014  #define R_ACMPHS5                ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
20015  #define R_ADC0                   ((R_ADC0_Type *) R_ADC0_BASE)
20016  #define R_ADC1                   ((R_ADC0_Type *) R_ADC1_BASE)
20017  #define R_BUS                    ((R_BUS_Type *) R_BUS_BASE)
20018  #define R_CAC                    ((R_CAC_Type *) R_CAC_BASE)
20019  #define R_CAN0                   ((R_CAN0_Type *) R_CAN0_BASE)
20020  #define R_CAN1                   ((R_CAN0_Type *) R_CAN1_BASE)
20021  #define R_CRC                    ((R_CRC_Type *) R_CRC_BASE)
20022  #define R_CTSU                   ((R_CTSU_Type *) R_CTSU_BASE)
20023  #define R_DAC                    ((R_DAC_Type *) R_DAC_BASE)
20024  #define R_DEBUG                  ((R_DEBUG_Type *) R_DEBUG_BASE)
20025  #define R_DMA                    ((R_DMA_Type *) R_DMA_BASE)
20026  #define R_DMAC0                  ((R_DMAC0_Type *) R_DMAC0_BASE)
20027  #define R_DMAC1                  ((R_DMAC0_Type *) R_DMAC1_BASE)
20028  #define R_DMAC2                  ((R_DMAC0_Type *) R_DMAC2_BASE)
20029  #define R_DMAC3                  ((R_DMAC0_Type *) R_DMAC3_BASE)
20030  #define R_DMAC4                  ((R_DMAC0_Type *) R_DMAC4_BASE)
20031  #define R_DMAC5                  ((R_DMAC0_Type *) R_DMAC5_BASE)
20032  #define R_DMAC6                  ((R_DMAC0_Type *) R_DMAC6_BASE)
20033  #define R_DMAC7                  ((R_DMAC0_Type *) R_DMAC7_BASE)
20034  #define R_DOC                    ((R_DOC_Type *) R_DOC_BASE)
20035  #define R_DRW                    ((R_DRW_Type *) R_DRW_BASE)
20036  #define R_DTC                    ((R_DTC_Type *) R_DTC_BASE)
20037  #define R_ELC                    ((R_ELC_Type *) R_ELC_BASE)
20038  #define R_ETHERC0                ((R_ETHERC0_Type *) R_ETHERC0_BASE)
20039  #define R_ETHERC_EDMAC           ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
20040  #define R_PTP_EDMAC              ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE)
20041  #define R_ETHERC_EPTPC           ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE)
20042  #define R_ETHERC_EPTPC1          ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC1_BASE)
20043  #define R_ETHERC_EPTPC_CFG       ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE)
20044  #define R_ETHERC_EPTPC_COMMON    ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE)
20045  #define R_FACI_HP_CMD            ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
20046  #define R_FACI_HP                ((R_FACI_HP_Type *) R_FACI_HP_BASE)
20047  #define R_FCACHE                 ((R_FCACHE_Type *) R_FCACHE_BASE)
20048  #define R_GLCDC                  ((R_GLCDC_Type *) R_GLCDC_BASE)
20049  #define R_GPT0                   ((R_GPT0_Type *) R_GPT0_BASE)
20050  #define R_GPT1                   ((R_GPT0_Type *) R_GPT1_BASE)
20051  #define R_GPT2                   ((R_GPT0_Type *) R_GPT2_BASE)
20052  #define R_GPT3                   ((R_GPT0_Type *) R_GPT3_BASE)
20053  #define R_GPT4                   ((R_GPT0_Type *) R_GPT4_BASE)
20054  #define R_GPT5                   ((R_GPT0_Type *) R_GPT5_BASE)
20055  #define R_GPT6                   ((R_GPT0_Type *) R_GPT6_BASE)
20056  #define R_GPT7                   ((R_GPT0_Type *) R_GPT7_BASE)
20057  #define R_GPT8                   ((R_GPT0_Type *) R_GPT8_BASE)
20058  #define R_GPT9                   ((R_GPT0_Type *) R_GPT9_BASE)
20059  #define R_GPT10                  ((R_GPT0_Type *) R_GPT10_BASE)
20060  #define R_GPT11                  ((R_GPT0_Type *) R_GPT11_BASE)
20061  #define R_GPT12                  ((R_GPT0_Type *) R_GPT12_BASE)
20062  #define R_GPT13                  ((R_GPT0_Type *) R_GPT13_BASE)
20063  #define R_GPT_ODC                ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
20064  #define R_GPT_OPS                ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
20065  #define R_GPT_POEG0              ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
20066  #define R_GPT_POEG1              ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
20067  #define R_GPT_POEG2              ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
20068  #define R_GPT_POEG3              ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
20069  #define R_ICU                    ((R_ICU_Type *) R_ICU_BASE)
20070  #define R_IIC0                   ((R_IIC0_Type *) R_IIC0_BASE)
20071  #define R_IIC1                   ((R_IIC0_Type *) R_IIC1_BASE)
20072  #define R_IIC2                   ((R_IIC0_Type *) R_IIC2_BASE)
20073  #define R_IRDA                   ((R_IRDA_Type *) R_IRDA_BASE)
20074  #define R_IWDT                   ((R_IWDT_Type *) R_IWDT_BASE)
20075  #define R_JPEG                   ((R_JPEG_Type *) R_JPEG_BASE)
20076  #define R_KINT                   ((R_KINT_Type *) R_KINT_BASE)
20077  #define R_MMF                    ((R_MMF_Type *) R_MMF_BASE)
20078  #define R_MPU_MMPU               ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
20079  #define R_MPU_SMPU               ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
20080  #define R_MPU_SPMON              ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
20081  #define R_MSTP                   ((R_MSTP_Type *) R_MSTP_BASE)
20082  #define R_PDC                    ((R_PDC_Type *) R_PDC_BASE)
20083  #define R_PORT0                  ((R_PORT0_Type *) R_PORT0_BASE)
20084  #define R_PORT1                  ((R_PORT0_Type *) R_PORT1_BASE)
20085  #define R_PORT2                  ((R_PORT0_Type *) R_PORT2_BASE)
20086  #define R_PORT3                  ((R_PORT0_Type *) R_PORT3_BASE)
20087  #define R_PORT4                  ((R_PORT0_Type *) R_PORT4_BASE)
20088  #define R_PORT5                  ((R_PORT0_Type *) R_PORT5_BASE)
20089  #define R_PORT6                  ((R_PORT0_Type *) R_PORT6_BASE)
20090  #define R_PORT7                  ((R_PORT0_Type *) R_PORT7_BASE)
20091  #define R_PORT8                  ((R_PORT0_Type *) R_PORT8_BASE)
20092  #define R_PORT9                  ((R_PORT0_Type *) R_PORT9_BASE)
20093  #define R_PORT10                 ((R_PORT0_Type *) R_PORT10_BASE)
20094  #define R_PORT11                 ((R_PORT0_Type *) R_PORT11_BASE)
20095  #define R_PORT12                 ((R_PORT0_Type *) R_PORT12_BASE)
20096  #define R_PORT13                 ((R_PORT0_Type *) R_PORT13_BASE)
20097  #define R_PORT14                 ((R_PORT0_Type *) R_PORT14_BASE)
20098  #define R_PFS                    ((R_PFS_Type *) R_PFS_BASE)
20099  #define R_PMISC                  ((R_PMISC_Type *) R_PMISC_BASE)
20100  #define R_QSPI                   ((R_QSPI_Type *) R_QSPI_BASE)
20101  #define R_RTC                    ((R_RTC_Type *) R_RTC_BASE)
20102  #define R_SCI0                   ((R_SCI0_Type *) R_SCI0_BASE)
20103  #define R_SCI1                   ((R_SCI0_Type *) R_SCI1_BASE)
20104  #define R_SCI2                   ((R_SCI0_Type *) R_SCI2_BASE)
20105  #define R_SCI3                   ((R_SCI0_Type *) R_SCI3_BASE)
20106  #define R_SCI4                   ((R_SCI0_Type *) R_SCI4_BASE)
20107  #define R_SCI5                   ((R_SCI0_Type *) R_SCI5_BASE)
20108  #define R_SCI6                   ((R_SCI0_Type *) R_SCI6_BASE)
20109  #define R_SCI7                   ((R_SCI0_Type *) R_SCI7_BASE)
20110  #define R_SCI8                   ((R_SCI0_Type *) R_SCI8_BASE)
20111  #define R_SCI9                   ((R_SCI0_Type *) R_SCI9_BASE)
20112  #define R_SDHI0                  ((R_SDHI0_Type *) R_SDHI0_BASE)
20113  #define R_SDHI1                  ((R_SDHI0_Type *) R_SDHI1_BASE)
20114  #define R_SPI0                   ((R_SPI0_Type *) R_SPI0_BASE)
20115  #define R_SPI1                   ((R_SPI0_Type *) R_SPI1_BASE)
20116  #define R_SRAM                   ((R_SRAM_Type *) R_SRAM_BASE)
20117  #define R_SRC                    ((R_SRC_Type *) R_SRC_BASE)
20118  #define R_SSI0                   ((R_SSI0_Type *) R_SSI0_BASE)
20119  #define R_SSI1                   ((R_SSI0_Type *) R_SSI1_BASE)
20120  #define R_SYSTEM                 ((R_SYSTEM_Type *) R_SYSTEM_BASE)
20121  #define R_TSN_CAL                ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
20122  #define R_TSN_CTRL               ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
20123  #define R_USB_FS0                ((R_USB_FS0_Type *) R_USB_FS0_BASE)
20124  #define R_WDT                    ((R_WDT_Type *) R_WDT_BASE)
20125  #define R_USB_HS0                ((R_USB_HS0_Type *) R_USB_HS0_BASE)
20126  #define R_AGT0                   ((R_AGTX0_Type *) R_AGTX0_BASE)
20127  #define R_AGT1                   ((R_AGTX0_Type *) R_AGTX1_BASE)
20128  #define R_AGT2                   ((R_AGTX0_Type *) R_AGTX2_BASE)
20129  #define R_AGT3                   ((R_AGTX0_Type *) R_AGTX3_BASE)
20130  #define R_AGT4                   ((R_AGTX0_Type *) R_AGTX4_BASE)
20131  #define R_AGT5                   ((R_AGTX0_Type *) R_AGTX5_BASE)
20132  #define R_AGT6                   ((R_AGTX0_Type *) R_AGTX6_BASE)
20133  #define R_AGT7                   ((R_AGTX0_Type *) R_AGTX7_BASE)
20134  #define R_AGT8                   ((R_AGTX0_Type *) R_AGTX8_BASE)
20135  #define R_AGT9                   ((R_AGTX0_Type *) R_AGTX9_BASE)
20136 
20137 /** @} */ /* End of group Device_Peripheral_declaration */
20138 
20139 /* =========================================  End of section using anonymous unions  ========================================= */
20140  #if defined(__CC_ARM)
20141   #pragma pop
20142  #elif defined(__ICCARM__)
20143 
20144 /* leave anonymous unions enabled */
20145  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
20146   #pragma clang diagnostic pop
20147  #elif defined(__GNUC__)
20148 
20149 /* anonymous unions are enabled by default */
20150  #elif defined(__TMS470__)
20151 
20152 /* anonymous unions are enabled by default */
20153  #elif defined(__TASKING__)
20154   #pragma warning restore
20155  #elif defined(__CSMC__)
20156 
20157 /* anonymous unions are enabled by default */
20158  #endif
20159 
20160 /* =========================================================================================================================== */
20161 /* ================                                 Pos/Mask Cluster Section                                  ================ */
20162 /* =========================================================================================================================== */
20163 
20164 /** @addtogroup PosMask_clusters
20165  * @{
20166  */
20167 
20168 /* =========================================================================================================================== */
20169 /* ================                                            CSa                                            ================ */
20170 /* =========================================================================================================================== */
20171 
20172 /* ==========================================================  MOD  ========================================================== */
20173  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
20174  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
20175  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
20176  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
20177  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
20178  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
20179  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
20180  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
20181  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
20182  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
20183 /* =========================================================  WCR1  ========================================================== */
20184  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
20185  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
20186  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
20187  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
20188  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
20189  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
20190  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
20191  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
20192 /* =========================================================  WCR2  ========================================================== */
20193  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
20194  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
20195  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
20196  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
20197  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
20198  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
20199  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
20200  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
20201  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
20202  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
20203  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
20204  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
20205  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
20206  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
20207  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
20208  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
20209 
20210 /* =========================================================================================================================== */
20211 /* ================                                            CSb                                            ================ */
20212 /* =========================================================================================================================== */
20213 
20214 /* ==========================================================  CR  =========================================================== */
20215  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
20216  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
20217  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
20218  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
20219  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
20220  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
20221  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
20222  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
20223 /* ==========================================================  REC  ========================================================== */
20224  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
20225  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
20226  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
20227  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
20228 
20229 /* =========================================================================================================================== */
20230 /* ================                                           SDRAM                                           ================ */
20231 /* =========================================================================================================================== */
20232 
20233 /* =========================================================  SDCCR  ========================================================= */
20234  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
20235  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
20236  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
20237  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
20238 /* ========================================================  SDCMOD  ========================================================= */
20239  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
20240  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
20241 /* ========================================================  SDAMOD  ========================================================= */
20242  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
20243  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
20244 /* ========================================================  SDSELF  ========================================================= */
20245  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
20246  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
20247 /* ========================================================  SDRFCR  ========================================================= */
20248  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
20249  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
20250  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
20251  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
20252 /* ========================================================  SDRFEN  ========================================================= */
20253  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
20254  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
20255 /* =========================================================  SDICR  ========================================================= */
20256  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
20257  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
20258 /* =========================================================  SDIR  ========================================================== */
20259  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
20260  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
20261  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
20262  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
20263  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
20264  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
20265 /* =========================================================  SDADR  ========================================================= */
20266  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
20267  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
20268 /* =========================================================  SDTR  ========================================================== */
20269  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
20270  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
20271  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
20272  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
20273  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
20274  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
20275  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
20276  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
20277  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
20278  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
20279 /* =========================================================  SDMOD  ========================================================= */
20280  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
20281  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
20282 /* =========================================================  SDSR  ========================================================== */
20283  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
20284  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
20285  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
20286  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
20287  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
20288  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
20289 
20290 /* =========================================================================================================================== */
20291 /* ================                                          BUSERRa                                          ================ */
20292 /* =========================================================================================================================== */
20293 
20294 /* ==========================================================  ADD  ========================================================== */
20295  #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
20296  #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
20297 /* =========================================================  STAT  ========================================================== */
20298  #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
20299  #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
20300  #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
20301  #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
20302 /* ==========================================================  RW  =========================================================== */
20303  #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
20304  #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
20305 
20306 /* =========================================================================================================================== */
20307 /* ================                                          BTZFERR                                          ================ */
20308 /* =========================================================================================================================== */
20309 
20310 /* ==========================================================  ADD  ========================================================== */
20311  #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
20312  #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
20313 /* ==========================================================  RW  =========================================================== */
20314  #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
20315  #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
20316 
20317 /* =========================================================================================================================== */
20318 /* ================                                          BUSERRb                                          ================ */
20319 /* =========================================================================================================================== */
20320 
20321 /* =========================================================  STAT  ========================================================== */
20322  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
20323  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
20324  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
20325  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
20326  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
20327  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
20328  #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
20329  #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
20330  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
20331  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
20332 /* ==========================================================  CLR  ========================================================== */
20333  #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
20334  #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
20335  #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
20336  #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
20337  #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
20338  #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
20339  #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
20340  #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
20341  #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
20342  #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
20343 
20344 /* =========================================================================================================================== */
20345 /* ================                                        DMACDTCERR                                         ================ */
20346 /* =========================================================================================================================== */
20347 
20348 /* =========================================================  STAT  ========================================================== */
20349  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
20350  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
20351 /* ==========================================================  CLR  ========================================================== */
20352  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
20353  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
20354 
20355 /* =========================================================================================================================== */
20356 /* ================                                         BUSSABT0                                          ================ */
20357 /* =========================================================================================================================== */
20358 
20359 /* =========================================================  FLBI  ========================================================== */
20360  #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20361  #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20362 /* ========================================================  MRE0BI  ========================================================= */
20363  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
20364  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20365 /* =========================================================  S0BI  ========================================================== */
20366  #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20367  #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20368 /* =========================================================  S1BI  ========================================================== */
20369  #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20370  #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20371 /* =========================================================  S2BI  ========================================================== */
20372  #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20373  #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20374 /* =========================================================  S3BI  ========================================================== */
20375  #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20376  #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20377 /* ========================================================  STBYSBI  ======================================================== */
20378  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20379  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20380 /* =========================================================  ECBI  ========================================================== */
20381  #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20382  #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20383 /* =========================================================  EOBI  ========================================================== */
20384  #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20385  #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20386 /* ========================================================  SPI0BI  ========================================================= */
20387  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
20388  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20389 /* ========================================================  SPI1BI  ========================================================= */
20390  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
20391  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20392 /* =========================================================  PBBI  ========================================================== */
20393  #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20394  #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20395 /* =========================================================  PABI  ========================================================== */
20396  #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20397  #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20398 /* =========================================================  PIBI  ========================================================== */
20399  #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20400  #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20401 /* =========================================================  PSBI  ========================================================== */
20402  #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20403  #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20404 /* =======================================================  CPU0SAHBI  ======================================================= */
20405  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
20406  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20407 /* =======================================================  CPU1TCMBI  ======================================================= */
20408  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
20409  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20410 
20411 /* =========================================================================================================================== */
20412 /* ================                                         BUSSABT1                                          ================ */
20413 /* =========================================================================================================================== */
20414 
20415 /* =========================================================  FHBI  ========================================================== */
20416  #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20417  #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20418 /* ========================================================  MRC0BI  ========================================================= */
20419  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
20420  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20421 /* =========================================================  S0BI  ========================================================== */
20422  #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20423  #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20424 /* =========================================================  S1BI  ========================================================== */
20425  #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20426  #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20427 
20428 /* =========================================================================================================================== */
20429 /* ================                                          BMSAERR                                          ================ */
20430 /* =========================================================================================================================== */
20431 
20432 /* ==========================================================  ADD  ========================================================== */
20433  #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
20434  #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
20435 /* ==========================================================  RW  =========================================================== */
20436  #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
20437  #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */
20438 
20439 /* =========================================================================================================================== */
20440 /* ================                                            OAD                                            ================ */
20441 /* =========================================================================================================================== */
20442 
20443 /* ========================================================  BUSOAD  ========================================================= */
20444  #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
20445  #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
20446  #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
20447  #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
20448  #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
20449  #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
20450 /* =======================================================  BUSOADPT  ======================================================== */
20451  #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
20452  #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20453  #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
20454  #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20455 /* ========================================================  MSAOAD  ========================================================= */
20456  #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
20457  #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20458  #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
20459  #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
20460 /* =========================================================  MSAPT  ========================================================= */
20461  #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
20462  #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20463  #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
20464  #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20465 
20466 /* =========================================================================================================================== */
20467 /* ================                                          MBWERR                                           ================ */
20468 /* =========================================================================================================================== */
20469 
20470 /* =========================================================  STAT  ========================================================== */
20471  #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
20472  #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
20473 /* ==========================================================  CLR  ========================================================== */
20474  #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
20475  #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
20476 
20477 /* =========================================================================================================================== */
20478 /* ================                                           BUSM                                            ================ */
20479 /* =========================================================================================================================== */
20480 
20481 /* ==========================================================  CNT  ========================================================== */
20482  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
20483  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
20484 
20485 /* =========================================================================================================================== */
20486 /* ================                                           BUSS                                            ================ */
20487 /* =========================================================================================================================== */
20488 
20489 /* ==========================================================  CNT  ========================================================== */
20490  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
20491  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
20492  #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
20493  #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */
20494 
20495 /* =========================================================================================================================== */
20496 /* ================                                            MB                                             ================ */
20497 /* =========================================================================================================================== */
20498 
20499 /* ==========================================================  ID  =========================================================== */
20500  #define R_CAN0_MB_ID_IDE_Pos    (31UL)         /*!< IDE (Bit 31)                                          */
20501  #define R_CAN0_MB_ID_IDE_Msk    (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
20502  #define R_CAN0_MB_ID_RTR_Pos    (30UL)         /*!< RTR (Bit 30)                                          */
20503  #define R_CAN0_MB_ID_RTR_Msk    (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
20504  #define R_CAN0_MB_ID_SID_Pos    (18UL)         /*!< SID (Bit 18)                                          */
20505  #define R_CAN0_MB_ID_SID_Msk    (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
20506  #define R_CAN0_MB_ID_EID_Pos    (0UL)          /*!< EID (Bit 0)                                           */
20507  #define R_CAN0_MB_ID_EID_Msk    (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
20508 /* ==========================================================  DL  =========================================================== */
20509  #define R_CAN0_MB_DL_DLC_Pos    (0UL)          /*!< DLC (Bit 0)                                           */
20510  #define R_CAN0_MB_DL_DLC_Msk    (0xfUL)        /*!< DLC (Bitfield-Mask: 0x0f)                             */
20511 /* ===========================================================  D  =========================================================== */
20512  #define R_CAN0_MB_D_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
20513  #define R_CAN0_MB_D_DATA_Msk    (0xffUL)       /*!< DATA (Bitfield-Mask: 0xff)                            */
20514 /* ==========================================================  TS  =========================================================== */
20515  #define R_CAN0_MB_TS_TSH_Pos    (8UL)          /*!< TSH (Bit 8)                                           */
20516  #define R_CAN0_MB_TS_TSH_Msk    (0xff00UL)     /*!< TSH (Bitfield-Mask: 0xff)                             */
20517  #define R_CAN0_MB_TS_TSL_Pos    (0UL)          /*!< TSL (Bit 0)                                           */
20518  #define R_CAN0_MB_TS_TSL_Msk    (0xffUL)       /*!< TSL (Bitfield-Mask: 0xff)                             */
20519 
20520 /* =========================================================================================================================== */
20521 /* ================                                          ELSEGR                                           ================ */
20522 /* =========================================================================================================================== */
20523 
20524 /* ==========================================================  BY  =========================================================== */
20525  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
20526  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
20527  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
20528  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
20529  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
20530  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
20531 
20532 /* =========================================================================================================================== */
20533 /* ================                                           ELSR                                            ================ */
20534 /* =========================================================================================================================== */
20535 
20536 /* ==========================================================  HA  =========================================================== */
20537  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
20538  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
20539 
20540 /* =========================================================================================================================== */
20541 /* ================                                            TM                                             ================ */
20542 /* =========================================================================================================================== */
20543 
20544 /* =========================================================  STTRU  ========================================================= */
20545  #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos    (0UL)          /*!< TMSTTRU (Bit 0)                                       */
20546  #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk    (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff)                   */
20547 /* =========================================================  STTRL  ========================================================= */
20548  #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos    (0UL)          /*!< TMSTTRL (Bit 0)                                       */
20549  #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk    (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff)                   */
20550 /* =========================================================  CYCR  ========================================================== */
20551  #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos      (0UL)          /*!< TMCYCR (Bit 0)                                        */
20552  #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk      (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff)                    */
20553 /* =========================================================  PLSR  ========================================================== */
20554  #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos      (0UL)          /*!< TMPLSR (Bit 0)                                        */
20555  #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk      (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff)                    */
20556 
20557 /* =========================================================================================================================== */
20558 /* ================                                            PR                                             ================ */
20559 /* =========================================================================================================================== */
20560 
20561 /* =========================================================  MACRU  ========================================================= */
20562  #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos    (0UL)        /*!< PRMACRU (Bit 0)                                       */
20563  #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk    (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff)                     */
20564 /* =========================================================  MACRL  ========================================================= */
20565  #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos    (0UL)        /*!< PRMACRL (Bit 0)                                       */
20566  #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk    (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff)                     */
20567 
20568 /* =========================================================================================================================== */
20569 /* ================                                            BG                                             ================ */
20570 /* =========================================================================================================================== */
20571 
20572 /* ==========================================================  EN  =========================================================== */
20573  #define R_GLCDC_BG_EN_SWRST_Pos     (16UL)        /*!< SWRST (Bit 16)                                        */
20574  #define R_GLCDC_BG_EN_SWRST_Msk     (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
20575  #define R_GLCDC_BG_EN_VEN_Pos       (8UL)         /*!< VEN (Bit 8)                                           */
20576  #define R_GLCDC_BG_EN_VEN_Msk       (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
20577  #define R_GLCDC_BG_EN_EN_Pos        (0UL)         /*!< EN (Bit 0)                                            */
20578  #define R_GLCDC_BG_EN_EN_Msk        (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
20579 /* =========================================================  PERI  ========================================================== */
20580  #define R_GLCDC_BG_PERI_FV_Pos      (16UL)        /*!< FV (Bit 16)                                           */
20581  #define R_GLCDC_BG_PERI_FV_Msk      (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff)                             */
20582  #define R_GLCDC_BG_PERI_FH_Pos      (0UL)         /*!< FH (Bit 0)                                            */
20583  #define R_GLCDC_BG_PERI_FH_Msk      (0x7ffUL)     /*!< FH (Bitfield-Mask: 0x7ff)                             */
20584 /* =========================================================  SYNC  ========================================================== */
20585  #define R_GLCDC_BG_SYNC_VP_Pos      (16UL)        /*!< VP (Bit 16)                                           */
20586  #define R_GLCDC_BG_SYNC_VP_Msk      (0xf0000UL)   /*!< VP (Bitfield-Mask: 0x0f)                              */
20587  #define R_GLCDC_BG_SYNC_HP_Pos      (0UL)         /*!< HP (Bit 0)                                            */
20588  #define R_GLCDC_BG_SYNC_HP_Msk      (0xfUL)       /*!< HP (Bitfield-Mask: 0x0f)                              */
20589 /* =========================================================  VSIZE  ========================================================= */
20590  #define R_GLCDC_BG_VSIZE_VP_Pos     (16UL)        /*!< VP (Bit 16)                                           */
20591  #define R_GLCDC_BG_VSIZE_VP_Msk     (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff)                             */
20592  #define R_GLCDC_BG_VSIZE_VW_Pos     (0UL)         /*!< VW (Bit 0)                                            */
20593  #define R_GLCDC_BG_VSIZE_VW_Msk     (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
20594 /* =========================================================  HSIZE  ========================================================= */
20595  #define R_GLCDC_BG_HSIZE_HP_Pos     (16UL)        /*!< HP (Bit 16)                                           */
20596  #define R_GLCDC_BG_HSIZE_HP_Msk     (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff)                             */
20597  #define R_GLCDC_BG_HSIZE_HW_Pos     (0UL)         /*!< HW (Bit 0)                                            */
20598  #define R_GLCDC_BG_HSIZE_HW_Msk     (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
20599 /* ==========================================================  BGC  ========================================================== */
20600  #define R_GLCDC_BG_BGC_R_Pos        (16UL)        /*!< R (Bit 16)                                            */
20601  #define R_GLCDC_BG_BGC_R_Msk        (0xff0000UL)  /*!< R (Bitfield-Mask: 0xff)                               */
20602  #define R_GLCDC_BG_BGC_G_Pos        (8UL)         /*!< G (Bit 8)                                             */
20603  #define R_GLCDC_BG_BGC_G_Msk        (0xff00UL)    /*!< G (Bitfield-Mask: 0xff)                               */
20604  #define R_GLCDC_BG_BGC_B_Pos        (0UL)         /*!< B (Bit 0)                                             */
20605  #define R_GLCDC_BG_BGC_B_Msk        (0xffUL)      /*!< B (Bitfield-Mask: 0xff)                               */
20606 /* ==========================================================  MON  ========================================================== */
20607  #define R_GLCDC_BG_MON_SWRST_Pos    (16UL)        /*!< SWRST (Bit 16)                                        */
20608  #define R_GLCDC_BG_MON_SWRST_Msk    (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
20609  #define R_GLCDC_BG_MON_VEN_Pos      (8UL)         /*!< VEN (Bit 8)                                           */
20610  #define R_GLCDC_BG_MON_VEN_Msk      (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
20611  #define R_GLCDC_BG_MON_EN_Pos       (0UL)         /*!< EN (Bit 0)                                            */
20612  #define R_GLCDC_BG_MON_EN_Msk       (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
20613 
20614 /* =========================================================================================================================== */
20615 /* ================                                            GR                                             ================ */
20616 /* =========================================================================================================================== */
20617 
20618 /* ==========================================================  VEN  ========================================================== */
20619  #define R_GLCDC_GR_VEN_PVEN_Pos         (0UL)          /*!< PVEN (Bit 0)                                          */
20620  #define R_GLCDC_GR_VEN_PVEN_Msk         (0x1UL)        /*!< PVEN (Bitfield-Mask: 0x01)                            */
20621 /* =========================================================  FLMRD  ========================================================= */
20622  #define R_GLCDC_GR_FLMRD_RENB_Pos       (0UL)          /*!< RENB (Bit 0)                                          */
20623  #define R_GLCDC_GR_FLMRD_RENB_Msk       (0x1UL)        /*!< RENB (Bitfield-Mask: 0x01)                            */
20624 /* =========================================================  FLM1  ========================================================== */
20625  #define R_GLCDC_GR_FLM1_BSTMD_Pos       (0UL)          /*!< BSTMD (Bit 0)                                         */
20626  #define R_GLCDC_GR_FLM1_BSTMD_Msk       (0x3UL)        /*!< BSTMD (Bitfield-Mask: 0x03)                           */
20627 /* =========================================================  FLM2  ========================================================== */
20628  #define R_GLCDC_GR_FLM2_BASE_Pos        (0UL)          /*!< BASE (Bit 0)                                          */
20629  #define R_GLCDC_GR_FLM2_BASE_Msk        (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff)                      */
20630 /* =========================================================  FLM3  ========================================================== */
20631  #define R_GLCDC_GR_FLM3_LNOFF_Pos       (16UL)         /*!< LNOFF (Bit 16)                                        */
20632  #define R_GLCDC_GR_FLM3_LNOFF_Msk       (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff)                         */
20633 /* =========================================================  FLM5  ========================================================== */
20634  #define R_GLCDC_GR_FLM5_LNNUM_Pos       (16UL)         /*!< LNNUM (Bit 16)                                        */
20635  #define R_GLCDC_GR_FLM5_LNNUM_Msk       (0x7ff0000UL)  /*!< LNNUM (Bitfield-Mask: 0x7ff)                          */
20636  #define R_GLCDC_GR_FLM5_DATANUM_Pos     (0UL)          /*!< DATANUM (Bit 0)                                       */
20637  #define R_GLCDC_GR_FLM5_DATANUM_Msk     (0xffffUL)     /*!< DATANUM (Bitfield-Mask: 0xffff)                       */
20638 /* =========================================================  FLM6  ========================================================== */
20639  #define R_GLCDC_GR_FLM6_FORMAT_Pos      (28UL)         /*!< FORMAT (Bit 28)                                       */
20640  #define R_GLCDC_GR_FLM6_FORMAT_Msk      (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07)                          */
20641 /* ==========================================================  AB1  ========================================================== */
20642  #define R_GLCDC_GR_AB1_ARCON_Pos        (12UL)         /*!< ARCON (Bit 12)                                        */
20643  #define R_GLCDC_GR_AB1_ARCON_Msk        (0x1000UL)     /*!< ARCON (Bitfield-Mask: 0x01)                           */
20644  #define R_GLCDC_GR_AB1_ARCDISPON_Pos    (8UL)          /*!< ARCDISPON (Bit 8)                                     */
20645  #define R_GLCDC_GR_AB1_ARCDISPON_Msk    (0x100UL)      /*!< ARCDISPON (Bitfield-Mask: 0x01)                       */
20646  #define R_GLCDC_GR_AB1_GRCDISPON_Pos    (4UL)          /*!< GRCDISPON (Bit 4)                                     */
20647  #define R_GLCDC_GR_AB1_GRCDISPON_Msk    (0x10UL)       /*!< GRCDISPON (Bitfield-Mask: 0x01)                       */
20648  #define R_GLCDC_GR_AB1_DISPSEL_Pos      (0UL)          /*!< DISPSEL (Bit 0)                                       */
20649  #define R_GLCDC_GR_AB1_DISPSEL_Msk      (0x3UL)        /*!< DISPSEL (Bitfield-Mask: 0x03)                         */
20650 /* ==========================================================  AB2  ========================================================== */
20651  #define R_GLCDC_GR_AB2_GRCVS_Pos        (16UL)         /*!< GRCVS (Bit 16)                                        */
20652  #define R_GLCDC_GR_AB2_GRCVS_Msk        (0x7ff0000UL)  /*!< GRCVS (Bitfield-Mask: 0x7ff)                          */
20653  #define R_GLCDC_GR_AB2_GRCVW_Pos        (0UL)          /*!< GRCVW (Bit 0)                                         */
20654  #define R_GLCDC_GR_AB2_GRCVW_Msk        (0x7ffUL)      /*!< GRCVW (Bitfield-Mask: 0x7ff)                          */
20655 /* ==========================================================  AB3  ========================================================== */
20656  #define R_GLCDC_GR_AB3_GRCHS_Pos        (16UL)         /*!< GRCHS (Bit 16)                                        */
20657  #define R_GLCDC_GR_AB3_GRCHS_Msk        (0x7ff0000UL)  /*!< GRCHS (Bitfield-Mask: 0x7ff)                          */
20658  #define R_GLCDC_GR_AB3_GRCHW_Pos        (0UL)          /*!< GRCHW (Bit 0)                                         */
20659  #define R_GLCDC_GR_AB3_GRCHW_Msk        (0x7ffUL)      /*!< GRCHW (Bitfield-Mask: 0x7ff)                          */
20660 /* ==========================================================  AB4  ========================================================== */
20661  #define R_GLCDC_GR_AB4_ARCVS_Pos        (16UL)         /*!< ARCVS (Bit 16)                                        */
20662  #define R_GLCDC_GR_AB4_ARCVS_Msk        (0x7ff0000UL)  /*!< ARCVS (Bitfield-Mask: 0x7ff)                          */
20663  #define R_GLCDC_GR_AB4_ARCVW_Pos        (0UL)          /*!< ARCVW (Bit 0)                                         */
20664  #define R_GLCDC_GR_AB4_ARCVW_Msk        (0x7ffUL)      /*!< ARCVW (Bitfield-Mask: 0x7ff)                          */
20665 /* ==========================================================  AB5  ========================================================== */
20666  #define R_GLCDC_GR_AB5_ARCHS_Pos        (16UL)         /*!< ARCHS (Bit 16)                                        */
20667  #define R_GLCDC_GR_AB5_ARCHS_Msk        (0x7ff0000UL)  /*!< ARCHS (Bitfield-Mask: 0x7ff)                          */
20668  #define R_GLCDC_GR_AB5_ARCHW_Pos        (0UL)          /*!< ARCHW (Bit 0)                                         */
20669  #define R_GLCDC_GR_AB5_ARCHW_Msk        (0x7ffUL)      /*!< ARCHW (Bitfield-Mask: 0x7ff)                          */
20670 /* ==========================================================  AB6  ========================================================== */
20671  #define R_GLCDC_GR_AB6_ARCCOEF_Pos      (16UL)         /*!< ARCCOEF (Bit 16)                                      */
20672  #define R_GLCDC_GR_AB6_ARCCOEF_Msk      (0x1ff0000UL)  /*!< ARCCOEF (Bitfield-Mask: 0x1ff)                        */
20673  #define R_GLCDC_GR_AB6_ARCRATE_Pos      (0UL)          /*!< ARCRATE (Bit 0)                                       */
20674  #define R_GLCDC_GR_AB6_ARCRATE_Msk      (0xffUL)       /*!< ARCRATE (Bitfield-Mask: 0xff)                         */
20675 /* ==========================================================  AB7  ========================================================== */
20676  #define R_GLCDC_GR_AB7_ARCDEF_Pos       (16UL)         /*!< ARCDEF (Bit 16)                                       */
20677  #define R_GLCDC_GR_AB7_ARCDEF_Msk       (0xff0000UL)   /*!< ARCDEF (Bitfield-Mask: 0xff)                          */
20678  #define R_GLCDC_GR_AB7_CKON_Pos         (0UL)          /*!< CKON (Bit 0)                                          */
20679  #define R_GLCDC_GR_AB7_CKON_Msk         (0x1UL)        /*!< CKON (Bitfield-Mask: 0x01)                            */
20680 /* ==========================================================  AB8  ========================================================== */
20681  #define R_GLCDC_GR_AB8_CKKG_Pos         (16UL)         /*!< CKKG (Bit 16)                                         */
20682  #define R_GLCDC_GR_AB8_CKKG_Msk         (0xff0000UL)   /*!< CKKG (Bitfield-Mask: 0xff)                            */
20683  #define R_GLCDC_GR_AB8_CKKB_Pos         (8UL)          /*!< CKKB (Bit 8)                                          */
20684  #define R_GLCDC_GR_AB8_CKKB_Msk         (0xff00UL)     /*!< CKKB (Bitfield-Mask: 0xff)                            */
20685  #define R_GLCDC_GR_AB8_CKKR_Pos         (0UL)          /*!< CKKR (Bit 0)                                          */
20686  #define R_GLCDC_GR_AB8_CKKR_Msk         (0xffUL)       /*!< CKKR (Bitfield-Mask: 0xff)                            */
20687 /* ==========================================================  AB9  ========================================================== */
20688  #define R_GLCDC_GR_AB9_CKA_Pos          (24UL)         /*!< CKA (Bit 24)                                          */
20689  #define R_GLCDC_GR_AB9_CKA_Msk          (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff)                             */
20690  #define R_GLCDC_GR_AB9_CKG_Pos          (16UL)         /*!< CKG (Bit 16)                                          */
20691  #define R_GLCDC_GR_AB9_CKG_Msk          (0xff0000UL)   /*!< CKG (Bitfield-Mask: 0xff)                             */
20692  #define R_GLCDC_GR_AB9_CKB_Pos          (8UL)          /*!< CKB (Bit 8)                                           */
20693  #define R_GLCDC_GR_AB9_CKB_Msk          (0xff00UL)     /*!< CKB (Bitfield-Mask: 0xff)                             */
20694  #define R_GLCDC_GR_AB9_CKR_Pos          (0UL)          /*!< CKR (Bit 0)                                           */
20695  #define R_GLCDC_GR_AB9_CKR_Msk          (0xffUL)       /*!< CKR (Bitfield-Mask: 0xff)                             */
20696 /* =========================================================  BASE  ========================================================== */
20697  #define R_GLCDC_GR_BASE_G_Pos           (16UL)         /*!< G (Bit 16)                                            */
20698  #define R_GLCDC_GR_BASE_G_Msk           (0xff0000UL)   /*!< G (Bitfield-Mask: 0xff)                               */
20699  #define R_GLCDC_GR_BASE_B_Pos           (8UL)          /*!< B (Bit 8)                                             */
20700  #define R_GLCDC_GR_BASE_B_Msk           (0xff00UL)     /*!< B (Bitfield-Mask: 0xff)                               */
20701  #define R_GLCDC_GR_BASE_R_Pos           (0UL)          /*!< R (Bit 0)                                             */
20702  #define R_GLCDC_GR_BASE_R_Msk           (0xffUL)       /*!< R (Bitfield-Mask: 0xff)                               */
20703 /* ========================================================  CLUTINT  ======================================================== */
20704  #define R_GLCDC_GR_CLUTINT_SEL_Pos      (16UL)         /*!< SEL (Bit 16)                                          */
20705  #define R_GLCDC_GR_CLUTINT_SEL_Msk      (0x10000UL)    /*!< SEL (Bitfield-Mask: 0x01)                             */
20706  #define R_GLCDC_GR_CLUTINT_LINE_Pos     (0UL)          /*!< LINE (Bit 0)                                          */
20707  #define R_GLCDC_GR_CLUTINT_LINE_Msk     (0x7ffUL)      /*!< LINE (Bitfield-Mask: 0x7ff)                           */
20708 /* ==========================================================  MON  ========================================================== */
20709  #define R_GLCDC_GR_MON_UNDFLST_Pos      (16UL)         /*!< UNDFLST (Bit 16)                                      */
20710  #define R_GLCDC_GR_MON_UNDFLST_Msk      (0x10000UL)    /*!< UNDFLST (Bitfield-Mask: 0x01)                         */
20711  #define R_GLCDC_GR_MON_ARCST_Pos        (0UL)          /*!< ARCST (Bit 0)                                         */
20712  #define R_GLCDC_GR_MON_ARCST_Msk        (0x1UL)        /*!< ARCST (Bitfield-Mask: 0x01)                           */
20713 
20714 /* =========================================================================================================================== */
20715 /* ================                                            GAM                                            ================ */
20716 /* =========================================================================================================================== */
20717 
20718 /* =========================================================  LATCH  ========================================================= */
20719  #define R_GLCDC_GAM_LATCH_VEN_Pos       (0UL)     /*!< VEN (Bit 0)                                           */
20720  #define R_GLCDC_GAM_LATCH_VEN_Msk       (0x1UL)   /*!< VEN (Bitfield-Mask: 0x01)                             */
20721 /* ========================================================  GAM_SW  ========================================================= */
20722  #define R_GLCDC_GAM_GAM_SW_GAMON_Pos    (0UL)     /*!< GAMON (Bit 0)                                         */
20723  #define R_GLCDC_GAM_GAM_SW_GAMON_Msk    (0x1UL)   /*!< GAMON (Bitfield-Mask: 0x01)                           */
20724 /* ==========================================================  LUT  ========================================================== */
20725  #define R_GLCDC_GAM_LUT___Pos           (0UL)     /*!< _ (Bit 0)                                             */
20726  #define R_GLCDC_GAM_LUT___Msk           (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff)                              */
20727 /* =========================================================  AREA  ========================================================== */
20728  #define R_GLCDC_GAM_AREA___Pos          (0UL)     /*!< _ (Bit 0)                                             */
20729  #define R_GLCDC_GAM_AREA___Msk          (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff)                              */
20730 
20731 /* =========================================================================================================================== */
20732 /* ================                                            OUT                                            ================ */
20733 /* =========================================================================================================================== */
20734 
20735 /* ========================================================  VLATCH  ========================================================= */
20736  #define R_GLCDC_OUT_VLATCH_VEN_Pos            (0UL)          /*!< VEN (Bit 0)                                           */
20737  #define R_GLCDC_OUT_VLATCH_VEN_Msk            (0x1UL)        /*!< VEN (Bitfield-Mask: 0x01)                             */
20738 /* ==========================================================  SET  ========================================================== */
20739  #define R_GLCDC_OUT_SET_ENDIANON_Pos          (28UL)         /*!< ENDIANON (Bit 28)                                     */
20740  #define R_GLCDC_OUT_SET_ENDIANON_Msk          (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01)                        */
20741  #define R_GLCDC_OUT_SET_SWAPON_Pos            (24UL)         /*!< SWAPON (Bit 24)                                       */
20742  #define R_GLCDC_OUT_SET_SWAPON_Msk            (0x1000000UL)  /*!< SWAPON (Bitfield-Mask: 0x01)                          */
20743  #define R_GLCDC_OUT_SET_FORMAT_Pos            (12UL)         /*!< FORMAT (Bit 12)                                       */
20744  #define R_GLCDC_OUT_SET_FORMAT_Msk            (0x3000UL)     /*!< FORMAT (Bitfield-Mask: 0x03)                          */
20745  #define R_GLCDC_OUT_SET_FRQSEL_Pos            (8UL)          /*!< FRQSEL (Bit 8)                                        */
20746  #define R_GLCDC_OUT_SET_FRQSEL_Msk            (0x300UL)      /*!< FRQSEL (Bitfield-Mask: 0x03)                          */
20747  #define R_GLCDC_OUT_SET_DIRSEL_Pos            (4UL)          /*!< DIRSEL (Bit 4)                                        */
20748  #define R_GLCDC_OUT_SET_DIRSEL_Msk            (0x10UL)       /*!< DIRSEL (Bitfield-Mask: 0x01)                          */
20749  #define R_GLCDC_OUT_SET_PHASE_Pos             (0UL)          /*!< PHASE (Bit 0)                                         */
20750  #define R_GLCDC_OUT_SET_PHASE_Msk             (0x3UL)        /*!< PHASE (Bitfield-Mask: 0x03)                           */
20751 /* ========================================================  BRIGHT1  ======================================================== */
20752  #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos          (0UL)          /*!< BRTG (Bit 0)                                          */
20753  #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk          (0x3ffUL)      /*!< BRTG (Bitfield-Mask: 0x3ff)                           */
20754 /* ========================================================  BRIGHT2  ======================================================== */
20755  #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos          (16UL)         /*!< BRTB (Bit 16)                                         */
20756  #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk          (0x3ff0000UL)  /*!< BRTB (Bitfield-Mask: 0x3ff)                           */
20757  #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos          (0UL)          /*!< BRTR (Bit 0)                                          */
20758  #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk          (0x3ffUL)      /*!< BRTR (Bitfield-Mask: 0x3ff)                           */
20759 /* =======================================================  CONTRAST  ======================================================== */
20760  #define R_GLCDC_OUT_CONTRAST_CONTG_Pos        (16UL)         /*!< CONTG (Bit 16)                                        */
20761  #define R_GLCDC_OUT_CONTRAST_CONTG_Msk        (0xff0000UL)   /*!< CONTG (Bitfield-Mask: 0xff)                           */
20762  #define R_GLCDC_OUT_CONTRAST_CONTB_Pos        (8UL)          /*!< CONTB (Bit 8)                                         */
20763  #define R_GLCDC_OUT_CONTRAST_CONTB_Msk        (0xff00UL)     /*!< CONTB (Bitfield-Mask: 0xff)                           */
20764  #define R_GLCDC_OUT_CONTRAST_CONTR_Pos        (0UL)          /*!< CONTR (Bit 0)                                         */
20765  #define R_GLCDC_OUT_CONTRAST_CONTR_Msk        (0xffUL)       /*!< CONTR (Bitfield-Mask: 0xff)                           */
20766 /* =========================================================  PDTHA  ========================================================= */
20767  #define R_GLCDC_OUT_PDTHA_SEL_Pos             (20UL)         /*!< SEL (Bit 20)                                          */
20768  #define R_GLCDC_OUT_PDTHA_SEL_Msk             (0x300000UL)   /*!< SEL (Bitfield-Mask: 0x03)                             */
20769  #define R_GLCDC_OUT_PDTHA_FORM_Pos            (16UL)         /*!< FORM (Bit 16)                                         */
20770  #define R_GLCDC_OUT_PDTHA_FORM_Msk            (0x30000UL)    /*!< FORM (Bitfield-Mask: 0x03)                            */
20771  #define R_GLCDC_OUT_PDTHA_PA_Pos              (12UL)         /*!< PA (Bit 12)                                           */
20772  #define R_GLCDC_OUT_PDTHA_PA_Msk              (0x3000UL)     /*!< PA (Bitfield-Mask: 0x03)                              */
20773  #define R_GLCDC_OUT_PDTHA_PB_Pos              (8UL)          /*!< PB (Bit 8)                                            */
20774  #define R_GLCDC_OUT_PDTHA_PB_Msk              (0x300UL)      /*!< PB (Bitfield-Mask: 0x03)                              */
20775  #define R_GLCDC_OUT_PDTHA_PC_Pos              (4UL)          /*!< PC (Bit 4)                                            */
20776  #define R_GLCDC_OUT_PDTHA_PC_Msk              (0x30UL)       /*!< PC (Bitfield-Mask: 0x03)                              */
20777  #define R_GLCDC_OUT_PDTHA_PD_Pos              (0UL)          /*!< PD (Bit 0)                                            */
20778  #define R_GLCDC_OUT_PDTHA_PD_Msk              (0x3UL)        /*!< PD (Bitfield-Mask: 0x03)                              */
20779 /* =======================================================  CLKPHASE  ======================================================== */
20780  #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos     (12UL)         /*!< FRONTGAM (Bit 12)                                     */
20781  #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk     (0x1000UL)     /*!< FRONTGAM (Bitfield-Mask: 0x01)                        */
20782  #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos      (8UL)          /*!< LCDEDGE (Bit 8)                                       */
20783  #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk      (0x100UL)      /*!< LCDEDGE (Bitfield-Mask: 0x01)                         */
20784  #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos    (6UL)          /*!< TCON0EDGE (Bit 6)                                     */
20785  #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk    (0x40UL)       /*!< TCON0EDGE (Bitfield-Mask: 0x01)                       */
20786  #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos    (5UL)          /*!< TCON1EDGE (Bit 5)                                     */
20787  #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk    (0x20UL)       /*!< TCON1EDGE (Bitfield-Mask: 0x01)                       */
20788  #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos    (4UL)          /*!< TCON2EDGE (Bit 4)                                     */
20789  #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk    (0x10UL)       /*!< TCON2EDGE (Bitfield-Mask: 0x01)                       */
20790  #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos    (3UL)          /*!< TCON3EDGE (Bit 3)                                     */
20791  #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk    (0x8UL)        /*!< TCON3EDGE (Bitfield-Mask: 0x01)                       */
20792 
20793 /* =========================================================================================================================== */
20794 /* ================                                           TCON                                            ================ */
20795 /* =========================================================================================================================== */
20796 
20797 /* ==========================================================  TIM  ========================================================== */
20798  #define R_GLCDC_TCON_TIM_HALF_Pos       (16UL)        /*!< HALF (Bit 16)                                         */
20799  #define R_GLCDC_TCON_TIM_HALF_Msk       (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff)                           */
20800  #define R_GLCDC_TCON_TIM_OFFSET_Pos     (0UL)         /*!< OFFSET (Bit 0)                                        */
20801  #define R_GLCDC_TCON_TIM_OFFSET_Msk     (0x7ffUL)     /*!< OFFSET (Bitfield-Mask: 0x7ff)                         */
20802 /* =========================================================  STVA1  ========================================================= */
20803  #define R_GLCDC_TCON_STVA1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
20804  #define R_GLCDC_TCON_STVA1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
20805  #define R_GLCDC_TCON_STVA1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
20806  #define R_GLCDC_TCON_STVA1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
20807 /* =========================================================  STVB1  ========================================================= */
20808  #define R_GLCDC_TCON_STVB1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
20809  #define R_GLCDC_TCON_STVB1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
20810  #define R_GLCDC_TCON_STVB1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
20811  #define R_GLCDC_TCON_STVB1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
20812 /* =========================================================  STVA2  ========================================================= */
20813  #define R_GLCDC_TCON_STVA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
20814  #define R_GLCDC_TCON_STVA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
20815  #define R_GLCDC_TCON_STVA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
20816  #define R_GLCDC_TCON_STVA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
20817 /* =========================================================  STVB2  ========================================================= */
20818  #define R_GLCDC_TCON_STVB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
20819  #define R_GLCDC_TCON_STVB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
20820  #define R_GLCDC_TCON_STVB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
20821  #define R_GLCDC_TCON_STVB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
20822 /* =========================================================  STHA1  ========================================================= */
20823  #define R_GLCDC_TCON_STHA1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
20824  #define R_GLCDC_TCON_STHA1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
20825  #define R_GLCDC_TCON_STHA1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
20826  #define R_GLCDC_TCON_STHA1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
20827 /* =========================================================  STHB1  ========================================================= */
20828  #define R_GLCDC_TCON_STHB1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
20829  #define R_GLCDC_TCON_STHB1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
20830  #define R_GLCDC_TCON_STHB1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
20831  #define R_GLCDC_TCON_STHB1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
20832 /* =========================================================  STHA2  ========================================================= */
20833  #define R_GLCDC_TCON_STHA2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
20834  #define R_GLCDC_TCON_STHA2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
20835  #define R_GLCDC_TCON_STHA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
20836  #define R_GLCDC_TCON_STHA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
20837  #define R_GLCDC_TCON_STHA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
20838  #define R_GLCDC_TCON_STHA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
20839 /* =========================================================  STHB2  ========================================================= */
20840  #define R_GLCDC_TCON_STHB2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
20841  #define R_GLCDC_TCON_STHB2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
20842  #define R_GLCDC_TCON_STHB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
20843  #define R_GLCDC_TCON_STHB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
20844  #define R_GLCDC_TCON_STHB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
20845  #define R_GLCDC_TCON_STHB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
20846 /* ==========================================================  DE  =========================================================== */
20847  #define R_GLCDC_TCON_DE_INV_Pos         (0UL)         /*!< INV (Bit 0)                                           */
20848  #define R_GLCDC_TCON_DE_INV_Msk         (0x1UL)       /*!< INV (Bitfield-Mask: 0x01)                             */
20849 
20850 /* =========================================================================================================================== */
20851 /* ================                                          SYSCNT                                           ================ */
20852 /* =========================================================================================================================== */
20853 
20854 /* ========================================================  DTCTEN  ========================================================= */
20855  #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos     (2UL)          /*!< L2UNDFDTC (Bit 2)                                     */
20856  #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk     (0x4UL)        /*!< L2UNDFDTC (Bitfield-Mask: 0x01)                       */
20857  #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos     (1UL)          /*!< L1UNDFDTC (Bit 1)                                     */
20858  #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk     (0x2UL)        /*!< L1UNDFDTC (Bitfield-Mask: 0x01)                       */
20859  #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos       (0UL)          /*!< VPOSDTC (Bit 0)                                       */
20860  #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk       (0x1UL)        /*!< VPOSDTC (Bitfield-Mask: 0x01)                         */
20861 /* =========================================================  INTEN  ========================================================= */
20862  #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos    (2UL)          /*!< L2UNDFINTEN (Bit 2)                                   */
20863  #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk    (0x4UL)        /*!< L2UNDFINTEN (Bitfield-Mask: 0x01)                     */
20864  #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos    (1UL)          /*!< L1UNDFINTEN (Bit 1)                                   */
20865  #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk    (0x2UL)        /*!< L1UNDFINTEN (Bitfield-Mask: 0x01)                     */
20866  #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos      (0UL)          /*!< VPOSINTEN (Bit 0)                                     */
20867  #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk      (0x1UL)        /*!< VPOSINTEN (Bitfield-Mask: 0x01)                       */
20868 /* =========================================================  STCLR  ========================================================= */
20869  #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos      (2UL)          /*!< L2UNDFCLR (Bit 2)                                     */
20870  #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk      (0x4UL)        /*!< L2UNDFCLR (Bitfield-Mask: 0x01)                       */
20871  #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos      (1UL)          /*!< L1UNDFCLR (Bit 1)                                     */
20872  #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk      (0x2UL)        /*!< L1UNDFCLR (Bitfield-Mask: 0x01)                       */
20873  #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos        (0UL)          /*!< VPOSCLR (Bit 0)                                       */
20874  #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk        (0x1UL)        /*!< VPOSCLR (Bitfield-Mask: 0x01)                         */
20875 /* =========================================================  STMON  ========================================================= */
20876  #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos         (2UL)          /*!< L2UNDF (Bit 2)                                        */
20877  #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk         (0x4UL)        /*!< L2UNDF (Bitfield-Mask: 0x01)                          */
20878  #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos         (1UL)          /*!< L1UNDF (Bit 1)                                        */
20879  #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk         (0x2UL)        /*!< L1UNDF (Bitfield-Mask: 0x01)                          */
20880  #define R_GLCDC_SYSCNT_STMON_VPOS_Pos           (0UL)          /*!< VPOS (Bit 0)                                          */
20881  #define R_GLCDC_SYSCNT_STMON_VPOS_Msk           (0x1UL)        /*!< VPOS (Bitfield-Mask: 0x01)                            */
20882 /* =======================================================  PANEL_CLK  ======================================================= */
20883  #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos        (16UL)         /*!< VER (Bit 16)                                          */
20884  #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk        (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff)                           */
20885  #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos     (12UL)         /*!< PIXSEL (Bit 12)                                       */
20886  #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk     (0x1000UL)     /*!< PIXSEL (Bitfield-Mask: 0x01)                          */
20887  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos     (8UL)          /*!< CLKSEL (Bit 8)                                        */
20888  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk     (0x100UL)      /*!< CLKSEL (Bitfield-Mask: 0x01)                          */
20889  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos      (6UL)          /*!< CLKEN (Bit 6)                                         */
20890  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk      (0x40UL)       /*!< CLKEN (Bitfield-Mask: 0x01)                           */
20891  #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos       (0UL)          /*!< DCDR (Bit 0)                                          */
20892  #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk       (0x3fUL)       /*!< DCDR (Bitfield-Mask: 0x3f)                            */
20893 
20894 /* =========================================================================================================================== */
20895 /* ================                                          GTDLYR                                           ================ */
20896 /* =========================================================================================================================== */
20897 
20898 /* ===========================================================  A  =========================================================== */
20899  #define R_GPT_ODC_GTDLYR_A_DLY_Pos    (0UL)    /*!< DLY (Bit 0)                                           */
20900  #define R_GPT_ODC_GTDLYR_A_DLY_Msk    (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f)                             */
20901 /* ===========================================================  B  =========================================================== */
20902  #define R_GPT_ODC_GTDLYR_B_DLY_Pos    (0UL)    /*!< DLY (Bit 0)                                           */
20903  #define R_GPT_ODC_GTDLYR_B_DLY_Msk    (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f)                             */
20904 
20905 /* =========================================================================================================================== */
20906 /* ================                                            SAR                                            ================ */
20907 /* =========================================================================================================================== */
20908 
20909 /* ===========================================================  L  =========================================================== */
20910  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
20911  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
20912 /* ===========================================================  U  =========================================================== */
20913  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
20914  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
20915  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
20916  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
20917  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
20918  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
20919 
20920 /* =========================================================================================================================== */
20921 /* ================                                          REGION                                           ================ */
20922 /* =========================================================================================================================== */
20923 
20924 /* ==========================================================  AC  =========================================================== */
20925  #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
20926  #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
20927  #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
20928  #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
20929  #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
20930  #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
20931 /* ===========================================================  S  =========================================================== */
20932  #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
20933  #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
20934 /* ===========================================================  E  =========================================================== */
20935  #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
20936  #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */
20937 
20938 /* =========================================================================================================================== */
20939 /* ================                                           MMPU                                            ================ */
20940 /* =========================================================================================================================== */
20941 
20942 /* ==========================================================  CTL  ========================================================== */
20943  #define R_MPU_MMPU_MMPU_CTL_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
20944  #define R_MPU_MMPU_MMPU_CTL_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20945  #define R_MPU_MMPU_MMPU_CTL_OAD_Pos       (1UL)      /*!< OAD (Bit 1)                                           */
20946  #define R_MPU_MMPU_MMPU_CTL_OAD_Msk       (0x2UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
20947  #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos    (0UL)      /*!< ENABLE (Bit 0)                                        */
20948  #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk    (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
20949 /* ==========================================================  PT  =========================================================== */
20950  #define R_MPU_MMPU_MMPU_PT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
20951  #define R_MPU_MMPU_MMPU_PT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20952  #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
20953  #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20954 
20955 /* =========================================================================================================================== */
20956 /* ================                                           SMPU                                            ================ */
20957 /* =========================================================================================================================== */
20958 
20959 /* ===========================================================  R  =========================================================== */
20960  #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos    (15UL)     /*!< WPSRAMHS (Bit 15)                                     */
20961  #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk    (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01)                        */
20962  #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos    (14UL)     /*!< RPSRAMHS (Bit 14)                                     */
20963  #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk    (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01)                        */
20964  #define R_MPU_SMPU_SMPU_R_WPFLI_Pos       (13UL)     /*!< WPFLI (Bit 13)                                        */
20965  #define R_MPU_SMPU_SMPU_R_WPFLI_Msk       (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01)                           */
20966  #define R_MPU_SMPU_SMPU_R_RPFLI_Pos       (12UL)     /*!< RPFLI (Bit 12)                                        */
20967  #define R_MPU_SMPU_SMPU_R_RPFLI_Msk       (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01)                           */
20968  #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos      (7UL)      /*!< WPGRPC (Bit 7)                                        */
20969  #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk      (0x80UL)   /*!< WPGRPC (Bitfield-Mask: 0x01)                          */
20970  #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos      (6UL)      /*!< RPGRPC (Bit 6)                                        */
20971  #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk      (0x40UL)   /*!< RPGRPC (Bitfield-Mask: 0x01)                          */
20972  #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos      (5UL)      /*!< WPGRPB (Bit 5)                                        */
20973  #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk      (0x20UL)   /*!< WPGRPB (Bitfield-Mask: 0x01)                          */
20974  #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos      (4UL)      /*!< RPGRPB (Bit 4)                                        */
20975  #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk      (0x10UL)   /*!< RPGRPB (Bitfield-Mask: 0x01)                          */
20976  #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos      (3UL)      /*!< WPGRPA (Bit 3)                                        */
20977  #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk      (0x8UL)    /*!< WPGRPA (Bitfield-Mask: 0x01)                          */
20978  #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos      (2UL)      /*!< RPGRPA (Bit 2)                                        */
20979  #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk      (0x4UL)    /*!< RPGRPA (Bitfield-Mask: 0x01)                          */
20980 
20981 /* =========================================================================================================================== */
20982 /* ================                                            SP                                             ================ */
20983 /* =========================================================================================================================== */
20984 
20985 /* ==========================================================  OAD  ========================================================== */
20986  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
20987  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20988  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
20989  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
20990 /* ==========================================================  CTL  ========================================================== */
20991  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
20992  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
20993  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
20994  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
20995 /* ==========================================================  PT  =========================================================== */
20996  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
20997  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20998  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
20999  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
21000 /* ==========================================================  SA  =========================================================== */
21001  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
21002  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
21003 /* ==========================================================  EA  =========================================================== */
21004  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
21005  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
21006 
21007 /* =========================================================================================================================== */
21008 /* ================                                            PIN                                            ================ */
21009 /* =========================================================================================================================== */
21010 
21011 /* =======================================================  PmnPFS_BY  ======================================================= */
21012  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
21013  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
21014  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
21015  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
21016  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
21017  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
21018  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
21019  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
21020  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
21021  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
21022  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
21023  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
21024 /* =======================================================  PmnPFS_HA  ======================================================= */
21025  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
21026  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
21027  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
21028  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
21029  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
21030  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
21031  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
21032  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
21033  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
21034  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
21035  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
21036  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
21037  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
21038  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
21039  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
21040  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
21041  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
21042  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
21043  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
21044  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
21045 /* ========================================================  PmnPFS  ========================================================= */
21046  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
21047  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
21048  #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
21049  #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
21050  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
21051  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
21052  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
21053  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
21054  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
21055  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
21056  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
21057  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
21058  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
21059  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
21060  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
21061  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
21062  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
21063  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
21064  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
21065  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
21066  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
21067  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
21068  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
21069  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
21070 
21071 /* =========================================================================================================================== */
21072 /* ================                                           PORT                                            ================ */
21073 /* =========================================================================================================================== */
21074 
21075 /* =========================================================================================================================== */
21076 /* ================                                           VLSEL                                           ================ */
21077 /* =========================================================================================================================== */
21078 
21079 /* ========================================================  VL1SEL  ========================================================= */
21080  #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
21081  #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
21082 
21083 /* =========================================================================================================================== */
21084 /* ================                                           PMSAR                                           ================ */
21085 /* =========================================================================================================================== */
21086 
21087 /* =========================================================  PMSAR  ========================================================= */
21088 
21089 /* =========================================================================================================================== */
21090 /* ================                                           RTCCR                                           ================ */
21091 /* =========================================================================================================================== */
21092 
21093 /* =========================================================  RTCCR  ========================================================= */
21094  #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
21095  #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
21096  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
21097  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
21098  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
21099  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
21100  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
21101  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
21102 
21103 /* =========================================================================================================================== */
21104 /* ================                                            CP                                             ================ */
21105 /* =========================================================================================================================== */
21106 
21107 /* =========================================================  RSEC  ========================================================== */
21108  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
21109  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
21110  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
21111  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
21112 /* =========================================================  BCNT0  ========================================================= */
21113  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
21114  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
21115 /* =========================================================  RMIN  ========================================================== */
21116  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
21117  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
21118  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
21119  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
21120 /* =========================================================  BCNT1  ========================================================= */
21121  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
21122  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
21123 /* ==========================================================  RHR  ========================================================== */
21124  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
21125  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
21126  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
21127  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
21128  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
21129  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
21130 /* =========================================================  BCNT2  ========================================================= */
21131  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
21132  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
21133 /* =========================================================  RDAY  ========================================================== */
21134  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
21135  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
21136  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
21137  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
21138 /* =========================================================  BCNT3  ========================================================= */
21139  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
21140  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
21141 /* =========================================================  RMON  ========================================================== */
21142  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
21143  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
21144  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
21145  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
21146 
21147 /* =========================================================================================================================== */
21148 /* ================                                          PIPE_TR                                          ================ */
21149 /* =========================================================================================================================== */
21150 
21151 /* ===========================================================  E  =========================================================== */
21152  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
21153  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
21154  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
21155  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
21156 /* ===========================================================  N  =========================================================== */
21157  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
21158  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
21159 
21160 /* =========================================================================================================================== */
21161 /* ================                                          PIPE_TR                                          ================ */
21162 /* =========================================================================================================================== */
21163 
21164 /* ===========================================================  E  =========================================================== */
21165  #define R_USB_HS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
21166  #define R_USB_HS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
21167  #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
21168  #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
21169 /* ===========================================================  N  =========================================================== */
21170  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
21171  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
21172 
21173 /* =========================================================================================================================== */
21174 /* ================                                           CTRL                                            ================ */
21175 /* =========================================================================================================================== */
21176 
21177 /* =========================================================  AGTCR  ========================================================= */
21178  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
21179  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
21180  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
21181  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
21182  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
21183  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
21184  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
21185  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
21186  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
21187  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
21188  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
21189  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
21190  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
21191  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
21192 /* ========================================================  AGTMR1  ========================================================= */
21193  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
21194  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
21195  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
21196  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
21197  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
21198  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
21199 /* ========================================================  AGTMR2  ========================================================= */
21200  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
21201  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
21202  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
21203  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
21204 /* =====================================================  AGTIOSEL_ALT  ====================================================== */
21205  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
21206  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
21207  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
21208  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
21209 /* ========================================================  AGTIOC  ========================================================= */
21210  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
21211  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
21212  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
21213  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
21214  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
21215  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
21216  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
21217  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
21218 /* ========================================================  AGTISR  ========================================================= */
21219  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
21220  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
21221 /* ========================================================  AGTCMSR  ======================================================== */
21222  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
21223  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
21224  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
21225  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
21226  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
21227  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
21228  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
21229  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
21230  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
21231  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
21232  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
21233  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
21234 /* =======================================================  AGTIOSEL  ======================================================== */
21235  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
21236  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
21237  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
21238  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
21239 
21240 /* =========================================================================================================================== */
21241 /* ================                                           AGT16                                           ================ */
21242 /* =========================================================================================================================== */
21243 
21244 /* ==========================================================  AGT  ========================================================== */
21245  #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
21246  #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
21247 /* ========================================================  AGTCMA  ========================================================= */
21248  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
21249  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
21250 /* ========================================================  AGTCMB  ========================================================= */
21251  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
21252  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
21253 
21254 /* =========================================================================================================================== */
21255 /* ================                                           AGT32                                           ================ */
21256 /* =========================================================================================================================== */
21257 
21258 /* ==========================================================  AGT  ========================================================== */
21259  #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
21260  #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
21261 /* ========================================================  AGTCMA  ========================================================= */
21262  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
21263  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
21264 /* ========================================================  AGTCMB  ========================================================= */
21265  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
21266  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
21267 
21268 /** @} */ /* End of group PosMask_clusters */
21269 
21270 /* =========================================================================================================================== */
21271 /* ================                                Pos/Mask Peripheral Section                                ================ */
21272 /* =========================================================================================================================== */
21273 
21274 /** @addtogroup PosMask_peripherals
21275  * @{
21276  */
21277 
21278 /* =========================================================================================================================== */
21279 /* ================                                         R_ACMPHS0                                         ================ */
21280 /* =========================================================================================================================== */
21281 
21282 /* ========================================================  CMPCTL  ========================================================= */
21283  #define R_ACMPHS0_CMPCTL_HCMPON_Pos     (7UL)    /*!< HCMPON (Bit 7)                                        */
21284  #define R_ACMPHS0_CMPCTL_HCMPON_Msk     (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01)                          */
21285  #define R_ACMPHS0_CMPCTL_CDFS_Pos       (5UL)    /*!< CDFS (Bit 5)                                          */
21286  #define R_ACMPHS0_CMPCTL_CDFS_Msk       (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03)                            */
21287  #define R_ACMPHS0_CMPCTL_CEG_Pos        (3UL)    /*!< CEG (Bit 3)                                           */
21288  #define R_ACMPHS0_CMPCTL_CEG_Msk        (0x18UL) /*!< CEG (Bitfield-Mask: 0x03)                             */
21289  #define R_ACMPHS0_CMPCTL_CSTEN_Pos      (2UL)    /*!< CSTEN (Bit 2)                                         */
21290  #define R_ACMPHS0_CMPCTL_CSTEN_Msk      (0x4UL)  /*!< CSTEN (Bitfield-Mask: 0x01)                           */
21291  #define R_ACMPHS0_CMPCTL_COE_Pos        (1UL)    /*!< COE (Bit 1)                                           */
21292  #define R_ACMPHS0_CMPCTL_COE_Msk        (0x2UL)  /*!< COE (Bitfield-Mask: 0x01)                             */
21293  #define R_ACMPHS0_CMPCTL_CINV_Pos       (0UL)    /*!< CINV (Bit 0)                                          */
21294  #define R_ACMPHS0_CMPCTL_CINV_Msk       (0x1UL)  /*!< CINV (Bitfield-Mask: 0x01)                            */
21295 /* ========================================================  CMPSEL0  ======================================================== */
21296  #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos    (0UL)    /*!< CMPSEL (Bit 0)                                        */
21297  #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk    (0xfUL)  /*!< CMPSEL (Bitfield-Mask: 0x0f)                          */
21298 /* ========================================================  CMPSEL1  ======================================================== */
21299  #define R_ACMPHS0_CMPSEL1_CRVS_Pos      (0UL)    /*!< CRVS (Bit 0)                                          */
21300  #define R_ACMPHS0_CMPSEL1_CRVS_Msk      (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f)                            */
21301 /* ========================================================  CMPMON  ========================================================= */
21302  #define R_ACMPHS0_CMPMON_CMPMON_Pos     (0UL)    /*!< CMPMON (Bit 0)                                        */
21303  #define R_ACMPHS0_CMPMON_CMPMON_Msk     (0x1UL)  /*!< CMPMON (Bitfield-Mask: 0x01)                          */
21304 /* =========================================================  CPIOC  ========================================================= */
21305  #define R_ACMPHS0_CPIOC_VREFEN_Pos      (7UL)    /*!< VREFEN (Bit 7)                                        */
21306  #define R_ACMPHS0_CPIOC_VREFEN_Msk      (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01)                          */
21307  #define R_ACMPHS0_CPIOC_CPOE_Pos        (0UL)    /*!< CPOE (Bit 0)                                          */
21308  #define R_ACMPHS0_CPIOC_CPOE_Msk        (0x1UL)  /*!< CPOE (Bitfield-Mask: 0x01)                            */
21309 
21310 /* =========================================================================================================================== */
21311 /* ================                                          R_ADC0                                           ================ */
21312 /* =========================================================================================================================== */
21313 
21314 /* =========================================================  ADCSR  ========================================================= */
21315  #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
21316  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
21317  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
21318  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
21319  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
21320  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
21321  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
21322  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
21323  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
21324  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
21325  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
21326  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
21327  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
21328  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
21329  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
21330  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
21331  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
21332  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
21333 /* ========================================================  ADANSA  ========================================================= */
21334  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
21335  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
21336 /* =========================================================  ADADS  ========================================================= */
21337  #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
21338  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
21339 /* =========================================================  ADADC  ========================================================= */
21340  #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
21341  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
21342  #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
21343  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
21344 /* =========================================================  ADCER  ========================================================= */
21345  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
21346  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
21347  #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
21348  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
21349  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
21350  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
21351  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
21352  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
21353  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
21354  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
21355  #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
21356  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
21357  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
21358  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
21359  #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
21360  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
21361 /* ========================================================  ADSTRGR  ======================================================== */
21362  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
21363  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
21364  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
21365  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
21366 /* ========================================================  ADEXICR  ======================================================== */
21367  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
21368  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
21369  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
21370  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
21371  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
21372  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
21373  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
21374  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
21375  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
21376  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
21377  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
21378  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
21379  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
21380  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
21381  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
21382  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
21383 /* ========================================================  ADANSB  ========================================================= */
21384  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
21385  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
21386 /* ========================================================  ADDBLDR  ======================================================== */
21387  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
21388  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
21389 /* ========================================================  ADTSDR  ========================================================= */
21390  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
21391  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
21392 /* ========================================================  ADOCDR  ========================================================= */
21393  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
21394  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
21395 /* ======================================================  ADRD_RIGHT  ======================================================= */
21396  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
21397  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
21398  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
21399  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
21400 /* =======================================================  ADRD_LEFT  ======================================================= */
21401  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
21402  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
21403  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
21404  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
21405 /* =========================================================  ADDR  ========================================================== */
21406  #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
21407  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
21408 /* ========================================================  ADSHCR  ========================================================= */
21409  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
21410  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
21411  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
21412  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
21413  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
21414  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
21415  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
21416  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
21417 /* ========================================================  ADDISCR  ======================================================== */
21418  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
21419  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
21420  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
21421  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
21422 /* ========================================================  ADSHMSR  ======================================================== */
21423  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
21424  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
21425 /* ========================================================  ADACSR  ========================================================= */
21426  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
21427  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
21428 /* ========================================================  ADGSPCR  ======================================================== */
21429  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
21430  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
21431  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
21432  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
21433  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
21434  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
21435  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
21436  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
21437 /* =========================================================  ADICR  ========================================================= */
21438  #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
21439  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
21440 /* =======================================================  ADDBLDRA  ======================================================== */
21441  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
21442  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
21443 /* =======================================================  ADDBLDRB  ======================================================== */
21444  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
21445  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
21446 /* ======================================================  ADHVREFCNT  ======================================================= */
21447  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
21448  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
21449  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
21450  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
21451  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
21452  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
21453 /* =======================================================  ADWINMON  ======================================================== */
21454  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
21455  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
21456  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
21457  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
21458  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
21459  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
21460 /* ========================================================  ADCMPCR  ======================================================== */
21461  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
21462  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
21463  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
21464  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
21465  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
21466  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
21467  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
21468  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
21469  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
21470  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
21471  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
21472  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
21473 /* ======================================================  ADCMPANSER  ======================================================= */
21474  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
21475  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
21476  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
21477  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
21478 /* =======================================================  ADCMPLER  ======================================================== */
21479  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
21480  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
21481  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
21482  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
21483 /* =======================================================  ADCMPANSR  ======================================================= */
21484  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
21485  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
21486 /* ========================================================  ADCMPLR  ======================================================== */
21487  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
21488  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
21489 /* =======================================================  ADCMPDR0  ======================================================== */
21490  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
21491  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
21492 /* =======================================================  ADCMPDR1  ======================================================== */
21493  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
21494  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
21495 /* ========================================================  ADCMPSR  ======================================================== */
21496  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
21497  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
21498 /* =======================================================  ADCMPSER  ======================================================== */
21499  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
21500  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
21501  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
21502  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
21503 /* =======================================================  ADCMPBNSR  ======================================================= */
21504  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
21505  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
21506  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
21507  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
21508 /* =======================================================  ADWINLLB  ======================================================== */
21509  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
21510  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
21511 /* =======================================================  ADWINULB  ======================================================== */
21512  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
21513  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
21514 /* =======================================================  ADCMPBSR  ======================================================== */
21515  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
21516  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
21517 /* ========================================================  ADSSTRL  ======================================================== */
21518  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
21519  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21520 /* ========================================================  ADSSTRT  ======================================================== */
21521  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
21522  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21523 /* ========================================================  ADSSTRO  ======================================================== */
21524  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
21525  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21526 /* ========================================================  ADSSTR  ========================================================= */
21527  #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
21528  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21529 /* ========================================================  ADPGACR  ======================================================== */
21530  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
21531  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
21532  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
21533  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
21534  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
21535  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
21536  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
21537  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
21538  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
21539  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
21540  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
21541  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
21542  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
21543  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
21544  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
21545  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
21546  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
21547  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
21548  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
21549  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
21550  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
21551  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
21552  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
21553  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
21554  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
21555  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
21556  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
21557  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
21558  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
21559  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
21560  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
21561  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
21562 /* =========================================================  ADRD  ========================================================== */
21563  #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
21564  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
21565 /* =========================================================  ADRST  ========================================================= */
21566  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
21567  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
21568 /* ======================================================  VREFAMPCNT  ======================================================= */
21569  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
21570  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
21571  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
21572  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
21573  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
21574  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
21575  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
21576  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
21577  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
21578  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
21579 /* =======================================================  ADCALEXE  ======================================================== */
21580  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
21581  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
21582  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
21583  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
21584 /* ========================================================  ADANIM  ========================================================= */
21585  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
21586  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
21587 /* =======================================================  ADPGAGS0  ======================================================== */
21588  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
21589  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
21590  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
21591  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
21592  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
21593  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
21594  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
21595  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
21596 /* =======================================================  ADPGADCR0  ======================================================= */
21597  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
21598  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
21599  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
21600  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
21601  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
21602  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
21603  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
21604  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
21605  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
21606  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
21607  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
21608  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
21609  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
21610  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
21611  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
21612  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
21613 /* =========================================================  ADREF  ========================================================= */
21614  #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
21615  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
21616  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
21617  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
21618 /* ========================================================  ADEXREF  ======================================================== */
21619  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
21620  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
21621 /* =======================================================  ADAMPOFF  ======================================================== */
21622  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
21623  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
21624 /* ========================================================  ADTSTPR  ======================================================== */
21625  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
21626  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
21627  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
21628  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
21629 /* =======================================================  ADDDACER  ======================================================== */
21630  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
21631  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
21632  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
21633  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
21634  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
21635  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
21636 /* =======================================================  ADEXTSTR  ======================================================== */
21637  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
21638  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
21639  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
21640  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
21641  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
21642  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
21643  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
21644  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
21645  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
21646  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
21647  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
21648  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
21649 /* ========================================================  ADTSTRA  ======================================================== */
21650  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
21651  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
21652  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
21653  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
21654  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
21655  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
21656  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
21657  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
21658  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
21659  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
21660  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
21661  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
21662 /* ========================================================  ADTSTRB  ======================================================== */
21663  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
21664  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
21665 /* ========================================================  ADTSTRC  ======================================================== */
21666  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
21667  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
21668  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
21669  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
21670 /* ========================================================  ADTSTRD  ======================================================== */
21671  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
21672  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
21673 /* =======================================================  ADSWTSTR0  ======================================================= */
21674  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
21675  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
21676  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
21677  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
21678  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
21679  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
21680  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
21681  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
21682  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
21683  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
21684  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
21685  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
21686 /* =======================================================  ADSWTSTR1  ======================================================= */
21687  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
21688  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
21689  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
21690  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
21691  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
21692  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
21693  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
21694  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
21695  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
21696  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
21697  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
21698  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
21699 /* =======================================================  ADSWTSTR2  ======================================================= */
21700  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
21701  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
21702  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
21703  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
21704  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
21705  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
21706  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
21707  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
21708  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
21709  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
21710  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
21711  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
21712  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
21713  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
21714  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
21715  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
21716  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
21717  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
21718  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
21719  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
21720 /* ========================================================  ADSWCR  ========================================================= */
21721  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
21722  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
21723  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
21724  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
21725 /* ========================================================  ADGSCS  ========================================================= */
21726  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
21727  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
21728  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
21729  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
21730 /* =========================================================  ADSER  ========================================================= */
21731  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
21732  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
21733 /* ========================================================  ADBUF0  ========================================================= */
21734  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21735  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21736 /* ========================================================  ADBUF1  ========================================================= */
21737  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21738  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21739 /* ========================================================  ADBUF2  ========================================================= */
21740  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21741  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21742 /* ========================================================  ADBUF3  ========================================================= */
21743  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21744  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21745 /* ========================================================  ADBUF4  ========================================================= */
21746  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21747  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21748 /* ========================================================  ADBUF5  ========================================================= */
21749  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21750  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21751 /* ========================================================  ADBUF6  ========================================================= */
21752  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21753  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21754 /* ========================================================  ADBUF7  ========================================================= */
21755  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21756  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21757 /* ========================================================  ADBUF8  ========================================================= */
21758  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21759  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21760 /* ========================================================  ADBUF9  ========================================================= */
21761  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21762  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21763 /* ========================================================  ADBUF10  ======================================================== */
21764  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21765  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21766 /* ========================================================  ADBUF11  ======================================================== */
21767  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21768  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21769 /* ========================================================  ADBUF12  ======================================================== */
21770  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21771  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21772 /* ========================================================  ADBUF13  ======================================================== */
21773  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21774  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21775 /* ========================================================  ADBUF14  ======================================================== */
21776  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21777  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21778 /* ========================================================  ADBUF15  ======================================================== */
21779  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21780  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21781 /* ========================================================  ADBUFEN  ======================================================== */
21782  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
21783  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
21784 /* =======================================================  ADBUFPTR  ======================================================== */
21785  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
21786  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
21787  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
21788  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
21789 /* =======================================================  ADPGADBS0  ======================================================= */
21790  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
21791  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
21792 /* =======================================================  ADPGADBS1  ======================================================= */
21793  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
21794  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
21795 /* =======================================================  ADREFMON  ======================================================== */
21796  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
21797  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
21798  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
21799  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
21800 
21801 /* =========================================================================================================================== */
21802 /* ================                                           R_BUS                                           ================ */
21803 /* =========================================================================================================================== */
21804 
21805 /* ========================================================  CSRECEN  ======================================================== */
21806  #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
21807  #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
21808  #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
21809  #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
21810 /* ========================================================  BUSMABT  ======================================================== */
21811  #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
21812  #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
21813 /* =======================================================  BUSDIVBYP  ======================================================= */
21814  #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
21815  #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
21816  #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
21817  #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
21818  #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
21819  #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
21820 
21821 /* =========================================================================================================================== */
21822 /* ================                                           R_CAC                                           ================ */
21823 /* =========================================================================================================================== */
21824 
21825 /* =========================================================  CACR0  ========================================================= */
21826  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
21827  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
21828 /* =========================================================  CACR1  ========================================================= */
21829  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
21830  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
21831  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
21832  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
21833  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
21834  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
21835  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
21836  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
21837 /* =========================================================  CACR2  ========================================================= */
21838  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
21839  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
21840  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
21841  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
21842  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
21843  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
21844  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
21845  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
21846 /* =========================================================  CAICR  ========================================================= */
21847  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
21848  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
21849  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
21850  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
21851  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
21852  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
21853  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
21854  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
21855  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
21856  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
21857  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
21858  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
21859 /* =========================================================  CASTR  ========================================================= */
21860  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
21861  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
21862  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
21863  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
21864  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
21865  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
21866 /* ========================================================  CAULVR  ========================================================= */
21867  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
21868  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
21869 /* ========================================================  CALLVR  ========================================================= */
21870  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
21871  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
21872 /* ========================================================  CACNTBR  ======================================================== */
21873  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
21874  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
21875 
21876 /* =========================================================================================================================== */
21877 /* ================                                          R_CAN0                                           ================ */
21878 /* =========================================================================================================================== */
21879 
21880 /* ==========================================================  MKR  ========================================================== */
21881  #define R_CAN0_MKR_SID_Pos              (18UL)         /*!< SID (Bit 18)                                          */
21882  #define R_CAN0_MKR_SID_Msk              (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
21883  #define R_CAN0_MKR_EID_Pos              (0UL)          /*!< EID (Bit 0)                                           */
21884  #define R_CAN0_MKR_EID_Msk              (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
21885 /* =========================================================  FIDCR  ========================================================= */
21886  #define R_CAN0_FIDCR_IDE_Pos            (31UL)         /*!< IDE (Bit 31)                                          */
21887  #define R_CAN0_FIDCR_IDE_Msk            (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
21888  #define R_CAN0_FIDCR_RTR_Pos            (30UL)         /*!< RTR (Bit 30)                                          */
21889  #define R_CAN0_FIDCR_RTR_Msk            (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
21890  #define R_CAN0_FIDCR_SID_Pos            (18UL)         /*!< SID (Bit 18)                                          */
21891  #define R_CAN0_FIDCR_SID_Msk            (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
21892  #define R_CAN0_FIDCR_EID_Pos            (0UL)          /*!< EID (Bit 0)                                           */
21893  #define R_CAN0_FIDCR_EID_Msk            (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
21894 /* ========================================================  MKIVLR  ========================================================= */
21895  #define R_CAN0_MKIVLR_MB31_Pos          (31UL)         /*!< MB31 (Bit 31)                                         */
21896  #define R_CAN0_MKIVLR_MB31_Msk          (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
21897  #define R_CAN0_MKIVLR_MB30_Pos          (30UL)         /*!< MB30 (Bit 30)                                         */
21898  #define R_CAN0_MKIVLR_MB30_Msk          (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
21899  #define R_CAN0_MKIVLR_MB29_Pos          (29UL)         /*!< MB29 (Bit 29)                                         */
21900  #define R_CAN0_MKIVLR_MB29_Msk          (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
21901  #define R_CAN0_MKIVLR_MB28_Pos          (28UL)         /*!< MB28 (Bit 28)                                         */
21902  #define R_CAN0_MKIVLR_MB28_Msk          (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
21903  #define R_CAN0_MKIVLR_MB27_Pos          (27UL)         /*!< MB27 (Bit 27)                                         */
21904  #define R_CAN0_MKIVLR_MB27_Msk          (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
21905  #define R_CAN0_MKIVLR_MB26_Pos          (26UL)         /*!< MB26 (Bit 26)                                         */
21906  #define R_CAN0_MKIVLR_MB26_Msk          (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
21907  #define R_CAN0_MKIVLR_MB25_Pos          (25UL)         /*!< MB25 (Bit 25)                                         */
21908  #define R_CAN0_MKIVLR_MB25_Msk          (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
21909  #define R_CAN0_MKIVLR_MB24_Pos          (24UL)         /*!< MB24 (Bit 24)                                         */
21910  #define R_CAN0_MKIVLR_MB24_Msk          (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
21911  #define R_CAN0_MKIVLR_MB23_Pos          (23UL)         /*!< MB23 (Bit 23)                                         */
21912  #define R_CAN0_MKIVLR_MB23_Msk          (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
21913  #define R_CAN0_MKIVLR_MB22_Pos          (22UL)         /*!< MB22 (Bit 22)                                         */
21914  #define R_CAN0_MKIVLR_MB22_Msk          (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
21915  #define R_CAN0_MKIVLR_MB21_Pos          (21UL)         /*!< MB21 (Bit 21)                                         */
21916  #define R_CAN0_MKIVLR_MB21_Msk          (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
21917  #define R_CAN0_MKIVLR_MB20_Pos          (20UL)         /*!< MB20 (Bit 20)                                         */
21918  #define R_CAN0_MKIVLR_MB20_Msk          (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
21919  #define R_CAN0_MKIVLR_MB19_Pos          (19UL)         /*!< MB19 (Bit 19)                                         */
21920  #define R_CAN0_MKIVLR_MB19_Msk          (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
21921  #define R_CAN0_MKIVLR_MB18_Pos          (18UL)         /*!< MB18 (Bit 18)                                         */
21922  #define R_CAN0_MKIVLR_MB18_Msk          (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
21923  #define R_CAN0_MKIVLR_MB17_Pos          (17UL)         /*!< MB17 (Bit 17)                                         */
21924  #define R_CAN0_MKIVLR_MB17_Msk          (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
21925  #define R_CAN0_MKIVLR_MB16_Pos          (16UL)         /*!< MB16 (Bit 16)                                         */
21926  #define R_CAN0_MKIVLR_MB16_Msk          (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
21927  #define R_CAN0_MKIVLR_MB15_Pos          (15UL)         /*!< MB15 (Bit 15)                                         */
21928  #define R_CAN0_MKIVLR_MB15_Msk          (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
21929  #define R_CAN0_MKIVLR_MB14_Pos          (14UL)         /*!< MB14 (Bit 14)                                         */
21930  #define R_CAN0_MKIVLR_MB14_Msk          (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
21931  #define R_CAN0_MKIVLR_MB13_Pos          (13UL)         /*!< MB13 (Bit 13)                                         */
21932  #define R_CAN0_MKIVLR_MB13_Msk          (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
21933  #define R_CAN0_MKIVLR_MB12_Pos          (12UL)         /*!< MB12 (Bit 12)                                         */
21934  #define R_CAN0_MKIVLR_MB12_Msk          (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
21935  #define R_CAN0_MKIVLR_MB11_Pos          (11UL)         /*!< MB11 (Bit 11)                                         */
21936  #define R_CAN0_MKIVLR_MB11_Msk          (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
21937  #define R_CAN0_MKIVLR_MB10_Pos          (10UL)         /*!< MB10 (Bit 10)                                         */
21938  #define R_CAN0_MKIVLR_MB10_Msk          (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
21939  #define R_CAN0_MKIVLR_MB9_Pos           (9UL)          /*!< MB9 (Bit 9)                                           */
21940  #define R_CAN0_MKIVLR_MB9_Msk           (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
21941  #define R_CAN0_MKIVLR_MB8_Pos           (8UL)          /*!< MB8 (Bit 8)                                           */
21942  #define R_CAN0_MKIVLR_MB8_Msk           (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
21943  #define R_CAN0_MKIVLR_MB7_Pos           (7UL)          /*!< MB7 (Bit 7)                                           */
21944  #define R_CAN0_MKIVLR_MB7_Msk           (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
21945  #define R_CAN0_MKIVLR_MB6_Pos           (6UL)          /*!< MB6 (Bit 6)                                           */
21946  #define R_CAN0_MKIVLR_MB6_Msk           (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
21947  #define R_CAN0_MKIVLR_MB5_Pos           (5UL)          /*!< MB5 (Bit 5)                                           */
21948  #define R_CAN0_MKIVLR_MB5_Msk           (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
21949  #define R_CAN0_MKIVLR_MB4_Pos           (4UL)          /*!< MB4 (Bit 4)                                           */
21950  #define R_CAN0_MKIVLR_MB4_Msk           (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
21951  #define R_CAN0_MKIVLR_MB3_Pos           (3UL)          /*!< MB3 (Bit 3)                                           */
21952  #define R_CAN0_MKIVLR_MB3_Msk           (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
21953  #define R_CAN0_MKIVLR_MB2_Pos           (2UL)          /*!< MB2 (Bit 2)                                           */
21954  #define R_CAN0_MKIVLR_MB2_Msk           (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
21955  #define R_CAN0_MKIVLR_MB1_Pos           (1UL)          /*!< MB1 (Bit 1)                                           */
21956  #define R_CAN0_MKIVLR_MB1_Msk           (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
21957  #define R_CAN0_MKIVLR_MB0_Pos           (0UL)          /*!< MB0 (Bit 0)                                           */
21958  #define R_CAN0_MKIVLR_MB0_Msk           (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
21959 /* =========================================================  MIER  ========================================================== */
21960  #define R_CAN0_MIER_MB31_Pos            (31UL)         /*!< MB31 (Bit 31)                                         */
21961  #define R_CAN0_MIER_MB31_Msk            (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
21962  #define R_CAN0_MIER_MB30_Pos            (30UL)         /*!< MB30 (Bit 30)                                         */
21963  #define R_CAN0_MIER_MB30_Msk            (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
21964  #define R_CAN0_MIER_MB29_Pos            (29UL)         /*!< MB29 (Bit 29)                                         */
21965  #define R_CAN0_MIER_MB29_Msk            (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
21966  #define R_CAN0_MIER_MB28_Pos            (28UL)         /*!< MB28 (Bit 28)                                         */
21967  #define R_CAN0_MIER_MB28_Msk            (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
21968  #define R_CAN0_MIER_MB27_Pos            (27UL)         /*!< MB27 (Bit 27)                                         */
21969  #define R_CAN0_MIER_MB27_Msk            (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
21970  #define R_CAN0_MIER_MB26_Pos            (26UL)         /*!< MB26 (Bit 26)                                         */
21971  #define R_CAN0_MIER_MB26_Msk            (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
21972  #define R_CAN0_MIER_MB25_Pos            (25UL)         /*!< MB25 (Bit 25)                                         */
21973  #define R_CAN0_MIER_MB25_Msk            (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
21974  #define R_CAN0_MIER_MB24_Pos            (24UL)         /*!< MB24 (Bit 24)                                         */
21975  #define R_CAN0_MIER_MB24_Msk            (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
21976  #define R_CAN0_MIER_MB23_Pos            (23UL)         /*!< MB23 (Bit 23)                                         */
21977  #define R_CAN0_MIER_MB23_Msk            (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
21978  #define R_CAN0_MIER_MB22_Pos            (22UL)         /*!< MB22 (Bit 22)                                         */
21979  #define R_CAN0_MIER_MB22_Msk            (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
21980  #define R_CAN0_MIER_MB21_Pos            (21UL)         /*!< MB21 (Bit 21)                                         */
21981  #define R_CAN0_MIER_MB21_Msk            (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
21982  #define R_CAN0_MIER_MB20_Pos            (20UL)         /*!< MB20 (Bit 20)                                         */
21983  #define R_CAN0_MIER_MB20_Msk            (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
21984  #define R_CAN0_MIER_MB19_Pos            (19UL)         /*!< MB19 (Bit 19)                                         */
21985  #define R_CAN0_MIER_MB19_Msk            (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
21986  #define R_CAN0_MIER_MB18_Pos            (18UL)         /*!< MB18 (Bit 18)                                         */
21987  #define R_CAN0_MIER_MB18_Msk            (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
21988  #define R_CAN0_MIER_MB17_Pos            (17UL)         /*!< MB17 (Bit 17)                                         */
21989  #define R_CAN0_MIER_MB17_Msk            (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
21990  #define R_CAN0_MIER_MB16_Pos            (16UL)         /*!< MB16 (Bit 16)                                         */
21991  #define R_CAN0_MIER_MB16_Msk            (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
21992  #define R_CAN0_MIER_MB15_Pos            (15UL)         /*!< MB15 (Bit 15)                                         */
21993  #define R_CAN0_MIER_MB15_Msk            (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
21994  #define R_CAN0_MIER_MB14_Pos            (14UL)         /*!< MB14 (Bit 14)                                         */
21995  #define R_CAN0_MIER_MB14_Msk            (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
21996  #define R_CAN0_MIER_MB13_Pos            (13UL)         /*!< MB13 (Bit 13)                                         */
21997  #define R_CAN0_MIER_MB13_Msk            (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
21998  #define R_CAN0_MIER_MB12_Pos            (12UL)         /*!< MB12 (Bit 12)                                         */
21999  #define R_CAN0_MIER_MB12_Msk            (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
22000  #define R_CAN0_MIER_MB11_Pos            (11UL)         /*!< MB11 (Bit 11)                                         */
22001  #define R_CAN0_MIER_MB11_Msk            (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
22002  #define R_CAN0_MIER_MB10_Pos            (10UL)         /*!< MB10 (Bit 10)                                         */
22003  #define R_CAN0_MIER_MB10_Msk            (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
22004  #define R_CAN0_MIER_MB9_Pos             (9UL)          /*!< MB9 (Bit 9)                                           */
22005  #define R_CAN0_MIER_MB9_Msk             (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
22006  #define R_CAN0_MIER_MB8_Pos             (8UL)          /*!< MB8 (Bit 8)                                           */
22007  #define R_CAN0_MIER_MB8_Msk             (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
22008  #define R_CAN0_MIER_MB7_Pos             (7UL)          /*!< MB7 (Bit 7)                                           */
22009  #define R_CAN0_MIER_MB7_Msk             (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
22010  #define R_CAN0_MIER_MB6_Pos             (6UL)          /*!< MB6 (Bit 6)                                           */
22011  #define R_CAN0_MIER_MB6_Msk             (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
22012  #define R_CAN0_MIER_MB5_Pos             (5UL)          /*!< MB5 (Bit 5)                                           */
22013  #define R_CAN0_MIER_MB5_Msk             (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
22014  #define R_CAN0_MIER_MB4_Pos             (4UL)          /*!< MB4 (Bit 4)                                           */
22015  #define R_CAN0_MIER_MB4_Msk             (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
22016  #define R_CAN0_MIER_MB3_Pos             (3UL)          /*!< MB3 (Bit 3)                                           */
22017  #define R_CAN0_MIER_MB3_Msk             (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
22018  #define R_CAN0_MIER_MB2_Pos             (2UL)          /*!< MB2 (Bit 2)                                           */
22019  #define R_CAN0_MIER_MB2_Msk             (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
22020  #define R_CAN0_MIER_MB1_Pos             (1UL)          /*!< MB1 (Bit 1)                                           */
22021  #define R_CAN0_MIER_MB1_Msk             (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
22022  #define R_CAN0_MIER_MB0_Pos             (0UL)          /*!< MB0 (Bit 0)                                           */
22023  #define R_CAN0_MIER_MB0_Msk             (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
22024 /* =======================================================  MIER_FIFO  ======================================================= */
22025  #define R_CAN0_MIER_FIFO_MB29_Pos       (29UL)         /*!< MB29 (Bit 29)                                         */
22026  #define R_CAN0_MIER_FIFO_MB29_Msk       (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
22027  #define R_CAN0_MIER_FIFO_MB28_Pos       (28UL)         /*!< MB28 (Bit 28)                                         */
22028  #define R_CAN0_MIER_FIFO_MB28_Msk       (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
22029  #define R_CAN0_MIER_FIFO_MB25_Pos       (25UL)         /*!< MB25 (Bit 25)                                         */
22030  #define R_CAN0_MIER_FIFO_MB25_Msk       (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
22031  #define R_CAN0_MIER_FIFO_MB24_Pos       (24UL)         /*!< MB24 (Bit 24)                                         */
22032  #define R_CAN0_MIER_FIFO_MB24_Msk       (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
22033  #define R_CAN0_MIER_FIFO_MB23_Pos       (23UL)         /*!< MB23 (Bit 23)                                         */
22034  #define R_CAN0_MIER_FIFO_MB23_Msk       (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
22035  #define R_CAN0_MIER_FIFO_MB22_Pos       (22UL)         /*!< MB22 (Bit 22)                                         */
22036  #define R_CAN0_MIER_FIFO_MB22_Msk       (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
22037  #define R_CAN0_MIER_FIFO_MB21_Pos       (21UL)         /*!< MB21 (Bit 21)                                         */
22038  #define R_CAN0_MIER_FIFO_MB21_Msk       (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
22039  #define R_CAN0_MIER_FIFO_MB20_Pos       (20UL)         /*!< MB20 (Bit 20)                                         */
22040  #define R_CAN0_MIER_FIFO_MB20_Msk       (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
22041  #define R_CAN0_MIER_FIFO_MB19_Pos       (19UL)         /*!< MB19 (Bit 19)                                         */
22042  #define R_CAN0_MIER_FIFO_MB19_Msk       (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
22043  #define R_CAN0_MIER_FIFO_MB18_Pos       (18UL)         /*!< MB18 (Bit 18)                                         */
22044  #define R_CAN0_MIER_FIFO_MB18_Msk       (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
22045  #define R_CAN0_MIER_FIFO_MB17_Pos       (17UL)         /*!< MB17 (Bit 17)                                         */
22046  #define R_CAN0_MIER_FIFO_MB17_Msk       (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
22047  #define R_CAN0_MIER_FIFO_MB16_Pos       (16UL)         /*!< MB16 (Bit 16)                                         */
22048  #define R_CAN0_MIER_FIFO_MB16_Msk       (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
22049  #define R_CAN0_MIER_FIFO_MB15_Pos       (15UL)         /*!< MB15 (Bit 15)                                         */
22050  #define R_CAN0_MIER_FIFO_MB15_Msk       (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
22051  #define R_CAN0_MIER_FIFO_MB14_Pos       (14UL)         /*!< MB14 (Bit 14)                                         */
22052  #define R_CAN0_MIER_FIFO_MB14_Msk       (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
22053  #define R_CAN0_MIER_FIFO_MB13_Pos       (13UL)         /*!< MB13 (Bit 13)                                         */
22054  #define R_CAN0_MIER_FIFO_MB13_Msk       (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
22055  #define R_CAN0_MIER_FIFO_MB12_Pos       (12UL)         /*!< MB12 (Bit 12)                                         */
22056  #define R_CAN0_MIER_FIFO_MB12_Msk       (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
22057  #define R_CAN0_MIER_FIFO_MB11_Pos       (11UL)         /*!< MB11 (Bit 11)                                         */
22058  #define R_CAN0_MIER_FIFO_MB11_Msk       (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
22059  #define R_CAN0_MIER_FIFO_MB10_Pos       (10UL)         /*!< MB10 (Bit 10)                                         */
22060  #define R_CAN0_MIER_FIFO_MB10_Msk       (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
22061  #define R_CAN0_MIER_FIFO_MB9_Pos        (9UL)          /*!< MB9 (Bit 9)                                           */
22062  #define R_CAN0_MIER_FIFO_MB9_Msk        (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
22063  #define R_CAN0_MIER_FIFO_MB8_Pos        (8UL)          /*!< MB8 (Bit 8)                                           */
22064  #define R_CAN0_MIER_FIFO_MB8_Msk        (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
22065  #define R_CAN0_MIER_FIFO_MB7_Pos        (7UL)          /*!< MB7 (Bit 7)                                           */
22066  #define R_CAN0_MIER_FIFO_MB7_Msk        (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
22067  #define R_CAN0_MIER_FIFO_MB6_Pos        (6UL)          /*!< MB6 (Bit 6)                                           */
22068  #define R_CAN0_MIER_FIFO_MB6_Msk        (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
22069  #define R_CAN0_MIER_FIFO_MB5_Pos        (5UL)          /*!< MB5 (Bit 5)                                           */
22070  #define R_CAN0_MIER_FIFO_MB5_Msk        (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
22071  #define R_CAN0_MIER_FIFO_MB4_Pos        (4UL)          /*!< MB4 (Bit 4)                                           */
22072  #define R_CAN0_MIER_FIFO_MB4_Msk        (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
22073  #define R_CAN0_MIER_FIFO_MB3_Pos        (3UL)          /*!< MB3 (Bit 3)                                           */
22074  #define R_CAN0_MIER_FIFO_MB3_Msk        (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
22075  #define R_CAN0_MIER_FIFO_MB2_Pos        (2UL)          /*!< MB2 (Bit 2)                                           */
22076  #define R_CAN0_MIER_FIFO_MB2_Msk        (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
22077  #define R_CAN0_MIER_FIFO_MB1_Pos        (1UL)          /*!< MB1 (Bit 1)                                           */
22078  #define R_CAN0_MIER_FIFO_MB1_Msk        (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
22079  #define R_CAN0_MIER_FIFO_MB0_Pos        (0UL)          /*!< MB0 (Bit 0)                                           */
22080  #define R_CAN0_MIER_FIFO_MB0_Msk        (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
22081 /* ========================================================  MCTL_TX  ======================================================== */
22082  #define R_CAN0_MCTL_TX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
22083  #define R_CAN0_MCTL_TX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
22084  #define R_CAN0_MCTL_TX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
22085  #define R_CAN0_MCTL_TX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
22086  #define R_CAN0_MCTL_TX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
22087  #define R_CAN0_MCTL_TX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
22088  #define R_CAN0_MCTL_TX_TRMABT_Pos       (2UL)          /*!< TRMABT (Bit 2)                                        */
22089  #define R_CAN0_MCTL_TX_TRMABT_Msk       (0x4UL)        /*!< TRMABT (Bitfield-Mask: 0x01)                          */
22090  #define R_CAN0_MCTL_TX_TRMACTIVE_Pos    (1UL)          /*!< TRMACTIVE (Bit 1)                                     */
22091  #define R_CAN0_MCTL_TX_TRMACTIVE_Msk    (0x2UL)        /*!< TRMACTIVE (Bitfield-Mask: 0x01)                       */
22092  #define R_CAN0_MCTL_TX_SENTDATA_Pos     (0UL)          /*!< SENTDATA (Bit 0)                                      */
22093  #define R_CAN0_MCTL_TX_SENTDATA_Msk     (0x1UL)        /*!< SENTDATA (Bitfield-Mask: 0x01)                        */
22094 /* ========================================================  MCTL_RX  ======================================================== */
22095  #define R_CAN0_MCTL_RX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
22096  #define R_CAN0_MCTL_RX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
22097  #define R_CAN0_MCTL_RX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
22098  #define R_CAN0_MCTL_RX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
22099  #define R_CAN0_MCTL_RX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
22100  #define R_CAN0_MCTL_RX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
22101  #define R_CAN0_MCTL_RX_MSGLOST_Pos      (2UL)          /*!< MSGLOST (Bit 2)                                       */
22102  #define R_CAN0_MCTL_RX_MSGLOST_Msk      (0x4UL)        /*!< MSGLOST (Bitfield-Mask: 0x01)                         */
22103  #define R_CAN0_MCTL_RX_INVALDATA_Pos    (1UL)          /*!< INVALDATA (Bit 1)                                     */
22104  #define R_CAN0_MCTL_RX_INVALDATA_Msk    (0x2UL)        /*!< INVALDATA (Bitfield-Mask: 0x01)                       */
22105  #define R_CAN0_MCTL_RX_NEWDATA_Pos      (0UL)          /*!< NEWDATA (Bit 0)                                       */
22106  #define R_CAN0_MCTL_RX_NEWDATA_Msk      (0x1UL)        /*!< NEWDATA (Bitfield-Mask: 0x01)                         */
22107 /* =========================================================  CTLR  ========================================================== */
22108  #define R_CAN0_CTLR_RBOC_Pos            (13UL)         /*!< RBOC (Bit 13)                                         */
22109  #define R_CAN0_CTLR_RBOC_Msk            (0x2000UL)     /*!< RBOC (Bitfield-Mask: 0x01)                            */
22110  #define R_CAN0_CTLR_BOM_Pos             (11UL)         /*!< BOM (Bit 11)                                          */
22111  #define R_CAN0_CTLR_BOM_Msk             (0x1800UL)     /*!< BOM (Bitfield-Mask: 0x03)                             */
22112  #define R_CAN0_CTLR_SLPM_Pos            (10UL)         /*!< SLPM (Bit 10)                                         */
22113  #define R_CAN0_CTLR_SLPM_Msk            (0x400UL)      /*!< SLPM (Bitfield-Mask: 0x01)                            */
22114  #define R_CAN0_CTLR_CANM_Pos            (8UL)          /*!< CANM (Bit 8)                                          */
22115  #define R_CAN0_CTLR_CANM_Msk            (0x300UL)      /*!< CANM (Bitfield-Mask: 0x03)                            */
22116  #define R_CAN0_CTLR_TSPS_Pos            (6UL)          /*!< TSPS (Bit 6)                                          */
22117  #define R_CAN0_CTLR_TSPS_Msk            (0xc0UL)       /*!< TSPS (Bitfield-Mask: 0x03)                            */
22118  #define R_CAN0_CTLR_TSRC_Pos            (5UL)          /*!< TSRC (Bit 5)                                          */
22119  #define R_CAN0_CTLR_TSRC_Msk            (0x20UL)       /*!< TSRC (Bitfield-Mask: 0x01)                            */
22120  #define R_CAN0_CTLR_TPM_Pos             (4UL)          /*!< TPM (Bit 4)                                           */
22121  #define R_CAN0_CTLR_TPM_Msk             (0x10UL)       /*!< TPM (Bitfield-Mask: 0x01)                             */
22122  #define R_CAN0_CTLR_MLM_Pos             (3UL)          /*!< MLM (Bit 3)                                           */
22123  #define R_CAN0_CTLR_MLM_Msk             (0x8UL)        /*!< MLM (Bitfield-Mask: 0x01)                             */
22124  #define R_CAN0_CTLR_IDFM_Pos            (1UL)          /*!< IDFM (Bit 1)                                          */
22125  #define R_CAN0_CTLR_IDFM_Msk            (0x6UL)        /*!< IDFM (Bitfield-Mask: 0x03)                            */
22126  #define R_CAN0_CTLR_MBM_Pos             (0UL)          /*!< MBM (Bit 0)                                           */
22127  #define R_CAN0_CTLR_MBM_Msk             (0x1UL)        /*!< MBM (Bitfield-Mask: 0x01)                             */
22128 /* ==========================================================  STR  ========================================================== */
22129  #define R_CAN0_STR_RECST_Pos            (14UL)         /*!< RECST (Bit 14)                                        */
22130  #define R_CAN0_STR_RECST_Msk            (0x4000UL)     /*!< RECST (Bitfield-Mask: 0x01)                           */
22131  #define R_CAN0_STR_TRMST_Pos            (13UL)         /*!< TRMST (Bit 13)                                        */
22132  #define R_CAN0_STR_TRMST_Msk            (0x2000UL)     /*!< TRMST (Bitfield-Mask: 0x01)                           */
22133  #define R_CAN0_STR_BOST_Pos             (12UL)         /*!< BOST (Bit 12)                                         */
22134  #define R_CAN0_STR_BOST_Msk             (0x1000UL)     /*!< BOST (Bitfield-Mask: 0x01)                            */
22135  #define R_CAN0_STR_EPST_Pos             (11UL)         /*!< EPST (Bit 11)                                         */
22136  #define R_CAN0_STR_EPST_Msk             (0x800UL)      /*!< EPST (Bitfield-Mask: 0x01)                            */
22137  #define R_CAN0_STR_SLPST_Pos            (10UL)         /*!< SLPST (Bit 10)                                        */
22138  #define R_CAN0_STR_SLPST_Msk            (0x400UL)      /*!< SLPST (Bitfield-Mask: 0x01)                           */
22139  #define R_CAN0_STR_HLTST_Pos            (9UL)          /*!< HLTST (Bit 9)                                         */
22140  #define R_CAN0_STR_HLTST_Msk            (0x200UL)      /*!< HLTST (Bitfield-Mask: 0x01)                           */
22141  #define R_CAN0_STR_RSTST_Pos            (8UL)          /*!< RSTST (Bit 8)                                         */
22142  #define R_CAN0_STR_RSTST_Msk            (0x100UL)      /*!< RSTST (Bitfield-Mask: 0x01)                           */
22143  #define R_CAN0_STR_EST_Pos              (7UL)          /*!< EST (Bit 7)                                           */
22144  #define R_CAN0_STR_EST_Msk              (0x80UL)       /*!< EST (Bitfield-Mask: 0x01)                             */
22145  #define R_CAN0_STR_TABST_Pos            (6UL)          /*!< TABST (Bit 6)                                         */
22146  #define R_CAN0_STR_TABST_Msk            (0x40UL)       /*!< TABST (Bitfield-Mask: 0x01)                           */
22147  #define R_CAN0_STR_FMLST_Pos            (5UL)          /*!< FMLST (Bit 5)                                         */
22148  #define R_CAN0_STR_FMLST_Msk            (0x20UL)       /*!< FMLST (Bitfield-Mask: 0x01)                           */
22149  #define R_CAN0_STR_NMLST_Pos            (4UL)          /*!< NMLST (Bit 4)                                         */
22150  #define R_CAN0_STR_NMLST_Msk            (0x10UL)       /*!< NMLST (Bitfield-Mask: 0x01)                           */
22151  #define R_CAN0_STR_TFST_Pos             (3UL)          /*!< TFST (Bit 3)                                          */
22152  #define R_CAN0_STR_TFST_Msk             (0x8UL)        /*!< TFST (Bitfield-Mask: 0x01)                            */
22153  #define R_CAN0_STR_RFST_Pos             (2UL)          /*!< RFST (Bit 2)                                          */
22154  #define R_CAN0_STR_RFST_Msk             (0x4UL)        /*!< RFST (Bitfield-Mask: 0x01)                            */
22155  #define R_CAN0_STR_SDST_Pos             (1UL)          /*!< SDST (Bit 1)                                          */
22156  #define R_CAN0_STR_SDST_Msk             (0x2UL)        /*!< SDST (Bitfield-Mask: 0x01)                            */
22157  #define R_CAN0_STR_NDST_Pos             (0UL)          /*!< NDST (Bit 0)                                          */
22158  #define R_CAN0_STR_NDST_Msk             (0x1UL)        /*!< NDST (Bitfield-Mask: 0x01)                            */
22159 /* ==========================================================  BCR  ========================================================== */
22160  #define R_CAN0_BCR_TSEG1_Pos            (28UL)         /*!< TSEG1 (Bit 28)                                        */
22161  #define R_CAN0_BCR_TSEG1_Msk            (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f)                           */
22162  #define R_CAN0_BCR_BRP_Pos              (16UL)         /*!< BRP (Bit 16)                                          */
22163  #define R_CAN0_BCR_BRP_Msk              (0x3ff0000UL)  /*!< BRP (Bitfield-Mask: 0x3ff)                            */
22164  #define R_CAN0_BCR_SJW_Pos              (12UL)         /*!< SJW (Bit 12)                                          */
22165  #define R_CAN0_BCR_SJW_Msk              (0x3000UL)     /*!< SJW (Bitfield-Mask: 0x03)                             */
22166  #define R_CAN0_BCR_TSEG2_Pos            (8UL)          /*!< TSEG2 (Bit 8)                                         */
22167  #define R_CAN0_BCR_TSEG2_Msk            (0x700UL)      /*!< TSEG2 (Bitfield-Mask: 0x07)                           */
22168  #define R_CAN0_BCR_CCLKS_Pos            (0UL)          /*!< CCLKS (Bit 0)                                         */
22169  #define R_CAN0_BCR_CCLKS_Msk            (0x1UL)        /*!< CCLKS (Bitfield-Mask: 0x01)                           */
22170 /* =========================================================  RFCR  ========================================================== */
22171  #define R_CAN0_RFCR_RFEST_Pos           (7UL)          /*!< RFEST (Bit 7)                                         */
22172  #define R_CAN0_RFCR_RFEST_Msk           (0x80UL)       /*!< RFEST (Bitfield-Mask: 0x01)                           */
22173  #define R_CAN0_RFCR_RFWST_Pos           (6UL)          /*!< RFWST (Bit 6)                                         */
22174  #define R_CAN0_RFCR_RFWST_Msk           (0x40UL)       /*!< RFWST (Bitfield-Mask: 0x01)                           */
22175  #define R_CAN0_RFCR_RFFST_Pos           (5UL)          /*!< RFFST (Bit 5)                                         */
22176  #define R_CAN0_RFCR_RFFST_Msk           (0x20UL)       /*!< RFFST (Bitfield-Mask: 0x01)                           */
22177  #define R_CAN0_RFCR_RFMLF_Pos           (4UL)          /*!< RFMLF (Bit 4)                                         */
22178  #define R_CAN0_RFCR_RFMLF_Msk           (0x10UL)       /*!< RFMLF (Bitfield-Mask: 0x01)                           */
22179  #define R_CAN0_RFCR_RFUST_Pos           (1UL)          /*!< RFUST (Bit 1)                                         */
22180  #define R_CAN0_RFCR_RFUST_Msk           (0xeUL)        /*!< RFUST (Bitfield-Mask: 0x07)                           */
22181  #define R_CAN0_RFCR_RFE_Pos             (0UL)          /*!< RFE (Bit 0)                                           */
22182  #define R_CAN0_RFCR_RFE_Msk             (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
22183 /* =========================================================  RFPCR  ========================================================= */
22184  #define R_CAN0_RFPCR_RFPCR_Pos          (0UL)          /*!< RFPCR (Bit 0)                                         */
22185  #define R_CAN0_RFPCR_RFPCR_Msk          (0xffUL)       /*!< RFPCR (Bitfield-Mask: 0xff)                           */
22186 /* =========================================================  TFCR  ========================================================== */
22187  #define R_CAN0_TFCR_TFEST_Pos           (7UL)          /*!< TFEST (Bit 7)                                         */
22188  #define R_CAN0_TFCR_TFEST_Msk           (0x80UL)       /*!< TFEST (Bitfield-Mask: 0x01)                           */
22189  #define R_CAN0_TFCR_TFFST_Pos           (6UL)          /*!< TFFST (Bit 6)                                         */
22190  #define R_CAN0_TFCR_TFFST_Msk           (0x40UL)       /*!< TFFST (Bitfield-Mask: 0x01)                           */
22191  #define R_CAN0_TFCR_TFUST_Pos           (1UL)          /*!< TFUST (Bit 1)                                         */
22192  #define R_CAN0_TFCR_TFUST_Msk           (0xeUL)        /*!< TFUST (Bitfield-Mask: 0x07)                           */
22193  #define R_CAN0_TFCR_TFE_Pos             (0UL)          /*!< TFE (Bit 0)                                           */
22194  #define R_CAN0_TFCR_TFE_Msk             (0x1UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
22195 /* =========================================================  TFPCR  ========================================================= */
22196  #define R_CAN0_TFPCR_TFPCR_Pos          (0UL)          /*!< TFPCR (Bit 0)                                         */
22197  #define R_CAN0_TFPCR_TFPCR_Msk          (0xffUL)       /*!< TFPCR (Bitfield-Mask: 0xff)                           */
22198 /* =========================================================  EIER  ========================================================== */
22199  #define R_CAN0_EIER_BLIE_Pos            (7UL)          /*!< BLIE (Bit 7)                                          */
22200  #define R_CAN0_EIER_BLIE_Msk            (0x80UL)       /*!< BLIE (Bitfield-Mask: 0x01)                            */
22201  #define R_CAN0_EIER_OLIE_Pos            (6UL)          /*!< OLIE (Bit 6)                                          */
22202  #define R_CAN0_EIER_OLIE_Msk            (0x40UL)       /*!< OLIE (Bitfield-Mask: 0x01)                            */
22203  #define R_CAN0_EIER_ORIE_Pos            (5UL)          /*!< ORIE (Bit 5)                                          */
22204  #define R_CAN0_EIER_ORIE_Msk            (0x20UL)       /*!< ORIE (Bitfield-Mask: 0x01)                            */
22205  #define R_CAN0_EIER_BORIE_Pos           (4UL)          /*!< BORIE (Bit 4)                                         */
22206  #define R_CAN0_EIER_BORIE_Msk           (0x10UL)       /*!< BORIE (Bitfield-Mask: 0x01)                           */
22207  #define R_CAN0_EIER_BOEIE_Pos           (3UL)          /*!< BOEIE (Bit 3)                                         */
22208  #define R_CAN0_EIER_BOEIE_Msk           (0x8UL)        /*!< BOEIE (Bitfield-Mask: 0x01)                           */
22209  #define R_CAN0_EIER_EPIE_Pos            (2UL)          /*!< EPIE (Bit 2)                                          */
22210  #define R_CAN0_EIER_EPIE_Msk            (0x4UL)        /*!< EPIE (Bitfield-Mask: 0x01)                            */
22211  #define R_CAN0_EIER_EWIE_Pos            (1UL)          /*!< EWIE (Bit 1)                                          */
22212  #define R_CAN0_EIER_EWIE_Msk            (0x2UL)        /*!< EWIE (Bitfield-Mask: 0x01)                            */
22213  #define R_CAN0_EIER_BEIE_Pos            (0UL)          /*!< BEIE (Bit 0)                                          */
22214  #define R_CAN0_EIER_BEIE_Msk            (0x1UL)        /*!< BEIE (Bitfield-Mask: 0x01)                            */
22215 /* =========================================================  EIFR  ========================================================== */
22216  #define R_CAN0_EIFR_BLIF_Pos            (7UL)          /*!< BLIF (Bit 7)                                          */
22217  #define R_CAN0_EIFR_BLIF_Msk            (0x80UL)       /*!< BLIF (Bitfield-Mask: 0x01)                            */
22218  #define R_CAN0_EIFR_OLIF_Pos            (6UL)          /*!< OLIF (Bit 6)                                          */
22219  #define R_CAN0_EIFR_OLIF_Msk            (0x40UL)       /*!< OLIF (Bitfield-Mask: 0x01)                            */
22220  #define R_CAN0_EIFR_ORIF_Pos            (5UL)          /*!< ORIF (Bit 5)                                          */
22221  #define R_CAN0_EIFR_ORIF_Msk            (0x20UL)       /*!< ORIF (Bitfield-Mask: 0x01)                            */
22222  #define R_CAN0_EIFR_BORIF_Pos           (4UL)          /*!< BORIF (Bit 4)                                         */
22223  #define R_CAN0_EIFR_BORIF_Msk           (0x10UL)       /*!< BORIF (Bitfield-Mask: 0x01)                           */
22224  #define R_CAN0_EIFR_BOEIF_Pos           (3UL)          /*!< BOEIF (Bit 3)                                         */
22225  #define R_CAN0_EIFR_BOEIF_Msk           (0x8UL)        /*!< BOEIF (Bitfield-Mask: 0x01)                           */
22226  #define R_CAN0_EIFR_EPIF_Pos            (2UL)          /*!< EPIF (Bit 2)                                          */
22227  #define R_CAN0_EIFR_EPIF_Msk            (0x4UL)        /*!< EPIF (Bitfield-Mask: 0x01)                            */
22228  #define R_CAN0_EIFR_EWIF_Pos            (1UL)          /*!< EWIF (Bit 1)                                          */
22229  #define R_CAN0_EIFR_EWIF_Msk            (0x2UL)        /*!< EWIF (Bitfield-Mask: 0x01)                            */
22230  #define R_CAN0_EIFR_BEIF_Pos            (0UL)          /*!< BEIF (Bit 0)                                          */
22231  #define R_CAN0_EIFR_BEIF_Msk            (0x1UL)        /*!< BEIF (Bitfield-Mask: 0x01)                            */
22232 /* =========================================================  RECR  ========================================================== */
22233  #define R_CAN0_RECR_RECR_Pos            (0UL)          /*!< RECR (Bit 0)                                          */
22234  #define R_CAN0_RECR_RECR_Msk            (0xffUL)       /*!< RECR (Bitfield-Mask: 0xff)                            */
22235 /* =========================================================  TECR  ========================================================== */
22236  #define R_CAN0_TECR_TECR_Pos            (0UL)          /*!< TECR (Bit 0)                                          */
22237  #define R_CAN0_TECR_TECR_Msk            (0xffUL)       /*!< TECR (Bitfield-Mask: 0xff)                            */
22238 /* =========================================================  ECSR  ========================================================== */
22239  #define R_CAN0_ECSR_EDPM_Pos            (7UL)          /*!< EDPM (Bit 7)                                          */
22240  #define R_CAN0_ECSR_EDPM_Msk            (0x80UL)       /*!< EDPM (Bitfield-Mask: 0x01)                            */
22241  #define R_CAN0_ECSR_ADEF_Pos            (6UL)          /*!< ADEF (Bit 6)                                          */
22242  #define R_CAN0_ECSR_ADEF_Msk            (0x40UL)       /*!< ADEF (Bitfield-Mask: 0x01)                            */
22243  #define R_CAN0_ECSR_BE0F_Pos            (5UL)          /*!< BE0F (Bit 5)                                          */
22244  #define R_CAN0_ECSR_BE0F_Msk            (0x20UL)       /*!< BE0F (Bitfield-Mask: 0x01)                            */
22245  #define R_CAN0_ECSR_BE1F_Pos            (4UL)          /*!< BE1F (Bit 4)                                          */
22246  #define R_CAN0_ECSR_BE1F_Msk            (0x10UL)       /*!< BE1F (Bitfield-Mask: 0x01)                            */
22247  #define R_CAN0_ECSR_CEF_Pos             (3UL)          /*!< CEF (Bit 3)                                           */
22248  #define R_CAN0_ECSR_CEF_Msk             (0x8UL)        /*!< CEF (Bitfield-Mask: 0x01)                             */
22249  #define R_CAN0_ECSR_AEF_Pos             (2UL)          /*!< AEF (Bit 2)                                           */
22250  #define R_CAN0_ECSR_AEF_Msk             (0x4UL)        /*!< AEF (Bitfield-Mask: 0x01)                             */
22251  #define R_CAN0_ECSR_FEF_Pos             (1UL)          /*!< FEF (Bit 1)                                           */
22252  #define R_CAN0_ECSR_FEF_Msk             (0x2UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
22253  #define R_CAN0_ECSR_SEF_Pos             (0UL)          /*!< SEF (Bit 0)                                           */
22254  #define R_CAN0_ECSR_SEF_Msk             (0x1UL)        /*!< SEF (Bitfield-Mask: 0x01)                             */
22255 /* =========================================================  CSSR  ========================================================== */
22256  #define R_CAN0_CSSR_CSSR_Pos            (0UL)          /*!< CSSR (Bit 0)                                          */
22257  #define R_CAN0_CSSR_CSSR_Msk            (0xffUL)       /*!< CSSR (Bitfield-Mask: 0xff)                            */
22258 /* =========================================================  MSSR  ========================================================== */
22259  #define R_CAN0_MSSR_SEST_Pos            (7UL)          /*!< SEST (Bit 7)                                          */
22260  #define R_CAN0_MSSR_SEST_Msk            (0x80UL)       /*!< SEST (Bitfield-Mask: 0x01)                            */
22261  #define R_CAN0_MSSR_MBNST_Pos           (0UL)          /*!< MBNST (Bit 0)                                         */
22262  #define R_CAN0_MSSR_MBNST_Msk           (0x1fUL)       /*!< MBNST (Bitfield-Mask: 0x1f)                           */
22263 /* =========================================================  MSMR  ========================================================== */
22264  #define R_CAN0_MSMR_MBSM_Pos            (0UL)          /*!< MBSM (Bit 0)                                          */
22265  #define R_CAN0_MSMR_MBSM_Msk            (0x3UL)        /*!< MBSM (Bitfield-Mask: 0x03)                            */
22266 /* ==========================================================  TSR  ========================================================== */
22267  #define R_CAN0_TSR_TSR_Pos              (0UL)          /*!< TSR (Bit 0)                                           */
22268  #define R_CAN0_TSR_TSR_Msk              (0xffffUL)     /*!< TSR (Bitfield-Mask: 0xffff)                           */
22269 /* =========================================================  AFSR  ========================================================== */
22270  #define R_CAN0_AFSR_AFSR_Pos            (0UL)          /*!< AFSR (Bit 0)                                          */
22271  #define R_CAN0_AFSR_AFSR_Msk            (0xffffUL)     /*!< AFSR (Bitfield-Mask: 0xffff)                          */
22272 /* ==========================================================  TCR  ========================================================== */
22273  #define R_CAN0_TCR_TSTM_Pos             (1UL)          /*!< TSTM (Bit 1)                                          */
22274  #define R_CAN0_TCR_TSTM_Msk             (0x6UL)        /*!< TSTM (Bitfield-Mask: 0x03)                            */
22275  #define R_CAN0_TCR_TSTE_Pos             (0UL)          /*!< TSTE (Bit 0)                                          */
22276  #define R_CAN0_TCR_TSTE_Msk             (0x1UL)        /*!< TSTE (Bitfield-Mask: 0x01)                            */
22277 
22278 /* =========================================================================================================================== */
22279 /* ================                                           R_CRC                                           ================ */
22280 /* =========================================================================================================================== */
22281 
22282 /* ========================================================  CRCCR0  ========================================================= */
22283  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
22284  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
22285  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
22286  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
22287  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
22288  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
22289 /* ========================================================  CRCCR1  ========================================================= */
22290  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
22291  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
22292  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
22293  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
22294 /* ========================================================  CRCDIR  ========================================================= */
22295  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
22296  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
22297 /* =======================================================  CRCDIR_BY  ======================================================= */
22298  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
22299  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
22300 /* ========================================================  CRCDOR  ========================================================= */
22301  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
22302  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
22303 /* =======================================================  CRCDOR_HA  ======================================================= */
22304  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
22305  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
22306 /* =======================================================  CRCDOR_BY  ======================================================= */
22307  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
22308  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
22309 /* ========================================================  CRCSAR  ========================================================= */
22310  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
22311  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
22312 
22313 /* =========================================================================================================================== */
22314 /* ================                                          R_CTSU                                           ================ */
22315 /* =========================================================================================================================== */
22316 
22317 /* ========================================================  CTSUCR0  ======================================================== */
22318  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos       (7UL)      /*!< CTSUTXVSEL (Bit 7)                                    */
22319  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk       (0x80UL)   /*!< CTSUTXVSEL (Bitfield-Mask: 0x01)                      */
22320  #define R_CTSU_CTSUCR0_CTSUINIT_Pos         (4UL)      /*!< CTSUINIT (Bit 4)                                      */
22321  #define R_CTSU_CTSUCR0_CTSUINIT_Msk         (0x10UL)   /*!< CTSUINIT (Bitfield-Mask: 0x01)                        */
22322  #define R_CTSU_CTSUCR0_CTSUIOC_Pos          (3UL)      /*!< CTSUIOC (Bit 3)                                       */
22323  #define R_CTSU_CTSUCR0_CTSUIOC_Msk          (0x8UL)    /*!< CTSUIOC (Bitfield-Mask: 0x01)                         */
22324  #define R_CTSU_CTSUCR0_CTSUSNZ_Pos          (2UL)      /*!< CTSUSNZ (Bit 2)                                       */
22325  #define R_CTSU_CTSUCR0_CTSUSNZ_Msk          (0x4UL)    /*!< CTSUSNZ (Bitfield-Mask: 0x01)                         */
22326  #define R_CTSU_CTSUCR0_CTSUCAP_Pos          (1UL)      /*!< CTSUCAP (Bit 1)                                       */
22327  #define R_CTSU_CTSUCR0_CTSUCAP_Msk          (0x2UL)    /*!< CTSUCAP (Bitfield-Mask: 0x01)                         */
22328  #define R_CTSU_CTSUCR0_CTSUSTRT_Pos         (0UL)      /*!< CTSUSTRT (Bit 0)                                      */
22329  #define R_CTSU_CTSUCR0_CTSUSTRT_Msk         (0x1UL)    /*!< CTSUSTRT (Bitfield-Mask: 0x01)                        */
22330 /* ========================================================  CTSUCR1  ======================================================== */
22331  #define R_CTSU_CTSUCR1_CTSUMD_Pos           (6UL)      /*!< CTSUMD (Bit 6)                                        */
22332  #define R_CTSU_CTSUCR1_CTSUMD_Msk           (0xc0UL)   /*!< CTSUMD (Bitfield-Mask: 0x03)                          */
22333  #define R_CTSU_CTSUCR1_CTSUCLK_Pos          (4UL)      /*!< CTSUCLK (Bit 4)                                       */
22334  #define R_CTSU_CTSUCR1_CTSUCLK_Msk          (0x30UL)   /*!< CTSUCLK (Bitfield-Mask: 0x03)                         */
22335  #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos       (3UL)      /*!< CTSUATUNE1 (Bit 3)                                    */
22336  #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk       (0x8UL)    /*!< CTSUATUNE1 (Bitfield-Mask: 0x01)                      */
22337  #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos       (2UL)      /*!< CTSUATUNE0 (Bit 2)                                    */
22338  #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk       (0x4UL)    /*!< CTSUATUNE0 (Bitfield-Mask: 0x01)                      */
22339  #define R_CTSU_CTSUCR1_CTSUCSW_Pos          (1UL)      /*!< CTSUCSW (Bit 1)                                       */
22340  #define R_CTSU_CTSUCR1_CTSUCSW_Msk          (0x2UL)    /*!< CTSUCSW (Bitfield-Mask: 0x01)                         */
22341  #define R_CTSU_CTSUCR1_CTSUPON_Pos          (0UL)      /*!< CTSUPON (Bit 0)                                       */
22342  #define R_CTSU_CTSUCR1_CTSUPON_Msk          (0x1UL)    /*!< CTSUPON (Bitfield-Mask: 0x01)                         */
22343 /* =======================================================  CTSUSDPRS  ======================================================= */
22344  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos       (6UL)      /*!< CTSUSOFF (Bit 6)                                      */
22345  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk       (0x40UL)   /*!< CTSUSOFF (Bitfield-Mask: 0x01)                        */
22346  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos     (4UL)      /*!< CTSUPRMODE (Bit 4)                                    */
22347  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk     (0x30UL)   /*!< CTSUPRMODE (Bitfield-Mask: 0x03)                      */
22348  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos    (0UL)      /*!< CTSUPRRATIO (Bit 0)                                   */
22349  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk    (0xfUL)    /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f)                     */
22350 /* ========================================================  CTSUSST  ======================================================== */
22351  #define R_CTSU_CTSUSST_CTSUSST_Pos          (0UL)      /*!< CTSUSST (Bit 0)                                       */
22352  #define R_CTSU_CTSUSST_CTSUSST_Msk          (0xffUL)   /*!< CTSUSST (Bitfield-Mask: 0xff)                         */
22353 /* =======================================================  CTSUMCH0  ======================================================== */
22354  #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos        (0UL)      /*!< CTSUMCH0 (Bit 0)                                      */
22355  #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk        (0x3fUL)   /*!< CTSUMCH0 (Bitfield-Mask: 0x3f)                        */
22356 /* =======================================================  CTSUMCH1  ======================================================== */
22357  #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos        (0UL)      /*!< CTSUMCH1 (Bit 0)                                      */
22358  #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk        (0x3fUL)   /*!< CTSUMCH1 (Bitfield-Mask: 0x3f)                        */
22359 /* =======================================================  CTSUCHAC  ======================================================== */
22360  #define R_CTSU_CTSUCHAC_TS_Pos              (0UL)      /*!< TS (Bit 0)                                            */
22361  #define R_CTSU_CTSUCHAC_TS_Msk              (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
22362 /* =======================================================  CTSUCHTRC  ======================================================= */
22363  #define R_CTSU_CTSUCHTRC_TS_Pos             (0UL)      /*!< TS (Bit 0)                                            */
22364  #define R_CTSU_CTSUCHTRC_TS_Msk             (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
22365 /* =======================================================  CTSUDCLKC  ======================================================= */
22366  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos      (4UL)      /*!< CTSUSSCNT (Bit 4)                                     */
22367  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk      (0x30UL)   /*!< CTSUSSCNT (Bitfield-Mask: 0x03)                       */
22368  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos      (0UL)      /*!< CTSUSSMOD (Bit 0)                                     */
22369  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk      (0x3UL)    /*!< CTSUSSMOD (Bitfield-Mask: 0x03)                       */
22370 /* ========================================================  CTSUST  ========================================================= */
22371  #define R_CTSU_CTSUST_CTSUPS_Pos            (7UL)      /*!< CTSUPS (Bit 7)                                        */
22372  #define R_CTSU_CTSUST_CTSUPS_Msk            (0x80UL)   /*!< CTSUPS (Bitfield-Mask: 0x01)                          */
22373  #define R_CTSU_CTSUST_CTSUROVF_Pos          (6UL)      /*!< CTSUROVF (Bit 6)                                      */
22374  #define R_CTSU_CTSUST_CTSUROVF_Msk          (0x40UL)   /*!< CTSUROVF (Bitfield-Mask: 0x01)                        */
22375  #define R_CTSU_CTSUST_CTSUSOVF_Pos          (5UL)      /*!< CTSUSOVF (Bit 5)                                      */
22376  #define R_CTSU_CTSUST_CTSUSOVF_Msk          (0x20UL)   /*!< CTSUSOVF (Bitfield-Mask: 0x01)                        */
22377  #define R_CTSU_CTSUST_CTSUDTSR_Pos          (4UL)      /*!< CTSUDTSR (Bit 4)                                      */
22378  #define R_CTSU_CTSUST_CTSUDTSR_Msk          (0x10UL)   /*!< CTSUDTSR (Bitfield-Mask: 0x01)                        */
22379  #define R_CTSU_CTSUST_CTSUSTC_Pos           (0UL)      /*!< CTSUSTC (Bit 0)                                       */
22380  #define R_CTSU_CTSUST_CTSUSTC_Msk           (0x7UL)    /*!< CTSUSTC (Bitfield-Mask: 0x07)                         */
22381 /* ========================================================  CTSUSSC  ======================================================== */
22382  #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos        (8UL)      /*!< CTSUSSDIV (Bit 8)                                     */
22383  #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk        (0xf00UL)  /*!< CTSUSSDIV (Bitfield-Mask: 0x0f)                       */
22384 /* ========================================================  CTSUSO0  ======================================================== */
22385  #define R_CTSU_CTSUSO0_CTSUSNUM_Pos         (10UL)     /*!< CTSUSNUM (Bit 10)                                     */
22386  #define R_CTSU_CTSUSO0_CTSUSNUM_Msk         (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f)                        */
22387  #define R_CTSU_CTSUSO0_CTSUSO_Pos           (0UL)      /*!< CTSUSO (Bit 0)                                        */
22388  #define R_CTSU_CTSUSO0_CTSUSO_Msk           (0x3ffUL)  /*!< CTSUSO (Bitfield-Mask: 0x3ff)                         */
22389 /* ========================================================  CTSUSO1  ======================================================== */
22390  #define R_CTSU_CTSUSO1_CTSUICOG_Pos         (13UL)     /*!< CTSUICOG (Bit 13)                                     */
22391  #define R_CTSU_CTSUSO1_CTSUICOG_Msk         (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03)                        */
22392  #define R_CTSU_CTSUSO1_CTSUSDPA_Pos         (8UL)      /*!< CTSUSDPA (Bit 8)                                      */
22393  #define R_CTSU_CTSUSO1_CTSUSDPA_Msk         (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f)                        */
22394  #define R_CTSU_CTSUSO1_CTSURICOA_Pos        (0UL)      /*!< CTSURICOA (Bit 0)                                     */
22395  #define R_CTSU_CTSUSO1_CTSURICOA_Msk        (0xffUL)   /*!< CTSURICOA (Bitfield-Mask: 0xff)                       */
22396 /* ========================================================  CTSUSC  ========================================================= */
22397  #define R_CTSU_CTSUSC_CTSUSC_Pos            (0UL)      /*!< CTSUSC (Bit 0)                                        */
22398  #define R_CTSU_CTSUSC_CTSUSC_Msk            (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff)                        */
22399 /* ========================================================  CTSURC  ========================================================= */
22400  #define R_CTSU_CTSURC_CTSURC_Pos            (0UL)      /*!< CTSURC (Bit 0)                                        */
22401  #define R_CTSU_CTSURC_CTSURC_Msk            (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff)                        */
22402 /* =======================================================  CTSUERRS  ======================================================== */
22403  #define R_CTSU_CTSUERRS_CTSUICOMP_Pos       (15UL)     /*!< CTSUICOMP (Bit 15)                                    */
22404  #define R_CTSU_CTSUERRS_CTSUICOMP_Msk       (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01)                       */
22405  #define R_CTSU_CTSUERRS_CTSUSPMD_Pos        (0UL)      /*!< CTSUSPMD (Bit 0)                                      */
22406  #define R_CTSU_CTSUERRS_CTSUSPMD_Msk        (0x3UL)    /*!< CTSUSPMD (Bitfield-Mask: 0x03)                        */
22407  #define R_CTSU_CTSUERRS_CTSUTSOD_Pos        (2UL)      /*!< CTSUTSOD (Bit 2)                                      */
22408  #define R_CTSU_CTSUERRS_CTSUTSOD_Msk        (0x4UL)    /*!< CTSUTSOD (Bitfield-Mask: 0x01)                        */
22409  #define R_CTSU_CTSUERRS_CTSUDRV_Pos         (3UL)      /*!< CTSUDRV (Bit 3)                                       */
22410  #define R_CTSU_CTSUERRS_CTSUDRV_Msk         (0x8UL)    /*!< CTSUDRV (Bitfield-Mask: 0x01)                         */
22411  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos     (6UL)      /*!< CTSUCLKSEL1 (Bit 6)                                   */
22412  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk     (0x40UL)   /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01)                     */
22413  #define R_CTSU_CTSUERRS_CTSUTSOC_Pos        (7UL)      /*!< CTSUTSOC (Bit 7)                                      */
22414  #define R_CTSU_CTSUERRS_CTSUTSOC_Msk        (0x80UL)   /*!< CTSUTSOC (Bitfield-Mask: 0x01)                        */
22415 /* =======================================================  CTSUTRMR  ======================================================== */
22416 
22417 /* =========================================================================================================================== */
22418 /* ================                                           R_DAC                                           ================ */
22419 /* =========================================================================================================================== */
22420 
22421 /* =========================================================  DACR  ========================================================== */
22422  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
22423  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
22424  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
22425  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
22426 /* =========================================================  DADR  ========================================================== */
22427  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
22428  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
22429 /* =========================================================  DADPR  ========================================================= */
22430  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
22431  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
22432 /* ========================================================  DAADSCR  ======================================================== */
22433  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
22434  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
22435 /* =======================================================  DAVREFCR  ======================================================== */
22436  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
22437  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
22438 /* =========================================================  DAPC  ========================================================== */
22439  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
22440  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
22441 /* ========================================================  DAAMPCR  ======================================================== */
22442  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
22443  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
22444 /* ========================================================  DAASWCR  ======================================================== */
22445  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
22446  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
22447  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
22448  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
22449 /* ========================================================  DAADUSR  ======================================================== */
22450  #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
22451  #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
22452  #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
22453  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
22454 
22455 /* =========================================================================================================================== */
22456 /* ================                                          R_DEBUG                                          ================ */
22457 /* =========================================================================================================================== */
22458 
22459 /* ========================================================  DBGSTR  ========================================================= */
22460  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
22461  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
22462  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
22463  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
22464 /* =======================================================  DBGSTOPCR  ======================================================= */
22465  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
22466  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
22467  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
22468  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
22469  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
22470  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
22471  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
22472  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
22473  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
22474  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
22475  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
22476  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
22477  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
22478  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
22479  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
22480  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
22481 /* =======================================================  FSBLSTAT  ======================================================== */
22482  #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
22483  #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
22484  #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
22485  #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
22486  #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
22487  #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
22488 
22489 /* =========================================================================================================================== */
22490 /* ================                                           R_DMA                                           ================ */
22491 /* =========================================================================================================================== */
22492 
22493 /* =========================================================  DMAST  ========================================================= */
22494  #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
22495  #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
22496 /* ========================================================  DMECHR  ========================================================= */
22497  #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
22498  #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
22499  #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
22500  #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
22501  #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
22502  #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
22503 /* =========================================================  DELSR  ========================================================= */
22504  #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
22505  #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
22506  #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
22507  #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
22508 
22509 /* =========================================================================================================================== */
22510 /* ================                                          R_DMAC0                                          ================ */
22511 /* =========================================================================================================================== */
22512 
22513 /* =========================================================  DMSAR  ========================================================= */
22514  #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
22515  #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
22516 /* =========================================================  DMDAR  ========================================================= */
22517  #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
22518  #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
22519 /* =========================================================  DMCRA  ========================================================= */
22520  #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
22521  #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
22522  #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
22523  #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
22524 /* =========================================================  DMCRB  ========================================================= */
22525  #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
22526  #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
22527  #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
22528  #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
22529 /* =========================================================  DMTMD  ========================================================= */
22530  #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
22531  #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
22532  #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
22533  #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
22534  #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
22535  #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
22536  #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
22537  #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
22538  #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
22539  #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
22540 /* =========================================================  DMINT  ========================================================= */
22541  #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
22542  #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
22543  #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
22544  #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
22545  #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
22546  #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
22547  #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
22548  #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
22549  #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
22550  #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
22551 /* =========================================================  DMAMD  ========================================================= */
22552  #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
22553  #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
22554  #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
22555  #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
22556  #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
22557  #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
22558  #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
22559  #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
22560  #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
22561  #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
22562  #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
22563  #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
22564 /* =========================================================  DMOFR  ========================================================= */
22565  #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
22566  #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
22567 /* =========================================================  DMCNT  ========================================================= */
22568  #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
22569  #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
22570 /* =========================================================  DMREQ  ========================================================= */
22571  #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
22572  #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
22573  #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
22574  #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
22575 /* =========================================================  DMSTS  ========================================================= */
22576  #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
22577  #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
22578  #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
22579  #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
22580  #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
22581  #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
22582 /* =========================================================  DMSRR  ========================================================= */
22583 /* =========================================================  DMDRR  ========================================================= */
22584 /* =========================================================  DMSBS  ========================================================= */
22585  #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
22586  #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
22587  #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
22588  #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
22589 /* =========================================================  DMDBS  ========================================================= */
22590  #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
22591  #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
22592  #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
22593  #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
22594 /* =========================================================  DMBWR  ========================================================= */
22595  #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
22596  #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
22597 
22598 /* =========================================================================================================================== */
22599 /* ================                                           R_DOC                                           ================ */
22600 /* =========================================================================================================================== */
22601 
22602 /* =========================================================  DOCR  ========================================================== */
22603  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
22604  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
22605  #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
22606  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
22607  #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
22608  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
22609  #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
22610  #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
22611 /* =========================================================  DODIR  ========================================================= */
22612  #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
22613  #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
22614 /* =========================================================  DODSR  ========================================================= */
22615  #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
22616  #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
22617 
22618 /* =========================================================================================================================== */
22619 /* ================                                           R_DRW                                           ================ */
22620 /* =========================================================================================================================== */
22621 
22622 /* ========================================================  CONTROL  ======================================================== */
22623  #define R_DRW_CONTROL_SPANSTORE_Pos           (23UL)         /*!< SPANSTORE (Bit 23)                                    */
22624  #define R_DRW_CONTROL_SPANSTORE_Msk           (0x800000UL)   /*!< SPANSTORE (Bitfield-Mask: 0x01)                       */
22625  #define R_DRW_CONTROL_SPANABORT_Pos           (22UL)         /*!< SPANABORT (Bit 22)                                    */
22626  #define R_DRW_CONTROL_SPANABORT_Msk           (0x400000UL)   /*!< SPANABORT (Bitfield-Mask: 0x01)                       */
22627  #define R_DRW_CONTROL_UNIONCD_Pos             (21UL)         /*!< UNIONCD (Bit 21)                                      */
22628  #define R_DRW_CONTROL_UNIONCD_Msk             (0x200000UL)   /*!< UNIONCD (Bitfield-Mask: 0x01)                         */
22629  #define R_DRW_CONTROL_UNIONAB_Pos             (20UL)         /*!< UNIONAB (Bit 20)                                      */
22630  #define R_DRW_CONTROL_UNIONAB_Msk             (0x100000UL)   /*!< UNIONAB (Bitfield-Mask: 0x01)                         */
22631  #define R_DRW_CONTROL_UNION56_Pos             (19UL)         /*!< UNION56 (Bit 19)                                      */
22632  #define R_DRW_CONTROL_UNION56_Msk             (0x80000UL)    /*!< UNION56 (Bitfield-Mask: 0x01)                         */
22633  #define R_DRW_CONTROL_UNION34_Pos             (18UL)         /*!< UNION34 (Bit 18)                                      */
22634  #define R_DRW_CONTROL_UNION34_Msk             (0x40000UL)    /*!< UNION34 (Bitfield-Mask: 0x01)                         */
22635  #define R_DRW_CONTROL_UNION12_Pos             (17UL)         /*!< UNION12 (Bit 17)                                      */
22636  #define R_DRW_CONTROL_UNION12_Msk             (0x20000UL)    /*!< UNION12 (Bitfield-Mask: 0x01)                         */
22637  #define R_DRW_CONTROL_BAND2ENABLE_Pos         (16UL)         /*!< BAND2ENABLE (Bit 16)                                  */
22638  #define R_DRW_CONTROL_BAND2ENABLE_Msk         (0x10000UL)    /*!< BAND2ENABLE (Bitfield-Mask: 0x01)                     */
22639  #define R_DRW_CONTROL_BAND1ENABLE_Pos         (15UL)         /*!< BAND1ENABLE (Bit 15)                                  */
22640  #define R_DRW_CONTROL_BAND1ENABLE_Msk         (0x8000UL)     /*!< BAND1ENABLE (Bitfield-Mask: 0x01)                     */
22641  #define R_DRW_CONTROL_LIM6THRESHOLD_Pos       (14UL)         /*!< LIM6THRESHOLD (Bit 14)                                */
22642  #define R_DRW_CONTROL_LIM6THRESHOLD_Msk       (0x4000UL)     /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01)                   */
22643  #define R_DRW_CONTROL_LIM5THRESHOLD_Pos       (13UL)         /*!< LIM5THRESHOLD (Bit 13)                                */
22644  #define R_DRW_CONTROL_LIM5THRESHOLD_Msk       (0x2000UL)     /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01)                   */
22645  #define R_DRW_CONTROL_LIM4THRESHOLD_Pos       (12UL)         /*!< LIM4THRESHOLD (Bit 12)                                */
22646  #define R_DRW_CONTROL_LIM4THRESHOLD_Msk       (0x1000UL)     /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01)                   */
22647  #define R_DRW_CONTROL_LIM3THRESHOLD_Pos       (11UL)         /*!< LIM3THRESHOLD (Bit 11)                                */
22648  #define R_DRW_CONTROL_LIM3THRESHOLD_Msk       (0x800UL)      /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01)                   */
22649  #define R_DRW_CONTROL_LIM2THRESHOLD_Pos       (10UL)         /*!< LIM2THRESHOLD (Bit 10)                                */
22650  #define R_DRW_CONTROL_LIM2THRESHOLD_Msk       (0x400UL)      /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01)                   */
22651  #define R_DRW_CONTROL_LIM1THRESHOLD_Pos       (9UL)          /*!< LIM1THRESHOLD (Bit 9)                                 */
22652  #define R_DRW_CONTROL_LIM1THRESHOLD_Msk       (0x200UL)      /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01)                   */
22653  #define R_DRW_CONTROL_QUAD3ENABLE_Pos         (8UL)          /*!< QUAD3ENABLE (Bit 8)                                   */
22654  #define R_DRW_CONTROL_QUAD3ENABLE_Msk         (0x100UL)      /*!< QUAD3ENABLE (Bitfield-Mask: 0x01)                     */
22655  #define R_DRW_CONTROL_QUAD2ENABLE_Pos         (7UL)          /*!< QUAD2ENABLE (Bit 7)                                   */
22656  #define R_DRW_CONTROL_QUAD2ENABLE_Msk         (0x80UL)       /*!< QUAD2ENABLE (Bitfield-Mask: 0x01)                     */
22657  #define R_DRW_CONTROL_QUAD1ENABLE_Pos         (6UL)          /*!< QUAD1ENABLE (Bit 6)                                   */
22658  #define R_DRW_CONTROL_QUAD1ENABLE_Msk         (0x40UL)       /*!< QUAD1ENABLE (Bitfield-Mask: 0x01)                     */
22659  #define R_DRW_CONTROL_LIM6ENABLE_Pos          (5UL)          /*!< LIM6ENABLE (Bit 5)                                    */
22660  #define R_DRW_CONTROL_LIM6ENABLE_Msk          (0x20UL)       /*!< LIM6ENABLE (Bitfield-Mask: 0x01)                      */
22661  #define R_DRW_CONTROL_LIM5ENABLE_Pos          (4UL)          /*!< LIM5ENABLE (Bit 4)                                    */
22662  #define R_DRW_CONTROL_LIM5ENABLE_Msk          (0x10UL)       /*!< LIM5ENABLE (Bitfield-Mask: 0x01)                      */
22663  #define R_DRW_CONTROL_LIM4ENABLE_Pos          (3UL)          /*!< LIM4ENABLE (Bit 3)                                    */
22664  #define R_DRW_CONTROL_LIM4ENABLE_Msk          (0x8UL)        /*!< LIM4ENABLE (Bitfield-Mask: 0x01)                      */
22665  #define R_DRW_CONTROL_LIM3ENABLE_Pos          (2UL)          /*!< LIM3ENABLE (Bit 2)                                    */
22666  #define R_DRW_CONTROL_LIM3ENABLE_Msk          (0x4UL)        /*!< LIM3ENABLE (Bitfield-Mask: 0x01)                      */
22667  #define R_DRW_CONTROL_LIM2ENABLE_Pos          (1UL)          /*!< LIM2ENABLE (Bit 1)                                    */
22668  #define R_DRW_CONTROL_LIM2ENABLE_Msk          (0x2UL)        /*!< LIM2ENABLE (Bitfield-Mask: 0x01)                      */
22669  #define R_DRW_CONTROL_LIM1ENABLE_Pos          (0UL)          /*!< LIM1ENABLE (Bit 0)                                    */
22670  #define R_DRW_CONTROL_LIM1ENABLE_Msk          (0x1UL)        /*!< LIM1ENABLE (Bitfield-Mask: 0x01)                      */
22671 /* =======================================================  CONTROL2  ======================================================== */
22672  #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos      (30UL)         /*!< RLEPIXELWIDTH (Bit 30)                                */
22673  #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk      (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03)                   */
22674  #define R_DRW_CONTROL2_BDIA_Pos               (29UL)         /*!< BDIA (Bit 29)                                         */
22675  #define R_DRW_CONTROL2_BDIA_Msk               (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01)                            */
22676  #define R_DRW_CONTROL2_BSIA_Pos               (28UL)         /*!< BSIA (Bit 28)                                         */
22677  #define R_DRW_CONTROL2_BSIA_Msk               (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01)                            */
22678  #define R_DRW_CONTROL2_CLUTFORMAT_Pos         (27UL)         /*!< CLUTFORMAT (Bit 27)                                   */
22679  #define R_DRW_CONTROL2_CLUTFORMAT_Msk         (0x8000000UL)  /*!< CLUTFORMAT (Bitfield-Mask: 0x01)                      */
22680  #define R_DRW_CONTROL2_COLKEYENABLE_Pos       (26UL)         /*!< COLKEYENABLE (Bit 26)                                 */
22681  #define R_DRW_CONTROL2_COLKEYENABLE_Msk       (0x4000000UL)  /*!< COLKEYENABLE (Bitfield-Mask: 0x01)                    */
22682  #define R_DRW_CONTROL2_CLUTENABLE_Pos         (25UL)         /*!< CLUTENABLE (Bit 25)                                   */
22683  #define R_DRW_CONTROL2_CLUTENABLE_Msk         (0x2000000UL)  /*!< CLUTENABLE (Bitfield-Mask: 0x01)                      */
22684  #define R_DRW_CONTROL2_RLEENABLE_Pos          (24UL)         /*!< RLEENABLE (Bit 24)                                    */
22685  #define R_DRW_CONTROL2_RLEENABLE_Msk          (0x1000000UL)  /*!< RLEENABLE (Bitfield-Mask: 0x01)                       */
22686  #define R_DRW_CONTROL2_WRITEALPHA_Pos         (22UL)         /*!< WRITEALPHA (Bit 22)                                   */
22687  #define R_DRW_CONTROL2_WRITEALPHA_Msk         (0xc00000UL)   /*!< WRITEALPHA (Bitfield-Mask: 0x03)                      */
22688  #define R_DRW_CONTROL2_WRITEFORMAT10_Pos      (20UL)         /*!< WRITEFORMAT10 (Bit 20)                                */
22689  #define R_DRW_CONTROL2_WRITEFORMAT10_Msk      (0x300000UL)   /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03)                   */
22690  #define R_DRW_CONTROL2_READFORMAT10_Pos       (18UL)         /*!< READFORMAT10 (Bit 18)                                 */
22691  #define R_DRW_CONTROL2_READFORMAT10_Msk       (0xc0000UL)    /*!< READFORMAT10 (Bitfield-Mask: 0x03)                    */
22692  #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos     (17UL)         /*!< TEXTUREFILTERY (Bit 17)                               */
22693  #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk     (0x20000UL)    /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01)                  */
22694  #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos     (16UL)         /*!< TEXTUREFILTERX (Bit 16)                               */
22695  #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk     (0x10000UL)    /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01)                  */
22696  #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos      (15UL)         /*!< TEXTURECLAMPY (Bit 15)                                */
22697  #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk      (0x8000UL)     /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01)                   */
22698  #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos      (14UL)         /*!< TEXTURECLAMPX (Bit 14)                                */
22699  #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk      (0x4000UL)     /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01)                   */
22700  #define R_DRW_CONTROL2_BC2_Pos                (13UL)         /*!< BC2 (Bit 13)                                          */
22701  #define R_DRW_CONTROL2_BC2_Msk                (0x2000UL)     /*!< BC2 (Bitfield-Mask: 0x01)                             */
22702  #define R_DRW_CONTROL2_BDI_Pos                (12UL)         /*!< BDI (Bit 12)                                          */
22703  #define R_DRW_CONTROL2_BDI_Msk                (0x1000UL)     /*!< BDI (Bitfield-Mask: 0x01)                             */
22704  #define R_DRW_CONTROL2_BSI_Pos                (11UL)         /*!< BSI (Bit 11)                                          */
22705  #define R_DRW_CONTROL2_BSI_Msk                (0x800UL)      /*!< BSI (Bitfield-Mask: 0x01)                             */
22706  #define R_DRW_CONTROL2_BDF_Pos                (10UL)         /*!< BDF (Bit 10)                                          */
22707  #define R_DRW_CONTROL2_BDF_Msk                (0x400UL)      /*!< BDF (Bitfield-Mask: 0x01)                             */
22708  #define R_DRW_CONTROL2_BSF_Pos                (9UL)          /*!< BSF (Bit 9)                                           */
22709  #define R_DRW_CONTROL2_BSF_Msk                (0x200UL)      /*!< BSF (Bitfield-Mask: 0x01)                             */
22710  #define R_DRW_CONTROL2_WRITEFORMAT2_Pos       (8UL)          /*!< WRITEFORMAT2 (Bit 8)                                  */
22711  #define R_DRW_CONTROL2_WRITEFORMAT2_Msk       (0x100UL)      /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01)                    */
22712  #define R_DRW_CONTROL2_BDFA_Pos               (7UL)          /*!< BDFA (Bit 7)                                          */
22713  #define R_DRW_CONTROL2_BDFA_Msk               (0x80UL)       /*!< BDFA (Bitfield-Mask: 0x01)                            */
22714  #define R_DRW_CONTROL2_BSFA_Pos               (6UL)          /*!< BSFA (Bit 6)                                          */
22715  #define R_DRW_CONTROL2_BSFA_Msk               (0x40UL)       /*!< BSFA (Bitfield-Mask: 0x01)                            */
22716  #define R_DRW_CONTROL2_READFORMAT32_Pos       (4UL)          /*!< READFORMAT32 (Bit 4)                                  */
22717  #define R_DRW_CONTROL2_READFORMAT32_Msk       (0x30UL)       /*!< READFORMAT32 (Bitfield-Mask: 0x03)                    */
22718  #define R_DRW_CONTROL2_USEACB_Pos             (3UL)          /*!< USEACB (Bit 3)                                        */
22719  #define R_DRW_CONTROL2_USEACB_Msk             (0x8UL)        /*!< USEACB (Bitfield-Mask: 0x01)                          */
22720  #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos    (2UL)          /*!< PATTERNSOURCEL5 (Bit 2)                               */
22721  #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk    (0x4UL)        /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01)                 */
22722  #define R_DRW_CONTROL2_TEXTUREENABLE_Pos      (1UL)          /*!< TEXTUREENABLE (Bit 1)                                 */
22723  #define R_DRW_CONTROL2_TEXTUREENABLE_Msk      (0x2UL)        /*!< TEXTUREENABLE (Bitfield-Mask: 0x01)                   */
22724  #define R_DRW_CONTROL2_PATTERNENABLE_Pos      (0UL)          /*!< PATTERNENABLE (Bit 0)                                 */
22725  #define R_DRW_CONTROL2_PATTERNENABLE_Msk      (0x1UL)        /*!< PATTERNENABLE (Bitfield-Mask: 0x01)                   */
22726 /* ========================================================  IRQCTL  ========================================================= */
22727  #define R_DRW_IRQCTL_BUSIRQCLR_Pos            (5UL)          /*!< BUSIRQCLR (Bit 5)                                     */
22728  #define R_DRW_IRQCTL_BUSIRQCLR_Msk            (0x20UL)       /*!< BUSIRQCLR (Bitfield-Mask: 0x01)                       */
22729  #define R_DRW_IRQCTL_BUSIRQEN_Pos             (4UL)          /*!< BUSIRQEN (Bit 4)                                      */
22730  #define R_DRW_IRQCTL_BUSIRQEN_Msk             (0x10UL)       /*!< BUSIRQEN (Bitfield-Mask: 0x01)                        */
22731  #define R_DRW_IRQCTL_DLISTIRQCLR_Pos          (3UL)          /*!< DLISTIRQCLR (Bit 3)                                   */
22732  #define R_DRW_IRQCTL_DLISTIRQCLR_Msk          (0x8UL)        /*!< DLISTIRQCLR (Bitfield-Mask: 0x01)                     */
22733  #define R_DRW_IRQCTL_ENUMIRQCLR_Pos           (2UL)          /*!< ENUMIRQCLR (Bit 2)                                    */
22734  #define R_DRW_IRQCTL_ENUMIRQCLR_Msk           (0x4UL)        /*!< ENUMIRQCLR (Bitfield-Mask: 0x01)                      */
22735  #define R_DRW_IRQCTL_DLISTIRQEN_Pos           (1UL)          /*!< DLISTIRQEN (Bit 1)                                    */
22736  #define R_DRW_IRQCTL_DLISTIRQEN_Msk           (0x2UL)        /*!< DLISTIRQEN (Bitfield-Mask: 0x01)                      */
22737  #define R_DRW_IRQCTL_ENUMIRQEN_Pos            (0UL)          /*!< ENUMIRQEN (Bit 0)                                     */
22738  #define R_DRW_IRQCTL_ENUMIRQEN_Msk            (0x1UL)        /*!< ENUMIRQEN (Bitfield-Mask: 0x01)                       */
22739 /* =======================================================  CACHECTL  ======================================================== */
22740  #define R_DRW_CACHECTL_CFLUSHTX_Pos           (3UL)          /*!< CFLUSHTX (Bit 3)                                      */
22741  #define R_DRW_CACHECTL_CFLUSHTX_Msk           (0x8UL)        /*!< CFLUSHTX (Bitfield-Mask: 0x01)                        */
22742  #define R_DRW_CACHECTL_CENABLETX_Pos          (2UL)          /*!< CENABLETX (Bit 2)                                     */
22743  #define R_DRW_CACHECTL_CENABLETX_Msk          (0x4UL)        /*!< CENABLETX (Bitfield-Mask: 0x01)                       */
22744  #define R_DRW_CACHECTL_CFLUSHFX_Pos           (1UL)          /*!< CFLUSHFX (Bit 1)                                      */
22745  #define R_DRW_CACHECTL_CFLUSHFX_Msk           (0x2UL)        /*!< CFLUSHFX (Bitfield-Mask: 0x01)                        */
22746  #define R_DRW_CACHECTL_CENABLEFX_Pos          (0UL)          /*!< CENABLEFX (Bit 0)                                     */
22747  #define R_DRW_CACHECTL_CENABLEFX_Msk          (0x1UL)        /*!< CENABLEFX (Bitfield-Mask: 0x01)                       */
22748 /* ========================================================  STATUS  ========================================================= */
22749  #define R_DRW_STATUS_BUSERRMDL_Pos            (10UL)         /*!< BUSERRMDL (Bit 10)                                    */
22750  #define R_DRW_STATUS_BUSERRMDL_Msk            (0x400UL)      /*!< BUSERRMDL (Bitfield-Mask: 0x01)                       */
22751  #define R_DRW_STATUS_BUSERRMTXMRL_Pos         (9UL)          /*!< BUSERRMTXMRL (Bit 9)                                  */
22752  #define R_DRW_STATUS_BUSERRMTXMRL_Msk         (0x200UL)      /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01)                    */
22753  #define R_DRW_STATUS_BUSERRMFB_Pos            (8UL)          /*!< BUSERRMFB (Bit 8)                                     */
22754  #define R_DRW_STATUS_BUSERRMFB_Msk            (0x100UL)      /*!< BUSERRMFB (Bitfield-Mask: 0x01)                       */
22755  #define R_DRW_STATUS_BUSIRQ_Pos               (6UL)          /*!< BUSIRQ (Bit 6)                                        */
22756  #define R_DRW_STATUS_BUSIRQ_Msk               (0x40UL)       /*!< BUSIRQ (Bitfield-Mask: 0x01)                          */
22757  #define R_DRW_STATUS_DLISTIRQ_Pos             (5UL)          /*!< DLISTIRQ (Bit 5)                                      */
22758  #define R_DRW_STATUS_DLISTIRQ_Msk             (0x20UL)       /*!< DLISTIRQ (Bitfield-Mask: 0x01)                        */
22759  #define R_DRW_STATUS_ENUMIRQ_Pos              (4UL)          /*!< ENUMIRQ (Bit 4)                                       */
22760  #define R_DRW_STATUS_ENUMIRQ_Msk              (0x10UL)       /*!< ENUMIRQ (Bitfield-Mask: 0x01)                         */
22761  #define R_DRW_STATUS_DLISTACTIVE_Pos          (3UL)          /*!< DLISTACTIVE (Bit 3)                                   */
22762  #define R_DRW_STATUS_DLISTACTIVE_Msk          (0x8UL)        /*!< DLISTACTIVE (Bitfield-Mask: 0x01)                     */
22763  #define R_DRW_STATUS_CACHEDIRTY_Pos           (2UL)          /*!< CACHEDIRTY (Bit 2)                                    */
22764  #define R_DRW_STATUS_CACHEDIRTY_Msk           (0x4UL)        /*!< CACHEDIRTY (Bitfield-Mask: 0x01)                      */
22765  #define R_DRW_STATUS_BUSYWRITE_Pos            (1UL)          /*!< BUSYWRITE (Bit 1)                                     */
22766  #define R_DRW_STATUS_BUSYWRITE_Msk            (0x2UL)        /*!< BUSYWRITE (Bitfield-Mask: 0x01)                       */
22767  #define R_DRW_STATUS_BUSYENUM_Pos             (0UL)          /*!< BUSYENUM (Bit 0)                                      */
22768  #define R_DRW_STATUS_BUSYENUM_Msk             (0x1UL)        /*!< BUSYENUM (Bitfield-Mask: 0x01)                        */
22769 /* ======================================================  HWREVISION  ======================================================= */
22770  #define R_DRW_HWREVISION_ACBLEND_Pos          (27UL)         /*!< ACBLEND (Bit 27)                                      */
22771  #define R_DRW_HWREVISION_ACBLEND_Msk          (0x8000000UL)  /*!< ACBLEND (Bitfield-Mask: 0x01)                         */
22772  #define R_DRW_HWREVISION_COLORKEY_Pos         (25UL)         /*!< COLORKEY (Bit 25)                                     */
22773  #define R_DRW_HWREVISION_COLORKEY_Msk         (0x2000000UL)  /*!< COLORKEY (Bitfield-Mask: 0x01)                        */
22774  #define R_DRW_HWREVISION_TEXCLUT256_Pos       (24UL)         /*!< TEXCLUT256 (Bit 24)                                   */
22775  #define R_DRW_HWREVISION_TEXCLUT256_Msk       (0x1000000UL)  /*!< TEXCLUT256 (Bitfield-Mask: 0x01)                      */
22776  #define R_DRW_HWREVISION_RLEUNIT_Pos          (23UL)         /*!< RLEUNIT (Bit 23)                                      */
22777  #define R_DRW_HWREVISION_RLEUNIT_Msk          (0x800000UL)   /*!< RLEUNIT (Bitfield-Mask: 0x01)                         */
22778  #define R_DRW_HWREVISION_TEXCLU_Pos           (21UL)         /*!< TEXCLU (Bit 21)                                       */
22779  #define R_DRW_HWREVISION_TEXCLU_Msk           (0x200000UL)   /*!< TEXCLU (Bitfield-Mask: 0x01)                          */
22780  #define R_DRW_HWREVISION_PERFCOUNT_Pos        (20UL)         /*!< PERFCOUNT (Bit 20)                                    */
22781  #define R_DRW_HWREVISION_PERFCOUNT_Msk        (0x100000UL)   /*!< PERFCOUNT (Bitfield-Mask: 0x01)                       */
22782  #define R_DRW_HWREVISION_TXCACHE_Pos          (19UL)         /*!< TXCACHE (Bit 19)                                      */
22783  #define R_DRW_HWREVISION_TXCACHE_Msk          (0x80000UL)    /*!< TXCACHE (Bitfield-Mask: 0x01)                         */
22784  #define R_DRW_HWREVISION_FBCACHE_Pos          (18UL)         /*!< FBCACHE (Bit 18)                                      */
22785  #define R_DRW_HWREVISION_FBCACHE_Msk          (0x40000UL)    /*!< FBCACHE (Bitfield-Mask: 0x01)                         */
22786  #define R_DRW_HWREVISION_DLR_Pos              (17UL)         /*!< DLR (Bit 17)                                          */
22787  #define R_DRW_HWREVISION_DLR_Msk              (0x20000UL)    /*!< DLR (Bitfield-Mask: 0x01)                             */
22788  #define R_DRW_HWREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
22789  #define R_DRW_HWREVISION_REV_Msk              (0xfffUL)      /*!< REV (Bitfield-Mask: 0xfff)                            */
22790 /* ========================================================  COLOR1  ========================================================= */
22791  #define R_DRW_COLOR1_COLOR1A_Pos              (24UL)         /*!< COLOR1A (Bit 24)                                      */
22792  #define R_DRW_COLOR1_COLOR1A_Msk              (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff)                         */
22793  #define R_DRW_COLOR1_COLOR1R_Pos              (16UL)         /*!< COLOR1R (Bit 16)                                      */
22794  #define R_DRW_COLOR1_COLOR1R_Msk              (0xff0000UL)   /*!< COLOR1R (Bitfield-Mask: 0xff)                         */
22795  #define R_DRW_COLOR1_COLOR1G_Pos              (8UL)          /*!< COLOR1G (Bit 8)                                       */
22796  #define R_DRW_COLOR1_COLOR1G_Msk              (0xff00UL)     /*!< COLOR1G (Bitfield-Mask: 0xff)                         */
22797  #define R_DRW_COLOR1_COLOR1B_Pos              (0UL)          /*!< COLOR1B (Bit 0)                                       */
22798  #define R_DRW_COLOR1_COLOR1B_Msk              (0xffUL)       /*!< COLOR1B (Bitfield-Mask: 0xff)                         */
22799 /* ========================================================  COLOR2  ========================================================= */
22800  #define R_DRW_COLOR2_COLOR2A_Pos              (24UL)         /*!< COLOR2A (Bit 24)                                      */
22801  #define R_DRW_COLOR2_COLOR2A_Msk              (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff)                         */
22802  #define R_DRW_COLOR2_COLOR2R_Pos              (16UL)         /*!< COLOR2R (Bit 16)                                      */
22803  #define R_DRW_COLOR2_COLOR2R_Msk              (0xff0000UL)   /*!< COLOR2R (Bitfield-Mask: 0xff)                         */
22804  #define R_DRW_COLOR2_COLOR2G_Pos              (8UL)          /*!< COLOR2G (Bit 8)                                       */
22805  #define R_DRW_COLOR2_COLOR2G_Msk              (0xff00UL)     /*!< COLOR2G (Bitfield-Mask: 0xff)                         */
22806  #define R_DRW_COLOR2_COLOR2B_Pos              (0UL)          /*!< COLOR2B (Bit 0)                                       */
22807  #define R_DRW_COLOR2_COLOR2B_Msk              (0xffUL)       /*!< COLOR2B (Bitfield-Mask: 0xff)                         */
22808 /* ========================================================  PATTERN  ======================================================== */
22809  #define R_DRW_PATTERN_PATTERN_Pos             (0UL)          /*!< PATTERN (Bit 0)                                       */
22810  #define R_DRW_PATTERN_PATTERN_Msk             (0xffUL)       /*!< PATTERN (Bitfield-Mask: 0xff)                         */
22811 /* ========================================================  L1START  ======================================================== */
22812  #define R_DRW_L1START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
22813  #define R_DRW_L1START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
22814 /* ========================================================  L2START  ======================================================== */
22815  #define R_DRW_L2START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
22816  #define R_DRW_L2START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
22817 /* ========================================================  L3START  ======================================================== */
22818  #define R_DRW_L3START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
22819  #define R_DRW_L3START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
22820 /* ========================================================  L4START  ======================================================== */
22821  #define R_DRW_L4START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
22822  #define R_DRW_L4START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
22823 /* ========================================================  L5START  ======================================================== */
22824  #define R_DRW_L5START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
22825  #define R_DRW_L5START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
22826 /* ========================================================  L6START  ======================================================== */
22827  #define R_DRW_L6START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
22828  #define R_DRW_L6START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
22829 /* ========================================================  L1XADD  ========================================================= */
22830  #define R_DRW_L1XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
22831  #define R_DRW_L1XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
22832 /* ========================================================  L2XADD  ========================================================= */
22833  #define R_DRW_L2XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
22834  #define R_DRW_L2XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
22835 /* ========================================================  L3XADD  ========================================================= */
22836  #define R_DRW_L3XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
22837  #define R_DRW_L3XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
22838 /* ========================================================  L4XADD  ========================================================= */
22839  #define R_DRW_L4XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
22840  #define R_DRW_L4XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
22841 /* ========================================================  L5XADD  ========================================================= */
22842  #define R_DRW_L5XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
22843  #define R_DRW_L5XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
22844 /* ========================================================  L6XADD  ========================================================= */
22845  #define R_DRW_L6XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
22846  #define R_DRW_L6XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
22847 /* ========================================================  L1YADD  ========================================================= */
22848  #define R_DRW_L1YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
22849  #define R_DRW_L1YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
22850 /* ========================================================  L2YADD  ========================================================= */
22851  #define R_DRW_L2YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
22852  #define R_DRW_L2YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
22853 /* ========================================================  L3YADD  ========================================================= */
22854  #define R_DRW_L3YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
22855  #define R_DRW_L3YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
22856 /* ========================================================  L4YADD  ========================================================= */
22857  #define R_DRW_L4YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
22858  #define R_DRW_L4YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
22859 /* ========================================================  L5YADD  ========================================================= */
22860  #define R_DRW_L5YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
22861  #define R_DRW_L5YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
22862 /* ========================================================  L6YADD  ========================================================= */
22863  #define R_DRW_L6YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
22864  #define R_DRW_L6YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
22865 /* ========================================================  L1BAND  ========================================================= */
22866  #define R_DRW_L1BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
22867  #define R_DRW_L1BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
22868 /* ========================================================  L2BAND  ========================================================= */
22869  #define R_DRW_L2BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
22870  #define R_DRW_L2BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
22871 /* =======================================================  TEXORIGIN  ======================================================= */
22872  #define R_DRW_TEXORIGIN_TEXORIGIN_Pos         (0UL)          /*!< TEXORIGIN (Bit 0)                                     */
22873  #define R_DRW_TEXORIGIN_TEXORIGIN_Msk         (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff)                 */
22874 /* =======================================================  TEXPITCH  ======================================================== */
22875  #define R_DRW_TEXPITCH_TEXPITCH_Pos           (0UL)          /*!< TEXPITCH (Bit 0)                                      */
22876  #define R_DRW_TEXPITCH_TEXPITCH_Msk           (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff)                  */
22877 /* ========================================================  TEXMASK  ======================================================== */
22878  #define R_DRW_TEXMASK_TEXVMASK_Pos            (11UL)         /*!< TEXVMASK (Bit 11)                                     */
22879  #define R_DRW_TEXMASK_TEXVMASK_Msk            (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff)                    */
22880  #define R_DRW_TEXMASK_TEXUMASK_Pos            (0UL)          /*!< TEXUMASK (Bit 0)                                      */
22881  #define R_DRW_TEXMASK_TEXUMASK_Msk            (0x7ffUL)      /*!< TEXUMASK (Bitfield-Mask: 0x7ff)                       */
22882 /* ========================================================  LUSTART  ======================================================== */
22883  #define R_DRW_LUSTART_LUSTART_Pos             (0UL)          /*!< LUSTART (Bit 0)                                       */
22884  #define R_DRW_LUSTART_LUSTART_Msk             (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff)                   */
22885 /* ========================================================  LUXADD  ========================================================= */
22886  #define R_DRW_LUXADD_LUXADD_Pos               (0UL)          /*!< LUXADD (Bit 0)                                        */
22887  #define R_DRW_LUXADD_LUXADD_Msk               (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff)                    */
22888 /* ========================================================  LUYADD  ========================================================= */
22889  #define R_DRW_LUYADD_LUYADD_Pos               (0UL)          /*!< LUYADD (Bit 0)                                        */
22890  #define R_DRW_LUYADD_LUYADD_Msk               (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff)                    */
22891 /* =======================================================  LVSTARTI  ======================================================== */
22892  #define R_DRW_LVSTARTI_LVSTARTI_Pos           (0UL)          /*!< LVSTARTI (Bit 0)                                      */
22893  #define R_DRW_LVSTARTI_LVSTARTI_Msk           (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff)                  */
22894 /* =======================================================  LVSTARTF  ======================================================== */
22895  #define R_DRW_LVSTARTF_LVSTARTF_Pos           (0UL)          /*!< LVSTARTF (Bit 0)                                      */
22896  #define R_DRW_LVSTARTF_LVSTARTF_Msk           (0xffffUL)     /*!< LVSTARTF (Bitfield-Mask: 0xffff)                      */
22897 /* ========================================================  LVXADDI  ======================================================== */
22898  #define R_DRW_LVXADDI_LVXADDI_Pos             (0UL)          /*!< LVXADDI (Bit 0)                                       */
22899  #define R_DRW_LVXADDI_LVXADDI_Msk             (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff)                   */
22900 /* ========================================================  LVYADDI  ======================================================== */
22901  #define R_DRW_LVYADDI_LVYADDI_Pos             (0UL)          /*!< LVYADDI (Bit 0)                                       */
22902  #define R_DRW_LVYADDI_LVYADDI_Msk             (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff)                   */
22903 /* =======================================================  LVYXADDF  ======================================================== */
22904  #define R_DRW_LVYXADDF_LVYADDF_Pos            (16UL)         /*!< LVYADDF (Bit 16)                                      */
22905  #define R_DRW_LVYXADDF_LVYADDF_Msk            (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff)                       */
22906  #define R_DRW_LVYXADDF_LVXADDF_Pos            (0UL)          /*!< LVXADDF (Bit 0)                                       */
22907  #define R_DRW_LVYXADDF_LVXADDF_Msk            (0xffffUL)     /*!< LVXADDF (Bitfield-Mask: 0xffff)                       */
22908 /* =======================================================  TEXCLADDR  ======================================================= */
22909  #define R_DRW_TEXCLADDR_CLADDR_Pos            (0UL)          /*!< CLADDR (Bit 0)                                        */
22910  #define R_DRW_TEXCLADDR_CLADDR_Msk            (0xffUL)       /*!< CLADDR (Bitfield-Mask: 0xff)                          */
22911 /* =======================================================  TEXCLDATA  ======================================================= */
22912  #define R_DRW_TEXCLDATA_CLDATA_Pos            (0UL)          /*!< CLDATA (Bit 0)                                        */
22913  #define R_DRW_TEXCLDATA_CLDATA_Msk            (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff)                    */
22914 /* ======================================================  TEXCLOFFSET  ====================================================== */
22915  #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos        (0UL)          /*!< CLOFFSET (Bit 0)                                      */
22916  #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk        (0xffUL)       /*!< CLOFFSET (Bitfield-Mask: 0xff)                        */
22917 /* ========================================================  COLKEY  ========================================================= */
22918  #define R_DRW_COLKEY_COLKEYR_Pos              (16UL)         /*!< COLKEYR (Bit 16)                                      */
22919  #define R_DRW_COLKEY_COLKEYR_Msk              (0xff0000UL)   /*!< COLKEYR (Bitfield-Mask: 0xff)                         */
22920  #define R_DRW_COLKEY_COLKEYG_Pos              (8UL)          /*!< COLKEYG (Bit 8)                                       */
22921  #define R_DRW_COLKEY_COLKEYG_Msk              (0xff00UL)     /*!< COLKEYG (Bitfield-Mask: 0xff)                         */
22922  #define R_DRW_COLKEY_COLKEYB_Pos              (0UL)          /*!< COLKEYB (Bit 0)                                       */
22923  #define R_DRW_COLKEY_COLKEYB_Msk              (0xffUL)       /*!< COLKEYB (Bitfield-Mask: 0xff)                         */
22924 /* =========================================================  SIZE  ========================================================== */
22925  #define R_DRW_SIZE_SIZEY_Pos                  (16UL)         /*!< SIZEY (Bit 16)                                        */
22926  #define R_DRW_SIZE_SIZEY_Msk                  (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff)                         */
22927  #define R_DRW_SIZE_SIZEX_Pos                  (0UL)          /*!< SIZEX (Bit 0)                                         */
22928  #define R_DRW_SIZE_SIZEX_Msk                  (0xffffUL)     /*!< SIZEX (Bitfield-Mask: 0xffff)                         */
22929 /* =========================================================  PITCH  ========================================================= */
22930  #define R_DRW_PITCH_SSD_Pos                   (16UL)         /*!< SSD (Bit 16)                                          */
22931  #define R_DRW_PITCH_SSD_Msk                   (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff)                           */
22932  #define R_DRW_PITCH_PITCH_Pos                 (0UL)          /*!< PITCH (Bit 0)                                         */
22933  #define R_DRW_PITCH_PITCH_Msk                 (0xffffUL)     /*!< PITCH (Bitfield-Mask: 0xffff)                         */
22934 /* ========================================================  ORIGIN  ========================================================= */
22935  #define R_DRW_ORIGIN_ORIGIN_Pos               (0UL)          /*!< ORIGIN (Bit 0)                                        */
22936  #define R_DRW_ORIGIN_ORIGIN_Msk               (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff)                    */
22937 /* ======================================================  DLISTSTART  ======================================================= */
22938  #define R_DRW_DLISTSTART_DLISTSTART_Pos       (0UL)          /*!< DLISTSTART (Bit 0)                                    */
22939  #define R_DRW_DLISTSTART_DLISTSTART_Msk       (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff)                */
22940 /* ======================================================  PERFTRIGGER  ====================================================== */
22941  #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos    (16UL)         /*!< PERFTRIGGER2 (Bit 16)                                 */
22942  #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk    (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff)                  */
22943  #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos    (0UL)          /*!< PERFTRIGGER1 (Bit 0)                                  */
22944  #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk    (0xffffUL)     /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff)                  */
22945 /* ======================================================  PERFCOUNT1  ======================================================= */
22946  #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
22947  #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
22948 /* ======================================================  PERFCOUNT2  ======================================================= */
22949  #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
22950  #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
22951 
22952 /* =========================================================================================================================== */
22953 /* ================                                           R_DTC                                           ================ */
22954 /* =========================================================================================================================== */
22955 
22956 /* =========================================================  DTCCR  ========================================================= */
22957  #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
22958  #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
22959 /* ========================================================  DTCVBR  ========================================================= */
22960  #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
22961  #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
22962 /* =========================================================  DTCST  ========================================================= */
22963  #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
22964  #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
22965 /* ========================================================  DTCSTS  ========================================================= */
22966  #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
22967  #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
22968  #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
22969  #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
22970 /* =======================================================  DTCCR_SEC  ======================================================= */
22971  #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
22972  #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
22973 /* ======================================================  DTCVBR_SEC  ======================================================= */
22974 /* =========================================================  DTEVR  ========================================================= */
22975  #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
22976  #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
22977  #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
22978  #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
22979  #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
22980  #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
22981 
22982 /* =========================================================================================================================== */
22983 /* ================                                           R_ELC                                           ================ */
22984 /* =========================================================================================================================== */
22985 
22986 /* =========================================================  ELCR  ========================================================== */
22987  #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
22988  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
22989 /* ========================================================  ELCSARA  ======================================================== */
22990  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
22991  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
22992  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
22993  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
22994  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
22995  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
22996 /* ========================================================  ELCSARB  ======================================================== */
22997  #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
22998  #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
22999  #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
23000  #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
23001  #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
23002  #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
23003  #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
23004  #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
23005  #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
23006  #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
23007  #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
23008  #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
23009  #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
23010  #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
23011  #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
23012  #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
23013  #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
23014  #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
23015  #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
23016  #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
23017  #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
23018  #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
23019  #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
23020  #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
23021  #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
23022  #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
23023  #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
23024  #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
23025  #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
23026  #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
23027  #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
23028  #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
23029 /* ========================================================  ELCSARC  ======================================================== */
23030  #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
23031  #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
23032  #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
23033  #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
23034  #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
23035  #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
23036 
23037 /* =========================================================================================================================== */
23038 /* ================                                         R_ETHERC0                                         ================ */
23039 /* =========================================================================================================================== */
23040 
23041 /* =========================================================  ECMR  ========================================================== */
23042  #define R_ETHERC0_ECMR_TPC_Pos          (20UL)         /*!< TPC (Bit 20)                                          */
23043  #define R_ETHERC0_ECMR_TPC_Msk          (0x100000UL)   /*!< TPC (Bitfield-Mask: 0x01)                             */
23044  #define R_ETHERC0_ECMR_ZPF_Pos          (19UL)         /*!< ZPF (Bit 19)                                          */
23045  #define R_ETHERC0_ECMR_ZPF_Msk          (0x80000UL)    /*!< ZPF (Bitfield-Mask: 0x01)                             */
23046  #define R_ETHERC0_ECMR_PFR_Pos          (18UL)         /*!< PFR (Bit 18)                                          */
23047  #define R_ETHERC0_ECMR_PFR_Msk          (0x40000UL)    /*!< PFR (Bitfield-Mask: 0x01)                             */
23048  #define R_ETHERC0_ECMR_RXF_Pos          (17UL)         /*!< RXF (Bit 17)                                          */
23049  #define R_ETHERC0_ECMR_RXF_Msk          (0x20000UL)    /*!< RXF (Bitfield-Mask: 0x01)                             */
23050  #define R_ETHERC0_ECMR_TXF_Pos          (16UL)         /*!< TXF (Bit 16)                                          */
23051  #define R_ETHERC0_ECMR_TXF_Msk          (0x10000UL)    /*!< TXF (Bitfield-Mask: 0x01)                             */
23052  #define R_ETHERC0_ECMR_PRCEF_Pos        (12UL)         /*!< PRCEF (Bit 12)                                        */
23053  #define R_ETHERC0_ECMR_PRCEF_Msk        (0x1000UL)     /*!< PRCEF (Bitfield-Mask: 0x01)                           */
23054  #define R_ETHERC0_ECMR_MPDE_Pos         (9UL)          /*!< MPDE (Bit 9)                                          */
23055  #define R_ETHERC0_ECMR_MPDE_Msk         (0x200UL)      /*!< MPDE (Bitfield-Mask: 0x01)                            */
23056  #define R_ETHERC0_ECMR_RE_Pos           (6UL)          /*!< RE (Bit 6)                                            */
23057  #define R_ETHERC0_ECMR_RE_Msk           (0x40UL)       /*!< RE (Bitfield-Mask: 0x01)                              */
23058  #define R_ETHERC0_ECMR_TE_Pos           (5UL)          /*!< TE (Bit 5)                                            */
23059  #define R_ETHERC0_ECMR_TE_Msk           (0x20UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
23060  #define R_ETHERC0_ECMR_ILB_Pos          (3UL)          /*!< ILB (Bit 3)                                           */
23061  #define R_ETHERC0_ECMR_ILB_Msk          (0x8UL)        /*!< ILB (Bitfield-Mask: 0x01)                             */
23062  #define R_ETHERC0_ECMR_RTM_Pos          (2UL)          /*!< RTM (Bit 2)                                           */
23063  #define R_ETHERC0_ECMR_RTM_Msk          (0x4UL)        /*!< RTM (Bitfield-Mask: 0x01)                             */
23064  #define R_ETHERC0_ECMR_DM_Pos           (1UL)          /*!< DM (Bit 1)                                            */
23065  #define R_ETHERC0_ECMR_DM_Msk           (0x2UL)        /*!< DM (Bitfield-Mask: 0x01)                              */
23066  #define R_ETHERC0_ECMR_PRM_Pos          (0UL)          /*!< PRM (Bit 0)                                           */
23067  #define R_ETHERC0_ECMR_PRM_Msk          (0x1UL)        /*!< PRM (Bitfield-Mask: 0x01)                             */
23068 /* =========================================================  RFLR  ========================================================== */
23069  #define R_ETHERC0_RFLR_RFL_Pos          (0UL)          /*!< RFL (Bit 0)                                           */
23070  #define R_ETHERC0_RFLR_RFL_Msk          (0xfffUL)      /*!< RFL (Bitfield-Mask: 0xfff)                            */
23071 /* =========================================================  ECSR  ========================================================== */
23072  #define R_ETHERC0_ECSR_BFR_Pos          (5UL)          /*!< BFR (Bit 5)                                           */
23073  #define R_ETHERC0_ECSR_BFR_Msk          (0x20UL)       /*!< BFR (Bitfield-Mask: 0x01)                             */
23074  #define R_ETHERC0_ECSR_PSRTO_Pos        (4UL)          /*!< PSRTO (Bit 4)                                         */
23075  #define R_ETHERC0_ECSR_PSRTO_Msk        (0x10UL)       /*!< PSRTO (Bitfield-Mask: 0x01)                           */
23076  #define R_ETHERC0_ECSR_LCHNG_Pos        (2UL)          /*!< LCHNG (Bit 2)                                         */
23077  #define R_ETHERC0_ECSR_LCHNG_Msk        (0x4UL)        /*!< LCHNG (Bitfield-Mask: 0x01)                           */
23078  #define R_ETHERC0_ECSR_MPD_Pos          (1UL)          /*!< MPD (Bit 1)                                           */
23079  #define R_ETHERC0_ECSR_MPD_Msk          (0x2UL)        /*!< MPD (Bitfield-Mask: 0x01)                             */
23080  #define R_ETHERC0_ECSR_ICD_Pos          (0UL)          /*!< ICD (Bit 0)                                           */
23081  #define R_ETHERC0_ECSR_ICD_Msk          (0x1UL)        /*!< ICD (Bitfield-Mask: 0x01)                             */
23082 /* ========================================================  ECSIPR  ========================================================= */
23083  #define R_ETHERC0_ECSIPR_BFSIPR_Pos     (5UL)          /*!< BFSIPR (Bit 5)                                        */
23084  #define R_ETHERC0_ECSIPR_BFSIPR_Msk     (0x20UL)       /*!< BFSIPR (Bitfield-Mask: 0x01)                          */
23085  #define R_ETHERC0_ECSIPR_PSRTOIP_Pos    (4UL)          /*!< PSRTOIP (Bit 4)                                       */
23086  #define R_ETHERC0_ECSIPR_PSRTOIP_Msk    (0x10UL)       /*!< PSRTOIP (Bitfield-Mask: 0x01)                         */
23087  #define R_ETHERC0_ECSIPR_LCHNGIP_Pos    (2UL)          /*!< LCHNGIP (Bit 2)                                       */
23088  #define R_ETHERC0_ECSIPR_LCHNGIP_Msk    (0x4UL)        /*!< LCHNGIP (Bitfield-Mask: 0x01)                         */
23089  #define R_ETHERC0_ECSIPR_MPDIP_Pos      (1UL)          /*!< MPDIP (Bit 1)                                         */
23090  #define R_ETHERC0_ECSIPR_MPDIP_Msk      (0x2UL)        /*!< MPDIP (Bitfield-Mask: 0x01)                           */
23091  #define R_ETHERC0_ECSIPR_ICDIP_Pos      (0UL)          /*!< ICDIP (Bit 0)                                         */
23092  #define R_ETHERC0_ECSIPR_ICDIP_Msk      (0x1UL)        /*!< ICDIP (Bitfield-Mask: 0x01)                           */
23093 /* ==========================================================  PIR  ========================================================== */
23094  #define R_ETHERC0_PIR_MDI_Pos           (3UL)          /*!< MDI (Bit 3)                                           */
23095  #define R_ETHERC0_PIR_MDI_Msk           (0x8UL)        /*!< MDI (Bitfield-Mask: 0x01)                             */
23096  #define R_ETHERC0_PIR_MDO_Pos           (2UL)          /*!< MDO (Bit 2)                                           */
23097  #define R_ETHERC0_PIR_MDO_Msk           (0x4UL)        /*!< MDO (Bitfield-Mask: 0x01)                             */
23098  #define R_ETHERC0_PIR_MMD_Pos           (1UL)          /*!< MMD (Bit 1)                                           */
23099  #define R_ETHERC0_PIR_MMD_Msk           (0x2UL)        /*!< MMD (Bitfield-Mask: 0x01)                             */
23100  #define R_ETHERC0_PIR_MDC_Pos           (0UL)          /*!< MDC (Bit 0)                                           */
23101  #define R_ETHERC0_PIR_MDC_Msk           (0x1UL)        /*!< MDC (Bitfield-Mask: 0x01)                             */
23102 /* ==========================================================  PSR  ========================================================== */
23103  #define R_ETHERC0_PSR_LMON_Pos          (0UL)          /*!< LMON (Bit 0)                                          */
23104  #define R_ETHERC0_PSR_LMON_Msk          (0x1UL)        /*!< LMON (Bitfield-Mask: 0x01)                            */
23105 /* =========================================================  RDMLR  ========================================================= */
23106  #define R_ETHERC0_RDMLR_RMD_Pos         (0UL)          /*!< RMD (Bit 0)                                           */
23107  #define R_ETHERC0_RDMLR_RMD_Msk         (0xfffffUL)    /*!< RMD (Bitfield-Mask: 0xfffff)                          */
23108 /* =========================================================  IPGR  ========================================================== */
23109  #define R_ETHERC0_IPGR_IPG_Pos          (0UL)          /*!< IPG (Bit 0)                                           */
23110  #define R_ETHERC0_IPGR_IPG_Msk          (0x1fUL)       /*!< IPG (Bitfield-Mask: 0x1f)                             */
23111 /* ==========================================================  APR  ========================================================== */
23112  #define R_ETHERC0_APR_AP_Pos            (0UL)          /*!< AP (Bit 0)                                            */
23113  #define R_ETHERC0_APR_AP_Msk            (0xffffUL)     /*!< AP (Bitfield-Mask: 0xffff)                            */
23114 /* ==========================================================  MPR  ========================================================== */
23115  #define R_ETHERC0_MPR_MP_Pos            (0UL)          /*!< MP (Bit 0)                                            */
23116  #define R_ETHERC0_MPR_MP_Msk            (0xffffUL)     /*!< MP (Bitfield-Mask: 0xffff)                            */
23117 /* =========================================================  RFCF  ========================================================== */
23118  #define R_ETHERC0_RFCF_RPAUSE_Pos       (0UL)          /*!< RPAUSE (Bit 0)                                        */
23119  #define R_ETHERC0_RFCF_RPAUSE_Msk       (0xffUL)       /*!< RPAUSE (Bitfield-Mask: 0xff)                          */
23120 /* ========================================================  TPAUSER  ======================================================== */
23121  #define R_ETHERC0_TPAUSER_TPAUSE_Pos    (0UL)          /*!< TPAUSE (Bit 0)                                        */
23122  #define R_ETHERC0_TPAUSER_TPAUSE_Msk    (0xffffUL)     /*!< TPAUSE (Bitfield-Mask: 0xffff)                        */
23123 /* =======================================================  TPAUSECR  ======================================================== */
23124 /* =========================================================  BCFRR  ========================================================= */
23125  #define R_ETHERC0_BCFRR_BCF_Pos         (0UL)          /*!< BCF (Bit 0)                                           */
23126  #define R_ETHERC0_BCFRR_BCF_Msk         (0xffffUL)     /*!< BCF (Bitfield-Mask: 0xffff)                           */
23127 /* =========================================================  MAHR  ========================================================== */
23128  #define R_ETHERC0_MAHR_MAHR_Pos         (0UL)          /*!< MAHR (Bit 0)                                          */
23129  #define R_ETHERC0_MAHR_MAHR_Msk         (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff)                      */
23130 /* =========================================================  MALR  ========================================================== */
23131  #define R_ETHERC0_MALR_MALR_Pos         (0UL)          /*!< MALR (Bit 0)                                          */
23132  #define R_ETHERC0_MALR_MALR_Msk         (0xffffUL)     /*!< MALR (Bitfield-Mask: 0xffff)                          */
23133 /* =========================================================  TROCR  ========================================================= */
23134  #define R_ETHERC0_TROCR_TROCR_Pos       (0UL)          /*!< TROCR (Bit 0)                                         */
23135  #define R_ETHERC0_TROCR_TROCR_Msk       (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff)                     */
23136 /* =========================================================  CDCR  ========================================================== */
23137 /* =========================================================  LCCR  ========================================================== */
23138  #define R_ETHERC0_LCCR_LCCR_Pos         (0UL)          /*!< LCCR (Bit 0)                                          */
23139  #define R_ETHERC0_LCCR_LCCR_Msk         (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff)                      */
23140 /* =========================================================  CNDCR  ========================================================= */
23141  #define R_ETHERC0_CNDCR_CNDCR_Pos       (0UL)          /*!< CNDCR (Bit 0)                                         */
23142  #define R_ETHERC0_CNDCR_CNDCR_Msk       (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff)                     */
23143 /* =========================================================  CEFCR  ========================================================= */
23144  #define R_ETHERC0_CEFCR_CEFCR_Pos       (0UL)          /*!< CEFCR (Bit 0)                                         */
23145  #define R_ETHERC0_CEFCR_CEFCR_Msk       (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff)                     */
23146 /* =========================================================  FRECR  ========================================================= */
23147  #define R_ETHERC0_FRECR_FRECR_Pos       (0UL)          /*!< FRECR (Bit 0)                                         */
23148  #define R_ETHERC0_FRECR_FRECR_Msk       (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff)                     */
23149 /* ========================================================  TSFRCR  ========================================================= */
23150  #define R_ETHERC0_TSFRCR_TSFRCR_Pos     (0UL)          /*!< TSFRCR (Bit 0)                                        */
23151  #define R_ETHERC0_TSFRCR_TSFRCR_Msk     (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff)                    */
23152 /* ========================================================  TLFRCR  ========================================================= */
23153  #define R_ETHERC0_TLFRCR_TLFRCR_Pos     (0UL)          /*!< TLFRCR (Bit 0)                                        */
23154  #define R_ETHERC0_TLFRCR_TLFRCR_Msk     (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff)                    */
23155 /* =========================================================  RFCR  ========================================================== */
23156  #define R_ETHERC0_RFCR_RFCR_Pos         (0UL)          /*!< RFCR (Bit 0)                                          */
23157  #define R_ETHERC0_RFCR_RFCR_Msk         (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff)                      */
23158 /* =========================================================  MAFCR  ========================================================= */
23159  #define R_ETHERC0_MAFCR_MAFCR_Pos       (0UL)          /*!< MAFCR (Bit 0)                                         */
23160  #define R_ETHERC0_MAFCR_MAFCR_Msk       (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff)                     */
23161 
23162 /* =========================================================================================================================== */
23163 /* ================                                      R_ETHERC_EDMAC                                       ================ */
23164 /* =========================================================================================================================== */
23165 
23166 /* =========================================================  EDMR  ========================================================== */
23167  #define R_ETHERC_EDMAC_EDMR_DE_Pos           (6UL)          /*!< DE (Bit 6)                                            */
23168  #define R_ETHERC_EDMAC_EDMR_DE_Msk           (0x40UL)       /*!< DE (Bitfield-Mask: 0x01)                              */
23169  #define R_ETHERC_EDMAC_EDMR_DL_Pos           (4UL)          /*!< DL (Bit 4)                                            */
23170  #define R_ETHERC_EDMAC_EDMR_DL_Msk           (0x30UL)       /*!< DL (Bitfield-Mask: 0x03)                              */
23171  #define R_ETHERC_EDMAC_EDMR_SWR_Pos          (0UL)          /*!< SWR (Bit 0)                                           */
23172  #define R_ETHERC_EDMAC_EDMR_SWR_Msk          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
23173 /* =========================================================  EDTRR  ========================================================= */
23174  #define R_ETHERC_EDMAC_EDTRR_TR_Pos          (0UL)          /*!< TR (Bit 0)                                            */
23175  #define R_ETHERC_EDMAC_EDTRR_TR_Msk          (0x1UL)        /*!< TR (Bitfield-Mask: 0x01)                              */
23176 /* =========================================================  EDRRR  ========================================================= */
23177  #define R_ETHERC_EDMAC_EDRRR_RR_Pos          (0UL)          /*!< RR (Bit 0)                                            */
23178  #define R_ETHERC_EDMAC_EDRRR_RR_Msk          (0x1UL)        /*!< RR (Bitfield-Mask: 0x01)                              */
23179 /* =========================================================  TDLAR  ========================================================= */
23180  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos       (0UL)          /*!< TDLAR (Bit 0)                                         */
23181  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk       (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff)                     */
23182 /* =========================================================  RDLAR  ========================================================= */
23183  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos       (0UL)          /*!< RDLAR (Bit 0)                                         */
23184  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk       (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff)                     */
23185 /* =========================================================  EESR  ========================================================== */
23186  #define R_ETHERC_EDMAC_EESR_TWB_Pos          (30UL)         /*!< TWB (Bit 30)                                          */
23187  #define R_ETHERC_EDMAC_EESR_TWB_Msk          (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01)                             */
23188  #define R_ETHERC_EDMAC_EESR_TABT_Pos         (26UL)         /*!< TABT (Bit 26)                                         */
23189  #define R_ETHERC_EDMAC_EESR_TABT_Msk         (0x4000000UL)  /*!< TABT (Bitfield-Mask: 0x01)                            */
23190  #define R_ETHERC_EDMAC_EESR_RABT_Pos         (25UL)         /*!< RABT (Bit 25)                                         */
23191  #define R_ETHERC_EDMAC_EESR_RABT_Msk         (0x2000000UL)  /*!< RABT (Bitfield-Mask: 0x01)                            */
23192  #define R_ETHERC_EDMAC_EESR_RFCOF_Pos        (24UL)         /*!< RFCOF (Bit 24)                                        */
23193  #define R_ETHERC_EDMAC_EESR_RFCOF_Msk        (0x1000000UL)  /*!< RFCOF (Bitfield-Mask: 0x01)                           */
23194  #define R_ETHERC_EDMAC_EESR_ADE_Pos          (23UL)         /*!< ADE (Bit 23)                                          */
23195  #define R_ETHERC_EDMAC_EESR_ADE_Msk          (0x800000UL)   /*!< ADE (Bitfield-Mask: 0x01)                             */
23196  #define R_ETHERC_EDMAC_EESR_ECI_Pos          (22UL)         /*!< ECI (Bit 22)                                          */
23197  #define R_ETHERC_EDMAC_EESR_ECI_Msk          (0x400000UL)   /*!< ECI (Bitfield-Mask: 0x01)                             */
23198  #define R_ETHERC_EDMAC_EESR_TC_Pos           (21UL)         /*!< TC (Bit 21)                                           */
23199  #define R_ETHERC_EDMAC_EESR_TC_Msk           (0x200000UL)   /*!< TC (Bitfield-Mask: 0x01)                              */
23200  #define R_ETHERC_EDMAC_EESR_TDE_Pos          (20UL)         /*!< TDE (Bit 20)                                          */
23201  #define R_ETHERC_EDMAC_EESR_TDE_Msk          (0x100000UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
23202  #define R_ETHERC_EDMAC_EESR_TFUF_Pos         (19UL)         /*!< TFUF (Bit 19)                                         */
23203  #define R_ETHERC_EDMAC_EESR_TFUF_Msk         (0x80000UL)    /*!< TFUF (Bitfield-Mask: 0x01)                            */
23204  #define R_ETHERC_EDMAC_EESR_FR_Pos           (18UL)         /*!< FR (Bit 18)                                           */
23205  #define R_ETHERC_EDMAC_EESR_FR_Msk           (0x40000UL)    /*!< FR (Bitfield-Mask: 0x01)                              */
23206  #define R_ETHERC_EDMAC_EESR_RDE_Pos          (17UL)         /*!< RDE (Bit 17)                                          */
23207  #define R_ETHERC_EDMAC_EESR_RDE_Msk          (0x20000UL)    /*!< RDE (Bitfield-Mask: 0x01)                             */
23208  #define R_ETHERC_EDMAC_EESR_RFOF_Pos         (16UL)         /*!< RFOF (Bit 16)                                         */
23209  #define R_ETHERC_EDMAC_EESR_RFOF_Msk         (0x10000UL)    /*!< RFOF (Bitfield-Mask: 0x01)                            */
23210  #define R_ETHERC_EDMAC_EESR_CND_Pos          (11UL)         /*!< CND (Bit 11)                                          */
23211  #define R_ETHERC_EDMAC_EESR_CND_Msk          (0x800UL)      /*!< CND (Bitfield-Mask: 0x01)                             */
23212  #define R_ETHERC_EDMAC_EESR_DLC_Pos          (10UL)         /*!< DLC (Bit 10)                                          */
23213  #define R_ETHERC_EDMAC_EESR_DLC_Msk          (0x400UL)      /*!< DLC (Bitfield-Mask: 0x01)                             */
23214  #define R_ETHERC_EDMAC_EESR_CD_Pos           (9UL)          /*!< CD (Bit 9)                                            */
23215  #define R_ETHERC_EDMAC_EESR_CD_Msk           (0x200UL)      /*!< CD (Bitfield-Mask: 0x01)                              */
23216  #define R_ETHERC_EDMAC_EESR_TRO_Pos          (8UL)          /*!< TRO (Bit 8)                                           */
23217  #define R_ETHERC_EDMAC_EESR_TRO_Msk          (0x100UL)      /*!< TRO (Bitfield-Mask: 0x01)                             */
23218  #define R_ETHERC_EDMAC_EESR_RMAF_Pos         (7UL)          /*!< RMAF (Bit 7)                                          */
23219  #define R_ETHERC_EDMAC_EESR_RMAF_Msk         (0x80UL)       /*!< RMAF (Bitfield-Mask: 0x01)                            */
23220  #define R_ETHERC_EDMAC_EESR_RRF_Pos          (4UL)          /*!< RRF (Bit 4)                                           */
23221  #define R_ETHERC_EDMAC_EESR_RRF_Msk          (0x10UL)       /*!< RRF (Bitfield-Mask: 0x01)                             */
23222  #define R_ETHERC_EDMAC_EESR_RTLF_Pos         (3UL)          /*!< RTLF (Bit 3)                                          */
23223  #define R_ETHERC_EDMAC_EESR_RTLF_Msk         (0x8UL)        /*!< RTLF (Bitfield-Mask: 0x01)                            */
23224  #define R_ETHERC_EDMAC_EESR_RTSF_Pos         (2UL)          /*!< RTSF (Bit 2)                                          */
23225  #define R_ETHERC_EDMAC_EESR_RTSF_Msk         (0x4UL)        /*!< RTSF (Bitfield-Mask: 0x01)                            */
23226  #define R_ETHERC_EDMAC_EESR_PRE_Pos          (1UL)          /*!< PRE (Bit 1)                                           */
23227  #define R_ETHERC_EDMAC_EESR_PRE_Msk          (0x2UL)        /*!< PRE (Bitfield-Mask: 0x01)                             */
23228  #define R_ETHERC_EDMAC_EESR_CERF_Pos         (0UL)          /*!< CERF (Bit 0)                                          */
23229  #define R_ETHERC_EDMAC_EESR_CERF_Msk         (0x1UL)        /*!< CERF (Bitfield-Mask: 0x01)                            */
23230 /* ========================================================  EESIPR  ========================================================= */
23231  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos      (30UL)         /*!< TWBIP (Bit 30)                                        */
23232  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk      (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01)                           */
23233  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos     (26UL)         /*!< TABTIP (Bit 26)                                       */
23234  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk     (0x4000000UL)  /*!< TABTIP (Bitfield-Mask: 0x01)                          */
23235  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos     (25UL)         /*!< RABTIP (Bit 25)                                       */
23236  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk     (0x2000000UL)  /*!< RABTIP (Bitfield-Mask: 0x01)                          */
23237  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos    (24UL)         /*!< RFCOFIP (Bit 24)                                      */
23238  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk    (0x1000000UL)  /*!< RFCOFIP (Bitfield-Mask: 0x01)                         */
23239  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos      (23UL)         /*!< ADEIP (Bit 23)                                        */
23240  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk      (0x800000UL)   /*!< ADEIP (Bitfield-Mask: 0x01)                           */
23241  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos      (22UL)         /*!< ECIIP (Bit 22)                                        */
23242  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk      (0x400000UL)   /*!< ECIIP (Bitfield-Mask: 0x01)                           */
23243  #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos       (21UL)         /*!< TCIP (Bit 21)                                         */
23244  #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk       (0x200000UL)   /*!< TCIP (Bitfield-Mask: 0x01)                            */
23245  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos      (20UL)         /*!< TDEIP (Bit 20)                                        */
23246  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk      (0x100000UL)   /*!< TDEIP (Bitfield-Mask: 0x01)                           */
23247  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos     (19UL)         /*!< TFUFIP (Bit 19)                                       */
23248  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk     (0x80000UL)    /*!< TFUFIP (Bitfield-Mask: 0x01)                          */
23249  #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos       (18UL)         /*!< FRIP (Bit 18)                                         */
23250  #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk       (0x40000UL)    /*!< FRIP (Bitfield-Mask: 0x01)                            */
23251  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos      (17UL)         /*!< RDEIP (Bit 17)                                        */
23252  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk      (0x20000UL)    /*!< RDEIP (Bitfield-Mask: 0x01)                           */
23253  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos     (16UL)         /*!< RFOFIP (Bit 16)                                       */
23254  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk     (0x10000UL)    /*!< RFOFIP (Bitfield-Mask: 0x01)                          */
23255  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos      (11UL)         /*!< CNDIP (Bit 11)                                        */
23256  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk      (0x800UL)      /*!< CNDIP (Bitfield-Mask: 0x01)                           */
23257  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos      (10UL)         /*!< DLCIP (Bit 10)                                        */
23258  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk      (0x400UL)      /*!< DLCIP (Bitfield-Mask: 0x01)                           */
23259  #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos       (9UL)          /*!< CDIP (Bit 9)                                          */
23260  #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk       (0x200UL)      /*!< CDIP (Bitfield-Mask: 0x01)                            */
23261  #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos      (8UL)          /*!< TROIP (Bit 8)                                         */
23262  #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk      (0x100UL)      /*!< TROIP (Bitfield-Mask: 0x01)                           */
23263  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos     (7UL)          /*!< RMAFIP (Bit 7)                                        */
23264  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk     (0x80UL)       /*!< RMAFIP (Bitfield-Mask: 0x01)                          */
23265  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos      (4UL)          /*!< RRFIP (Bit 4)                                         */
23266  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk      (0x10UL)       /*!< RRFIP (Bitfield-Mask: 0x01)                           */
23267  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos     (3UL)          /*!< RTLFIP (Bit 3)                                        */
23268  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk     (0x8UL)        /*!< RTLFIP (Bitfield-Mask: 0x01)                          */
23269  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos     (2UL)          /*!< RTSFIP (Bit 2)                                        */
23270  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk     (0x4UL)        /*!< RTSFIP (Bitfield-Mask: 0x01)                          */
23271  #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos      (1UL)          /*!< PREIP (Bit 1)                                         */
23272  #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk      (0x2UL)        /*!< PREIP (Bitfield-Mask: 0x01)                           */
23273  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos     (0UL)          /*!< CERFIP (Bit 0)                                        */
23274  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk     (0x1UL)        /*!< CERFIP (Bitfield-Mask: 0x01)                          */
23275 /* ========================================================  TRSCER  ========================================================= */
23276  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos     (7UL)          /*!< RMAFCE (Bit 7)                                        */
23277  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk     (0x80UL)       /*!< RMAFCE (Bitfield-Mask: 0x01)                          */
23278  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos      (4UL)          /*!< RRFCE (Bit 4)                                         */
23279  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk      (0x10UL)       /*!< RRFCE (Bitfield-Mask: 0x01)                           */
23280 /* =========================================================  RMFCR  ========================================================= */
23281  #define R_ETHERC_EDMAC_RMFCR_MFC_Pos         (0UL)          /*!< MFC (Bit 0)                                           */
23282  #define R_ETHERC_EDMAC_RMFCR_MFC_Msk         (0xffffUL)     /*!< MFC (Bitfield-Mask: 0xffff)                           */
23283 /* =========================================================  TFTR  ========================================================== */
23284  #define R_ETHERC_EDMAC_TFTR_TFT_Pos          (0UL)          /*!< TFT (Bit 0)                                           */
23285  #define R_ETHERC_EDMAC_TFTR_TFT_Msk          (0x7ffUL)      /*!< TFT (Bitfield-Mask: 0x7ff)                            */
23286 /* ==========================================================  FDR  ========================================================== */
23287  #define R_ETHERC_EDMAC_FDR_TFD_Pos           (8UL)          /*!< TFD (Bit 8)                                           */
23288  #define R_ETHERC_EDMAC_FDR_TFD_Msk           (0x1f00UL)     /*!< TFD (Bitfield-Mask: 0x1f)                             */
23289  #define R_ETHERC_EDMAC_FDR_RFD_Pos           (0UL)          /*!< RFD (Bit 0)                                           */
23290  #define R_ETHERC_EDMAC_FDR_RFD_Msk           (0x1fUL)       /*!< RFD (Bitfield-Mask: 0x1f)                             */
23291 /* =========================================================  RMCR  ========================================================== */
23292  #define R_ETHERC_EDMAC_RMCR_RNR_Pos          (0UL)          /*!< RNR (Bit 0)                                           */
23293  #define R_ETHERC_EDMAC_RMCR_RNR_Msk          (0x1UL)        /*!< RNR (Bitfield-Mask: 0x01)                             */
23294 /* =========================================================  TFUCR  ========================================================= */
23295  #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos       (0UL)          /*!< UNDER (Bit 0)                                         */
23296  #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk       (0xffffUL)     /*!< UNDER (Bitfield-Mask: 0xffff)                         */
23297 /* =========================================================  RFOCR  ========================================================= */
23298  #define R_ETHERC_EDMAC_RFOCR_OVER_Pos        (0UL)          /*!< OVER (Bit 0)                                          */
23299  #define R_ETHERC_EDMAC_RFOCR_OVER_Msk        (0xffffUL)     /*!< OVER (Bitfield-Mask: 0xffff)                          */
23300 /* =========================================================  IOSR  ========================================================== */
23301  #define R_ETHERC_EDMAC_IOSR_ELB_Pos          (0UL)          /*!< ELB (Bit 0)                                           */
23302  #define R_ETHERC_EDMAC_IOSR_ELB_Msk          (0x1UL)        /*!< ELB (Bitfield-Mask: 0x01)                             */
23303 /* =========================================================  FCFTR  ========================================================= */
23304  #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos        (16UL)         /*!< RFFO (Bit 16)                                         */
23305  #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk        (0x70000UL)    /*!< RFFO (Bitfield-Mask: 0x07)                            */
23306  #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos        (0UL)          /*!< RFDO (Bit 0)                                          */
23307  #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk        (0x7UL)        /*!< RFDO (Bitfield-Mask: 0x07)                            */
23308 /* ========================================================  RPADIR  ========================================================= */
23309  #define R_ETHERC_EDMAC_RPADIR_PADS_Pos       (16UL)         /*!< PADS (Bit 16)                                         */
23310  #define R_ETHERC_EDMAC_RPADIR_PADS_Msk       (0x30000UL)    /*!< PADS (Bitfield-Mask: 0x03)                            */
23311  #define R_ETHERC_EDMAC_RPADIR_PADR_Pos       (0UL)          /*!< PADR (Bit 0)                                          */
23312  #define R_ETHERC_EDMAC_RPADIR_PADR_Msk       (0x3fUL)       /*!< PADR (Bitfield-Mask: 0x3f)                            */
23313 /* =========================================================  TRIMD  ========================================================= */
23314  #define R_ETHERC_EDMAC_TRIMD_TIM_Pos         (4UL)          /*!< TIM (Bit 4)                                           */
23315  #define R_ETHERC_EDMAC_TRIMD_TIM_Msk         (0x10UL)       /*!< TIM (Bitfield-Mask: 0x01)                             */
23316  #define R_ETHERC_EDMAC_TRIMD_TIS_Pos         (0UL)          /*!< TIS (Bit 0)                                           */
23317  #define R_ETHERC_EDMAC_TRIMD_TIS_Msk         (0x1UL)        /*!< TIS (Bitfield-Mask: 0x01)                             */
23318 /* =========================================================  RBWAR  ========================================================= */
23319  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos       (0UL)          /*!< RBWAR (Bit 0)                                         */
23320  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk       (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff)                     */
23321 /* =========================================================  RDFAR  ========================================================= */
23322  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos       (0UL)          /*!< RDFAR (Bit 0)                                         */
23323  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk       (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff)                     */
23324 /* =========================================================  TBRAR  ========================================================= */
23325  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos       (0UL)          /*!< TBRAR (Bit 0)                                         */
23326  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk       (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff)                     */
23327 /* =========================================================  TDFAR  ========================================================= */
23328  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos       (0UL)          /*!< TDFAR (Bit 0)                                         */
23329  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk       (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff)                     */
23330 
23331 /* =========================================================================================================================== */
23332 /* ================                                      R_ETHERC_EPTPC                                       ================ */
23333 /* =========================================================================================================================== */
23334 
23335 /* =========================================================  SYSR  ========================================================== */
23336  #define R_ETHERC_EPTPC_SYSR_GENDN_Pos             (17UL)         /*!< GENDN (Bit 17)                                        */
23337  #define R_ETHERC_EPTPC_SYSR_GENDN_Msk             (0x20000UL)    /*!< GENDN (Bitfield-Mask: 0x01)                           */
23338  #define R_ETHERC_EPTPC_SYSR_RESDN_Pos             (16UL)         /*!< RESDN (Bit 16)                                        */
23339  #define R_ETHERC_EPTPC_SYSR_RESDN_Msk             (0x10000UL)    /*!< RESDN (Bitfield-Mask: 0x01)                           */
23340  #define R_ETHERC_EPTPC_SYSR_INFABT_Pos            (14UL)         /*!< INFABT (Bit 14)                                       */
23341  #define R_ETHERC_EPTPC_SYSR_INFABT_Msk            (0x4000UL)     /*!< INFABT (Bitfield-Mask: 0x01)                          */
23342  #define R_ETHERC_EPTPC_SYSR_RECLP_Pos             (12UL)         /*!< RECLP (Bit 12)                                        */
23343  #define R_ETHERC_EPTPC_SYSR_RECLP_Msk             (0x1000UL)     /*!< RECLP (Bitfield-Mask: 0x01)                           */
23344  #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos            (6UL)          /*!< DRQOVR (Bit 6)                                        */
23345  #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk            (0x40UL)       /*!< DRQOVR (Bitfield-Mask: 0x01)                          */
23346  #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos            (5UL)          /*!< INTDEV (Bit 5)                                        */
23347  #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk            (0x20UL)       /*!< INTDEV (Bitfield-Mask: 0x01)                          */
23348  #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos             (4UL)          /*!< DRPTO (Bit 4)                                         */
23349  #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk             (0x10UL)       /*!< DRPTO (Bitfield-Mask: 0x01)                           */
23350  #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos             (2UL)          /*!< MPDUD (Bit 2)                                         */
23351  #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk             (0x4UL)        /*!< MPDUD (Bitfield-Mask: 0x01)                           */
23352  #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos            (1UL)          /*!< INTCHG (Bit 1)                                        */
23353  #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk            (0x2UL)        /*!< INTCHG (Bitfield-Mask: 0x01)                          */
23354  #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos             (0UL)          /*!< OFMUD (Bit 0)                                         */
23355  #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk             (0x1UL)        /*!< OFMUD (Bitfield-Mask: 0x01)                           */
23356 /* =========================================================  SYIPR  ========================================================= */
23357  #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos            (17UL)         /*!< GENDN (Bit 17)                                        */
23358  #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk            (0x20000UL)    /*!< GENDN (Bitfield-Mask: 0x01)                           */
23359  #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos            (16UL)         /*!< RESDN (Bit 16)                                        */
23360  #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk            (0x10000UL)    /*!< RESDN (Bitfield-Mask: 0x01)                           */
23361  #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos           (14UL)         /*!< INFABT (Bit 14)                                       */
23362  #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk           (0x4000UL)     /*!< INFABT (Bitfield-Mask: 0x01)                          */
23363  #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos            (12UL)         /*!< RECLP (Bit 12)                                        */
23364  #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk            (0x1000UL)     /*!< RECLP (Bitfield-Mask: 0x01)                           */
23365  #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos           (6UL)          /*!< DRQOVR (Bit 6)                                        */
23366  #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk           (0x40UL)       /*!< DRQOVR (Bitfield-Mask: 0x01)                          */
23367  #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos           (5UL)          /*!< INTDEV (Bit 5)                                        */
23368  #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk           (0x20UL)       /*!< INTDEV (Bitfield-Mask: 0x01)                          */
23369  #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos            (4UL)          /*!< DRPTO (Bit 4)                                         */
23370  #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk            (0x10UL)       /*!< DRPTO (Bitfield-Mask: 0x01)                           */
23371  #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos            (2UL)          /*!< MPDUD (Bit 2)                                         */
23372  #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk            (0x4UL)        /*!< MPDUD (Bitfield-Mask: 0x01)                           */
23373  #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos           (1UL)          /*!< INTCHG (Bit 1)                                        */
23374  #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk           (0x2UL)        /*!< INTCHG (Bitfield-Mask: 0x01)                          */
23375  #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos            (0UL)          /*!< OFMUD (Bit 0)                                         */
23376  #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk            (0x1UL)        /*!< OFMUD (Bitfield-Mask: 0x01)                           */
23377 /* ========================================================  SYMACRU  ======================================================== */
23378  #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos        (0UL)          /*!< SYMACRU (Bit 0)                                       */
23379  #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk        (0xffffffUL)   /*!< SYMACRU (Bitfield-Mask: 0xffffff)                     */
23380 /* ========================================================  SYMACRL  ======================================================== */
23381  #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos        (0UL)          /*!< SYMACRL (Bit 0)                                       */
23382  #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk        (0xffffffUL)   /*!< SYMACRL (Bitfield-Mask: 0xffffff)                     */
23383 /* =======================================================  SYLLCCTLR  ======================================================= */
23384  #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos          (0UL)          /*!< CTL (Bit 0)                                           */
23385  #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk          (0xffUL)       /*!< CTL (Bitfield-Mask: 0xff)                             */
23386 /* =======================================================  SYIPADDRR  ======================================================= */
23387  #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos    (0UL)          /*!< SYIPADDRR (Bit 0)                                     */
23388  #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk    (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff)                 */
23389 /* ========================================================  SYSPVRR  ======================================================== */
23390  #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos           (4UL)          /*!< TRSP (Bit 4)                                          */
23391  #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk           (0xf0UL)       /*!< TRSP (Bitfield-Mask: 0x0f)                            */
23392  #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
23393  #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk            (0xfUL)        /*!< VER (Bitfield-Mask: 0x0f)                             */
23394 /* ========================================================  SYDOMR  ========================================================= */
23395  #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos            (0UL)          /*!< DNUM (Bit 0)                                          */
23396  #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk            (0xffUL)       /*!< DNUM (Bitfield-Mask: 0xff)                            */
23397 /* =========================================================  ANFR  ========================================================== */
23398  #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos            (14UL)         /*!< FLAG14 (Bit 14)                                       */
23399  #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk            (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
23400  #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos            (13UL)         /*!< FLAG13 (Bit 13)                                       */
23401  #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk            (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
23402  #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos            (10UL)         /*!< FLAG10 (Bit 10)                                       */
23403  #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk            (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
23404  #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos             (8UL)          /*!< FLAG8 (Bit 8)                                         */
23405  #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk             (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
23406  #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos             (5UL)          /*!< FLAG5 (Bit 5)                                         */
23407  #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk             (0x20UL)       /*!< FLAG5 (Bitfield-Mask: 0x01)                           */
23408  #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos             (4UL)          /*!< FLAG4 (Bit 4)                                         */
23409  #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk             (0x10UL)       /*!< FLAG4 (Bitfield-Mask: 0x01)                           */
23410  #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos             (3UL)          /*!< FLAG3 (Bit 3)                                         */
23411  #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk             (0x8UL)        /*!< FLAG3 (Bitfield-Mask: 0x01)                           */
23412  #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos             (2UL)          /*!< FLAG2 (Bit 2)                                         */
23413  #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk             (0x4UL)        /*!< FLAG2 (Bitfield-Mask: 0x01)                           */
23414  #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos             (1UL)          /*!< FLAG1 (Bit 1)                                         */
23415  #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk             (0x2UL)        /*!< FLAG1 (Bitfield-Mask: 0x01)                           */
23416  #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos             (0UL)          /*!< FLAG0 (Bit 0)                                         */
23417  #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk             (0x1UL)        /*!< FLAG0 (Bitfield-Mask: 0x01)                           */
23418 /* =========================================================  SYNFR  ========================================================= */
23419  #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos           (14UL)         /*!< FLAG14 (Bit 14)                                       */
23420  #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk           (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
23421  #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos           (13UL)         /*!< FLAG13 (Bit 13)                                       */
23422  #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk           (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
23423  #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos           (10UL)         /*!< FLAG10 (Bit 10)                                       */
23424  #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk           (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
23425  #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos            (9UL)          /*!< FLAG9 (Bit 9)                                         */
23426  #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk            (0x200UL)      /*!< FLAG9 (Bitfield-Mask: 0x01)                           */
23427  #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos            (8UL)          /*!< FLAG8 (Bit 8)                                         */
23428  #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk            (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
23429 /* ========================================================  DYRQFR  ========================================================= */
23430  #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos          (14UL)         /*!< FLAG14 (Bit 14)                                       */
23431  #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk          (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
23432  #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos          (13UL)         /*!< FLAG13 (Bit 13)                                       */
23433  #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk          (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
23434  #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos          (10UL)         /*!< FLAG10 (Bit 10)                                       */
23435  #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk          (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
23436 /* ========================================================  DYRPFR  ========================================================= */
23437  #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos          (14UL)         /*!< FLAG14 (Bit 14)                                       */
23438  #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk          (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
23439  #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos          (13UL)         /*!< FLAG13 (Bit 13)                                       */
23440  #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk          (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
23441  #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos          (10UL)         /*!< FLAG10 (Bit 10)                                       */
23442  #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk          (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
23443  #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos           (9UL)          /*!< FLAG9 (Bit 9)                                         */
23444  #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk           (0x200UL)      /*!< FLAG9 (Bitfield-Mask: 0x01)                           */
23445  #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos           (8UL)          /*!< FLAG8 (Bit 8)                                         */
23446  #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk           (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
23447 /* ========================================================  SYCIDRU  ======================================================== */
23448  #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos        (0UL)          /*!< SYCIDRU (Bit 0)                                       */
23449  #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk        (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff)                   */
23450 /* ========================================================  SYCIDRL  ======================================================== */
23451  #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos        (0UL)          /*!< SYCIDRL (Bit 0)                                       */
23452  #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk        (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff)                   */
23453 /* ========================================================  SYPNUMR  ======================================================== */
23454  #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos           (0UL)          /*!< PNUM (Bit 0)                                          */
23455  #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk           (0xffffUL)     /*!< PNUM (Bitfield-Mask: 0xffff)                          */
23456 /* ========================================================  SYRVLDR  ======================================================== */
23457  #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos           (2UL)          /*!< ANUP (Bit 2)                                          */
23458  #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk           (0x4UL)        /*!< ANUP (Bitfield-Mask: 0x01)                            */
23459  #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos           (1UL)          /*!< STUP (Bit 1)                                          */
23460  #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk           (0x2UL)        /*!< STUP (Bitfield-Mask: 0x01)                            */
23461  #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos           (0UL)          /*!< BMUP (Bit 0)                                          */
23462  #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk           (0x1UL)        /*!< BMUP (Bitfield-Mask: 0x01)                            */
23463 /* ========================================================  SYRFL1R  ======================================================== */
23464  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos         (30UL)         /*!< PDFUP2 (Bit 30)                                       */
23465  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk         (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01)                          */
23466  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos         (29UL)         /*!< PDFUP1 (Bit 29)                                       */
23467  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk         (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01)                          */
23468  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos         (28UL)         /*!< PDFUP0 (Bit 28)                                       */
23469  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk         (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01)                          */
23470  #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos          (26UL)         /*!< PDRP2 (Bit 26)                                        */
23471  #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk          (0x4000000UL)  /*!< PDRP2 (Bitfield-Mask: 0x01)                           */
23472  #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos          (25UL)         /*!< PDRP1 (Bit 25)                                        */
23473  #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk          (0x2000000UL)  /*!< PDRP1 (Bitfield-Mask: 0x01)                           */
23474  #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos          (24UL)         /*!< PDRP0 (Bit 24)                                        */
23475  #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk          (0x1000000UL)  /*!< PDRP0 (Bitfield-Mask: 0x01)                           */
23476  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos          (22UL)         /*!< PDRQ2 (Bit 22)                                        */
23477  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk          (0x400000UL)   /*!< PDRQ2 (Bitfield-Mask: 0x01)                           */
23478  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos          (21UL)         /*!< PDRQ1 (Bit 21)                                        */
23479  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk          (0x200000UL)   /*!< PDRQ1 (Bitfield-Mask: 0x01)                           */
23480  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos          (20UL)         /*!< PDRQ0 (Bit 20)                                        */
23481  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk          (0x100000UL)   /*!< PDRQ0 (Bitfield-Mask: 0x01)                           */
23482  #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos           (18UL)         /*!< DRP2 (Bit 18)                                         */
23483  #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk           (0x40000UL)    /*!< DRP2 (Bitfield-Mask: 0x01)                            */
23484  #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos           (17UL)         /*!< DRP1 (Bit 17)                                         */
23485  #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk           (0x20000UL)    /*!< DRP1 (Bitfield-Mask: 0x01)                            */
23486  #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos           (16UL)         /*!< DRP0 (Bit 16)                                         */
23487  #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk           (0x10000UL)    /*!< DRP0 (Bitfield-Mask: 0x01)                            */
23488  #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos           (14UL)         /*!< DRQ2 (Bit 14)                                         */
23489  #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk           (0x4000UL)     /*!< DRQ2 (Bitfield-Mask: 0x01)                            */
23490  #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos           (13UL)         /*!< DRQ1 (Bit 13)                                         */
23491  #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk           (0x2000UL)     /*!< DRQ1 (Bitfield-Mask: 0x01)                            */
23492  #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos           (12UL)         /*!< DRQ0 (Bit 12)                                         */
23493  #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk           (0x1000UL)     /*!< DRQ0 (Bitfield-Mask: 0x01)                            */
23494  #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos           (10UL)         /*!< FUP2 (Bit 10)                                         */
23495  #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk           (0x400UL)      /*!< FUP2 (Bitfield-Mask: 0x01)                            */
23496  #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos           (9UL)          /*!< FUP1 (Bit 9)                                          */
23497  #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk           (0x200UL)      /*!< FUP1 (Bitfield-Mask: 0x01)                            */
23498  #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos           (8UL)          /*!< FUP0 (Bit 8)                                          */
23499  #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk           (0x100UL)      /*!< FUP0 (Bitfield-Mask: 0x01)                            */
23500  #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos          (6UL)          /*!< SYNC2 (Bit 6)                                         */
23501  #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk          (0x40UL)       /*!< SYNC2 (Bitfield-Mask: 0x01)                           */
23502  #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos          (5UL)          /*!< SYNC1 (Bit 5)                                         */
23503  #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk          (0x20UL)       /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
23504  #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos          (4UL)          /*!< SYNC0 (Bit 4)                                         */
23505  #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk          (0x10UL)       /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
23506  #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos          (1UL)          /*!< ANCE1 (Bit 1)                                         */
23507  #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk          (0x2UL)        /*!< ANCE1 (Bitfield-Mask: 0x01)                           */
23508  #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos          (0UL)          /*!< ANCE0 (Bit 0)                                         */
23509  #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk          (0x1UL)        /*!< ANCE0 (Bitfield-Mask: 0x01)                           */
23510 /* ========================================================  SYRFL2R  ======================================================== */
23511  #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos           (29UL)         /*!< ILL1 (Bit 29)                                         */
23512  #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk           (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01)                            */
23513  #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos           (28UL)         /*!< ILL0 (Bit 28)                                         */
23514  #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk           (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01)                            */
23515  #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos           (5UL)          /*!< SIG1 (Bit 5)                                          */
23516  #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk           (0x20UL)       /*!< SIG1 (Bitfield-Mask: 0x01)                            */
23517  #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos           (4UL)          /*!< SIG0 (Bit 4)                                          */
23518  #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk           (0x10UL)       /*!< SIG0 (Bitfield-Mask: 0x01)                            */
23519  #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos           (1UL)          /*!< MAN1 (Bit 1)                                          */
23520  #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk           (0x2UL)        /*!< MAN1 (Bitfield-Mask: 0x01)                            */
23521  #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos           (0UL)          /*!< MAN0 (Bit 0)                                          */
23522  #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk           (0x1UL)        /*!< MAN0 (Bitfield-Mask: 0x01)                            */
23523 /* ========================================================  SYTRENR  ======================================================== */
23524  #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos           (12UL)         /*!< PDRQ (Bit 12)                                         */
23525  #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk           (0x1000UL)     /*!< PDRQ (Bitfield-Mask: 0x01)                            */
23526  #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos            (8UL)          /*!< DRQ (Bit 8)                                           */
23527  #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk            (0x100UL)      /*!< DRQ (Bitfield-Mask: 0x01)                             */
23528  #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos           (4UL)          /*!< SYNC (Bit 4)                                          */
23529  #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk           (0x10UL)       /*!< SYNC (Bitfield-Mask: 0x01)                            */
23530  #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos           (0UL)          /*!< ANCE (Bit 0)                                          */
23531  #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk           (0x1UL)        /*!< ANCE (Bitfield-Mask: 0x01)                            */
23532 /* ========================================================  MTCIDU  ========================================================= */
23533  #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos          (0UL)          /*!< MTCIDU (Bit 0)                                        */
23534  #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk          (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff)                    */
23535 /* ========================================================  MTCIDL  ========================================================= */
23536  #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos          (0UL)          /*!< MTCIDL (Bit 0)                                        */
23537  #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk          (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff)                    */
23538 /* =========================================================  MTPID  ========================================================= */
23539  #define R_ETHERC_EPTPC_MTPID_PNUM_Pos             (0UL)          /*!< PNUM (Bit 0)                                          */
23540  #define R_ETHERC_EPTPC_MTPID_PNUM_Msk             (0xffffUL)     /*!< PNUM (Bitfield-Mask: 0xffff)                          */
23541 /* ========================================================  SYTLIR  ========================================================= */
23542  #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos            (16UL)         /*!< DREQ (Bit 16)                                         */
23543  #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk            (0xff0000UL)   /*!< DREQ (Bitfield-Mask: 0xff)                            */
23544  #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos            (8UL)          /*!< SYNC (Bit 8)                                          */
23545  #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk            (0xff00UL)     /*!< SYNC (Bitfield-Mask: 0xff)                            */
23546  #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos            (0UL)          /*!< ANCE (Bit 0)                                          */
23547  #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk            (0xffUL)       /*!< ANCE (Bitfield-Mask: 0xff)                            */
23548 /* ========================================================  SYRLIR  ========================================================= */
23549  #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos           (16UL)         /*!< DRESP (Bit 16)                                        */
23550  #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk           (0xff0000UL)   /*!< DRESP (Bitfield-Mask: 0xff)                           */
23551  #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos            (8UL)          /*!< SYNC (Bit 8)                                          */
23552  #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk            (0xff00UL)     /*!< SYNC (Bitfield-Mask: 0xff)                            */
23553  #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos            (0UL)          /*!< ANCE (Bit 0)                                          */
23554  #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk            (0xffUL)       /*!< ANCE (Bitfield-Mask: 0xff)                            */
23555 /* =========================================================  OFMRU  ========================================================= */
23556  #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos            (0UL)          /*!< OFMRU (Bit 0)                                         */
23557  #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk            (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff)                     */
23558 /* =========================================================  OFMRL  ========================================================= */
23559  #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos            (0UL)          /*!< OFMRL (Bit 0)                                         */
23560  #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk            (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff)                     */
23561 /* =========================================================  MPDRU  ========================================================= */
23562  #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos            (0UL)          /*!< MPDRU (Bit 0)                                         */
23563  #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk            (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff)                     */
23564 /* =========================================================  MPDRL  ========================================================= */
23565  #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos            (0UL)          /*!< MPDRL (Bit 0)                                         */
23566  #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk            (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff)                     */
23567 /* =========================================================  GMPR  ========================================================== */
23568  #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos             (16UL)         /*!< GMPR1 (Bit 16)                                        */
23569  #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk             (0xff0000UL)   /*!< GMPR1 (Bitfield-Mask: 0xff)                           */
23570  #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos             (0UL)          /*!< GMPR2 (Bit 0)                                         */
23571  #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk             (0xffUL)       /*!< GMPR2 (Bitfield-Mask: 0xff)                           */
23572 /* =========================================================  GMCQR  ========================================================= */
23573  #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos            (0UL)          /*!< GMCQR (Bit 0)                                         */
23574  #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk            (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff)                     */
23575 /* ========================================================  GMIDRU  ========================================================= */
23576  #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos          (0UL)          /*!< GMIDRU (Bit 0)                                        */
23577  #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk          (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff)                    */
23578 /* ========================================================  GMIDRL  ========================================================= */
23579  #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos          (0UL)          /*!< GMIDRL (Bit 0)                                        */
23580  #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk          (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff)                    */
23581 /* ========================================================  CUOTSR  ========================================================= */
23582  #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos            (16UL)         /*!< CUTO (Bit 16)                                         */
23583  #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk            (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff)                          */
23584  #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos            (0UL)          /*!< TSRC (Bit 0)                                          */
23585  #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk            (0xffUL)       /*!< TSRC (Bitfield-Mask: 0xff)                            */
23586 /* ==========================================================  SRR  ========================================================== */
23587  #define R_ETHERC_EPTPC_SRR_SRMV_Pos               (0UL)          /*!< SRMV (Bit 0)                                          */
23588  #define R_ETHERC_EPTPC_SRR_SRMV_Msk               (0xffffUL)     /*!< SRMV (Bitfield-Mask: 0xffff)                          */
23589 /* ========================================================  PPMACRU  ======================================================== */
23590  #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos        (0UL)          /*!< PPMACRU (Bit 0)                                       */
23591  #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk        (0xffffffUL)   /*!< PPMACRU (Bitfield-Mask: 0xffffff)                     */
23592 /* ========================================================  PPMACRL  ======================================================== */
23593  #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos        (0UL)          /*!< PPMACRL (Bit 0)                                       */
23594  #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk        (0xffffffUL)   /*!< PPMACRL (Bitfield-Mask: 0xffffff)                     */
23595 /* ========================================================  PDMACRU  ======================================================== */
23596  #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos        (0UL)          /*!< PDMACRU (Bit 0)                                       */
23597  #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk        (0xffffffUL)   /*!< PDMACRU (Bitfield-Mask: 0xffffff)                     */
23598 /* ========================================================  PDMACRL  ======================================================== */
23599  #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos        (0UL)          /*!< PDMACRL (Bit 0)                                       */
23600  #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk        (0xffffffUL)   /*!< PDMACRL (Bitfield-Mask: 0xffffff)                     */
23601 /* ========================================================  PETYPER  ======================================================== */
23602  #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos           (0UL)          /*!< TYPE (Bit 0)                                          */
23603  #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk           (0xffffUL)     /*!< TYPE (Bitfield-Mask: 0xffff)                          */
23604 /* =========================================================  PPIPR  ========================================================= */
23605  #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos            (0UL)          /*!< PPIPR (Bit 0)                                         */
23606  #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk            (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff)                     */
23607 /* =========================================================  PDIPR  ========================================================= */
23608  #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos            (0UL)          /*!< PDIPR (Bit 0)                                         */
23609  #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk            (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff)                     */
23610 /* ========================================================  PETOSR  ========================================================= */
23611  #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos            (0UL)          /*!< EVTO (Bit 0)                                          */
23612  #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk            (0xffUL)       /*!< EVTO (Bitfield-Mask: 0xff)                            */
23613 /* ========================================================  PGTOSR  ========================================================= */
23614  #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos            (0UL)          /*!< GETO (Bit 0)                                          */
23615  #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk            (0xffUL)       /*!< GETO (Bitfield-Mask: 0xff)                            */
23616 /* ========================================================  PPTTLR  ========================================================= */
23617  #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos            (0UL)          /*!< PRTL (Bit 0)                                          */
23618  #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk            (0xffUL)       /*!< PRTL (Bitfield-Mask: 0xff)                            */
23619 /* ========================================================  PDTTLR  ========================================================= */
23620  #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos            (0UL)          /*!< PDTL (Bit 0)                                          */
23621  #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk            (0xffUL)       /*!< PDTL (Bitfield-Mask: 0xff)                            */
23622 /* ========================================================  PEUDPR  ========================================================= */
23623  #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos           (0UL)          /*!< EVUPT (Bit 0)                                         */
23624  #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk           (0xffffUL)     /*!< EVUPT (Bitfield-Mask: 0xffff)                         */
23625 /* ========================================================  PGUDPR  ========================================================= */
23626  #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos           (0UL)          /*!< GEUPT (Bit 0)                                         */
23627  #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk           (0xffffUL)     /*!< GEUPT (Bitfield-Mask: 0xffff)                         */
23628 /* =========================================================  FFLTR  ========================================================= */
23629  #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos           (16UL)         /*!< EXTPRM (Bit 16)                                       */
23630  #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk           (0x10000UL)    /*!< EXTPRM (Bitfield-Mask: 0x01)                          */
23631  #define R_ETHERC_EPTPC_FFLTR_ENB_Pos              (2UL)          /*!< ENB (Bit 2)                                           */
23632  #define R_ETHERC_EPTPC_FFLTR_ENB_Msk              (0x4UL)        /*!< ENB (Bitfield-Mask: 0x01)                             */
23633  #define R_ETHERC_EPTPC_FFLTR_PRT_Pos              (1UL)          /*!< PRT (Bit 1)                                           */
23634  #define R_ETHERC_EPTPC_FFLTR_PRT_Msk              (0x2UL)        /*!< PRT (Bitfield-Mask: 0x01)                             */
23635  #define R_ETHERC_EPTPC_FFLTR_SEL_Pos              (0UL)          /*!< SEL (Bit 0)                                           */
23636  #define R_ETHERC_EPTPC_FFLTR_SEL_Msk              (0x1UL)        /*!< SEL (Bitfield-Mask: 0x01)                             */
23637 /* ========================================================  FMAC0RU  ======================================================== */
23638  #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Pos        (0UL)          /*!< FMAC0RU (Bit 0)                                       */
23639  #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Msk        (0xffffffUL)   /*!< FMAC0RU (Bitfield-Mask: 0xffffff)                     */
23640 /* ========================================================  FMAC0RL  ======================================================== */
23641  #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Pos        (0UL)          /*!< FMAC0RL (Bit 0)                                       */
23642  #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Msk        (0xffffffUL)   /*!< FMAC0RL (Bitfield-Mask: 0xffffff)                     */
23643 /* ========================================================  FMAC1RU  ======================================================== */
23644  #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Pos        (0UL)          /*!< FMAC1RU (Bit 0)                                       */
23645  #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Msk        (0xffffffUL)   /*!< FMAC1RU (Bitfield-Mask: 0xffffff)                     */
23646 /* ========================================================  FMAC1RL  ======================================================== */
23647  #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Pos        (0UL)          /*!< FMAC1RL (Bit 0)                                       */
23648  #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Msk        (0xffffffUL)   /*!< FMAC1RL (Bitfield-Mask: 0xffffff)                     */
23649 /* ========================================================  DASYMRU  ======================================================== */
23650  #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos        (0UL)          /*!< DASYMRU (Bit 0)                                       */
23651  #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk        (0xffffUL)     /*!< DASYMRU (Bitfield-Mask: 0xffff)                       */
23652 /* ========================================================  DASYMRL  ======================================================== */
23653  #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos        (0UL)          /*!< DASYMRL (Bit 0)                                       */
23654  #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk        (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff)                   */
23655 /* ========================================================  TSLATR  ========================================================= */
23656  #define R_ETHERC_EPTPC_TSLATR_INGP_Pos            (16UL)         /*!< INGP (Bit 16)                                         */
23657  #define R_ETHERC_EPTPC_TSLATR_INGP_Msk            (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff)                          */
23658  #define R_ETHERC_EPTPC_TSLATR_EGP_Pos             (0UL)          /*!< EGP (Bit 0)                                           */
23659  #define R_ETHERC_EPTPC_TSLATR_EGP_Msk             (0xffffUL)     /*!< EGP (Bitfield-Mask: 0xffff)                           */
23660 /* ========================================================  SYCONFR  ======================================================== */
23661  #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos          (20UL)         /*!< TCMOD (Bit 20)                                        */
23662  #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk          (0x100000UL)   /*!< TCMOD (Bitfield-Mask: 0x01)                           */
23663  #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos         (16UL)         /*!< FILDIS (Bit 16)                                       */
23664  #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk         (0x10000UL)    /*!< FILDIS (Bitfield-Mask: 0x01)                          */
23665  #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos          (12UL)         /*!< SBDIS (Bit 12)                                        */
23666  #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk          (0x1000UL)     /*!< SBDIS (Bitfield-Mask: 0x01)                           */
23667  #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos           (0UL)          /*!< TCYC (Bit 0)                                          */
23668  #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk           (0xffUL)       /*!< TCYC (Bitfield-Mask: 0xff)                            */
23669 /* ========================================================  SYFORMR  ======================================================== */
23670  #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos          (1UL)          /*!< FORM1 (Bit 1)                                         */
23671  #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk          (0x2UL)        /*!< FORM1 (Bitfield-Mask: 0x01)                           */
23672  #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos          (0UL)          /*!< FORM0 (Bit 0)                                         */
23673  #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk          (0x1UL)        /*!< FORM0 (Bitfield-Mask: 0x01)                           */
23674 /* ========================================================  RSTOUTR  ======================================================== */
23675  #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos        (0UL)          /*!< RSTOUTR (Bit 0)                                       */
23676  #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk        (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff)                   */
23677 
23678 /* =========================================================================================================================== */
23679 /* ================                                    R_ETHERC_EPTPC_CFG                                     ================ */
23680 /* =========================================================================================================================== */
23681 
23682 /* ========================================================  PTRSTR  ========================================================= */
23683  #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos       (0UL)       /*!< RESET (Bit 0)                                         */
23684  #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk       (0x1UL)     /*!< RESET (Bitfield-Mask: 0x01)                           */
23685 /* ========================================================  STCSELR  ======================================================== */
23686  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos    (8UL)       /*!< SCLKSEL (Bit 8)                                       */
23687  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk    (0x700UL)   /*!< SCLKSEL (Bitfield-Mask: 0x07)                         */
23688  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos    (0UL)       /*!< SCLKDIV (Bit 0)                                       */
23689  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk    (0x7UL)     /*!< SCLKDIV (Bitfield-Mask: 0x07)                         */
23690 /* ========================================================  BYPASS  ========================================================= */
23691  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos     (16UL)      /*!< BYPASS1 (Bit 16)                                      */
23692  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk     (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01)                         */
23693  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos     (0UL)       /*!< BYPASS0 (Bit 0)                                       */
23694  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk     (0x1UL)     /*!< BYPASS0 (Bitfield-Mask: 0x01)                         */
23695 
23696 /* =========================================================================================================================== */
23697 /* ================                                   R_ETHERC_EPTPC_COMMON                                   ================ */
23698 /* =========================================================================================================================== */
23699 
23700 /* =========================================================  MIESR  ========================================================= */
23701  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos           (21UL)         /*!< CYC5 (Bit 21)                                         */
23702  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk           (0x200000UL)   /*!< CYC5 (Bitfield-Mask: 0x01)                            */
23703  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos           (20UL)         /*!< CYC4 (Bit 20)                                         */
23704  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk           (0x100000UL)   /*!< CYC4 (Bitfield-Mask: 0x01)                            */
23705  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos           (19UL)         /*!< CYC3 (Bit 19)                                         */
23706  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk           (0x80000UL)    /*!< CYC3 (Bitfield-Mask: 0x01)                            */
23707  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos           (18UL)         /*!< CYC2 (Bit 18)                                         */
23708  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk           (0x40000UL)    /*!< CYC2 (Bitfield-Mask: 0x01)                            */
23709  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos           (17UL)         /*!< CYC1 (Bit 17)                                         */
23710  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk           (0x20000UL)    /*!< CYC1 (Bitfield-Mask: 0x01)                            */
23711  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos           (16UL)         /*!< CYC0 (Bit 16)                                         */
23712  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk           (0x10000UL)    /*!< CYC0 (Bitfield-Mask: 0x01)                            */
23713  #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos            (3UL)          /*!< PRC (Bit 3)                                           */
23714  #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk            (0x8UL)        /*!< PRC (Bitfield-Mask: 0x01)                             */
23715  #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos            (2UL)          /*!< SY1 (Bit 2)                                           */
23716  #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk            (0x4UL)        /*!< SY1 (Bitfield-Mask: 0x01)                             */
23717  #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos            (1UL)          /*!< SY0 (Bit 1)                                           */
23718  #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk            (0x2UL)        /*!< SY0 (Bitfield-Mask: 0x01)                             */
23719  #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos             (0UL)          /*!< ST (Bit 0)                                            */
23720  #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk             (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
23721 /* ========================================================  MIEIPR  ========================================================= */
23722  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos          (21UL)         /*!< CYC5 (Bit 21)                                         */
23723  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk          (0x200000UL)   /*!< CYC5 (Bitfield-Mask: 0x01)                            */
23724  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos          (20UL)         /*!< CYC4 (Bit 20)                                         */
23725  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk          (0x100000UL)   /*!< CYC4 (Bitfield-Mask: 0x01)                            */
23726  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos          (19UL)         /*!< CYC3 (Bit 19)                                         */
23727  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk          (0x80000UL)    /*!< CYC3 (Bitfield-Mask: 0x01)                            */
23728  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos          (18UL)         /*!< CYC2 (Bit 18)                                         */
23729  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk          (0x40000UL)    /*!< CYC2 (Bitfield-Mask: 0x01)                            */
23730  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos          (17UL)         /*!< CYC1 (Bit 17)                                         */
23731  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk          (0x20000UL)    /*!< CYC1 (Bitfield-Mask: 0x01)                            */
23732  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos          (16UL)         /*!< CYC0 (Bit 16)                                         */
23733  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk          (0x10000UL)    /*!< CYC0 (Bitfield-Mask: 0x01)                            */
23734  #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos           (3UL)          /*!< PRC (Bit 3)                                           */
23735  #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk           (0x8UL)        /*!< PRC (Bitfield-Mask: 0x01)                             */
23736  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos           (2UL)          /*!< SY1 (Bit 2)                                           */
23737  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk           (0x4UL)        /*!< SY1 (Bitfield-Mask: 0x01)                             */
23738  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos           (1UL)          /*!< SY0 (Bit 1)                                           */
23739  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk           (0x2UL)        /*!< SY0 (Bitfield-Mask: 0x01)                             */
23740  #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos            (0UL)          /*!< ST (Bit 0)                                            */
23741  #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk            (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
23742 /* ========================================================  ELIPPR  ========================================================= */
23743  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos          (24UL)         /*!< PLSN (Bit 24)                                         */
23744  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk          (0x1000000UL)  /*!< PLSN (Bitfield-Mask: 0x01)                            */
23745  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos          (16UL)         /*!< PLSP (Bit 16)                                         */
23746  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk          (0x10000UL)    /*!< PLSP (Bitfield-Mask: 0x01)                            */
23747  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos         (13UL)         /*!< CYCN5 (Bit 13)                                        */
23748  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk         (0x2000UL)     /*!< CYCN5 (Bitfield-Mask: 0x01)                           */
23749  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos         (12UL)         /*!< CYCN4 (Bit 12)                                        */
23750  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk         (0x1000UL)     /*!< CYCN4 (Bitfield-Mask: 0x01)                           */
23751  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos         (11UL)         /*!< CYCN3 (Bit 11)                                        */
23752  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk         (0x800UL)      /*!< CYCN3 (Bitfield-Mask: 0x01)                           */
23753  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos         (10UL)         /*!< CYCN2 (Bit 10)                                        */
23754  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk         (0x400UL)      /*!< CYCN2 (Bitfield-Mask: 0x01)                           */
23755  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos         (9UL)          /*!< CYCN1 (Bit 9)                                         */
23756  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk         (0x200UL)      /*!< CYCN1 (Bitfield-Mask: 0x01)                           */
23757  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos         (8UL)          /*!< CYCN0 (Bit 8)                                         */
23758  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk         (0x100UL)      /*!< CYCN0 (Bitfield-Mask: 0x01)                           */
23759  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos         (5UL)          /*!< CYCP5 (Bit 5)                                         */
23760  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk         (0x20UL)       /*!< CYCP5 (Bitfield-Mask: 0x01)                           */
23761  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos         (4UL)          /*!< CYCP4 (Bit 4)                                         */
23762  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk         (0x10UL)       /*!< CYCP4 (Bitfield-Mask: 0x01)                           */
23763  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos         (3UL)          /*!< CYCP3 (Bit 3)                                         */
23764  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk         (0x8UL)        /*!< CYCP3 (Bitfield-Mask: 0x01)                           */
23765  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos         (2UL)          /*!< CYCP2 (Bit 2)                                         */
23766  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk         (0x4UL)        /*!< CYCP2 (Bitfield-Mask: 0x01)                           */
23767  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos         (1UL)          /*!< CYCP1 (Bit 1)                                         */
23768  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk         (0x2UL)        /*!< CYCP1 (Bitfield-Mask: 0x01)                           */
23769  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos         (0UL)          /*!< CYCP0 (Bit 0)                                         */
23770  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk         (0x1UL)        /*!< CYCP0 (Bitfield-Mask: 0x01)                           */
23771 /* ========================================================  ELIPACR  ======================================================== */
23772  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos         (24UL)         /*!< PLSN (Bit 24)                                         */
23773  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk         (0x1000000UL)  /*!< PLSN (Bitfield-Mask: 0x01)                            */
23774  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos         (16UL)         /*!< PLSP (Bit 16)                                         */
23775  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk         (0x10000UL)    /*!< PLSP (Bitfield-Mask: 0x01)                            */
23776  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos        (13UL)         /*!< CYCN5 (Bit 13)                                        */
23777  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk        (0x2000UL)     /*!< CYCN5 (Bitfield-Mask: 0x01)                           */
23778  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos        (12UL)         /*!< CYCN4 (Bit 12)                                        */
23779  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk        (0x1000UL)     /*!< CYCN4 (Bitfield-Mask: 0x01)                           */
23780  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos        (11UL)         /*!< CYCN3 (Bit 11)                                        */
23781  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk        (0x800UL)      /*!< CYCN3 (Bitfield-Mask: 0x01)                           */
23782  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos        (10UL)         /*!< CYCN2 (Bit 10)                                        */
23783  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk        (0x400UL)      /*!< CYCN2 (Bitfield-Mask: 0x01)                           */
23784  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos        (9UL)          /*!< CYCN1 (Bit 9)                                         */
23785  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk        (0x200UL)      /*!< CYCN1 (Bitfield-Mask: 0x01)                           */
23786  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos        (8UL)          /*!< CYCN0 (Bit 8)                                         */
23787  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk        (0x100UL)      /*!< CYCN0 (Bitfield-Mask: 0x01)                           */
23788  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos        (5UL)          /*!< CYCP5 (Bit 5)                                         */
23789  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk        (0x20UL)       /*!< CYCP5 (Bitfield-Mask: 0x01)                           */
23790  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos        (4UL)          /*!< CYCP4 (Bit 4)                                         */
23791  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk        (0x10UL)       /*!< CYCP4 (Bitfield-Mask: 0x01)                           */
23792  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos        (3UL)          /*!< CYCP3 (Bit 3)                                         */
23793  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk        (0x8UL)        /*!< CYCP3 (Bitfield-Mask: 0x01)                           */
23794  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos        (2UL)          /*!< CYCP2 (Bit 2)                                         */
23795  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk        (0x4UL)        /*!< CYCP2 (Bitfield-Mask: 0x01)                           */
23796  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos        (1UL)          /*!< CYCP1 (Bit 1)                                         */
23797  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk        (0x2UL)        /*!< CYCP1 (Bitfield-Mask: 0x01)                           */
23798  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos        (0UL)          /*!< CYCP0 (Bit 0)                                         */
23799  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk        (0x1UL)        /*!< CYCP0 (Bitfield-Mask: 0x01)                           */
23800 /* =========================================================  STSR  ========================================================== */
23801  #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos            (4UL)          /*!< W10D (Bit 4)                                          */
23802  #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk            (0x10UL)       /*!< W10D (Bitfield-Mask: 0x01)                            */
23803  #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos         (3UL)          /*!< SYNTOUT (Bit 3)                                       */
23804  #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk         (0x8UL)        /*!< SYNTOUT (Bitfield-Mask: 0x01)                         */
23805  #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos         (1UL)          /*!< SYNCOUT (Bit 1)                                       */
23806  #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk         (0x2UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
23807  #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos            (0UL)          /*!< SYNC (Bit 0)                                          */
23808  #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk            (0x1UL)        /*!< SYNC (Bitfield-Mask: 0x01)                            */
23809 /* =========================================================  STIPR  ========================================================= */
23810  #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos           (4UL)          /*!< W10D (Bit 4)                                          */
23811  #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk           (0x10UL)       /*!< W10D (Bitfield-Mask: 0x01)                            */
23812  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos        (3UL)          /*!< SYNTOUT (Bit 3)                                       */
23813  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk        (0x8UL)        /*!< SYNTOUT (Bitfield-Mask: 0x01)                         */
23814  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos        (1UL)          /*!< SYNCOUT (Bit 1)                                       */
23815  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk        (0x2UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
23816  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos           (0UL)          /*!< SYNC (Bit 0)                                          */
23817  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk           (0x1UL)        /*!< SYNC (Bitfield-Mask: 0x01)                            */
23818 /* =========================================================  STCFR  ========================================================= */
23819  #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos           (0UL)          /*!< STCF (Bit 0)                                          */
23820  #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk           (0x3UL)        /*!< STCF (Bitfield-Mask: 0x03)                            */
23821 /* =========================================================  STMR  ========================================================== */
23822  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos           (29UL)         /*!< ALEN1 (Bit 29)                                        */
23823  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk           (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01)                           */
23824  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos           (28UL)         /*!< ALEN0 (Bit 28)                                        */
23825  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk           (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01)                           */
23826  #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos            (20UL)         /*!< DVTH (Bit 20)                                         */
23827  #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk            (0xf00000UL)   /*!< DVTH (Bitfield-Mask: 0x0f)                            */
23828  #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos            (16UL)         /*!< SYTH (Bit 16)                                         */
23829  #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk            (0xf0000UL)    /*!< SYTH (Bitfield-Mask: 0x0f)                            */
23830  #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos            (15UL)         /*!< W10S (Bit 15)                                         */
23831  #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk            (0x8000UL)     /*!< W10S (Bitfield-Mask: 0x01)                            */
23832  #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos            (13UL)         /*!< CMOD (Bit 13)                                         */
23833  #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk            (0x2000UL)     /*!< CMOD (Bitfield-Mask: 0x01)                            */
23834  #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos            (0UL)          /*!< WINT (Bit 0)                                          */
23835  #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk            (0xffUL)       /*!< WINT (Bitfield-Mask: 0xff)                            */
23836 /* ========================================================  SYNTOR  ========================================================= */
23837  #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos        (0UL)          /*!< SYNTOR (Bit 0)                                        */
23838  #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk        (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff)                    */
23839 /* ========================================================  IPTSELR  ======================================================== */
23840  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos      (5UL)          /*!< IPTSEL5 (Bit 5)                                       */
23841  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk      (0x20UL)       /*!< IPTSEL5 (Bitfield-Mask: 0x01)                         */
23842  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos      (4UL)          /*!< IPTSEL4 (Bit 4)                                       */
23843  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk      (0x10UL)       /*!< IPTSEL4 (Bitfield-Mask: 0x01)                         */
23844  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos      (3UL)          /*!< IPTSEL3 (Bit 3)                                       */
23845  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk      (0x8UL)        /*!< IPTSEL3 (Bitfield-Mask: 0x01)                         */
23846  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos      (2UL)          /*!< IPTSEL2 (Bit 2)                                       */
23847  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk      (0x4UL)        /*!< IPTSEL2 (Bitfield-Mask: 0x01)                         */
23848  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos      (1UL)          /*!< IPTSEL1 (Bit 1)                                       */
23849  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk      (0x2UL)        /*!< IPTSEL1 (Bitfield-Mask: 0x01)                         */
23850  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos      (0UL)          /*!< IPTSEL0 (Bit 0)                                       */
23851  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk      (0x1UL)        /*!< IPTSEL0 (Bitfield-Mask: 0x01)                         */
23852 /* ========================================================  MITSELR  ======================================================== */
23853  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos      (5UL)          /*!< MINTEN5 (Bit 5)                                       */
23854  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk      (0x20UL)       /*!< MINTEN5 (Bitfield-Mask: 0x01)                         */
23855  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos      (4UL)          /*!< MINTEN4 (Bit 4)                                       */
23856  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk      (0x10UL)       /*!< MINTEN4 (Bitfield-Mask: 0x01)                         */
23857  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos      (3UL)          /*!< MINTEN3 (Bit 3)                                       */
23858  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk      (0x8UL)        /*!< MINTEN3 (Bitfield-Mask: 0x01)                         */
23859  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos      (2UL)          /*!< MINTEN2 (Bit 2)                                       */
23860  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk      (0x4UL)        /*!< MINTEN2 (Bitfield-Mask: 0x01)                         */
23861  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos      (1UL)          /*!< MINTEN1 (Bit 1)                                       */
23862  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk      (0x2UL)        /*!< MINTEN1 (Bitfield-Mask: 0x01)                         */
23863  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos      (0UL)          /*!< MINTEN0 (Bit 0)                                       */
23864  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk      (0x1UL)        /*!< MINTEN0 (Bitfield-Mask: 0x01)                         */
23865 /* ========================================================  ELTSELR  ======================================================== */
23866  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos      (5UL)          /*!< ELTDIS5 (Bit 5)                                       */
23867  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk      (0x20UL)       /*!< ELTDIS5 (Bitfield-Mask: 0x01)                         */
23868  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos      (4UL)          /*!< ELTDIS4 (Bit 4)                                       */
23869  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk      (0x10UL)       /*!< ELTDIS4 (Bitfield-Mask: 0x01)                         */
23870  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos      (3UL)          /*!< ELTDIS3 (Bit 3)                                       */
23871  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk      (0x8UL)        /*!< ELTDIS3 (Bitfield-Mask: 0x01)                         */
23872  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos      (2UL)          /*!< ELTDIS2 (Bit 2)                                       */
23873  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk      (0x4UL)        /*!< ELTDIS2 (Bitfield-Mask: 0x01)                         */
23874  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos      (1UL)          /*!< ELTDIS1 (Bit 1)                                       */
23875  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk      (0x2UL)        /*!< ELTDIS1 (Bitfield-Mask: 0x01)                         */
23876  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos      (0UL)          /*!< ELTDIS0 (Bit 0)                                       */
23877  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk      (0x1UL)        /*!< ELTDIS0 (Bitfield-Mask: 0x01)                         */
23878 /* =======================================================  STCHSELR  ======================================================== */
23879  #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos       (0UL)          /*!< SYSEL (Bit 0)                                         */
23880  #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk       (0x1UL)        /*!< SYSEL (Bitfield-Mask: 0x01)                           */
23881 /* =======================================================  SYNSTARTR  ======================================================= */
23882  #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos        (0UL)          /*!< STR (Bit 0)                                           */
23883  #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk        (0x1UL)        /*!< STR (Bitfield-Mask: 0x01)                             */
23884 /* ========================================================  LCIVLDR  ======================================================== */
23885  #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos         (0UL)          /*!< LOAD (Bit 0)                                          */
23886  #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk         (0x1UL)        /*!< LOAD (Bitfield-Mask: 0x01)                            */
23887 /* =======================================================  SYNTDARU  ======================================================== */
23888  #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos    (0UL)          /*!< SYNTDARU (Bit 0)                                      */
23889  #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk    (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff)                  */
23890 /* =======================================================  SYNTDARL  ======================================================== */
23891  #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos    (0UL)          /*!< SYNTDARL (Bit 0)                                      */
23892  #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk    (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff)                  */
23893 /* =======================================================  SYNTDBRU  ======================================================== */
23894  #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos    (0UL)          /*!< SYNTDBRU (Bit 0)                                      */
23895  #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk    (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff)                  */
23896 /* =======================================================  SYNTDBRL  ======================================================== */
23897  #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos    (0UL)          /*!< SYNTDBRL (Bit 0)                                      */
23898  #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk    (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff)                  */
23899 /* ========================================================  LCIVRU  ========================================================= */
23900  #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos        (0UL)          /*!< LCIVRU (Bit 0)                                        */
23901  #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk        (0xffffUL)     /*!< LCIVRU (Bitfield-Mask: 0xffff)                        */
23902 /* ========================================================  LCIVRM  ========================================================= */
23903  #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos        (0UL)          /*!< LCIVRM (Bit 0)                                        */
23904  #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk        (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff)                    */
23905 /* ========================================================  LCIVRL  ========================================================= */
23906  #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos        (0UL)          /*!< LCIVRL (Bit 0)                                        */
23907  #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk        (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff)                    */
23908 /* ========================================================  GETW10R  ======================================================== */
23909  #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos         (0UL)          /*!< GW10 (Bit 0)                                          */
23910  #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk         (0x1UL)        /*!< GW10 (Bitfield-Mask: 0x01)                            */
23911 /* =======================================================  PLIMITRU  ======================================================== */
23912  #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos    (0UL)          /*!< PLIMITRU (Bit 0)                                      */
23913  #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk    (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff)                  */
23914 /* =======================================================  PLIMITRM  ======================================================== */
23915  #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos    (0UL)          /*!< PLIMITRM (Bit 0)                                      */
23916  #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk    (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff)                  */
23917 /* =======================================================  PLIMITRL  ======================================================== */
23918  #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos    (0UL)          /*!< PLIMITRL (Bit 0)                                      */
23919  #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk    (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff)                  */
23920 /* =======================================================  MLIMITRU  ======================================================== */
23921  #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos    (0UL)          /*!< MLIMITRU (Bit 0)                                      */
23922  #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk    (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff)                  */
23923 /* =======================================================  MLIMITRM  ======================================================== */
23924  #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos    (0UL)          /*!< MLIMITRM (Bit 0)                                      */
23925  #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk    (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff)                  */
23926 /* =======================================================  MLIMITRL  ======================================================== */
23927  #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos    (0UL)          /*!< MLIMITRL (Bit 0)                                      */
23928  #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk    (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff)                  */
23929 /* =======================================================  GETINFOR  ======================================================== */
23930  #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos        (0UL)          /*!< INFO (Bit 0)                                          */
23931  #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk        (0x1UL)        /*!< INFO (Bitfield-Mask: 0x01)                            */
23932 /* ========================================================  LCCVRU  ========================================================= */
23933  #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos        (0UL)          /*!< LCCVRU (Bit 0)                                        */
23934  #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk        (0xffffUL)     /*!< LCCVRU (Bitfield-Mask: 0xffff)                        */
23935 /* ========================================================  LCCVRM  ========================================================= */
23936  #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos        (0UL)          /*!< LCCVRM (Bit 0)                                        */
23937  #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk        (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff)                    */
23938 /* ========================================================  LCCVRL  ========================================================= */
23939  #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos        (0UL)          /*!< LCCVRL (Bit 0)                                        */
23940  #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk        (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff)                    */
23941 /* ========================================================  PW10VRU  ======================================================== */
23942  #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos      (0UL)          /*!< PW10VRU (Bit 0)                                       */
23943  #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk      (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff)                   */
23944 /* ========================================================  PW10VRM  ======================================================== */
23945  #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos      (0UL)          /*!< PW10VRM (Bit 0)                                       */
23946  #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk      (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff)                   */
23947 /* ========================================================  PW10VRL  ======================================================== */
23948  #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos      (0UL)          /*!< PW10VRL (Bit 0)                                       */
23949  #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk      (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff)                   */
23950 /* ========================================================  MW10RU  ========================================================= */
23951  #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos        (0UL)          /*!< MW10RU (Bit 0)                                        */
23952  #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk        (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff)                    */
23953 /* ========================================================  MW10RM  ========================================================= */
23954  #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos        (0UL)          /*!< MW10RM (Bit 0)                                        */
23955  #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk        (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff)                    */
23956 /* ========================================================  MW10RL  ========================================================= */
23957  #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos        (0UL)          /*!< MW10RL (Bit 0)                                        */
23958  #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk        (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff)                    */
23959 /* =======================================================  TMSTARTR  ======================================================== */
23960  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos         (5UL)          /*!< EN5 (Bit 5)                                           */
23961  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk         (0x20UL)       /*!< EN5 (Bitfield-Mask: 0x01)                             */
23962  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos         (4UL)          /*!< EN4 (Bit 4)                                           */
23963  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk         (0x10UL)       /*!< EN4 (Bitfield-Mask: 0x01)                             */
23964  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos         (3UL)          /*!< EN3 (Bit 3)                                           */
23965  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk         (0x8UL)        /*!< EN3 (Bitfield-Mask: 0x01)                             */
23966  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos         (2UL)          /*!< EN2 (Bit 2)                                           */
23967  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk         (0x4UL)        /*!< EN2 (Bitfield-Mask: 0x01)                             */
23968  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos         (1UL)          /*!< EN1 (Bit 1)                                           */
23969  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk         (0x2UL)        /*!< EN1 (Bitfield-Mask: 0x01)                             */
23970  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos         (0UL)          /*!< EN0 (Bit 0)                                           */
23971  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk         (0x1UL)        /*!< EN0 (Bitfield-Mask: 0x01)                             */
23972 /* =========================================================  PRSR  ========================================================== */
23973  #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos            (29UL)         /*!< URE1 (Bit 29)                                         */
23974  #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk            (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01)                            */
23975  #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos            (28UL)         /*!< URE0 (Bit 28)                                         */
23976  #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk            (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01)                            */
23977  #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos            (8UL)          /*!< MACE (Bit 8)                                          */
23978  #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk            (0x100UL)      /*!< MACE (Bitfield-Mask: 0x01)                            */
23979  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos           (3UL)          /*!< OVRE3 (Bit 3)                                         */
23980  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk           (0x8UL)        /*!< OVRE3 (Bitfield-Mask: 0x01)                           */
23981  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos           (2UL)          /*!< OVRE2 (Bit 2)                                         */
23982  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk           (0x4UL)        /*!< OVRE2 (Bitfield-Mask: 0x01)                           */
23983  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos           (1UL)          /*!< OVRE1 (Bit 1)                                         */
23984  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk           (0x2UL)        /*!< OVRE1 (Bitfield-Mask: 0x01)                           */
23985  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos           (0UL)          /*!< OVRE0 (Bit 0)                                         */
23986  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk           (0x1UL)        /*!< OVRE0 (Bitfield-Mask: 0x01)                           */
23987 /* =========================================================  PRIPR  ========================================================= */
23988  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos           (29UL)         /*!< URE1 (Bit 29)                                         */
23989  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk           (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01)                            */
23990  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos           (28UL)         /*!< URE0 (Bit 28)                                         */
23991  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk           (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01)                            */
23992  #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos           (8UL)          /*!< MACE (Bit 8)                                          */
23993  #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk           (0x100UL)      /*!< MACE (Bitfield-Mask: 0x01)                            */
23994  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos          (3UL)          /*!< OVRE3 (Bit 3)                                         */
23995  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk          (0x8UL)        /*!< OVRE3 (Bitfield-Mask: 0x01)                           */
23996  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos          (2UL)          /*!< OVRE2 (Bit 2)                                         */
23997  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk          (0x4UL)        /*!< OVRE2 (Bitfield-Mask: 0x01)                           */
23998  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos          (1UL)          /*!< OVRE1 (Bit 1)                                         */
23999  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk          (0x2UL)        /*!< OVRE1 (Bitfield-Mask: 0x01)                           */
24000  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos          (0UL)          /*!< OVRE0 (Bit 0)                                         */
24001  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk          (0x1UL)        /*!< OVRE0 (Bitfield-Mask: 0x01)                           */
24002 /* ========================================================  TRNDISR  ======================================================== */
24003  #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos         (0UL)          /*!< TDIS (Bit 0)                                          */
24004  #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk         (0x3UL)        /*!< TDIS (Bitfield-Mask: 0x03)                            */
24005 /* =========================================================  TRNMR  ========================================================= */
24006  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos           (9UL)          /*!< FWD1 (Bit 9)                                          */
24007  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk           (0x200UL)      /*!< FWD1 (Bitfield-Mask: 0x01)                            */
24008  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos           (8UL)          /*!< FWD0 (Bit 8)                                          */
24009  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk           (0x100UL)      /*!< FWD0 (Bitfield-Mask: 0x01)                            */
24010  #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos            (0UL)          /*!< MOD (Bit 0)                                           */
24011  #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk            (0x1UL)        /*!< MOD (Bitfield-Mask: 0x01)                             */
24012 /* =======================================================  TRNCTTDR  ======================================================== */
24013  #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos       (0UL)          /*!< THVAL (Bit 0)                                         */
24014  #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk       (0x7ffUL)      /*!< THVAL (Bitfield-Mask: 0x7ff)                          */
24015 
24016 /* =========================================================================================================================== */
24017 /* ================                                       R_FACI_HP_CMD                                       ================ */
24018 /* =========================================================================================================================== */
24019 
24020 /* ======================================================  FACI_CMD16  ======================================================= */
24021 /* =======================================================  FACI_CMD8  ======================================================= */
24022 
24023 /* =========================================================================================================================== */
24024 /* ================                                         R_FACI_HP                                         ================ */
24025 /* =========================================================================================================================== */
24026 
24027 /* ========================================================  FASTAT  ========================================================= */
24028  #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
24029  #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
24030  #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
24031  #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
24032  #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
24033  #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
24034 /* ========================================================  FAEINT  ========================================================= */
24035  #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
24036  #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
24037  #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
24038  #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
24039  #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
24040  #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
24041 /* ========================================================  FRDYIE  ========================================================= */
24042  #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
24043  #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
24044 /* ========================================================  FSADDR  ========================================================= */
24045  #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
24046  #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
24047 /* ========================================================  FEADDR  ========================================================= */
24048  #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
24049  #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
24050 /* ========================================================  FMEPROT  ======================================================== */
24051  #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
24052  #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24053  #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
24054  #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
24055 /* ========================================================  FBPROT0  ======================================================== */
24056  #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
24057  #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24058  #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
24059  #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
24060 /* ========================================================  FBPROT1  ======================================================== */
24061  #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
24062  #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24063  #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
24064  #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
24065 /* ========================================================  FSTATR  ========================================================= */
24066  #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
24067  #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
24068  #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
24069  #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
24070  #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
24071  #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
24072  #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
24073  #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
24074  #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
24075  #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
24076  #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
24077  #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
24078  #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
24079  #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
24080  #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
24081  #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
24082  #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
24083  #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
24084  #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
24085  #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
24086  #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
24087  #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
24088  #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
24089  #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
24090  #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
24091  #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
24092 /* ========================================================  FENTRYR  ======================================================== */
24093  #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
24094  #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24095  #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
24096  #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
24097  #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
24098  #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
24099 /* =======================================================  FSUINITR  ======================================================== */
24100  #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
24101  #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24102  #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
24103  #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
24104 /* =========================================================  FCMDR  ========================================================= */
24105  #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
24106  #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
24107  #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
24108  #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
24109 /* ========================================================  FBCCNT  ========================================================= */
24110  #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
24111  #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
24112 /* ========================================================  FBCSTAT  ======================================================== */
24113  #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
24114  #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
24115 /* ========================================================  FPSADDR  ======================================================== */
24116  #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
24117  #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
24118 /* ========================================================  FAWMON  ========================================================= */
24119  #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
24120  #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
24121  #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
24122  #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
24123  #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
24124  #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
24125  #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
24126  #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
24127 /* =========================================================  FCPSR  ========================================================= */
24128  #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
24129  #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
24130 /* ========================================================  FPCKAR  ========================================================= */
24131  #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
24132  #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24133  #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
24134  #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
24135 /* ========================================================  FSUACR  ========================================================= */
24136  #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
24137  #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
24138  #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
24139  #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
24140 
24141 /* =========================================================================================================================== */
24142 /* ================                                         R_FCACHE                                          ================ */
24143 /* =========================================================================================================================== */
24144 
24145 /* ========================================================  FCACHEE  ======================================================== */
24146  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
24147  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
24148 /* =======================================================  FCACHEIV  ======================================================== */
24149  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
24150  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
24151 /* =========================================================  FLWT  ========================================================== */
24152  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
24153  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
24154 /* =========================================================  FSAR  ========================================================== */
24155  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
24156  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
24157  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
24158  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
24159 
24160 /* =========================================================================================================================== */
24161 /* ================                                          R_GLCDC                                          ================ */
24162 /* =========================================================================================================================== */
24163 
24164 /* =======================================================  GR1_CLUT0  ======================================================= */
24165  #define R_GLCDC_GR1_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
24166  #define R_GLCDC_GR1_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
24167  #define R_GLCDC_GR1_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
24168  #define R_GLCDC_GR1_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
24169  #define R_GLCDC_GR1_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
24170  #define R_GLCDC_GR1_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
24171  #define R_GLCDC_GR1_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
24172  #define R_GLCDC_GR1_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
24173 /* =======================================================  GR1_CLUT1  ======================================================= */
24174  #define R_GLCDC_GR1_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
24175  #define R_GLCDC_GR1_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
24176  #define R_GLCDC_GR1_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
24177  #define R_GLCDC_GR1_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
24178  #define R_GLCDC_GR1_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
24179  #define R_GLCDC_GR1_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
24180  #define R_GLCDC_GR1_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
24181  #define R_GLCDC_GR1_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
24182 /* =======================================================  GR2_CLUT0  ======================================================= */
24183  #define R_GLCDC_GR2_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
24184  #define R_GLCDC_GR2_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
24185  #define R_GLCDC_GR2_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
24186  #define R_GLCDC_GR2_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
24187  #define R_GLCDC_GR2_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
24188  #define R_GLCDC_GR2_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
24189  #define R_GLCDC_GR2_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
24190  #define R_GLCDC_GR2_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
24191 /* =======================================================  GR2_CLUT1  ======================================================= */
24192  #define R_GLCDC_GR2_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
24193  #define R_GLCDC_GR2_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
24194  #define R_GLCDC_GR2_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
24195  #define R_GLCDC_GR2_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
24196  #define R_GLCDC_GR2_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
24197  #define R_GLCDC_GR2_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
24198  #define R_GLCDC_GR2_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
24199  #define R_GLCDC_GR2_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
24200 
24201 /* =========================================================================================================================== */
24202 /* ================                                          R_GPT0                                           ================ */
24203 /* =========================================================================================================================== */
24204 
24205 /* =========================================================  GTWP  ========================================================== */
24206  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
24207  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
24208  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
24209  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
24210  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
24211  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
24212  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
24213  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
24214  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
24215  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
24216  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
24217  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
24218 /* =========================================================  GTSTR  ========================================================= */
24219  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
24220  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
24221 /* =========================================================  GTSTP  ========================================================= */
24222  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
24223  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
24224 /* =========================================================  GTCLR  ========================================================= */
24225  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
24226  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
24227 /* =========================================================  GTSSR  ========================================================= */
24228  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
24229  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
24230  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
24231  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
24232  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
24233  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
24234  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
24235  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
24236  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
24237  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
24238  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
24239  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
24240  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
24241  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
24242  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
24243  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
24244  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
24245  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
24246  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
24247  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
24248  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
24249  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
24250  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
24251  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
24252 /* =========================================================  GTPSR  ========================================================= */
24253  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
24254  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
24255  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
24256  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
24257  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
24258  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
24259  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
24260  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
24261  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
24262  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
24263  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
24264  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
24265  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
24266  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
24267  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
24268  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
24269  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
24270  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
24271  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
24272  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
24273  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
24274  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
24275  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
24276  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
24277 /* =========================================================  GTCSR  ========================================================= */
24278  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
24279  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
24280  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
24281  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
24282  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
24283  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
24284  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
24285  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
24286  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
24287  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
24288  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
24289  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
24290  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
24291  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
24292  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
24293  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
24294  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
24295  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
24296  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
24297  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
24298  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
24299  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
24300  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
24301  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
24302  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
24303  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
24304  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
24305  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
24306 /* ========================================================  GTUPSR  ========================================================= */
24307  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
24308  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
24309  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
24310  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
24311  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
24312  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
24313  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
24314  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
24315  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
24316  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
24317  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
24318  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
24319  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
24320  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
24321  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
24322  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
24323  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
24324  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
24325  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
24326  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
24327  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
24328  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
24329  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
24330  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
24331 /* ========================================================  GTDNSR  ========================================================= */
24332  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
24333  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
24334  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
24335  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
24336  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
24337  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
24338  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
24339  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
24340  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
24341  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
24342  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
24343  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
24344  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
24345  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
24346  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
24347  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
24348  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
24349  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
24350  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
24351  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
24352  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
24353  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
24354  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
24355  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
24356 /* ========================================================  GTICASR  ======================================================== */
24357  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
24358  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
24359  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
24360  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
24361  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
24362  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
24363  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
24364  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
24365  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
24366  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
24367  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
24368  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
24369  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
24370  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
24371  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
24372  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
24373  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
24374  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
24375  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
24376  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
24377  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
24378  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
24379 /* ========================================================  GTICBSR  ======================================================== */
24380  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
24381  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
24382  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
24383  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
24384  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
24385  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
24386  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
24387  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
24388  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
24389  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
24390  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
24391  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
24392  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
24393  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
24394  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
24395  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
24396  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
24397  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
24398  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
24399  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
24400  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
24401  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
24402 /* =========================================================  GTCR  ========================================================== */
24403  #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
24404  #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
24405  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
24406  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
24407  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
24408  #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
24409  #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
24410  #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
24411  #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
24412  #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
24413  #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
24414  #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
24415  #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
24416  #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
24417  #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
24418  #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
24419  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
24420  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
24421 /* =======================================================  GTUDDTYC  ======================================================== */
24422  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
24423  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
24424  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
24425  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
24426  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
24427  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
24428  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
24429  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
24430  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
24431  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
24432  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
24433  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
24434  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
24435  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
24436  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
24437  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
24438 /* =========================================================  GTIOR  ========================================================= */
24439  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
24440  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
24441  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
24442  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
24443  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
24444  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
24445  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
24446  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
24447  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
24448  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
24449  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
24450  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
24451  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
24452  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
24453  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
24454  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
24455  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
24456  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
24457  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
24458  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
24459  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
24460  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
24461  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
24462  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
24463  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
24464  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
24465  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
24466  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
24467  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
24468  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
24469  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
24470  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
24471  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
24472  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
24473  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
24474  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
24475 /* ========================================================  GTINTAD  ======================================================== */
24476  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
24477  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
24478  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
24479  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
24480  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
24481  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
24482  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
24483  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
24484  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
24485  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
24486  #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
24487  #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
24488  #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
24489  #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
24490  #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
24491  #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
24492  #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
24493  #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
24494  #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
24495  #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
24496 /* =========================================================  GTST  ========================================================== */
24497  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
24498  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
24499  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
24500  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
24501  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
24502  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
24503  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
24504  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
24505  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
24506  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
24507  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
24508  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
24509  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
24510  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
24511  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
24512  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
24513  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
24514  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
24515  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
24516  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
24517  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
24518  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
24519  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
24520  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
24521  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
24522  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
24523  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
24524  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
24525  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
24526  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
24527  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
24528  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
24529  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
24530  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
24531  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
24532  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
24533  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
24534  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
24535 /* =========================================================  GTBER  ========================================================= */
24536  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
24537  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
24538  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
24539  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
24540  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
24541  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
24542  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
24543  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
24544  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
24545  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
24546  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
24547  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
24548  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
24549  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
24550  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
24551  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
24552  #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
24553  #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
24554  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
24555  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
24556  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
24557  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
24558  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
24559  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
24560  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
24561  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
24562 /* =========================================================  GTITC  ========================================================= */
24563  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
24564  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
24565  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
24566  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
24567  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
24568  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
24569  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
24570  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
24571  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
24572  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
24573  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
24574  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
24575  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
24576  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
24577  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
24578  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
24579  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
24580  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
24581  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
24582  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
24583 /* =========================================================  GTCNT  ========================================================= */
24584  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
24585  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
24586 /* =========================================================  GTCCR  ========================================================= */
24587  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
24588  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
24589 /* =========================================================  GTPR  ========================================================== */
24590  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
24591  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
24592 /* =========================================================  GTPBR  ========================================================= */
24593  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
24594  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
24595 /* ========================================================  GTPDBR  ========================================================= */
24596  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
24597  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
24598 /* ========================================================  GTADTRA  ======================================================== */
24599  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
24600  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
24601 /* ========================================================  GTADTRB  ======================================================== */
24602  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
24603  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
24604 /* =======================================================  GTADTBRA  ======================================================== */
24605  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
24606  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
24607 /* =======================================================  GTADTBRB  ======================================================== */
24608  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
24609  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
24610 /* =======================================================  GTADTDBRA  ======================================================= */
24611  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
24612  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
24613 /* =======================================================  GTADTDBRB  ======================================================= */
24614  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
24615  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
24616 /* ========================================================  GTDTCR  ========================================================= */
24617  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
24618  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
24619  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
24620  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
24621  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
24622  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
24623  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
24624  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
24625 /* =========================================================  GTDVU  ========================================================= */
24626  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
24627  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
24628 /* =========================================================  GTDVD  ========================================================= */
24629  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
24630  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
24631 /* =========================================================  GTDBU  ========================================================= */
24632  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
24633  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
24634 /* =========================================================  GTDBD  ========================================================= */
24635  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
24636  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
24637 /* =========================================================  GTSOS  ========================================================= */
24638  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
24639  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
24640 /* ========================================================  GTSOTR  ========================================================= */
24641  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
24642  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
24643 /* ========================================================  GTADSMR  ======================================================== */
24644  #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
24645  #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
24646  #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
24647  #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
24648  #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
24649  #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
24650  #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
24651  #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
24652 /* ========================================================  GTEITC  ========================================================= */
24653  #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
24654  #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
24655  #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
24656  #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
24657  #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
24658  #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
24659  #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
24660  #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
24661  #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
24662  #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
24663  #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
24664  #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
24665  #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
24666  #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
24667 /* =======================================================  GTEITLI1  ======================================================== */
24668  #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
24669  #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
24670  #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
24671  #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
24672  #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
24673  #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
24674  #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
24675  #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
24676  #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
24677  #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
24678  #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
24679  #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
24680  #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
24681  #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
24682  #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
24683  #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
24684 /* =======================================================  GTEITLI2  ======================================================== */
24685  #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
24686  #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
24687  #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
24688  #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
24689 /* ========================================================  GTEITLB  ======================================================== */
24690  #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
24691  #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
24692  #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
24693  #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
24694  #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
24695  #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
24696  #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
24697  #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
24698  #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
24699  #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
24700  #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
24701  #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
24702  #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
24703  #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
24704 /* ========================================================  GTICLF  ========================================================= */
24705  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
24706  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
24707  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
24708  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
24709  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
24710  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
24711  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
24712  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
24713 /* =========================================================  GTPC  ========================================================== */
24714  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
24715  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
24716  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
24717  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
24718  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
24719  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
24720 /* ========================================================  GTSECSR  ======================================================== */
24721  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
24722  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
24723  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
24724  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
24725  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
24726  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
24727  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
24728  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
24729  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
24730  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
24731  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
24732  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
24733  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
24734  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
24735  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
24736  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
24737  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
24738  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
24739  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
24740  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
24741 /* ========================================================  GTSECR  ========================================================= */
24742  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
24743  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
24744  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
24745  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
24746  #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
24747  #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
24748  #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
24749  #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
24750  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
24751  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
24752  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
24753  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
24754  #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
24755  #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
24756  #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
24757  #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
24758  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
24759  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
24760  #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
24761  #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
24762  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
24763  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
24764  #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
24765  #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
24766 /* ========================================================  GTBER2  ========================================================= */
24767  #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
24768  #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
24769  #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
24770  #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
24771  #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
24772  #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
24773  #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
24774  #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
24775  #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
24776  #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
24777  #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
24778  #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
24779  #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
24780  #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
24781  #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
24782  #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
24783  #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
24784  #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
24785  #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
24786  #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
24787  #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
24788  #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
24789  #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
24790  #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
24791  #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
24792  #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
24793  #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
24794  #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
24795  #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
24796  #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
24797  #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
24798  #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
24799  #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
24800  #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
24801  #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
24802  #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
24803  #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
24804  #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
24805  #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
24806  #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
24807 /* ========================================================  GTOLBR  ========================================================= */
24808  #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
24809  #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
24810  #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
24811  #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
24812 /* ========================================================  GTICCR  ========================================================= */
24813  #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
24814  #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
24815  #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
24816  #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
24817  #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
24818  #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
24819  #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
24820  #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
24821  #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
24822  #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
24823  #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
24824  #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
24825  #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
24826  #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
24827  #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
24828  #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
24829  #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
24830  #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
24831  #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
24832  #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
24833  #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
24834  #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
24835  #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
24836  #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
24837  #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
24838  #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
24839  #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
24840  #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
24841  #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
24842  #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
24843  #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
24844  #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
24845  #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
24846  #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
24847  #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
24848  #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
24849  #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
24850  #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
24851  #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
24852  #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
24853 
24854 /* =========================================================================================================================== */
24855 /* ================                                         R_GPT_ODC                                         ================ */
24856 /* =========================================================================================================================== */
24857 
24858 /* =======================================================  GTDLYCR1  ======================================================== */
24859  #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos     (8UL)      /*!< FRANGE (Bit 8)                                        */
24860  #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk     (0x100UL)  /*!< FRANGE (Bitfield-Mask: 0x01)                          */
24861  #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos     (1UL)      /*!< DLYRST (Bit 1)                                        */
24862  #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk     (0x2UL)    /*!< DLYRST (Bitfield-Mask: 0x01)                          */
24863  #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos      (0UL)      /*!< DLLEN (Bit 0)                                         */
24864  #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk      (0x1UL)    /*!< DLLEN (Bitfield-Mask: 0x01)                           */
24865 /* =======================================================  GTDLYCR2  ======================================================== */
24866  #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos    (12UL)     /*!< DLYDENB (Bit 12)                                      */
24867  #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk    (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01)                         */
24868  #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos      (8UL)      /*!< DLYEN (Bit 8)                                         */
24869  #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk      (0x100UL)  /*!< DLYEN (Bitfield-Mask: 0x01)                           */
24870  #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos      (0UL)      /*!< DLYBS (Bit 0)                                         */
24871  #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk      (0x1UL)    /*!< DLYBS (Bitfield-Mask: 0x01)                           */
24872 
24873 /* =========================================================================================================================== */
24874 /* ================                                         R_GPT_OPS                                         ================ */
24875 /* =========================================================================================================================== */
24876 
24877 /* =========================================================  OPSCR  ========================================================= */
24878  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
24879  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
24880  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
24881  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
24882  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
24883  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
24884  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
24885  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
24886  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
24887  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
24888  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
24889  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
24890  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
24891  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
24892  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
24893  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
24894  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
24895  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
24896  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
24897  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
24898  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
24899  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
24900  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
24901  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
24902  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
24903  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
24904  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
24905  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
24906  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
24907  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
24908  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
24909  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
24910  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
24911  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
24912 
24913 /* =========================================================================================================================== */
24914 /* ================                                        R_GPT_POEG0                                        ================ */
24915 /* =========================================================================================================================== */
24916 
24917 /* =========================================================  POEGG  ========================================================= */
24918  #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
24919  #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
24920  #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
24921  #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
24922  #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
24923  #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
24924  #define R_GPT_POEG0_POEGG_DERRE_Pos      (26UL)         /*!< DERRE (Bit 26)                                        */
24925  #define R_GPT_POEG0_POEGG_DERRE_Msk      (0x4000000UL)  /*!< DERRE (Bitfield-Mask: 0x01)                           */
24926  #define R_GPT_POEG0_POEGG_DERRST_Pos     (24UL)         /*!< DERRST (Bit 24)                                       */
24927  #define R_GPT_POEG0_POEGG_DERRST_Msk     (0x1000000UL)  /*!< DERRST (Bitfield-Mask: 0x01)                          */
24928  #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
24929  #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
24930  #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
24931  #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
24932  #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
24933  #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
24934  #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
24935  #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
24936  #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
24937  #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
24938  #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
24939  #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
24940  #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
24941  #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
24942  #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
24943  #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
24944  #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
24945  #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
24946 /* ========================================================  GTONCWP  ======================================================== */
24947  #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
24948  #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
24949  #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
24950  #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
24951 /* ========================================================  GTONCCR  ======================================================== */
24952  #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
24953  #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
24954  #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
24955  #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
24956  #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
24957  #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */
24958 
24959 /* =========================================================================================================================== */
24960 /* ================                                           R_ICU                                           ================ */
24961 /* =========================================================================================================================== */
24962 
24963 /* =========================================================  IRQCR  ========================================================= */
24964  #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
24965  #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
24966  #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
24967  #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
24968  #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
24969  #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
24970 /* =========================================================  NMISR  ========================================================= */
24971  #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
24972  #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
24973  #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
24974  #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
24975  #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
24976  #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
24977  #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
24978  #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
24979  #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
24980  #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
24981  #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
24982  #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
24983  #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
24984  #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
24985  #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
24986  #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
24987  #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
24988  #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
24989  #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
24990  #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
24991  #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
24992  #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
24993  #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
24994  #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
24995  #define R_ICU_NMISR_TZFST_Pos           (13UL)         /*!< TZFST (Bit 13)                                        */
24996  #define R_ICU_NMISR_TZFST_Msk           (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
24997  #define R_ICU_NMISR_CPEST_Pos           (15UL)         /*!< CPEST (Bit 15)                                        */
24998  #define R_ICU_NMISR_CPEST_Msk           (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
24999 /* =========================================================  NMIER  ========================================================= */
25000  #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
25001  #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
25002  #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
25003  #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
25004  #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
25005  #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
25006  #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
25007  #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
25008  #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
25009  #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
25010  #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
25011  #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
25012  #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
25013  #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
25014  #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
25015  #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
25016  #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
25017  #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
25018  #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
25019  #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
25020  #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
25021  #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
25022  #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
25023  #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
25024  #define R_ICU_NMIER_TZFEN_Pos           (13UL)         /*!< TZFEN (Bit 13)                                        */
25025  #define R_ICU_NMIER_TZFEN_Msk           (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
25026  #define R_ICU_NMIER_CPEEN_Pos           (15UL)         /*!< CPEEN (Bit 15)                                        */
25027  #define R_ICU_NMIER_CPEEN_Msk           (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
25028 /* ========================================================  NMICLR  ========================================================= */
25029  #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
25030  #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
25031  #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
25032  #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
25033  #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
25034  #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
25035  #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
25036  #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
25037  #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
25038  #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
25039  #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
25040  #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
25041  #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
25042  #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
25043  #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
25044  #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
25045  #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
25046  #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
25047  #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
25048  #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
25049  #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
25050  #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
25051  #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
25052  #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
25053  #define R_ICU_NMICLR_TZFCLR_Pos         (13UL)         /*!< TZFCLR (Bit 13)                                       */
25054  #define R_ICU_NMICLR_TZFCLR_Msk         (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
25055  #define R_ICU_NMICLR_CPECLR_Pos         (15UL)         /*!< CPECLR (Bit 15)                                       */
25056  #define R_ICU_NMICLR_CPECLR_Msk         (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
25057 /* =========================================================  NMICR  ========================================================= */
25058  #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
25059  #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
25060  #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
25061  #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
25062  #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
25063  #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
25064 /* =========================================================  IELSR  ========================================================= */
25065  #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
25066  #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
25067  #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
25068  #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
25069  #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
25070  #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
25071 /* =========================================================  DELSR  ========================================================= */
25072  #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
25073  #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
25074  #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
25075  #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
25076 /* ========================================================  SELSR0  ========================================================= */
25077  #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
25078  #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
25079 /* =========================================================  WUPEN  ========================================================= */
25080  #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
25081  #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
25082  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
25083  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
25084  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
25085  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
25086  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
25087  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
25088  #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
25089  #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
25090  #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
25091  #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
25092  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
25093  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
25094  #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
25095  #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
25096  #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
25097  #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
25098  #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
25099  #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
25100  #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
25101  #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
25102  #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
25103  #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
25104  #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
25105  #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
25106  #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
25107  #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
25108  #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
25109  #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
25110  #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
25111  #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
25112 /* ========================================================  WUPEN1  ========================================================= */
25113  #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos    (0UL)          /*!< AGT3UDWUPEN (Bit 0)                                   */
25114  #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk    (0x1UL)        /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01)                     */
25115  #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos    (1UL)          /*!< AGT3CAWUPEN (Bit 1)                                   */
25116  #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk    (0x2UL)        /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01)                     */
25117  #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos    (2UL)          /*!< AGT3CBWUPEN (Bit 2)                                   */
25118  #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk    (0x4UL)        /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01)                     */
25119 /* =========================================================  IELEN  ========================================================= */
25120  #define R_ICU_IELEN_IELEN_Pos           (1UL)          /*!< IELEN (Bit 1)                                         */
25121  #define R_ICU_IELEN_IELEN_Msk           (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
25122  #define R_ICU_IELEN_RTCINTEN_Pos        (0UL)          /*!< RTCINTEN (Bit 0)                                      */
25123  #define R_ICU_IELEN_RTCINTEN_Msk        (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
25124 
25125 /* =========================================================================================================================== */
25126 /* ================                                          R_IIC0                                           ================ */
25127 /* =========================================================================================================================== */
25128 
25129 /* =========================================================  ICCR1  ========================================================= */
25130  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
25131  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
25132  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
25133  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
25134  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
25135  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
25136  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
25137  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
25138  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
25139  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
25140  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
25141  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
25142  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
25143  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
25144  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
25145  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
25146 /* =========================================================  ICCR2  ========================================================= */
25147  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
25148  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
25149  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
25150  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
25151  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
25152  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
25153  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
25154  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
25155  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
25156  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
25157  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
25158  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
25159 /* =========================================================  ICMR1  ========================================================= */
25160  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
25161  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
25162  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
25163  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
25164  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
25165  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
25166  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
25167  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
25168 /* =========================================================  ICMR2  ========================================================= */
25169  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
25170  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
25171  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
25172  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
25173  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
25174  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
25175  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
25176  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
25177  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
25178  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
25179 /* =========================================================  ICMR3  ========================================================= */
25180  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
25181  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
25182  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
25183  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
25184  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
25185  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
25186  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
25187  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
25188  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
25189  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
25190  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
25191  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
25192  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
25193  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
25194 /* =========================================================  ICFER  ========================================================= */
25195  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
25196  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
25197  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
25198  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
25199  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
25200  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
25201  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
25202  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
25203  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
25204  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
25205  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
25206  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
25207  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
25208  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
25209  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
25210  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
25211 /* =========================================================  ICSER  ========================================================= */
25212  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
25213  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
25214  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
25215  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
25216  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
25217  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
25218  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
25219  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
25220  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
25221  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
25222  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
25223  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
25224 /* =========================================================  ICIER  ========================================================= */
25225  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
25226  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
25227  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
25228  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
25229  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
25230  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
25231  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
25232  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
25233  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
25234  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
25235  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
25236  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
25237  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
25238  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
25239  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
25240  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
25241 /* =========================================================  ICSR1  ========================================================= */
25242  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
25243  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
25244  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
25245  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
25246  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
25247  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
25248  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
25249  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
25250  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
25251  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
25252  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
25253  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
25254 /* =========================================================  ICSR2  ========================================================= */
25255  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
25256  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
25257  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
25258  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
25259  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
25260  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
25261  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
25262  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
25263  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
25264  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
25265  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
25266  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
25267  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
25268  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
25269  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
25270  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
25271 /* =========================================================  ICBRL  ========================================================= */
25272  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
25273  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
25274 /* =========================================================  ICBRH  ========================================================= */
25275  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
25276  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
25277 /* =========================================================  ICDRT  ========================================================= */
25278  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
25279  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
25280 /* =========================================================  ICDRR  ========================================================= */
25281  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
25282  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
25283 /* =========================================================  ICWUR  ========================================================= */
25284  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
25285  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
25286  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
25287  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
25288  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
25289  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
25290  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
25291  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
25292  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
25293  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
25294 /* ========================================================  ICWUR2  ========================================================= */
25295  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
25296  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
25297  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
25298  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
25299  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
25300  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
25301 
25302 /* =========================================================================================================================== */
25303 /* ================                                          R_IRDA                                           ================ */
25304 /* =========================================================================================================================== */
25305 
25306 /* =========================================================  IRCR  ========================================================== */
25307  #define R_IRDA_IRCR_IRE_Pos        (7UL)    /*!< IRE (Bit 7)                                           */
25308  #define R_IRDA_IRCR_IRE_Msk        (0x80UL) /*!< IRE (Bitfield-Mask: 0x01)                             */
25309  #define R_IRDA_IRCR_IRTXINV_Pos    (3UL)    /*!< IRTXINV (Bit 3)                                       */
25310  #define R_IRDA_IRCR_IRTXINV_Msk    (0x8UL)  /*!< IRTXINV (Bitfield-Mask: 0x01)                         */
25311  #define R_IRDA_IRCR_IRRXINV_Pos    (2UL)    /*!< IRRXINV (Bit 2)                                       */
25312  #define R_IRDA_IRCR_IRRXINV_Msk    (0x4UL)  /*!< IRRXINV (Bitfield-Mask: 0x01)                         */
25313 
25314 /* =========================================================================================================================== */
25315 /* ================                                          R_IWDT                                           ================ */
25316 /* =========================================================================================================================== */
25317 
25318 /* ========================================================  IWDTRR  ========================================================= */
25319  #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
25320  #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
25321 /* ========================================================  IWDTCR  ========================================================= */
25322  #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
25323  #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
25324  #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
25325  #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
25326  #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
25327  #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
25328  #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
25329  #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
25330 /* ========================================================  IWDTSR  ========================================================= */
25331  #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
25332  #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
25333  #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
25334  #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
25335  #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
25336  #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
25337 /* ========================================================  IWDTRCR  ======================================================== */
25338  #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
25339  #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
25340 /* =======================================================  IWDTCSTPR  ======================================================= */
25341  #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
25342  #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
25343 
25344 /* =========================================================================================================================== */
25345 /* ================                                          R_JPEG                                           ================ */
25346 /* =========================================================================================================================== */
25347 
25348 /* =========================================================  JCMOD  ========================================================= */
25349  #define R_JPEG_JCMOD_DSP_Pos           (3UL)          /*!< DSP (Bit 3)                                           */
25350  #define R_JPEG_JCMOD_DSP_Msk           (0x8UL)        /*!< DSP (Bitfield-Mask: 0x01)                             */
25351  #define R_JPEG_JCMOD_REDU_Pos          (0UL)          /*!< REDU (Bit 0)                                          */
25352  #define R_JPEG_JCMOD_REDU_Msk          (0x7UL)        /*!< REDU (Bitfield-Mask: 0x07)                            */
25353 /* =========================================================  JCCMD  ========================================================= */
25354  #define R_JPEG_JCCMD_BRST_Pos          (7UL)          /*!< BRST (Bit 7)                                          */
25355  #define R_JPEG_JCCMD_BRST_Msk          (0x80UL)       /*!< BRST (Bitfield-Mask: 0x01)                            */
25356  #define R_JPEG_JCCMD_JEND_Pos          (2UL)          /*!< JEND (Bit 2)                                          */
25357  #define R_JPEG_JCCMD_JEND_Msk          (0x4UL)        /*!< JEND (Bitfield-Mask: 0x01)                            */
25358  #define R_JPEG_JCCMD_JRST_Pos          (1UL)          /*!< JRST (Bit 1)                                          */
25359  #define R_JPEG_JCCMD_JRST_Msk          (0x2UL)        /*!< JRST (Bitfield-Mask: 0x01)                            */
25360  #define R_JPEG_JCCMD_JSRT_Pos          (0UL)          /*!< JSRT (Bit 0)                                          */
25361  #define R_JPEG_JCCMD_JSRT_Msk          (0x1UL)        /*!< JSRT (Bitfield-Mask: 0x01)                            */
25362 /* =========================================================  JCQTN  ========================================================= */
25363  #define R_JPEG_JCQTN_QT3_Pos           (4UL)          /*!< QT3 (Bit 4)                                           */
25364  #define R_JPEG_JCQTN_QT3_Msk           (0x30UL)       /*!< QT3 (Bitfield-Mask: 0x03)                             */
25365  #define R_JPEG_JCQTN_QT2_Pos           (2UL)          /*!< QT2 (Bit 2)                                           */
25366  #define R_JPEG_JCQTN_QT2_Msk           (0xcUL)        /*!< QT2 (Bitfield-Mask: 0x03)                             */
25367  #define R_JPEG_JCQTN_QT1_Pos           (0UL)          /*!< QT1 (Bit 0)                                           */
25368  #define R_JPEG_JCQTN_QT1_Msk           (0x3UL)        /*!< QT1 (Bitfield-Mask: 0x03)                             */
25369 /* =========================================================  JCHTN  ========================================================= */
25370  #define R_JPEG_JCHTN_HTA3_Pos          (5UL)          /*!< HTA3 (Bit 5)                                          */
25371  #define R_JPEG_JCHTN_HTA3_Msk          (0x20UL)       /*!< HTA3 (Bitfield-Mask: 0x01)                            */
25372  #define R_JPEG_JCHTN_HTD3_Pos          (4UL)          /*!< HTD3 (Bit 4)                                          */
25373  #define R_JPEG_JCHTN_HTD3_Msk          (0x10UL)       /*!< HTD3 (Bitfield-Mask: 0x01)                            */
25374  #define R_JPEG_JCHTN_HTA2_Pos          (3UL)          /*!< HTA2 (Bit 3)                                          */
25375  #define R_JPEG_JCHTN_HTA2_Msk          (0x8UL)        /*!< HTA2 (Bitfield-Mask: 0x01)                            */
25376  #define R_JPEG_JCHTN_HTD2_Pos          (2UL)          /*!< HTD2 (Bit 2)                                          */
25377  #define R_JPEG_JCHTN_HTD2_Msk          (0x4UL)        /*!< HTD2 (Bitfield-Mask: 0x01)                            */
25378  #define R_JPEG_JCHTN_HTA1_Pos          (1UL)          /*!< HTA1 (Bit 1)                                          */
25379  #define R_JPEG_JCHTN_HTA1_Msk          (0x2UL)        /*!< HTA1 (Bitfield-Mask: 0x01)                            */
25380  #define R_JPEG_JCHTN_HTD1_Pos          (0UL)          /*!< HTD1 (Bit 0)                                          */
25381  #define R_JPEG_JCHTN_HTD1_Msk          (0x1UL)        /*!< HTD1 (Bitfield-Mask: 0x01)                            */
25382 /* ========================================================  JCDRIU  ========================================================= */
25383  #define R_JPEG_JCDRIU_DRIU_Pos         (0UL)          /*!< DRIU (Bit 0)                                          */
25384  #define R_JPEG_JCDRIU_DRIU_Msk         (0xffUL)       /*!< DRIU (Bitfield-Mask: 0xff)                            */
25385 /* ========================================================  JCDRID  ========================================================= */
25386  #define R_JPEG_JCDRID_DRID_Pos         (0UL)          /*!< DRID (Bit 0)                                          */
25387  #define R_JPEG_JCDRID_DRID_Msk         (0xffUL)       /*!< DRID (Bitfield-Mask: 0xff)                            */
25388 /* ========================================================  JCVSZU  ========================================================= */
25389  #define R_JPEG_JCVSZU_VSZU_Pos         (0UL)          /*!< VSZU (Bit 0)                                          */
25390  #define R_JPEG_JCVSZU_VSZU_Msk         (0xffUL)       /*!< VSZU (Bitfield-Mask: 0xff)                            */
25391 /* ========================================================  JCVSZD  ========================================================= */
25392  #define R_JPEG_JCVSZD_VSZD_Pos         (0UL)          /*!< VSZD (Bit 0)                                          */
25393  #define R_JPEG_JCVSZD_VSZD_Msk         (0xffUL)       /*!< VSZD (Bitfield-Mask: 0xff)                            */
25394 /* ========================================================  JCHSZU  ========================================================= */
25395  #define R_JPEG_JCHSZU_HSZU_Pos         (0UL)          /*!< HSZU (Bit 0)                                          */
25396  #define R_JPEG_JCHSZU_HSZU_Msk         (0xffUL)       /*!< HSZU (Bitfield-Mask: 0xff)                            */
25397 /* ========================================================  JCHSZD  ========================================================= */
25398  #define R_JPEG_JCHSZD_HSZD_Pos         (0UL)          /*!< HSZD (Bit 0)                                          */
25399  #define R_JPEG_JCHSZD_HSZD_Msk         (0xffUL)       /*!< HSZD (Bitfield-Mask: 0xff)                            */
25400 /* ========================================================  JCDTCU  ========================================================= */
25401  #define R_JPEG_JCDTCU_DCU_Pos          (0UL)          /*!< DCU (Bit 0)                                           */
25402  #define R_JPEG_JCDTCU_DCU_Msk          (0xffUL)       /*!< DCU (Bitfield-Mask: 0xff)                             */
25403 /* ========================================================  JCDTCM  ========================================================= */
25404  #define R_JPEG_JCDTCM_DCM_Pos          (0UL)          /*!< DCM (Bit 0)                                           */
25405  #define R_JPEG_JCDTCM_DCM_Msk          (0xffUL)       /*!< DCM (Bitfield-Mask: 0xff)                             */
25406 /* ========================================================  JCDTCD  ========================================================= */
25407  #define R_JPEG_JCDTCD_DCD_Pos          (0UL)          /*!< DCD (Bit 0)                                           */
25408  #define R_JPEG_JCDTCD_DCD_Msk          (0xffUL)       /*!< DCD (Bitfield-Mask: 0xff)                             */
25409 /* ========================================================  JINTE0  ========================================================= */
25410  #define R_JPEG_JINTE0_INT7_Pos         (7UL)          /*!< INT7 (Bit 7)                                          */
25411  #define R_JPEG_JINTE0_INT7_Msk         (0x80UL)       /*!< INT7 (Bitfield-Mask: 0x01)                            */
25412  #define R_JPEG_JINTE0_INT6_Pos         (6UL)          /*!< INT6 (Bit 6)                                          */
25413  #define R_JPEG_JINTE0_INT6_Msk         (0x40UL)       /*!< INT6 (Bitfield-Mask: 0x01)                            */
25414  #define R_JPEG_JINTE0_INT5_Pos         (5UL)          /*!< INT5 (Bit 5)                                          */
25415  #define R_JPEG_JINTE0_INT5_Msk         (0x20UL)       /*!< INT5 (Bitfield-Mask: 0x01)                            */
25416  #define R_JPEG_JINTE0_INT3_Pos         (3UL)          /*!< INT3 (Bit 3)                                          */
25417  #define R_JPEG_JINTE0_INT3_Msk         (0x8UL)        /*!< INT3 (Bitfield-Mask: 0x01)                            */
25418 /* ========================================================  JINTS0  ========================================================= */
25419  #define R_JPEG_JINTS0_INS6_Pos         (6UL)          /*!< INS6 (Bit 6)                                          */
25420  #define R_JPEG_JINTS0_INS6_Msk         (0x40UL)       /*!< INS6 (Bitfield-Mask: 0x01)                            */
25421  #define R_JPEG_JINTS0_INS5_Pos         (5UL)          /*!< INS5 (Bit 5)                                          */
25422  #define R_JPEG_JINTS0_INS5_Msk         (0x20UL)       /*!< INS5 (Bitfield-Mask: 0x01)                            */
25423  #define R_JPEG_JINTS0_INS3_Pos         (3UL)          /*!< INS3 (Bit 3)                                          */
25424  #define R_JPEG_JINTS0_INS3_Msk         (0x8UL)        /*!< INS3 (Bitfield-Mask: 0x01)                            */
25425 /* ========================================================  JCDERR  ========================================================= */
25426  #define R_JPEG_JCDERR_ERR_Pos          (0UL)          /*!< ERR (Bit 0)                                           */
25427  #define R_JPEG_JCDERR_ERR_Msk          (0xfUL)        /*!< ERR (Bitfield-Mask: 0x0f)                             */
25428 /* =========================================================  JCRST  ========================================================= */
25429  #define R_JPEG_JCRST_RST_Pos           (0UL)          /*!< RST (Bit 0)                                           */
25430  #define R_JPEG_JCRST_RST_Msk           (0x1UL)        /*!< RST (Bitfield-Mask: 0x01)                             */
25431 /* ========================================================  JIFECNT  ======================================================== */
25432  #define R_JPEG_JIFECNT_JOUTSWAP_Pos    (8UL)          /*!< JOUTSWAP (Bit 8)                                      */
25433  #define R_JPEG_JIFECNT_JOUTSWAP_Msk    (0x700UL)      /*!< JOUTSWAP (Bitfield-Mask: 0x07)                        */
25434  #define R_JPEG_JIFECNT_DINRINI_Pos     (6UL)          /*!< DINRINI (Bit 6)                                       */
25435  #define R_JPEG_JIFECNT_DINRINI_Msk     (0x40UL)       /*!< DINRINI (Bitfield-Mask: 0x01)                         */
25436  #define R_JPEG_JIFECNT_DINRCMD_Pos     (5UL)          /*!< DINRCMD (Bit 5)                                       */
25437  #define R_JPEG_JIFECNT_DINRCMD_Msk     (0x20UL)       /*!< DINRCMD (Bitfield-Mask: 0x01)                         */
25438  #define R_JPEG_JIFECNT_DINLC_Pos       (4UL)          /*!< DINLC (Bit 4)                                         */
25439  #define R_JPEG_JIFECNT_DINLC_Msk       (0x10UL)       /*!< DINLC (Bitfield-Mask: 0x01)                           */
25440  #define R_JPEG_JIFECNT_DINSWAP_Pos     (0UL)          /*!< DINSWAP (Bit 0)                                       */
25441  #define R_JPEG_JIFECNT_DINSWAP_Msk     (0x7UL)        /*!< DINSWAP (Bitfield-Mask: 0x07)                         */
25442 /* ========================================================  JIFESA  ========================================================= */
25443  #define R_JPEG_JIFESA_ESA_Pos          (0UL)          /*!< ESA (Bit 0)                                           */
25444  #define R_JPEG_JIFESA_ESA_Msk          (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff)                       */
25445 /* =======================================================  JIFESOFST  ======================================================= */
25446  #define R_JPEG_JIFESOFST_ESMW_Pos      (0UL)          /*!< ESMW (Bit 0)                                          */
25447  #define R_JPEG_JIFESOFST_ESMW_Msk      (0x7fffUL)     /*!< ESMW (Bitfield-Mask: 0x7fff)                          */
25448 /* ========================================================  JIFEDA  ========================================================= */
25449  #define R_JPEG_JIFEDA_EDA_Pos          (0UL)          /*!< EDA (Bit 0)                                           */
25450  #define R_JPEG_JIFEDA_EDA_Msk          (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff)                       */
25451 /* ========================================================  JIFESLC  ======================================================== */
25452  #define R_JPEG_JIFESLC_LINES_Pos       (0UL)          /*!< LINES (Bit 0)                                         */
25453  #define R_JPEG_JIFESLC_LINES_Msk       (0xffffUL)     /*!< LINES (Bitfield-Mask: 0xffff)                         */
25454 /* ========================================================  JIFDCNT  ======================================================== */
25455  #define R_JPEG_JIFDCNT_VINTER_Pos      (28UL)         /*!< VINTER (Bit 28)                                       */
25456  #define R_JPEG_JIFDCNT_VINTER_Msk      (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03)                          */
25457  #define R_JPEG_JIFDCNT_HINTER_Pos      (26UL)         /*!< HINTER (Bit 26)                                       */
25458  #define R_JPEG_JIFDCNT_HINTER_Msk      (0xc000000UL)  /*!< HINTER (Bitfield-Mask: 0x03)                          */
25459  #define R_JPEG_JIFDCNT_OPF_Pos         (24UL)         /*!< OPF (Bit 24)                                          */
25460  #define R_JPEG_JIFDCNT_OPF_Msk         (0x3000000UL)  /*!< OPF (Bitfield-Mask: 0x03)                             */
25461  #define R_JPEG_JIFDCNT_JINRINI_Pos     (14UL)         /*!< JINRINI (Bit 14)                                      */
25462  #define R_JPEG_JIFDCNT_JINRINI_Msk     (0x4000UL)     /*!< JINRINI (Bitfield-Mask: 0x01)                         */
25463  #define R_JPEG_JIFDCNT_JINRCMD_Pos     (13UL)         /*!< JINRCMD (Bit 13)                                      */
25464  #define R_JPEG_JIFDCNT_JINRCMD_Msk     (0x2000UL)     /*!< JINRCMD (Bitfield-Mask: 0x01)                         */
25465  #define R_JPEG_JIFDCNT_JINC_Pos        (12UL)         /*!< JINC (Bit 12)                                         */
25466  #define R_JPEG_JIFDCNT_JINC_Msk        (0x1000UL)     /*!< JINC (Bitfield-Mask: 0x01)                            */
25467  #define R_JPEG_JIFDCNT_JINSWAP_Pos     (8UL)          /*!< JINSWAP (Bit 8)                                       */
25468  #define R_JPEG_JIFDCNT_JINSWAP_Msk     (0x700UL)      /*!< JINSWAP (Bitfield-Mask: 0x07)                         */
25469  #define R_JPEG_JIFDCNT_DOUTRINI_Pos    (6UL)          /*!< DOUTRINI (Bit 6)                                      */
25470  #define R_JPEG_JIFDCNT_DOUTRINI_Msk    (0x40UL)       /*!< DOUTRINI (Bitfield-Mask: 0x01)                        */
25471  #define R_JPEG_JIFDCNT_DOUTRCMD_Pos    (5UL)          /*!< DOUTRCMD (Bit 5)                                      */
25472  #define R_JPEG_JIFDCNT_DOUTRCMD_Msk    (0x20UL)       /*!< DOUTRCMD (Bitfield-Mask: 0x01)                        */
25473  #define R_JPEG_JIFDCNT_DOUTLC_Pos      (4UL)          /*!< DOUTLC (Bit 4)                                        */
25474  #define R_JPEG_JIFDCNT_DOUTLC_Msk      (0x10UL)       /*!< DOUTLC (Bitfield-Mask: 0x01)                          */
25475  #define R_JPEG_JIFDCNT_DOUTSWAP_Pos    (0UL)          /*!< DOUTSWAP (Bit 0)                                      */
25476  #define R_JPEG_JIFDCNT_DOUTSWAP_Msk    (0x7UL)        /*!< DOUTSWAP (Bitfield-Mask: 0x07)                        */
25477 /* ========================================================  JIFDSA  ========================================================= */
25478  #define R_JPEG_JIFDSA_DSA_Pos          (0UL)          /*!< DSA (Bit 0)                                           */
25479  #define R_JPEG_JIFDSA_DSA_Msk          (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff)                       */
25480 /* =======================================================  JIFDDOFST  ======================================================= */
25481  #define R_JPEG_JIFDDOFST_DDMW_Pos      (0UL)          /*!< DDMW (Bit 0)                                          */
25482  #define R_JPEG_JIFDDOFST_DDMW_Msk      (0x7fffUL)     /*!< DDMW (Bitfield-Mask: 0x7fff)                          */
25483 /* ========================================================  JIFDDA  ========================================================= */
25484  #define R_JPEG_JIFDDA_DDA_Pos          (0UL)          /*!< DDA (Bit 0)                                           */
25485  #define R_JPEG_JIFDDA_DDA_Msk          (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff)                       */
25486 /* ========================================================  JIFDSDC  ======================================================== */
25487  #define R_JPEG_JIFDSDC_JDATAS_Pos      (0UL)          /*!< JDATAS (Bit 0)                                        */
25488  #define R_JPEG_JIFDSDC_JDATAS_Msk      (0xffffUL)     /*!< JDATAS (Bitfield-Mask: 0xffff)                        */
25489 /* ========================================================  JIFDDLC  ======================================================== */
25490  #define R_JPEG_JIFDDLC_LINES_Pos       (0UL)          /*!< LINES (Bit 0)                                         */
25491  #define R_JPEG_JIFDDLC_LINES_Msk       (0xffffUL)     /*!< LINES (Bitfield-Mask: 0xffff)                         */
25492 /* ========================================================  JIFDADT  ======================================================== */
25493  #define R_JPEG_JIFDADT_ALPHA_Pos       (0UL)          /*!< ALPHA (Bit 0)                                         */
25494  #define R_JPEG_JIFDADT_ALPHA_Msk       (0xffUL)       /*!< ALPHA (Bitfield-Mask: 0xff)                           */
25495 /* ========================================================  JINTE1  ========================================================= */
25496  #define R_JPEG_JINTE1_CBTEN_Pos        (6UL)          /*!< CBTEN (Bit 6)                                         */
25497  #define R_JPEG_JINTE1_CBTEN_Msk        (0x40UL)       /*!< CBTEN (Bitfield-Mask: 0x01)                           */
25498  #define R_JPEG_JINTE1_DINLEN_Pos       (5UL)          /*!< DINLEN (Bit 5)                                        */
25499  #define R_JPEG_JINTE1_DINLEN_Msk       (0x20UL)       /*!< DINLEN (Bitfield-Mask: 0x01)                          */
25500  #define R_JPEG_JINTE1_DBTEN_Pos        (2UL)          /*!< DBTEN (Bit 2)                                         */
25501  #define R_JPEG_JINTE1_DBTEN_Msk        (0x4UL)        /*!< DBTEN (Bitfield-Mask: 0x01)                           */
25502  #define R_JPEG_JINTE1_JINEN_Pos        (1UL)          /*!< JINEN (Bit 1)                                         */
25503  #define R_JPEG_JINTE1_JINEN_Msk        (0x2UL)        /*!< JINEN (Bitfield-Mask: 0x01)                           */
25504  #define R_JPEG_JINTE1_DOUTLEN_Pos      (0UL)          /*!< DOUTLEN (Bit 0)                                       */
25505  #define R_JPEG_JINTE1_DOUTLEN_Msk      (0x1UL)        /*!< DOUTLEN (Bitfield-Mask: 0x01)                         */
25506 /* ========================================================  JINTS1  ========================================================= */
25507  #define R_JPEG_JINTS1_CBTF_Pos         (6UL)          /*!< CBTF (Bit 6)                                          */
25508  #define R_JPEG_JINTS1_CBTF_Msk         (0x40UL)       /*!< CBTF (Bitfield-Mask: 0x01)                            */
25509  #define R_JPEG_JINTS1_DINLF_Pos        (5UL)          /*!< DINLF (Bit 5)                                         */
25510  #define R_JPEG_JINTS1_DINLF_Msk        (0x20UL)       /*!< DINLF (Bitfield-Mask: 0x01)                           */
25511  #define R_JPEG_JINTS1_DBTF_Pos         (2UL)          /*!< DBTF (Bit 2)                                          */
25512  #define R_JPEG_JINTS1_DBTF_Msk         (0x4UL)        /*!< DBTF (Bitfield-Mask: 0x01)                            */
25513  #define R_JPEG_JINTS1_JINF_Pos         (1UL)          /*!< JINF (Bit 1)                                          */
25514  #define R_JPEG_JINTS1_JINF_Msk         (0x2UL)        /*!< JINF (Bitfield-Mask: 0x01)                            */
25515  #define R_JPEG_JINTS1_DOUTLF_Pos       (0UL)          /*!< DOUTLF (Bit 0)                                        */
25516  #define R_JPEG_JINTS1_DOUTLF_Msk       (0x1UL)        /*!< DOUTLF (Bitfield-Mask: 0x01)                          */
25517 /* ========================================================  JCQTBL0  ======================================================== */
25518 /* ========================================================  JCQTBL1  ======================================================== */
25519 /* ========================================================  JCQTBL2  ======================================================== */
25520 /* ========================================================  JCQTBL3  ======================================================== */
25521 /* ========================================================  JCHTBD0  ======================================================== */
25522 /* ========================================================  JCHTBD1  ======================================================== */
25523 /* ========================================================  JCHTBA0  ======================================================== */
25524 /* ========================================================  JCHTBA1  ======================================================== */
25525 
25526 /* =========================================================================================================================== */
25527 /* ================                                          R_KINT                                           ================ */
25528 /* =========================================================================================================================== */
25529 
25530 /* =========================================================  KRCTL  ========================================================= */
25531  #define R_KINT_KRCTL_KRMD_Pos    (7UL)    /*!< KRMD (Bit 7)                                          */
25532  #define R_KINT_KRCTL_KRMD_Msk    (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01)                            */
25533  #define R_KINT_KRCTL_KREG_Pos    (0UL)    /*!< KREG (Bit 0)                                          */
25534  #define R_KINT_KRCTL_KREG_Msk    (0x1UL)  /*!< KREG (Bitfield-Mask: 0x01)                            */
25535 /* ==========================================================  KRF  ========================================================== */
25536  #define R_KINT_KRF_KRF7_Pos      (7UL)    /*!< KRF7 (Bit 7)                                          */
25537  #define R_KINT_KRF_KRF7_Msk      (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01)                            */
25538  #define R_KINT_KRF_KRF6_Pos      (6UL)    /*!< KRF6 (Bit 6)                                          */
25539  #define R_KINT_KRF_KRF6_Msk      (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01)                            */
25540  #define R_KINT_KRF_KRF5_Pos      (5UL)    /*!< KRF5 (Bit 5)                                          */
25541  #define R_KINT_KRF_KRF5_Msk      (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01)                            */
25542  #define R_KINT_KRF_KRF4_Pos      (4UL)    /*!< KRF4 (Bit 4)                                          */
25543  #define R_KINT_KRF_KRF4_Msk      (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01)                            */
25544  #define R_KINT_KRF_KRF3_Pos      (3UL)    /*!< KRF3 (Bit 3)                                          */
25545  #define R_KINT_KRF_KRF3_Msk      (0x8UL)  /*!< KRF3 (Bitfield-Mask: 0x01)                            */
25546  #define R_KINT_KRF_KRF2_Pos      (2UL)    /*!< KRF2 (Bit 2)                                          */
25547  #define R_KINT_KRF_KRF2_Msk      (0x4UL)  /*!< KRF2 (Bitfield-Mask: 0x01)                            */
25548  #define R_KINT_KRF_KRF1_Pos      (1UL)    /*!< KRF1 (Bit 1)                                          */
25549  #define R_KINT_KRF_KRF1_Msk      (0x2UL)  /*!< KRF1 (Bitfield-Mask: 0x01)                            */
25550  #define R_KINT_KRF_KRF0_Pos      (0UL)    /*!< KRF0 (Bit 0)                                          */
25551  #define R_KINT_KRF_KRF0_Msk      (0x1UL)  /*!< KRF0 (Bitfield-Mask: 0x01)                            */
25552 /* ==========================================================  KRM  ========================================================== */
25553  #define R_KINT_KRM_KRM7_Pos      (7UL)    /*!< KRM7 (Bit 7)                                          */
25554  #define R_KINT_KRM_KRM7_Msk      (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01)                            */
25555  #define R_KINT_KRM_KRM6_Pos      (6UL)    /*!< KRM6 (Bit 6)                                          */
25556  #define R_KINT_KRM_KRM6_Msk      (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01)                            */
25557  #define R_KINT_KRM_KRM5_Pos      (5UL)    /*!< KRM5 (Bit 5)                                          */
25558  #define R_KINT_KRM_KRM5_Msk      (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01)                            */
25559  #define R_KINT_KRM_KRM4_Pos      (4UL)    /*!< KRM4 (Bit 4)                                          */
25560  #define R_KINT_KRM_KRM4_Msk      (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01)                            */
25561  #define R_KINT_KRM_KRM3_Pos      (3UL)    /*!< KRM3 (Bit 3)                                          */
25562  #define R_KINT_KRM_KRM3_Msk      (0x8UL)  /*!< KRM3 (Bitfield-Mask: 0x01)                            */
25563  #define R_KINT_KRM_KRM2_Pos      (2UL)    /*!< KRM2 (Bit 2)                                          */
25564  #define R_KINT_KRM_KRM2_Msk      (0x4UL)  /*!< KRM2 (Bitfield-Mask: 0x01)                            */
25565  #define R_KINT_KRM_KRM1_Pos      (1UL)    /*!< KRM1 (Bit 1)                                          */
25566  #define R_KINT_KRM_KRM1_Msk      (0x2UL)  /*!< KRM1 (Bitfield-Mask: 0x01)                            */
25567  #define R_KINT_KRM_KRM0_Pos      (0UL)    /*!< KRM0 (Bit 0)                                          */
25568  #define R_KINT_KRM_KRM0_Msk      (0x1UL)  /*!< KRM0 (Bitfield-Mask: 0x01)                            */
25569 
25570 /* =========================================================================================================================== */
25571 /* ================                                           R_MMF                                           ================ */
25572 /* =========================================================================================================================== */
25573 
25574 /* =========================================================  MMSFR  ========================================================= */
25575  #define R_MMF_MMSFR_KEY_Pos           (24UL)         /*!< KEY (Bit 24)                                          */
25576  #define R_MMF_MMSFR_KEY_Msk           (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25577  #define R_MMF_MMSFR_MEMMIRADDR_Pos    (7UL)          /*!< MEMMIRADDR (Bit 7)                                    */
25578  #define R_MMF_MMSFR_MEMMIRADDR_Msk    (0x7fff80UL)   /*!< MEMMIRADDR (Bitfield-Mask: 0xffff)                    */
25579 /* =========================================================  MMEN  ========================================================== */
25580  #define R_MMF_MMEN_KEY_Pos            (24UL)         /*!< KEY (Bit 24)                                          */
25581  #define R_MMF_MMEN_KEY_Msk            (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25582  #define R_MMF_MMEN_EN_Pos             (0UL)          /*!< EN (Bit 0)                                            */
25583  #define R_MMF_MMEN_EN_Msk             (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
25584 
25585 /* =========================================================================================================================== */
25586 /* ================                                        R_MPU_MMPU                                         ================ */
25587 /* =========================================================================================================================== */
25588 
25589 /* =========================================================================================================================== */
25590 /* ================                                        R_MPU_SMPU                                         ================ */
25591 /* =========================================================================================================================== */
25592 
25593 /* ========================================================  SMPUCTL  ======================================================== */
25594  #define R_MPU_SMPU_SMPUCTL_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
25595  #define R_MPU_SMPU_SMPUCTL_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25596  #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos    (1UL)      /*!< PROTECT (Bit 1)                                       */
25597  #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk    (0x2UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
25598  #define R_MPU_SMPU_SMPUCTL_OAD_Pos        (0UL)      /*!< OAD (Bit 0)                                           */
25599  #define R_MPU_SMPU_SMPUCTL_OAD_Msk        (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
25600 
25601 /* =========================================================================================================================== */
25602 /* ================                                        R_MPU_SPMON                                        ================ */
25603 /* =========================================================================================================================== */
25604 
25605 /* =========================================================================================================================== */
25606 /* ================                                          R_MSTP                                           ================ */
25607 /* =========================================================================================================================== */
25608 
25609 /* ========================================================  MSTPCRA  ======================================================== */
25610  #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
25611  #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
25612 /* ========================================================  MSTPCRB  ======================================================== */
25613  #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
25614  #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
25615 /* ========================================================  MSTPCRC  ======================================================== */
25616  #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
25617  #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
25618 /* ========================================================  MSTPCRD  ======================================================== */
25619  #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
25620  #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
25621 /* ========================================================  MSTPCRE  ======================================================== */
25622  #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
25623  #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
25624 /* =======================================================  LSMRWDIS  ======================================================== */
25625  #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
25626  #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
25627  #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
25628  #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
25629  #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
25630  #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
25631  #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
25632  #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
25633  #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
25634  #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
25635 
25636 /* =========================================================================================================================== */
25637 /* ================                                           R_PDC                                           ================ */
25638 /* =========================================================================================================================== */
25639 
25640 /* =========================================================  PCCR0  ========================================================= */
25641  #define R_PDC_PCCR0_EDS_Pos       (14UL)         /*!< EDS (Bit 14)                                          */
25642  #define R_PDC_PCCR0_EDS_Msk       (0x4000UL)     /*!< EDS (Bitfield-Mask: 0x01)                             */
25643  #define R_PDC_PCCR0_PCKDIV_Pos    (11UL)         /*!< PCKDIV (Bit 11)                                       */
25644  #define R_PDC_PCCR0_PCKDIV_Msk    (0x3800UL)     /*!< PCKDIV (Bitfield-Mask: 0x07)                          */
25645  #define R_PDC_PCCR0_PCKOE_Pos     (10UL)         /*!< PCKOE (Bit 10)                                        */
25646  #define R_PDC_PCCR0_PCKOE_Msk     (0x400UL)      /*!< PCKOE (Bitfield-Mask: 0x01)                           */
25647  #define R_PDC_PCCR0_HERIE_Pos     (9UL)          /*!< HERIE (Bit 9)                                         */
25648  #define R_PDC_PCCR0_HERIE_Msk     (0x200UL)      /*!< HERIE (Bitfield-Mask: 0x01)                           */
25649  #define R_PDC_PCCR0_VERIE_Pos     (8UL)          /*!< VERIE (Bit 8)                                         */
25650  #define R_PDC_PCCR0_VERIE_Msk     (0x100UL)      /*!< VERIE (Bitfield-Mask: 0x01)                           */
25651  #define R_PDC_PCCR0_UDRIE_Pos     (7UL)          /*!< UDRIE (Bit 7)                                         */
25652  #define R_PDC_PCCR0_UDRIE_Msk     (0x80UL)       /*!< UDRIE (Bitfield-Mask: 0x01)                           */
25653  #define R_PDC_PCCR0_OVIE_Pos      (6UL)          /*!< OVIE (Bit 6)                                          */
25654  #define R_PDC_PCCR0_OVIE_Msk      (0x40UL)       /*!< OVIE (Bitfield-Mask: 0x01)                            */
25655  #define R_PDC_PCCR0_FEIE_Pos      (5UL)          /*!< FEIE (Bit 5)                                          */
25656  #define R_PDC_PCCR0_FEIE_Msk      (0x20UL)       /*!< FEIE (Bitfield-Mask: 0x01)                            */
25657  #define R_PDC_PCCR0_DFIE_Pos      (4UL)          /*!< DFIE (Bit 4)                                          */
25658  #define R_PDC_PCCR0_DFIE_Msk      (0x10UL)       /*!< DFIE (Bitfield-Mask: 0x01)                            */
25659  #define R_PDC_PCCR0_PRST_Pos      (3UL)          /*!< PRST (Bit 3)                                          */
25660  #define R_PDC_PCCR0_PRST_Msk      (0x8UL)        /*!< PRST (Bitfield-Mask: 0x01)                            */
25661  #define R_PDC_PCCR0_HPS_Pos       (2UL)          /*!< HPS (Bit 2)                                           */
25662  #define R_PDC_PCCR0_HPS_Msk       (0x4UL)        /*!< HPS (Bitfield-Mask: 0x01)                             */
25663  #define R_PDC_PCCR0_VPS_Pos       (1UL)          /*!< VPS (Bit 1)                                           */
25664  #define R_PDC_PCCR0_VPS_Msk       (0x2UL)        /*!< VPS (Bitfield-Mask: 0x01)                             */
25665  #define R_PDC_PCCR0_PCKE_Pos      (0UL)          /*!< PCKE (Bit 0)                                          */
25666  #define R_PDC_PCCR0_PCKE_Msk      (0x1UL)        /*!< PCKE (Bitfield-Mask: 0x01)                            */
25667 /* =========================================================  PCCR1  ========================================================= */
25668  #define R_PDC_PCCR1_PCE_Pos       (0UL)          /*!< PCE (Bit 0)                                           */
25669  #define R_PDC_PCCR1_PCE_Msk       (0x1UL)        /*!< PCE (Bitfield-Mask: 0x01)                             */
25670 /* =========================================================  PCSR  ========================================================== */
25671  #define R_PDC_PCSR_HERF_Pos       (6UL)          /*!< HERF (Bit 6)                                          */
25672  #define R_PDC_PCSR_HERF_Msk       (0x40UL)       /*!< HERF (Bitfield-Mask: 0x01)                            */
25673  #define R_PDC_PCSR_VERF_Pos       (5UL)          /*!< VERF (Bit 5)                                          */
25674  #define R_PDC_PCSR_VERF_Msk       (0x20UL)       /*!< VERF (Bitfield-Mask: 0x01)                            */
25675  #define R_PDC_PCSR_UDRF_Pos       (4UL)          /*!< UDRF (Bit 4)                                          */
25676  #define R_PDC_PCSR_UDRF_Msk       (0x10UL)       /*!< UDRF (Bitfield-Mask: 0x01)                            */
25677  #define R_PDC_PCSR_OVRF_Pos       (3UL)          /*!< OVRF (Bit 3)                                          */
25678  #define R_PDC_PCSR_OVRF_Msk       (0x8UL)        /*!< OVRF (Bitfield-Mask: 0x01)                            */
25679  #define R_PDC_PCSR_FEF_Pos        (2UL)          /*!< FEF (Bit 2)                                           */
25680  #define R_PDC_PCSR_FEF_Msk        (0x4UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
25681  #define R_PDC_PCSR_FEMPF_Pos      (1UL)          /*!< FEMPF (Bit 1)                                         */
25682  #define R_PDC_PCSR_FEMPF_Msk      (0x2UL)        /*!< FEMPF (Bitfield-Mask: 0x01)                           */
25683  #define R_PDC_PCSR_FBSY_Pos       (0UL)          /*!< FBSY (Bit 0)                                          */
25684  #define R_PDC_PCSR_FBSY_Msk       (0x1UL)        /*!< FBSY (Bitfield-Mask: 0x01)                            */
25685 /* ========================================================  PCMONR  ========================================================= */
25686  #define R_PDC_PCMONR_HSYNC_Pos    (1UL)          /*!< HSYNC (Bit 1)                                         */
25687  #define R_PDC_PCMONR_HSYNC_Msk    (0x2UL)        /*!< HSYNC (Bitfield-Mask: 0x01)                           */
25688  #define R_PDC_PCMONR_VSYNC_Pos    (0UL)          /*!< VSYNC (Bit 0)                                         */
25689  #define R_PDC_PCMONR_VSYNC_Msk    (0x1UL)        /*!< VSYNC (Bitfield-Mask: 0x01)                           */
25690 /* =========================================================  PCDR  ========================================================== */
25691  #define R_PDC_PCDR_PCDR_Pos       (0UL)          /*!< PCDR (Bit 0)                                          */
25692  #define R_PDC_PCDR_PCDR_Msk       (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff)                      */
25693 /* ==========================================================  VCR  ========================================================== */
25694  #define R_PDC_VCR_VSZ_Pos         (16UL)         /*!< VSZ (Bit 16)                                          */
25695  #define R_PDC_VCR_VSZ_Msk         (0xfff0000UL)  /*!< VSZ (Bitfield-Mask: 0xfff)                            */
25696  #define R_PDC_VCR_VST_Pos         (0UL)          /*!< VST (Bit 0)                                           */
25697  #define R_PDC_VCR_VST_Msk         (0xfffUL)      /*!< VST (Bitfield-Mask: 0xfff)                            */
25698 /* ==========================================================  HCR  ========================================================== */
25699  #define R_PDC_HCR_HSZ_Pos         (16UL)         /*!< HSZ (Bit 16)                                          */
25700  #define R_PDC_HCR_HSZ_Msk         (0xfff0000UL)  /*!< HSZ (Bitfield-Mask: 0xfff)                            */
25701  #define R_PDC_HCR_HST_Pos         (0UL)          /*!< HST (Bit 0)                                           */
25702  #define R_PDC_HCR_HST_Msk         (0xfffUL)      /*!< HST (Bitfield-Mask: 0xfff)                            */
25703 
25704 /* =========================================================================================================================== */
25705 /* ================                                          R_PORT0                                          ================ */
25706 /* =========================================================================================================================== */
25707 
25708 /* ========================================================  PCNTR1  ========================================================= */
25709  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
25710  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
25711  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
25712  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
25713 /* =========================================================  PODR  ========================================================== */
25714  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
25715  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
25716 /* ==========================================================  PDR  ========================================================== */
25717  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
25718  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
25719 /* ========================================================  PCNTR2  ========================================================= */
25720  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
25721  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
25722  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
25723  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
25724 /* =========================================================  EIDR  ========================================================== */
25725  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
25726  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
25727 /* =========================================================  PIDR  ========================================================== */
25728  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
25729  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
25730 /* ========================================================  PCNTR3  ========================================================= */
25731  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
25732  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
25733  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
25734  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
25735 /* =========================================================  PORR  ========================================================== */
25736  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
25737  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
25738 /* =========================================================  POSR  ========================================================== */
25739  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
25740  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
25741 /* ========================================================  PCNTR4  ========================================================= */
25742  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
25743  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
25744  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
25745  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
25746 /* =========================================================  EORR  ========================================================== */
25747  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
25748  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
25749 /* =========================================================  EOSR  ========================================================== */
25750  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
25751  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
25752 
25753 /* =========================================================================================================================== */
25754 /* ================                                           R_PFS                                           ================ */
25755 /* =========================================================================================================================== */
25756 
25757 /* =========================================================================================================================== */
25758 /* ================                                          R_PMISC                                          ================ */
25759 /* =========================================================================================================================== */
25760 
25761 /* ========================================================  PFENET  ========================================================= */
25762  #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
25763  #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
25764  #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
25765  #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
25766 /* =========================================================  PWPR  ========================================================== */
25767  #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
25768  #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
25769  #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
25770  #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
25771 /* =========================================================  PWPRS  ========================================================= */
25772  #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
25773  #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
25774  #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
25775  #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
25776 /* ========================================================  PRWCNTR  ======================================================== */
25777  #define R_PMISC_PRWCNTR_WAIT_Pos       (0UL)    /*!< WAIT (Bit 0)                                          */
25778  #define R_PMISC_PRWCNTR_WAIT_Msk       (0x3UL)  /*!< WAIT (Bitfield-Mask: 0x03)                            */
25779 
25780 /* =========================================================================================================================== */
25781 /* ================                                          R_QSPI                                           ================ */
25782 /* =========================================================================================================================== */
25783 
25784 /* ========================================================  SFMSMD  ========================================================= */
25785  #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
25786  #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
25787  #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
25788  #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
25789  #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
25790  #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
25791  #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
25792  #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
25793  #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
25794  #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
25795  #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
25796  #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
25797  #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
25798  #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
25799  #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
25800  #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
25801  #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
25802  #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
25803 /* ========================================================  SFMSSC  ========================================================= */
25804  #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
25805  #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
25806  #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
25807  #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
25808  #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
25809  #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
25810 /* ========================================================  SFMSKC  ========================================================= */
25811  #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
25812  #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
25813  #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
25814  #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
25815 /* ========================================================  SFMSST  ========================================================= */
25816  #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
25817  #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
25818  #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
25819  #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
25820  #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
25821  #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
25822 /* ========================================================  SFMCOM  ========================================================= */
25823  #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
25824  #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
25825 /* ========================================================  SFMCMD  ========================================================= */
25826  #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
25827  #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
25828 /* ========================================================  SFMCST  ========================================================= */
25829  #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
25830  #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
25831  #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
25832  #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
25833 /* ========================================================  SFMSIC  ========================================================= */
25834  #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
25835  #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
25836 /* ========================================================  SFMSAC  ========================================================= */
25837  #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
25838  #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
25839  #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
25840  #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
25841 /* ========================================================  SFMSDC  ========================================================= */
25842  #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
25843  #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
25844  #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
25845  #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
25846  #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
25847  #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
25848  #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
25849  #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
25850 /* ========================================================  SFMSPC  ========================================================= */
25851  #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
25852  #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
25853  #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
25854  #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
25855 /* ========================================================  SFMPMD  ========================================================= */
25856  #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
25857  #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
25858 /* ========================================================  SFMCNT1  ======================================================== */
25859  #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
25860  #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */
25861 
25862 /* =========================================================================================================================== */
25863 /* ================                                           R_RTC                                           ================ */
25864 /* =========================================================================================================================== */
25865 
25866 /* ========================================================  R64CNT  ========================================================= */
25867  #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
25868  #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
25869  #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
25870  #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
25871  #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
25872  #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
25873  #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
25874  #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
25875  #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
25876  #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
25877  #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
25878  #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
25879  #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
25880  #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
25881 /* =========================================================  BCNT0  ========================================================= */
25882  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
25883  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
25884 /* ========================================================  RSECCNT  ======================================================== */
25885  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
25886  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
25887  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
25888  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
25889 /* =========================================================  BCNT1  ========================================================= */
25890  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
25891  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
25892 /* ========================================================  RMINCNT  ======================================================== */
25893  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
25894  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
25895  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
25896  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
25897 /* =========================================================  BCNT2  ========================================================= */
25898  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
25899  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
25900 /* ========================================================  RHRCNT  ========================================================= */
25901  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
25902  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
25903  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
25904  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
25905  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
25906  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
25907 /* =========================================================  BCNT3  ========================================================= */
25908  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
25909  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
25910 /* ========================================================  RWKCNT  ========================================================= */
25911  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
25912  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
25913 /* ========================================================  RDAYCNT  ======================================================== */
25914  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
25915  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
25916  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
25917  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
25918 /* ========================================================  RMONCNT  ======================================================== */
25919  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
25920  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
25921  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
25922  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
25923 /* ========================================================  RYRCNT  ========================================================= */
25924  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
25925  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
25926  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
25927  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
25928 /* ========================================================  BCNT0AR  ======================================================== */
25929  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
25930  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
25931 /* ========================================================  RSECAR  ========================================================= */
25932  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25933  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25934  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
25935  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
25936  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
25937  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
25938 /* ========================================================  BCNT1AR  ======================================================== */
25939  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
25940  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
25941 /* ========================================================  RMINAR  ========================================================= */
25942  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25943  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25944  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
25945  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
25946  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
25947  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
25948 /* ========================================================  BCNT2AR  ======================================================== */
25949  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
25950  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
25951 /* =========================================================  RHRAR  ========================================================= */
25952  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
25953  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25954  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
25955  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
25956  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
25957  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
25958  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
25959  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
25960 /* ========================================================  BCNT3AR  ======================================================== */
25961  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
25962  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
25963 /* =========================================================  RWKAR  ========================================================= */
25964  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
25965  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25966  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
25967  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
25968 /* =======================================================  BCNT0AER  ======================================================== */
25969  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25970  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25971 /* ========================================================  RDAYAR  ========================================================= */
25972  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25973  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25974  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
25975  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
25976  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
25977  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
25978 /* =======================================================  BCNT1AER  ======================================================== */
25979  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25980  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25981 /* ========================================================  RMONAR  ========================================================= */
25982  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25983  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25984  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
25985  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
25986  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
25987  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
25988 /* =======================================================  BCNT2AER  ======================================================== */
25989  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25990  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25991 /* =========================================================  RYRAR  ========================================================= */
25992  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
25993  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
25994  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
25995  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
25996 /* =======================================================  BCNT3AER  ======================================================== */
25997  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25998  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25999 /* ========================================================  RYRAREN  ======================================================== */
26000  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
26001  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
26002 /* =========================================================  RCR1  ========================================================== */
26003  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
26004  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
26005  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
26006  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
26007  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
26008  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
26009  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
26010  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
26011  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
26012  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
26013 /* =========================================================  RCR2  ========================================================== */
26014  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
26015  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
26016  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
26017  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
26018  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
26019  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
26020  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
26021  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
26022  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
26023  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
26024  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
26025  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
26026  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
26027  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
26028  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
26029  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
26030 /* =========================================================  RCR4  ========================================================== */
26031  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
26032  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
26033  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
26034  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
26035 /* =========================================================  RFRH  ========================================================== */
26036  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
26037  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
26038 /* =========================================================  RFRL  ========================================================== */
26039  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
26040  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
26041 /* =========================================================  RADJ  ========================================================== */
26042  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
26043  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
26044  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
26045  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
26046 
26047 /* =========================================================================================================================== */
26048 /* ================                                          R_SCI0                                           ================ */
26049 /* =========================================================================================================================== */
26050 
26051 /* ==========================================================  SMR  ========================================================== */
26052  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
26053  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
26054  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
26055  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
26056  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
26057  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
26058  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
26059  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
26060  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
26061  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
26062  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
26063  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
26064  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
26065  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
26066 /* =======================================================  SMR_SMCI  ======================================================== */
26067  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
26068  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
26069  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
26070  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
26071  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
26072  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
26073  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
26074  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
26075  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
26076  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
26077  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
26078  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
26079 /* ==========================================================  BRR  ========================================================== */
26080  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
26081  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
26082 /* ==========================================================  SCR  ========================================================== */
26083  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
26084  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
26085  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
26086  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
26087  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
26088  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
26089  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
26090  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
26091  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
26092  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
26093  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
26094  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
26095  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
26096  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
26097 /* =======================================================  SCR_SMCI  ======================================================== */
26098  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
26099  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
26100  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
26101  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
26102  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
26103  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
26104  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
26105  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
26106  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
26107  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
26108  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
26109  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
26110  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
26111  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
26112 /* ==========================================================  TDR  ========================================================== */
26113  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
26114  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
26115 /* ==========================================================  SSR  ========================================================== */
26116  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
26117  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
26118  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
26119  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
26120  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
26121  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
26122  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
26123  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
26124  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
26125  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
26126  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
26127  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
26128  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
26129  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
26130  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
26131  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
26132 /* =======================================================  SSR_FIFO  ======================================================== */
26133  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
26134  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
26135  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
26136  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
26137  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
26138  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
26139  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
26140  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
26141  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
26142  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
26143  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
26144  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
26145  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
26146  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
26147 /* =======================================================  SSR_SMCI  ======================================================== */
26148  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
26149  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
26150  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
26151  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
26152  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
26153  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
26154  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
26155  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
26156  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
26157  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
26158  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
26159  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
26160  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
26161  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
26162  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
26163  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
26164 /* ==========================================================  RDR  ========================================================== */
26165  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
26166  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
26167 /* =========================================================  SCMR  ========================================================== */
26168  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
26169  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
26170  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
26171  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
26172  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
26173  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
26174  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
26175  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
26176  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
26177  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
26178 /* =========================================================  SEMR  ========================================================== */
26179  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
26180  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
26181  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
26182  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
26183  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
26184  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
26185  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
26186  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
26187  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
26188  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
26189  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
26190  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
26191  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
26192  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
26193  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
26194  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
26195 /* =========================================================  SNFR  ========================================================== */
26196  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
26197  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
26198 /* =========================================================  SIMR1  ========================================================= */
26199  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
26200  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
26201  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
26202  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
26203 /* =========================================================  SIMR2  ========================================================= */
26204  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
26205  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
26206  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
26207  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
26208  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
26209  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
26210 /* =========================================================  SIMR3  ========================================================= */
26211  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
26212  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
26213  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
26214  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
26215  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
26216  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
26217  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
26218  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
26219  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
26220  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
26221  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
26222  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
26223 /* =========================================================  SISR  ========================================================== */
26224  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
26225  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
26226 /* =========================================================  SPMR  ========================================================== */
26227  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
26228  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
26229  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
26230  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
26231  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
26232  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
26233  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
26234  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
26235  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
26236  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
26237  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
26238  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
26239  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
26240  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
26241 /* =========================================================  TDRHL  ========================================================= */
26242  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
26243  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
26244 /* ========================================================  FTDRHL  ========================================================= */
26245  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
26246  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
26247  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
26248  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
26249 /* =========================================================  FTDRH  ========================================================= */
26250  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
26251  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
26252  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
26253  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
26254 /* =========================================================  FTDRL  ========================================================= */
26255  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
26256  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
26257 /* =========================================================  RDRHL  ========================================================= */
26258  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
26259  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
26260 /* ========================================================  FRDRHL  ========================================================= */
26261  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
26262  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
26263  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
26264  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
26265  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
26266  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
26267  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
26268  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
26269  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
26270  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
26271  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
26272  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
26273  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
26274  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
26275 /* =========================================================  FRDRH  ========================================================= */
26276  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
26277  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
26278  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
26279  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
26280  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
26281  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
26282  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
26283  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
26284  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
26285  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
26286  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
26287  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
26288  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
26289  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
26290 /* =========================================================  FRDRL  ========================================================= */
26291  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
26292  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
26293 /* =========================================================  MDDR  ========================================================== */
26294  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
26295  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
26296 /* =========================================================  DCCR  ========================================================== */
26297  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
26298  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
26299  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
26300  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
26301  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
26302  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
26303  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
26304  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
26305  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
26306  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
26307 /* ==========================================================  FCR  ========================================================== */
26308  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
26309  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
26310  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
26311  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
26312  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
26313  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
26314  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
26315  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
26316  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
26317  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
26318  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
26319  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
26320  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
26321  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
26322 /* ==========================================================  FDR  ========================================================== */
26323  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
26324  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
26325  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
26326  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
26327 /* ==========================================================  LSR  ========================================================== */
26328  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
26329  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
26330  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
26331  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
26332  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
26333  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
26334 /* ==========================================================  CDR  ========================================================== */
26335  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
26336  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
26337 /* =========================================================  SPTR  ========================================================== */
26338  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
26339  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
26340  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
26341  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
26342  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
26343  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
26344  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
26345  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
26346  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
26347  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
26348  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
26349  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
26350  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
26351  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
26352 /* =========================================================  ACTR  ========================================================== */
26353  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
26354  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
26355  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
26356  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
26357  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
26358  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
26359  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
26360  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
26361 /* =========================================================  ESMER  ========================================================= */
26362  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
26363  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
26364 /* ==========================================================  CR0  ========================================================== */
26365  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
26366  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
26367  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
26368  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
26369  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
26370  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
26371 /* ==========================================================  CR1  ========================================================== */
26372  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
26373  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
26374  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
26375  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
26376  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
26377  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
26378  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
26379  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
26380  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
26381  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
26382 /* ==========================================================  CR2  ========================================================== */
26383  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
26384  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
26385  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
26386  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
26387  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
26388  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
26389 /* ==========================================================  CR3  ========================================================== */
26390  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
26391  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
26392 /* ==========================================================  PCR  ========================================================== */
26393  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
26394  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
26395  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
26396  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
26397  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
26398  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
26399 /* ==========================================================  ICR  ========================================================== */
26400  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
26401  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
26402  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
26403  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
26404  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
26405  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
26406  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
26407  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
26408  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
26409  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
26410  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
26411  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
26412 /* ==========================================================  STR  ========================================================== */
26413  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
26414  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
26415  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
26416  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
26417  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
26418  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
26419  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
26420  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
26421  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
26422  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
26423  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
26424  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
26425 /* =========================================================  STCR  ========================================================== */
26426  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
26427  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
26428  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
26429  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
26430  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
26431  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
26432  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
26433  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
26434  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
26435  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
26436  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
26437  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
26438 /* =========================================================  CF0DR  ========================================================= */
26439 /* =========================================================  CF0CR  ========================================================= */
26440  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
26441  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
26442  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
26443  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
26444  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
26445  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
26446  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
26447  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
26448  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
26449  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
26450  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
26451  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
26452  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
26453  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
26454  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
26455  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
26456 /* =========================================================  CF0RR  ========================================================= */
26457 /* ========================================================  PCF1DR  ========================================================= */
26458 /* ========================================================  SCF1DR  ========================================================= */
26459 /* =========================================================  CF1CR  ========================================================= */
26460  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
26461  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
26462  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
26463  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
26464  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
26465  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
26466  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
26467  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
26468  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
26469  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
26470  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
26471  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
26472  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
26473  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
26474  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
26475  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
26476 /* =========================================================  CF1RR  ========================================================= */
26477 /* ==========================================================  TCR  ========================================================== */
26478  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
26479  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
26480 /* ==========================================================  TMR  ========================================================== */
26481  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
26482  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
26483  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
26484  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
26485  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
26486  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
26487 /* =========================================================  TPRE  ========================================================== */
26488 /* =========================================================  TCNT  ========================================================== */
26489 
26490 /* =========================================================================================================================== */
26491 /* ================                                          R_SDHI0                                          ================ */
26492 /* =========================================================================================================================== */
26493 
26494 /* ========================================================  SD_CMD  ========================================================= */
26495  #define R_SDHI0_SD_CMD_CMD12AT_Pos              (14UL)         /*!< CMD12AT (Bit 14)                                      */
26496  #define R_SDHI0_SD_CMD_CMD12AT_Msk              (0xc000UL)     /*!< CMD12AT (Bitfield-Mask: 0x03)                         */
26497  #define R_SDHI0_SD_CMD_TRSTP_Pos                (13UL)         /*!< TRSTP (Bit 13)                                        */
26498  #define R_SDHI0_SD_CMD_TRSTP_Msk                (0x2000UL)     /*!< TRSTP (Bitfield-Mask: 0x01)                           */
26499  #define R_SDHI0_SD_CMD_CMDRW_Pos                (12UL)         /*!< CMDRW (Bit 12)                                        */
26500  #define R_SDHI0_SD_CMD_CMDRW_Msk                (0x1000UL)     /*!< CMDRW (Bitfield-Mask: 0x01)                           */
26501  #define R_SDHI0_SD_CMD_CMDTP_Pos                (11UL)         /*!< CMDTP (Bit 11)                                        */
26502  #define R_SDHI0_SD_CMD_CMDTP_Msk                (0x800UL)      /*!< CMDTP (Bitfield-Mask: 0x01)                           */
26503  #define R_SDHI0_SD_CMD_RSPTP_Pos                (8UL)          /*!< RSPTP (Bit 8)                                         */
26504  #define R_SDHI0_SD_CMD_RSPTP_Msk                (0x700UL)      /*!< RSPTP (Bitfield-Mask: 0x07)                           */
26505  #define R_SDHI0_SD_CMD_ACMD_Pos                 (6UL)          /*!< ACMD (Bit 6)                                          */
26506  #define R_SDHI0_SD_CMD_ACMD_Msk                 (0xc0UL)       /*!< ACMD (Bitfield-Mask: 0x03)                            */
26507  #define R_SDHI0_SD_CMD_CMDIDX_Pos               (0UL)          /*!< CMDIDX (Bit 0)                                        */
26508  #define R_SDHI0_SD_CMD_CMDIDX_Msk               (0x3fUL)       /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
26509 /* ========================================================  SD_ARG  ========================================================= */
26510  #define R_SDHI0_SD_ARG_SD_ARG_Pos               (0UL)          /*!< SD_ARG (Bit 0)                                        */
26511  #define R_SDHI0_SD_ARG_SD_ARG_Msk               (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff)                    */
26512 /* ========================================================  SD_ARG1  ======================================================== */
26513  #define R_SDHI0_SD_ARG1_SD_ARG1_Pos             (0UL)          /*!< SD_ARG1 (Bit 0)                                       */
26514  #define R_SDHI0_SD_ARG1_SD_ARG1_Msk             (0xffffUL)     /*!< SD_ARG1 (Bitfield-Mask: 0xffff)                       */
26515 /* ========================================================  SD_STOP  ======================================================== */
26516  #define R_SDHI0_SD_STOP_SEC_Pos                 (8UL)          /*!< SEC (Bit 8)                                           */
26517  #define R_SDHI0_SD_STOP_SEC_Msk                 (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
26518  #define R_SDHI0_SD_STOP_STP_Pos                 (0UL)          /*!< STP (Bit 0)                                           */
26519  #define R_SDHI0_SD_STOP_STP_Msk                 (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
26520 /* =======================================================  SD_SECCNT  ======================================================= */
26521  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos         (0UL)          /*!< SD_SECCNT (Bit 0)                                     */
26522  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk         (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff)                 */
26523 /* =======================================================  SD_RSP10  ======================================================== */
26524  #define R_SDHI0_SD_RSP10_SD_RSP10_Pos           (0UL)          /*!< SD_RSP10 (Bit 0)                                      */
26525  #define R_SDHI0_SD_RSP10_SD_RSP10_Msk           (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff)                  */
26526 /* ========================================================  SD_RSP1  ======================================================== */
26527  #define R_SDHI0_SD_RSP1_SD_RSP1_Pos             (0UL)          /*!< SD_RSP1 (Bit 0)                                       */
26528  #define R_SDHI0_SD_RSP1_SD_RSP1_Msk             (0xffffUL)     /*!< SD_RSP1 (Bitfield-Mask: 0xffff)                       */
26529 /* =======================================================  SD_RSP32  ======================================================== */
26530  #define R_SDHI0_SD_RSP32_SD_RSP32_Pos           (0UL)          /*!< SD_RSP32 (Bit 0)                                      */
26531  #define R_SDHI0_SD_RSP32_SD_RSP32_Msk           (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff)                  */
26532 /* ========================================================  SD_RSP3  ======================================================== */
26533  #define R_SDHI0_SD_RSP3_SD_RSP3_Pos             (0UL)          /*!< SD_RSP3 (Bit 0)                                       */
26534  #define R_SDHI0_SD_RSP3_SD_RSP3_Msk             (0xffffUL)     /*!< SD_RSP3 (Bitfield-Mask: 0xffff)                       */
26535 /* =======================================================  SD_RSP54  ======================================================== */
26536  #define R_SDHI0_SD_RSP54_SD_RSP54_Pos           (0UL)          /*!< SD_RSP54 (Bit 0)                                      */
26537  #define R_SDHI0_SD_RSP54_SD_RSP54_Msk           (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff)                  */
26538 /* ========================================================  SD_RSP5  ======================================================== */
26539  #define R_SDHI0_SD_RSP5_SD_RSP5_Pos             (0UL)          /*!< SD_RSP5 (Bit 0)                                       */
26540  #define R_SDHI0_SD_RSP5_SD_RSP5_Msk             (0xffffUL)     /*!< SD_RSP5 (Bitfield-Mask: 0xffff)                       */
26541 /* =======================================================  SD_RSP76  ======================================================== */
26542  #define R_SDHI0_SD_RSP76_SD_RSP76_Pos           (0UL)          /*!< SD_RSP76 (Bit 0)                                      */
26543  #define R_SDHI0_SD_RSP76_SD_RSP76_Msk           (0xffffffUL)   /*!< SD_RSP76 (Bitfield-Mask: 0xffffff)                    */
26544 /* ========================================================  SD_RSP7  ======================================================== */
26545  #define R_SDHI0_SD_RSP7_SD_RSP7_Pos             (0UL)          /*!< SD_RSP7 (Bit 0)                                       */
26546  #define R_SDHI0_SD_RSP7_SD_RSP7_Msk             (0xffUL)       /*!< SD_RSP7 (Bitfield-Mask: 0xff)                         */
26547 /* =======================================================  SD_INFO1  ======================================================== */
26548  #define R_SDHI0_SD_INFO1_SDD3MON_Pos            (10UL)         /*!< SDD3MON (Bit 10)                                      */
26549  #define R_SDHI0_SD_INFO1_SDD3MON_Msk            (0x400UL)      /*!< SDD3MON (Bitfield-Mask: 0x01)                         */
26550  #define R_SDHI0_SD_INFO1_SDD3IN_Pos             (9UL)          /*!< SDD3IN (Bit 9)                                        */
26551  #define R_SDHI0_SD_INFO1_SDD3IN_Msk             (0x200UL)      /*!< SDD3IN (Bitfield-Mask: 0x01)                          */
26552  #define R_SDHI0_SD_INFO1_SDD3RM_Pos             (8UL)          /*!< SDD3RM (Bit 8)                                        */
26553  #define R_SDHI0_SD_INFO1_SDD3RM_Msk             (0x100UL)      /*!< SDD3RM (Bitfield-Mask: 0x01)                          */
26554  #define R_SDHI0_SD_INFO1_SDWPMON_Pos            (7UL)          /*!< SDWPMON (Bit 7)                                       */
26555  #define R_SDHI0_SD_INFO1_SDWPMON_Msk            (0x80UL)       /*!< SDWPMON (Bitfield-Mask: 0x01)                         */
26556  #define R_SDHI0_SD_INFO1_SDCDMON_Pos            (5UL)          /*!< SDCDMON (Bit 5)                                       */
26557  #define R_SDHI0_SD_INFO1_SDCDMON_Msk            (0x20UL)       /*!< SDCDMON (Bitfield-Mask: 0x01)                         */
26558  #define R_SDHI0_SD_INFO1_SDCDIN_Pos             (4UL)          /*!< SDCDIN (Bit 4)                                        */
26559  #define R_SDHI0_SD_INFO1_SDCDIN_Msk             (0x10UL)       /*!< SDCDIN (Bitfield-Mask: 0x01)                          */
26560  #define R_SDHI0_SD_INFO1_SDCDRM_Pos             (3UL)          /*!< SDCDRM (Bit 3)                                        */
26561  #define R_SDHI0_SD_INFO1_SDCDRM_Msk             (0x8UL)        /*!< SDCDRM (Bitfield-Mask: 0x01)                          */
26562  #define R_SDHI0_SD_INFO1_ACEND_Pos              (2UL)          /*!< ACEND (Bit 2)                                         */
26563  #define R_SDHI0_SD_INFO1_ACEND_Msk              (0x4UL)        /*!< ACEND (Bitfield-Mask: 0x01)                           */
26564  #define R_SDHI0_SD_INFO1_RSPEND_Pos             (0UL)          /*!< RSPEND (Bit 0)                                        */
26565  #define R_SDHI0_SD_INFO1_RSPEND_Msk             (0x1UL)        /*!< RSPEND (Bitfield-Mask: 0x01)                          */
26566 /* =======================================================  SD_INFO2  ======================================================== */
26567  #define R_SDHI0_SD_INFO2_ILA_Pos                (15UL)         /*!< ILA (Bit 15)                                          */
26568  #define R_SDHI0_SD_INFO2_ILA_Msk                (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
26569  #define R_SDHI0_SD_INFO2_CBSY_Pos               (14UL)         /*!< CBSY (Bit 14)                                         */
26570  #define R_SDHI0_SD_INFO2_CBSY_Msk               (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
26571  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos      (13UL)         /*!< SD_CLK_CTRLEN (Bit 13)                                */
26572  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk      (0x2000UL)     /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01)                   */
26573  #define R_SDHI0_SD_INFO2_BWE_Pos                (9UL)          /*!< BWE (Bit 9)                                           */
26574  #define R_SDHI0_SD_INFO2_BWE_Msk                (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
26575  #define R_SDHI0_SD_INFO2_BRE_Pos                (8UL)          /*!< BRE (Bit 8)                                           */
26576  #define R_SDHI0_SD_INFO2_BRE_Msk                (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
26577  #define R_SDHI0_SD_INFO2_SDD0MON_Pos            (7UL)          /*!< SDD0MON (Bit 7)                                       */
26578  #define R_SDHI0_SD_INFO2_SDD0MON_Msk            (0x80UL)       /*!< SDD0MON (Bitfield-Mask: 0x01)                         */
26579  #define R_SDHI0_SD_INFO2_RSPTO_Pos              (6UL)          /*!< RSPTO (Bit 6)                                         */
26580  #define R_SDHI0_SD_INFO2_RSPTO_Msk              (0x40UL)       /*!< RSPTO (Bitfield-Mask: 0x01)                           */
26581  #define R_SDHI0_SD_INFO2_ILR_Pos                (5UL)          /*!< ILR (Bit 5)                                           */
26582  #define R_SDHI0_SD_INFO2_ILR_Msk                (0x20UL)       /*!< ILR (Bitfield-Mask: 0x01)                             */
26583  #define R_SDHI0_SD_INFO2_ILW_Pos                (4UL)          /*!< ILW (Bit 4)                                           */
26584  #define R_SDHI0_SD_INFO2_ILW_Msk                (0x10UL)       /*!< ILW (Bitfield-Mask: 0x01)                             */
26585  #define R_SDHI0_SD_INFO2_DTO_Pos                (3UL)          /*!< DTO (Bit 3)                                           */
26586  #define R_SDHI0_SD_INFO2_DTO_Msk                (0x8UL)        /*!< DTO (Bitfield-Mask: 0x01)                             */
26587  #define R_SDHI0_SD_INFO2_ENDE_Pos               (2UL)          /*!< ENDE (Bit 2)                                          */
26588  #define R_SDHI0_SD_INFO2_ENDE_Msk               (0x4UL)        /*!< ENDE (Bitfield-Mask: 0x01)                            */
26589  #define R_SDHI0_SD_INFO2_CRCE_Pos               (1UL)          /*!< CRCE (Bit 1)                                          */
26590  #define R_SDHI0_SD_INFO2_CRCE_Msk               (0x2UL)        /*!< CRCE (Bitfield-Mask: 0x01)                            */
26591  #define R_SDHI0_SD_INFO2_CMDE_Pos               (0UL)          /*!< CMDE (Bit 0)                                          */
26592  #define R_SDHI0_SD_INFO2_CMDE_Msk               (0x1UL)        /*!< CMDE (Bitfield-Mask: 0x01)                            */
26593 /* =====================================================  SD_INFO1_MASK  ===================================================== */
26594  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos       (9UL)          /*!< SDD3INM (Bit 9)                                       */
26595  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk       (0x200UL)      /*!< SDD3INM (Bitfield-Mask: 0x01)                         */
26596  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos       (8UL)          /*!< SDD3RMM (Bit 8)                                       */
26597  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk       (0x100UL)      /*!< SDD3RMM (Bitfield-Mask: 0x01)                         */
26598  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos       (4UL)          /*!< SDCDINM (Bit 4)                                       */
26599  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk       (0x10UL)       /*!< SDCDINM (Bitfield-Mask: 0x01)                         */
26600  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos       (3UL)          /*!< SDCDRMM (Bit 3)                                       */
26601  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk       (0x8UL)        /*!< SDCDRMM (Bitfield-Mask: 0x01)                         */
26602  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos        (2UL)          /*!< ACENDM (Bit 2)                                        */
26603  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk        (0x4UL)        /*!< ACENDM (Bitfield-Mask: 0x01)                          */
26604  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos       (0UL)          /*!< RSPENDM (Bit 0)                                       */
26605  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk       (0x1UL)        /*!< RSPENDM (Bitfield-Mask: 0x01)                         */
26606 /* =====================================================  SD_INFO2_MASK  ===================================================== */
26607  #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos          (15UL)         /*!< ILAM (Bit 15)                                         */
26608  #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk          (0x8000UL)     /*!< ILAM (Bitfield-Mask: 0x01)                            */
26609  #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos          (9UL)          /*!< BWEM (Bit 9)                                          */
26610  #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk          (0x200UL)      /*!< BWEM (Bitfield-Mask: 0x01)                            */
26611  #define R_SDHI0_SD_INFO2_MASK_BREM_Pos          (8UL)          /*!< BREM (Bit 8)                                          */
26612  #define R_SDHI0_SD_INFO2_MASK_BREM_Msk          (0x100UL)      /*!< BREM (Bitfield-Mask: 0x01)                            */
26613  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos        (6UL)          /*!< RSPTOM (Bit 6)                                        */
26614  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk        (0x40UL)       /*!< RSPTOM (Bitfield-Mask: 0x01)                          */
26615  #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos          (5UL)          /*!< ILRM (Bit 5)                                          */
26616  #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk          (0x20UL)       /*!< ILRM (Bitfield-Mask: 0x01)                            */
26617  #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos          (4UL)          /*!< ILWM (Bit 4)                                          */
26618  #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk          (0x10UL)       /*!< ILWM (Bitfield-Mask: 0x01)                            */
26619  #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos          (3UL)          /*!< DTOM (Bit 3)                                          */
26620  #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk          (0x8UL)        /*!< DTOM (Bitfield-Mask: 0x01)                            */
26621  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos         (2UL)          /*!< ENDEM (Bit 2)                                         */
26622  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk         (0x4UL)        /*!< ENDEM (Bitfield-Mask: 0x01)                           */
26623  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos         (1UL)          /*!< CRCEM (Bit 1)                                         */
26624  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk         (0x2UL)        /*!< CRCEM (Bitfield-Mask: 0x01)                           */
26625  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos         (0UL)          /*!< CMDEM (Bit 0)                                         */
26626  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk         (0x1UL)        /*!< CMDEM (Bitfield-Mask: 0x01)                           */
26627 /* ======================================================  SD_CLK_CTRL  ====================================================== */
26628  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos       (9UL)          /*!< CLKCTRLEN (Bit 9)                                     */
26629  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk       (0x200UL)      /*!< CLKCTRLEN (Bitfield-Mask: 0x01)                       */
26630  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos           (8UL)          /*!< CLKEN (Bit 8)                                         */
26631  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk           (0x100UL)      /*!< CLKEN (Bitfield-Mask: 0x01)                           */
26632  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos          (0UL)          /*!< CLKSEL (Bit 0)                                        */
26633  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk          (0xffUL)       /*!< CLKSEL (Bitfield-Mask: 0xff)                          */
26634 /* ========================================================  SD_SIZE  ======================================================== */
26635  #define R_SDHI0_SD_SIZE_LEN_Pos                 (0UL)          /*!< LEN (Bit 0)                                           */
26636  #define R_SDHI0_SD_SIZE_LEN_Msk                 (0x3ffUL)      /*!< LEN (Bitfield-Mask: 0x3ff)                            */
26637 /* =======================================================  SD_OPTION  ======================================================= */
26638  #define R_SDHI0_SD_OPTION_WIDTH_Pos             (15UL)         /*!< WIDTH (Bit 15)                                        */
26639  #define R_SDHI0_SD_OPTION_WIDTH_Msk             (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
26640  #define R_SDHI0_SD_OPTION_WIDTH8_Pos            (13UL)         /*!< WIDTH8 (Bit 13)                                       */
26641  #define R_SDHI0_SD_OPTION_WIDTH8_Msk            (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
26642  #define R_SDHI0_SD_OPTION_TOUTMASK_Pos          (8UL)          /*!< TOUTMASK (Bit 8)                                      */
26643  #define R_SDHI0_SD_OPTION_TOUTMASK_Msk          (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
26644  #define R_SDHI0_SD_OPTION_TOP_Pos               (4UL)          /*!< TOP (Bit 4)                                           */
26645  #define R_SDHI0_SD_OPTION_TOP_Msk               (0xf0UL)       /*!< TOP (Bitfield-Mask: 0x0f)                             */
26646  #define R_SDHI0_SD_OPTION_CTOP_Pos              (0UL)          /*!< CTOP (Bit 0)                                          */
26647  #define R_SDHI0_SD_OPTION_CTOP_Msk              (0xfUL)        /*!< CTOP (Bitfield-Mask: 0x0f)                            */
26648 /* ======================================================  SD_ERR_STS1  ====================================================== */
26649  #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos           (12UL)         /*!< CRCTK (Bit 12)                                        */
26650  #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk           (0x7000UL)     /*!< CRCTK (Bitfield-Mask: 0x07)                           */
26651  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos          (11UL)         /*!< CRCTKE (Bit 11)                                       */
26652  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk          (0x800UL)      /*!< CRCTKE (Bitfield-Mask: 0x01)                          */
26653  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos          (10UL)         /*!< RDCRCE (Bit 10)                                       */
26654  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk          (0x400UL)      /*!< RDCRCE (Bitfield-Mask: 0x01)                          */
26655  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos        (9UL)          /*!< RSPCRCE1 (Bit 9)                                      */
26656  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk        (0x200UL)      /*!< RSPCRCE1 (Bitfield-Mask: 0x01)                        */
26657  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos        (8UL)          /*!< RSPCRCE0 (Bit 8)                                      */
26658  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk        (0x100UL)      /*!< RSPCRCE0 (Bitfield-Mask: 0x01)                        */
26659  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos         (5UL)          /*!< CRCLENE (Bit 5)                                       */
26660  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk         (0x20UL)       /*!< CRCLENE (Bitfield-Mask: 0x01)                         */
26661  #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos          (4UL)          /*!< RDLENE (Bit 4)                                        */
26662  #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk          (0x10UL)       /*!< RDLENE (Bitfield-Mask: 0x01)                          */
26663  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos        (3UL)          /*!< RSPLENE1 (Bit 3)                                      */
26664  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk        (0x8UL)        /*!< RSPLENE1 (Bitfield-Mask: 0x01)                        */
26665  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos        (2UL)          /*!< RSPLENE0 (Bit 2)                                      */
26666  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk        (0x4UL)        /*!< RSPLENE0 (Bitfield-Mask: 0x01)                        */
26667  #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos           (1UL)          /*!< CMDE1 (Bit 1)                                         */
26668  #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk           (0x2UL)        /*!< CMDE1 (Bitfield-Mask: 0x01)                           */
26669  #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos           (0UL)          /*!< CMDE0 (Bit 0)                                         */
26670  #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk           (0x1UL)        /*!< CMDE0 (Bitfield-Mask: 0x01)                           */
26671 /* ======================================================  SD_ERR_STS2  ====================================================== */
26672  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos        (6UL)          /*!< CRCBSYTO (Bit 6)                                      */
26673  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk        (0x40UL)       /*!< CRCBSYTO (Bitfield-Mask: 0x01)                        */
26674  #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos           (5UL)          /*!< CRCTO (Bit 5)                                         */
26675  #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk           (0x20UL)       /*!< CRCTO (Bitfield-Mask: 0x01)                           */
26676  #define R_SDHI0_SD_ERR_STS2_RDTO_Pos            (4UL)          /*!< RDTO (Bit 4)                                          */
26677  #define R_SDHI0_SD_ERR_STS2_RDTO_Msk            (0x10UL)       /*!< RDTO (Bitfield-Mask: 0x01)                            */
26678  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos          (3UL)          /*!< BSYTO1 (Bit 3)                                        */
26679  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk          (0x8UL)        /*!< BSYTO1 (Bitfield-Mask: 0x01)                          */
26680  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos          (2UL)          /*!< BSYTO0 (Bit 2)                                        */
26681  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk          (0x4UL)        /*!< BSYTO0 (Bitfield-Mask: 0x01)                          */
26682  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos          (1UL)          /*!< RSPTO1 (Bit 1)                                        */
26683  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk          (0x2UL)        /*!< RSPTO1 (Bitfield-Mask: 0x01)                          */
26684  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos          (0UL)          /*!< RSPTO0 (Bit 0)                                        */
26685  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk          (0x1UL)        /*!< RSPTO0 (Bitfield-Mask: 0x01)                          */
26686 /* ========================================================  SD_BUF0  ======================================================== */
26687  #define R_SDHI0_SD_BUF0_SD_BUF_Pos              (0UL)          /*!< SD_BUF (Bit 0)                                        */
26688  #define R_SDHI0_SD_BUF0_SD_BUF_Msk              (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff)                    */
26689 /* =======================================================  SDIO_MODE  ======================================================= */
26690  #define R_SDHI0_SDIO_MODE_C52PUB_Pos            (9UL)          /*!< C52PUB (Bit 9)                                        */
26691  #define R_SDHI0_SDIO_MODE_C52PUB_Msk            (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
26692  #define R_SDHI0_SDIO_MODE_IOABT_Pos             (8UL)          /*!< IOABT (Bit 8)                                         */
26693  #define R_SDHI0_SDIO_MODE_IOABT_Msk             (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
26694  #define R_SDHI0_SDIO_MODE_RWREQ_Pos             (2UL)          /*!< RWREQ (Bit 2)                                         */
26695  #define R_SDHI0_SDIO_MODE_RWREQ_Msk             (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
26696  #define R_SDHI0_SDIO_MODE_INTEN_Pos             (0UL)          /*!< INTEN (Bit 0)                                         */
26697  #define R_SDHI0_SDIO_MODE_INTEN_Msk             (0x1UL)        /*!< INTEN (Bitfield-Mask: 0x01)                           */
26698 /* ======================================================  SDIO_INFO1  ======================================================= */
26699  #define R_SDHI0_SDIO_INFO1_EXWT_Pos             (15UL)         /*!< EXWT (Bit 15)                                         */
26700  #define R_SDHI0_SDIO_INFO1_EXWT_Msk             (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
26701  #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos          (14UL)         /*!< EXPUB52 (Bit 14)                                      */
26702  #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk          (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
26703  #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos            (0UL)          /*!< IOIRQ (Bit 0)                                         */
26704  #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk            (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
26705 /* ====================================================  SDIO_INFO1_MASK  ==================================================== */
26706  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos       (15UL)         /*!< EXWTM (Bit 15)                                        */
26707  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk       (0x8000UL)     /*!< EXWTM (Bitfield-Mask: 0x01)                           */
26708  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos    (14UL)         /*!< EXPUB52M (Bit 14)                                     */
26709  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk    (0x4000UL)     /*!< EXPUB52M (Bitfield-Mask: 0x01)                        */
26710  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos      (0UL)          /*!< IOIRQM (Bit 0)                                        */
26711  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk      (0x1UL)        /*!< IOIRQM (Bitfield-Mask: 0x01)                          */
26712 /* =======================================================  SD_DMAEN  ======================================================== */
26713  #define R_SDHI0_SD_DMAEN_DMAEN_Pos              (1UL)          /*!< DMAEN (Bit 1)                                         */
26714  #define R_SDHI0_SD_DMAEN_DMAEN_Msk              (0x2UL)        /*!< DMAEN (Bitfield-Mask: 0x01)                           */
26715 /* =======================================================  SOFT_RST  ======================================================== */
26716  #define R_SDHI0_SOFT_RST_SDRST_Pos              (0UL)          /*!< SDRST (Bit 0)                                         */
26717  #define R_SDHI0_SOFT_RST_SDRST_Msk              (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
26718 /* =======================================================  SDIF_MODE  ======================================================= */
26719  #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos           (8UL)          /*!< NOCHKCR (Bit 8)                                       */
26720  #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk           (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
26721 /* =======================================================  EXT_SWAP  ======================================================== */
26722  #define R_SDHI0_EXT_SWAP_BRSWP_Pos              (7UL)          /*!< BRSWP (Bit 7)                                         */
26723  #define R_SDHI0_EXT_SWAP_BRSWP_Msk              (0x80UL)       /*!< BRSWP (Bitfield-Mask: 0x01)                           */
26724  #define R_SDHI0_EXT_SWAP_BWSWP_Pos              (6UL)          /*!< BWSWP (Bit 6)                                         */
26725  #define R_SDHI0_EXT_SWAP_BWSWP_Msk              (0x40UL)       /*!< BWSWP (Bitfield-Mask: 0x01)                           */
26726 
26727 /* =========================================================================================================================== */
26728 /* ================                                          R_SPI0                                           ================ */
26729 /* =========================================================================================================================== */
26730 
26731 /* =========================================================  SPCR  ========================================================== */
26732  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
26733  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
26734  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
26735  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
26736  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
26737  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
26738  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
26739  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
26740  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
26741  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
26742  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
26743  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
26744  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
26745  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
26746  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
26747  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
26748 /* =========================================================  SSLP  ========================================================== */
26749  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
26750  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
26751  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
26752  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
26753  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
26754  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
26755  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
26756  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
26757  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
26758  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
26759  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
26760  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
26761  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
26762  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
26763  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
26764  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
26765 /* =========================================================  SPPCR  ========================================================= */
26766  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
26767  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
26768  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
26769  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
26770  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
26771  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
26772  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
26773  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
26774 /* =========================================================  SPSR  ========================================================== */
26775  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
26776  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
26777  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
26778  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
26779  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
26780  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
26781  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
26782  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
26783  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
26784  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
26785  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
26786  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
26787  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
26788  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
26789  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
26790  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
26791 /* =========================================================  SPDR  ========================================================== */
26792 /* ========================================================  SPDR_HA  ======================================================== */
26793 /* ========================================================  SPDR_BY  ======================================================== */
26794 /* =========================================================  SPSCR  ========================================================= */
26795  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
26796  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
26797 /* =========================================================  SPBR  ========================================================== */
26798  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
26799  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
26800 /* =========================================================  SPDCR  ========================================================= */
26801  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
26802  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
26803  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
26804  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
26805  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
26806  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
26807  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
26808  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
26809  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
26810  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
26811 /* =========================================================  SPCKD  ========================================================= */
26812  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
26813  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
26814 /* =========================================================  SSLND  ========================================================= */
26815  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
26816  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
26817 /* =========================================================  SPND  ========================================================== */
26818  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
26819  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
26820 /* =========================================================  SPCR2  ========================================================= */
26821  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
26822  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
26823  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
26824  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
26825  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
26826  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
26827  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
26828  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
26829  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
26830  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
26831  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
26832  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
26833 /* =========================================================  SPCMD  ========================================================= */
26834  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
26835  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
26836  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
26837  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
26838  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
26839  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
26840  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
26841  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
26842  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
26843  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
26844  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
26845  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
26846  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
26847  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
26848  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
26849  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
26850  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
26851  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
26852  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
26853  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
26854 /* ========================================================  SPDCR2  ========================================================= */
26855  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
26856  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
26857  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
26858  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
26859 /* =========================================================  SPSSR  ========================================================= */
26860  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
26861  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
26862  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
26863  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
26864 /* =========================================================  SPCR3  ========================================================= */
26865  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
26866  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
26867  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
26868  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
26869  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
26870  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
26871 /* =========================================================  SPPR  ========================================================== */
26872  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
26873  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
26874  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
26875  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
26876  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
26877  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
26878 
26879 /* =========================================================================================================================== */
26880 /* ================                                          R_SRAM                                           ================ */
26881 /* =========================================================================================================================== */
26882 
26883 /* ========================================================  PARIOAD  ======================================================== */
26884  #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
26885  #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
26886 /* =======================================================  SRAMPRCR  ======================================================== */
26887  #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
26888  #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
26889  #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
26890  #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
26891 /* =======================================================  SRAMWTSC  ======================================================== */
26892 /* ========================================================  ECCMODE  ======================================================== */
26893  #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
26894  #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
26895 /* ========================================================  ECC2STS  ======================================================== */
26896  #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
26897  #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
26898 /* =======================================================  ECC1STSEN  ======================================================= */
26899  #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
26900  #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
26901 /* ========================================================  ECC1STS  ======================================================== */
26902  #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
26903  #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
26904 /* ========================================================  ECCPRCR  ======================================================== */
26905  #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
26906  #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
26907  #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
26908  #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
26909 /* =======================================================  ECCPRCR2  ======================================================== */
26910  #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
26911  #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
26912  #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
26913  #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
26914 /* ========================================================  ECCETST  ======================================================== */
26915  #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
26916  #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
26917 /* ========================================================  ECCOAD  ========================================================= */
26918  #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
26919  #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
26920 /* =======================================================  SRAMPRCR2  ======================================================= */
26921  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
26922  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
26923  #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
26924  #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
26925 
26926 /* =========================================================================================================================== */
26927 /* ================                                           R_SRC                                           ================ */
26928 /* =========================================================================================================================== */
26929 
26930 /* ========================================================  SRCFCTR  ======================================================== */
26931  #define R_SRC_SRCFCTR_SRCFCOE_Pos    (0UL)          /*!< SRCFCOE (Bit 0)                                       */
26932  #define R_SRC_SRCFCTR_SRCFCOE_Msk    (0x3fffffUL)   /*!< SRCFCOE (Bitfield-Mask: 0x3fffff)                     */
26933 /* =========================================================  SRCID  ========================================================= */
26934  #define R_SRC_SRCID_SRCID_Pos        (0UL)          /*!< SRCID (Bit 0)                                         */
26935  #define R_SRC_SRCID_SRCID_Msk        (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff)                     */
26936 /* =========================================================  SRCOD  ========================================================= */
26937  #define R_SRC_SRCOD_SRCOD_Pos        (0UL)          /*!< SRCOD (Bit 0)                                         */
26938  #define R_SRC_SRCOD_SRCOD_Msk        (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff)                     */
26939 /* =======================================================  SRCIDCTRL  ======================================================= */
26940  #define R_SRC_SRCIDCTRL_IED_Pos      (9UL)          /*!< IED (Bit 9)                                           */
26941  #define R_SRC_SRCIDCTRL_IED_Msk      (0x200UL)      /*!< IED (Bitfield-Mask: 0x01)                             */
26942  #define R_SRC_SRCIDCTRL_IEN_Pos      (8UL)          /*!< IEN (Bit 8)                                           */
26943  #define R_SRC_SRCIDCTRL_IEN_Msk      (0x100UL)      /*!< IEN (Bitfield-Mask: 0x01)                             */
26944  #define R_SRC_SRCIDCTRL_IFTRG_Pos    (0UL)          /*!< IFTRG (Bit 0)                                         */
26945  #define R_SRC_SRCIDCTRL_IFTRG_Msk    (0x3UL)        /*!< IFTRG (Bitfield-Mask: 0x03)                           */
26946 /* ========================================================  SRCCTRL  ======================================================== */
26947  #define R_SRC_SRCCTRL_FICRAE_Pos     (15UL)         /*!< FICRAE (Bit 15)                                       */
26948  #define R_SRC_SRCCTRL_FICRAE_Msk     (0x8000UL)     /*!< FICRAE (Bitfield-Mask: 0x01)                          */
26949  #define R_SRC_SRCCTRL_CEEN_Pos       (13UL)         /*!< CEEN (Bit 13)                                         */
26950  #define R_SRC_SRCCTRL_CEEN_Msk       (0x2000UL)     /*!< CEEN (Bitfield-Mask: 0x01)                            */
26951  #define R_SRC_SRCCTRL_SRCEN_Pos      (12UL)         /*!< SRCEN (Bit 12)                                        */
26952  #define R_SRC_SRCCTRL_SRCEN_Msk      (0x1000UL)     /*!< SRCEN (Bitfield-Mask: 0x01)                           */
26953  #define R_SRC_SRCCTRL_UDEN_Pos       (11UL)         /*!< UDEN (Bit 11)                                         */
26954  #define R_SRC_SRCCTRL_UDEN_Msk       (0x800UL)      /*!< UDEN (Bitfield-Mask: 0x01)                            */
26955  #define R_SRC_SRCCTRL_OVEN_Pos       (10UL)         /*!< OVEN (Bit 10)                                         */
26956  #define R_SRC_SRCCTRL_OVEN_Msk       (0x400UL)      /*!< OVEN (Bitfield-Mask: 0x01)                            */
26957  #define R_SRC_SRCCTRL_FL_Pos         (9UL)          /*!< FL (Bit 9)                                            */
26958  #define R_SRC_SRCCTRL_FL_Msk         (0x200UL)      /*!< FL (Bitfield-Mask: 0x01)                              */
26959  #define R_SRC_SRCCTRL_CL_Pos         (8UL)          /*!< CL (Bit 8)                                            */
26960  #define R_SRC_SRCCTRL_CL_Msk         (0x100UL)      /*!< CL (Bitfield-Mask: 0x01)                              */
26961  #define R_SRC_SRCCTRL_IFS_Pos        (4UL)          /*!< IFS (Bit 4)                                           */
26962  #define R_SRC_SRCCTRL_IFS_Msk        (0xf0UL)       /*!< IFS (Bitfield-Mask: 0x0f)                             */
26963  #define R_SRC_SRCCTRL_OFS_Pos        (0UL)          /*!< OFS (Bit 0)                                           */
26964  #define R_SRC_SRCCTRL_OFS_Msk        (0x7UL)        /*!< OFS (Bitfield-Mask: 0x07)                             */
26965 /* =======================================================  SRCODCTRL  ======================================================= */
26966  #define R_SRC_SRCODCTRL_OCH_Pos      (10UL)         /*!< OCH (Bit 10)                                          */
26967  #define R_SRC_SRCODCTRL_OCH_Msk      (0x400UL)      /*!< OCH (Bitfield-Mask: 0x01)                             */
26968  #define R_SRC_SRCODCTRL_OED_Pos      (9UL)          /*!< OED (Bit 9)                                           */
26969  #define R_SRC_SRCODCTRL_OED_Msk      (0x200UL)      /*!< OED (Bitfield-Mask: 0x01)                             */
26970  #define R_SRC_SRCODCTRL_OEN_Pos      (8UL)          /*!< OEN (Bit 8)                                           */
26971  #define R_SRC_SRCODCTRL_OEN_Msk      (0x100UL)      /*!< OEN (Bitfield-Mask: 0x01)                             */
26972  #define R_SRC_SRCODCTRL_OFTRG_Pos    (0UL)          /*!< OFTRG (Bit 0)                                         */
26973  #define R_SRC_SRCODCTRL_OFTRG_Msk    (0x3UL)        /*!< OFTRG (Bitfield-Mask: 0x03)                           */
26974 /* ========================================================  SRCSTAT  ======================================================== */
26975  #define R_SRC_SRCSTAT_OFDN_Pos       (11UL)         /*!< OFDN (Bit 11)                                         */
26976  #define R_SRC_SRCSTAT_OFDN_Msk       (0xf800UL)     /*!< OFDN (Bitfield-Mask: 0x1f)                            */
26977  #define R_SRC_SRCSTAT_IFDN_Pos       (7UL)          /*!< IFDN (Bit 7)                                          */
26978  #define R_SRC_SRCSTAT_IFDN_Msk       (0x780UL)      /*!< IFDN (Bitfield-Mask: 0x0f)                            */
26979  #define R_SRC_SRCSTAT_CEF_Pos        (5UL)          /*!< CEF (Bit 5)                                           */
26980  #define R_SRC_SRCSTAT_CEF_Msk        (0x20UL)       /*!< CEF (Bitfield-Mask: 0x01)                             */
26981  #define R_SRC_SRCSTAT_FLF_Pos        (4UL)          /*!< FLF (Bit 4)                                           */
26982  #define R_SRC_SRCSTAT_FLF_Msk        (0x10UL)       /*!< FLF (Bitfield-Mask: 0x01)                             */
26983  #define R_SRC_SRCSTAT_UDF_Pos        (3UL)          /*!< UDF (Bit 3)                                           */
26984  #define R_SRC_SRCSTAT_UDF_Msk        (0x8UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
26985  #define R_SRC_SRCSTAT_OVF_Pos        (2UL)          /*!< OVF (Bit 2)                                           */
26986  #define R_SRC_SRCSTAT_OVF_Msk        (0x4UL)        /*!< OVF (Bitfield-Mask: 0x01)                             */
26987  #define R_SRC_SRCSTAT_IINT_Pos       (1UL)          /*!< IINT (Bit 1)                                          */
26988  #define R_SRC_SRCSTAT_IINT_Msk       (0x2UL)        /*!< IINT (Bitfield-Mask: 0x01)                            */
26989  #define R_SRC_SRCSTAT_OINT_Pos       (0UL)          /*!< OINT (Bit 0)                                          */
26990  #define R_SRC_SRCSTAT_OINT_Msk       (0x1UL)        /*!< OINT (Bitfield-Mask: 0x01)                            */
26991 
26992 /* =========================================================================================================================== */
26993 /* ================                                          R_SSI0                                           ================ */
26994 /* =========================================================================================================================== */
26995 
26996 /* =========================================================  SSICR  ========================================================= */
26997  #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
26998  #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
26999  #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
27000  #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
27001  #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
27002  #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
27003  #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
27004  #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
27005  #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
27006  #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
27007  #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
27008  #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
27009  #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
27010  #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
27011  #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
27012  #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
27013  #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
27014  #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
27015  #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
27016  #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
27017  #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
27018  #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
27019  #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
27020  #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
27021  #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
27022  #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
27023  #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
27024  #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
27025  #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
27026  #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
27027  #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
27028  #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
27029  #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
27030  #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
27031  #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
27032  #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
27033  #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
27034  #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
27035  #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
27036  #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
27037 /* =========================================================  SSISR  ========================================================= */
27038  #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
27039  #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
27040  #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
27041  #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
27042  #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
27043  #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
27044  #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
27045  #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
27046  #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
27047  #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
27048  #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
27049  #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
27050  #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
27051  #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
27052  #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
27053  #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
27054  #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
27055  #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
27056  #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
27057  #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
27058 /* ========================================================  SSIFCR  ========================================================= */
27059  #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
27060  #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
27061  #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
27062  #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
27063  #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
27064  #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
27065  #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
27066  #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
27067  #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
27068  #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
27069  #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
27070  #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
27071  #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
27072  #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
27073  #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
27074  #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
27075  #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
27076  #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
27077 /* ========================================================  SSIFSR  ========================================================= */
27078  #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
27079  #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
27080  #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
27081  #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
27082  #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
27083  #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
27084  #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
27085  #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
27086 /* ========================================================  SSIFTDR  ======================================================== */
27087  #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
27088  #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
27089 /* =======================================================  SSIFTDR16  ======================================================= */
27090 /* =======================================================  SSIFTDR8  ======================================================== */
27091 /* ========================================================  SSIFRDR  ======================================================== */
27092  #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
27093  #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
27094 /* =======================================================  SSIFRDR16  ======================================================= */
27095 /* =======================================================  SSIFRDR8  ======================================================== */
27096 /* ========================================================  SSIOFR  ========================================================= */
27097  #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
27098  #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
27099  #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
27100  #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
27101  #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
27102  #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
27103 /* ========================================================  SSISCR  ========================================================= */
27104  #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
27105  #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
27106  #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
27107  #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
27108 
27109 /* =========================================================================================================================== */
27110 /* ================                                         R_SYSTEM                                          ================ */
27111 /* =========================================================================================================================== */
27112 
27113 /* =========================================================  SBYCR  ========================================================= */
27114  #define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
27115  #define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
27116  #define R_SYSTEM_SBYCR_OPE_Pos                    (14UL)         /*!< OPE (Bit 14)                                          */
27117  #define R_SYSTEM_SBYCR_OPE_Msk                    (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
27118 /* ========================================================  MSTPCRA  ======================================================== */
27119  #define R_SYSTEM_MSTPCRA_MSTPA_Pos                (0UL)          /*!< MSTPA (Bit 0)                                         */
27120  #define R_SYSTEM_MSTPCRA_MSTPA_Msk                (0x1UL)        /*!< MSTPA (Bitfield-Mask: 0x01)                           */
27121 /* =======================================================  SCKDIVCR  ======================================================== */
27122  #define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
27123  #define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
27124  #define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
27125  #define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
27126  #define R_SYSTEM_SCKDIVCR_BCK_Pos                 (16UL)         /*!< BCK (Bit 16)                                          */
27127  #define R_SYSTEM_SCKDIVCR_BCK_Msk                 (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
27128  #define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
27129  #define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
27130  #define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
27131  #define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
27132  #define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
27133  #define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
27134  #define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
27135  #define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
27136 /* =======================================================  SCKDIVCR2  ======================================================= */
27137  #define R_SYSTEM_SCKDIVCR2_UCK_Pos                (4UL)          /*!< UCK (Bit 4)                                           */
27138  #define R_SYSTEM_SCKDIVCR2_UCK_Msk                (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
27139 /* ========================================================  SCKSCR  ========================================================= */
27140  #define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
27141  #define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
27142 /* ========================================================  PLLCCR  ========================================================= */
27143  #define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
27144  #define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
27145  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
27146  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
27147  #define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
27148  #define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
27149 /* =========================================================  PLLCR  ========================================================= */
27150  #define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
27151  #define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
27152 /* ========================================================  PLLCCR2  ======================================================== */
27153  #define R_SYSTEM_PLLCCR2_PLODIV_Pos               (6UL)          /*!< PLODIV (Bit 6)                                        */
27154  #define R_SYSTEM_PLLCCR2_PLODIV_Msk               (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
27155  #define R_SYSTEM_PLLCCR2_PLLMUL_Pos               (0UL)          /*!< PLLMUL (Bit 0)                                        */
27156  #define R_SYSTEM_PLLCCR2_PLLMUL_Msk               (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
27157 /* =========================================================  BCKCR  ========================================================= */
27158  #define R_SYSTEM_BCKCR_BCLKDIV_Pos                (0UL)          /*!< BCLKDIV (Bit 0)                                       */
27159  #define R_SYSTEM_BCKCR_BCLKDIV_Msk                (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
27160 /* ========================================================  MEMWAIT  ======================================================== */
27161  #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos              (0UL)          /*!< MEMWAIT (Bit 0)                                       */
27162  #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk              (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
27163 /* ========================================================  MOSCCR  ========================================================= */
27164  #define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
27165  #define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
27166 /* ========================================================  HOCOCR  ========================================================= */
27167  #define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
27168  #define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
27169 /* ========================================================  HOCOCR2  ======================================================== */
27170  #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos               (0UL)          /*!< HCFRQ0 (Bit 0)                                        */
27171  #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk               (0x3UL)        /*!< HCFRQ0 (Bitfield-Mask: 0x03)                          */
27172  #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos               (3UL)          /*!< HCFRQ1 (Bit 3)                                        */
27173  #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk               (0x38UL)       /*!< HCFRQ1 (Bitfield-Mask: 0x07)                          */
27174 /* ========================================================  MOCOCR  ========================================================= */
27175  #define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
27176  #define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
27177 /* ========================================================  FLLCR1  ========================================================= */
27178  #define R_SYSTEM_FLLCR1_FLLEN_Pos                 (0UL)          /*!< FLLEN (Bit 0)                                         */
27179  #define R_SYSTEM_FLLCR1_FLLEN_Msk                 (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
27180 /* ========================================================  FLLCR2  ========================================================= */
27181  #define R_SYSTEM_FLLCR2_FLLCNTL_Pos               (0UL)          /*!< FLLCNTL (Bit 0)                                       */
27182  #define R_SYSTEM_FLLCR2_FLLCNTL_Msk               (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
27183 /* =========================================================  OSCSF  ========================================================= */
27184  #define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
27185  #define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
27186  #define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
27187  #define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
27188  #define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
27189  #define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
27190  #define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
27191  #define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
27192 /* =========================================================  CKOCR  ========================================================= */
27193  #define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
27194  #define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
27195  #define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
27196  #define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
27197  #define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
27198  #define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
27199 /* ========================================================  TRCKCR  ========================================================= */
27200  #define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
27201  #define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
27202  #define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
27203  #define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
27204 /* ========================================================  OSTDCR  ========================================================= */
27205  #define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
27206  #define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
27207  #define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
27208  #define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
27209 /* ========================================================  OSTDSR  ========================================================= */
27210  #define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
27211  #define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
27212 /* =========================================================  LPOPT  ========================================================= */
27213  #define R_SYSTEM_LPOPT_LPOPTEN_Pos                (7UL)          /*!< LPOPTEN (Bit 7)                                       */
27214  #define R_SYSTEM_LPOPT_LPOPTEN_Msk                (0x80UL)       /*!< LPOPTEN (Bitfield-Mask: 0x01)                         */
27215  #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos              (3UL)          /*!< BPFCLKDIS (Bit 3)                                     */
27216  #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk              (0x8UL)        /*!< BPFCLKDIS (Bitfield-Mask: 0x01)                       */
27217  #define R_SYSTEM_LPOPT_DCLKDIS_Pos                (1UL)          /*!< DCLKDIS (Bit 1)                                       */
27218  #define R_SYSTEM_LPOPT_DCLKDIS_Msk                (0x6UL)        /*!< DCLKDIS (Bitfield-Mask: 0x03)                         */
27219  #define R_SYSTEM_LPOPT_MPUDIS_Pos                 (0UL)          /*!< MPUDIS (Bit 0)                                        */
27220  #define R_SYSTEM_LPOPT_MPUDIS_Msk                 (0x1UL)        /*!< MPUDIS (Bitfield-Mask: 0x01)                          */
27221 /* =======================================================  SLCDSCKCR  ======================================================= */
27222  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos           (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
27223  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk           (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
27224  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos          (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
27225  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk          (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
27226 /* ========================================================  EBCKOCR  ======================================================== */
27227  #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos              (0UL)          /*!< EBCKOEN (Bit 0)                                       */
27228  #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk              (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
27229 /* ========================================================  SDCKOCR  ======================================================== */
27230  #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos              (0UL)          /*!< SDCKOEN (Bit 0)                                       */
27231  #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk              (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
27232 /* =======================================================  MOCOUTCR  ======================================================== */
27233  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
27234  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
27235 /* =======================================================  HOCOUTCR  ======================================================== */
27236  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
27237  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
27238 /* =========================================================  SNZCR  ========================================================= */
27239  #define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
27240  #define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
27241  #define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
27242  #define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
27243  #define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
27244  #define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
27245 /* ========================================================  SNZEDCR  ======================================================== */
27246  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos            (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
27247  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk            (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
27248  #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos             (6UL)          /*!< AD1UMTED (Bit 6)                                      */
27249  #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk             (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
27250  #define R_SYSTEM_SNZEDCR_AD1MATED_Pos             (5UL)          /*!< AD1MATED (Bit 5)                                      */
27251  #define R_SYSTEM_SNZEDCR_AD1MATED_Msk             (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
27252  #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos             (4UL)          /*!< AD0UMTED (Bit 4)                                      */
27253  #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk             (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
27254  #define R_SYSTEM_SNZEDCR_AD0MATED_Pos             (3UL)          /*!< AD0MATED (Bit 3)                                      */
27255  #define R_SYSTEM_SNZEDCR_AD0MATED_Msk             (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
27256  #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos             (2UL)          /*!< DTCNZRED (Bit 2)                                      */
27257  #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk             (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
27258  #define R_SYSTEM_SNZEDCR_DTCZRED_Pos              (1UL)          /*!< DTCZRED (Bit 1)                                       */
27259  #define R_SYSTEM_SNZEDCR_DTCZRED_Msk              (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
27260  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos            (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
27261  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk            (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
27262 /* =======================================================  SNZREQCR  ======================================================== */
27263  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos          (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
27264  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk          (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
27265  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos          (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
27266  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk          (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
27267  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos          (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
27268  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk          (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
27269  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos          (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
27270  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk          (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
27271  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos          (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
27272  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk          (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
27273  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos          (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
27274  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk          (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
27275  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos          (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
27276  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk          (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
27277  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos          (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
27278  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk          (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
27279  #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos            (0UL)          /*!< SNZREQEN (Bit 0)                                      */
27280  #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk            (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
27281 /* ========================================================  FLSTOP  ========================================================= */
27282  #define R_SYSTEM_FLSTOP_FLSTPF_Pos                (4UL)          /*!< FLSTPF (Bit 4)                                        */
27283  #define R_SYSTEM_FLSTOP_FLSTPF_Msk                (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
27284  #define R_SYSTEM_FLSTOP_FLSTOP_Pos                (0UL)          /*!< FLSTOP (Bit 0)                                        */
27285  #define R_SYSTEM_FLSTOP_FLSTOP_Msk                (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
27286 /* =========================================================  PSMCR  ========================================================= */
27287  #define R_SYSTEM_PSMCR_PSMC_Pos                   (0UL)          /*!< PSMC (Bit 0)                                          */
27288  #define R_SYSTEM_PSMCR_PSMC_Msk                   (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
27289 /* =========================================================  OPCCR  ========================================================= */
27290  #define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
27291  #define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
27292  #define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
27293  #define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
27294 /* ========================================================  SOPCCR  ========================================================= */
27295  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos              (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
27296  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk              (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
27297  #define R_SYSTEM_SOPCCR_SOPCM_Pos                 (0UL)          /*!< SOPCM (Bit 0)                                         */
27298  #define R_SYSTEM_SOPCCR_SOPCM_Msk                 (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
27299 /* =======================================================  MOSCWTCR  ======================================================== */
27300  #define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
27301  #define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
27302 /* =======================================================  HOCOWTCR  ======================================================== */
27303  #define R_SYSTEM_HOCOWTCR_HSTS_Pos                (0UL)          /*!< HSTS (Bit 0)                                          */
27304  #define R_SYSTEM_HOCOWTCR_HSTS_Msk                (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
27305 /* ========================================================  RSTSR1  ========================================================= */
27306  #define R_SYSTEM_RSTSR1_SPERF_Pos                 (12UL)         /*!< SPERF (Bit 12)                                        */
27307  #define R_SYSTEM_RSTSR1_SPERF_Msk                 (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
27308  #define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
27309  #define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
27310  #define R_SYSTEM_RSTSR1_BUSSRF_Pos                (10UL)         /*!< BUSSRF (Bit 10)                                       */
27311  #define R_SYSTEM_RSTSR1_BUSSRF_Msk                (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
27312  #define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
27313  #define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
27314  #define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
27315  #define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
27316  #define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
27317  #define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
27318  #define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
27319  #define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
27320  #define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
27321  #define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
27322  #define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
27323  #define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
27324  #define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
27325  #define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
27326 /* ========================================================  STCONR  ========================================================= */
27327  #define R_SYSTEM_STCONR_STCON_Pos                 (0UL)          /*!< STCON (Bit 0)                                         */
27328  #define R_SYSTEM_STCONR_STCON_Msk                 (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
27329 /* ========================================================  LVD1CR1  ======================================================== */
27330  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
27331  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
27332  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
27333  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
27334 /* ========================================================  LVD2CR1  ======================================================== */
27335  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
27336  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
27337  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
27338  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
27339 /* ======================================================  USBCKCR_ALT  ====================================================== */
27340  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos        (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
27341  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk        (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
27342 /* =======================================================  SDADCCKCR  ======================================================= */
27343  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos         (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
27344  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk         (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
27345  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos          (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
27346  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk          (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
27347 /* ========================================================  LVD1SR  ========================================================= */
27348  #define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
27349  #define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
27350  #define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
27351  #define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
27352 /* ========================================================  LVD2SR  ========================================================= */
27353  #define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
27354  #define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
27355  #define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
27356  #define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
27357 /* =========================================================  PRCR  ========================================================== */
27358  #define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
27359  #define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
27360  #define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
27361  #define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
27362  #define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
27363  #define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
27364  #define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
27365  #define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
27366  #define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
27367  #define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
27368 /* ========================================================  DPSIER0  ======================================================== */
27369  #define R_SYSTEM_DPSIER0_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
27370  #define R_SYSTEM_DPSIER0_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
27371 /* ========================================================  DPSIER1  ======================================================== */
27372  #define R_SYSTEM_DPSIER1_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
27373  #define R_SYSTEM_DPSIER1_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
27374 /* ========================================================  DPSIER2  ======================================================== */
27375  #define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
27376  #define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
27377  #define R_SYSTEM_DPSIER2_DRTCAIE_Pos              (3UL)          /*!< DRTCAIE (Bit 3)                                       */
27378  #define R_SYSTEM_DPSIER2_DRTCAIE_Msk              (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
27379  #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos             (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
27380  #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk             (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
27381  #define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
27382  #define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
27383  #define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
27384  #define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
27385 /* ========================================================  DPSIER3  ======================================================== */
27386  #define R_SYSTEM_DPSIER3_DAGT1IE_Pos              (2UL)          /*!< DAGT1IE (Bit 2)                                       */
27387  #define R_SYSTEM_DPSIER3_DAGT1IE_Msk              (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
27388  #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos             (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
27389  #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk             (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
27390  #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos             (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
27391  #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk             (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
27392  #define R_SYSTEM_DPSIER3_DAGT3IE_Pos              (3UL)          /*!< DAGT3IE (Bit 3)                                       */
27393  #define R_SYSTEM_DPSIER3_DAGT3IE_Msk              (0x8UL)        /*!< DAGT3IE (Bitfield-Mask: 0x01)                         */
27394 /* ========================================================  DPSIFR0  ======================================================== */
27395  #define R_SYSTEM_DPSIFR0_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
27396  #define R_SYSTEM_DPSIFR0_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
27397 /* ========================================================  DPSIFR1  ======================================================== */
27398  #define R_SYSTEM_DPSIFR1_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
27399  #define R_SYSTEM_DPSIFR1_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
27400 /* ========================================================  DPSIFR2  ======================================================== */
27401  #define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
27402  #define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
27403  #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos              (3UL)          /*!< DRTCAIF (Bit 3)                                       */
27404  #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk              (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
27405  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos             (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
27406  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk             (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
27407  #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
27408  #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
27409  #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
27410  #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
27411 /* ========================================================  DPSIFR3  ======================================================== */
27412  #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos              (2UL)          /*!< DAGT1IF (Bit 2)                                       */
27413  #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk              (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
27414  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos             (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
27415  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk             (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
27416  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos             (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
27417  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk             (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
27418  #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos              (3UL)          /*!< DAGT3IF (Bit 3)                                       */
27419  #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk              (0x8UL)        /*!< DAGT3IF (Bitfield-Mask: 0x01)                         */
27420 /* =======================================================  DPSIEGR0  ======================================================== */
27421  #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
27422  #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
27423 /* =======================================================  DPSIEGR1  ======================================================== */
27424  #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
27425  #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
27426 /* =======================================================  DPSIEGR2  ======================================================== */
27427  #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
27428  #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
27429  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos            (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
27430  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk            (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
27431  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos            (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
27432  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk            (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
27433 /* ========================================================  DPSBYCR  ======================================================== */
27434  #define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
27435  #define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
27436  #define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
27437  #define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
27438  #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
27439  #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
27440 /* ========================================================  SYOCDCR  ======================================================== */
27441  #define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
27442  #define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
27443  #define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
27444  #define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
27445 /* =========================================================  MOMCR  ========================================================= */
27446  #define R_SYSTEM_MOMCR_AUTODRVEN_Pos              (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
27447  #define R_SYSTEM_MOMCR_AUTODRVEN_Msk              (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
27448  #define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
27449  #define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
27450  #define R_SYSTEM_MOMCR_MODRV0_Pos                 (4UL)          /*!< MODRV0 (Bit 4)                                        */
27451  #define R_SYSTEM_MOMCR_MODRV0_Msk                 (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
27452  #define R_SYSTEM_MOMCR_MODRV1_Pos                 (3UL)          /*!< MODRV1 (Bit 3)                                        */
27453  #define R_SYSTEM_MOMCR_MODRV1_Msk                 (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
27454 /* ========================================================  RSTSR0  ========================================================= */
27455  #define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
27456  #define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
27457  #define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
27458  #define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
27459  #define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
27460  #define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
27461  #define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
27462  #define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
27463  #define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
27464  #define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
27465 /* ========================================================  RSTSR2  ========================================================= */
27466  #define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
27467  #define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
27468 /* ========================================================  LVCMPCR  ======================================================== */
27469  #define R_SYSTEM_LVCMPCR_LVD2E_Pos                (6UL)          /*!< LVD2E (Bit 6)                                         */
27470  #define R_SYSTEM_LVCMPCR_LVD2E_Msk                (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
27471  #define R_SYSTEM_LVCMPCR_LVD1E_Pos                (5UL)          /*!< LVD1E (Bit 5)                                         */
27472  #define R_SYSTEM_LVCMPCR_LVD1E_Msk                (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
27473 /* =======================================================  LVD1CMPCR  ======================================================= */
27474  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
27475  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
27476  #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
27477  #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
27478 /* ========================================================  LVDLVLR  ======================================================== */
27479  #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos              (5UL)          /*!< LVD2LVL (Bit 5)                                       */
27480  #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk              (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
27481  #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos              (0UL)          /*!< LVD1LVL (Bit 0)                                       */
27482  #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk              (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
27483 /* =======================================================  LVD2CMPCR  ======================================================= */
27484  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
27485  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
27486  #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
27487  #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
27488 /* ========================================================  LVD1CR0  ======================================================== */
27489  #define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
27490  #define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
27491  #define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
27492  #define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
27493  #define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
27494  #define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
27495  #define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
27496  #define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
27497  #define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
27498  #define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
27499  #define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
27500  #define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
27501 /* ========================================================  LVD2CR0  ======================================================== */
27502  #define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
27503  #define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
27504  #define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
27505  #define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
27506  #define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
27507  #define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
27508  #define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
27509  #define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
27510  #define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
27511  #define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
27512  #define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
27513  #define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
27514 /* ========================================================  VBTCR1  ========================================================= */
27515  #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos              (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
27516  #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk              (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
27517 /* ========================================================  DCDCCTL  ======================================================== */
27518  #define R_SYSTEM_DCDCCTL_PD_Pos                   (7UL)          /*!< PD (Bit 7)                                            */
27519  #define R_SYSTEM_DCDCCTL_PD_Msk                   (0x80UL)       /*!< PD (Bitfield-Mask: 0x01)                              */
27520  #define R_SYSTEM_DCDCCTL_FST_Pos                  (6UL)          /*!< FST (Bit 6)                                           */
27521  #define R_SYSTEM_DCDCCTL_FST_Msk                  (0x40UL)       /*!< FST (Bitfield-Mask: 0x01)                             */
27522  #define R_SYSTEM_DCDCCTL_LCBOOST_Pos              (5UL)          /*!< LCBOOST (Bit 5)                                       */
27523  #define R_SYSTEM_DCDCCTL_LCBOOST_Msk              (0x20UL)       /*!< LCBOOST (Bitfield-Mask: 0x01)                         */
27524  #define R_SYSTEM_DCDCCTL_STOPZA_Pos               (4UL)          /*!< STOPZA (Bit 4)                                        */
27525  #define R_SYSTEM_DCDCCTL_STOPZA_Msk               (0x10UL)       /*!< STOPZA (Bitfield-Mask: 0x01)                          */
27526  #define R_SYSTEM_DCDCCTL_OCPEN_Pos                (1UL)          /*!< OCPEN (Bit 1)                                         */
27527  #define R_SYSTEM_DCDCCTL_OCPEN_Msk                (0x2UL)        /*!< OCPEN (Bitfield-Mask: 0x01)                           */
27528  #define R_SYSTEM_DCDCCTL_DCDCON_Pos               (0UL)          /*!< DCDCON (Bit 0)                                        */
27529  #define R_SYSTEM_DCDCCTL_DCDCON_Msk               (0x1UL)        /*!< DCDCON (Bitfield-Mask: 0x01)                          */
27530 /* ========================================================  VCCSEL  ========================================================= */
27531  #define R_SYSTEM_VCCSEL_VCCSEL_Pos                (0UL)          /*!< VCCSEL (Bit 0)                                        */
27532  #define R_SYSTEM_VCCSEL_VCCSEL_Msk                (0x3UL)        /*!< VCCSEL (Bitfield-Mask: 0x03)                          */
27533 /* ========================================================  LDOSCR  ========================================================= */
27534  #define R_SYSTEM_LDOSCR_LDOSTP0_Pos               (0UL)          /*!< LDOSTP0 (Bit 0)                                       */
27535  #define R_SYSTEM_LDOSCR_LDOSTP0_Msk               (0x1UL)        /*!< LDOSTP0 (Bitfield-Mask: 0x01)                         */
27536  #define R_SYSTEM_LDOSCR_LDOSTP1_Pos               (1UL)          /*!< LDOSTP1 (Bit 1)                                       */
27537  #define R_SYSTEM_LDOSCR_LDOSTP1_Msk               (0x2UL)        /*!< LDOSTP1 (Bitfield-Mask: 0x01)                         */
27538 /* =======================================================  PL2LDOSCR  ======================================================= */
27539  #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos          (0UL)          /*!< PL2LDOSTP (Bit 0)                                     */
27540  #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk          (0x1UL)        /*!< PL2LDOSTP (Bitfield-Mask: 0x01)                       */
27541 /* ========================================================  SOSCCR  ========================================================= */
27542  #define R_SYSTEM_SOSCCR_SOSTP_Pos                 (0UL)          /*!< SOSTP (Bit 0)                                         */
27543  #define R_SYSTEM_SOSCCR_SOSTP_Msk                 (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
27544 /* =========================================================  SOMCR  ========================================================= */
27545  #define R_SYSTEM_SOMCR_SODRV_Pos                  (0UL)          /*!< SODRV (Bit 0)                                         */
27546  #define R_SYSTEM_SOMCR_SODRV_Msk                  (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
27547 /* =========================================================  SOMRG  ========================================================= */
27548  #define R_SYSTEM_SOMRG_SOSCMRG_Pos                (0UL)          /*!< SOSCMRG (Bit 0)                                       */
27549  #define R_SYSTEM_SOMRG_SOSCMRG_Msk                (0x3UL)        /*!< SOSCMRG (Bitfield-Mask: 0x03)                         */
27550 /* ========================================================  LOCOCR  ========================================================= */
27551  #define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
27552  #define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
27553 /* =======================================================  LOCOUTCR  ======================================================== */
27554  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
27555  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
27556 /* ========================================================  VBTCR2  ========================================================= */
27557  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos             (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
27558  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk             (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
27559  #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos              (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
27560  #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk              (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
27561 /* =========================================================  VBTSR  ========================================================= */
27562  #define R_SYSTEM_VBTSR_VBTRVLD_Pos                (4UL)          /*!< VBTRVLD (Bit 4)                                       */
27563  #define R_SYSTEM_VBTSR_VBTRVLD_Msk                (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
27564  #define R_SYSTEM_VBTSR_VBTBLDF_Pos                (1UL)          /*!< VBTBLDF (Bit 1)                                       */
27565  #define R_SYSTEM_VBTSR_VBTBLDF_Msk                (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
27566  #define R_SYSTEM_VBTSR_VBTRDF_Pos                 (0UL)          /*!< VBTRDF (Bit 0)                                        */
27567  #define R_SYSTEM_VBTSR_VBTRDF_Msk                 (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
27568 /* =======================================================  VBTCMPCR  ======================================================== */
27569  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos             (0UL)          /*!< VBTCMPE (Bit 0)                                       */
27570  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk             (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
27571 /* =======================================================  VBTLVDICR  ======================================================= */
27572  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos         (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
27573  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk         (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
27574  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos           (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
27575  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk           (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
27576 /* =======================================================  VBTWCTLR  ======================================================== */
27577  #define R_SYSTEM_VBTWCTLR_VWEN_Pos                (0UL)          /*!< VWEN (Bit 0)                                          */
27578  #define R_SYSTEM_VBTWCTLR_VWEN_Msk                (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
27579 /* ======================================================  VBTWCH0OTSR  ====================================================== */
27580  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos       (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
27581  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk       (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
27582  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos       (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
27583  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk       (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
27584  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos        (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
27585  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk        (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
27586  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos        (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
27587  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk        (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
27588  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos        (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
27589  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk        (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
27590 /* ======================================================  VBTWCH1OTSR  ====================================================== */
27591  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos       (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
27592  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk       (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
27593  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos       (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
27594  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk       (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
27595  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos        (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
27596  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk        (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
27597  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos        (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
27598  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk        (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
27599  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos        (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
27600  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk        (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
27601 /* ======================================================  VBTWCH2OTSR  ====================================================== */
27602  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos       (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
27603  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk       (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
27604  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos       (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
27605  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk       (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
27606  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos        (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
27607  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk        (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
27608  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos        (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
27609  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk        (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
27610  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos        (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
27611  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk        (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
27612 /* =======================================================  VBTICTLR  ======================================================== */
27613  #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos            (2UL)          /*!< VCH2INEN (Bit 2)                                      */
27614  #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk            (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
27615  #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos            (1UL)          /*!< VCH1INEN (Bit 1)                                      */
27616  #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk            (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
27617  #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos            (0UL)          /*!< VCH0INEN (Bit 0)                                      */
27618  #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk            (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
27619 /* =======================================================  VBTOCTLR  ======================================================== */
27620  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos           (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
27621  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk           (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
27622  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos           (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
27623  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk           (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
27624  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos           (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
27625  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk           (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
27626  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos             (2UL)          /*!< VCH2OEN (Bit 2)                                       */
27627  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk             (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
27628  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos             (1UL)          /*!< VCH1OEN (Bit 1)                                       */
27629  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk             (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
27630  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos             (0UL)          /*!< VCH0OEN (Bit 0)                                       */
27631  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk             (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
27632 /* ========================================================  VBTWTER  ======================================================== */
27633  #define R_SYSTEM_VBTWTER_VAGTUE_Pos               (5UL)          /*!< VAGTUE (Bit 5)                                        */
27634  #define R_SYSTEM_VBTWTER_VAGTUE_Msk               (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
27635  #define R_SYSTEM_VBTWTER_VRTCAE_Pos               (4UL)          /*!< VRTCAE (Bit 4)                                        */
27636  #define R_SYSTEM_VBTWTER_VRTCAE_Msk               (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
27637  #define R_SYSTEM_VBTWTER_VRTCIE_Pos               (3UL)          /*!< VRTCIE (Bit 3)                                        */
27638  #define R_SYSTEM_VBTWTER_VRTCIE_Msk               (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
27639  #define R_SYSTEM_VBTWTER_VCH2E_Pos                (2UL)          /*!< VCH2E (Bit 2)                                         */
27640  #define R_SYSTEM_VBTWTER_VCH2E_Msk                (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
27641  #define R_SYSTEM_VBTWTER_VCH1E_Pos                (1UL)          /*!< VCH1E (Bit 1)                                         */
27642  #define R_SYSTEM_VBTWTER_VCH1E_Msk                (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
27643  #define R_SYSTEM_VBTWTER_VCH0E_Pos                (0UL)          /*!< VCH0E (Bit 0)                                         */
27644  #define R_SYSTEM_VBTWTER_VCH0E_Msk                (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
27645 /* ========================================================  VBTWEGR  ======================================================== */
27646  #define R_SYSTEM_VBTWEGR_VCH2EG_Pos               (2UL)          /*!< VCH2EG (Bit 2)                                        */
27647  #define R_SYSTEM_VBTWEGR_VCH2EG_Msk               (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
27648  #define R_SYSTEM_VBTWEGR_VCH1EG_Pos               (1UL)          /*!< VCH1EG (Bit 1)                                        */
27649  #define R_SYSTEM_VBTWEGR_VCH1EG_Msk               (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
27650  #define R_SYSTEM_VBTWEGR_VCH0EG_Pos               (0UL)          /*!< VCH0EG (Bit 0)                                        */
27651  #define R_SYSTEM_VBTWEGR_VCH0EG_Msk               (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
27652 /* ========================================================  VBTWFR  ========================================================= */
27653  #define R_SYSTEM_VBTWFR_VAGTUF_Pos                (5UL)          /*!< VAGTUF (Bit 5)                                        */
27654  #define R_SYSTEM_VBTWFR_VAGTUF_Msk                (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
27655  #define R_SYSTEM_VBTWFR_VRTCAF_Pos                (4UL)          /*!< VRTCAF (Bit 4)                                        */
27656  #define R_SYSTEM_VBTWFR_VRTCAF_Msk                (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
27657  #define R_SYSTEM_VBTWFR_VRTCIF_Pos                (3UL)          /*!< VRTCIF (Bit 3)                                        */
27658  #define R_SYSTEM_VBTWFR_VRTCIF_Msk                (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
27659  #define R_SYSTEM_VBTWFR_VCH2F_Pos                 (2UL)          /*!< VCH2F (Bit 2)                                         */
27660  #define R_SYSTEM_VBTWFR_VCH2F_Msk                 (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
27661  #define R_SYSTEM_VBTWFR_VCH1F_Pos                 (1UL)          /*!< VCH1F (Bit 1)                                         */
27662  #define R_SYSTEM_VBTWFR_VCH1F_Msk                 (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
27663  #define R_SYSTEM_VBTWFR_VCH0F_Pos                 (0UL)          /*!< VCH0F (Bit 0)                                         */
27664  #define R_SYSTEM_VBTWFR_VCH0F_Msk                 (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
27665 /* ========================================================  VBTBKR  ========================================================= */
27666  #define R_SYSTEM_VBTBKR_VBTBKR_Pos                (0UL)          /*!< VBTBKR (Bit 0)                                        */
27667  #define R_SYSTEM_VBTBKR_VBTBKR_Msk                (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27668 /* ========================================================  FWEPROR  ======================================================== */
27669  #define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
27670  #define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
27671 /* ========================================================  PLL2CCR  ======================================================== */
27672  #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
27673  #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
27674  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
27675  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
27676  #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
27677  #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
27678 /* ========================================================  PLL2CR  ========================================================= */
27679  #define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
27680  #define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
27681 /* ======================================================  USBCKDIVCR  ======================================================= */
27682  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos          (0UL)          /*!< USBCKDIV (Bit 0)                                      */
27683  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk          (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
27684 /* ======================================================  OCTACKDIVCR  ====================================================== */
27685  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos        (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
27686  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk        (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
27687 /* =====================================================  SCISPICKDIVCR  ===================================================== */
27688  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
27689  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
27690 /* =====================================================  CANFDCKDIVCR  ====================================================== */
27691  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
27692  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
27693 /* ======================================================  GPTCKDIVCR  ======================================================= */
27694  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
27695  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
27696 /* =====================================================  USB60CKDIVCR  ====================================================== */
27697  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos      (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
27698  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk      (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
27699 /* ======================================================  CECCKDIVCR  ======================================================= */
27700  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
27701  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
27702 /* ======================================================  I3CCKDIVCR  ======================================================= */
27703  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
27704  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
27705 /* ======================================================  IICCKDIVCR  ======================================================= */
27706  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
27707  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
27708 /* ========================================================  USBCKCR  ======================================================== */
27709  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos             (0UL)          /*!< USBCKSEL (Bit 0)                                      */
27710  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk             (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
27711  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos            (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
27712  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk            (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
27713  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos            (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
27714  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk            (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
27715 /* =======================================================  OCTACKCR  ======================================================== */
27716  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos           (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
27717  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk           (0x7UL)        /*!< OCTACKSEL (Bitfield-Mask: 0x07)                       */
27718  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos          (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
27719  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk          (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
27720  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos          (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
27721  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk          (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
27722 /* ======================================================  SCISPICKCR  ======================================================= */
27723  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
27724  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
27725  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
27726  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
27727  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
27728  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
27729 /* =======================================================  CANFDCKCR  ======================================================= */
27730  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
27731  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
27732  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
27733  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
27734  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
27735  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
27736 /* ========================================================  GPTCKCR  ======================================================== */
27737  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
27738  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
27739  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
27740  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
27741  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
27742  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
27743 /* =======================================================  USB60CKCR  ======================================================= */
27744  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos         (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
27745  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk         (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
27746  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos        (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
27747  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk        (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
27748  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos        (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
27749  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk        (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
27750 /* ========================================================  CECCKCR  ======================================================== */
27751  #define R_SYSTEM_CECCKCR_CECCKSEL_Pos             (0UL)          /*!< CECCKSEL (Bit 0)                                      */
27752  #define R_SYSTEM_CECCKCR_CECCKSEL_Msk             (0x7UL)        /*!< CECCKSEL (Bitfield-Mask: 0x07)                        */
27753  #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos            (6UL)          /*!< CECCKSREQ (Bit 6)                                     */
27754  #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk            (0x40UL)       /*!< CECCKSREQ (Bitfield-Mask: 0x01)                       */
27755  #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos            (7UL)          /*!< CECCKSRDY (Bit 7)                                     */
27756  #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk            (0x80UL)       /*!< CECCKSRDY (Bitfield-Mask: 0x01)                       */
27757 /* ========================================================  IICCKCR  ======================================================== */
27758  #define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
27759  #define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
27760  #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
27761  #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
27762  #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
27763  #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
27764 /* ========================================================  I3CCKCR  ======================================================== */
27765  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos             (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
27766  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk             (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
27767  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos            (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
27768  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk            (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
27769  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos            (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
27770  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk            (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
27771 /* =======================================================  SNZREQCR1  ======================================================= */
27772  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
27773  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
27774  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
27775  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
27776  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
27777  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
27778 /* =======================================================  SNZEDCR1  ======================================================== */
27779  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos           (0UL)          /*!< AGT3UNFED (Bit 0)                                     */
27780  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk           (0x1UL)        /*!< AGT3UNFED (Bitfield-Mask: 0x01)                       */
27781 /* ========================================================  CGFSAR  ========================================================= */
27782  #define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
27783  #define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
27784  #define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
27785  #define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
27786  #define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
27787  #define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
27788  #define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
27789  #define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
27790  #define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
27791  #define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
27792  #define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
27793  #define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
27794  #define R_SYSTEM_CGFSAR_NONSEC07_Pos              (7UL)          /*!< NONSEC07 (Bit 7)                                      */
27795  #define R_SYSTEM_CGFSAR_NONSEC07_Msk              (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
27796  #define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
27797  #define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
27798  #define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
27799  #define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
27800  #define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
27801  #define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
27802  #define R_SYSTEM_CGFSAR_NONSEC12_Pos              (12UL)         /*!< NONSEC12 (Bit 12)                                     */
27803  #define R_SYSTEM_CGFSAR_NONSEC12_Msk              (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
27804  #define R_SYSTEM_CGFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
27805  #define R_SYSTEM_CGFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
27806  #define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
27807  #define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
27808 /* ========================================================  LPMSAR  ========================================================= */
27809  #define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
27810  #define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
27811  #define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
27812  #define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
27813  #define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
27814  #define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
27815  #define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
27816  #define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
27817  #define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
27818  #define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
27819 /* ========================================================  LVDSAR  ========================================================= */
27820  #define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
27821  #define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
27822  #define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
27823  #define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
27824 /* ========================================================  RSTSAR  ========================================================= */
27825  #define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
27826  #define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
27827  #define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
27828  #define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
27829  #define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
27830  #define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
27831 /* ========================================================  BBFSAR  ========================================================= */
27832  #define R_SYSTEM_BBFSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
27833  #define R_SYSTEM_BBFSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
27834  #define R_SYSTEM_BBFSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
27835  #define R_SYSTEM_BBFSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
27836  #define R_SYSTEM_BBFSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
27837  #define R_SYSTEM_BBFSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
27838  #define R_SYSTEM_BBFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
27839  #define R_SYSTEM_BBFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
27840  #define R_SYSTEM_BBFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
27841  #define R_SYSTEM_BBFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
27842  #define R_SYSTEM_BBFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
27843  #define R_SYSTEM_BBFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
27844  #define R_SYSTEM_BBFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
27845  #define R_SYSTEM_BBFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
27846  #define R_SYSTEM_BBFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
27847  #define R_SYSTEM_BBFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
27848  #define R_SYSTEM_BBFSAR_NONSEC21_Pos              (21UL)         /*!< NONSEC21 (Bit 21)                                     */
27849  #define R_SYSTEM_BBFSAR_NONSEC21_Msk              (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
27850  #define R_SYSTEM_BBFSAR_NONSEC22_Pos              (22UL)         /*!< NONSEC22 (Bit 22)                                     */
27851  #define R_SYSTEM_BBFSAR_NONSEC22_Msk              (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
27852  #define R_SYSTEM_BBFSAR_NONSEC23_Pos              (23UL)         /*!< NONSEC23 (Bit 23)                                     */
27853  #define R_SYSTEM_BBFSAR_NONSEC23_Msk              (0x800000UL)   /*!< NONSEC23 (Bitfield-Mask: 0x01)                        */
27854 /* ========================================================  DPFSAR  ========================================================= */
27855  #define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
27856  #define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
27857  #define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
27858  #define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
27859  #define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
27860  #define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
27861  #define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
27862  #define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
27863  #define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
27864  #define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
27865  #define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
27866  #define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
27867  #define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
27868  #define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
27869  #define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
27870  #define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
27871  #define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
27872  #define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
27873  #define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
27874  #define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
27875  #define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
27876  #define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
27877  #define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
27878  #define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
27879  #define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
27880  #define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
27881  #define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
27882  #define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
27883  #define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
27884  #define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
27885  #define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
27886  #define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
27887  #define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
27888  #define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
27889  #define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
27890  #define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
27891  #define R_SYSTEM_DPFSAR_DPFSA18_Pos               (18UL)         /*!< DPFSA18 (Bit 18)                                      */
27892  #define R_SYSTEM_DPFSAR_DPFSA18_Msk               (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
27893  #define R_SYSTEM_DPFSAR_DPFSA19_Pos               (19UL)         /*!< DPFSA19 (Bit 19)                                      */
27894  #define R_SYSTEM_DPFSAR_DPFSA19_Msk               (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
27895  #define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
27896  #define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
27897  #define R_SYSTEM_DPFSAR_DPFSA24_Pos               (24UL)         /*!< DPFSA24 (Bit 24)                                      */
27898  #define R_SYSTEM_DPFSAR_DPFSA24_Msk               (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
27899  #define R_SYSTEM_DPFSAR_DPFSA26_Pos               (26UL)         /*!< DPFSA26 (Bit 26)                                      */
27900  #define R_SYSTEM_DPFSAR_DPFSA26_Msk               (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
27901  #define R_SYSTEM_DPFSAR_DPFSA27_Pos               (27UL)         /*!< DPFSA27 (Bit 27)                                      */
27902  #define R_SYSTEM_DPFSAR_DPFSA27_Msk               (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
27903 /* ========================================================  DPSWCR  ========================================================= */
27904  #define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
27905  #define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
27906 /* ======================================================  VBATTMNSELR  ====================================================== */
27907  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos       (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
27908  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk       (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
27909 /* =======================================================  VBATTMONR  ======================================================= */
27910  #define R_SYSTEM_VBATTMONR_VBATTMON_Pos           (0UL)          /*!< VBATTMON (Bit 0)                                      */
27911  #define R_SYSTEM_VBATTMONR_VBATTMON_Msk           (0x1UL)        /*!< VBATTMON (Bitfield-Mask: 0x01)                        */
27912 /* ========================================================  VBTBER  ========================================================= */
27913  #define R_SYSTEM_VBTBER_VBAE_Pos                  (3UL)          /*!< VBAE (Bit 3)                                          */
27914  #define R_SYSTEM_VBTBER_VBAE_Msk                  (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
27915 
27916 /* =========================================================================================================================== */
27917 /* ================                                         R_TSN_CAL                                         ================ */
27918 /* =========================================================================================================================== */
27919 
27920 /* =========================================================  TSCDR  ========================================================= */
27921  #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
27922  #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
27923 
27924 /* =========================================================================================================================== */
27925 /* ================                                        R_TSN_CTRL                                         ================ */
27926 /* =========================================================================================================================== */
27927 
27928 /* =========================================================  TSCR  ========================================================== */
27929  #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
27930  #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
27931  #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
27932  #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
27933 
27934 /* =========================================================================================================================== */
27935 /* ================                                         R_USB_FS0                                         ================ */
27936 /* =========================================================================================================================== */
27937 
27938 /* ========================================================  SYSCFG  ========================================================= */
27939  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
27940  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
27941  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
27942  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
27943  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
27944  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
27945  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
27946  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
27947  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
27948  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
27949  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
27950  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
27951  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
27952  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
27953 /* ========================================================  BUSWAIT  ======================================================== */
27954  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
27955  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
27956 /* ========================================================  SYSSTS0  ======================================================== */
27957  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
27958  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
27959  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
27960  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
27961  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
27962  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
27963  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
27964  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
27965  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
27966  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
27967 /* ========================================================  PLLSTA  ========================================================= */
27968  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
27969  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
27970 /* =======================================================  DVSTCTR0  ======================================================== */
27971  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
27972  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
27973  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
27974  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
27975  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
27976  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
27977  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
27978  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
27979  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
27980  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
27981  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
27982  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
27983  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
27984  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
27985  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
27986  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
27987  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
27988  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
27989 /* =======================================================  TESTMODE  ======================================================== */
27990  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
27991  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
27992 /* ========================================================  CFIFOL  ========================================================= */
27993 /* ========================================================  CFIFOLL  ======================================================== */
27994 /* =========================================================  CFIFO  ========================================================= */
27995 /* ========================================================  CFIFOH  ========================================================= */
27996 /* ========================================================  CFIFOHH  ======================================================== */
27997 /* ========================================================  D0FIFOL  ======================================================== */
27998 /* =======================================================  D0FIFOLL  ======================================================== */
27999 /* ========================================================  D0FIFO  ========================================================= */
28000 /* ========================================================  D0FIFOH  ======================================================== */
28001 /* =======================================================  D0FIFOHH  ======================================================== */
28002 /* ========================================================  D1FIFOL  ======================================================== */
28003 /* =======================================================  D1FIFOLL  ======================================================== */
28004 /* ========================================================  D1FIFO  ========================================================= */
28005 /* ========================================================  D1FIFOH  ======================================================== */
28006 /* =======================================================  D1FIFOHH  ======================================================== */
28007 /* =======================================================  CFIFOSEL  ======================================================== */
28008  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
28009  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28010  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
28011  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28012  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
28013  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28014  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
28015  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28016  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
28017  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
28018  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
28019  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28020 /* =======================================================  CFIFOCTR  ======================================================== */
28021  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
28022  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28023  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
28024  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28025  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
28026  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28027  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
28028  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28029 /* =======================================================  D0FIFOSEL  ======================================================= */
28030  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
28031  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28032  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
28033  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28034  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
28035  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
28036  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
28037  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
28038  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
28039  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28040  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
28041  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28042  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
28043  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28044 /* =======================================================  D0FIFOCTR  ======================================================= */
28045  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
28046  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28047  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
28048  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28049  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
28050  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28051  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
28052  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28053 /* =======================================================  D1FIFOSEL  ======================================================= */
28054  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
28055  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28056  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
28057  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28058  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
28059  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
28060  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
28061  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
28062  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
28063  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28064  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
28065  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28066  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
28067  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28068 /* =======================================================  D1FIFOCTR  ======================================================= */
28069  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
28070  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28071  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
28072  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28073  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
28074  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28075  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
28076  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28077 /* ========================================================  INTENB0  ======================================================== */
28078  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
28079  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
28080  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
28081  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
28082  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
28083  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
28084  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
28085  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
28086  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
28087  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
28088  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
28089  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
28090  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
28091  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
28092  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
28093  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
28094 /* ========================================================  INTENB1  ======================================================== */
28095  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
28096  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
28097  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
28098  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
28099  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
28100  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
28101  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
28102  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
28103  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
28104  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
28105  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
28106  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
28107  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
28108  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
28109  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
28110  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
28111 /* ========================================================  BRDYENB  ======================================================== */
28112  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
28113  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
28114 /* ========================================================  NRDYENB  ======================================================== */
28115  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
28116  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
28117 /* ========================================================  BEMPENB  ======================================================== */
28118  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
28119  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
28120 /* ========================================================  SOFCFG  ========================================================= */
28121  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
28122  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
28123  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
28124  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
28125  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
28126  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
28127  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
28128  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
28129 /* ========================================================  PHYSET  ========================================================= */
28130  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
28131  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
28132  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
28133  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
28134  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
28135  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
28136  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
28137  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
28138  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
28139  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
28140  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
28141  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
28142  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
28143  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
28144 /* ========================================================  INTSTS0  ======================================================== */
28145  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
28146  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
28147  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
28148  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
28149  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
28150  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
28151  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
28152  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
28153  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
28154  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
28155  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
28156  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
28157  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
28158  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
28159  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
28160  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
28161  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
28162  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
28163  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
28164  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
28165  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
28166  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
28167  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
28168  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
28169 /* ========================================================  INTSTS1  ======================================================== */
28170  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
28171  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
28172  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
28173  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
28174  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
28175  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
28176  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
28177  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
28178  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
28179  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
28180  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
28181  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
28182  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
28183  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
28184  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
28185  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
28186  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
28187  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
28188  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
28189  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
28190 /* ========================================================  BRDYSTS  ======================================================== */
28191  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
28192  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
28193 /* ========================================================  NRDYSTS  ======================================================== */
28194  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
28195  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
28196 /* ========================================================  BEMPSTS  ======================================================== */
28197  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
28198  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
28199 /* ========================================================  FRMNUM  ========================================================= */
28200  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
28201  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
28202  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
28203  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
28204  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
28205  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
28206 /* ========================================================  UFRMNUM  ======================================================== */
28207  #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
28208  #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
28209  #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
28210  #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
28211 /* ========================================================  USBADDR  ======================================================== */
28212  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
28213  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
28214  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
28215  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
28216 /* ========================================================  USBREQ  ========================================================= */
28217  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
28218  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
28219  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
28220  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
28221 /* ========================================================  USBVAL  ========================================================= */
28222  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
28223  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
28224 /* ========================================================  USBINDX  ======================================================== */
28225  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
28226  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
28227 /* ========================================================  USBLENG  ======================================================== */
28228  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
28229  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
28230 /* ========================================================  DCPCFG  ========================================================= */
28231  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
28232  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
28233  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
28234  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28235  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
28236  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28237 /* ========================================================  DCPMAXP  ======================================================== */
28238  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
28239  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28240  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
28241  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
28242 /* ========================================================  DCPCTR  ========================================================= */
28243  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
28244  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28245  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
28246  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
28247  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
28248  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
28249  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
28250  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28251  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
28252  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28253  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
28254  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28255  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
28256  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28257  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
28258  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
28259  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
28260  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28261 /* ========================================================  PIPESEL  ======================================================== */
28262  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
28263  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
28264 /* ========================================================  PIPECFG  ======================================================== */
28265  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
28266  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
28267  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
28268  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
28269  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
28270  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
28271  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
28272  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28273  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
28274  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28275  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
28276  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
28277 /* =======================================================  PIPEMAXP  ======================================================== */
28278  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
28279  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28280  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
28281  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
28282 /* =======================================================  PIPEPERI  ======================================================== */
28283  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
28284  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
28285  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
28286  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
28287 /* =======================================================  PIPE_CTR  ======================================================== */
28288  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
28289  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28290  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
28291  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
28292  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
28293  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
28294  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
28295  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
28296  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
28297  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
28298  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
28299  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
28300  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
28301  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28302  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
28303  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28304  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
28305  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28306  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
28307  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28308  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
28309  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28310 /* ========================================================  DEVADD  ========================================================= */
28311  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
28312  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
28313  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
28314  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
28315  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
28316  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
28317 /* ======================================================  USBBCCTRL0  ======================================================= */
28318  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
28319  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
28320  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
28321  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
28322  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
28323  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
28324  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
28325  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
28326  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
28327  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
28328  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
28329  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
28330  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
28331  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
28332  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
28333  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
28334  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
28335  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
28336 /* ========================================================  UCKSEL  ========================================================= */
28337  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
28338  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
28339 /* =========================================================  USBMC  ========================================================= */
28340  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
28341  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
28342  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
28343  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
28344 /* ========================================================  PHYSLEW  ======================================================== */
28345  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
28346  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
28347  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
28348  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
28349  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
28350  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
28351  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
28352  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
28353 /* ========================================================  LPCTRL  ========================================================= */
28354  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
28355  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
28356 /* =========================================================  LPSTS  ========================================================= */
28357  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
28358  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
28359 /* ========================================================  BCCTRL  ========================================================= */
28360  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
28361  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
28362  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
28363  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
28364  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
28365  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
28366  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
28367  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
28368  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
28369  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
28370  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
28371  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
28372  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
28373  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
28374  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
28375  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
28376 /* =======================================================  PL1CTRL1  ======================================================== */
28377  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
28378  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
28379  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
28380  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
28381  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
28382  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
28383  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
28384  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
28385  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
28386  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
28387  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
28388  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
28389 /* =======================================================  PL1CTRL2  ======================================================== */
28390  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
28391  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
28392  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
28393  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
28394 /* =======================================================  HL1CTRL1  ======================================================== */
28395  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
28396  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
28397  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
28398  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
28399 /* =======================================================  HL1CTRL2  ======================================================== */
28400  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
28401  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
28402  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
28403  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
28404  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
28405  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
28406  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
28407  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
28408 /* ========================================================  DPUSR0R  ======================================================== */
28409  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
28410  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
28411  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
28412  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
28413  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
28414  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
28415 /* ========================================================  DPUSR1R  ======================================================== */
28416  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
28417  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
28418  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
28419  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
28420  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
28421  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
28422  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
28423  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
28424  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
28425  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
28426  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
28427  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
28428 /* ========================================================  DPUSR2R  ======================================================== */
28429  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
28430  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
28431  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
28432  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
28433  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
28434  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
28435  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
28436  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
28437  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
28438  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
28439  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
28440  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
28441 /* ========================================================  DPUSRCR  ======================================================== */
28442  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
28443  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
28444  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
28445  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
28446 /* ======================================================  DPUSR0R_FS  ======================================================= */
28447  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
28448  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
28449  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
28450  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
28451  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
28452  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
28453  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
28454  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
28455  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
28456  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
28457  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
28458  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
28459  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
28460  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
28461  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
28462  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
28463  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
28464  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
28465 /* ======================================================  DPUSR1R_FS  ======================================================= */
28466  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
28467  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
28468  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
28469  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
28470  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
28471  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
28472  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
28473  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
28474  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
28475  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
28476  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
28477  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
28478  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
28479  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
28480  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
28481  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
28482  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
28483  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
28484  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
28485  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
28486 
28487 /* =========================================================================================================================== */
28488 /* ================                                           R_WDT                                           ================ */
28489 /* =========================================================================================================================== */
28490 
28491 /* =========================================================  WDTRR  ========================================================= */
28492  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
28493  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
28494 /* =========================================================  WDTCR  ========================================================= */
28495  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
28496  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
28497  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
28498  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
28499  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
28500  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
28501  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
28502  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
28503 /* =========================================================  WDTSR  ========================================================= */
28504  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
28505  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
28506  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
28507  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
28508  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
28509  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
28510 /* ========================================================  WDTRCR  ========================================================= */
28511  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
28512  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
28513 /* =======================================================  WDTCSTPR  ======================================================== */
28514  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
28515  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
28516 
28517 /* =========================================================================================================================== */
28518 /* ================                                         R_USB_HS0                                         ================ */
28519 /* =========================================================================================================================== */
28520 
28521 /* ========================================================  SYSCFG  ========================================================= */
28522  #define R_USB_HS0_SYSCFG_CNEN_Pos         (8UL)          /*!< CNEN (Bit 8)                                          */
28523  #define R_USB_HS0_SYSCFG_CNEN_Msk         (0x100UL)      /*!< CNEN (Bitfield-Mask: 0x01)                            */
28524  #define R_USB_HS0_SYSCFG_HSE_Pos          (7UL)          /*!< HSE (Bit 7)                                           */
28525  #define R_USB_HS0_SYSCFG_HSE_Msk          (0x80UL)       /*!< HSE (Bitfield-Mask: 0x01)                             */
28526  #define R_USB_HS0_SYSCFG_DCFM_Pos         (6UL)          /*!< DCFM (Bit 6)                                          */
28527  #define R_USB_HS0_SYSCFG_DCFM_Msk         (0x40UL)       /*!< DCFM (Bitfield-Mask: 0x01)                            */
28528  #define R_USB_HS0_SYSCFG_DRPD_Pos         (5UL)          /*!< DRPD (Bit 5)                                          */
28529  #define R_USB_HS0_SYSCFG_DRPD_Msk         (0x20UL)       /*!< DRPD (Bitfield-Mask: 0x01)                            */
28530  #define R_USB_HS0_SYSCFG_DPRPU_Pos        (4UL)          /*!< DPRPU (Bit 4)                                         */
28531  #define R_USB_HS0_SYSCFG_DPRPU_Msk        (0x10UL)       /*!< DPRPU (Bitfield-Mask: 0x01)                           */
28532  #define R_USB_HS0_SYSCFG_USBE_Pos         (0UL)          /*!< USBE (Bit 0)                                          */
28533  #define R_USB_HS0_SYSCFG_USBE_Msk         (0x1UL)        /*!< USBE (Bitfield-Mask: 0x01)                            */
28534 /* ========================================================  BUSWAIT  ======================================================== */
28535  #define R_USB_HS0_BUSWAIT_BWAIT_Pos       (0UL)          /*!< BWAIT (Bit 0)                                         */
28536  #define R_USB_HS0_BUSWAIT_BWAIT_Msk       (0xfUL)        /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
28537 /* ========================================================  SYSSTS0  ======================================================== */
28538  #define R_USB_HS0_SYSSTS0_HTACT_Pos       (6UL)          /*!< HTACT (Bit 6)                                         */
28539  #define R_USB_HS0_SYSSTS0_HTACT_Msk       (0x40UL)       /*!< HTACT (Bitfield-Mask: 0x01)                           */
28540  #define R_USB_HS0_SYSSTS0_SOFEA_Pos       (5UL)          /*!< SOFEA (Bit 5)                                         */
28541  #define R_USB_HS0_SYSSTS0_SOFEA_Msk       (0x20UL)       /*!< SOFEA (Bitfield-Mask: 0x01)                           */
28542  #define R_USB_HS0_SYSSTS0_IDMON_Pos       (2UL)          /*!< IDMON (Bit 2)                                         */
28543  #define R_USB_HS0_SYSSTS0_IDMON_Msk       (0x4UL)        /*!< IDMON (Bitfield-Mask: 0x01)                           */
28544  #define R_USB_HS0_SYSSTS0_LNST_Pos        (0UL)          /*!< LNST (Bit 0)                                          */
28545  #define R_USB_HS0_SYSSTS0_LNST_Msk        (0x3UL)        /*!< LNST (Bitfield-Mask: 0x03)                            */
28546  #define R_USB_HS0_SYSSTS0_OVCMON_Pos      (14UL)         /*!< OVCMON (Bit 14)                                       */
28547  #define R_USB_HS0_SYSSTS0_OVCMON_Msk      (0xc000UL)     /*!< OVCMON (Bitfield-Mask: 0x03)                          */
28548 /* ========================================================  PLLSTA  ========================================================= */
28549  #define R_USB_HS0_PLLSTA_PLLLOCK_Pos      (0UL)          /*!< PLLLOCK (Bit 0)                                       */
28550  #define R_USB_HS0_PLLSTA_PLLLOCK_Msk      (0x1UL)        /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
28551 /* =======================================================  DVSTCTR0  ======================================================== */
28552  #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos    (11UL)         /*!< HNPBTOA (Bit 11)                                      */
28553  #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)      /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
28554  #define R_USB_HS0_DVSTCTR0_EXICEN_Pos     (10UL)         /*!< EXICEN (Bit 10)                                       */
28555  #define R_USB_HS0_DVSTCTR0_EXICEN_Msk     (0x400UL)      /*!< EXICEN (Bitfield-Mask: 0x01)                          */
28556  #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos     (9UL)          /*!< VBUSEN (Bit 9)                                        */
28557  #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)      /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
28558  #define R_USB_HS0_DVSTCTR0_WKUP_Pos       (8UL)          /*!< WKUP (Bit 8)                                          */
28559  #define R_USB_HS0_DVSTCTR0_WKUP_Msk       (0x100UL)      /*!< WKUP (Bitfield-Mask: 0x01)                            */
28560  #define R_USB_HS0_DVSTCTR0_RWUPE_Pos      (7UL)          /*!< RWUPE (Bit 7)                                         */
28561  #define R_USB_HS0_DVSTCTR0_RWUPE_Msk      (0x80UL)       /*!< RWUPE (Bitfield-Mask: 0x01)                           */
28562  #define R_USB_HS0_DVSTCTR0_USBRST_Pos     (6UL)          /*!< USBRST (Bit 6)                                        */
28563  #define R_USB_HS0_DVSTCTR0_USBRST_Msk     (0x40UL)       /*!< USBRST (Bitfield-Mask: 0x01)                          */
28564  #define R_USB_HS0_DVSTCTR0_RESUME_Pos     (5UL)          /*!< RESUME (Bit 5)                                        */
28565  #define R_USB_HS0_DVSTCTR0_RESUME_Msk     (0x20UL)       /*!< RESUME (Bitfield-Mask: 0x01)                          */
28566  #define R_USB_HS0_DVSTCTR0_UACT_Pos       (4UL)          /*!< UACT (Bit 4)                                          */
28567  #define R_USB_HS0_DVSTCTR0_UACT_Msk       (0x10UL)       /*!< UACT (Bitfield-Mask: 0x01)                            */
28568  #define R_USB_HS0_DVSTCTR0_RHST_Pos       (0UL)          /*!< RHST (Bit 0)                                          */
28569  #define R_USB_HS0_DVSTCTR0_RHST_Msk       (0x7UL)        /*!< RHST (Bitfield-Mask: 0x07)                            */
28570 /* =======================================================  TESTMODE  ======================================================== */
28571  #define R_USB_HS0_TESTMODE_UTST_Pos       (0UL)          /*!< UTST (Bit 0)                                          */
28572  #define R_USB_HS0_TESTMODE_UTST_Msk       (0xfUL)        /*!< UTST (Bitfield-Mask: 0x0f)                            */
28573 /* =========================================================  CFIFO  ========================================================= */
28574  #define R_USB_HS0_CFIFO_FIFOPORT_Pos      (0UL)          /*!< FIFOPORT (Bit 0)                                      */
28575  #define R_USB_HS0_CFIFO_FIFOPORT_Msk      (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
28576 /* ========================================================  CFIFOL  ========================================================= */
28577 /* ========================================================  CFIFOH  ========================================================= */
28578 /* ========================================================  CFIFOLL  ======================================================== */
28579 /* ========================================================  CFIFOHH  ======================================================== */
28580 /* ========================================================  D0FIFO  ========================================================= */
28581  #define R_USB_HS0_D0FIFO_FIFOPORT_Pos    (0UL)          /*!< FIFOPORT (Bit 0)                                      */
28582  #define R_USB_HS0_D0FIFO_FIFOPORT_Msk    (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
28583 /* ========================================================  D0FIFOL  ======================================================== */
28584 /* ========================================================  D0FIFOH  ======================================================== */
28585 /* =======================================================  D0FIFOLL  ======================================================== */
28586 /* =======================================================  D0FIFOHH  ======================================================== */
28587 /* ========================================================  D1FIFO  ========================================================= */
28588  #define R_USB_HS0_D1FIFO_FIFOPORT_Pos    (0UL)          /*!< FIFOPORT (Bit 0)                                      */
28589  #define R_USB_HS0_D1FIFO_FIFOPORT_Msk    (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
28590 /* ========================================================  D1FIFOL  ======================================================== */
28591 /* ========================================================  D1FIFOH  ======================================================== */
28592 /* =======================================================  D1FIFOLL  ======================================================== */
28593 /* =======================================================  D1FIFOHH  ======================================================== */
28594 /* =======================================================  CFIFOSEL  ======================================================== */
28595  #define R_USB_HS0_CFIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
28596  #define R_USB_HS0_CFIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28597  #define R_USB_HS0_CFIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
28598  #define R_USB_HS0_CFIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28599  #define R_USB_HS0_CFIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
28600  #define R_USB_HS0_CFIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28601  #define R_USB_HS0_CFIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
28602  #define R_USB_HS0_CFIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28603  #define R_USB_HS0_CFIFOSEL_ISEL_Pos           (5UL)        /*!< ISEL (Bit 5)                                          */
28604  #define R_USB_HS0_CFIFOSEL_ISEL_Msk           (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
28605  #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
28606  #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28607 /* =======================================================  CFIFOCTR  ======================================================== */
28608  #define R_USB_HS0_CFIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
28609  #define R_USB_HS0_CFIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28610  #define R_USB_HS0_CFIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
28611  #define R_USB_HS0_CFIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28612  #define R_USB_HS0_CFIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
28613  #define R_USB_HS0_CFIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28614  #define R_USB_HS0_CFIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
28615  #define R_USB_HS0_CFIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28616 /* =======================================================  D0FIFOSEL  ======================================================= */
28617  #define R_USB_HS0_D0FIFOSEL_RCNT_Pos          (15UL)       /*!< RCNT (Bit 15)                                         */
28618  #define R_USB_HS0_D0FIFOSEL_RCNT_Msk          (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28619  #define R_USB_HS0_D0FIFOSEL_REW_Pos           (14UL)       /*!< REW (Bit 14)                                          */
28620  #define R_USB_HS0_D0FIFOSEL_REW_Msk           (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28621  #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos         (13UL)       /*!< DCLRM (Bit 13)                                        */
28622  #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk         (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
28623  #define R_USB_HS0_D0FIFOSEL_DREQE_Pos         (12UL)       /*!< DREQE (Bit 12)                                        */
28624  #define R_USB_HS0_D0FIFOSEL_DREQE_Msk         (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
28625  #define R_USB_HS0_D0FIFOSEL_MBW_Pos           (10UL)       /*!< MBW (Bit 10)                                          */
28626  #define R_USB_HS0_D0FIFOSEL_MBW_Msk           (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28627  #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos        (8UL)        /*!< BIGEND (Bit 8)                                        */
28628  #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk        (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28629  #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos       (0UL)        /*!< CURPIPE (Bit 0)                                       */
28630  #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk       (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28631 /* =======================================================  D0FIFOCTR  ======================================================= */
28632  #define R_USB_HS0_D0FIFOCTR_BVAL_Pos          (15UL)       /*!< BVAL (Bit 15)                                         */
28633  #define R_USB_HS0_D0FIFOCTR_BVAL_Msk          (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28634  #define R_USB_HS0_D0FIFOCTR_BCLR_Pos          (14UL)       /*!< BCLR (Bit 14)                                         */
28635  #define R_USB_HS0_D0FIFOCTR_BCLR_Msk          (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28636  #define R_USB_HS0_D0FIFOCTR_FRDY_Pos          (13UL)       /*!< FRDY (Bit 13)                                         */
28637  #define R_USB_HS0_D0FIFOCTR_FRDY_Msk          (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28638  #define R_USB_HS0_D0FIFOCTR_DTLN_Pos          (0UL)        /*!< DTLN (Bit 0)                                          */
28639  #define R_USB_HS0_D0FIFOCTR_DTLN_Msk          (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28640 /* =======================================================  D1FIFOSEL  ======================================================= */
28641  #define R_USB_HS0_D1FIFOSEL_RCNT_Pos          (15UL)       /*!< RCNT (Bit 15)                                         */
28642  #define R_USB_HS0_D1FIFOSEL_RCNT_Msk          (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28643  #define R_USB_HS0_D1FIFOSEL_REW_Pos           (14UL)       /*!< REW (Bit 14)                                          */
28644  #define R_USB_HS0_D1FIFOSEL_REW_Msk           (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28645  #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos         (13UL)       /*!< DCLRM (Bit 13)                                        */
28646  #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk         (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
28647  #define R_USB_HS0_D1FIFOSEL_DREQE_Pos         (12UL)       /*!< DREQE (Bit 12)                                        */
28648  #define R_USB_HS0_D1FIFOSEL_DREQE_Msk         (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
28649  #define R_USB_HS0_D1FIFOSEL_MBW_Pos           (10UL)       /*!< MBW (Bit 10)                                          */
28650  #define R_USB_HS0_D1FIFOSEL_MBW_Msk           (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28651  #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos        (8UL)        /*!< BIGEND (Bit 8)                                        */
28652  #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk        (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28653  #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos       (0UL)        /*!< CURPIPE (Bit 0)                                       */
28654  #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk       (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28655 /* =======================================================  D1FIFOCTR  ======================================================= */
28656  #define R_USB_HS0_D1FIFOCTR_BVAL_Pos          (15UL)       /*!< BVAL (Bit 15)                                         */
28657  #define R_USB_HS0_D1FIFOCTR_BVAL_Msk          (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28658  #define R_USB_HS0_D1FIFOCTR_BCLR_Pos          (14UL)       /*!< BCLR (Bit 14)                                         */
28659  #define R_USB_HS0_D1FIFOCTR_BCLR_Msk          (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28660  #define R_USB_HS0_D1FIFOCTR_FRDY_Pos          (13UL)       /*!< FRDY (Bit 13)                                         */
28661  #define R_USB_HS0_D1FIFOCTR_FRDY_Msk          (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28662  #define R_USB_HS0_D1FIFOCTR_DTLN_Pos          (0UL)        /*!< DTLN (Bit 0)                                          */
28663  #define R_USB_HS0_D1FIFOCTR_DTLN_Msk          (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28664 /* ========================================================  INTENB0  ======================================================== */
28665  #define R_USB_HS0_INTENB0_VBSE_Pos            (15UL)       /*!< VBSE (Bit 15)                                         */
28666  #define R_USB_HS0_INTENB0_VBSE_Msk            (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
28667  #define R_USB_HS0_INTENB0_RSME_Pos            (14UL)       /*!< RSME (Bit 14)                                         */
28668  #define R_USB_HS0_INTENB0_RSME_Msk            (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
28669  #define R_USB_HS0_INTENB0_SOFE_Pos            (13UL)       /*!< SOFE (Bit 13)                                         */
28670  #define R_USB_HS0_INTENB0_SOFE_Msk            (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
28671  #define R_USB_HS0_INTENB0_DVSE_Pos            (12UL)       /*!< DVSE (Bit 12)                                         */
28672  #define R_USB_HS0_INTENB0_DVSE_Msk            (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
28673  #define R_USB_HS0_INTENB0_CTRE_Pos            (11UL)       /*!< CTRE (Bit 11)                                         */
28674  #define R_USB_HS0_INTENB0_CTRE_Msk            (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
28675  #define R_USB_HS0_INTENB0_BEMPE_Pos           (10UL)       /*!< BEMPE (Bit 10)                                        */
28676  #define R_USB_HS0_INTENB0_BEMPE_Msk           (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
28677  #define R_USB_HS0_INTENB0_NRDYE_Pos           (9UL)        /*!< NRDYE (Bit 9)                                         */
28678  #define R_USB_HS0_INTENB0_NRDYE_Msk           (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
28679  #define R_USB_HS0_INTENB0_BRDYE_Pos           (8UL)        /*!< BRDYE (Bit 8)                                         */
28680  #define R_USB_HS0_INTENB0_BRDYE_Msk           (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
28681 /* ========================================================  INTENB1  ======================================================== */
28682  #define R_USB_HS0_INTENB1_OVRCRE_Pos          (15UL)       /*!< OVRCRE (Bit 15)                                       */
28683  #define R_USB_HS0_INTENB1_OVRCRE_Msk          (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
28684  #define R_USB_HS0_INTENB1_BCHGE_Pos           (14UL)       /*!< BCHGE (Bit 14)                                        */
28685  #define R_USB_HS0_INTENB1_BCHGE_Msk           (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
28686  #define R_USB_HS0_INTENB1_DTCHE_Pos           (12UL)       /*!< DTCHE (Bit 12)                                        */
28687  #define R_USB_HS0_INTENB1_DTCHE_Msk           (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
28688  #define R_USB_HS0_INTENB1_ATTCHE_Pos          (11UL)       /*!< ATTCHE (Bit 11)                                       */
28689  #define R_USB_HS0_INTENB1_ATTCHE_Msk          (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
28690  #define R_USB_HS0_INTENB1_L1RSMENDE_Pos       (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
28691  #define R_USB_HS0_INTENB1_L1RSMENDE_Msk       (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
28692  #define R_USB_HS0_INTENB1_LPMENDE_Pos         (8UL)        /*!< LPMENDE (Bit 8)                                       */
28693  #define R_USB_HS0_INTENB1_LPMENDE_Msk         (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
28694  #define R_USB_HS0_INTENB1_EOFERRE_Pos         (6UL)        /*!< EOFERRE (Bit 6)                                       */
28695  #define R_USB_HS0_INTENB1_EOFERRE_Msk         (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
28696  #define R_USB_HS0_INTENB1_SIGNE_Pos           (5UL)        /*!< SIGNE (Bit 5)                                         */
28697  #define R_USB_HS0_INTENB1_SIGNE_Msk           (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
28698  #define R_USB_HS0_INTENB1_SACKE_Pos           (4UL)        /*!< SACKE (Bit 4)                                         */
28699  #define R_USB_HS0_INTENB1_SACKE_Msk           (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
28700  #define R_USB_HS0_INTENB1_PDDETINTE0_Pos      (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
28701  #define R_USB_HS0_INTENB1_PDDETINTE0_Msk      (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
28702 /* ========================================================  BRDYENB  ======================================================== */
28703  #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos       (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
28704  #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk       (0x3ffUL)    /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff)                      */
28705 /* ========================================================  NRDYENB  ======================================================== */
28706  #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos       (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
28707  #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk       (0x3ffUL)    /*!< PIPENRDYE (Bitfield-Mask: 0x3ff)                      */
28708 /* ========================================================  BEMPENB  ======================================================== */
28709  #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos       (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
28710  #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk       (0x3ffUL)    /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff)                      */
28711 /* ========================================================  SOFCFG  ========================================================= */
28712  #define R_USB_HS0_SOFCFG_TRNENSEL_Pos         (8UL)        /*!< TRNENSEL (Bit 8)                                      */
28713  #define R_USB_HS0_SOFCFG_TRNENSEL_Msk         (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
28714  #define R_USB_HS0_SOFCFG_BRDYM_Pos            (6UL)        /*!< BRDYM (Bit 6)                                         */
28715  #define R_USB_HS0_SOFCFG_BRDYM_Msk            (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
28716  #define R_USB_HS0_SOFCFG_INTL_Pos             (5UL)        /*!< INTL (Bit 5)                                          */
28717  #define R_USB_HS0_SOFCFG_INTL_Msk             (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
28718  #define R_USB_HS0_SOFCFG_EDGESTS_Pos          (4UL)        /*!< EDGESTS (Bit 4)                                       */
28719  #define R_USB_HS0_SOFCFG_EDGESTS_Msk          (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
28720 /* ========================================================  PHYSET  ========================================================= */
28721  #define R_USB_HS0_PHYSET_HSEB_Pos             (15UL)       /*!< HSEB (Bit 15)                                         */
28722  #define R_USB_HS0_PHYSET_HSEB_Msk             (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
28723  #define R_USB_HS0_PHYSET_REPSTART_Pos         (11UL)       /*!< REPSTART (Bit 11)                                     */
28724  #define R_USB_HS0_PHYSET_REPSTART_Msk         (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
28725  #define R_USB_HS0_PHYSET_REPSEL_Pos           (8UL)        /*!< REPSEL (Bit 8)                                        */
28726  #define R_USB_HS0_PHYSET_REPSEL_Msk           (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
28727  #define R_USB_HS0_PHYSET_CLKSEL_Pos           (4UL)        /*!< CLKSEL (Bit 4)                                        */
28728  #define R_USB_HS0_PHYSET_CLKSEL_Msk           (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
28729  #define R_USB_HS0_PHYSET_CDPEN_Pos            (3UL)        /*!< CDPEN (Bit 3)                                         */
28730  #define R_USB_HS0_PHYSET_CDPEN_Msk            (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
28731  #define R_USB_HS0_PHYSET_PLLRESET_Pos         (1UL)        /*!< PLLRESET (Bit 1)                                      */
28732  #define R_USB_HS0_PHYSET_PLLRESET_Msk         (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
28733  #define R_USB_HS0_PHYSET_DIRPD_Pos            (0UL)        /*!< DIRPD (Bit 0)                                         */
28734  #define R_USB_HS0_PHYSET_DIRPD_Msk            (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
28735 /* ========================================================  INTSTS0  ======================================================== */
28736  #define R_USB_HS0_INTSTS0_VBINT_Pos           (15UL)       /*!< VBINT (Bit 15)                                        */
28737  #define R_USB_HS0_INTSTS0_VBINT_Msk           (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
28738  #define R_USB_HS0_INTSTS0_RESM_Pos            (14UL)       /*!< RESM (Bit 14)                                         */
28739  #define R_USB_HS0_INTSTS0_RESM_Msk            (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
28740  #define R_USB_HS0_INTSTS0_SOFR_Pos            (13UL)       /*!< SOFR (Bit 13)                                         */
28741  #define R_USB_HS0_INTSTS0_SOFR_Msk            (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
28742  #define R_USB_HS0_INTSTS0_DVST_Pos            (12UL)       /*!< DVST (Bit 12)                                         */
28743  #define R_USB_HS0_INTSTS0_DVST_Msk            (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
28744  #define R_USB_HS0_INTSTS0_CTRT_Pos            (11UL)       /*!< CTRT (Bit 11)                                         */
28745  #define R_USB_HS0_INTSTS0_CTRT_Msk            (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
28746  #define R_USB_HS0_INTSTS0_BEMP_Pos            (10UL)       /*!< BEMP (Bit 10)                                         */
28747  #define R_USB_HS0_INTSTS0_BEMP_Msk            (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
28748  #define R_USB_HS0_INTSTS0_NRDY_Pos            (9UL)        /*!< NRDY (Bit 9)                                          */
28749  #define R_USB_HS0_INTSTS0_NRDY_Msk            (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
28750  #define R_USB_HS0_INTSTS0_BRDY_Pos            (8UL)        /*!< BRDY (Bit 8)                                          */
28751  #define R_USB_HS0_INTSTS0_BRDY_Msk            (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
28752  #define R_USB_HS0_INTSTS0_VBSTS_Pos           (7UL)        /*!< VBSTS (Bit 7)                                         */
28753  #define R_USB_HS0_INTSTS0_VBSTS_Msk           (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
28754  #define R_USB_HS0_INTSTS0_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
28755  #define R_USB_HS0_INTSTS0_DVSQ_Msk            (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
28756  #define R_USB_HS0_INTSTS0_VALID_Pos           (3UL)        /*!< VALID (Bit 3)                                         */
28757  #define R_USB_HS0_INTSTS0_VALID_Msk           (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
28758  #define R_USB_HS0_INTSTS0_CTSQ_Pos            (0UL)        /*!< CTSQ (Bit 0)                                          */
28759  #define R_USB_HS0_INTSTS0_CTSQ_Msk            (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
28760 /* ========================================================  INTSTS1  ======================================================== */
28761  #define R_USB_HS0_INTSTS1_OVRCR_Pos           (15UL)       /*!< OVRCR (Bit 15)                                        */
28762  #define R_USB_HS0_INTSTS1_OVRCR_Msk           (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
28763  #define R_USB_HS0_INTSTS1_BCHG_Pos            (14UL)       /*!< BCHG (Bit 14)                                         */
28764  #define R_USB_HS0_INTSTS1_BCHG_Msk            (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
28765  #define R_USB_HS0_INTSTS1_DTCH_Pos            (12UL)       /*!< DTCH (Bit 12)                                         */
28766  #define R_USB_HS0_INTSTS1_DTCH_Msk            (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
28767  #define R_USB_HS0_INTSTS1_ATTCH_Pos           (11UL)       /*!< ATTCH (Bit 11)                                        */
28768  #define R_USB_HS0_INTSTS1_ATTCH_Msk           (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
28769  #define R_USB_HS0_INTSTS1_L1RSMEND_Pos        (9UL)        /*!< L1RSMEND (Bit 9)                                      */
28770  #define R_USB_HS0_INTSTS1_L1RSMEND_Msk        (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
28771  #define R_USB_HS0_INTSTS1_LPMEND_Pos          (8UL)        /*!< LPMEND (Bit 8)                                        */
28772  #define R_USB_HS0_INTSTS1_LPMEND_Msk          (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
28773  #define R_USB_HS0_INTSTS1_EOFERR_Pos          (6UL)        /*!< EOFERR (Bit 6)                                        */
28774  #define R_USB_HS0_INTSTS1_EOFERR_Msk          (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
28775  #define R_USB_HS0_INTSTS1_SIGN_Pos            (5UL)        /*!< SIGN (Bit 5)                                          */
28776  #define R_USB_HS0_INTSTS1_SIGN_Msk            (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
28777  #define R_USB_HS0_INTSTS1_SACK_Pos            (4UL)        /*!< SACK (Bit 4)                                          */
28778  #define R_USB_HS0_INTSTS1_SACK_Msk            (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
28779  #define R_USB_HS0_INTSTS1_PDDETINT0_Pos       (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
28780  #define R_USB_HS0_INTSTS1_PDDETINT0_Msk       (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
28781 /* ========================================================  BRDYSTS  ======================================================== */
28782  #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos        (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
28783  #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk        (0x3ffUL)    /*!< PIPEBRDY (Bitfield-Mask: 0x3ff)                       */
28784 /* ========================================================  NRDYSTS  ======================================================== */
28785  #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos        (0UL)        /*!< PIPENRDY (Bit 0)                                      */
28786  #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk        (0x3ffUL)    /*!< PIPENRDY (Bitfield-Mask: 0x3ff)                       */
28787 /* ========================================================  BEMPSTS  ======================================================== */
28788  #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos        (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
28789  #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk        (0x3ffUL)    /*!< PIPEBEMP (Bitfield-Mask: 0x3ff)                       */
28790 /* ========================================================  FRMNUM  ========================================================= */
28791  #define R_USB_HS0_FRMNUM_OVRN_Pos             (15UL)       /*!< OVRN (Bit 15)                                         */
28792  #define R_USB_HS0_FRMNUM_OVRN_Msk             (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
28793  #define R_USB_HS0_FRMNUM_CRCE_Pos             (14UL)       /*!< CRCE (Bit 14)                                         */
28794  #define R_USB_HS0_FRMNUM_CRCE_Msk             (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
28795  #define R_USB_HS0_FRMNUM_FRNM_Pos             (0UL)        /*!< FRNM (Bit 0)                                          */
28796  #define R_USB_HS0_FRMNUM_FRNM_Msk             (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
28797 /* ========================================================  UFRMNUM  ======================================================== */
28798  #define R_USB_HS0_UFRMNUM_DVCHG_Pos           (15UL)       /*!< DVCHG (Bit 15)                                        */
28799  #define R_USB_HS0_UFRMNUM_DVCHG_Msk           (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
28800  #define R_USB_HS0_UFRMNUM_UFRNM_Pos           (0UL)        /*!< UFRNM (Bit 0)                                         */
28801  #define R_USB_HS0_UFRMNUM_UFRNM_Msk           (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
28802 /* ========================================================  USBADDR  ======================================================== */
28803  #define R_USB_HS0_USBADDR_STSRECOV0_Pos       (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
28804  #define R_USB_HS0_USBADDR_STSRECOV0_Msk       (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
28805 /* ========================================================  USBREQ  ========================================================= */
28806  #define R_USB_HS0_USBREQ_BREQUEST_Pos         (8UL)        /*!< BREQUEST (Bit 8)                                      */
28807  #define R_USB_HS0_USBREQ_BREQUEST_Msk         (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
28808  #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos    (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
28809  #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk    (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
28810 /* ========================================================  USBVAL  ========================================================= */
28811  #define R_USB_HS0_USBVAL_WVALUE_Pos           (0UL)        /*!< WVALUE (Bit 0)                                        */
28812  #define R_USB_HS0_USBVAL_WVALUE_Msk           (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
28813 /* ========================================================  USBINDX  ======================================================== */
28814  #define R_USB_HS0_USBINDX_WINDEX_Pos          (0UL)        /*!< WINDEX (Bit 0)                                        */
28815  #define R_USB_HS0_USBINDX_WINDEX_Msk          (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
28816 /* ========================================================  USBLENG  ======================================================== */
28817  #define R_USB_HS0_USBLENG_WLENGTH_Pos         (0UL)        /*!< WLENGTH (Bit 0)                                       */
28818  #define R_USB_HS0_USBLENG_WLENGTH_Msk         (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
28819 /* ========================================================  DCPCFG  ========================================================= */
28820  #define R_USB_HS0_DCPCFG_CNTMD_Pos            (8UL)        /*!< CNTMD (Bit 8)                                         */
28821  #define R_USB_HS0_DCPCFG_CNTMD_Msk            (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
28822  #define R_USB_HS0_DCPCFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
28823  #define R_USB_HS0_DCPCFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28824  #define R_USB_HS0_DCPCFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
28825  #define R_USB_HS0_DCPCFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28826 /* ========================================================  DCPMAXP  ======================================================== */
28827  #define R_USB_HS0_DCPMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
28828  #define R_USB_HS0_DCPMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28829  #define R_USB_HS0_DCPMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
28830  #define R_USB_HS0_DCPMAXP_MXPS_Msk            (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
28831 /* ========================================================  DCPCTR  ========================================================= */
28832  #define R_USB_HS0_DCPCTR_BSTS_Pos             (15UL)       /*!< BSTS (Bit 15)                                         */
28833  #define R_USB_HS0_DCPCTR_BSTS_Msk             (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28834  #define R_USB_HS0_DCPCTR_SUREQ_Pos            (14UL)       /*!< SUREQ (Bit 14)                                        */
28835  #define R_USB_HS0_DCPCTR_SUREQ_Msk            (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
28836  #define R_USB_HS0_DCPCTR_CSCLR_Pos            (13UL)       /*!< CSCLR (Bit 13)                                        */
28837  #define R_USB_HS0_DCPCTR_CSCLR_Msk            (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
28838  #define R_USB_HS0_DCPCTR_CSSTS_Pos            (12UL)       /*!< CSSTS (Bit 12)                                        */
28839  #define R_USB_HS0_DCPCTR_CSSTS_Msk            (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
28840  #define R_USB_HS0_DCPCTR_SUREQCLR_Pos         (11UL)       /*!< SUREQCLR (Bit 11)                                     */
28841  #define R_USB_HS0_DCPCTR_SUREQCLR_Msk         (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
28842  #define R_USB_HS0_DCPCTR_SQCLR_Pos            (8UL)        /*!< SQCLR (Bit 8)                                         */
28843  #define R_USB_HS0_DCPCTR_SQCLR_Msk            (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28844  #define R_USB_HS0_DCPCTR_SQSET_Pos            (7UL)        /*!< SQSET (Bit 7)                                         */
28845  #define R_USB_HS0_DCPCTR_SQSET_Msk            (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28846  #define R_USB_HS0_DCPCTR_SQMON_Pos            (6UL)        /*!< SQMON (Bit 6)                                         */
28847  #define R_USB_HS0_DCPCTR_SQMON_Msk            (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28848  #define R_USB_HS0_DCPCTR_PBUSY_Pos            (5UL)        /*!< PBUSY (Bit 5)                                         */
28849  #define R_USB_HS0_DCPCTR_PBUSY_Msk            (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28850  #define R_USB_HS0_DCPCTR_PINGE_Pos            (4UL)        /*!< PINGE (Bit 4)                                         */
28851  #define R_USB_HS0_DCPCTR_PINGE_Msk            (0x10UL)     /*!< PINGE (Bitfield-Mask: 0x01)                           */
28852  #define R_USB_HS0_DCPCTR_CCPL_Pos             (2UL)        /*!< CCPL (Bit 2)                                          */
28853  #define R_USB_HS0_DCPCTR_CCPL_Msk             (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
28854  #define R_USB_HS0_DCPCTR_PID_Pos              (0UL)        /*!< PID (Bit 0)                                           */
28855  #define R_USB_HS0_DCPCTR_PID_Msk              (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28856 /* ========================================================  PIPESEL  ======================================================== */
28857 /* ========================================================  PIPECFG  ======================================================== */
28858  #define R_USB_HS0_PIPECFG_TYPE_Pos            (14UL)       /*!< TYPE (Bit 14)                                         */
28859  #define R_USB_HS0_PIPECFG_TYPE_Msk            (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
28860  #define R_USB_HS0_PIPECFG_BFRE_Pos            (10UL)       /*!< BFRE (Bit 10)                                         */
28861  #define R_USB_HS0_PIPECFG_BFRE_Msk            (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
28862  #define R_USB_HS0_PIPECFG_DBLB_Pos            (9UL)        /*!< DBLB (Bit 9)                                          */
28863  #define R_USB_HS0_PIPECFG_DBLB_Msk            (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
28864  #define R_USB_HS0_PIPECFG_CNTMD_Pos           (8UL)        /*!< CNTMD (Bit 8)                                         */
28865  #define R_USB_HS0_PIPECFG_CNTMD_Msk           (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
28866  #define R_USB_HS0_PIPECFG_SHTNAK_Pos          (7UL)        /*!< SHTNAK (Bit 7)                                        */
28867  #define R_USB_HS0_PIPECFG_SHTNAK_Msk          (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28868  #define R_USB_HS0_PIPECFG_DIR_Pos             (4UL)        /*!< DIR (Bit 4)                                           */
28869  #define R_USB_HS0_PIPECFG_DIR_Msk             (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28870  #define R_USB_HS0_PIPECFG_EPNUM_Pos           (0UL)        /*!< EPNUM (Bit 0)                                         */
28871  #define R_USB_HS0_PIPECFG_EPNUM_Msk           (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
28872 /* ========================================================  PIPEBUF  ======================================================== */
28873  #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos         (10UL)       /*!< BUFSIZE (Bit 10)                                      */
28874  #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk         (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
28875  #define R_USB_HS0_PIPEBUF_BUFNMB_Pos          (0UL)        /*!< BUFNMB (Bit 0)                                        */
28876  #define R_USB_HS0_PIPEBUF_BUFNMB_Msk          (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
28877 /* =======================================================  PIPEMAXP  ======================================================== */
28878  #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos         (12UL)       /*!< DEVSEL (Bit 12)                                       */
28879  #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk         (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28880  #define R_USB_HS0_PIPEMAXP_MXPS_Pos           (0UL)        /*!< MXPS (Bit 0)                                          */
28881  #define R_USB_HS0_PIPEMAXP_MXPS_Msk           (0x7ffUL)    /*!< MXPS (Bitfield-Mask: 0x7ff)                           */
28882 /* =======================================================  PIPEPERI  ======================================================== */
28883  #define R_USB_HS0_PIPEPERI_IFIS_Pos           (12UL)       /*!< IFIS (Bit 12)                                         */
28884  #define R_USB_HS0_PIPEPERI_IFIS_Msk           (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
28885  #define R_USB_HS0_PIPEPERI_IITV_Pos           (0UL)        /*!< IITV (Bit 0)                                          */
28886  #define R_USB_HS0_PIPEPERI_IITV_Msk           (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
28887 /* =======================================================  PIPE_CTR  ======================================================== */
28888  #define R_USB_HS0_PIPE_CTR_BSTS_Pos           (15UL)       /*!< BSTS (Bit 15)                                         */
28889  #define R_USB_HS0_PIPE_CTR_BSTS_Msk           (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28890  #define R_USB_HS0_PIPE_CTR_INBUFM_Pos         (14UL)       /*!< INBUFM (Bit 14)                                       */
28891  #define R_USB_HS0_PIPE_CTR_INBUFM_Msk         (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
28892  #define R_USB_HS0_PIPE_CTR_CSCLR_Pos          (13UL)       /*!< CSCLR (Bit 13)                                        */
28893  #define R_USB_HS0_PIPE_CTR_CSCLR_Msk          (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
28894  #define R_USB_HS0_PIPE_CTR_CSSTS_Pos          (12UL)       /*!< CSSTS (Bit 12)                                        */
28895  #define R_USB_HS0_PIPE_CTR_CSSTS_Msk          (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
28896  #define R_USB_HS0_PIPE_CTR_ATREPM_Pos         (10UL)       /*!< ATREPM (Bit 10)                                       */
28897  #define R_USB_HS0_PIPE_CTR_ATREPM_Msk         (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
28898  #define R_USB_HS0_PIPE_CTR_ACLRM_Pos          (9UL)        /*!< ACLRM (Bit 9)                                         */
28899  #define R_USB_HS0_PIPE_CTR_ACLRM_Msk          (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
28900  #define R_USB_HS0_PIPE_CTR_SQCLR_Pos          (8UL)        /*!< SQCLR (Bit 8)                                         */
28901  #define R_USB_HS0_PIPE_CTR_SQCLR_Msk          (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28902  #define R_USB_HS0_PIPE_CTR_SQSET_Pos          (7UL)        /*!< SQSET (Bit 7)                                         */
28903  #define R_USB_HS0_PIPE_CTR_SQSET_Msk          (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28904  #define R_USB_HS0_PIPE_CTR_SQMON_Pos          (6UL)        /*!< SQMON (Bit 6)                                         */
28905  #define R_USB_HS0_PIPE_CTR_SQMON_Msk          (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28906  #define R_USB_HS0_PIPE_CTR_PBUSY_Pos          (5UL)        /*!< PBUSY (Bit 5)                                         */
28907  #define R_USB_HS0_PIPE_CTR_PBUSY_Msk          (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28908  #define R_USB_HS0_PIPE_CTR_PID_Pos            (0UL)        /*!< PID (Bit 0)                                           */
28909  #define R_USB_HS0_PIPE_CTR_PID_Msk            (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28910 /* ========================================================  DEVADD  ========================================================= */
28911  #define R_USB_HS0_DEVADD_UPPHUB_Pos           (11UL)       /*!< UPPHUB (Bit 11)                                       */
28912  #define R_USB_HS0_DEVADD_UPPHUB_Msk           (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
28913  #define R_USB_HS0_DEVADD_HUBPORT_Pos          (8UL)        /*!< HUBPORT (Bit 8)                                       */
28914  #define R_USB_HS0_DEVADD_HUBPORT_Msk          (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
28915  #define R_USB_HS0_DEVADD_USBSPD_Pos           (6UL)        /*!< USBSPD (Bit 6)                                        */
28916  #define R_USB_HS0_DEVADD_USBSPD_Msk           (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
28917 /* ========================================================  LPCTRL  ========================================================= */
28918  #define R_USB_HS0_LPCTRL_HWUPM_Pos            (7UL)        /*!< HWUPM (Bit 7)                                         */
28919  #define R_USB_HS0_LPCTRL_HWUPM_Msk            (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
28920 /* =========================================================  LPSTS  ========================================================= */
28921  #define R_USB_HS0_LPSTS_SUSPENDM_Pos          (14UL)       /*!< SUSPENDM (Bit 14)                                     */
28922  #define R_USB_HS0_LPSTS_SUSPENDM_Msk          (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
28923 /* ========================================================  BCCTRL  ========================================================= */
28924  #define R_USB_HS0_BCCTRL_PDDETSTS_Pos         (9UL)        /*!< PDDETSTS (Bit 9)                                      */
28925  #define R_USB_HS0_BCCTRL_PDDETSTS_Msk         (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
28926  #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos        (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
28927  #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk        (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
28928  #define R_USB_HS0_BCCTRL_DCPMODE_Pos          (5UL)        /*!< DCPMODE (Bit 5)                                       */
28929  #define R_USB_HS0_BCCTRL_DCPMODE_Msk          (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
28930  #define R_USB_HS0_BCCTRL_VDMSRCE_Pos          (4UL)        /*!< VDMSRCE (Bit 4)                                       */
28931  #define R_USB_HS0_BCCTRL_VDMSRCE_Msk          (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
28932  #define R_USB_HS0_BCCTRL_IDPSINKE_Pos         (3UL)        /*!< IDPSINKE (Bit 3)                                      */
28933  #define R_USB_HS0_BCCTRL_IDPSINKE_Msk         (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
28934  #define R_USB_HS0_BCCTRL_VDPSRCE_Pos          (2UL)        /*!< VDPSRCE (Bit 2)                                       */
28935  #define R_USB_HS0_BCCTRL_VDPSRCE_Msk          (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
28936  #define R_USB_HS0_BCCTRL_IDMSINKE_Pos         (1UL)        /*!< IDMSINKE (Bit 1)                                      */
28937  #define R_USB_HS0_BCCTRL_IDMSINKE_Msk         (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
28938  #define R_USB_HS0_BCCTRL_IDPSRCE_Pos          (0UL)        /*!< IDPSRCE (Bit 0)                                       */
28939  #define R_USB_HS0_BCCTRL_IDPSRCE_Msk          (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
28940 /* =======================================================  PL1CTRL1  ======================================================== */
28941  #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos        (14UL)       /*!< L1EXTMD (Bit 14)                                      */
28942  #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk        (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
28943  #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos        (8UL)        /*!< HIRDTHR (Bit 8)                                       */
28944  #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk        (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
28945  #define R_USB_HS0_PL1CTRL1_DVSQ_Pos           (4UL)        /*!< DVSQ (Bit 4)                                          */
28946  #define R_USB_HS0_PL1CTRL1_DVSQ_Msk           (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
28947  #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos       (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
28948  #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk       (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
28949  #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos       (1UL)        /*!< L1RESPMD (Bit 1)                                      */
28950  #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk       (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
28951  #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos       (0UL)        /*!< L1RESPEN (Bit 0)                                      */
28952  #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk       (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
28953 /* =======================================================  PL1CTRL2  ======================================================== */
28954  #define R_USB_HS0_PL1CTRL2_RWEMON_Pos         (12UL)       /*!< RWEMON (Bit 12)                                       */
28955  #define R_USB_HS0_PL1CTRL2_RWEMON_Msk         (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
28956  #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos        (8UL)        /*!< HIRDMON (Bit 8)                                       */
28957  #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk        (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
28958 /* =======================================================  HL1CTRL1  ======================================================== */
28959  #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos       (1UL)        /*!< L1STATUS (Bit 1)                                      */
28960  #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk       (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
28961  #define R_USB_HS0_HL1CTRL1_L1REQ_Pos          (0UL)        /*!< L1REQ (Bit 0)                                         */
28962  #define R_USB_HS0_HL1CTRL1_L1REQ_Msk          (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
28963 /* =======================================================  HL1CTRL2  ======================================================== */
28964  #define R_USB_HS0_HL1CTRL2_BESL_Pos           (15UL)       /*!< BESL (Bit 15)                                         */
28965  #define R_USB_HS0_HL1CTRL2_BESL_Msk           (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
28966  #define R_USB_HS0_HL1CTRL2_L1RWE_Pos          (12UL)       /*!< L1RWE (Bit 12)                                        */
28967  #define R_USB_HS0_HL1CTRL2_L1RWE_Msk          (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
28968  #define R_USB_HS0_HL1CTRL2_HIRD_Pos           (8UL)        /*!< HIRD (Bit 8)                                          */
28969  #define R_USB_HS0_HL1CTRL2_HIRD_Msk           (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
28970  #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos         (0UL)        /*!< L1ADDR (Bit 0)                                        */
28971  #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk         (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
28972 /* =======================================================  PHYTRIM1  ======================================================== */
28973  #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos      (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
28974  #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk      (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
28975  #define R_USB_HS0_PHYTRIM1_HSIUP_Pos          (8UL)        /*!< HSIUP (Bit 8)                                         */
28976  #define R_USB_HS0_PHYTRIM1_HSIUP_Msk          (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
28977  #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos       (7UL)        /*!< PCOMPENB (Bit 7)                                      */
28978  #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk       (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
28979  #define R_USB_HS0_PHYTRIM1_DFALL_Pos          (2UL)        /*!< DFALL (Bit 2)                                         */
28980  #define R_USB_HS0_PHYTRIM1_DFALL_Msk          (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
28981  #define R_USB_HS0_PHYTRIM1_DRISE_Pos          (0UL)        /*!< DRISE (Bit 0)                                         */
28982  #define R_USB_HS0_PHYTRIM1_DRISE_Msk          (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
28983 /* =======================================================  PHYTRIM2  ======================================================== */
28984  #define R_USB_HS0_PHYTRIM2_DIS_Pos            (12UL)       /*!< DIS (Bit 12)                                          */
28985  #define R_USB_HS0_PHYTRIM2_DIS_Msk            (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
28986  #define R_USB_HS0_PHYTRIM2_PDR_Pos            (8UL)        /*!< PDR (Bit 8)                                           */
28987  #define R_USB_HS0_PHYTRIM2_PDR_Msk            (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
28988  #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos       (7UL)        /*!< HSRXENMO (Bit 7)                                      */
28989  #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk       (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
28990  #define R_USB_HS0_PHYTRIM2_SQU_Pos            (0UL)        /*!< SQU (Bit 0)                                           */
28991  #define R_USB_HS0_PHYTRIM2_SQU_Msk            (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
28992 /* ========================================================  DPUSR0R  ======================================================== */
28993  #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos        (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
28994  #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk        (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
28995  #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos         (21UL)       /*!< DOVCBHM (Bit 21)                                      */
28996  #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk         (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
28997  #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos         (20UL)       /*!< DOVCAHM (Bit 20)                                      */
28998  #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk         (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
28999 /* ========================================================  DPUSR1R  ======================================================== */
29000  #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos         (23UL)       /*!< DVBSTSH (Bit 23)                                      */
29001  #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk         (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
29002  #define R_USB_HS0_DPUSR1R_DOVCBH_Pos          (21UL)       /*!< DOVCBH (Bit 21)                                       */
29003  #define R_USB_HS0_DPUSR1R_DOVCBH_Msk          (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
29004  #define R_USB_HS0_DPUSR1R_DOVCAH_Pos          (20UL)       /*!< DOVCAH (Bit 20)                                       */
29005  #define R_USB_HS0_DPUSR1R_DOVCAH_Msk          (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
29006  #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos        (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
29007  #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk        (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
29008  #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos         (5UL)        /*!< DOVCBHE (Bit 5)                                       */
29009  #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk         (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
29010  #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos         (4UL)        /*!< DOVCAHE (Bit 4)                                       */
29011  #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk         (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
29012 /* ========================================================  DPUSR2R  ======================================================== */
29013  #define R_USB_HS0_DPUSR2R_DMINTE_Pos          (9UL)        /*!< DMINTE (Bit 9)                                        */
29014  #define R_USB_HS0_DPUSR2R_DMINTE_Msk          (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
29015  #define R_USB_HS0_DPUSR2R_DPINTE_Pos          (8UL)        /*!< DPINTE (Bit 8)                                        */
29016  #define R_USB_HS0_DPUSR2R_DPINTE_Msk          (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
29017  #define R_USB_HS0_DPUSR2R_DMVAL_Pos           (5UL)        /*!< DMVAL (Bit 5)                                         */
29018  #define R_USB_HS0_DPUSR2R_DMVAL_Msk           (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
29019  #define R_USB_HS0_DPUSR2R_DPVAL_Pos           (4UL)        /*!< DPVAL (Bit 4)                                         */
29020  #define R_USB_HS0_DPUSR2R_DPVAL_Msk           (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
29021  #define R_USB_HS0_DPUSR2R_DMINT_Pos           (1UL)        /*!< DMINT (Bit 1)                                         */
29022  #define R_USB_HS0_DPUSR2R_DMINT_Msk           (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
29023  #define R_USB_HS0_DPUSR2R_DPINT_Pos           (0UL)        /*!< DPINT (Bit 0)                                         */
29024  #define R_USB_HS0_DPUSR2R_DPINT_Msk           (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
29025 /* ========================================================  DPUSRCR  ======================================================== */
29026  #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos        (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
29027  #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk        (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
29028  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
29029  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
29030 
29031 /* =========================================================================================================================== */
29032 /* ================                                          R_AGTX0                                          ================ */
29033 /* =========================================================================================================================== */
29034 
29035 /** @} */ /* End of group PosMask_peripherals */
29036 
29037  #ifdef __cplusplus
29038 }
29039  #endif
29040 
29041 #endif                                 /* R7FA6M3AH_H */
29042 
29043 /** @} */ /* End of group R7FA6M3AH */
29044 
29045 /** @} */ /* End of group Renesas */
29046