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Searched refs:SD_CLK_CTRL (Results 1 – 12 of 12) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/r_sdhi/
Dr_sdhi.c1400 p_ctrl->p_reg->SD_CLK_CTRL |= SDHI_PRV_SDHI_PRV_SD_CLK_AUTO_CLOCK_ENABLE_MASK; in r_sdhi_command_send_no_wait()
1474 … uint32_t clkctrlen = p_ctrl->p_reg->SD_CLK_CTRL & SDHI_PRV_SDHI_PRV_SD_CLK_CTRL_CLKCTRLEN_MASK; in r_sdhi_max_clock_rate_set()
1475 … p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | SDHI_PRV_SDHI_PRV_SD_CLK_CTRL_CLKEN_MASK; in r_sdhi_max_clock_rate_set()
1508 p_ctrl->p_reg->SD_CLK_CTRL = SDHI_PRV_SD_CLK_CTRL_DEFAULT; // Automatic clock control disabled. in r_sdhi_hw_cfg()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA4M2AD.h10104 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA4M3AF.h10104 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA6E10F.h10533 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA6M1AD.h10181 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA6M4AF.h10867 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA6M2AF.h12162 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA6M3AH.h14820 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA6M5BH.h13129 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA8T1AH.h12656 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA8M1AH.h12691 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member
DR7FA8D1BH.h14280 …__IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register … member