1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef R_USB_DEVICE_DEFINE_H 7 #define R_USB_DEVICE_DEFINE_H 8 9 #include "r_usb_device.h" 10 11 #define USB_NOT_SUPPORT (-1) 12 #define USB_FS_MODULE (0U) 13 #define USB_HS_MODULE (1U) 14 15 /********************************************************************************************************************** 16 * Macro definitions 17 **********************************************************************************************************************/ 18 #if BSP_FEATURE_USB_HAS_USBHS == 1U 19 20 #define USB_HIGH_SPEED_MODULE 21 #define USB_IP0_MODULE USB_FS_MODULE 22 #define USB_IP1_MODULE USB_HS_MODULE 23 #define USB_NUM_USBIP BSP_FEATURE_USB_NUM_IP 24 25 #define USB_IS_USBHS(usbip) ((usbip) == USB_HS_MODULE) 26 27 #else 28 29 #define USB_IP0_MODULE USB_FS_MODULE 30 #define USB_IP1_MODULE USB_NOT_SUPPORT 31 #define USB_NUM_USBIP BSP_FEATURE_USB_NUM_IP 32 33 #endif 34 35 /* USBFS & USBHS Register definition */ 36 37 /* PIPE_TR E */ 38 #define R_USB_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */ 39 #define R_USB_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */ 40 #define R_USB_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */ 41 #define R_USB_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */ 42 43 /* PIPE_TR N */ 44 #define R_USB_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */ 45 #define R_USB_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */ 46 47 /* SYSCFG */ 48 #define R_USB_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */ 49 #define R_USB_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */ 50 #define R_USB_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */ 51 #define R_USB_SYSCFG_CNEN_Msk (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */ 52 #define R_USB_SYSCFG_HSE_Pos (7UL) /* HSE (Bit 7) */ 53 #define R_USB_SYSCFG_HSE_Msk (0x80UL) /* HSE (Bitfield-Mask: 0x01) */ 54 #define R_USB_SYSCFG_DCFM_Pos (6UL) /* DCFM (Bit 6) */ 55 #define R_USB_SYSCFG_DCFM_Msk (0x40UL) /* DCFM (Bitfield-Mask: 0x01) */ 56 #define R_USB_SYSCFG_DRPD_Pos (5UL) /* DRPD (Bit 5) */ 57 #define R_USB_SYSCFG_DRPD_Msk (0x20UL) /* DRPD (Bitfield-Mask: 0x01) */ 58 #define R_USB_SYSCFG_DPRPU_Pos (4UL) /* DPRPU (Bit 4) */ 59 #define R_USB_SYSCFG_DPRPU_Msk (0x10UL) /* DPRPU (Bitfield-Mask: 0x01) */ 60 #define R_USB_SYSCFG_DMRPU_Pos (3UL) /* DMRPU (Bit 3) */ 61 #define R_USB_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */ 62 #define R_USB_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */ 63 #define R_USB_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */ 64 65 /* BUSWAIT */ 66 #define R_USB_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */ 67 #define R_USB_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */ 68 69 /* SYSSTS0 */ 70 #define R_USB_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */ 71 #define R_USB_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */ 72 #define R_USB_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */ 73 #define R_USB_SYSSTS0_HTACT_Msk (0x40UL) /* HTACT (Bitfield-Mask: 0x01) */ 74 #define R_USB_SYSSTS0_SOFEA_Pos (5UL) /* SOFEA (Bit 5) */ 75 #define R_USB_SYSSTS0_SOFEA_Msk (0x20UL) /* SOFEA (Bitfield-Mask: 0x01) */ 76 #define R_USB_SYSSTS0_IDMON_Pos (2UL) /* IDMON (Bit 2) */ 77 #define R_USB_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */ 78 #define R_USB_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */ 79 #define R_USB_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */ 80 81 /* PLLSTA */ 82 #define R_USB_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */ 83 #define R_USB_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */ 84 85 /* DVSTCTR0 */ 86 #define R_USB_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */ 87 #define R_USB_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */ 88 #define R_USB_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */ 89 #define R_USB_DVSTCTR0_EXICEN_Msk (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */ 90 #define R_USB_DVSTCTR0_VBUSEN_Pos (9UL) /* VBUSEN (Bit 9) */ 91 #define R_USB_DVSTCTR0_VBUSEN_Msk (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */ 92 #define R_USB_DVSTCTR0_WKUP_Pos (8UL) /* WKUP (Bit 8) */ 93 #define R_USB_DVSTCTR0_WKUP_Msk (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */ 94 #define R_USB_DVSTCTR0_RWUPE_Pos (7UL) /* RWUPE (Bit 7) */ 95 #define R_USB_DVSTCTR0_RWUPE_Msk (0x80UL) /* RWUPE (Bitfield-Mask: 0x01) */ 96 #define R_USB_DVSTCTR0_USBRST_Pos (6UL) /* USBRST (Bit 6) */ 97 #define R_USB_DVSTCTR0_USBRST_Msk (0x40UL) /* USBRST (Bitfield-Mask: 0x01) */ 98 #define R_USB_DVSTCTR0_RESUME_Pos (5UL) /* RESUME (Bit 5) */ 99 #define R_USB_DVSTCTR0_RESUME_Msk (0x20UL) /* RESUME (Bitfield-Mask: 0x01) */ 100 #define R_USB_DVSTCTR0_UACT_Pos (4UL) /* UACT (Bit 4) */ 101 #define R_USB_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */ 102 #define R_USB_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */ 103 #define R_USB_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */ 104 105 /* TESTMODE */ 106 #define R_USB_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */ 107 #define R_USB_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */ 108 109 /* CFIFOSEL */ 110 #define R_USB_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ 111 #define R_USB_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ 112 #define R_USB_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ 113 #define R_USB_CFIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ 114 #define R_USB_CFIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ 115 #define R_USB_CFIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ 116 #define R_USB_CFIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ 117 #define R_USB_CFIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ 118 #define R_USB_CFIFOSEL_ISEL_Pos (5UL) /* ISEL (Bit 5) */ 119 #define R_USB_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */ 120 #define R_USB_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ 121 #define R_USB_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ 122 123 /* CFIFOCTR */ 124 #define R_USB_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ 125 #define R_USB_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ 126 #define R_USB_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ 127 #define R_USB_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ 128 #define R_USB_CFIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ 129 #define R_USB_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ 130 #define R_USB_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ 131 #define R_USB_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ 132 133 /* D0FIFOSEL */ 134 #define R_USB_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ 135 #define R_USB_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ 136 #define R_USB_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ 137 #define R_USB_D0FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ 138 #define R_USB_D0FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ 139 #define R_USB_D0FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ 140 #define R_USB_D0FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ 141 #define R_USB_D0FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ 142 #define R_USB_D0FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ 143 #define R_USB_D0FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ 144 #define R_USB_D0FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ 145 #define R_USB_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ 146 #define R_USB_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ 147 #define R_USB_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ 148 149 /* D0FIFOCTR */ 150 #define R_USB_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ 151 #define R_USB_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ 152 #define R_USB_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ 153 #define R_USB_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ 154 #define R_USB_D0FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ 155 #define R_USB_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ 156 #define R_USB_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ 157 #define R_USB_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ 158 159 /* D1FIFOSEL */ 160 #define R_USB_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */ 161 #define R_USB_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */ 162 #define R_USB_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */ 163 #define R_USB_D1FIFOSEL_REW_Msk (0x4000UL) /* REW (Bitfield-Mask: 0x01) */ 164 #define R_USB_D1FIFOSEL_DCLRM_Pos (13UL) /* DCLRM (Bit 13) */ 165 #define R_USB_D1FIFOSEL_DCLRM_Msk (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */ 166 #define R_USB_D1FIFOSEL_DREQE_Pos (12UL) /* DREQE (Bit 12) */ 167 #define R_USB_D1FIFOSEL_DREQE_Msk (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */ 168 #define R_USB_D1FIFOSEL_MBW_Pos (10UL) /* MBW (Bit 10) */ 169 #define R_USB_D1FIFOSEL_MBW_Msk (0xc00UL) /* MBW (Bitfield-Mask: 0x03) */ 170 #define R_USB_D1FIFOSEL_BIGEND_Pos (8UL) /* BIGEND (Bit 8) */ 171 #define R_USB_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */ 172 #define R_USB_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */ 173 #define R_USB_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */ 174 175 /* D1FIFOCTR */ 176 #define R_USB_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */ 177 #define R_USB_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */ 178 #define R_USB_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */ 179 #define R_USB_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */ 180 #define R_USB_D1FIFOCTR_FRDY_Pos (13UL) /* FRDY (Bit 13) */ 181 #define R_USB_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */ 182 #define R_USB_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */ 183 #define R_USB_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */ 184 185 /* INTENB0 */ 186 #define R_USB_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */ 187 #define R_USB_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */ 188 #define R_USB_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */ 189 #define R_USB_INTENB0_RSME_Msk (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */ 190 #define R_USB_INTENB0_SOFE_Pos (13UL) /* SOFE (Bit 13) */ 191 #define R_USB_INTENB0_SOFE_Msk (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */ 192 #define R_USB_INTENB0_DVSE_Pos (12UL) /* DVSE (Bit 12) */ 193 #define R_USB_INTENB0_DVSE_Msk (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */ 194 #define R_USB_INTENB0_CTRE_Pos (11UL) /* CTRE (Bit 11) */ 195 #define R_USB_INTENB0_CTRE_Msk (0x800UL) /* CTRE (Bitfield-Mask: 0x01) */ 196 #define R_USB_INTENB0_BEMPE_Pos (10UL) /* BEMPE (Bit 10) */ 197 #define R_USB_INTENB0_BEMPE_Msk (0x400UL) /* BEMPE (Bitfield-Mask: 0x01) */ 198 #define R_USB_INTENB0_NRDYE_Pos (9UL) /* NRDYE (Bit 9) */ 199 #define R_USB_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */ 200 #define R_USB_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */ 201 #define R_USB_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */ 202 203 /* INTENB1 */ 204 #define R_USB_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */ 205 #define R_USB_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */ 206 #define R_USB_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */ 207 #define R_USB_INTENB1_BCHGE_Msk (0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */ 208 #define R_USB_INTENB1_DTCHE_Pos (12UL) /* DTCHE (Bit 12) */ 209 #define R_USB_INTENB1_DTCHE_Msk (0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */ 210 #define R_USB_INTENB1_ATTCHE_Pos (11UL) /* ATTCHE (Bit 11) */ 211 #define R_USB_INTENB1_ATTCHE_Msk (0x800UL) /* ATTCHE (Bitfield-Mask: 0x01) */ 212 #define R_USB_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ 213 #define R_USB_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ 214 #define R_USB_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ 215 #define R_USB_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ 216 #define R_USB_INTENB1_EOFERRE_Pos (6UL) /* EOFERRE (Bit 6) */ 217 #define R_USB_INTENB1_EOFERRE_Msk (0x40UL) /* EOFERRE (Bitfield-Mask: 0x01) */ 218 #define R_USB_INTENB1_SIGNE_Pos (5UL) /* SIGNE (Bit 5) */ 219 #define R_USB_INTENB1_SIGNE_Msk (0x20UL) /* SIGNE (Bitfield-Mask: 0x01) */ 220 #define R_USB_INTENB1_SACKE_Pos (4UL) /* SACKE (Bit 4) */ 221 #define R_USB_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */ 222 #define R_USB_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */ 223 #define R_USB_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */ 224 225 /* BRDYENB */ 226 #define R_USB_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */ 227 #define R_USB_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */ 228 229 /* NRDYENB */ 230 #define R_USB_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */ 231 #define R_USB_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */ 232 233 /* BEMPENB */ 234 #define R_USB_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */ 235 #define R_USB_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */ 236 237 /* SOFCFG */ 238 #define R_USB_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */ 239 #define R_USB_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */ 240 #define R_USB_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */ 241 #define R_USB_SOFCFG_BRDYM_Msk (0x40UL) /* BRDYM (Bitfield-Mask: 0x01) */ 242 #define R_USB_SOFCFG_INTL_Pos (5UL) /* INTL (Bit 5) */ 243 #define R_USB_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */ 244 #define R_USB_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */ 245 #define R_USB_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */ 246 247 /* PHYSET */ 248 #define R_USB_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */ 249 #define R_USB_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */ 250 #define R_USB_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */ 251 #define R_USB_PHYSET_REPSTART_Msk (0x800UL) /* REPSTART (Bitfield-Mask: 0x01) */ 252 #define R_USB_PHYSET_REPSEL_Pos (8UL) /* REPSEL (Bit 8) */ 253 #define R_USB_PHYSET_REPSEL_Msk (0x300UL) /* REPSEL (Bitfield-Mask: 0x03) */ 254 #define R_USB_PHYSET_CLKSEL_Pos (4UL) /* CLKSEL (Bit 4) */ 255 #define R_USB_PHYSET_CLKSEL_Msk (0x30UL) /* CLKSEL (Bitfield-Mask: 0x03) */ 256 #define R_USB_PHYSET_CDPEN_Pos (3UL) /* CDPEN (Bit 3) */ 257 #define R_USB_PHYSET_CDPEN_Msk (0x8UL) /* CDPEN (Bitfield-Mask: 0x01) */ 258 #define R_USB_PHYSET_PLLRESET_Pos (1UL) /* PLLRESET (Bit 1) */ 259 #define R_USB_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */ 260 #define R_USB_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */ 261 #define R_USB_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */ 262 263 /* INTSTS0 */ 264 #define R_USB_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */ 265 #define R_USB_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */ 266 #define R_USB_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */ 267 #define R_USB_INTSTS0_RESM_Msk (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */ 268 #define R_USB_INTSTS0_SOFR_Pos (13UL) /* SOFR (Bit 13) */ 269 #define R_USB_INTSTS0_SOFR_Msk (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */ 270 #define R_USB_INTSTS0_DVST_Pos (12UL) /* DVST (Bit 12) */ 271 #define R_USB_INTSTS0_DVST_Msk (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */ 272 #define R_USB_INTSTS0_CTRT_Pos (11UL) /* CTRT (Bit 11) */ 273 #define R_USB_INTSTS0_CTRT_Msk (0x800UL) /* CTRT (Bitfield-Mask: 0x01) */ 274 #define R_USB_INTSTS0_BEMP_Pos (10UL) /* BEMP (Bit 10) */ 275 #define R_USB_INTSTS0_BEMP_Msk (0x400UL) /* BEMP (Bitfield-Mask: 0x01) */ 276 #define R_USB_INTSTS0_NRDY_Pos (9UL) /* NRDY (Bit 9) */ 277 #define R_USB_INTSTS0_NRDY_Msk (0x200UL) /* NRDY (Bitfield-Mask: 0x01) */ 278 #define R_USB_INTSTS0_BRDY_Pos (8UL) /* BRDY (Bit 8) */ 279 #define R_USB_INTSTS0_BRDY_Msk (0x100UL) /* BRDY (Bitfield-Mask: 0x01) */ 280 #define R_USB_INTSTS0_VBSTS_Pos (7UL) /* VBSTS (Bit 7) */ 281 #define R_USB_INTSTS0_VBSTS_Msk (0x80UL) /* VBSTS (Bitfield-Mask: 0x01) */ 282 #define R_USB_INTSTS0_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ 283 #define R_USB_INTSTS0_DVSQ_Msk (0x70UL) /* DVSQ (Bitfield-Mask: 0x07) */ 284 #define R_USB_INTSTS0_VALID_Pos (3UL) /* VALID (Bit 3) */ 285 #define R_USB_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */ 286 #define R_USB_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */ 287 #define R_USB_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */ 288 289 /* INTSTS1 */ 290 #define R_USB_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */ 291 #define R_USB_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */ 292 #define R_USB_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */ 293 #define R_USB_INTSTS1_BCHG_Msk (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */ 294 #define R_USB_INTSTS1_DTCH_Pos (12UL) /* DTCH (Bit 12) */ 295 #define R_USB_INTSTS1_DTCH_Msk (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */ 296 #define R_USB_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */ 297 #define R_USB_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */ 298 #define R_USB_INTSTS1_L1RSMEND_Pos (9UL) /* L1RSMEND (Bit 9) */ 299 #define R_USB_INTSTS1_L1RSMEND_Msk (0x200UL) /* L1RSMEND (Bitfield-Mask: 0x01) */ 300 #define R_USB_INTSTS1_LPMEND_Pos (8UL) /* LPMEND (Bit 8) */ 301 #define R_USB_INTSTS1_LPMEND_Msk (0x100UL) /* LPMEND (Bitfield-Mask: 0x01) */ 302 #define R_USB_INTSTS1_EOFERR_Pos (6UL) /* EOFERR (Bit 6) */ 303 #define R_USB_INTSTS1_EOFERR_Msk (0x40UL) /* EOFERR (Bitfield-Mask: 0x01) */ 304 #define R_USB_INTSTS1_SIGN_Pos (5UL) /* SIGN (Bit 5) */ 305 #define R_USB_INTSTS1_SIGN_Msk (0x20UL) /* SIGN (Bitfield-Mask: 0x01) */ 306 #define R_USB_INTSTS1_SACK_Pos (4UL) /* SACK (Bit 4) */ 307 #define R_USB_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */ 308 #define R_USB_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */ 309 #define R_USB_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */ 310 311 /* BRDYSTS */ 312 #define R_USB_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */ 313 #define R_USB_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /* PIPEBRDY (Bitfield-Mask: 0x01) */ 314 315 /* NRDYSTS */ 316 #define R_USB_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */ 317 #define R_USB_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */ 318 319 /* BEMPSTS */ 320 #define R_USB_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */ 321 #define R_USB_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */ 322 323 /* FRMNUM */ 324 #define R_USB_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */ 325 #define R_USB_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */ 326 #define R_USB_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */ 327 #define R_USB_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */ 328 #define R_USB_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */ 329 #define R_USB_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */ 330 331 /* UFRMNUM */ 332 #define R_USB_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */ 333 #define R_USB_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */ 334 #define R_USB_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */ 335 #define R_USB_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */ 336 337 /* USBADDR */ 338 #define R_USB_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */ 339 #define R_USB_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */ 340 #define R_USB_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */ 341 #define R_USB_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */ 342 343 /* USBREQ */ 344 #define R_USB_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */ 345 #define R_USB_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */ 346 #define R_USB_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */ 347 #define R_USB_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */ 348 349 /* USBVAL */ 350 #define R_USB_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */ 351 #define R_USB_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */ 352 353 /* USBINDX */ 354 #define R_USB_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */ 355 #define R_USB_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */ 356 357 /* USBLENG */ 358 #define R_USB_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */ 359 #define R_USB_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */ 360 361 /* DCPCFG */ 362 #define R_USB_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */ 363 #define R_USB_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */ 364 #define R_USB_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ 365 #define R_USB_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ 366 #define R_USB_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */ 367 #define R_USB_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ 368 369 /* DCPMAXP */ 370 #define R_USB_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ 371 #define R_USB_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ 372 #define R_USB_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ 373 #define R_USB_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */ 374 375 /* DCPCTR */ 376 #define R_USB_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ 377 #define R_USB_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ 378 #define R_USB_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */ 379 #define R_USB_DCPCTR_SUREQ_Msk (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */ 380 #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ 381 #define R_USB_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ 382 #define R_USB_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ 383 #define R_USB_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ 384 #define R_USB_DCPCTR_SUREQCLR_Pos (11UL) /* SUREQCLR (Bit 11) */ 385 #define R_USB_DCPCTR_SUREQCLR_Msk (0x800UL) /* SUREQCLR (Bitfield-Mask: 0x01) */ 386 #define R_USB_DCPCTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ 387 #define R_USB_DCPCTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ 388 #define R_USB_DCPCTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ 389 #define R_USB_DCPCTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ 390 #define R_USB_DCPCTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ 391 #define R_USB_DCPCTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ 392 #define R_USB_DCPCTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ 393 #define R_USB_DCPCTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ 394 #define R_USB_DCPCTR_CCPL_Pos (2UL) /* CCPL (Bit 2) */ 395 #define R_USB_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */ 396 #define R_USB_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */ 397 #define R_USB_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ 398 399 /* PIPESEL */ 400 #define R_USB_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */ 401 #define R_USB_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */ 402 403 /* PIPECFG */ 404 #define R_USB_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */ 405 #define R_USB_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */ 406 #define R_USB_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */ 407 #define R_USB_PIPECFG_BFRE_Msk (0x400UL) /* BFRE (Bitfield-Mask: 0x01) */ 408 #define R_USB_PIPECFG_DBLB_Pos (9UL) /* DBLB (Bit 9) */ 409 #define R_USB_PIPECFG_DBLB_Msk (0x200UL) /* DBLB (Bitfield-Mask: 0x01) */ 410 #define R_USB_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ 411 #define R_USB_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ 412 #define R_USB_PIPECFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */ 413 #define R_USB_PIPECFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */ 414 #define R_USB_PIPECFG_DIR_Pos (4UL) /* DIR (Bit 4) */ 415 #define R_USB_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */ 416 #define R_USB_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */ 417 #define R_USB_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */ 418 419 /* PIPEBUF */ 420 #define R_USB_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ 421 #define R_USB_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ 422 #define R_USB_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ 423 #define R_USB_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ 424 425 /* PIPEMAXP */ 426 #define R_USB_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */ 427 #define R_USB_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */ 428 #define R_USB_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */ 429 #define R_USB_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */ 430 431 /* PIPEPERI */ 432 #define R_USB_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */ 433 #define R_USB_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */ 434 #define R_USB_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */ 435 #define R_USB_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */ 436 437 /* PIPE_CTR */ 438 #define R_USB_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */ 439 #define R_USB_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */ 440 #define R_USB_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */ 441 #define R_USB_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */ 442 #define R_USB_PIPE_CTR_CSCLR_Pos (13UL) /* CSCLR (Bit 13) */ 443 #define R_USB_PIPE_CTR_CSCLR_Msk (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */ 444 #define R_USB_PIPE_CTR_CSSTS_Pos (12UL) /* CSSTS (Bit 12) */ 445 #define R_USB_PIPE_CTR_CSSTS_Msk (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */ 446 #define R_USB_PIPE_CTR_ATREPM_Pos (10UL) /* ATREPM (Bit 10) */ 447 #define R_USB_PIPE_CTR_ATREPM_Msk (0x400UL) /* ATREPM (Bitfield-Mask: 0x01) */ 448 #define R_USB_PIPE_CTR_ACLRM_Pos (9UL) /* ACLRM (Bit 9) */ 449 #define R_USB_PIPE_CTR_ACLRM_Msk (0x200UL) /* ACLRM (Bitfield-Mask: 0x01) */ 450 #define R_USB_PIPE_CTR_SQCLR_Pos (8UL) /* SQCLR (Bit 8) */ 451 #define R_USB_PIPE_CTR_SQCLR_Msk (0x100UL) /* SQCLR (Bitfield-Mask: 0x01) */ 452 #define R_USB_PIPE_CTR_SQSET_Pos (7UL) /* SQSET (Bit 7) */ 453 #define R_USB_PIPE_CTR_SQSET_Msk (0x80UL) /* SQSET (Bitfield-Mask: 0x01) */ 454 #define R_USB_PIPE_CTR_SQMON_Pos (6UL) /* SQMON (Bit 6) */ 455 #define R_USB_PIPE_CTR_SQMON_Msk (0x40UL) /* SQMON (Bitfield-Mask: 0x01) */ 456 #define R_USB_PIPE_CTR_PBUSY_Pos (5UL) /* PBUSY (Bit 5) */ 457 #define R_USB_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */ 458 #define R_USB_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */ 459 #define R_USB_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */ 460 461 /* DEVADD */ 462 #define R_USB_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */ 463 #define R_USB_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */ 464 #define R_USB_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */ 465 #define R_USB_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */ 466 #define R_USB_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */ 467 #define R_USB_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */ 468 469 /* USBBCCTRL0 */ 470 #define R_USB_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */ 471 #define R_USB_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */ 472 #define R_USB_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */ 473 #define R_USB_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */ 474 #define R_USB_USBBCCTRL0_BATCHGE0_Pos (7UL) /* BATCHGE0 (Bit 7) */ 475 #define R_USB_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /* BATCHGE0 (Bitfield-Mask: 0x01) */ 476 #define R_USB_USBBCCTRL0_VDMSRCE0_Pos (5UL) /* VDMSRCE0 (Bit 5) */ 477 #define R_USB_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /* VDMSRCE0 (Bitfield-Mask: 0x01) */ 478 #define R_USB_USBBCCTRL0_IDPSINKE0_Pos (4UL) /* IDPSINKE0 (Bit 4) */ 479 #define R_USB_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /* IDPSINKE0 (Bitfield-Mask: 0x01) */ 480 #define R_USB_USBBCCTRL0_VDPSRCE0_Pos (3UL) /* VDPSRCE0 (Bit 3) */ 481 #define R_USB_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /* VDPSRCE0 (Bitfield-Mask: 0x01) */ 482 #define R_USB_USBBCCTRL0_IDMSINKE0_Pos (2UL) /* IDMSINKE0 (Bit 2) */ 483 #define R_USB_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /* IDMSINKE0 (Bitfield-Mask: 0x01) */ 484 #define R_USB_USBBCCTRL0_IDPSRCE0_Pos (1UL) /* IDPSRCE0 (Bit 1) */ 485 #define R_USB_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */ 486 #define R_USB_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */ 487 #define R_USB_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */ 488 489 /* UCKSEL */ 490 #define R_USB_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */ 491 #define R_USB_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */ 492 493 /* USBMC */ 494 #define R_USB_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */ 495 #define R_USB_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */ 496 #define R_USB_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */ 497 #define R_USB_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */ 498 499 /* PHYSLEW */ 500 #define R_USB_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */ 501 #define R_USB_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */ 502 #define R_USB_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */ 503 #define R_USB_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */ 504 #define R_USB_PHYSLEW_SLEWR01_Pos (1UL) /* SLEWR01 (Bit 1) */ 505 #define R_USB_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */ 506 #define R_USB_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */ 507 #define R_USB_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */ 508 509 /* LPCTRL */ 510 #define R_USB_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */ 511 #define R_USB_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */ 512 513 /* LPSTS */ 514 #define R_USB_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */ 515 #define R_USB_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */ 516 517 /* BCCTRL */ 518 #define R_USB_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */ 519 #define R_USB_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */ 520 #define R_USB_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */ 521 #define R_USB_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */ 522 #define R_USB_BCCTRL_DCPMODE_Pos (5UL) /* DCPMODE (Bit 5) */ 523 #define R_USB_BCCTRL_DCPMODE_Msk (0x20UL) /* DCPMODE (Bitfield-Mask: 0x01) */ 524 #define R_USB_BCCTRL_VDMSRCE_Pos (4UL) /* VDMSRCE (Bit 4) */ 525 #define R_USB_BCCTRL_VDMSRCE_Msk (0x10UL) /* VDMSRCE (Bitfield-Mask: 0x01) */ 526 #define R_USB_BCCTRL_IDPSINKE_Pos (3UL) /* IDPSINKE (Bit 3) */ 527 #define R_USB_BCCTRL_IDPSINKE_Msk (0x8UL) /* IDPSINKE (Bitfield-Mask: 0x01) */ 528 #define R_USB_BCCTRL_VDPSRCE_Pos (2UL) /* VDPSRCE (Bit 2) */ 529 #define R_USB_BCCTRL_VDPSRCE_Msk (0x4UL) /* VDPSRCE (Bitfield-Mask: 0x01) */ 530 #define R_USB_BCCTRL_IDMSINKE_Pos (1UL) /* IDMSINKE (Bit 1) */ 531 #define R_USB_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */ 532 #define R_USB_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */ 533 #define R_USB_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */ 534 535 /* PL1CTRL1 */ 536 #define R_USB_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */ 537 #define R_USB_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */ 538 #define R_USB_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */ 539 #define R_USB_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /* HIRDTHR (Bitfield-Mask: 0x0f) */ 540 #define R_USB_PL1CTRL1_DVSQ_Pos (4UL) /* DVSQ (Bit 4) */ 541 #define R_USB_PL1CTRL1_DVSQ_Msk (0xf0UL) /* DVSQ (Bitfield-Mask: 0x0f) */ 542 #define R_USB_PL1CTRL1_L1NEGOMD_Pos (3UL) /* L1NEGOMD (Bit 3) */ 543 #define R_USB_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /* L1NEGOMD (Bitfield-Mask: 0x01) */ 544 #define R_USB_PL1CTRL1_L1RESPMD_Pos (1UL) /* L1RESPMD (Bit 1) */ 545 #define R_USB_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */ 546 #define R_USB_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */ 547 #define R_USB_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */ 548 549 /* PL1CTRL2 */ 550 #define R_USB_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */ 551 #define R_USB_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */ 552 #define R_USB_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */ 553 #define R_USB_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */ 554 555 /* HL1CTRL1 */ 556 #define R_USB_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */ 557 #define R_USB_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */ 558 #define R_USB_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */ 559 #define R_USB_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */ 560 561 /* HL1CTRL2 */ 562 #define R_USB_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */ 563 #define R_USB_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */ 564 #define R_USB_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */ 565 #define R_USB_HL1CTRL2_L1RWE_Msk (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */ 566 #define R_USB_HL1CTRL2_HIRD_Pos (8UL) /* HIRD (Bit 8) */ 567 #define R_USB_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */ 568 #define R_USB_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */ 569 #define R_USB_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */ 570 571 /* PHYTRIM1 */ 572 #define R_USB_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ 573 #define R_USB_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ 574 #define R_USB_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ 575 #define R_USB_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ 576 #define R_USB_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ 577 #define R_USB_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ 578 #define R_USB_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ 579 #define R_USB_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ 580 #define R_USB_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ 581 #define R_USB_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ 582 583 /* PHYTRIM2 */ 584 #define R_USB_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ 585 #define R_USB_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ 586 #define R_USB_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ 587 #define R_USB_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ 588 #define R_USB_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ 589 #define R_USB_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ 590 #define R_USB_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ 591 #define R_USB_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ 592 593 /* DPUSR0R */ 594 #define R_USB_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */ 595 #define R_USB_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */ 596 #define R_USB_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */ 597 #define R_USB_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */ 598 #define R_USB_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */ 599 #define R_USB_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */ 600 601 /* DPUSR1R */ 602 #define R_USB_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */ 603 #define R_USB_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */ 604 #define R_USB_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */ 605 #define R_USB_DPUSR1R_DOVCBH_Msk (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */ 606 #define R_USB_DPUSR1R_DOVCAH_Pos (20UL) /* DOVCAH (Bit 20) */ 607 #define R_USB_DPUSR1R_DOVCAH_Msk (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */ 608 #define R_USB_DPUSR1R_DVBSTSHE_Pos (7UL) /* DVBSTSHE (Bit 7) */ 609 #define R_USB_DPUSR1R_DVBSTSHE_Msk (0x80UL) /* DVBSTSHE (Bitfield-Mask: 0x01) */ 610 #define R_USB_DPUSR1R_DOVCBHE_Pos (5UL) /* DOVCBHE (Bit 5) */ 611 #define R_USB_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */ 612 #define R_USB_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */ 613 #define R_USB_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */ 614 615 /* DPUSR2R */ 616 #define R_USB_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */ 617 #define R_USB_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */ 618 #define R_USB_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */ 619 #define R_USB_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */ 620 #define R_USB_DPUSR2R_DMVAL_Pos (5UL) /* DMVAL (Bit 5) */ 621 #define R_USB_DPUSR2R_DMVAL_Msk (0x20UL) /* DMVAL (Bitfield-Mask: 0x01) */ 622 #define R_USB_DPUSR2R_DPVAL_Pos (4UL) /* DPVAL (Bit 4) */ 623 #define R_USB_DPUSR2R_DPVAL_Msk (0x10UL) /* DPVAL (Bitfield-Mask: 0x01) */ 624 #define R_USB_DPUSR2R_DMINT_Pos (1UL) /* DMINT (Bit 1) */ 625 #define R_USB_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */ 626 #define R_USB_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */ 627 #define R_USB_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */ 628 629 /* DPUSRCR */ 630 #define R_USB_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */ 631 #define R_USB_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */ 632 #define R_USB_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */ 633 #define R_USB_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */ 634 635 /* DPUSR0R_FS */ 636 #define R_USB_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */ 637 #define R_USB_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */ 638 #define R_USB_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */ 639 #define R_USB_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */ 640 #define R_USB_DPUSR0R_FS_DOVCA0_Pos (20UL) /* DOVCA0 (Bit 20) */ 641 #define R_USB_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */ 642 #define R_USB_DPUSR0R_FS_DM0_Pos (17UL) /* DM0 (Bit 17) */ 643 #define R_USB_DPUSR0R_FS_DM0_Msk (0x20000UL) /* DM0 (Bitfield-Mask: 0x01) */ 644 #define R_USB_DPUSR0R_FS_DP0_Pos (16UL) /* DP0 (Bit 16) */ 645 #define R_USB_DPUSR0R_FS_DP0_Msk (0x10000UL) /* DP0 (Bitfield-Mask: 0x01) */ 646 #define R_USB_DPUSR0R_FS_FIXPHY0_Pos (4UL) /* FIXPHY0 (Bit 4) */ 647 #define R_USB_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /* FIXPHY0 (Bitfield-Mask: 0x01) */ 648 #define R_USB_DPUSR0R_FS_DRPD0_Pos (3UL) /* DRPD0 (Bit 3) */ 649 #define R_USB_DPUSR0R_FS_DRPD0_Msk (0x8UL) /* DRPD0 (Bitfield-Mask: 0x01) */ 650 #define R_USB_DPUSR0R_FS_RPUE0_Pos (1UL) /* RPUE0 (Bit 1) */ 651 #define R_USB_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */ 652 #define R_USB_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */ 653 #define R_USB_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */ 654 655 /* DPUSR1R_FS */ 656 #define R_USB_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */ 657 #define R_USB_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */ 658 #define R_USB_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */ 659 #define R_USB_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */ 660 #define R_USB_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /* DOVRCRA0 (Bit 20) */ 661 #define R_USB_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */ 662 #define R_USB_DPUSR1R_FS_DMINT0_Pos (17UL) /* DMINT0 (Bit 17) */ 663 #define R_USB_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /* DMINT0 (Bitfield-Mask: 0x01) */ 664 #define R_USB_DPUSR1R_FS_DPINT0_Pos (16UL) /* DPINT0 (Bit 16) */ 665 #define R_USB_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /* DPINT0 (Bitfield-Mask: 0x01) */ 666 #define R_USB_DPUSR1R_FS_DVBSE0_Pos (7UL) /* DVBSE0 (Bit 7) */ 667 #define R_USB_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /* DVBSE0 (Bitfield-Mask: 0x01) */ 668 #define R_USB_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /* DOVRCRBE0 (Bit 5) */ 669 #define R_USB_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /* DOVRCRBE0 (Bitfield-Mask: 0x01) */ 670 #define R_USB_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /* DOVRCRAE0 (Bit 4) */ 671 #define R_USB_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /* DOVRCRAE0 (Bitfield-Mask: 0x01) */ 672 #define R_USB_DPUSR1R_FS_DMINTE0_Pos (1UL) /* DMINTE0 (Bit 1) */ 673 #define R_USB_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /* DMINTE0 (Bitfield-Mask: 0x01) */ 674 #define R_USB_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */ 675 #define R_USB_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */ 676 677 /*--------------------------------------------------------------------*/ 678 /* Register Bit Utils */ 679 /*--------------------------------------------------------------------*/ 680 #define R_USB_PIPE_CTR_PID_NAK (0U << R_USB_PIPE_CTR_PID_Pos) /* NAK response */ 681 #define R_USB_PIPE_CTR_PID_BUF (1U << R_USB_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ 682 #define R_USB_PIPE_CTR_PID_STALL (2U << R_USB_PIPE_CTR_PID_Pos) /* STALL response */ 683 #define R_USB_PIPE_CTR_PID_STALL2 (3U << R_USB_PIPE_CTR_PID_Pos) /* Also STALL response */ 684 685 #define R_USB_DVSTCTR0_RHST_LS (1U << R_USB_DVSTCTR0_RHST_Pos) /* Low-speed connection */ 686 #define R_USB_DVSTCTR0_RHST_FS (2U << R_USB_DVSTCTR0_RHST_Pos) /* Full-speed connection */ 687 #define R_USB_DVSTCTR0_RHST_HS (3U << R_USB_DVSTCTR0_RHST_Pos) /* Full-speed connection */ 688 689 #define R_USB_DEVADD_USBSPD_LS (1U << R_USB_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ 690 #define R_USB_DEVADD_USBSPD_FS (2U << R_USB_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ 691 692 #define R_USB_CFIFOSEL_ISEL_WRITE (1U << R_USB_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ 693 694 #define R_USB_FIFOSEL_BIGEND (1U << R_USB_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ 695 #define R_USB_FIFOSEL_MBW_8BIT (0U << R_USB_CFIFOSEL_MBW_Pos) /* 8-bit width */ 696 #define R_USB_FIFOSEL_MBW_16BIT (1U << R_USB_CFIFOSEL_MBW_Pos) /* 16-bit width */ 697 #define R_USB_FIFOSEL_MBW_32BIT (2U << R_USB_CFIFOSEL_MBW_Pos) /* 32-bit width */ 698 699 #define R_USB_INTSTS0_CTSQ_CTRL_RDATA (1U << R_USB_INTSTS0_CTSQ_Pos) 700 701 #define R_USB_INTSTS0_DVSQ_STATE_DEF (1U << R_USB_INTSTS0_DVSQ_Pos) /* Default state */ 702 #define R_USB_INTSTS0_DVSQ_STATE_ADDR (2U << R_USB_INTSTS0_DVSQ_Pos) /* Address state */ 703 #define R_USB_INTSTS0_DVSQ_STATE_SUSP0 (4U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 704 #define R_USB_INTSTS0_DVSQ_STATE_SUSP1 (5U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 705 #define R_USB_INTSTS0_DVSQ_STATE_SUSP2 (6U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 706 #define R_USB_INTSTS0_DVSQ_STATE_SUSP3 (7U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 707 708 #define R_USB_PIPECFG_TYPE_BULK (1U << R_USB_PIPECFG_TYPE_Pos) 709 #define R_USB_PIPECFG_TYPE_INT (2U << R_USB_PIPECFG_TYPE_Pos) 710 #define R_USB_PIPECFG_TYPE_ISO (3U << R_USB_PIPECFG_TYPE_Pos) 711 712 typedef struct 713 { 714 union 715 { 716 volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */ 717 718 struct __PACKED 719 { 720 uint16_t : 8; 721 volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */ 722 volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */ 723 uint16_t : 6; 724 } E_b; 725 }; 726 727 union 728 { 729 volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */ 730 731 struct __PACKED 732 { 733 volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */ 734 } N_b; 735 }; 736 } R_USB_PIPE_TR_t; /* Size = 4 (0x4) */ 737 738 /*--------------------------------------------------------------------*/ 739 /* Register Bit Utils */ 740 /*--------------------------------------------------------------------*/ 741 #define R_USB_PIPE_CTR_PID_NAK (0U << R_USB_PIPE_CTR_PID_Pos) /* NAK response */ 742 #define R_USB_PIPE_CTR_PID_BUF (1U << R_USB_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */ 743 #define R_USB_PIPE_CTR_PID_STALL (2U << R_USB_PIPE_CTR_PID_Pos) /* STALL response */ 744 #define R_USB_PIPE_CTR_PID_STALL2 (3U << R_USB_PIPE_CTR_PID_Pos) /* Also STALL response */ 745 746 #define R_USB_DVSTCTR0_RHST_LS (1U << R_USB_DVSTCTR0_RHST_Pos) /* Low-speed connection */ 747 #define R_USB_DVSTCTR0_RHST_FS (2U << R_USB_DVSTCTR0_RHST_Pos) /* Full-speed connection */ 748 #define R_USB_DVSTCTR0_RHST_HS (3U << R_USB_DVSTCTR0_RHST_Pos) /* Full-speed connection */ 749 750 #define R_USB_DEVADD_USBSPD_LS (1U << R_USB_DEVADD_USBSPD_Pos) /* Target Device Low-speed */ 751 #define R_USB_DEVADD_USBSPD_FS (2U << R_USB_DEVADD_USBSPD_Pos) /* Target Device Full-speed */ 752 753 #define R_USB_CFIFOSEL_ISEL_WRITE (1U << R_USB_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/ 754 755 #define R_USB_FIFOSEL_BIGEND (1U << R_USB_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */ 756 #define R_USB_FIFOSEL_MBW_8BIT (0U << R_USB_CFIFOSEL_MBW_Pos) /* 8-bit width */ 757 #define R_USB_FIFOSEL_MBW_16BIT (1U << R_USB_CFIFOSEL_MBW_Pos) /* 16-bit width */ 758 #define R_USB_FIFOSEL_MBW_32BIT (2U << R_USB_CFIFOSEL_MBW_Pos) /* 32-bit width */ 759 760 #define R_USB_INTSTS0_CTSQ_CTRL_RDATA (1U << R_USB_INTSTS0_CTSQ_Pos) 761 762 #define R_USB_INTSTS0_DVSQ_STATE_DEF (1U << R_USB_INTSTS0_DVSQ_Pos) /* Default state */ 763 #define R_USB_INTSTS0_DVSQ_STATE_ADDR (2U << R_USB_INTSTS0_DVSQ_Pos) /* Address state */ 764 #define R_USB_INTSTS0_DVSQ_STATE_SUSP0 (4U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 765 #define R_USB_INTSTS0_DVSQ_STATE_SUSP1 (5U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 766 #define R_USB_INTSTS0_DVSQ_STATE_SUSP2 (6U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 767 #define R_USB_INTSTS0_DVSQ_STATE_SUSP3 (7U << R_USB_INTSTS0_DVSQ_Pos) /* Suspend state */ 768 769 #define R_USB_PIPECFG_TYPE_BULK (1U << R_USB_PIPECFG_TYPE_Pos) 770 #define R_USB_PIPECFG_TYPE_INT (2U << R_USB_PIPECFG_TYPE_Pos) 771 #define R_USB_PIPECFG_TYPE_ISO (3U << R_USB_PIPECFG_TYPE_Pos) 772 773 #endif /* R_USB_DEVICE_DEFINE_H */ 774
