1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * @file     ./out/R7FA8T1AH.h
7  * @brief    CMSIS HeaderFile
8  * @version  1.2
9  */
10 
11 /** @addtogroup Renesas
12  * @{
13  */
14 
15 /** @addtogroup R7FA8T1AH
16  * @{
17  */
18 
19 #ifndef R7FA8T1AH_H
20  #define R7FA8T1AH_H
21 
22  #ifdef __cplusplus
23 extern "C" {
24  #endif
25 
26 /** @addtogroup Configuration_of_CMSIS
27  * @{
28  */
29 
30 /* =========================================================================================================================== */
31 /* ================                                Interrupt Number Definition                                ================ */
32 /* =========================================================================================================================== */
33 
34 /* =========================================================================================================================== */
35 /* ================                           Processor and Core Peripheral Section                           ================ */
36 /* =========================================================================================================================== */
37 
38 /* ==========================  Configuration of the ARM Cortex-M85 Processor and Core Peripherals  =========================== */
39  #define __CM85_REV                0x0000U /*!< CM85 Core Revision                                                        */
40  #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
41  #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
42  #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
43  #define __MPU_PRESENT             1       /*!< MPU present                                                               */
44  #define __FPU_PRESENT             1       /*!< FPU present                                                               */
45  #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
46  #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
47  #define __ICACHE_PRESENT          1       /*!< Instruction Cache present                                                 */
48  #define __DCACHE_PRESENT          1       /*!< Data Cache present                                                        */
49  #define __SAUREGION_PRESENT       1       /*!< SAU region present                                                        */
50  #define __PMU_PRESENT             0       /*!< PMU present                                                               */
51  #define __PMU_NUM_EVENTCNT        0       /*!< PMU Event Counters                                                        */
52 
53 /** @} */ /* End of group Configuration_of_CMSIS */
54 
55  #include "core_cm85.h"                    /*!< ARM Cortex-M85 processor and core peripherals                             */
56  #include "system.h"                       /*!< R7FA8T1AH System                                                          */
57 
58  #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
59   #define __IM     __I
60  #endif
61  #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
62   #define __OM     __O
63  #endif
64  #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
65   #define __IOM    __IO
66  #endif
67 
68 /* ========================================  Start of section using anonymous unions  ======================================== */
69  #if defined(__CC_ARM)
70   #pragma push
71   #pragma anon_unions
72  #elif defined(__ICCARM__)
73   #pragma language=extended
74  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
75   #pragma clang diagnostic push
76   #pragma clang diagnostic ignored "-Wc11-extensions"
77   #pragma clang diagnostic ignored "-Wreserved-id-macro"
78   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
79   #pragma clang diagnostic ignored "-Wnested-anon-types"
80  #elif defined(__GNUC__)
81 
82 /* anonymous unions are enabled by default */
83  #elif defined(__TMS470__)
84 
85 /* anonymous unions are enabled by default */
86  #elif defined(__TASKING__)
87   #pragma warning 586
88  #elif defined(__CSMC__)
89 
90 /* anonymous unions are enabled by default */
91  #else
92   #warning Not supported compiler type
93  #endif
94 
95 /* =========================================================================================================================== */
96 /* ================                              Device Specific Cluster Section                              ================ */
97 /* =========================================================================================================================== */
98 
99 /** @addtogroup Device_Peripheral_clusters
100  * @{
101  */
102 
103 /**
104  * @brief R_BUS_CSa [CSa] (CS Registers)
105  */
106 typedef struct
107 {
108     __IM uint16_t RESERVED;
109 
110     union
111     {
112         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
113 
114         struct
115         {
116             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
117             uint16_t             : 2;
118             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
119             uint16_t             : 4;
120             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
121             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
122             uint16_t             : 5;
123             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
124         } MOD_b;
125     };
126 
127     union
128     {
129         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
130 
131         struct
132         {
133             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
134             uint32_t                : 5;
135             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
136             uint32_t                : 5;
137             __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
138             uint32_t                : 3;
139             __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
140             uint32_t                : 3;
141         } WCR1_b;
142     };
143 
144     union
145     {
146         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
147 
148         struct
149         {
150             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
151             uint32_t              : 1;
152             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
153             uint32_t              : 1;
154             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
155             uint32_t              : 1;
156             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
157             uint32_t              : 2;
158             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
159             uint32_t              : 1;
160             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
161             uint32_t              : 1;
162             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
163             uint32_t              : 1;
164             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
165             uint32_t              : 1;
166         } WCR2_b;
167     };
168     __IM uint32_t RESERVED1;
169 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
170 
171 /**
172  * @brief R_BUS_CSb [CSb] (CS Registers)
173  */
174 typedef struct
175 {
176     __IM uint16_t RESERVED;
177 
178     union
179     {
180         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
181 
182         struct
183         {
184             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
185             uint16_t             : 3;
186             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
187             uint16_t             : 2;
188             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
189             uint16_t             : 3;
190             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
191             uint16_t             : 3;
192         } CR_b;
193     };
194     __IM uint16_t RESERVED1[3];
195 
196     union
197     {
198         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
199 
200         struct
201         {
202             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
203             uint16_t            : 4;
204             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
205             uint16_t            : 4;
206         } REC_b;
207     };
208     __IM uint16_t RESERVED2[2];
209 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
210 
211 /**
212  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
213  */
214 typedef struct
215 {
216     union
217     {
218         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
219 
220         struct
221         {
222             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
223             uint8_t             : 3;
224             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
225             uint8_t             : 2;
226         } SDCCR_b;
227     };
228 
229     union
230     {
231         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
232 
233         struct
234         {
235             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
236             uint8_t             : 7;
237         } SDCMOD_b;
238     };
239 
240     union
241     {
242         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
243 
244         struct
245         {
246             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
247             uint8_t          : 7;
248         } SDAMOD_b;
249     };
250     __IM uint8_t  RESERVED;
251     __IM uint32_t RESERVED1[3];
252 
253     union
254     {
255         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
256 
257         struct
258         {
259             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
260             uint8_t            : 7;
261         } SDSELF_b;
262     };
263     __IM uint8_t  RESERVED2;
264     __IM uint16_t RESERVED3;
265 
266     union
267     {
268         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
269 
270         struct
271         {
272             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
273             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
274                                         *   Setting. ( REFW+1 Cycles )                                                */
275         } SDRFCR_b;
276     };
277 
278     union
279     {
280         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
281 
282         struct
283         {
284             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
285             uint8_t            : 7;
286         } SDRFEN_b;
287     };
288     __IM uint8_t  RESERVED4;
289     __IM uint32_t RESERVED5[2];
290 
291     union
292     {
293         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
294 
295         struct
296         {
297             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
298             uint8_t             : 7;
299         } SDICR_b;
300     };
301     __IM uint8_t  RESERVED6;
302     __IM uint16_t RESERVED7;
303 
304     union
305     {
306         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
307 
308         struct
309         {
310             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
311             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
312             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
313                                         *   )                                                                         */
314             uint16_t : 5;
315         } SDIR_b;
316     };
317     __IM uint16_t RESERVED8;
318     __IM uint32_t RESERVED9[6];
319 
320     union
321     {
322         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
323 
324         struct
325         {
326             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
327             uint8_t           : 6;
328         } SDADR_b;
329     };
330     __IM uint8_t  RESERVED10;
331     __IM uint16_t RESERVED11;
332 
333     union
334     {
335         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
336 
337         struct
338         {
339             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
340             uint32_t           : 5;
341             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
342             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
343             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
344             uint32_t           : 2;
345             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
346             uint32_t           : 13;
347         } SDTR_b;
348     };
349 
350     union
351     {
352         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
353 
354         struct
355         {
356             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
357             uint16_t          : 1;
358         } SDMOD_b;
359     };
360     __IM uint16_t RESERVED12;
361     __IM uint32_t RESERVED13;
362 
363     union
364     {
365         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
366 
367         struct
368         {
369             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
370             uint8_t            : 2;
371             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
372             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
373             uint8_t            : 3;
374         } SDSR_b;
375     };
376     __IM uint8_t  RESERVED14;
377     __IM uint16_t RESERVED15;
378 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
379 
380 /**
381  * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
382  */
383 typedef struct
384 {
385     union
386     {
387         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
388 
389         struct
390         {
391             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
392         } ADD_b;
393     };
394 
395     union
396     {
397         union
398         {
399             __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */
400 
401             struct
402             {
403                 __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
404                 uint8_t              : 6;
405                 __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
406             } STAT_b;
407         };
408 
409         union
410         {
411             __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */
412 
413             struct
414             {
415                 __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
416                 uint8_t             : 7;
417             } RW_b;
418         };
419     };
420     __IM uint8_t  RESERVED;
421     __IM uint16_t RESERVED1;
422     __IM uint32_t RESERVED2[2];
423 } R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */
424 
425 /**
426  * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
427  */
428 typedef struct
429 {
430     union
431     {
432         __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */
433 
434         struct
435         {
436             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
437         } ADD_b;
438     };
439 
440     union
441     {
442         __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */
443 
444         struct
445         {
446             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
447             uint8_t              : 7;
448         } RW_b;
449     };
450     __IM uint8_t  RESERVED;
451     __IM uint16_t RESERVED1;
452     __IM uint32_t RESERVED2[2];
453 } R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */
454 
455 /**
456  * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
457  */
458 typedef struct
459 {
460     union
461     {
462         __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */
463 
464         struct
465         {
466             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
467             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
468             uint8_t                : 1;
469             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
470             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
471             __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
472             uint8_t                : 2;
473         } STAT_b;
474     };
475     __IM uint8_t RESERVED[7];
476 
477     union
478     {
479         __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */
480 
481         struct
482         {
483             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
484             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
485             uint8_t                : 1;
486             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
487             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
488             __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
489             uint8_t                : 2;
490         } CLR_b;
491     };
492     __IM uint8_t RESERVED1[7];
493 } R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */
494 
495 /**
496  * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
497  */
498 typedef struct
499 {
500     __IM uint8_t RESERVED[36];
501 
502     union
503     {
504         __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */
505 
506         struct
507         {
508             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
509             uint8_t                : 7;
510         } STAT_b;
511     };
512     __IM uint8_t RESERVED1[7];
513 
514     union
515     {
516         __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */
517 
518         struct
519         {
520             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
521             uint8_t                : 7;
522         } CLR_b;
523     };
524 } R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */
525 
526 /**
527  * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
528  */
529 typedef struct
530 {
531     __IM uint32_t RESERVED[2];
532 
533     union
534     {
535         __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */
536 
537         struct
538         {
539             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
540             uint32_t            : 31;
541         } MRE0BI_b;
542     };
543     __IM uint32_t RESERVED1;
544 
545     union
546     {
547         __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */
548 
549         struct
550         {
551             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
552             uint32_t            : 31;
553         } FLBI_b;
554     };
555     __IM uint32_t RESERVED2[3];
556 
557     union
558     {
559         __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
560 
561         struct
562         {
563             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
564             uint32_t            : 31;
565         } S0BI_b;
566     };
567     __IM uint32_t RESERVED3;
568 
569     union
570     {
571         __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */
572 
573         struct
574         {
575             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
576             uint32_t            : 31;
577         } S1BI_b;
578     };
579     __IM uint32_t RESERVED4;
580 
581     union
582     {
583         __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */
584 
585         struct
586         {
587             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
588             uint32_t            : 31;
589         } S2BI_b;
590     };
591     __IM uint32_t RESERVED5;
592 
593     union
594     {
595         __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */
596 
597         struct
598         {
599             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
600             uint32_t            : 31;
601         } S3BI_b;
602     };
603     __IM uint32_t RESERVED6[3];
604 
605     union
606     {
607         __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */
608 
609         struct
610         {
611             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
612             uint32_t            : 31;
613         } STBYSBI_b;
614     };
615     __IM uint32_t RESERVED7;
616 
617     union
618     {
619         union
620         {
621             __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
622 
623             struct
624             {
625                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
626                 uint32_t            : 31;
627             } ECBI_b;
628         };
629 
630         union
631         {
632             __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
633 
634             struct
635             {
636                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
637                 uint32_t            : 31;
638             } SPI0BI_b;
639         };
640     };
641     __IM uint32_t RESERVED8;
642 
643     union
644     {
645         union
646         {
647             __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
648 
649             struct
650             {
651                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
652                 uint32_t            : 31;
653             } EOBI_b;
654         };
655 
656         union
657         {
658             __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
659 
660             struct
661             {
662                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
663                 uint32_t            : 31;
664             } SPI1BI_b;
665         };
666     };
667     __IM uint32_t RESERVED9;
668 
669     union
670     {
671         __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */
672 
673         struct
674         {
675             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
676             uint32_t            : 31;
677         } PBBI_b;
678     };
679     __IM uint32_t RESERVED10;
680 
681     union
682     {
683         union
684         {
685             __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
686 
687             struct
688             {
689                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
690                 uint32_t            : 31;
691             } PABI_b;
692         };
693 
694         union
695         {
696             __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
697 
698             struct
699             {
700                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
701                 uint32_t            : 31;
702             } CPU0SAHBI_b;
703         };
704     };
705     __IM uint32_t RESERVED11;
706 
707     union
708     {
709         union
710         {
711             __IOM uint32_t PIBI;         /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
712 
713             struct
714             {
715                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
716                 uint32_t            : 31;
717             } PIBI_b;
718         };
719 
720         union
721         {
722             __IOM uint32_t CPU1TCMBI;    /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
723 
724             struct
725             {
726                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
727                 uint32_t            : 31;
728             } CPU1TCMBI_b;
729         };
730     };
731     __IM uint32_t RESERVED12;
732 
733     union
734     {
735         __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */
736 
737         struct
738         {
739             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
740             uint32_t            : 31;
741         } PSBI_b;
742     };
743 } R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */
744 
745 /**
746  * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
747  */
748 typedef struct
749 {
750     union
751     {
752         union
753         {
754             __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
755 
756             struct
757             {
758                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
759                 uint32_t            : 30;
760             } FHBI_b;
761         };
762 
763         union
764         {
765             __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
766 
767             struct
768             {
769                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
770                 uint32_t            : 30;
771             } MRC0BI_b;
772         };
773     };
774     __IM uint32_t RESERVED[5];
775 
776     union
777     {
778         __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */
779 
780         struct
781         {
782             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
783             uint32_t            : 30;
784         } S0BI_b;
785     };
786     __IM uint32_t RESERVED1;
787 
788     union
789     {
790         __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
791 
792         struct
793         {
794             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
795             uint32_t            : 30;
796         } S1BI_b;
797     };
798 } R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */
799 
800 /**
801  * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
802  */
803 typedef struct
804 {
805     union
806     {
807         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */
808 
809         struct
810         {
811             __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
812         } ADD_b;
813     };
814 
815     union
816     {
817         __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
818                                          *                  Write.                                                     */
819 
820         struct
821         {
822             __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
823                                          *   Status.                                                                   */
824             uint8_t : 7;
825         } RW_b;
826     };
827     __IM uint8_t  RESERVED;
828     __IM uint16_t RESERVED1;
829     __IM uint32_t RESERVED2[2];
830 } R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */
831 
832 /**
833  * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
834  */
835 typedef struct
836 {
837     union
838     {
839         __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */
840 
841         struct
842         {
843             __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
844             __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
845             __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
846             uint16_t                : 13;
847         } BUSOAD_b;
848     };
849     __IM uint16_t RESERVED;
850 
851     union
852     {
853         __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */
854 
855         struct
856         {
857             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
858             uint16_t               : 7;
859             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
860         } BUSOADPT_b;
861     };
862     __IM uint16_t RESERVED1[5];
863 
864     union
865     {
866         __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
867                                         *                  Register.                                                  */
868 
869         struct
870         {
871             __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
872             uint16_t           : 7;
873             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
874         } MSAOAD_b;
875     };
876     __IM uint16_t RESERVED2;
877 
878     union
879     {
880         __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */
881 
882         struct
883         {
884             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
885             uint16_t               : 7;
886             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
887         } MSAPT_b;
888     };
889 } R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */
890 
891 /**
892  * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
893  */
894 typedef struct
895 {
896     union
897     {
898         __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */
899 
900         struct
901         {
902             __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
903             __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
904             __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
905             __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
906             __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
907             __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
908             __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
909             __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
910             __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
911             __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
912             __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
913             __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
914             __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
915             __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
916             __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
917             __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
918             __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
919             __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
920             __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
921             __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
922             __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
923             __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
924             __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
925             __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
926             __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
927             __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
928             __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
929             __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
930             __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
931             __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
932             __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
933             __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
934         } STAT_b;
935     };
936     __IM uint32_t RESERVED;
937 
938     union
939     {
940         __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */
941 
942         struct
943         {
944             __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
945             __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
946             __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
947             __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
948             __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
949             __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
950             __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
951             __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
952             __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
953             __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
954             __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
955             __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
956             __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
957             __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
958             __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
959             __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
960             __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
961             __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
962             __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
963             __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
964             __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
965             __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
966             __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
967             __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
968             __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
969             __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
970             __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
971             __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
972             __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
973             __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
974             __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
975             __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
976         } CLR_b;
977     };
978 } R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */
979 
980 /**
981  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
982  */
983 typedef struct
984 {
985     union
986     {
987         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
988 
989         struct
990         {
991             uint16_t             : 15;
992             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
993         } CNT_b;
994     };
995     __IM uint16_t RESERVED;
996 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
997 
998 /**
999  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
1000  */
1001 typedef struct
1002 {
1003     union
1004     {
1005         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
1006 
1007         struct
1008         {
1009             __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
1010             uint16_t              : 2;
1011             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
1012             uint16_t              : 10;
1013         } CNT_b;
1014     };
1015     __IM uint16_t RESERVED;
1016 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
1017 
1018 /**
1019  * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
1020  */
1021 typedef struct
1022 {
1023     union
1024     {
1025         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
1026 
1027         struct
1028         {
1029             __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
1030             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
1031             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
1032             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
1033         } NCFG_b;
1034     };
1035 
1036     union
1037     {
1038         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
1039 
1040         struct
1041         {
1042             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
1043             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
1044             __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
1045             uint32_t               : 4;
1046             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
1047             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
1048             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
1049             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
1050             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
1051             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
1052             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
1053             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
1054             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
1055             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
1056             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
1057             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
1058                                          *   enable                                                                    */
1059             uint32_t            : 1;
1060             __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
1061             __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
1062             __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
1063             __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
1064             uint32_t            : 3;
1065             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
1066             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
1067         } CTR_b;
1068     };
1069 
1070     union
1071     {
1072         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
1073 
1074         struct
1075         {
1076             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
1077             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
1078             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
1079             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
1080             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
1081             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
1082             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
1083             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
1084             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
1085             uint32_t               : 7;
1086             __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
1087             __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
1088         } STS_b;
1089     };
1090 
1091     union
1092     {
1093         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
1094 
1095         struct
1096         {
1097             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
1098             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
1099             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
1100             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
1101             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
1102             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
1103             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
1104             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
1105             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
1106             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
1107             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
1108             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
1109             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
1110             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
1111             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
1112             uint32_t             : 1;
1113             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
1114             uint32_t             : 1;
1115         } ERFL_b;
1116     };
1117 } R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
1118 
1119 /**
1120  * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
1121  */
1122 typedef struct
1123 {
1124     union
1125     {
1126         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
1127 
1128         struct
1129         {
1130             __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
1131             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
1132             uint32_t              : 3;
1133             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
1134             uint32_t              : 4;
1135             __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
1136             uint32_t              : 4;
1137         } DCFG_b;
1138     };
1139 
1140     union
1141     {
1142         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
1143 
1144         struct
1145         {
1146             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
1147             uint32_t              : 5;
1148             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
1149             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
1150             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
1151             uint32_t              : 5;
1152             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
1153             uint32_t              : 4;
1154             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
1155             __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
1156             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
1157             uint32_t              : 1;
1158         } FDCFG_b;
1159     };
1160 
1161     union
1162     {
1163         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
1164 
1165         struct
1166         {
1167             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
1168             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
1169             uint32_t              : 30;
1170         } FDCTR_b;
1171     };
1172 
1173     union
1174     {
1175         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
1176 
1177         struct
1178         {
1179             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
1180             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
1181             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
1182             uint32_t             : 5;
1183             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
1184             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
1185             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
1186         } FDSTS_b;
1187     };
1188 
1189     union
1190     {
1191         __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
1192 
1193         struct
1194         {
1195             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
1196             uint32_t             : 3;
1197             __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
1198             uint32_t             : 4;
1199         } FDCRC_b;
1200     };
1201     __IM uint32_t RESERVED[3];
1202 } R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
1203 
1204 /**
1205  * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
1206  */
1207 typedef struct
1208 {
1209     union
1210     {
1211         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
1212 
1213         struct
1214         {
1215             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
1216             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
1217             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
1218             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
1219         } ID_b;
1220     };
1221 
1222     union
1223     {
1224         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
1225 
1226         struct
1227         {
1228             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
1229             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
1230             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
1231             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
1232         } M_b;
1233     };
1234 
1235     union
1236     {
1237         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
1238 
1239         struct
1240         {
1241             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
1242             uint32_t                : 3;
1243             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
1244             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
1245                                           *   Pointer                                                                   */
1246             uint32_t               : 2;
1247             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
1248             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
1249         } P0_b;
1250     };
1251 
1252     union
1253     {
1254         __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
1255 
1256         struct
1257         {
1258             __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
1259             uint32_t               : 23;
1260         } P1_b;
1261     };
1262 } R_CANFD_CFDGAFL_Type;                 /*!< Size = 16 (0x10)                                                          */
1263 
1264 /**
1265  * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
1266  */
1267 typedef struct
1268 {
1269     union
1270     {
1271         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
1272 
1273         struct
1274         {
1275             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
1276             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
1277             uint32_t           : 6;
1278             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
1279         } ACC0_b;
1280     };
1281 
1282     union
1283     {
1284         __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
1285 
1286         struct
1287         {
1288             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
1289             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
1290             uint32_t           : 14;
1291         } ACC1_b;
1292     };
1293 } R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
1294 
1295 /**
1296  * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
1297  */
1298 typedef struct
1299 {
1300     union
1301     {
1302         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
1303 
1304         struct
1305         {
1306             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
1307             uint32_t            : 1;
1308             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
1309             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
1310         } ID_b;
1311     };
1312 
1313     union
1314     {
1315         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
1316 
1317         struct
1318         {
1319             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
1320             uint32_t            : 12;
1321             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
1322         } PTR_b;
1323     };
1324 
1325     union
1326     {
1327         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
1328 
1329         struct
1330         {
1331             __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1332             __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1333             __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1334             uint32_t            : 5;
1335             __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
1336             uint32_t            : 6;
1337             __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
1338         } FDSTS_b;
1339     };
1340 
1341     union
1342     {
1343         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
1344 
1345         struct
1346         {
1347             __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
1348         } DF_b[64];
1349     };
1350 } R_CANFD_CFDRF_Type;                  /*!< Size = 76 (0x4c)                                                          */
1351 
1352 /**
1353  * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
1354  */
1355 typedef struct
1356 {
1357     union
1358     {
1359         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
1360 
1361         struct
1362         {
1363             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
1364             uint32_t             : 1;
1365             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
1366             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
1367         } ID_b;
1368     };
1369 
1370     union
1371     {
1372         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
1373 
1374         struct
1375         {
1376             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
1377             uint32_t             : 12;
1378             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
1379         } PTR_b;
1380     };
1381 
1382     union
1383     {
1384         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
1385 
1386         struct
1387         {
1388             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1389             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1390             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1391             uint32_t             : 5;
1392             __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
1393             uint32_t             : 6;
1394             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
1395         } FDSTS_b;
1396     };
1397 
1398     union
1399     {
1400         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
1401 
1402         struct
1403         {
1404             __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
1405         } DF_b[64];
1406     };
1407 } R_CANFD_CFDCF_Type;                  /*!< Size = 76 (0x4c)                                                          */
1408 
1409 /**
1410  * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
1411  */
1412 typedef struct
1413 {
1414     union
1415     {
1416         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
1417 
1418         struct
1419         {
1420             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
1421             uint32_t             : 1;
1422             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
1423             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
1424         } ID_b;
1425     };
1426 
1427     union
1428     {
1429         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
1430 
1431         struct
1432         {
1433             __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
1434             uint32_t             : 12;
1435             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
1436         } PTR_b;
1437     };
1438 
1439     union
1440     {
1441         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
1442 
1443         struct
1444         {
1445             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1446             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1447             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1448             uint32_t             : 5;
1449             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
1450             uint32_t             : 6;
1451             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
1452         } FDCTR_b;
1453     };
1454 
1455     union
1456     {
1457         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
1458 
1459         struct
1460         {
1461             __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
1462         } DF_b[64];
1463     };
1464 } R_CANFD_CFDTM_Type;                  /*!< Size = 76 (0x4c)                                                          */
1465 
1466 /**
1467  * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
1468  */
1469 typedef struct
1470 {
1471     union
1472     {
1473         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
1474 
1475         struct
1476         {
1477             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
1478             uint32_t            : 1;
1479             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
1480             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
1481         } ID_b;
1482     };
1483 
1484     union
1485     {
1486         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
1487 
1488         struct
1489         {
1490             __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
1491             uint32_t            : 12;
1492             __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
1493         } PTR_b;
1494     };
1495 
1496     union
1497     {
1498         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
1499 
1500         struct
1501         {
1502             __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1503             __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1504             __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1505             uint32_t            : 5;
1506             __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
1507             uint32_t            : 6;
1508             __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
1509         } FDSTS_b;
1510     };
1511 
1512     union
1513     {
1514         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
1515 
1516         struct
1517         {
1518             __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
1519         } DF_b[64];
1520     };
1521 } R_CANFD_CFDRM_RM_Type;               /*!< Size = 76 (0x4c)                                                          */
1522 
1523 /**
1524  * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
1525  */
1526 typedef struct
1527 {
1528     __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
1529     __IM uint32_t               RESERVED[104];
1530 } R_CANFD_CFDRM_Type;                  /*!< Size = 1024 (0x400)                                                       */
1531 
1532 /**
1533  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1534  */
1535 typedef struct
1536 {
1537     union
1538     {
1539         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1540 
1541         struct
1542         {
1543             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1544             uint8_t          : 5;
1545             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1546             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1547         } BY_b;
1548     };
1549     __IM uint8_t RESERVED;
1550 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1551 
1552 /**
1553  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..30])
1554  */
1555 typedef struct
1556 {
1557     union
1558     {
1559         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1560 
1561         struct
1562         {
1563             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1564             uint16_t           : 7;
1565         } HA_b;
1566     };
1567     __IM uint16_t RESERVED;
1568 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1569 
1570 /**
1571  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
1572  */
1573 typedef struct
1574 {
1575     union
1576     {
1577         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
1578 
1579         struct
1580         {
1581             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
1582                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
1583         } L_b;
1584     };
1585 
1586     union
1587     {
1588         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
1589 
1590         struct
1591         {
1592             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
1593             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
1594             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
1595             uint8_t            : 5;
1596         } U_b;
1597     };
1598 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
1599 
1600 /**
1601  * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control)
1602  */
1603 typedef struct
1604 {
1605     union
1606     {
1607         __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */
1608 
1609         struct
1610         {
1611             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
1612             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
1613             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
1614             __IOM uint16_t PP     : 1; /*!< [3..3] Privilege protection                                               */
1615             uint16_t              : 12;
1616         } AC_b;
1617     };
1618     __IM uint16_t RESERVED;
1619 
1620     union
1621     {
1622         __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */
1623 
1624         struct
1625         {
1626             __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
1627                                         *   NOTE: Some low-order bits are fixed to 0.                                 */
1628         } S_b;
1629     };
1630 
1631     union
1632     {
1633         __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */
1634 
1635         struct
1636         {
1637             __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
1638                                         *   end, for use in region determination. NOTE: Some low-order
1639                                         *   bits are fixed to 1.                                                      */
1640         } E_b;
1641     };
1642     __IM uint32_t RESERVED1;
1643 } R_MPU_MMPU_GROUP_REGION_Type;        /*!< Size = 16 (0x10)                                                          */
1644 
1645 /**
1646  * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers)
1647  */
1648 typedef struct
1649 {
1650     union
1651     {
1652         __IOM uint16_t EN;             /*!< (@ 0x00000000) MMPU enable register                                       */
1653 
1654         struct
1655         {
1656             __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable                                      */
1657             uint16_t              : 7;
1658             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1659                                         *   stored.                                                                   */
1660         } EN_b;
1661     };
1662     __IM uint16_t RESERVED;
1663 
1664     union
1665     {
1666         __IOM uint16_t ENPT;            /*!< (@ 0x00000004) MMPU enable protect register                               */
1667 
1668         struct
1669         {
1670             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN                                          */
1671             uint16_t               : 7;
1672             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1673                                          *   stored.                                                                   */
1674         } ENPT_b;
1675     };
1676     __IM uint16_t RESERVED1;
1677 
1678     union
1679     {
1680         __IOM uint16_t RPT;             /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure                   */
1681 
1682         struct
1683         {
1684             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
1685             uint16_t               : 7;
1686             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1687                                          *   stored.                                                                   */
1688         } RPT_b;
1689     };
1690     __IM uint16_t RESERVED2;
1691 
1692     union
1693     {
1694         __IOM uint16_t RPT_SEC;         /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only)           */
1695 
1696         struct
1697         {
1698             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
1699             uint16_t               : 7;
1700             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1701                                          *   stored.                                                                   */
1702         } RPT_SEC_b;
1703     };
1704     __IM uint16_t RESERVED3;
1705     __IM uint32_t RESERVED4[60];
1706     __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control                                     */
1707     __IM uint32_t RESERVED5[32];
1708 } R_MPU_MMPU_GROUP_Type;                          /*!< Size = 512 (0x200)                                                        */
1709 
1710 /**
1711  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
1712  */
1713 typedef struct
1714 {
1715     union
1716     {
1717         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
1718                                         *                  Register                                                   */
1719 
1720         struct
1721         {
1722             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
1723             uint16_t           : 7;
1724             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
1725                                         *   stored.                                                                   */
1726         } OAD_b;
1727     };
1728     __IM uint16_t RESERVED;
1729 
1730     union
1731     {
1732         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
1733 
1734         struct
1735         {
1736             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
1737             uint16_t              : 7;
1738             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
1739             uint16_t              : 7;
1740         } CTL_b;
1741     };
1742 
1743     union
1744     {
1745         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
1746 
1747         struct
1748         {
1749             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
1750             uint16_t               : 7;
1751             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1752                                          *   stored.                                                                   */
1753         } PT_b;
1754     };
1755 
1756     union
1757     {
1758         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
1759 
1760         struct
1761         {
1762             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
1763                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
1764                                            *   The low-order 2 bits are fixed to 0.                                      */
1765         } SA_b;
1766     };
1767 
1768     union
1769     {
1770         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
1771 
1772         struct
1773         {
1774             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
1775                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
1776                                            *   The low-order 2 bits are fixed to 1.                                      */
1777         } EA_b;
1778     };
1779 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
1780 
1781 /**
1782  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
1783  */
1784 typedef struct
1785 {
1786     union
1787     {
1788         union
1789         {
1790             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
1791 
1792             struct
1793             {
1794                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1795                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1796                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1797                 uint32_t             : 1;
1798                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1799                 uint32_t             : 1;
1800                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1801                 uint32_t             : 3;
1802                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1803                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Event on Rising.                                */
1804                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1805                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1806                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
1807                 uint32_t             : 7;
1808                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
1809                                            *   function. For individual pin functions, see the MPC table                 */
1810                 uint32_t : 3;
1811             } PmnPFS_b;
1812         };
1813 
1814         union
1815         {
1816             __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000000) Pin Function Control Register                              */
1817 
1818             struct
1819             {
1820                 __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1821                 __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1822                 __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1823                 uint16_t             : 1;
1824                 __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1825                 uint16_t             : 1;
1826                 __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1827                 uint16_t             : 3;
1828                 __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1829                 __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Event on Rising.                                */
1830                 __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1831                 __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1832             } PmnPFS_HA_b;
1833         };
1834 
1835         union
1836         {
1837             __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000000) Pin Function Control Register                              */
1838 
1839             struct
1840             {
1841                 __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1842                 __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1843                 __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1844                 uint8_t             : 1;
1845                 __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1846                 uint8_t             : 1;
1847                 __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1848                 uint8_t             : 1;
1849             } PmnPFS_BY_b;
1850         };
1851     };
1852 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
1853 
1854 /**
1855  * @brief R_PFS_PORT [PORT] (Port [0..14])
1856  */
1857 typedef struct
1858 {
1859     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
1860 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
1861 
1862 /**
1863  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
1864  */
1865 typedef struct
1866 {
1867     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
1868     __IM uint16_t  RESERVED;
1869 } R_PMISC_PMSAR_Type;                  /*!< Size = 4 (0x4)                                                            */
1870 
1871 /**
1872  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
1873  */
1874 typedef struct
1875 {
1876     union
1877     {
1878         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
1879 
1880         struct
1881         {
1882             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
1883             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
1884             uint8_t            : 1;
1885             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
1886             uint8_t            : 1;
1887             __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
1888         } RTCCR_b;
1889     };
1890     __IM uint8_t RESERVED;
1891 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
1892 
1893 /**
1894  * @brief R_RTC_CP [CP] (Capture registers)
1895  */
1896 typedef struct
1897 {
1898     __IM uint8_t RESERVED[2];
1899 
1900     union
1901     {
1902         union
1903         {
1904             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
1905 
1906             struct
1907             {
1908                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
1909                                          *   seconds                                                                   */
1910                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
1911                                          *   seconds                                                                   */
1912                 uint8_t : 1;
1913             } RSEC_b;
1914         };
1915 
1916         union
1917         {
1918             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
1919 
1920             struct
1921             {
1922                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
1923                                            *   value when a time capture event is detected.                              */
1924             } BCNT0_b;
1925         };
1926     };
1927     __IM uint8_t RESERVED1;
1928 
1929     union
1930     {
1931         union
1932         {
1933             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
1934 
1935             struct
1936             {
1937                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
1938                                          *   minutes                                                                   */
1939                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
1940                                          *   minutes                                                                   */
1941                 uint8_t : 1;
1942             } RMIN_b;
1943         };
1944 
1945         union
1946         {
1947             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
1948 
1949             struct
1950             {
1951                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
1952                                            *   value when a time capture event is detected.                              */
1953             } BCNT1_b;
1954         };
1955     };
1956     __IM uint8_t RESERVED2;
1957 
1958     union
1959     {
1960         union
1961         {
1962             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
1963 
1964             struct
1965             {
1966                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
1967                                         *   minutes                                                                   */
1968                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
1969                                         *   minutes                                                                   */
1970                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
1971                 uint8_t         : 1;
1972             } RHR_b;
1973         };
1974 
1975         union
1976         {
1977             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
1978 
1979             struct
1980             {
1981                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
1982                                            *   value when a time capture event is detected.                              */
1983             } BCNT2_b;
1984         };
1985     };
1986     __IM uint8_t RESERVED3[3];
1987 
1988     union
1989     {
1990         union
1991         {
1992             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
1993 
1994             struct
1995             {
1996                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
1997                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
1998                 uint8_t             : 2;
1999             } RDAY_b;
2000         };
2001 
2002         union
2003         {
2004             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
2005 
2006             struct
2007             {
2008                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
2009                                            *   value when a time capture event is detected.                              */
2010             } BCNT3_b;
2011         };
2012     };
2013     __IM uint8_t RESERVED4;
2014 
2015     union
2016     {
2017         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
2018 
2019         struct
2020         {
2021             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
2022             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
2023                                         *   months                                                                    */
2024             uint8_t : 3;
2025         } RMON_b;
2026     };
2027     __IM uint8_t RESERVED5[3];
2028 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
2029 
2030 /**
2031  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2032  */
2033 typedef struct
2034 {
2035     union
2036     {
2037         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
2038 
2039         struct
2040         {
2041             uint16_t             : 8;
2042             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
2043             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
2044             uint16_t             : 6;
2045         } E_b;
2046     };
2047 
2048     union
2049     {
2050         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
2051 
2052         struct
2053         {
2054             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
2055         } N_b;
2056     };
2057 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2058 
2059 /**
2060  * @brief R_XSPI_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers)
2061  */
2062 typedef struct
2063 {
2064     union
2065     {
2066         __IOM uint32_t CMCFG0;          /*!< (@ 0x00000000) xSPI Command Map Configuration register 0                  */
2067 
2068         struct
2069         {
2070             __IOM uint32_t FFMT    : 2; /*!< [1..0] Frame format                                                       */
2071             __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size                                                       */
2072             __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode                                                */
2073             __IOM uint32_t ARYAMD  : 1; /*!< [5..5] Array address mode                                                 */
2074             uint32_t               : 10;
2075             __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable                                           */
2076             __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code                                             */
2077         } CMCFG0_b;
2078     };
2079 
2080     union
2081     {
2082         __IOM uint32_t CMCFG1;          /*!< (@ 0x00000004) xSPI Command Map Configuration register 1                  */
2083 
2084         struct
2085         {
2086             __IOM uint32_t RDCMD  : 16; /*!< [15..0] Read command                                                      */
2087             __IOM uint32_t RDLATE : 5;  /*!< [20..16] Read latency cycle                                               */
2088             uint32_t              : 11;
2089         } CMCFG1_b;
2090     };
2091 
2092     union
2093     {
2094         __IOM uint32_t CMCFG2;          /*!< (@ 0x00000008) xSPI Command Map Configuration register 2                  */
2095 
2096         struct
2097         {
2098             __IOM uint32_t WRCMD  : 16; /*!< [15..0] Write command                                                     */
2099             __IOM uint32_t WRLATE : 5;  /*!< [20..16] Write latency cycle                                              */
2100             uint32_t              : 11;
2101         } CMCFG2_b;
2102     };
2103     __IM uint32_t RESERVED;
2104 } R_XSPI_CMCFGCS_Type;                 /*!< Size = 16 (0x10)                                                          */
2105 
2106 /**
2107  * @brief R_XSPI_CDBUF [CDBUF] (xSPI BUF register)
2108  */
2109 typedef struct
2110 {
2111     union
2112     {
2113         __IOM uint32_t CDT;               /*!< (@ 0x00000000) xSPI Command Manual Type buf                               */
2114 
2115         struct
2116         {
2117             __IOM uint32_t CMDSIZE  : 2;  /*!< [1..0] Command Size                                                       */
2118             __IOM uint32_t ADDSIZE  : 3;  /*!< [4..2] Address size                                                       */
2119             __IOM uint32_t DATASIZE : 4;  /*!< [8..5] Write/Read Data Size                                               */
2120             __IOM uint32_t LATE     : 5;  /*!< [13..9] Latency cycle                                                     */
2121             uint32_t                : 1;
2122             __IOM uint32_t TRTYPE   : 1;  /*!< [15..15] Transaction Type                                                 */
2123             __IOM uint32_t CMD      : 16; /*!< [31..16] Command (1-2byte)                                                */
2124         } CDT_b;
2125     };
2126 
2127     union
2128     {
2129         __IOM uint32_t CDA;            /*!< (@ 0x00000004) xSPI Command Manual Address buf                            */
2130 
2131         struct
2132         {
2133             __IOM uint32_t ADD : 32;   /*!< [31..0] Address                                                           */
2134         } CDA_b;
2135     };
2136 
2137     union
2138     {
2139         __IOM uint32_t CDD0;           /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf                             */
2140 
2141         struct
2142         {
2143             __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
2144         } CDD0_b;
2145     };
2146 
2147     union
2148     {
2149         __IOM uint32_t CDD1;           /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf                             */
2150 
2151         struct
2152         {
2153             __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
2154         } CDD1_b;
2155     };
2156 } R_XSPI_CDBUF_Type;                   /*!< Size = 16 (0x10)                                                          */
2157 
2158 /**
2159  * @brief R_XSPI_CCCTLCS [CCCTLCS] (xSPI CS register)
2160  */
2161 typedef struct
2162 {
2163     union
2164     {
2165         __IOM uint32_t CCCTL0;           /*!< (@ 0x00000000) xSPI Command Calibration Control register 0                */
2166 
2167         struct
2168         {
2169             __IOM uint32_t CAEN     : 1; /*!< [0..0] Automatic Calibration Enable                                       */
2170             __IOM uint32_t CANOWR   : 1; /*!< [1..1] Calibration no write mode                                          */
2171             uint32_t                : 6;
2172             __IOM uint32_t CAITV    : 5; /*!< [12..8] Calibration interval                                              */
2173             uint32_t                : 3;
2174             __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value                                 */
2175             uint32_t                : 3;
2176             __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value                                   */
2177             uint32_t                : 3;
2178         } CCCTL0_b;
2179     };
2180 
2181     union
2182     {
2183         __IOM uint32_t CCCTL1;             /*!< (@ 0x00000004) xSPI Command Calibration Control register 1                */
2184 
2185         struct
2186         {
2187             __IOM uint32_t CACMDSIZE  : 2; /*!< [1..0] Command Size                                                       */
2188             __IOM uint32_t CAADDSIZE  : 3; /*!< [4..2] Address size                                                       */
2189             __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size                                               */
2190             uint32_t                  : 7;
2191             __IOM uint32_t CAWRLATE   : 5; /*!< [20..16] Write Latency cycle                                              */
2192             uint32_t                  : 3;
2193             __IOM uint32_t CARDLATE   : 5; /*!< [28..24] Read Latency cycle                                               */
2194             uint32_t                  : 3;
2195         } CCCTL1_b;
2196     };
2197 
2198     union
2199     {
2200         __IOM uint32_t CCCTL2;           /*!< (@ 0x00000008) xSPI Command Calibration Control register 2                */
2201 
2202         struct
2203         {
2204             __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command                                 */
2205             __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command                                 */
2206         } CCCTL2_b;
2207     };
2208 
2209     union
2210     {
2211         __IOM uint32_t CCCTL3;         /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3                */
2212 
2213         struct
2214         {
2215             __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address                                       */
2216         } CCCTL3_b;
2217     };
2218 
2219     union
2220     {
2221         __IOM uint32_t CCCTL4;          /*!< (@ 0x00000010) xSPI Command Calibration Control register 4                */
2222 
2223         struct
2224         {
2225             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
2226         } CCCTL4_b;
2227     };
2228 
2229     union
2230     {
2231         __IOM uint32_t CCCTL5;          /*!< (@ 0x00000014) xSPI Command Calibration Control register 5                */
2232 
2233         struct
2234         {
2235             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
2236         } CCCTL5_b;
2237     };
2238 
2239     union
2240     {
2241         __IOM uint32_t CCCTL6;          /*!< (@ 0x00000018) xSPI Command Calibration Control register 6                */
2242 
2243         struct
2244         {
2245             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
2246         } CCCTL6_b;
2247     };
2248 
2249     union
2250     {
2251         __IOM uint32_t CCCTL7;          /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7                */
2252 
2253         struct
2254         {
2255             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
2256         } CCCTL7_b;
2257     };
2258 } R_XSPI_CCCTLCS_Type;                  /*!< Size = 32 (0x20)                                                          */
2259 
2260 /**
2261  * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
2262  */
2263 typedef struct
2264 {
2265     union
2266     {
2267         __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
2268 
2269         struct
2270         {
2271             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
2272             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
2273             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
2274             uint8_t              : 1;
2275             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
2276             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
2277             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
2278             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
2279         } AGTCR_b;
2280     };
2281 
2282     union
2283     {
2284         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
2285 
2286         struct
2287         {
2288             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
2289             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
2290             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
2291             uint8_t              : 1;
2292         } AGTMR1_b;
2293     };
2294 
2295     union
2296     {
2297         __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
2298 
2299         struct
2300         {
2301             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
2302                                         *   ratio                                                                     */
2303             uint8_t           : 4;
2304             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
2305         } AGTMR2_b;
2306     };
2307 
2308     union
2309     {
2310         __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
2311 
2312         struct
2313         {
2314             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2315             uint8_t            : 2;
2316             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2317             uint8_t            : 3;
2318         } AGTIOSEL_ALT_b;
2319     };
2320 
2321     union
2322     {
2323         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
2324 
2325         struct
2326         {
2327             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
2328                                         *   mode.                                                                     */
2329             uint8_t             : 1;
2330             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
2331             uint8_t             : 1;
2332             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
2333             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
2334         } AGTIOC_b;
2335     };
2336 
2337     union
2338     {
2339         __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
2340 
2341         struct
2342         {
2343             uint8_t            : 2;
2344             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
2345             uint8_t            : 5;
2346         } AGTISR_b;
2347     };
2348 
2349     union
2350     {
2351         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
2352 
2353         struct
2354         {
2355             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
2356             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
2357             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
2358             uint8_t              : 1;
2359             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
2360             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
2361             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
2362             uint8_t              : 1;
2363         } AGTCMSR_b;
2364     };
2365 
2366     union
2367     {
2368         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
2369 
2370         struct
2371         {
2372             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2373             uint8_t            : 2;
2374             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2375             uint8_t            : 3;
2376         } AGTIOSEL_b;
2377     };
2378 } R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
2379 
2380 /**
2381  * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
2382  */
2383 typedef struct
2384 {
2385     union
2386     {
2387         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
2388 
2389         struct
2390         {
2391             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
2392                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2393                                         *   counter is forcibly stopped and set to FFFFH.                             */
2394         } AGT_b;
2395     };
2396 
2397     union
2398     {
2399         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
2400 
2401         struct
2402         {
2403             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
2404                                          *   written to the TSTOP bit in the AGTCRn register, set to
2405                                          *   FFFFH                                                                     */
2406         } AGTCMA_b;
2407     };
2408 
2409     union
2410     {
2411         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
2412 
2413         struct
2414         {
2415             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
2416                                          *   written to the TSTOP bit in the AGTCR register, set to
2417                                          *   FFFFH                                                                     */
2418         } AGTCMB_b;
2419     };
2420     __IM uint16_t                 RESERVED;
2421     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
2422 } R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
2423 
2424 /**
2425  * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
2426  */
2427 typedef struct
2428 {
2429     union
2430     {
2431         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
2432 
2433         struct
2434         {
2435             __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
2436                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2437                                         *   counter is forcibly stopped and set to FFFFH.                             */
2438         } AGT_b;
2439     };
2440 
2441     union
2442     {
2443         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
2444 
2445         struct
2446         {
2447             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
2448                                          *   written to the TSTOP bit in the AGTCRn register, set to
2449                                          *   FFFFH                                                                     */
2450         } AGTCMA_b;
2451     };
2452 
2453     union
2454     {
2455         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
2456 
2457         struct
2458         {
2459             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
2460                                          *   written to the TSTOP bit in the AGTCR register, set to
2461                                          *   FFFFH                                                                     */
2462         } AGTCMB_b;
2463     };
2464     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
2465 } R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
2466 
2467 /**
2468  * @brief R_OFS_DATAFLASH_CFGDLOCK_CFGD [CFGD] (Configuration Data [0..1] Lock Bits)
2469  */
2470 typedef struct
2471 {
2472     union
2473     {
2474         __IM uint32_t CFGD_L;          /*!< (@ 0x00000000) Configuration Data Lock Bits Lower Word                    */
2475 
2476         struct
2477         {
2478             __IM uint32_t CDLK0  : 1;  /*!< [0..0] Configuration Data Lock Bit                                        */
2479             __IM uint32_t CDLK1  : 1;  /*!< [1..1] Configuration Data Lock Bit                                        */
2480             __IM uint32_t CDLK2  : 1;  /*!< [2..2] Configuration Data Lock Bit                                        */
2481             __IM uint32_t CDLK3  : 1;  /*!< [3..3] Configuration Data Lock Bit                                        */
2482             __IM uint32_t CDLK4  : 1;  /*!< [4..4] Configuration Data Lock Bit                                        */
2483             __IM uint32_t CDLK5  : 1;  /*!< [5..5] Configuration Data Lock Bit                                        */
2484             __IM uint32_t CDLK6  : 1;  /*!< [6..6] Configuration Data Lock Bit                                        */
2485             __IM uint32_t CDLK7  : 1;  /*!< [7..7] Configuration Data Lock Bit                                        */
2486             __IM uint32_t CDLK8  : 1;  /*!< [8..8] Configuration Data Lock Bit                                        */
2487             __IM uint32_t CDLK9  : 1;  /*!< [9..9] Configuration Data Lock Bit                                        */
2488             __IM uint32_t CDLK10 : 1;  /*!< [10..10] Configuration Data Lock Bit                                      */
2489             __IM uint32_t CDLK11 : 1;  /*!< [11..11] Configuration Data Lock Bit                                      */
2490             __IM uint32_t CDLK12 : 1;  /*!< [12..12] Configuration Data Lock Bit                                      */
2491             __IM uint32_t CDLK13 : 1;  /*!< [13..13] Configuration Data Lock Bit                                      */
2492             __IM uint32_t CDLK14 : 1;  /*!< [14..14] Configuration Data Lock Bit                                      */
2493             __IM uint32_t CDLK15 : 1;  /*!< [15..15] Configuration Data Lock Bit                                      */
2494             __IM uint32_t CDLK16 : 1;  /*!< [16..16] Configuration Data Lock Bit                                      */
2495             __IM uint32_t CDLK17 : 1;  /*!< [17..17] Configuration Data Lock Bit                                      */
2496             __IM uint32_t CDLK18 : 1;  /*!< [18..18] Configuration Data Lock Bit                                      */
2497             __IM uint32_t CDLK19 : 1;  /*!< [19..19] Configuration Data Lock Bit                                      */
2498             __IM uint32_t CDLK20 : 1;  /*!< [20..20] Configuration Data Lock Bit                                      */
2499             __IM uint32_t CDLK21 : 1;  /*!< [21..21] Configuration Data Lock Bit                                      */
2500             __IM uint32_t CDLK22 : 1;  /*!< [22..22] Configuration Data Lock Bit                                      */
2501             __IM uint32_t CDLK23 : 1;  /*!< [23..23] Configuration Data Lock Bit                                      */
2502             __IM uint32_t CDLK24 : 1;  /*!< [24..24] Configuration Data Lock Bit                                      */
2503             __IM uint32_t CDLK25 : 1;  /*!< [25..25] Configuration Data Lock Bit                                      */
2504             __IM uint32_t CDLK26 : 1;  /*!< [26..26] Configuration Data Lock Bit                                      */
2505             __IM uint32_t CDLK27 : 1;  /*!< [27..27] Configuration Data Lock Bit                                      */
2506             __IM uint32_t CDLK28 : 1;  /*!< [28..28] Configuration Data Lock Bit                                      */
2507             __IM uint32_t CDLK29 : 1;  /*!< [29..29] Configuration Data Lock Bit                                      */
2508             __IM uint32_t CDLK30 : 1;  /*!< [30..30] Configuration Data Lock Bit                                      */
2509             __IM uint32_t CDLK31 : 1;  /*!< [31..31] Configuration Data Lock Bit                                      */
2510         } CFGD_L_b;
2511     };
2512 
2513     union
2514     {
2515         __IM uint32_t CFGD_H;          /*!< (@ 0x00000004) Configuration Data Lock Bits Higher Word                   */
2516 
2517         struct
2518         {
2519             __IM uint32_t CDLK32 : 1;  /*!< [0..0] Configuration Data Lock Bit                                        */
2520             __IM uint32_t CDLK33 : 1;  /*!< [1..1] Configuration Data Lock Bit                                        */
2521             __IM uint32_t CDLK34 : 1;  /*!< [2..2] Configuration Data Lock Bit                                        */
2522             __IM uint32_t CDLK35 : 1;  /*!< [3..3] Configuration Data Lock Bit                                        */
2523             __IM uint32_t CDLK36 : 1;  /*!< [4..4] Configuration Data Lock Bit                                        */
2524             __IM uint32_t CDLK37 : 1;  /*!< [5..5] Configuration Data Lock Bit                                        */
2525             __IM uint32_t CDLK38 : 1;  /*!< [6..6] Configuration Data Lock Bit                                        */
2526             __IM uint32_t CDLK39 : 1;  /*!< [7..7] Configuration Data Lock Bit                                        */
2527             __IM uint32_t CDLK40 : 1;  /*!< [8..8] Configuration Data Lock Bit                                        */
2528             __IM uint32_t CDLK41 : 1;  /*!< [9..9] Configuration Data Lock Bit                                        */
2529             __IM uint32_t CDLK42 : 1;  /*!< [10..10] Configuration Data Lock Bit                                      */
2530             __IM uint32_t CDLK43 : 1;  /*!< [11..11] Configuration Data Lock Bit                                      */
2531             __IM uint32_t CDLK44 : 1;  /*!< [12..12] Configuration Data Lock Bit                                      */
2532             __IM uint32_t CDLK45 : 1;  /*!< [13..13] Configuration Data Lock Bit                                      */
2533             __IM uint32_t CDLK46 : 1;  /*!< [14..14] Configuration Data Lock Bit                                      */
2534             __IM uint32_t CDLK47 : 1;  /*!< [15..15] Configuration Data Lock Bit                                      */
2535             __IM uint32_t CDLK48 : 1;  /*!< [16..16] Configuration Data Lock Bit                                      */
2536             __IM uint32_t CDLK49 : 1;  /*!< [17..17] Configuration Data Lock Bit                                      */
2537             __IM uint32_t CDLK50 : 1;  /*!< [18..18] Configuration Data Lock Bit                                      */
2538             __IM uint32_t CDLK51 : 1;  /*!< [19..19] Configuration Data Lock Bit                                      */
2539             __IM uint32_t CDLK52 : 1;  /*!< [20..20] Configuration Data Lock Bit                                      */
2540             __IM uint32_t CDLK53 : 1;  /*!< [21..21] Configuration Data Lock Bit                                      */
2541             __IM uint32_t CDLK54 : 1;  /*!< [22..22] Configuration Data Lock Bit                                      */
2542             __IM uint32_t CDLK55 : 1;  /*!< [23..23] Configuration Data Lock Bit                                      */
2543             __IM uint32_t CDLK56 : 1;  /*!< [24..24] Configuration Data Lock Bit                                      */
2544             __IM uint32_t CDLK57 : 1;  /*!< [25..25] Configuration Data Lock Bit                                      */
2545             __IM uint32_t CDLK58 : 1;  /*!< [26..26] Configuration Data Lock Bit                                      */
2546             __IM uint32_t CDLK59 : 1;  /*!< [27..27] Configuration Data Lock Bit                                      */
2547             __IM uint32_t CDLK60 : 1;  /*!< [28..28] Configuration Data Lock Bit                                      */
2548             __IM uint32_t CDLK61 : 1;  /*!< [29..29] Configuration Data Lock Bit                                      */
2549             __IM uint32_t CDLK62 : 1;  /*!< [30..30] Configuration Data Lock Bit                                      */
2550             __IM uint32_t CDLK63 : 1;  /*!< [31..31] Configuration Data Lock Bit                                      */
2551         } CFGD_H_b;
2552     };
2553 } R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type;  /*!< Size = 8 (0x8)                                                            */
2554 
2555 /**
2556  * @brief R_OFS_DATAFLASH_CFGDLOCK [CFGDLOCK] (Configuration Data Lock Bits)
2557  */
2558 typedef struct
2559 {
2560     __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD0; /*!< (@ 0x00000000) Configuration Data 0 Lock Bits                            */
2561     __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD1; /*!< (@ 0x00000008) Configuration Data 1 Lock Bits                            */
2562 
2563     union
2564     {
2565         __IM uint16_t CFGD2;                        /*!< (@ 0x00000010) Configuration Data 2 Lock Bit                              */
2566 
2567         struct
2568         {
2569             __IM uint16_t CDLK0  : 1;               /*!< [0..0] Configuration Data Lock Bit                                        */
2570             __IM uint16_t CDLK1  : 1;               /*!< [1..1] Configuration Data Lock Bit                                        */
2571             __IM uint16_t CDLK2  : 1;               /*!< [2..2] Configuration Data Lock Bit                                        */
2572             __IM uint16_t CDLK3  : 1;               /*!< [3..3] Configuration Data Lock Bit                                        */
2573             __IM uint16_t CDLK4  : 1;               /*!< [4..4] Configuration Data Lock Bit                                        */
2574             __IM uint16_t CDLK5  : 1;               /*!< [5..5] Configuration Data Lock Bit                                        */
2575             __IM uint16_t CDLK6  : 1;               /*!< [6..6] Configuration Data Lock Bit                                        */
2576             __IM uint16_t CDLK7  : 1;               /*!< [7..7] Configuration Data Lock Bit                                        */
2577             __IM uint16_t CDLK8  : 1;               /*!< [8..8] Configuration Data Lock Bit                                        */
2578             __IM uint16_t CDLK9  : 1;               /*!< [9..9] Configuration Data Lock Bit                                        */
2579             __IM uint16_t CDLK10 : 1;               /*!< [10..10] Configuration Data Lock Bit                                      */
2580             __IM uint16_t CDLK11 : 1;               /*!< [11..11] Configuration Data Lock Bit                                      */
2581             __IM uint16_t CDLK12 : 1;               /*!< [12..12] Configuration Data Lock Bit                                      */
2582             __IM uint16_t CDLK13 : 1;               /*!< [13..13] Configuration Data Lock Bit                                      */
2583             __IM uint16_t CDLK14 : 1;               /*!< [14..14] Configuration Data Lock Bit                                      */
2584             __IM uint16_t CDLK15 : 1;               /*!< [15..15] Configuration Data Lock Bit                                      */
2585         } CFGD2_b;
2586     };
2587     __IM uint16_t RESERVED;
2588 } R_OFS_DATAFLASH_CFGDLOCK_Type;                    /*!< Size = 20 (0x14)                                                          */
2589 
2590 /** @} */ /* End of group Device_Peripheral_clusters */
2591 
2592 /* =========================================================================================================================== */
2593 /* ================                            Device Specific Peripheral Section                             ================ */
2594 /* =========================================================================================================================== */
2595 
2596 /** @addtogroup Device_Peripheral_peripherals
2597  * @{
2598  */
2599 
2600 /* =========================================================================================================================== */
2601 /* ================                                         R_ACMPHS0                                         ================ */
2602 /* =========================================================================================================================== */
2603 
2604 /**
2605  * @brief High-Speed Analog Comparator (R_ACMPHS0)
2606  */
2607 
2608 typedef struct                         /*!< (@ 0x40236000) R_ACMPHS0 Structure                                        */
2609 {
2610     union
2611     {
2612         __IOM uint8_t CMPCTL;          /*!< (@ 0x00000000) Comparator Control Register                                */
2613 
2614         struct
2615         {
2616             __IOM uint8_t CINV   : 1;  /*!< [0..0] Comparator output polarity selection                               */
2617             __IOM uint8_t COE    : 1;  /*!< [1..1] Comparator output enable                                           */
2618             __IOM uint8_t CSTEN  : 1;  /*!< [2..2] Interrupt Select                                                   */
2619             __IOM uint8_t CEG    : 2;  /*!< [4..3] Selection of valid edge (Edge selector)                            */
2620             __IOM uint8_t CDFS   : 2;  /*!< [6..5] Noise filter selection                                             */
2621             __IOM uint8_t HCMPON : 1;  /*!< [7..7] Comparator operation control                                       */
2622         } CMPCTL_b;
2623     };
2624     __IM uint8_t RESERVED[3];
2625 
2626     union
2627     {
2628         __IOM uint8_t CMPSEL0;         /*!< (@ 0x00000004) Comparator Input Select Register                           */
2629 
2630         struct
2631         {
2632             __IOM uint8_t CMPSEL : 4;  /*!< [3..0] Comparator Input Selection                                         */
2633             uint8_t              : 4;
2634         } CMPSEL0_b;
2635     };
2636     __IM uint8_t RESERVED1[3];
2637 
2638     union
2639     {
2640         __IOM uint8_t CMPSEL1;         /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
2641 
2642         struct
2643         {
2644             __IOM uint8_t CRVS : 6;    /*!< [5..0] Reference Voltage Selection                                        */
2645             uint8_t            : 2;
2646         } CMPSEL1_b;
2647     };
2648     __IM uint8_t RESERVED2[3];
2649 
2650     union
2651     {
2652         __IM uint8_t CMPMON;           /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
2653 
2654         struct
2655         {
2656             __IM uint8_t CMPMON : 1;   /*!< [0..0] Comparator output monitor                                          */
2657             uint8_t             : 7;
2658         } CMPMON_b;
2659     };
2660     __IM uint8_t RESERVED3[3];
2661 
2662     union
2663     {
2664         __IOM uint8_t CPIOC;           /*!< (@ 0x00000010) Comparator Output Control Register                         */
2665 
2666         struct
2667         {
2668             __IOM uint8_t CPOE   : 1;  /*!< [0..0] Comparator output selection                                        */
2669             uint8_t              : 6;
2670             __IOM uint8_t VREFEN : 1;  /*!< [7..7] Internal Vref enable                                               */
2671         } CPIOC_b;
2672     };
2673 } R_ACMPHS0_Type;                      /*!< Size = 17 (0x11)                                                          */
2674 
2675 /* =========================================================================================================================== */
2676 /* ================                                          R_ADC0                                           ================ */
2677 /* =========================================================================================================================== */
2678 
2679 /**
2680  * @brief A/D Converter (R_ADC0)
2681  */
2682 
2683 typedef struct                         /*!< (@ 0x40332000) R_ADC0 Structure                                           */
2684 {
2685     union
2686     {
2687         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
2688 
2689         struct
2690         {
2691             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
2692                                         *   input channel for double triggered operation. The setting
2693                                         *   is only effective while double trigger mode is selected.                  */
2694             uint16_t              : 1;
2695             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
2696             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
2697             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
2698             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
2699             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
2700             uint16_t              : 1;
2701             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
2702             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
2703             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
2704         } ADCSR_b;
2705     };
2706 
2707     union
2708     {
2709         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
2710 
2711         struct
2712         {
2713             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
2714                                         *   '1' while scanning.                                                       */
2715             uint8_t              : 6;
2716             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
2717         } ADREF_b;
2718     };
2719 
2720     union
2721     {
2722         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
2723 
2724         struct
2725         {
2726             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
2727             uint8_t             : 7;
2728         } ADEXREF_b;
2729     };
2730 
2731     union
2732     {
2733         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
2734 
2735         struct
2736         {
2737             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
2738             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
2739             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
2740             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
2741             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
2742             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
2743             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
2744             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
2745             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
2746             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
2747             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
2748             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
2749             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
2750             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
2751             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
2752             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
2753         } ADANSA_b[2];
2754     };
2755 
2756     union
2757     {
2758         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
2759                                         *                  Select Register                                            */
2760 
2761         struct
2762         {
2763             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
2764             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
2765             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
2766             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
2767             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
2768             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
2769             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
2770             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
2771             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
2772             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
2773             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
2774             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
2775             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
2776             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
2777             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
2778             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
2779         } ADADS_b[2];
2780     };
2781 
2782     union
2783     {
2784         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
2785                                         *                  Register                                                   */
2786 
2787         struct
2788         {
2789             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
2790                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
2791                                         *   average mode is selected by setting the ADADC.AVEE bit
2792                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
2793                                         *   = 010b)                                                                   */
2794             uint8_t            : 4;
2795             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
2796                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
2797                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
2798                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
2799                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
2800                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
2801                                         *   bit to 1, do not set the addition count to three times
2802                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
2803         } ADADC_b;
2804     };
2805     __IM uint8_t RESERVED;
2806 
2807     union
2808     {
2809         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
2810 
2811         struct
2812         {
2813             uint16_t               : 1;
2814             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
2815             uint16_t               : 1;
2816             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
2817             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
2818             uint16_t               : 2;
2819             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
2820             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
2821             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
2822             uint16_t               : 2;
2823             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
2824             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
2825         } ADCER_b;
2826     };
2827 
2828     union
2829     {
2830         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
2831 
2832         struct
2833         {
2834             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
2835                                         *   the A/D conversion start trigger for group B in group scan
2836                                         *   mode.                                                                     */
2837             uint16_t            : 2;
2838             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
2839                                         *   start trigger in single scan mode and continuous mode.
2840                                         *   In group scan mode, the A/D conversion start trigger for
2841                                         *   group A is selected.                                                      */
2842             uint16_t : 2;
2843         } ADSTRGR_b;
2844     };
2845 
2846     union
2847     {
2848         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
2849 
2850         struct
2851         {
2852             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
2853                                         *   Mode Select                                                               */
2854             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
2855                                         *   Mode Select                                                               */
2856             uint16_t            : 6;
2857             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
2858             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
2859             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
2860                                         *   Group B in group scan mode.                                               */
2861             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
2862                                         *   Group B in group scan mode.                                               */
2863             uint16_t             : 2;
2864             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
2865             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
2866         } ADEXICR_b;
2867     };
2868 
2869     union
2870     {
2871         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
2872 
2873         struct
2874         {
2875             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
2876             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
2877             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
2878             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
2879             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
2880             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
2881             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
2882             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
2883             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
2884             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
2885             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
2886             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
2887             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
2888             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
2889             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
2890             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
2891         } ADANSB_b[2];
2892     };
2893 
2894     union
2895     {
2896         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
2897 
2898         struct
2899         {
2900             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2901                                          *   result of A/D conversion in response to the second trigger
2902                                          *   in double trigger mode.                                                   */
2903         } ADDBLDR_b;
2904     };
2905 
2906     union
2907     {
2908         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
2909 
2910         struct
2911         {
2912             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2913                                         *   A/D conversion result of temperature sensor output.                       */
2914         } ADTSDR_b;
2915     };
2916 
2917     union
2918     {
2919         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
2920 
2921         struct
2922         {
2923             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2924                                         *   A/D result of internal reference voltage.                                 */
2925         } ADOCDR_b;
2926     };
2927 
2928     union
2929     {
2930         union
2931         {
2932             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
2933 
2934             struct
2935             {
2936                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
2937                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2938                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
2939             } ADRD_RIGHT_b;
2940         };
2941 
2942         union
2943         {
2944             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
2945 
2946             struct
2947             {
2948                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
2949                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
2950                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2951             } ADRD_LEFT_b;
2952         };
2953     };
2954 
2955     union
2956     {
2957         __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
2958 
2959         struct
2960         {
2961             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
2962                                         *   storing the result of A/D conversion.                                     */
2963         } ADDR_b[29];
2964     };
2965     __IM uint16_t RESERVED1;
2966     __IM uint32_t RESERVED2;
2967     __IM uint16_t RESERVED3;
2968 
2969     union
2970     {
2971         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
2972 
2973         struct
2974         {
2975             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
2976         } ADAMPOFF_b;
2977     };
2978 
2979     union
2980     {
2981         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
2982 
2983         struct
2984         {
2985             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
2986             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
2987             uint8_t            : 6;
2988         } ADTSTPR_b;
2989     };
2990 
2991     union
2992     {
2993         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
2994 
2995         struct
2996         {
2997             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
2998             uint16_t              : 3;
2999             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
3000             uint16_t              : 2;
3001             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
3002         } ADDDACER_b;
3003     };
3004 
3005     union
3006     {
3007         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
3008 
3009         struct
3010         {
3011             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
3012                                         *   Setting Set the sampling time (4 to 255 states)                           */
3013             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
3014             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
3015             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
3016             uint16_t              : 5;
3017         } ADSHCR_b;
3018     };
3019 
3020     union
3021     {
3022         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
3023 
3024         struct
3025         {
3026             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
3027                                         *   only for channel.                                                         */
3028             uint16_t             : 1;
3029             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
3030             uint16_t             : 2;
3031             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
3032                                         *   for adjustment to hardening of process.                                   */
3033             uint16_t              : 1;
3034             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
3035                                         *   power save bit for A/D hard macro to hardening of process.                */
3036             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
3037                                         *   bit for A/D hard macro to hardening of process.                           */
3038             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
3039                                         *   bit for A/D hard macro to hardening of process.                           */
3040         } ADEXTSTR_b;
3041     };
3042 
3043     union
3044     {
3045         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
3046 
3047         struct
3048         {
3049             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
3050             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
3051                                            *   amplifier test.Refreshing the pressure switch that opens
3052                                            *   for the DAC output voltage charge period when the amplifier
3053                                            *   of the S&H circuit is tested only for the channel is set.                 */
3054             uint16_t            : 1;
3055             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
3056                                            *   bit.                                                                      */
3057             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
3058                                            *   bit                                                                       */
3059             uint16_t                 : 1;
3060             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
3061                                            *   module Details are described to the bit explanation.                      */
3062             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
3063                                            *   bit explanation.                                                          */
3064         } ADTSTRA_b;
3065     };
3066 
3067     union
3068     {
3069         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
3070 
3071         struct
3072         {
3073             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
3074                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
3075             uint16_t : 1;
3076         } ADTSTRB_b;
3077     };
3078 
3079     union
3080     {
3081         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
3082 
3083         struct
3084         {
3085             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
3086                                          *   analog module.                                                            */
3087             uint16_t               : 4;
3088             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
3089             uint16_t               : 3;
3090         } ADTSTRC_b;
3091     };
3092 
3093     union
3094     {
3095         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
3096 
3097         struct
3098         {
3099             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
3100                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
3101             uint16_t : 15;
3102         } ADTSTRD_b;
3103     };
3104 
3105     union
3106     {
3107         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
3108 
3109         struct
3110         {
3111             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
3112             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
3113             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
3114             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
3115             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
3116             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
3117             uint16_t              : 10;
3118         } ADSWTSTR0_b;
3119     };
3120 
3121     union
3122     {
3123         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
3124 
3125         struct
3126         {
3127             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
3128             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
3129             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
3130             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
3131             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
3132             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
3133             uint16_t              : 10;
3134         } ADSWTSTR1_b;
3135     };
3136 
3137     union
3138     {
3139         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
3140 
3141         struct
3142         {
3143             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
3144                                           *   (ANEX0 switch)                                                            */
3145             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
3146                                           *   (ANEX1 switch).                                                           */
3147             uint16_t                : 2;
3148             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
3149             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
3150             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
3151             uint16_t                : 1;
3152             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
3153             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
3154             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
3155             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
3156             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
3157             uint16_t                : 3;
3158         } ADSWTSTR2_b;
3159     };
3160     __IM uint16_t RESERVED4;
3161 
3162     union
3163     {
3164         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
3165 
3166         struct
3167         {
3168             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
3169             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
3170             uint8_t              : 3;
3171         } ADDISCR_b;
3172     };
3173 
3174     union
3175     {
3176         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
3177 
3178         struct
3179         {
3180             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
3181                                         *   the pressure switch in A/D analog module is set.                          */
3182             uint8_t               : 1;
3183             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
3184             uint8_t               : 1;
3185         } ADSWCR_b;
3186     };
3187 
3188     union
3189     {
3190         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
3191 
3192         struct
3193         {
3194             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
3195                                         *   Select                                                                    */
3196             uint8_t : 7;
3197         } ADSHMSR_b;
3198     };
3199 
3200     union
3201     {
3202         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
3203 
3204         struct
3205         {
3206             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
3207             uint8_t            : 6;
3208         } ADICR_b;
3209     };
3210 
3211     union
3212     {
3213         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
3214 
3215         struct
3216         {
3217             uint8_t             : 1;
3218             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
3219             uint8_t             : 6;
3220         } ADACSR_b;
3221     };
3222     __IM uint8_t RESERVED5;
3223 
3224     union
3225     {
3226         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
3227 
3228         struct
3229         {
3230             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
3231                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
3232                                          *   set to 01b (group scan mode). If the bits are set to any
3233                                          *   other values, proper operation is not guaranteed.                         */
3234             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
3235                                          *   when PGS = 0.)                                                            */
3236             uint16_t               : 6;
3237             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
3238             uint16_t               : 6;
3239             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
3240                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
3241                                          *   has been set to 1, single scan is performed continuously
3242                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
3243         } ADGSPCR_b;
3244     };
3245 
3246     union
3247     {
3248         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
3249                                         *                  Scan)                                                      */
3250 
3251         struct
3252         {
3253             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
3254             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
3255         } ADGSCS_b;
3256     };
3257 
3258     union
3259     {
3260         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
3261 
3262         struct
3263         {
3264             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
3265                                           *   the result of A/D conversion in response to the respective
3266                                           *   triggers during extended operation in double trigger mode.                */
3267         } ADDBLDRA_b;
3268     };
3269 
3270     union
3271     {
3272         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
3273 
3274         struct
3275         {
3276             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
3277                                           *   the result of A/D conversion in response to the respective
3278                                           *   triggers during extended operation in double trigger mode.                */
3279         } ADDBLDRB_b;
3280     };
3281 
3282     union
3283     {
3284         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
3285 
3286         struct
3287         {
3288             uint8_t             : 7;
3289             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
3290         } ADSER_b;
3291     };
3292     __IM uint8_t RESERVED6;
3293 
3294     union
3295     {
3296         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
3297                                         *                  Control Register                                           */
3298 
3299         struct
3300         {
3301             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
3302             uint8_t             : 2;
3303             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
3304             uint8_t             : 2;
3305             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
3306         } ADHVREFCNT_b;
3307     };
3308     __IM uint8_t RESERVED7;
3309 
3310     union
3311     {
3312         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
3313                                         *                  Register                                                   */
3314 
3315         struct
3316         {
3317             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
3318                                         *   result.This bit is valid when both window A operation and
3319                                         *   window B operation are enabled.                                           */
3320             uint8_t              : 3;
3321             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
3322             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
3323             uint8_t              : 2;
3324         } ADWINMON_b;
3325     };
3326     __IM uint8_t  RESERVED8;
3327     __IM uint16_t RESERVED9;
3328 
3329     union
3330     {
3331         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
3332 
3333         struct
3334         {
3335             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
3336                                         *   are valid when both window A and window B are enabled (CMPAE
3337                                         *   = 1 and CMPBE = 1).                                                       */
3338             uint16_t              : 7;
3339             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
3340             uint16_t              : 1;
3341             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
3342             uint16_t              : 1;
3343             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
3344             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
3345             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
3346         } ADCMPCR_b;
3347     };
3348 
3349     union
3350     {
3351         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
3352                                         *                  Select Register                                            */
3353 
3354         struct
3355         {
3356             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
3357             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
3358             uint8_t              : 6;
3359         } ADCMPANSER_b;
3360     };
3361 
3362     union
3363     {
3364         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
3365                                         *                  Comparison Condition Setting Register                      */
3366 
3367         struct
3368         {
3369             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
3370                                         *   Condition Select                                                          */
3371             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
3372                                         *   Select                                                                    */
3373             uint8_t : 6;
3374         } ADCMPLER_b;
3375     };
3376 
3377     union
3378     {
3379         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
3380                                           *                  Register                                                   */
3381 
3382         struct
3383         {
3384             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
3385             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
3386             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
3387             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
3388             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
3389             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
3390             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
3391             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
3392             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
3393             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
3394             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
3395             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
3396             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
3397             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
3398             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
3399             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
3400         } ADCMPANSR_b[2];
3401     };
3402 
3403     union
3404     {
3405         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
3406                                            *                  Setting Register                                           */
3407 
3408         struct
3409         {
3410             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
3411             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
3412             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
3413             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
3414             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
3415             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
3416             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
3417             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
3418             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
3419             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
3420             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
3421             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
3422             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
3423             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
3424             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
3425             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
3426         } ADCMPLR_b[2];
3427     };
3428 
3429     union
3430     {
3431         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
3432                                            *                  Setting Register                                           */
3433 
3434         struct
3435         {
3436             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
3437                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
3438                                            *   level of window A.                                                        */
3439         } ADCMPDR0_b;
3440     };
3441 
3442     union
3443     {
3444         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
3445                                            *                  Setting Register                                           */
3446 
3447         struct
3448         {
3449             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
3450                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
3451                                            *   level of window A..                                                       */
3452         } ADCMPDR1_b;
3453     };
3454 
3455     union
3456     {
3457         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
3458                                             *                  Register                                                   */
3459 
3460         struct
3461         {
3462             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
3463             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
3464             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
3465             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
3466             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
3467             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
3468             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
3469             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
3470             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
3471             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
3472             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
3473             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
3474             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
3475             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
3476             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
3477             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
3478         } ADCMPSR_b[2];
3479     };
3480 
3481     union
3482     {
3483         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
3484                                          *                  Channel Status Register                                    */
3485 
3486         struct
3487         {
3488             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
3489                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3490                                          *   this bit indicates the temperature sensor output comparison
3491                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3492                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3493                                          *   time.                                                                     */
3494             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
3495                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3496                                          *   this bit indicates the temperature sensor output comparison
3497                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3498                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3499                                          *   time.                                                                     */
3500             uint8_t : 6;
3501         } ADCMPSER_b;
3502     };
3503     __IM uint8_t RESERVED10;
3504 
3505     union
3506     {
3507         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
3508                                         *                  Register                                                   */
3509 
3510         struct
3511         {
3512             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
3513                                         *   compares it on the condition of compare window B is selected.             */
3514             uint8_t             : 1;
3515             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
3516         } ADCMPBNSR_b;
3517     };
3518     __IM uint8_t RESERVED11;
3519 
3520     union
3521     {
3522         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
3523                                            *                  Setting Register                                           */
3524 
3525         struct
3526         {
3527             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
3528                                            *   used to set the lower level of the window B.                              */
3529         } ADWINLLB_b;
3530     };
3531 
3532     union
3533     {
3534         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
3535                                            *                  Setting Register                                           */
3536 
3537         struct
3538         {
3539             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
3540                                            *   used to set the higher level of the window B.                             */
3541         } ADWINULB_b;
3542     };
3543 
3544     union
3545     {
3546         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
3547 
3548         struct
3549         {
3550             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
3551                                         *   the comparative result of CH (AN000-AN027, temperature
3552                                         *   sensor, and internal reference voltage) made the object
3553                                         *   of window B relation condition.                                           */
3554             uint8_t : 7;
3555         } ADCMPBSR_b;
3556     };
3557     __IM uint8_t  RESERVED12;
3558     __IM uint16_t RESERVED13;
3559 
3560     union
3561     {
3562         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
3563 
3564         struct
3565         {
3566             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3567                                         *   registers that sequentially store all A/D converted values.
3568                                         *   The automatic clear function is not applied to these registers.           */
3569         } ADBUF0_b;
3570     };
3571 
3572     union
3573     {
3574         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
3575 
3576         struct
3577         {
3578             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3579                                         *   registers that sequentially store all A/D converted values.
3580                                         *   The automatic clear function is not applied to these registers.           */
3581         } ADBUF1_b;
3582     };
3583 
3584     union
3585     {
3586         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
3587 
3588         struct
3589         {
3590             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3591                                         *   registers that sequentially store all A/D converted values.
3592                                         *   The automatic clear function is not applied to these registers.           */
3593         } ADBUF2_b;
3594     };
3595 
3596     union
3597     {
3598         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
3599 
3600         struct
3601         {
3602             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3603                                         *   registers that sequentially store all A/D converted values.
3604                                         *   The automatic clear function is not applied to these registers.           */
3605         } ADBUF3_b;
3606     };
3607 
3608     union
3609     {
3610         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
3611 
3612         struct
3613         {
3614             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3615                                         *   registers that sequentially store all A/D converted values.
3616                                         *   The automatic clear function is not applied to these registers.           */
3617         } ADBUF4_b;
3618     };
3619 
3620     union
3621     {
3622         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
3623 
3624         struct
3625         {
3626             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3627                                         *   registers that sequentially store all A/D converted values.
3628                                         *   The automatic clear function is not applied to these registers.           */
3629         } ADBUF5_b;
3630     };
3631 
3632     union
3633     {
3634         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
3635 
3636         struct
3637         {
3638             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3639                                         *   registers that sequentially store all A/D converted values.
3640                                         *   The automatic clear function is not applied to these registers.           */
3641         } ADBUF6_b;
3642     };
3643 
3644     union
3645     {
3646         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
3647 
3648         struct
3649         {
3650             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3651                                         *   registers that sequentially store all A/D converted values.
3652                                         *   The automatic clear function is not applied to these registers.           */
3653         } ADBUF7_b;
3654     };
3655 
3656     union
3657     {
3658         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
3659 
3660         struct
3661         {
3662             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3663                                         *   registers that sequentially store all A/D converted values.
3664                                         *   The automatic clear function is not applied to these registers.           */
3665         } ADBUF8_b;
3666     };
3667 
3668     union
3669     {
3670         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
3671 
3672         struct
3673         {
3674             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3675                                         *   registers that sequentially store all A/D converted values.
3676                                         *   The automatic clear function is not applied to these registers.           */
3677         } ADBUF9_b;
3678     };
3679 
3680     union
3681     {
3682         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
3683 
3684         struct
3685         {
3686             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3687                                         *   registers that sequentially store all A/D converted values.
3688                                         *   The automatic clear function is not applied to these registers.           */
3689         } ADBUF10_b;
3690     };
3691 
3692     union
3693     {
3694         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
3695 
3696         struct
3697         {
3698             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3699                                         *   registers that sequentially store all A/D converted values.
3700                                         *   The automatic clear function is not applied to these registers.           */
3701         } ADBUF11_b;
3702     };
3703 
3704     union
3705     {
3706         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
3707 
3708         struct
3709         {
3710             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3711                                         *   registers that sequentially store all A/D converted values.
3712                                         *   The automatic clear function is not applied to these registers.           */
3713         } ADBUF12_b;
3714     };
3715 
3716     union
3717     {
3718         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
3719 
3720         struct
3721         {
3722             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3723                                         *   registers that sequentially store all A/D converted values.
3724                                         *   The automatic clear function is not applied to these registers.           */
3725         } ADBUF13_b;
3726     };
3727 
3728     union
3729     {
3730         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
3731 
3732         struct
3733         {
3734             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3735                                         *   registers that sequentially store all A/D converted values.
3736                                         *   The automatic clear function is not applied to these registers.           */
3737         } ADBUF14_b;
3738     };
3739 
3740     union
3741     {
3742         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
3743 
3744         struct
3745         {
3746             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3747                                         *   registers that sequentially store all A/D converted values.
3748                                         *   The automatic clear function is not applied to these registers.           */
3749         } ADBUF15_b;
3750     };
3751 
3752     union
3753     {
3754         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
3755 
3756         struct
3757         {
3758             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
3759             uint8_t             : 7;
3760         } ADBUFEN_b;
3761     };
3762     __IM uint8_t RESERVED14;
3763 
3764     union
3765     {
3766         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
3767 
3768         struct
3769         {
3770             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
3771                                         *   data buffer to which the next A/D converted data is transferred.          */
3772             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
3773             uint8_t             : 3;
3774         } ADBUFPTR_b;
3775     };
3776     __IM uint8_t  RESERVED15;
3777     __IM uint32_t RESERVED16[2];
3778     __IM uint8_t  RESERVED17;
3779 
3780     union
3781     {
3782         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
3783 
3784         struct
3785         {
3786             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
3787         } ADSSTRL_b;
3788     };
3789 
3790     union
3791     {
3792         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
3793 
3794         struct
3795         {
3796             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
3797         } ADSSTRT_b;
3798     };
3799 
3800     union
3801     {
3802         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
3803 
3804         struct
3805         {
3806             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
3807         } ADSSTRO_b;
3808     };
3809 
3810     union
3811     {
3812         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
3813 
3814         struct
3815         {
3816             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
3817         } ADSSTR_b[16];
3818     };
3819 
3820     union
3821     {
3822         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
3823 
3824         struct
3825         {
3826             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
3827             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
3828             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
3829             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
3830             uint16_t             : 12;
3831         } ADANIM_b;
3832     };
3833 
3834     union
3835     {
3836         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
3837 
3838         struct
3839         {
3840             uint8_t              : 6;
3841             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
3842             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
3843         } ADCALEXE_b;
3844     };
3845     __IM uint8_t RESERVED18;
3846 
3847     union
3848     {
3849         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
3850                                           *                  Register                                                   */
3851 
3852         struct
3853         {
3854             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
3855             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
3856             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
3857             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
3858             uint8_t                 : 2;
3859             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
3860         } VREFAMPCNT_b;
3861     };
3862     __IM uint8_t  RESERVED19;
3863     __IM uint16_t RESERVED20;
3864 
3865     union
3866     {
3867         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
3868 
3869         struct
3870         {
3871             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
3872         } ADRD_b;
3873     };
3874 
3875     union
3876     {
3877         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
3878 
3879         struct
3880         {
3881             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
3882             uint8_t             : 6;
3883         } ADRST_b;
3884     };
3885     __IM uint8_t  RESERVED21;
3886     __IM uint32_t RESERVED22[41];
3887 
3888     union
3889     {
3890         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
3891 
3892         struct
3893         {
3894             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
3895             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
3896             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
3897             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
3898             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
3899             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
3900             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
3901             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
3902             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
3903             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
3904             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
3905             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
3906             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
3907             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
3908             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
3909             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
3910         } ADPGACR_b;
3911     };
3912 
3913     union
3914     {
3915         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
3916                                           *                  Register 0                                                 */
3917 
3918         struct
3919         {
3920             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
3921                                           *   b) when the shingle end is input and each PGA P000 is set.
3922                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
3923                                           *   sets the gain magnification when the differential motion
3924                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
3925             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
3926                                           *   b) when the shingle end is input and each PGA P001 is set.
3927                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
3928                                           *   sets the gain magnification when the differential motion
3929                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
3930             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
3931                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
3932                                           *   each PGA P002 is set. When the differential motion is input,
3933                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
3934                                           *   the differential motion is input by the combination with
3935                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
3936             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
3937                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
3938                                           *   each PGA P003 is set. When the differential motion is input,
3939                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
3940                                           *   the differential motion is input by the combination with
3941                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
3942         } ADPGAGS0_b;
3943     };
3944     __IM uint32_t RESERVED23[3];
3945 
3946     union
3947     {
3948         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
3949                                          *                  Input Control Register                                     */
3950 
3951         struct
3952         {
3953             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
3954                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
3955             uint16_t               : 1;
3956             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
3957             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
3958                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
3959             uint16_t               : 1;
3960             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
3961             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
3962                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
3963             uint16_t               : 1;
3964             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
3965             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
3966                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
3967             uint16_t               : 1;
3968             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
3969         } ADPGADCR0_b;
3970     };
3971     __IM uint16_t RESERVED24;
3972 
3973     union
3974     {
3975         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
3976                                         *                  Input Bias Select Register 0                               */
3977 
3978         struct
3979         {
3980             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
3981                                         *   SelectNOTE: This bit selects the input bias voltage value
3982                                         *   when differential inputs are used.                                        */
3983             uint8_t : 7;
3984         } ADPGADBS0_b;
3985     };
3986 
3987     union
3988     {
3989         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
3990                                         *                  Input Bias Select Register 1                               */
3991 
3992         struct
3993         {
3994             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
3995                                         *   This bit selects the input bias voltage value when differential
3996                                         *   inputs are used.                                                          */
3997             uint8_t : 7;
3998         } ADPGADBS1_b;
3999     };
4000     __IM uint16_t RESERVED25;
4001     __IM uint32_t RESERVED26[10];
4002 
4003     union
4004     {
4005         __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
4006 
4007         struct
4008         {
4009             __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
4010             uint32_t              : 13;
4011             __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
4012             uint32_t              : 12;
4013         } ADREFMON_b;
4014     };
4015 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
4016 
4017 /* =========================================================================================================================== */
4018 /* ================                                          R_PSCU                                           ================ */
4019 /* =========================================================================================================================== */
4020 
4021 /**
4022  * @brief Peripheral Security Control Unit (R_PSCU)
4023  */
4024 
4025 typedef struct                         /*!< (@ 0x40204000) R_PSCU Structure                                           */
4026 {
4027     __IM uint32_t RESERVED;
4028 
4029     union
4030     {
4031         __IOM uint32_t PSARB;          /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
4032 
4033         struct
4034         {
4035             uint32_t               : 4;
4036             __IOM uint32_t PSARB4  : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution                           */
4037             uint32_t               : 3;
4038             __IOM uint32_t PSARB8  : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution                           */
4039             __IOM uint32_t PSARB9  : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution                           */
4040             uint32_t               : 1;
4041             __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution     */
4042             __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution     */
4043             uint32_t               : 2;
4044             __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution                    */
4045             __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution                      */
4046             uint32_t               : 1;
4047             __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution               */
4048             __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution               */
4049             uint32_t               : 2;
4050             __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution            */
4051             uint32_t               : 4;
4052             __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution            */
4053             __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution            */
4054             __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution            */
4055             __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution            */
4056             __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution            */
4057         } PSARB_b;
4058     };
4059 
4060     union
4061     {
4062         __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
4063 
4064         struct
4065         {
4066             __IOM uint32_t PSARC0 : 1;  /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security
4067                                          *   Attribution                                                               */
4068             __IOM uint32_t PSARC1 : 1;  /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution            */
4069             uint32_t              : 5;
4070             __IOM uint32_t PSARC7 : 1;  /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security
4071                                          *   Attribution                                                               */
4072             __IOM uint32_t PSARC8 : 1;  /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security
4073                                          *   Attribution                                                               */
4074             uint32_t               : 2;
4075             __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution                    */
4076             __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution                    */
4077             __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution                      */
4078             uint32_t               : 1;
4079             __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution               */
4080             __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution                                         */
4081             uint32_t               : 9;
4082             __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security
4083                                          *   Attribution                                                               */
4084             __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security
4085                                          *   Attribution                                                               */
4086             uint32_t               : 3;
4087             __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution                                        */
4088         } PSARC_b;
4089     };
4090 
4091     union
4092     {
4093         __IOM uint32_t PSARD;          /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
4094 
4095         struct
4096         {
4097             uint32_t               : 4;
4098             __IOM uint32_t PSARD4  : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution          */
4099             __IOM uint32_t PSARD5  : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution          */
4100             uint32_t               : 5;
4101             __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution          */
4102             __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution          */
4103             __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution          */
4104             __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution          */
4105             __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution                      */
4106             __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution                      */
4107             uint32_t               : 3;
4108             __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution                        */
4109             uint32_t               : 1;
4110             __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution                          */
4111             uint32_t               : 4;
4112             __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution              */
4113             __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution              */
4114             uint32_t               : 3;
4115         } PSARD_b;
4116     };
4117 
4118     union
4119     {
4120         __IOM uint32_t PSARE;          /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
4121 
4122         struct
4123         {
4124             uint32_t               : 1;
4125             __IOM uint32_t PSARE1  : 1; /*!< [1..1] WDT0 Security Attribution                                          */
4126             __IOM uint32_t PSARE2  : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution                    */
4127             __IOM uint32_t PSARE3  : 1; /*!< [3..3] Real Time Clock Security Attribution                               */
4128             uint32_t               : 4;
4129             __IOM uint32_t PSARE8  : 1; /*!< [8..8] ULPT1 Security Attribution                                         */
4130             __IOM uint32_t PSARE9  : 1; /*!< [9..9] ULPT0 Security Attribution                                         */
4131             uint32_t               : 8;
4132             __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution                 */
4133             __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution                 */
4134             __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution                 */
4135             __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution                 */
4136             __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution                  */
4137             __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution                  */
4138             __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution                  */
4139             __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution                  */
4140             __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution                  */
4141             __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution                  */
4142             __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution                  */
4143             __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution                  */
4144             __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution                  */
4145             __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution                  */
4146         } PSARE_b;
4147     };
4148 
4149     union
4150     {
4151         __IOM uint32_t MSSAR;           /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
4152 
4153         struct
4154         {
4155             __IOM uint32_t MSSAR0  : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution                              */
4156             __IOM uint32_t MSSAR1  : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution                              */
4157             uint32_t               : 9;
4158             __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution                                       */
4159             uint32_t               : 1;
4160             __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution                                       */
4161             uint32_t               : 1;
4162             __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution                      */
4163             uint32_t               : 6;
4164             __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution                       */
4165             uint32_t               : 8;
4166             __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution                              */
4167         } MSSAR_b;
4168     };
4169     __IM uint32_t RESERVED1;
4170 
4171     union
4172     {
4173         __IOM uint32_t PPARB;          /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B                */
4174 
4175         struct
4176         {
4177             uint32_t               : 4;
4178             __IOM uint32_t PPARB4  : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution                          */
4179             uint32_t               : 3;
4180             __IOM uint32_t PPARB8  : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution                          */
4181             __IOM uint32_t PPARB9  : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution                          */
4182             uint32_t               : 1;
4183             __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution    */
4184             __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution    */
4185             uint32_t               : 2;
4186             __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution                   */
4187             __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution                     */
4188             uint32_t               : 1;
4189             __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution              */
4190             __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution              */
4191             uint32_t               : 2;
4192             __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution           */
4193             uint32_t               : 4;
4194             __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution           */
4195             __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution           */
4196             __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution           */
4197             __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution           */
4198             __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution           */
4199         } PPARB_b;
4200     };
4201 
4202     union
4203     {
4204         __IOM uint32_t PPARC;           /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C                */
4205 
4206         struct
4207         {
4208             __IOM uint32_t PPARC0 : 1;  /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege
4209                                          *   Attribution                                                               */
4210             __IOM uint32_t PPARC1 : 1;  /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution           */
4211             uint32_t              : 5;
4212             __IOM uint32_t PPARC7 : 1;  /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege
4213                                          *   Attribution                                                               */
4214             __IOM uint32_t PPARC8 : 1;  /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege
4215                                          *   Attribution                                                               */
4216             uint32_t               : 2;
4217             __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution                */
4218             __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution                */
4219             __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution                     */
4220             uint32_t               : 1;
4221             __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution              */
4222             __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution                                        */
4223             uint32_t               : 9;
4224             __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege
4225                                          *   Attribution                                                               */
4226             __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege
4227                                          *   Attribution                                                               */
4228             uint32_t               : 3;
4229             __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution                                       */
4230         } PPARC_b;
4231     };
4232 
4233     union
4234     {
4235         __IOM uint32_t PPARD;          /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D                */
4236 
4237         struct
4238         {
4239             uint32_t               : 4;
4240             __IOM uint32_t PPARD4  : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution         */
4241             __IOM uint32_t PPARD5  : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution         */
4242             uint32_t               : 5;
4243             __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution         */
4244             __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution         */
4245             __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution         */
4246             __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution         */
4247             __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution                     */
4248             __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution                     */
4249             uint32_t               : 3;
4250             __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution                       */
4251             uint32_t               : 1;
4252             __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution                         */
4253             uint32_t               : 4;
4254             __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution             */
4255             __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution             */
4256             uint32_t               : 3;
4257         } PPARD_b;
4258     };
4259 
4260     union
4261     {
4262         __IOM uint32_t PPARE;          /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E                */
4263 
4264         struct
4265         {
4266             uint32_t               : 1;
4267             __IOM uint32_t PPARE1  : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution                              */
4268             __IOM uint32_t PPARE2  : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution                   */
4269             __IOM uint32_t PPARE3  : 1; /*!< [3..3] Real Time Clock Privilege Attribution                              */
4270             uint32_t               : 4;
4271             __IOM uint32_t PPARE8  : 1; /*!< [8..8] ULPT1 Privilege Attribution                                        */
4272             __IOM uint32_t PPARE9  : 1; /*!< [9..9] ULPT0 Privilege Attribution                                        */
4273             uint32_t               : 8;
4274             __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution                */
4275             __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution                */
4276             __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution                */
4277             __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution                */
4278             __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution                 */
4279             __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution                 */
4280             __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution                 */
4281             __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution                 */
4282             __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution                 */
4283             __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution                 */
4284             __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution                 */
4285             __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution                 */
4286             __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution                 */
4287             __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution                 */
4288         } PPARE_b;
4289     };
4290 
4291     union
4292     {
4293         __IOM uint32_t MSPAR;          /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register                 */
4294 
4295         struct
4296         {
4297             uint32_t               : 31;
4298             __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution                             */
4299         } MSPAR_b;
4300     };
4301 
4302     union
4303     {
4304         __IM uint32_t CFSAMONA;        /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register
4305                                         *                  A                                                          */
4306 
4307         struct
4308         {
4309             uint32_t           : 15;
4310             __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area                                           */
4311             uint32_t           : 8;
4312         } CFSAMONA_b;
4313     };
4314 
4315     union
4316     {
4317         __IM uint32_t DFSAMON;         /*!< (@ 0x00000034) Data Flash Security Attribution Monitor Register           */
4318 
4319         struct
4320         {
4321             uint32_t          : 10;
4322             __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
4323             uint32_t          : 16;
4324         } DFSAMON_b;
4325     };
4326 
4327     union
4328     {
4329         __IM uint32_t DLMMON;          /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register         */
4330 
4331         struct
4332         {
4333             __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
4334             uint32_t             : 28;
4335         } DLMMON_b;
4336     };
4337 } R_PSCU_Type;                         /*!< Size = 60 (0x3c)                                                          */
4338 
4339 /* =========================================================================================================================== */
4340 /* ================                                           R_BUS                                           ================ */
4341 /* =========================================================================================================================== */
4342 
4343 /**
4344  * @brief Bus Interface (R_BUS)
4345  */
4346 
4347 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
4348 {
4349     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
4350     __IM uint32_t        RESERVED[480];
4351     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
4352 
4353     union
4354     {
4355         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
4356 
4357         struct
4358         {
4359             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
4360             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
4361             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
4362             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
4363             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
4364             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
4365             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
4366             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
4367             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
4368             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
4369             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4370             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4371             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4372             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4373             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4374             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
4375         } CSRECEN_b;
4376     };
4377     __IM uint16_t          RESERVED1;
4378     __IM uint32_t          RESERVED2[223];
4379     __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
4380     __IM uint32_t          RESERVED3[235];
4381 
4382     union
4383     {
4384         __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
4385         __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
4386     };
4387     __IM uint32_t RESERVED4[58];
4388 
4389     union
4390     {
4391         union
4392         {
4393             __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */
4394 
4395             struct
4396             {
4397                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
4398                 uint32_t            : 31;
4399             } BUSMABT_b;
4400         };
4401         __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
4402     };
4403     __IM uint32_t RESERVED5[46];
4404 
4405     union
4406     {
4407         __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
4408         __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
4409     };
4410     __IM uint32_t RESERVED6[33];
4411 
4412     union
4413     {
4414         __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */
4415 
4416         struct
4417         {
4418             __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
4419             uint32_t                : 2;
4420             __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
4421             uint32_t                : 12;
4422             __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
4423             uint32_t                : 15;
4424         } BUSDIVBYP_b;
4425     };
4426     __IM uint32_t            RESERVED7[319];
4427     __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
4428     __IM uint32_t            RESERVED8[16];
4429 
4430     union
4431     {
4432         __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
4433         __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
4434                                               *                  and Read/Write Status registers.                           */
4435     };
4436     __IM uint32_t RESERVED9[28];
4437 
4438     union
4439     {
4440         __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
4441         __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
4442     };
4443     __IM uint32_t           RESERVED10[16];
4444     __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
4445     __IM uint32_t           RESERVED11[5];
4446     __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
4447 } R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */
4448 
4449 /* =========================================================================================================================== */
4450 /* ================                                           R_CAC                                           ================ */
4451 /* =========================================================================================================================== */
4452 
4453 /**
4454  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
4455  */
4456 
4457 typedef struct                         /*!< (@ 0x40202400) R_CAC Structure                                            */
4458 {
4459     union
4460     {
4461         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
4462 
4463         struct
4464         {
4465             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
4466             uint8_t            : 7;
4467         } CACR0_b;
4468     };
4469 
4470     union
4471     {
4472         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
4473 
4474         struct
4475         {
4476             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
4477             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
4478             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
4479             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
4480         } CACR1_b;
4481     };
4482 
4483     union
4484     {
4485         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
4486 
4487         struct
4488         {
4489             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
4490             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
4491             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
4492                                         *   Select                                                                    */
4493             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
4494         } CACR2_b;
4495     };
4496 
4497     union
4498     {
4499         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
4500 
4501         struct
4502         {
4503             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
4504             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
4505             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
4506             uint8_t              : 1;
4507             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
4508             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
4509             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
4510             uint8_t              : 1;
4511         } CAICR_b;
4512     };
4513 
4514     union
4515     {
4516         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
4517 
4518         struct
4519         {
4520             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
4521             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
4522             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
4523             uint8_t            : 5;
4524         } CASTR_b;
4525     };
4526     __IM uint8_t RESERVED;
4527 
4528     union
4529     {
4530         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
4531 
4532         struct
4533         {
4534             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
4535                                          *   the upper-limit value of the frequency.                                   */
4536         } CAULVR_b;
4537     };
4538 
4539     union
4540     {
4541         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
4542 
4543         struct
4544         {
4545             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
4546                                          *   the lower-limit value of the frequency.                                   */
4547         } CALLVR_b;
4548     };
4549 
4550     union
4551     {
4552         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
4553 
4554         struct
4555         {
4556             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
4557                                          *   the counter value at the time a valid reference signal
4558                                          *   edge is input                                                             */
4559         } CACNTBR_b;
4560     };
4561 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
4562 
4563 /* =========================================================================================================================== */
4564 /* ================                                         R_CANFD0                                          ================ */
4565 /* =========================================================================================================================== */
4566 
4567 /**
4568  * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
4569  */
4570 
4571 typedef struct                         /*!< (@ 0x40380000) R_CANFD0 Structure                                         */
4572 {
4573     __IOM R_CANFD_CFDC_Type CFDC[1];   /*!< (@ 0x00000000) Channel Control/Status                                     */
4574     __IM uint32_t           RESERVED;
4575 
4576     union
4577     {
4578         __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */
4579 
4580         struct
4581         {
4582             __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
4583             __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
4584             __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
4585             __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
4586             __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
4587             __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
4588             uint32_t             : 2;
4589             __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
4590             __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
4591             uint32_t             : 3;
4592             __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
4593         } CFDGCFG_b;
4594     };
4595 
4596     union
4597     {
4598         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */
4599 
4600         struct
4601         {
4602             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
4603             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
4604             uint32_t               : 5;
4605             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
4606             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
4607             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
4608             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
4609             uint32_t               : 4;
4610             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
4611             uint32_t               : 15;
4612         } CFDGCTR_b;
4613     };
4614 
4615     union
4616     {
4617         __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */
4618 
4619         struct
4620         {
4621             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
4622             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
4623             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
4624             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
4625             uint32_t               : 28;
4626         } CFDGSTS_b;
4627     };
4628 
4629     union
4630     {
4631         __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */
4632 
4633         struct
4634         {
4635             __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
4636             __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
4637             __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
4638             __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
4639             uint32_t             : 12;
4640             __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
4641             uint32_t             : 15;
4642         } CFDGERFL_b;
4643     };
4644 
4645     union
4646     {
4647         __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */
4648 
4649         struct
4650         {
4651             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
4652             uint32_t         : 16;
4653         } CFDGTSC_b;
4654     };
4655 
4656     union
4657     {
4658         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */
4659 
4660         struct
4661         {
4662             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
4663             uint32_t              : 4;
4664             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
4665             uint32_t              : 23;
4666         } CFDGAFLECTR_b;
4667     };
4668 
4669     union
4670     {
4671         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
4672                                         *                  0                                                          */
4673 
4674         struct
4675         {
4676             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
4677             uint32_t            : 7;
4678             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
4679             uint32_t            : 7;
4680         } CFDGAFLCFG0_b;
4681     };
4682 
4683     union
4684     {
4685         __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */
4686 
4687         struct
4688         {
4689             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
4690             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
4691             uint32_t             : 21;
4692         } CFDRMNB_b;
4693     };
4694 
4695     union
4696     {
4697         __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */
4698 
4699         struct
4700         {
4701             __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
4702         } CFDRMND0_b;
4703     };
4704 
4705     union
4706     {
4707         __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
4708                                         *                  Register                                                   */
4709 
4710         struct
4711         {
4712             __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
4713         } CFDRMIEC_b;
4714     };
4715 
4716     union
4717     {
4718         __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */
4719 
4720         struct
4721         {
4722             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
4723             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
4724             uint32_t              : 2;
4725             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
4726             uint32_t              : 1;
4727             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
4728             uint32_t              : 1;
4729             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
4730             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
4731             uint32_t              : 16;
4732         } CFDRFCC_b[2];
4733     };
4734 
4735     union
4736     {
4737         __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */
4738 
4739         struct
4740         {
4741             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
4742             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
4743             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
4744             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
4745             uint32_t             : 4;
4746             __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
4747             uint32_t             : 16;
4748         } CFDRFSTS_b[2];
4749     };
4750 
4751     union
4752     {
4753         __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */
4754 
4755         struct
4756         {
4757             __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
4758             uint32_t           : 24;
4759         } CFDRFPCTR_b[2];
4760     };
4761 
4762     union
4763     {
4764         __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */
4765 
4766         struct
4767         {
4768             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
4769             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
4770             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
4771             uint32_t              : 1;
4772             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
4773             uint32_t              : 1;
4774             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
4775             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
4776             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
4777             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
4778             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
4779             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
4780             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
4781             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
4782         } CFDCFCC_b[1];
4783     };
4784 
4785     union
4786     {
4787         __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */
4788 
4789         struct
4790         {
4791             __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
4792             __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
4793             __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
4794             __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
4795             __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
4796             uint32_t              : 3;
4797             __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
4798             uint32_t              : 16;
4799         } CFDCFSTS_b[1];
4800     };
4801 
4802     union
4803     {
4804         __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */
4805 
4806         struct
4807         {
4808             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
4809             uint32_t           : 24;
4810         } CFDCFPCTR_b[1];
4811     };
4812 
4813     union
4814     {
4815         __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */
4816 
4817         struct
4818         {
4819             __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
4820             uint32_t             : 6;
4821             __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
4822             uint32_t             : 23;
4823         } CFDFESTS_b;
4824     };
4825 
4826     union
4827     {
4828         __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */
4829 
4830         struct
4831         {
4832             __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
4833             uint32_t             : 6;
4834             __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
4835             uint32_t             : 23;
4836         } CFDFFSTS_b;
4837     };
4838 
4839     union
4840     {
4841         __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */
4842 
4843         struct
4844         {
4845             __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
4846             uint32_t             : 6;
4847             __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
4848             uint32_t             : 23;
4849         } CFDFMSTS_b;
4850     };
4851 
4852     union
4853     {
4854         __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */
4855 
4856         struct
4857         {
4858             __IM uint32_t RFXIF : 1;   /*!< [0..0] RX FIFO[x] Interrupt Flag Status                                   */
4859             uint32_t            : 31;
4860         } CFDRFISTS_b;
4861     };
4862 
4863     union
4864     {
4865         __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */
4866 
4867         struct
4868         {
4869             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
4870             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
4871             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
4872             uint8_t             : 5;
4873         } CFDTMC_b[4];
4874     };
4875 
4876     union
4877     {
4878         __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */
4879 
4880         struct
4881         {
4882             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
4883             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
4884             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
4885             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
4886             uint8_t              : 3;
4887         } CFDTMSTS_b[4];
4888     };
4889 
4890     union
4891     {
4892         __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
4893                                             *                  Register                                                   */
4894 
4895         struct
4896         {
4897             __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
4898             uint32_t                  : 28;
4899         } CFDTMTRSTS_b[1];
4900     };
4901 
4902     union
4903     {
4904         __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
4905                                              *                  Status Register                                            */
4906 
4907         struct
4908         {
4909             __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
4910             uint32_t                   : 28;
4911         } CFDTMTARSTS_b[1];
4912     };
4913 
4914     union
4915     {
4916         __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
4917                                             *                  Register                                                   */
4918 
4919         struct
4920         {
4921             __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
4922             uint32_t                  : 28;
4923         } CFDTMTCSTS_b[1];
4924     };
4925 
4926     union
4927     {
4928         __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */
4929 
4930         struct
4931         {
4932             __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
4933             uint32_t                  : 28;
4934         } CFDTMTASTS_b[1];
4935     };
4936 
4937     union
4938     {
4939         __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
4940                                         *                  Register                                                   */
4941 
4942         struct
4943         {
4944             __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
4945             uint32_t             : 28;
4946         } CFDTMIEC_b[1];
4947     };
4948 
4949     union
4950     {
4951         __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */
4952 
4953         struct
4954         {
4955             __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
4956             uint32_t               : 4;
4957             __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4958             uint32_t               : 1;
4959             __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4960             __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
4961             uint32_t               : 22;
4962         } CFDTXQCC0_b[1];
4963     };
4964 
4965     union
4966     {
4967         __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */
4968 
4969         struct
4970         {
4971             __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
4972             __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
4973             __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4974             uint32_t               : 5;
4975             __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
4976             uint32_t               : 18;
4977         } CFDTXQSTS0_b[1];
4978     };
4979 
4980     union
4981     {
4982         __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */
4983 
4984         struct
4985         {
4986             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4987             uint32_t            : 24;
4988         } CFDTXQPCTR0_b[1];
4989     };
4990 
4991     union
4992     {
4993         __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */
4994 
4995         struct
4996         {
4997             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
4998             uint32_t              : 7;
4999             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
5000             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
5001             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
5002             uint32_t              : 21;
5003         } CFDTHLCC_b[1];
5004     };
5005 
5006     union
5007     {
5008         __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */
5009 
5010         struct
5011         {
5012             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
5013             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
5014             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
5015             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
5016             uint32_t              : 4;
5017             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
5018             uint32_t              : 18;
5019         } CFDTHLSTS_b[1];
5020     };
5021 
5022     union
5023     {
5024         __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */
5025 
5026         struct
5027         {
5028             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
5029             uint32_t            : 24;
5030         } CFDTHLPCTR_b[1];
5031     };
5032 
5033     union
5034     {
5035         __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */
5036 
5037         struct
5038         {
5039             __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
5040             __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
5041             __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
5042             __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
5043             __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
5044             uint32_t             : 27;
5045         } CFDGTINTSTS0_b;
5046     };
5047 
5048     union
5049     {
5050         __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */
5051 
5052         struct
5053         {
5054             uint32_t             : 16;
5055             __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
5056             uint32_t             : 6;
5057         } CFDGTSTCFG_b;
5058     };
5059 
5060     union
5061     {
5062         __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */
5063 
5064         struct
5065         {
5066             uint32_t            : 2;
5067             __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
5068             uint32_t            : 29;
5069         } CFDGTSTCTR_b;
5070     };
5071 
5072     union
5073     {
5074         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */
5075 
5076         struct
5077         {
5078             __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
5079             uint32_t              : 7;
5080             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
5081             uint32_t              : 22;
5082         } CFDGFDCFG_b;
5083     };
5084     __IM uint32_t RESERVED1;
5085 
5086     union
5087     {
5088         __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */
5089 
5090         struct
5091         {
5092             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
5093             uint32_t           : 16;
5094         } CFDGLOCKK_b;
5095     };
5096     __IM uint32_t RESERVED2;
5097 
5098     union
5099     {
5100         __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */
5101 
5102         struct
5103         {
5104             __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
5105             uint32_t           : 27;
5106         } CFDGAFLIGNENT_b;
5107     };
5108 
5109     union
5110     {
5111         __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */
5112 
5113         struct
5114         {
5115             __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
5116             uint32_t            : 7;
5117             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
5118             uint32_t            : 16;
5119         } CFDGAFLIGNCTR_b;
5120     };
5121 
5122     union
5123     {
5124         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */
5125 
5126         struct
5127         {
5128             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
5129             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
5130             uint32_t               : 6;
5131             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
5132             uint32_t               : 23;
5133         } CFDCDTCT_b;
5134     };
5135 
5136     union
5137     {
5138         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */
5139 
5140         struct
5141         {
5142             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
5143             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
5144             uint32_t                : 6;
5145             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
5146                                           *   0                                                                         */
5147             uint32_t : 23;
5148         } CFDCDTSTS_b;
5149     };
5150     __IM uint32_t RESERVED3[2];
5151 
5152     union
5153     {
5154         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */
5155 
5156         struct
5157         {
5158             __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
5159             uint32_t            : 7;
5160             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
5161             uint32_t            : 16;
5162         } CFDGRSTC_b;
5163     };
5164     __IM uint32_t              RESERVED4[9];
5165     __IOM R_CANFD_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
5166     __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
5167     __IM uint32_t              RESERVED5[24];
5168 
5169     union
5170     {
5171         __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00000280) RAM Test Page Access Registers                             */
5172 
5173         struct
5174         {
5175             __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
5176         } CFDRPGACC_b[64];
5177     };
5178     __IM uint32_t             RESERVED6[104];
5179     __IOM R_CANFD_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
5180     __IOM R_CANFD_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
5181     __IOM R_CANFD_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
5182     __IM uint32_t             RESERVED7[3];
5183     __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
5184     __IM uint32_t             RESERVED8[118];
5185     __IOM R_CANFD_CFDRM_Type  CFDRM[4];  /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
5186 } R_CANFD_Type;                          /*!< Size = 6432 (0x1920)                                                      */
5187 
5188 /* =========================================================================================================================== */
5189 /* ================                                           R_CRC                                           ================ */
5190 /* =========================================================================================================================== */
5191 
5192 /**
5193  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
5194  */
5195 
5196 typedef struct                         /*!< (@ 0x40310000) R_CRC Structure                                            */
5197 {
5198     union
5199     {
5200         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
5201 
5202         struct
5203         {
5204             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
5205             uint8_t              : 3;
5206             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
5207             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
5208         } CRCCR0_b;
5209     };
5210 
5211     union
5212     {
5213         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
5214 
5215         struct
5216         {
5217             uint8_t              : 6;
5218             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
5219             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
5220         } CRCCR1_b;
5221     };
5222     __IM uint16_t RESERVED;
5223 
5224     union
5225     {
5226         union
5227         {
5228             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
5229 
5230             struct
5231             {
5232                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
5233             } CRCDIR_b;
5234         };
5235 
5236         union
5237         {
5238             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
5239 
5240             struct
5241             {
5242                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
5243                                               *   )                                                                         */
5244             } CRCDIR_BY_b;
5245         };
5246     };
5247 
5248     union
5249     {
5250         union
5251         {
5252             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
5253 
5254             struct
5255             {
5256                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
5257             } CRCDOR_b;
5258         };
5259 
5260         union
5261         {
5262             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
5263 
5264             struct
5265             {
5266                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
5267                                                 *   )                                                                         */
5268             } CRCDOR_HA_b;
5269         };
5270 
5271         union
5272         {
5273             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
5274 
5275             struct
5276             {
5277                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
5278             } CRCDOR_BY_b;
5279         };
5280     };
5281 
5282     union
5283     {
5284         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
5285 
5286         struct
5287         {
5288             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
5289             uint16_t             : 2;
5290         } CRCSAR_b;
5291     };
5292     __IM uint16_t RESERVED1;
5293 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
5294 
5295 /* =========================================================================================================================== */
5296 /* ================                                           R_DAC                                           ================ */
5297 /* =========================================================================================================================== */
5298 
5299 /**
5300  * @brief D/A Converter (R_DAC)
5301  */
5302 
5303 typedef struct                         /*!< (@ 0x40333000) R_DAC Structure                                            */
5304 {
5305     union
5306     {
5307         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
5308 
5309         struct
5310         {
5311             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
5312                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
5313                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
5314                                         *   format.                                                                   */
5315         } DADR_b[2];
5316     };
5317 
5318     union
5319     {
5320         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
5321 
5322         struct
5323         {
5324             uint8_t             : 5;
5325             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
5326             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
5327             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
5328         } DACR_b;
5329     };
5330 
5331     union
5332     {
5333         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
5334 
5335         struct
5336         {
5337             uint8_t             : 7;
5338             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
5339         } DADPR_b;
5340     };
5341 
5342     union
5343     {
5344         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
5345 
5346         struct
5347         {
5348             uint8_t              : 7;
5349             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
5350         } DAADSCR_b;
5351     };
5352 
5353     union
5354     {
5355         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
5356 
5357         struct
5358         {
5359             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
5360             uint8_t           : 5;
5361         } DAVREFCR_b;
5362     };
5363 
5364     union
5365     {
5366         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
5367 
5368         struct
5369         {
5370             uint8_t              : 6;
5371             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
5372             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
5373         } DAAMPCR_b;
5374     };
5375 
5376     union
5377     {
5378         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
5379 
5380         struct
5381         {
5382             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
5383             uint8_t              : 7;
5384         } DAPC_b;
5385     };
5386     __IM uint16_t RESERVED[9];
5387 
5388     union
5389     {
5390         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
5391 
5392         struct
5393         {
5394             uint8_t              : 6;
5395             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
5396                                         *   to wait for stabilization of the output amplifier of D/A
5397                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
5398                                         *   but the conversion result D/A is not output from channel
5399                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
5400                                         *   stops, and the D/A conversion result of channel 0 is output
5401                                         *   through the output amplifier.                                             */
5402             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
5403                                         *   to wait for stabilization of the output amplifier of D/A
5404                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
5405                                         *   but the conversion result D/A is not output from channel
5406                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
5407                                         *   stops, and the D/A conversion result of channel 1 is output
5408                                         *   through the output amplifier.                                             */
5409         } DAASWCR_b;
5410     };
5411     __IM uint8_t  RESERVED1;
5412     __IM uint16_t RESERVED2[2129];
5413 
5414     union
5415     {
5416         __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
5417 
5418         struct
5419         {
5420             __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
5421                                          *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
5422                                          *   select unit 0 as the target synchronous unit for the MCU.
5423                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5424                                          *   conversions, select the target unit in this register in
5425                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5426                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5427                                          *   is set to 0.                                                              */
5428             __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
5429                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
5430                                          *   select unit 1 as the target synchronous unit for the MCU.
5431                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5432                                          *   conversions, select the target unit in this register in
5433                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5434                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5435                                          *   is set to 0.                                                              */
5436             uint8_t : 6;
5437         } DAADUSR_b;
5438     };
5439     __IM uint8_t  RESERVED3;
5440     __IM uint16_t RESERVED4;
5441 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
5442 
5443 /* =========================================================================================================================== */
5444 /* ================                                          R_DEBUG                                          ================ */
5445 /* =========================================================================================================================== */
5446 
5447 /**
5448  * @brief Debug Function (R_DEBUG)
5449  */
5450 
5451 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
5452 {
5453     union
5454     {
5455         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
5456 
5457         struct
5458         {
5459             uint32_t                   : 28;
5460             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
5461             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
5462             uint32_t                   : 2;
5463         } DBGSTR_b;
5464     };
5465     __IM uint32_t RESERVED[3];
5466 
5467     union
5468     {
5469         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
5470 
5471         struct
5472         {
5473             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
5474             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
5475             uint32_t                     : 12;
5476             __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
5477             __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
5478             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
5479             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
5480             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
5481             uint32_t                     : 5;
5482             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
5483             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
5484             uint32_t                     : 5;
5485             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
5486         } DBGSTOPCR_b;
5487     };
5488     __IM uint32_t RESERVED1[123];
5489 
5490     union
5491     {
5492         __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */
5493 
5494         struct
5495         {
5496             __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
5497             __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
5498             uint32_t              : 6;
5499             __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
5500             uint32_t              : 21;
5501         } FSBLSTAT_b;
5502     };
5503 } R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */
5504 
5505 /* =========================================================================================================================== */
5506 /* ================                                           R_DMA                                           ================ */
5507 /* =========================================================================================================================== */
5508 
5509 /**
5510  * @brief DMA Controller Common (R_DMA)
5511  */
5512 
5513 typedef struct                         /*!< (@ 0x4000A800) R_DMA Structure                                            */
5514 {
5515     union
5516     {
5517         __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
5518 
5519         struct
5520         {
5521             __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
5522             uint8_t            : 7;
5523         } DMAST_b;
5524     };
5525     __IM uint8_t  RESERVED;
5526     __IM uint16_t RESERVED1;
5527     __IM uint32_t RESERVED2[15];
5528 
5529     union
5530     {
5531         __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
5532 
5533         struct
5534         {
5535             __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
5536             uint32_t               : 5;
5537             __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
5538             uint32_t               : 7;
5539             __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
5540             uint32_t               : 15;
5541         } DMECHR_b;
5542     };
5543     __IM uint32_t RESERVED3[15];
5544 
5545     union
5546     {
5547         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
5548 
5549         struct
5550         {
5551             __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
5552             uint32_t            : 7;
5553             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
5554                                         *   IR flag is prohibited.                                                    */
5555             uint32_t : 15;
5556         } DELSR_b[8];
5557     };
5558 } R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
5559 
5560 /* =========================================================================================================================== */
5561 /* ================                                          R_DMAC0                                          ================ */
5562 /* =========================================================================================================================== */
5563 
5564 /**
5565  * @brief DMA Controller (R_DMAC0)
5566  */
5567 
5568 typedef struct                         /*!< (@ 0x4000A000) R_DMAC0 Structure                                          */
5569 {
5570     union
5571     {
5572         __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
5573 
5574         struct
5575         {
5576             __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
5577         } DMSAR_b;
5578     };
5579 
5580     union
5581     {
5582         __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
5583 
5584         struct
5585         {
5586             __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
5587         } DMDAR_b;
5588     };
5589 
5590     union
5591     {
5592         __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
5593 
5594         struct
5595         {
5596             __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
5597             __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
5598             uint32_t              : 6;
5599         } DMCRA_b;
5600     };
5601 
5602     union
5603     {
5604         __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
5605 
5606         struct
5607         {
5608             __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
5609                                          *   transfer counter.                                                         */
5610             __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
5611                                          *   repeat transfer operations.                                               */
5612         } DMCRB_b;
5613     };
5614 
5615     union
5616     {
5617         __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
5618 
5619         struct
5620         {
5621             __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
5622             uint16_t            : 6;
5623             __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
5624             __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
5625             uint16_t            : 1;
5626             __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
5627             __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
5628         } DMTMD_b;
5629     };
5630     __IM uint8_t RESERVED;
5631 
5632     union
5633     {
5634         __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
5635 
5636         struct
5637         {
5638             __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
5639                                         *   Enable                                                                    */
5640             __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
5641                                         *   Enable                                                                    */
5642             __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
5643             __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
5644             __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
5645             uint8_t             : 3;
5646         } DMINT_b;
5647     };
5648 
5649     union
5650     {
5651         __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
5652 
5653         struct
5654         {
5655             __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
5656                                         *   extended repeat area on the destination address. For details
5657                                         *   on the settings.                                                          */
5658             __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
5659             __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
5660             __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
5661                                         *   repeat area on the source address. For details on the settings.           */
5662             __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
5663             __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
5664         } DMAMD_b;
5665     };
5666     __IM uint16_t RESERVED1;
5667 
5668     union
5669     {
5670         __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
5671 
5672         struct
5673         {
5674             __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
5675                                         *   as the address update mode for transfer source or destination.            */
5676         } DMOFR_b;
5677     };
5678 
5679     union
5680     {
5681         __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
5682 
5683         struct
5684         {
5685             __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
5686             uint8_t           : 7;
5687         } DMCNT_b;
5688     };
5689 
5690     union
5691     {
5692         __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
5693 
5694         struct
5695         {
5696             __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
5697             uint8_t             : 3;
5698             __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
5699             uint8_t             : 3;
5700         } DMREQ_b;
5701     };
5702 
5703     union
5704     {
5705         __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
5706 
5707         struct
5708         {
5709             __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
5710             uint8_t            : 3;
5711             __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
5712             uint8_t            : 2;
5713             __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
5714         } DMSTS_b;
5715     };
5716     __IM uint8_t   RESERVED2;
5717     __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
5718     __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
5719 
5720     union
5721     {
5722         __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
5723 
5724         struct
5725         {
5726             __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
5727                                          *   mode                                                                      */
5728             __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
5729                                          *   mode                                                                      */
5730         } DMSBS_b;
5731     };
5732 
5733     union
5734     {
5735         __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
5736 
5737         struct
5738         {
5739             __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
5740                                          *   mode                                                                      */
5741             __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
5742                                          *   mode                                                                      */
5743         } DMDBS_b;
5744     };
5745 
5746     union
5747     {
5748         __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
5749 
5750         struct
5751         {
5752             __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
5753             uint8_t           : 7;
5754         } DMBWR_b;
5755     };
5756     __IM uint8_t  RESERVED3;
5757     __IM uint16_t RESERVED4;
5758 } R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
5759 
5760 /* =========================================================================================================================== */
5761 /* ================                                           R_DOC                                           ================ */
5762 /* =========================================================================================================================== */
5763 
5764 /**
5765  * @brief Data Operation Circuit (R_DOC)
5766  */
5767 
5768 typedef struct                         /*!< (@ 0x40311000) R_DOC Structure                                            */
5769 {
5770     union
5771     {
5772         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
5773 
5774         struct
5775         {
5776             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
5777             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
5778             uint8_t               : 2;
5779             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
5780             __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
5781             uint8_t               : 1;
5782         } DOCR_b;
5783     };
5784     __IM uint8_t RESERVED;
5785 
5786     union
5787     {
5788         __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
5789 
5790         struct
5791         {
5792             __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
5793                                         *   use in the operations are stored.                                         */
5794         } DODIR_b;
5795     };
5796 
5797     union
5798     {
5799         __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
5800 
5801         struct
5802         {
5803             __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
5804                                         *   in data comparison mode. This register also stores the
5805                                         *   results of operations in data addition and data subtraction
5806                                         *   modes.                                                                    */
5807         } DODSR_b;
5808     };
5809 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
5810 
5811 /* =========================================================================================================================== */
5812 /* ================                                           R_DTC                                           ================ */
5813 /* =========================================================================================================================== */
5814 
5815 /**
5816  * @brief Data Transfer Controller (R_DTC)
5817  */
5818 
5819 typedef struct                         /*!< (@ 0x4000AC00) R_DTC Structure                                            */
5820 {
5821     union
5822     {
5823         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
5824 
5825         struct
5826         {
5827             uint8_t           : 4;
5828             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
5829             uint8_t           : 3;
5830         } DTCCR_b;
5831     };
5832     __IM uint8_t  RESERVED;
5833     __IM uint16_t RESERVED1;
5834 
5835     union
5836     {
5837         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
5838 
5839         struct
5840         {
5841             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
5842                                          *   in the lower-order 10 bits. These bits are fixed to 0.                    */
5843         } DTCVBR_b;
5844     };
5845     __IM uint32_t RESERVED2;
5846 
5847     union
5848     {
5849         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
5850 
5851         struct
5852         {
5853             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
5854             uint8_t             : 7;
5855         } DTCST_b;
5856     };
5857     __IM uint8_t RESERVED3;
5858 
5859     union
5860     {
5861         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
5862 
5863         struct
5864         {
5865             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
5866                                         *   the vector number for the activating source when DTC transfer
5867                                         *   is in progress.The value is only valid if DTC transfer
5868                                         *   is in progress (the value of the ACT flag is 1)                           */
5869             uint16_t          : 7;
5870             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
5871         } DTCSTS_b;
5872     };
5873 
5874     union
5875     {
5876         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
5877 
5878         struct
5879         {
5880             uint8_t            : 4;
5881             __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
5882             uint8_t            : 3;
5883         } DTCCR_SEC_b;
5884     };
5885     __IM uint8_t   RESERVED4;
5886     __IM uint16_t  RESERVED5;
5887     __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
5888     __IM uint32_t  RESERVED6[2];
5889 
5890     union
5891     {
5892         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
5893 
5894         struct
5895         {
5896             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
5897             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
5898             uint32_t              : 7;
5899             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
5900             uint32_t              : 15;
5901         } DTEVR_b;
5902     };
5903 } R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
5904 
5905 /* =========================================================================================================================== */
5906 /* ================                                           R_ELC                                           ================ */
5907 /* =========================================================================================================================== */
5908 
5909 /**
5910  * @brief Event Link Controller (R_ELC)
5911  */
5912 
5913 typedef struct                         /*!< (@ 0x40201000) R_ELC Structure                                            */
5914 {
5915     union
5916     {
5917         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
5918 
5919         struct
5920         {
5921             uint8_t             : 7;
5922             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
5923         } ELCR_b;
5924     };
5925     __IM uint8_t            RESERVED;
5926     __IM uint16_t           RESERVED1;
5927     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register              */
5928     __IM uint32_t           RESERVED2[6];
5929     __IOM R_ELC_ELSR_Type   ELSR[31];  /*!< (@ 0x00000020) Event Link Setting Register [0..30]                        */
5930     __IM uint32_t           RESERVED3[17];
5931 
5932     union
5933     {
5934         __IOM uint32_t ELCSARA;         /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register
5935                                          *                  A                                                          */
5936 
5937         struct
5938         {
5939             __IOM uint32_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
5940             __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
5941                                          *   Attribution                                                               */
5942             __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
5943                                          *   Attribution                                                               */
5944             uint32_t : 29;
5945         } ELCSARA_b;
5946     };
5947 
5948     union
5949     {
5950         __IOM uint32_t ELCSARB;        /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register
5951                                         *                  B                                                          */
5952 
5953         struct
5954         {
5955             __IOM uint32_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution                 */
5956             __IOM uint32_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution                 */
5957             __IOM uint32_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution                 */
5958             __IOM uint32_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution                 */
5959             __IOM uint32_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution                 */
5960             __IOM uint32_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution                 */
5961             __IOM uint32_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution                 */
5962             __IOM uint32_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution                 */
5963             __IOM uint32_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution                 */
5964             __IOM uint32_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution                 */
5965             __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution              */
5966             __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution              */
5967             __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution              */
5968             __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution              */
5969             __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution              */
5970             __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution              */
5971             __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution              */
5972             __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution              */
5973             uint32_t              : 12;
5974             __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution              */
5975             uint32_t              : 1;
5976         } ELCSARB_b;
5977     };
5978     __IM uint32_t RESERVED4[2];
5979 
5980     union
5981     {
5982         __IOM uint32_t ELCPARA;         /*!< (@ 0x000000F0) Event Link Controller Priviledge Attribution
5983                                          *                  Register A                                                 */
5984 
5985         struct
5986         {
5987             __IOM uint32_t ELCR    : 1; /*!< [0..0] Event Link Controller Register Priviledge Attribution              */
5988             __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Priviledge
5989                                          *   Attribution                                                               */
5990             __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Priviledge
5991                                          *   Attribution                                                               */
5992             uint32_t : 29;
5993         } ELCPARA_b;
5994     };
5995 
5996     union
5997     {
5998         __IOM uint32_t ELCPARB;        /*!< (@ 0x000000F4) Event Link Controller Priviledge Attribution
5999                                         *                  Register B                                                 */
6000 
6001         struct
6002         {
6003             __IOM uint32_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0 Priviledge Attribution               */
6004             __IOM uint32_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1 Priviledge Attribution               */
6005             __IOM uint32_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2 Priviledge Attribution               */
6006             __IOM uint32_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3 Priviledge Attribution               */
6007             __IOM uint32_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4 Priviledge Attribution               */
6008             __IOM uint32_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5 Priviledge Attribution               */
6009             __IOM uint32_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6 Priviledge Attribution               */
6010             __IOM uint32_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7 Priviledge Attribution               */
6011             __IOM uint32_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8 Priviledge Attribution               */
6012             __IOM uint32_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9 Priviledge Attribution               */
6013             __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Priviledge Attribution            */
6014             __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Priviledge Attribution            */
6015             __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Priviledge Attribution            */
6016             __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Priviledge Attribution            */
6017             __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Priviledge Attribution            */
6018             __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Priviledge Attribution            */
6019             __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Priviledge Attribution            */
6020             __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Priviledge Attribution            */
6021             uint32_t              : 12;
6022             __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Priviledge Attribution            */
6023             uint32_t              : 1;
6024         } ELCPARB_b;
6025     };
6026 } R_ELC_Type;                          /*!< Size = 248 (0xf8)                                                         */
6027 
6028 /* =========================================================================================================================== */
6029 /* ================                                         R_ETHERC0                                         ================ */
6030 /* =========================================================================================================================== */
6031 
6032 /**
6033  * @brief Ethernet MAC Controller (R_ETHERC0)
6034  */
6035 
6036 typedef struct                         /*!< (@ 0x40354100) R_ETHERC0 Structure                                        */
6037 {
6038     union
6039     {
6040         __IOM uint32_t ECMR;           /*!< (@ 0x00000000) ETHERC Mode Register                                       */
6041 
6042         struct
6043         {
6044             __IOM uint32_t PRM   : 1;  /*!< [0..0] Promiscuous Mode                                                   */
6045             __IOM uint32_t DM    : 1;  /*!< [1..1] Duplex Mode                                                        */
6046             __IOM uint32_t RTM   : 1;  /*!< [2..2] Bit Rate                                                           */
6047             __IOM uint32_t ILB   : 1;  /*!< [3..3] Internal Loopback Mode                                             */
6048             uint32_t             : 1;
6049             __IOM uint32_t TE    : 1;  /*!< [5..5] Transmission Enable                                                */
6050             __IOM uint32_t RE    : 1;  /*!< [6..6] Reception Enable                                                   */
6051             uint32_t             : 2;
6052             __IOM uint32_t MPDE  : 1;  /*!< [9..9] Magic Packet Detection Enable                                      */
6053             uint32_t             : 2;
6054             __IOM uint32_t PRCEF : 1;  /*!< [12..12] CRC Error Frame Receive Mode                                     */
6055             uint32_t             : 3;
6056             __IOM uint32_t TXF   : 1;  /*!< [16..16] Transmit Flow Control Operating Mode                             */
6057             __IOM uint32_t RXF   : 1;  /*!< [17..17] Receive Flow Control Operating Mode                              */
6058             __IOM uint32_t PFR   : 1;  /*!< [18..18] PAUSE Frame Receive Mode                                         */
6059             __IOM uint32_t ZPF   : 1;  /*!< [19..19] 0 Time PAUSE Frame Enable                                        */
6060             __IOM uint32_t TPC   : 1;  /*!< [20..20] PAUSE Frame Transmit                                             */
6061             uint32_t             : 11;
6062         } ECMR_b;
6063     };
6064     __IM uint32_t RESERVED;
6065 
6066     union
6067     {
6068         __IOM uint32_t RFLR;           /*!< (@ 0x00000008) Receive Frame Maximum Length Register                      */
6069 
6070         struct
6071         {
6072             __IOM uint32_t RFL : 12;   /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
6073                                         *   maximum frame length. The minimum value that can be set
6074                                         *   is 1,518 bytes, and the maximum value that can be set is
6075                                         *   2,048 bytes. Values that are less than 1,518 bytes are
6076                                         *   regarded as 1,518 bytes, and values larger than 2,048 bytes
6077                                         *   are regarded as 2,048 bytes.                                              */
6078             uint32_t : 20;
6079         } RFLR_b;
6080     };
6081     __IM uint32_t RESERVED1;
6082 
6083     union
6084     {
6085         __IOM uint32_t ECSR;           /*!< (@ 0x00000010) ETHERC Status Register                                     */
6086 
6087         struct
6088         {
6089             __IOM uint32_t ICD   : 1;  /*!< [0..0] False Carrier Detect Flag                                          */
6090             __IOM uint32_t MPD   : 1;  /*!< [1..1] Magic Packet Detect Flag                                           */
6091             __IOM uint32_t LCHNG : 1;  /*!< [2..2] LCHNG Link Signal Change Flag                                      */
6092             uint32_t             : 1;
6093             __IOM uint32_t PSRTO : 1;  /*!< [4..4] PAUSE Frame Retransmit Over Flag                                   */
6094             __IOM uint32_t BFR   : 1;  /*!< [5..5] Continuous Broadcast Frame Reception Flag                          */
6095             uint32_t             : 26;
6096         } ECSR_b;
6097     };
6098     __IM uint32_t RESERVED2;
6099 
6100     union
6101     {
6102         __IOM uint32_t ECSIPR;          /*!< (@ 0x00000018) ETHERC Interrupt Enable Register                           */
6103 
6104         struct
6105         {
6106             __IOM uint32_t ICDIP   : 1; /*!< [0..0] False Carrier Detect Interrupt Enable                              */
6107             __IOM uint32_t MPDIP   : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable                               */
6108             __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable                                */
6109             uint32_t               : 1;
6110             __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable                       */
6111             __IOM uint32_t BFSIPR  : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable              */
6112             uint32_t               : 26;
6113         } ECSIPR_b;
6114     };
6115     __IM uint32_t RESERVED3;
6116 
6117     union
6118     {
6119         __IOM uint32_t PIR;            /*!< (@ 0x00000020) PHY Interface Register                                     */
6120 
6121         struct
6122         {
6123             __IOM uint32_t MDC : 1;    /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
6124                                         *   from the ETn_MDC pin to supply the management data clock
6125                                         *   to the MII or RMII.                                                       */
6126             __IOM uint32_t MMD : 1;    /*!< [1..1] MII/RMII Management Mode                                           */
6127             __IOM uint32_t MDO : 1;    /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
6128                                         *   from the ETn_MDIO pin when the MMD bit is 1 (write). The
6129                                         *   value is not output when the MMD bit is 0 (read).                         */
6130             __IM uint32_t MDI : 1;     /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
6131                                         *   of the ETn_MDIO pin. The write value should be 0.                         */
6132             uint32_t : 28;
6133         } PIR_b;
6134     };
6135     __IM uint32_t RESERVED4;
6136 
6137     union
6138     {
6139         __IM uint32_t PSR;             /*!< (@ 0x00000028) PHY Status Register                                        */
6140 
6141         struct
6142         {
6143             __IM uint32_t LMON : 1;    /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
6144                                         *   by connecting the link signal output from the PHY-LSI to
6145                                         *   the ETn_LINKSTA pin. For details on the polarity, refer
6146                                         *   to the specifications of the connected PHY-LSI.                           */
6147             uint32_t : 31;
6148         } PSR_b;
6149     };
6150     __IM uint32_t RESERVED5[5];
6151 
6152     union
6153     {
6154         __IOM uint32_t RDMLR;          /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
6155                                         *                  Setting Register                                           */
6156 
6157         struct
6158         {
6159             __IOM uint32_t RMD : 20;   /*!< [19..0] Random Number Generation Counter                                  */
6160             uint32_t           : 12;
6161         } RDMLR_b;
6162     };
6163     __IM uint32_t RESERVED6[3];
6164 
6165     union
6166     {
6167         __IOM uint32_t IPGR;           /*!< (@ 0x00000050) IPG Register                                               */
6168 
6169         struct
6170         {
6171             __IOM uint32_t IPG : 5;    /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)'       */
6172             uint32_t           : 27;
6173         } IPGR_b;
6174     };
6175 
6176     union
6177     {
6178         __IOM uint32_t APR;            /*!< (@ 0x00000054) Automatic PAUSE Frame Register                             */
6179 
6180         struct
6181         {
6182             __IOM uint32_t AP : 16;    /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
6183                                         *   of the pause_time parameter for a PAUSE frame that is automatically
6184                                         *   transmitted. Transmission is not performed until the set
6185                                         *   value multiplied by 512 bit time has elapsed.                             */
6186             uint32_t : 16;
6187         } APR_b;
6188     };
6189 
6190     union
6191     {
6192         __OM uint32_t MPR;             /*!< (@ 0x00000058) Manual PAUSE Frame Register                                */
6193 
6194         struct
6195         {
6196             __OM uint32_t MP : 16;     /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
6197                                         *   the pause_time parameter for a PAUSE frame that is manually
6198                                         *   transmitted. Transmission is not performed until the set
6199                                         *   value multiplied by 512 bit time has elapsed. The read
6200                                         *   value is undefined.                                                       */
6201             uint32_t : 16;
6202         } MPR_b;
6203     };
6204     __IM uint32_t RESERVED7;
6205 
6206     union
6207     {
6208         __IM uint32_t RFCF;            /*!< (@ 0x00000060) Received PAUSE Frame Counter                               */
6209 
6210         struct
6211         {
6212             __IM uint32_t RPAUSE : 8;  /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames          */
6213             uint32_t             : 24;
6214         } RFCF_b;
6215     };
6216 
6217     union
6218     {
6219         __IOM uint32_t TPAUSER;         /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register              */
6220 
6221         struct
6222         {
6223             __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting                          */
6224             uint32_t              : 16;
6225         } TPAUSER_b;
6226     };
6227     __IM uint32_t TPAUSECR;             /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter                             */
6228 
6229     union
6230     {
6231         __IOM uint32_t BCFRR;           /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register             */
6232 
6233         struct
6234         {
6235             __IOM uint32_t BCF : 16;    /*!< [15..0] Broadcast Frame Continuous Receive Count Setting                  */
6236             uint32_t           : 16;
6237         } BCFRR_b;
6238     };
6239     __IM uint32_t RESERVED8[20];
6240 
6241     union
6242     {
6243         __IOM uint32_t MAHR;           /*!< (@ 0x000000C0) MAC Address Upper Bit Register                             */
6244 
6245         struct
6246         {
6247             __IOM uint32_t MAHR : 32;  /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
6248                                         *   the upper 32 bits (b47 to b16) of the 48-bit MAC address.                 */
6249         } MAHR_b;
6250     };
6251     __IM uint32_t RESERVED9;
6252 
6253     union
6254     {
6255         __IOM uint32_t MALR;           /*!< (@ 0x000000C8) MAC Address Lower Bit Register                             */
6256 
6257         struct
6258         {
6259             __IOM uint32_t MALR : 16;  /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
6260                                         *   the lower 16 bits of the 48-bit MAC address.                              */
6261             uint32_t : 16;
6262         } MALR_b;
6263     };
6264     __IM uint32_t RESERVED10;
6265 
6266     union
6267     {
6268         __IOM uint32_t TROCR;          /*!< (@ 0x000000D0) Transmit Retry Over Counter Register                       */
6269 
6270         struct
6271         {
6272             __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
6273                                         *   is a counter indicating the number of frames that fail
6274                                         *   to be retransmitted.                                                      */
6275         } TROCR_b;
6276     };
6277     __IOM uint32_t CDCR;               /*!< (@ 0x000000D4) Late Collision Detect Counter Register                     */
6278 
6279     union
6280     {
6281         __IOM uint32_t LCCR;           /*!< (@ 0x000000D8) Lost Carrier Counter Register                              */
6282 
6283         struct
6284         {
6285             __IOM uint32_t LCCR : 32;  /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
6286                                         *   counter indicating the number of times a loss of carrier
6287                                         *   is detected during frame transmission.                                    */
6288         } LCCR_b;
6289     };
6290 
6291     union
6292     {
6293         __IOM uint32_t CNDCR;          /*!< (@ 0x000000DC) Carrier Not Detect Counter Register                        */
6294 
6295         struct
6296         {
6297             __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
6298                                         *   is a counter indicating the number of times a carrier is
6299                                         *   not detected during preamble transmission.                                */
6300         } CNDCR_b;
6301     };
6302     __IM uint32_t RESERVED11;
6303 
6304     union
6305     {
6306         __IOM uint32_t CEFCR;          /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register                   */
6307 
6308         struct
6309         {
6310             __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
6311                                         *   is a counter indicating the number of received frames where
6312                                         *   a CRC error has been detected.                                            */
6313         } CEFCR_b;
6314     };
6315 
6316     union
6317     {
6318         __IOM uint32_t FRECR;          /*!< (@ 0x000000E8) Frame Receive Error Counter Register                       */
6319 
6320         struct
6321         {
6322             __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
6323                                         *   is a counter indicating the number of times a frame receive
6324                                         *   error has occurred.                                                       */
6325         } FRECR_b;
6326     };
6327 
6328     union
6329     {
6330         __IOM uint32_t TSFRCR;          /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register                   */
6331 
6332         struct
6333         {
6334             __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
6335                                          *   is a counter indicating the number of times a short frame
6336                                          *   that is shorter than 64 bytes has been received.                          */
6337         } TSFRCR_b;
6338     };
6339 
6340     union
6341     {
6342         __IOM uint32_t TLFRCR;          /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register                    */
6343 
6344         struct
6345         {
6346             __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
6347                                          *   is a counter indicating the number of times a long frame
6348                                          *   that is longer than the RFLR register value has been received.            */
6349         } TLFRCR_b;
6350     };
6351 
6352     union
6353     {
6354         __IOM uint32_t RFCR;           /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register            */
6355 
6356         struct
6357         {
6358             __IOM uint32_t RFCR : 32;  /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
6359                                         *   register is a counter indicating the number of times a
6360                                         *   frame has been received with the alignment error (frame
6361                                         *   is not an integral number of octets).                                     */
6362         } RFCR_b;
6363     };
6364 
6365     union
6366     {
6367         __IOM uint32_t MAFCR;          /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register           */
6368 
6369         struct
6370         {
6371             __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
6372                                         *   MAFCR register is a counter indicating the number of times
6373                                         *   a frame where the multicast address is set has been received.             */
6374         } MAFCR_b;
6375     };
6376 } R_ETHERC0_Type;                      /*!< Size = 252 (0xfc)                                                         */
6377 
6378 /* =========================================================================================================================== */
6379 /* ================                                      R_ETHERC_EDMAC                                       ================ */
6380 /* =========================================================================================================================== */
6381 
6382 /**
6383  * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
6384  */
6385 
6386 typedef struct                         /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure                                   */
6387 {
6388     union
6389     {
6390         __IOM uint32_t EDMR;           /*!< (@ 0x00000000) EDMAC Mode Register                                        */
6391 
6392         struct
6393         {
6394             __OM uint32_t SWR : 1;     /*!< [0..0] Software Reset                                                     */
6395             uint32_t          : 3;
6396             __IOM uint32_t DL : 2;     /*!< [5..4] Transmit/Receive DescriptorLength                                  */
6397             __IOM uint32_t DE : 1;     /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
6398                                         *   applies to data for the transmit/receive buffer. It does
6399                                         *   not apply to transmit/receive descriptors and registers.                  */
6400             uint32_t : 25;
6401         } EDMR_b;
6402     };
6403     __IM uint32_t RESERVED;
6404 
6405     union
6406     {
6407         __IOM uint32_t EDTRR;          /*!< (@ 0x00000008) EDMAC Transmit Request Register                            */
6408 
6409         struct
6410         {
6411             __OM uint32_t TR : 1;      /*!< [0..0] Transmit Request                                                   */
6412             uint32_t         : 31;
6413         } EDTRR_b;
6414     };
6415     __IM uint32_t RESERVED1;
6416 
6417     union
6418     {
6419         __IOM uint32_t EDRRR;          /*!< (@ 0x00000010) EDMAC Receive Request Register                             */
6420 
6421         struct
6422         {
6423             __IOM uint32_t RR : 1;     /*!< [0..0] Receive Request                                                    */
6424             uint32_t          : 31;
6425         } EDRRR_b;
6426     };
6427     __IM uint32_t RESERVED2;
6428 
6429     union
6430     {
6431         __IOM uint32_t TDLAR;          /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register            */
6432 
6433         struct
6434         {
6435             __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
6436                                         *   set. Set the start address according to the descriptor
6437                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
6438                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
6439                                         *   boundary: Lower 6 bits = 000000b                                          */
6440         } TDLAR_b;
6441     };
6442     __IM uint32_t RESERVED3;
6443 
6444     union
6445     {
6446         __IOM uint32_t RDLAR;          /*!< (@ 0x00000020) Receive Descriptor List Start Address Register             */
6447 
6448         struct
6449         {
6450             __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
6451                                         *   set. Set the start address according to the descriptor
6452                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
6453                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
6454                                         *   boundary: Lower 6 bits = 000000b                                          */
6455         } RDLAR_b;
6456     };
6457     __IM uint32_t RESERVED4;
6458 
6459     union
6460     {
6461         __IOM uint32_t EESR;           /*!< (@ 0x00000028) ETHERC/EDMAC Status Register                               */
6462 
6463         struct
6464         {
6465             __IOM uint32_t CERF : 1;   /*!< [0..0] CRC Error Flag                                                     */
6466             __IOM uint32_t PRE  : 1;   /*!< [1..1] PHY-LSI Receive Error Flag                                         */
6467             __IOM uint32_t RTSF : 1;   /*!< [2..2] Frame-Too-Short Error Flag                                         */
6468             __IOM uint32_t RTLF : 1;   /*!< [3..3] Frame-Too-Long Error Flag                                          */
6469             __IOM uint32_t RRF  : 1;   /*!< [4..4] Alignment Error Flag                                               */
6470             uint32_t            : 2;
6471             __IOM uint32_t RMAF : 1;   /*!< [7..7] Multicast Address Frame Receive Flag                               */
6472             __IOM uint32_t TRO  : 1;   /*!< [8..8] Transmit Retry Over Flag                                           */
6473             __IOM uint32_t CD   : 1;   /*!< [9..9] Late Collision Detect Flag                                         */
6474             __IOM uint32_t DLC  : 1;   /*!< [10..10] Loss of Carrier Detect Flag                                      */
6475             __IOM uint32_t CND  : 1;   /*!< [11..11] Carrier Not Detect Flag                                          */
6476             uint32_t            : 4;
6477             __IOM uint32_t RFOF : 1;   /*!< [16..16] Receive FIFO Overflow Flag                                       */
6478             __IOM uint32_t RDE  : 1;   /*!< [17..17] Receive Descriptor Empty Flag                                    */
6479             __IOM uint32_t FR   : 1;   /*!< [18..18] Frame Receive Flag                                               */
6480             __IOM uint32_t TFUF : 1;   /*!< [19..19] Transmit FIFO Underflow Flag                                     */
6481             __IOM uint32_t TDE  : 1;   /*!< [20..20] Transmit Descriptor Empty Flag                                   */
6482             __IOM uint32_t TC   : 1;   /*!< [21..21] Frame Transfer Complete Flag                                     */
6483             __IM uint32_t  ECI  : 1;   /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
6484                                         *   in the ETHERCn.ECSR register is cleared, the ECI flag is
6485                                         *   also cleared.                                                             */
6486             __IOM uint32_t ADE   : 1;  /*!< [23..23] Address Error Flag                                               */
6487             __IOM uint32_t RFCOF : 1;  /*!< [24..24] Receive Frame Counter Overflow Flag                              */
6488             __IOM uint32_t RABT  : 1;  /*!< [25..25] Receive Abort Detect Flag                                        */
6489             __IOM uint32_t TABT  : 1;  /*!< [26..26] Transmit Abort Detect Flag                                       */
6490             uint32_t             : 3;
6491             __IOM uint32_t TWB   : 1;  /*!< [30..30] Write-Back Complete Flag                                         */
6492             uint32_t             : 1;
6493         } EESR_b;
6494     };
6495     __IM uint32_t RESERVED5;
6496 
6497     union
6498     {
6499         __IOM uint32_t EESIPR;          /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register              */
6500 
6501         struct
6502         {
6503             __IOM uint32_t CERFIP  : 1; /*!< [0..0] CRC Error Interrupt Request Enable                                 */
6504             __IOM uint32_t PREIP   : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable                     */
6505             __IOM uint32_t RTSFIP  : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable                     */
6506             __IOM uint32_t RTLFIP  : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable                      */
6507             __IOM uint32_t RRFIP   : 1; /*!< [4..4] Alignment Error Interrupt Request Enable                           */
6508             uint32_t               : 2;
6509             __IOM uint32_t RMAFIP  : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable           */
6510             __IOM uint32_t TROIP   : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable                       */
6511             __IOM uint32_t CDIP    : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable                     */
6512             __IOM uint32_t DLCIP   : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable                  */
6513             __IOM uint32_t CNDIP   : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable                      */
6514             uint32_t               : 4;
6515             __IOM uint32_t RFOFIP  : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable                   */
6516             __IOM uint32_t RDEIP   : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable                */
6517             __IOM uint32_t FRIP    : 1; /*!< [18..18] Frame Receive Interrupt Request Enable                           */
6518             __IOM uint32_t TFUFIP  : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable                 */
6519             __IOM uint32_t TDEIP   : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable               */
6520             __IOM uint32_t TCIP    : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable                 */
6521             __IOM uint32_t ECIIP   : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable           */
6522             __IOM uint32_t ADEIP   : 1; /*!< [23..23] Address Error Interrupt Request Enable                           */
6523             __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable          */
6524             __IOM uint32_t RABTIP  : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable                    */
6525             __IOM uint32_t TABTIP  : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable                   */
6526             uint32_t               : 3;
6527             __IOM uint32_t TWBIP   : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable                     */
6528             uint32_t               : 1;
6529         } EESIPR_b;
6530     };
6531     __IM uint32_t RESERVED6;
6532 
6533     union
6534     {
6535         __IOM uint32_t TRSCER;         /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
6536                                         *                  Register                                                   */
6537 
6538         struct
6539         {
6540             uint32_t              : 4;
6541             __IOM uint32_t RRFCE  : 1; /*!< [4..4] RRF Flag Copy Enable                                               */
6542             uint32_t              : 2;
6543             __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable                                              */
6544             uint32_t              : 24;
6545         } TRSCER_b;
6546     };
6547     __IM uint32_t RESERVED7;
6548 
6549     union
6550     {
6551         __IOM uint32_t RMFCR;          /*!< (@ 0x00000040) Missed-Frame Counter Register                              */
6552 
6553         struct
6554         {
6555             __IOM uint32_t MFC : 16;   /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
6556                                         *   frames that are discarded and not transferred to the receive
6557                                         *   buffer during reception.                                                  */
6558             uint32_t : 16;
6559         } RMFCR_b;
6560     };
6561     __IM uint32_t RESERVED8;
6562 
6563     union
6564     {
6565         __IOM uint32_t TFTR;           /*!< (@ 0x00000048) Transmit FIFO Threshold Register                           */
6566 
6567         struct
6568         {
6569             __IOM uint32_t TFT : 11;   /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
6570                                         *   the set value multiplied by 4. Example: 00Dh: 52 bytes
6571                                         *   040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes                         */
6572             uint32_t : 21;
6573         } TFTR_b;
6574     };
6575     __IM uint32_t RESERVED9;
6576 
6577     union
6578     {
6579         __IOM uint32_t FDR;            /*!< (@ 0x00000050) Transmit FIFO Threshold Register                           */
6580 
6581         struct
6582         {
6583             __IOM uint32_t RFD : 5;    /*!< [4..0] Transmit FIFO Depth                                                */
6584             uint32_t           : 3;
6585             __IOM uint32_t TFD : 5;    /*!< [12..8] Receive FIFO Depth                                                */
6586             uint32_t           : 19;
6587         } FDR_b;
6588     };
6589     __IM uint32_t RESERVED10;
6590 
6591     union
6592     {
6593         __IOM uint32_t RMCR;           /*!< (@ 0x00000058) Receive Method Control Register                            */
6594 
6595         struct
6596         {
6597             __IOM uint32_t RNR : 1;    /*!< [0..0] Receive Request Reset                                              */
6598             uint32_t           : 31;
6599         } RMCR_b;
6600     };
6601     __IM uint32_t RESERVED11[2];
6602 
6603     union
6604     {
6605         __IOM uint32_t TFUCR;          /*!< (@ 0x00000064) Transmit FIFO Underflow Counter                            */
6606 
6607         struct
6608         {
6609             __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
6610                                         *   many times the transmit FIFO has underflowed. The counter
6611                                         *   stops when the counter value reaches FFFFh.                               */
6612             uint32_t : 16;
6613         } TFUCR_b;
6614     };
6615 
6616     union
6617     {
6618         __IOM uint32_t RFOCR;          /*!< (@ 0x00000068) Receive FIFO Overflow Counter                              */
6619 
6620         struct
6621         {
6622             __IOM uint32_t OVER : 16;  /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
6623                                         *   times the receive FIFO has overflowed. The counter stops
6624                                         *   when the counter value reaches FFFFh.                                     */
6625             uint32_t : 16;
6626         } RFOCR_b;
6627     };
6628 
6629     union
6630     {
6631         __IOM uint32_t IOSR;           /*!< (@ 0x0000006C) Independent Output Signal Setting Register                 */
6632 
6633         struct
6634         {
6635             __IOM uint32_t ELB : 1;    /*!< [0..0] External Loopback Mode                                             */
6636             uint32_t           : 31;
6637         } IOSR_b;
6638     };
6639 
6640     union
6641     {
6642         __IOM uint32_t FCFTR;          /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register         */
6643 
6644         struct
6645         {
6646             __IOM uint32_t RFDO : 3;   /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
6647                                         *   bytes of data is stored in the receive FIFO.)                             */
6648             uint32_t            : 13;
6649             __IOM uint32_t RFFO : 3;   /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
6650                                         *   receive frames have been stored in the receive FIFO.)                     */
6651             uint32_t : 13;
6652         } FCFTR_b;
6653     };
6654     __IM uint32_t RESERVED12;
6655 
6656     union
6657     {
6658         __IOM uint32_t RPADIR;         /*!< (@ 0x00000078) Receive Data Padding Insert Register                       */
6659 
6660         struct
6661         {
6662             __IOM uint32_t PADR : 6;   /*!< [5..0] Padding Slot                                                       */
6663             uint32_t            : 10;
6664             __IOM uint32_t PADS : 2;   /*!< [17..16] Padding Size                                                     */
6665             uint32_t            : 14;
6666         } RPADIR_b;
6667     };
6668 
6669     union
6670     {
6671         __IOM uint32_t TRIMD;          /*!< (@ 0x0000007C) Transmit Interrupt Setting Register                        */
6672 
6673         struct
6674         {
6675             __IOM uint32_t TIS : 1;    /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
6676                                         *   the mode selected by the TIM bit to notify an interrupt.                  */
6677             uint32_t           : 3;
6678             __IOM uint32_t TIM : 1;    /*!< [4..4] Transmit Interrupt Mode                                            */
6679             uint32_t           : 27;
6680         } TRIMD_b;
6681     };
6682     __IM uint32_t RESERVED13[18];
6683 
6684     union
6685     {
6686         __IOM uint32_t RBWAR;          /*!< (@ 0x000000C8) Receive Buffer Write Address Register                      */
6687 
6688         struct
6689         {
6690             __IM uint32_t RBWAR : 32;  /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
6691                                         *   indicates the last address that the EDMAC has written data
6692                                         *   to when writing to the receive buffer.Refer to the address
6693                                         *   indicated by the RBWAR register to recognize which address
6694                                         *   in the receive buffer the EDMAC is writing data to. Note
6695                                         *   that the address that the EDMAC is outputting to the receive
6696                                         *   buffer may not match the read value of the RBWAR register
6697                                         *   during data reception.                                                    */
6698         } RBWAR_b;
6699     };
6700 
6701     union
6702     {
6703         __IOM uint32_t RDFAR;          /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register                  */
6704 
6705         struct
6706         {
6707             __IM uint32_t RDFAR : 32;  /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
6708                                         *   indicates the start address of the last fetched receive
6709                                         *   descriptor when the EDMAC fetches descriptor information
6710                                         *   from the receive descriptor.Refer to the address indicated
6711                                         *   by the RDFAR register to recognize which receive descriptor
6712                                         *   information the EDMAC is using for the current processing.
6713                                         *   Note that the address of the receive descriptor that the
6714                                         *   EDMAC fetches may not match the read value of the RDFAR
6715                                         *   register during data reception.                                           */
6716         } RDFAR_b;
6717     };
6718     __IM uint32_t RESERVED14;
6719 
6720     union
6721     {
6722         __IOM uint32_t TBRAR;          /*!< (@ 0x000000D4) Transmit Buffer Read Address Register                      */
6723 
6724         struct
6725         {
6726             __IM uint32_t TBRAR : 32;  /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
6727                                         *   indicates the last address that the EDMAC has read data
6728                                         *   from when reading data from the transmit buffer.Refer to
6729                                         *   the address indicated by the TBRAR register to recognize
6730                                         *   which address in the transmit buffer the EDMAC is reading
6731                                         *   from. Note that the address that the EDMAC is outputting
6732                                         *   to the transmit buffer may not match the read value of
6733                                         *   the TBRAR register.                                                       */
6734         } TBRAR_b;
6735     };
6736 
6737     union
6738     {
6739         __IM uint32_t TDFAR;           /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register                 */
6740 
6741         struct
6742         {
6743             __IM uint32_t TDFAR : 32;  /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
6744                                         *   register indicates the start address of the last fetched
6745                                         *   transmit descriptor when the EDMAC fetches descriptor information
6746                                         *   from the transmit descriptor.Refer to the address indicated
6747                                         *   by the TDFAR register to recognize which transmit descriptor
6748                                         *   information the EDMAC is using for the current processing.
6749                                         *   Note that the address of the transmit descriptor that the
6750                                         *   EDMAC fetches may not match the read value of the TDFAR
6751                                         *   register.                                                                 */
6752         } TDFAR_b;
6753     };
6754 } R_ETHERC_EDMAC_Type;                 /*!< Size = 220 (0xdc)                                                         */
6755 
6756 /* =========================================================================================================================== */
6757 /* ================                                       R_FACI_HP_CMD                                       ================ */
6758 /* =========================================================================================================================== */
6759 
6760 /**
6761  * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
6762  */
6763 
6764 typedef struct                         /*!< (@ 0x40100000) R_FACI_HP_CMD Structure                                    */
6765 {
6766     union
6767     {
6768         __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
6769         __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
6770     };
6771 } R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
6772 
6773 /* =========================================================================================================================== */
6774 /* ================                                         R_FACI_HP                                         ================ */
6775 /* =========================================================================================================================== */
6776 
6777 /**
6778  * @brief Flash Application Command Interface (R_FACI_HP)
6779  */
6780 
6781 typedef struct                         /*!< (@ 0x4011E000) R_FACI_HP Structure                                        */
6782 {
6783     __IM uint32_t RESERVED[4];
6784 
6785     union
6786     {
6787         __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
6788 
6789         struct
6790         {
6791             uint8_t             : 3;
6792             __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
6793             __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
6794             uint8_t             : 2;
6795             __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
6796         } FASTAT_b;
6797     };
6798     __IM uint8_t  RESERVED1;
6799     __IM uint16_t RESERVED2;
6800 
6801     union
6802     {
6803         __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
6804 
6805         struct
6806         {
6807             uint8_t               : 3;
6808             __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
6809             __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
6810             uint8_t               : 2;
6811             __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
6812         } FAEINT_b;
6813     };
6814     __IM uint8_t  RESERVED3;
6815     __IM uint16_t RESERVED4;
6816 
6817     union
6818     {
6819         __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
6820 
6821         struct
6822         {
6823             __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
6824             uint8_t              : 7;
6825         } FRDYIE_b;
6826     };
6827     __IM uint8_t  RESERVED5;
6828     __IM uint16_t RESERVED6;
6829     __IM uint32_t RESERVED7[5];
6830 
6831     union
6832     {
6833         __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
6834 
6835         struct
6836         {
6837             __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
6838                                         *   These bits can be written when FRDY bit of FSTATR register
6839                                         *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
6840         } FSADDR_b;
6841     };
6842 
6843     union
6844     {
6845         __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
6846 
6847         struct
6848         {
6849             __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
6850                                         *   end address of target area in 'Blank Check' command. These
6851                                         *   bits can be written when FRDY bit of FSTATR register is
6852                                         *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
6853         } FEADDR_b;
6854     };
6855     __IM uint32_t RESERVED8[3];
6856 
6857     union
6858     {
6859         __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
6860 
6861         struct
6862         {
6863             __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
6864                                         *   is only possible when the FRDY bit in the FSTATR register
6865                                         *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
6866                                         *   to this bit is only possible when 16 bits are written and
6867                                         *   the value written to the KEY bits is D9h.Written values
6868                                         *   are not retained by these bits (always read as 0x00).Only
6869                                         *   secure access can write to this register. Both secure access
6870                                         *   and non-secure read access are allowed. Non-secure writeaccess
6871                                         *   is denied, but TrustZo                                                    */
6872             uint16_t          : 7;
6873             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6874         } FMEPROT_b;
6875     };
6876     __IM uint16_t RESERVED9;
6877     __IM uint32_t RESERVED10[12];
6878 
6879     union
6880     {
6881         __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
6882 
6883         struct
6884         {
6885             __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
6886                                         *   written when the FRDY bit in the FSTATR register is 1.
6887                                         *   Writing to this bit is ignored when the FRDY bit is 0.Writing
6888                                         *   to this bit is only possible when 16 bits are written and
6889                                         *   the value written to the KEY[7:0] bits is 0x78.Written
6890                                         *   values are not retained by these bits (always read as 0x00).              */
6891             uint16_t          : 7;
6892             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6893         } FBPROT0_b;
6894     };
6895     __IM uint16_t RESERVED11;
6896 
6897     union
6898     {
6899         __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
6900 
6901         struct
6902         {
6903             __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
6904                                         *   is only possible when the FRDY bit in the FSTATR register
6905                                         *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
6906                                         *   to this bit is only possible when 16 bits are written and
6907                                         *   the value written to the KEY[7:0] bits is 0xB1.Written
6908                                         *   values are not retained by these bits (always read as 0x00).              */
6909             uint16_t          : 7;
6910             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6911         } FBPROT1_b;
6912     };
6913     __IM uint16_t RESERVED12;
6914 
6915     union
6916     {
6917         __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
6918 
6919         struct
6920         {
6921             uint32_t                 : 6;
6922             __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
6923             uint32_t                 : 1;
6924             __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
6925             __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
6926             __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
6927             __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
6928             __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
6929             __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
6930             __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
6931             __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
6932             uint32_t                 : 4;
6933             __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
6934             __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
6935             __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
6936             __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
6937             uint32_t                 : 8;
6938         } FSTATR_b;
6939     };
6940 
6941     union
6942     {
6943         __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
6944 
6945         struct
6946         {
6947             __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
6948                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
6949                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
6950                                          *   only when this register is accessed in 16-bit size and
6951                                          *   H'AA is written to KEY bits                                               */
6952             uint16_t               : 6;
6953             __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
6954                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
6955                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
6956                                          *   only when this register is accessed in 16-bit size and
6957                                          *   H'AA is written to KEY bits.                                              */
6958             __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
6959         } FENTRYR_b;
6960     };
6961     __IM uint16_t RESERVED13;
6962     __IM uint32_t RESERVED14;
6963 
6964     union
6965     {
6966         __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
6967 
6968         struct
6969         {
6970             __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
6971                                         *   bit of FSTATR register is '1'. Writing to this bit in FRDY
6972                                         *   = '0' is ignored. Writing to these bits is enabled only
6973                                         *   when this register is accessed in 16-bit size and H'2D
6974                                         *   is written to KEY bits.                                                   */
6975             uint16_t          : 7;
6976             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6977         } FSUINITR_b;
6978     };
6979     __IM uint16_t RESERVED15;
6980     __IM uint32_t RESERVED16[4];
6981 
6982     union
6983     {
6984         __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
6985 
6986         struct
6987         {
6988             __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
6989             __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
6990         } FCMDR_b;
6991     };
6992     __IM uint16_t RESERVED17;
6993     __IM uint32_t RESERVED18[11];
6994 
6995     union
6996     {
6997         __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
6998 
6999         struct
7000         {
7001             __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
7002             uint8_t             : 7;
7003         } FBCCNT_b;
7004     };
7005     __IM uint8_t  RESERVED19;
7006     __IM uint16_t RESERVED20;
7007 
7008     union
7009     {
7010         __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
7011 
7012         struct
7013         {
7014             __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
7015             uint8_t           : 7;
7016         } FBCSTAT_b;
7017     };
7018     __IM uint8_t  RESERVED21;
7019     __IM uint16_t RESERVED22;
7020 
7021     union
7022     {
7023         __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
7024 
7025         struct
7026         {
7027             __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
7028                                         *   of the first programmed data which is found in 'Blank Check'
7029                                         *   command execution.                                                        */
7030             uint32_t : 13;
7031         } FPSADDR_b;
7032     };
7033 
7034     union
7035     {
7036         __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
7037 
7038         struct
7039         {
7040             __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
7041                                         *   indicate the start sector address for setting the access
7042                                         *   window that is located in the configuration area.                         */
7043             uint32_t           : 4;
7044             __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
7045                                         *   Flag and Temporary Boot Swap Control and 'Config Clear'
7046                                         *   command execution                                                         */
7047             __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
7048                                         *   indicate the end sector address for setting the access
7049                                         *   window that is located in the configuration area.                         */
7050             uint32_t            : 4;
7051             __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
7052         } FAWMON_b;
7053     };
7054 
7055     union
7056     {
7057         __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
7058 
7059         struct
7060         {
7061             __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
7062             uint16_t               : 15;
7063         } FCPSR_b;
7064     };
7065     __IM uint16_t RESERVED23;
7066 
7067     union
7068     {
7069         __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
7070 
7071         struct
7072         {
7073             __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
7074                                         *   can be written when FRDY bit in FSTATR register is '1'.
7075                                         *   Writing to this bit in FRDY = '0' is ignored. Writing to
7076                                         *   these bits is enabled only when this register is accessed
7077                                         *   in 16-bit size and H'1E is written to KEY bits.                           */
7078             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7079         } FPCKAR_b;
7080     };
7081     __IM uint16_t RESERVED24;
7082 
7083     union
7084     {
7085         __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
7086 
7087         struct
7088         {
7089             __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
7090                                         *   bit in FSTATR register is '1'. Writing to this bit in FRDY
7091                                         *   = '0' is ignored. Writing to these bits is enabled only
7092                                         *   when this register is accessed in 16-bit size and H'66
7093                                         *   is written to KEY bits.                                                   */
7094             uint16_t          : 6;
7095             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7096         } FSUACR_b;
7097     };
7098     __IM uint16_t RESERVED25;
7099 } R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
7100 
7101 /* =========================================================================================================================== */
7102 /* ================                                         R_FCACHE                                          ================ */
7103 /* =========================================================================================================================== */
7104 
7105 /**
7106  * @brief Flash Cache (R_FCACHE)
7107  */
7108 
7109 typedef struct                           /*!< (@ 0x4001C100) R_FCACHE Structure                                         */
7110 {
7111     union
7112     {
7113         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000000) Flash Cache Enable Register                                */
7114 
7115         struct
7116         {
7117             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] Flash Cache Enable                                                 */
7118             uint16_t                : 15;
7119         } FCACHEE_b;
7120     };
7121     __IM uint16_t RESERVED;
7122 
7123     union
7124     {
7125         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000004) Flash Cache Invalidate Register                            */
7126 
7127         struct
7128         {
7129             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate                                             */
7130             uint16_t                : 15;
7131         } FCACHEIV_b;
7132     };
7133     __IM uint16_t RESERVED1[11];
7134 
7135     union
7136     {
7137         __IOM uint8_t FLWT;            /*!< (@ 0x0000001C) Flash Wait Cycle Register                                  */
7138 
7139         struct
7140         {
7141             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
7142             uint8_t            : 5;
7143         } FLWT_b;
7144     };
7145     __IM uint8_t  RESERVED2;
7146     __IM uint16_t RESERVED3[17];
7147 
7148     union
7149     {
7150         __IOM uint16_t FSAR;               /*!< (@ 0x00000040) Flash Security Attribution Register                        */
7151 
7152         struct
7153         {
7154             __IOM uint16_t FLWTSA     : 1; /*!< [0..0] FLWT Security Attribution                                          */
7155             __IOM uint16_t FCACHEENSA : 1; /*!< [1..1] FCHACHEEN Security Attribution                                     */
7156             uint16_t                  : 6;
7157             __IOM uint16_t FCKMHZSA   : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
7158             __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI command Issuing Security Attribution                          */
7159             __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI command Registers Security Attribution                      */
7160             __IOM uint16_t FACITRSA   : 1; /*!< [11..11] FACI transfer Security Attribution                               */
7161             uint16_t                  : 4;
7162         } FSAR_b;
7163     };
7164 } R_FCACHE_Type;                           /*!< Size = 66 (0x42)                                                          */
7165 
7166 /* =========================================================================================================================== */
7167 /* ================                                          R_GPT0                                           ================ */
7168 /* =========================================================================================================================== */
7169 
7170 /**
7171  * @brief General PWM Timer (R_GPT0)
7172  */
7173 
7174 typedef struct                         /*!< (@ 0x40322000) R_GPT0 Structure                                           */
7175 {
7176     union
7177     {
7178         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
7179 
7180         struct
7181         {
7182             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
7183             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
7184             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
7185             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
7186             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
7187             uint32_t             : 3;
7188             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
7189             uint32_t             : 16;
7190         } GTWP_b;
7191     };
7192 
7193     union
7194     {
7195         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
7196 
7197         struct
7198         {
7199             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
7200                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7201                                          *   means counter running.                                                    */
7202             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
7203                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7204                                          *   means counter running.                                                    */
7205             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
7206                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7207                                          *   means counter running.                                                    */
7208             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
7209                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7210                                          *   means counter running.                                                    */
7211             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
7212                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7213                                          *   means counter running.                                                    */
7214             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
7215                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7216                                          *   means counter running.                                                    */
7217             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
7218                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7219                                          *   means counter running.                                                    */
7220             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
7221                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7222                                          *   means counter running.                                                    */
7223             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
7224                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7225                                          *   means counter running.                                                    */
7226             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
7227                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7228                                          *   means counter running.                                                    */
7229             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
7230                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7231                                          *   means counter running.                                                    */
7232             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
7233                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7234                                          *   means counter running.                                                    */
7235             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
7236                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7237                                          *   means counter running.                                                    */
7238             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
7239                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7240                                          *   means counter running.                                                    */
7241             __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
7242                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7243                                          *   means counter running.                                                    */
7244             __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
7245                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7246                                          *   means counter running.                                                    */
7247             __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
7248                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7249                                          *   means counter running.                                                    */
7250             __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
7251                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7252                                          *   means counter running.                                                    */
7253             __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
7254                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7255                                          *   means counter running.                                                    */
7256             __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
7257                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7258                                          *   means counter running.                                                    */
7259             __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
7260                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7261                                          *   means counter running.                                                    */
7262             __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
7263                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7264                                          *   means counter running.                                                    */
7265             __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
7266                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7267                                          *   means counter running.                                                    */
7268             __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
7269                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7270                                          *   means counter running.                                                    */
7271             __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
7272                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7273                                          *   means counter running.                                                    */
7274             __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
7275                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7276                                          *   means counter running.                                                    */
7277             __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
7278                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7279                                          *   means counter running.                                                    */
7280             __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
7281                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7282                                          *   means counter running.                                                    */
7283             __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
7284                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7285                                          *   means counter running.                                                    */
7286             __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
7287                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7288                                          *   means counter running.                                                    */
7289             __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
7290                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7291                                          *   means counter running.                                                    */
7292             __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
7293                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7294                                          *   means counter running.                                                    */
7295         } GTSTR_b;
7296     };
7297 
7298     union
7299     {
7300         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
7301 
7302         struct
7303         {
7304             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
7305                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7306                                          *   1 means counter stop.                                                     */
7307             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
7308                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7309                                          *   1 means counter stop.                                                     */
7310             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
7311                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7312                                          *   1 means counter stop.                                                     */
7313             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
7314                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7315                                          *   1 means counter stop.                                                     */
7316             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
7317                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7318                                          *   1 means counter stop.                                                     */
7319             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
7320                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7321                                          *   1 means counter stop.                                                     */
7322             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
7323                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7324                                          *   1 means counter stop.                                                     */
7325             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
7326                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7327                                          *   1 means counter stop.                                                     */
7328             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
7329                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7330                                          *   1 means counter stop.                                                     */
7331             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
7332                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7333                                          *   1 means counter stop.                                                     */
7334             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
7335                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7336                                          *   1 means counter stop.                                                     */
7337             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
7338                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7339                                          *   1 means counter stop.                                                     */
7340             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
7341                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7342                                          *   1 means counter stop.                                                     */
7343             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
7344                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7345                                          *   1 means counter stop.                                                     */
7346             __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
7347                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7348                                          *   1 means counter stop.                                                     */
7349             __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
7350                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7351                                          *   1 means counter stop.                                                     */
7352             __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
7353                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7354                                          *   1 means counter stop.                                                     */
7355             __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
7356                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7357                                          *   1 means counter stop.                                                     */
7358             __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
7359                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7360                                          *   1 means counter stop.                                                     */
7361             __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
7362                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7363                                          *   1 means counter stop.                                                     */
7364             __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
7365                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7366                                          *   1 means counter stop.                                                     */
7367             __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
7368                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7369                                          *   1 means counter stop.                                                     */
7370             __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
7371                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7372                                          *   1 means counter stop.                                                     */
7373             __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
7374                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7375                                          *   1 means counter stop.                                                     */
7376             __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
7377                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7378                                          *   1 means counter stop.                                                     */
7379             __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
7380                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7381                                          *   1 means counter stop.                                                     */
7382             __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
7383                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7384                                          *   1 means counter stop.                                                     */
7385             __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
7386                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7387                                          *   1 means counter stop.                                                     */
7388             __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
7389                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7390                                          *   1 means counter stop.                                                     */
7391             __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
7392                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7393                                          *   1 means counter stop.                                                     */
7394             __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
7395                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7396                                          *   1 means counter stop.                                                     */
7397             __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
7398                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7399                                          *   1 means counter stop.                                                     */
7400         } GTSTP_b;
7401     };
7402 
7403     union
7404     {
7405         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
7406 
7407         struct
7408         {
7409             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
7410             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
7411             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
7412             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
7413             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
7414             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
7415             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
7416             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
7417             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
7418             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
7419             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
7420             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
7421             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
7422             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
7423             __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
7424             __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
7425             __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
7426             __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
7427             __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
7428             __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
7429             __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
7430             __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
7431             __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
7432             __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
7433             __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
7434             __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
7435             __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
7436             __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
7437             __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
7438             __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
7439             __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
7440             __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
7441         } GTCLR_b;
7442     };
7443 
7444     union
7445     {
7446         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
7447 
7448         struct
7449         {
7450             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
7451             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
7452             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
7453             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
7454             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
7455             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
7456             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
7457             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
7458             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7459                                           *   Counter Start Enable                                                      */
7460             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7461                                           *   Counter Start Enable                                                      */
7462             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7463                                           *   Counter Start Enable                                                      */
7464             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7465                                           *   Counter Start Enable                                                      */
7466             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7467                                           *   Counter Start Enable                                                      */
7468             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7469                                           *   Counter Start Enable                                                      */
7470             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7471                                           *   Counter Start Enable                                                      */
7472             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7473                                           *   Counter Start Enable                                                      */
7474             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
7475             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
7476             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
7477             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
7478             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
7479             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
7480             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
7481             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
7482             uint32_t              : 7;
7483             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
7484         } GTSSR_b;
7485     };
7486 
7487     union
7488     {
7489         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
7490 
7491         struct
7492         {
7493             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7494             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
7495             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7496             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
7497             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7498             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
7499             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7500             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
7501             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7502                                           *   Counter Stop Enable                                                       */
7503             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7504                                           *   Counter Stop Enable                                                       */
7505             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7506                                           *   Counter Stop Enable                                                       */
7507             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7508                                           *   Counter Stop Enable                                                       */
7509             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7510                                           *   Counter Stop Enable                                                       */
7511             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7512                                           *   Counter Stop Enable                                                       */
7513             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7514                                           *   Counter Stop Enable                                                       */
7515             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7516                                           *   Counter Stop Enable                                                       */
7517             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
7518             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
7519             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
7520             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
7521             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
7522             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
7523             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
7524             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
7525             uint32_t              : 7;
7526             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
7527         } GTPSR_b;
7528     };
7529 
7530     union
7531     {
7532         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
7533 
7534         struct
7535         {
7536             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
7537             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
7538             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
7539             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
7540             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
7541             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
7542             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
7543             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
7544             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7545                                           *   Counter Clear Enable                                                      */
7546             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7547                                           *   Counter Clear Enable                                                      */
7548             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7549                                           *   Counter Clear Enable                                                      */
7550             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7551                                           *   Counter Clear Enable                                                      */
7552             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7553                                           *   Counter Clear Enable                                                      */
7554             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7555                                           *   Counter Clear Enable                                                      */
7556             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7557                                           *   Counter Clear Enable                                                      */
7558             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7559                                           *   Counter Clear Enable                                                      */
7560             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
7561             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
7562             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
7563             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
7564             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
7565             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
7566             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
7567             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
7568             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
7569                                           *   Source Counter Clear Enable.                                              */
7570             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
7571                                           *   Enable (This bit is only available in GPT324 to GPT329.
7572                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
7573                                           *   should be 0.)                                                             */
7574             uint32_t            : 3;
7575             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
7576         } GTCSR_b;
7577     };
7578 
7579     union
7580     {
7581         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
7582 
7583         struct
7584         {
7585             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7586             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7587             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7588             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7589             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7590             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7591             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7592             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7593             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7594                                           *   Counter Count Up Enable                                                   */
7595             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7596                                           *   Counter Count Up Enable                                                   */
7597             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7598                                           *   Counter Count Up Enable                                                   */
7599             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7600                                           *   Counter Count Up Enable                                                   */
7601             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7602                                           *   Counter Count Up Enable                                                   */
7603             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7604                                           *   Counter Count Up Enable                                                   */
7605             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7606                                           *   Counter Count Up Enable                                                   */
7607             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7608                                           *   Counter Count Up Enable                                                   */
7609             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
7610             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
7611             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
7612             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
7613             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
7614             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
7615             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
7616             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
7617             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
7618             uint32_t              : 4;
7619         } GTUPSR_b;
7620     };
7621 
7622     union
7623     {
7624         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
7625 
7626         struct
7627         {
7628             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7629             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7630             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7631             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7632             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7633             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7634             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7635             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7636             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7637                                           *   Counter Count Down Enable                                                 */
7638             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7639                                           *   Counter Count Down Enable                                                 */
7640             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7641                                           *   Counter Count Down Enable                                                 */
7642             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7643                                           *   Counter Count Down Enable                                                 */
7644             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7645                                           *   Counter Count Down Enable                                                 */
7646             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7647                                           *   Counter Count Down Enable                                                 */
7648             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7649                                           *   Counter Count Down Enable                                                 */
7650             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7651                                           *   Counter Count Down Enable                                                 */
7652             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
7653             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
7654             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
7655             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
7656             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
7657             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
7658             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
7659             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
7660             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
7661             uint32_t              : 4;
7662         } GTDNSR_b;
7663     };
7664 
7665     union
7666     {
7667         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
7668                                           *                  Register A                                                 */
7669 
7670         struct
7671         {
7672             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7673             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
7674                                           *   Enable                                                                    */
7675             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7676             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
7677                                           *   Enable                                                                    */
7678             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7679             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
7680                                           *   Enable                                                                    */
7681             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7682             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
7683                                           *   Enable                                                                    */
7684             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7685                                           *   GTCCRA Input Capture Enable                                               */
7686             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7687                                           *   GTCCRA Input Capture Enable                                               */
7688             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7689                                           *   GTCCRA Input Capture Enable                                               */
7690             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7691                                           *   GTCCRA Input Capture Enable                                               */
7692             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7693                                           *   GTCCRA Input Capture Enable                                               */
7694             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7695                                           *   GTCCRA Input Capture Enable                                               */
7696             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7697                                           *   GTCCRA Input Capture Enable                                               */
7698             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7699                                           *   GTCCRA Input Capture Enable                                               */
7700             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7701             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7702             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7703             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7704             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7705             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7706             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7707             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7708             uint32_t              : 8;
7709         } GTICASR_b;
7710     };
7711 
7712     union
7713     {
7714         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
7715                                           *                  Register B                                                 */
7716 
7717         struct
7718         {
7719             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
7720             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
7721                                           *   Enable                                                                    */
7722             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
7723             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
7724                                           *   Enable                                                                    */
7725             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
7726             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
7727                                           *   Enable                                                                    */
7728             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
7729             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
7730                                           *   Enable                                                                    */
7731             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7732                                           *   GTCCRB Input Capture Enable                                               */
7733             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7734                                           *   GTCCRB Input Capture Enable                                               */
7735             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7736                                           *   GTCCRB Input Capture Enable                                               */
7737             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7738                                           *   GTCCRB Input Capture Enable                                               */
7739             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7740                                           *   GTCCRB Input Capture Enable                                               */
7741             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7742                                           *   GTCCRB Input Capture Enable                                               */
7743             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7744                                           *   GTCCRB Input Capture Enable                                               */
7745             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7746                                           *   GTCCRB Input Capture Enable                                               */
7747             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7748             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7749             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7750             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7751             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7752             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7753             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7754             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
7755             uint32_t              : 8;
7756         } GTICBSR_b;
7757     };
7758 
7759     union
7760     {
7761         __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
7762 
7763         struct
7764         {
7765             __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
7766             uint32_t               : 7;
7767             __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
7768             __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
7769             __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
7770             __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
7771             uint32_t               : 2;
7772             __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
7773             __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
7774             uint32_t               : 3;
7775             __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
7776             __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
7777             uint32_t               : 3;
7778         } GTCR_b;
7779     };
7780 
7781     union
7782     {
7783         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
7784                                         *                  Register                                                   */
7785 
7786         struct
7787         {
7788             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
7789             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
7790             uint32_t              : 14;
7791             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
7792             __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
7793             __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
7794                                         *   percent Duty Setting                                                      */
7795             uint32_t              : 4;
7796             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
7797             __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
7798             __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
7799                                         *   percent Duty Setting                                                      */
7800             uint32_t : 4;
7801         } GTUDDTYC_b;
7802     };
7803 
7804     union
7805     {
7806         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
7807 
7808         struct
7809         {
7810             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
7811             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
7812                                         *   Clear Disable.(This bit is only available in GPT324 to
7813                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
7814                                         *   write value should be 0.)                                                 */
7815             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
7816             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
7817             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
7818             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
7819             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
7820                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
7821                                         *   GPT323, this bit is read as 0. The write value should be
7822                                         *   0.)                                                                       */
7823             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
7824             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
7825             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
7826             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
7827             uint32_t              : 1;
7828             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
7829             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
7830             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
7831             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
7832             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
7833                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
7834                                         *   GPT323, this bit is read as 0. The write value should be
7835                                         *   0.)                                                                       */
7836             uint32_t             : 1;
7837             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
7838             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
7839         } GTIOR_b;
7840     };
7841 
7842     union
7843     {
7844         __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
7845 
7846         struct
7847         {
7848             uint32_t            : 8;
7849             __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
7850                                           *   Clear Enable                                                              */
7851             __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
7852                                           *   Clear Enable                                                              */
7853             __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
7854                                           *   Synchronous Clear Enable                                                  */
7855             __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
7856                                           *   Synchronous Clear Enable                                                  */
7857             __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
7858                                           *   Synchronous Clear Enable                                                  */
7859             __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
7860                                           *   Synchronous Clear Enable                                                  */
7861             __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
7862             __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
7863             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
7864                                           *   Start Request Enable                                                      */
7865             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
7866                                           *   Conversion Start Request Enable                                           */
7867             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
7868                                           *   Start Request Enable                                                      */
7869             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
7870                                           *   Conversion Start Request Enable                                           */
7871             uint32_t               : 4;
7872             __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
7873             uint32_t               : 2;
7874             __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
7875             __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
7876             __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
7877             __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
7878         } GTINTAD_b;
7879     };
7880 
7881     union
7882     {
7883         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
7884 
7885         struct
7886         {
7887             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
7888             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
7889             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
7890             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
7891             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
7892             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
7893             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
7894             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
7895             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
7896                                          *   for counting the number of times a timer interrupt has
7897                                          *   been skipped.)                                                            */
7898             uint32_t               : 4;
7899             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
7900             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
7901                                          *   Request Interrupt Enable                                                  */
7902             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
7903                                          *   Start Request Flag                                                        */
7904             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
7905                                          *   Request Flag                                                              */
7906             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
7907                                          *   Start Request Flag                                                        */
7908             uint32_t             : 4;
7909             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
7910             uint32_t             : 3;
7911             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
7912             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
7913             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
7914             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
7915         } GTST_b;
7916     };
7917 
7918     union
7919     {
7920         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
7921 
7922         struct
7923         {
7924             __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
7925             __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
7926             __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
7927             __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
7928             uint32_t               : 4;
7929             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
7930             uint32_t               : 1;
7931             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
7932             uint32_t               : 5;
7933             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
7934             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
7935             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
7936             __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
7937                                          *   is read as 0.                                                             */
7938             uint32_t             : 1;
7939             __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
7940                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
7941                                          *   at an underflow (in down-counting) or overflow (in up-counting)
7942                                          *   is performed.                                                             */
7943             __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
7944             uint32_t             : 1;
7945             __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
7946                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
7947                                          *   at an underflow (in down-counting) or overflow (in up-counting)
7948                                          *   is performed.                                                             */
7949             __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
7950             uint32_t             : 1;
7951         } GTBER_b;
7952     };
7953 
7954     union
7955     {
7956         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
7957                                         *                  Start Request Skipping Setting Register                    */
7958 
7959         struct
7960         {
7961             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
7962             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
7963             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
7964             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
7965             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
7966             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
7967             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
7968             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
7969             uint32_t             : 1;
7970             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
7971             uint32_t             : 1;
7972             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
7973             uint32_t             : 17;
7974         } GTITC_b;
7975     };
7976 
7977     union
7978     {
7979         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
7980 
7981         struct
7982         {
7983             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
7984         } GTCNT_b;
7985     };
7986 
7987     union
7988     {
7989         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
7990 
7991         struct
7992         {
7993             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
7994         } GTCCR_b[6];
7995     };
7996 
7997     union
7998     {
7999         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
8000 
8001         struct
8002         {
8003             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
8004         } GTPR_b;
8005     };
8006 
8007     union
8008     {
8009         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
8010 
8011         struct
8012         {
8013             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
8014         } GTPBR_b;
8015     };
8016 
8017     union
8018     {
8019         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
8020                                          *                  Register                                                   */
8021 
8022         struct
8023         {
8024             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
8025         } GTPDBR_b;
8026     };
8027 
8028     union
8029     {
8030         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
8031 
8032         struct
8033         {
8034             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
8035         } GTADTRA_b;
8036     };
8037 
8038     union
8039     {
8040         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
8041                                            *                  A                                                          */
8042 
8043         struct
8044         {
8045             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
8046         } GTADTBRA_b;
8047     };
8048 
8049     union
8050     {
8051         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
8052                                             *                  Register A                                                 */
8053 
8054         struct
8055         {
8056             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
8057                                             *   A                                                                         */
8058         } GTADTDBRA_b;
8059     };
8060 
8061     union
8062     {
8063         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
8064 
8065         struct
8066         {
8067             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
8068         } GTADTRB_b;
8069     };
8070 
8071     union
8072     {
8073         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
8074                                            *                  B                                                          */
8075 
8076         struct
8077         {
8078             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
8079         } GTADTBRB_b;
8080     };
8081 
8082     union
8083     {
8084         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
8085                                             *                  Register B                                                 */
8086 
8087         struct
8088         {
8089             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
8090                                             *   B                                                                         */
8091         } GTADTDBRB_b;
8092     };
8093 
8094     union
8095     {
8096         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
8097 
8098         struct
8099         {
8100             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
8101             uint32_t             : 3;
8102             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
8103             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
8104             uint32_t             : 2;
8105             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
8106             uint32_t             : 23;
8107         } GTDTCR_b;
8108     };
8109 
8110     union
8111     {
8112         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
8113 
8114         struct
8115         {
8116             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
8117         } GTDVU_b;
8118     };
8119 
8120     union
8121     {
8122         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
8123 
8124         struct
8125         {
8126             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
8127         } GTDVD_b;
8128     };
8129 
8130     union
8131     {
8132         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
8133 
8134         struct
8135         {
8136             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
8137         } GTDBU_b;
8138     };
8139 
8140     union
8141     {
8142         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
8143 
8144         struct
8145         {
8146             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
8147         } GTDBD_b;
8148     };
8149 
8150     union
8151     {
8152         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
8153                                         *                  Status Register                                            */
8154 
8155         struct
8156         {
8157             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
8158             uint32_t          : 30;
8159         } GTSOS_b;
8160     };
8161 
8162     union
8163     {
8164         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
8165                                         *                  Temporary Release Register                                 */
8166 
8167         struct
8168         {
8169             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
8170             uint32_t            : 31;
8171         } GTSOTR_b;
8172     };
8173 
8174     union
8175     {
8176         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
8177                                          *                  Signal Monitoring Register                                 */
8178 
8179         struct
8180         {
8181             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
8182             uint32_t               : 6;
8183             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
8184                                          *   Enabling                                                                  */
8185             uint32_t               : 7;
8186             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
8187             uint32_t               : 6;
8188             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
8189                                          *   Enabling                                                                  */
8190             uint32_t : 7;
8191         } GTADSMR_b;
8192     };
8193 
8194     union
8195     {
8196         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
8197                                            *                  Counter Control Register                                   */
8198 
8199         struct
8200         {
8201             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
8202             uint32_t               : 2;
8203             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
8204             uint32_t               : 4;
8205             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
8206             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
8207                                            *   select                                                                    */
8208             uint32_t                 : 2;
8209             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
8210             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
8211             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
8212         } GTEITC_b;
8213     };
8214 
8215     union
8216     {
8217         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
8218                                         *                  Setting Register 1                                         */
8219 
8220         struct
8221         {
8222             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
8223                                         *   Extended Skipping Function Select                                         */
8224             uint32_t             : 1;
8225             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
8226                                         *   Extended Skipping Function Select                                         */
8227             uint32_t             : 1;
8228             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
8229                                         *   Function Select                                                           */
8230             uint32_t             : 1;
8231             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
8232                                         *   Function Select                                                           */
8233             uint32_t             : 1;
8234             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
8235                                         *   Function Select                                                           */
8236             uint32_t             : 1;
8237             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
8238                                         *   Function Select                                                           */
8239             uint32_t             : 1;
8240             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
8241             uint32_t             : 1;
8242             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
8243             uint32_t             : 1;
8244         } GTEITLI1_b;
8245     };
8246 
8247     union
8248     {
8249         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
8250                                         *                  Setting Register 2                                         */
8251 
8252         struct
8253         {
8254             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
8255                                         *   Skipping Function Select                                                  */
8256             uint32_t              : 1;
8257             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
8258                                         *   Skipping Function Select                                                  */
8259             uint32_t : 25;
8260         } GTEITLI2_b;
8261     };
8262 
8263     union
8264     {
8265         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
8266                                          *                  Setting Register                                           */
8267 
8268         struct
8269         {
8270             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
8271                                          *   Select                                                                    */
8272             uint32_t              : 1;
8273             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
8274                                          *   Select                                                                    */
8275             uint32_t              : 1;
8276             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
8277                                          *   Select                                                                    */
8278             uint32_t               : 5;
8279             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
8280                                          *   Function Select                                                           */
8281             uint32_t               : 1;
8282             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
8283                                          *   Function Select                                                           */
8284             uint32_t               : 1;
8285             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
8286                                          *   Select                                                                    */
8287             uint32_t               : 1;
8288             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
8289                                          *   Select                                                                    */
8290             uint32_t : 1;
8291         } GTEITLB_b;
8292     };
8293 
8294     union
8295     {
8296         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
8297                                           *                  Function Setting Register                                  */
8298 
8299         struct
8300         {
8301             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
8302             uint32_t                : 1;
8303             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
8304             uint32_t                : 6;
8305             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
8306             uint32_t                : 1;
8307             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
8308             uint32_t                : 6;
8309         } GTICLF_b;
8310     };
8311 
8312     union
8313     {
8314         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
8315 
8316         struct
8317         {
8318             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
8319             uint32_t            : 7;
8320             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
8321             uint32_t            : 7;
8322             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
8323             uint32_t            : 4;
8324         } GTPC_b;
8325     };
8326     __IM uint32_t RESERVED[4];
8327 
8328     union
8329     {
8330         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
8331                                          *                  Control Channel Select Register                            */
8332 
8333         struct
8334         {
8335             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
8336                                          *   Select                                                                    */
8337             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
8338                                          *   Select                                                                    */
8339             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
8340                                          *   Select                                                                    */
8341             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
8342                                          *   Select                                                                    */
8343             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
8344                                          *   Select                                                                    */
8345             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
8346                                          *   Select                                                                    */
8347             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
8348                                          *   Select                                                                    */
8349             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
8350                                          *   Select                                                                    */
8351             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
8352                                          *   Select                                                                    */
8353             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
8354                                          *   Select                                                                    */
8355             uint32_t : 22;
8356         } GTSECSR_b;
8357     };
8358 
8359     union
8360     {
8361         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
8362                                         *                  Control Register                                           */
8363 
8364         struct
8365         {
8366             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
8367             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
8368             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
8369             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
8370             uint32_t             : 4;
8371             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
8372             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
8373             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
8374             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
8375             uint32_t             : 4;
8376             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
8377             __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
8378             uint32_t             : 6;
8379             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
8380             __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
8381             uint32_t             : 6;
8382         } GTSECR_b;
8383     };
8384     __IM uint32_t RESERVED1[2];
8385 
8386     union
8387     {
8388         __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
8389 
8390         struct
8391         {
8392             __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
8393                                         *   Disable                                                                   */
8394             __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
8395                                         *   Disable                                                                   */
8396             __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
8397             __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
8398                                         *   Disable                                                                   */
8399             __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
8400                                         *   Disable                                                                   */
8401             __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
8402                                         *   Disable                                                                   */
8403             uint32_t             : 2;
8404             __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
8405                                         *   Enable                                                                    */
8406             __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
8407                                         *   Enable                                                                    */
8408             uint32_t              : 1;
8409             __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
8410                                         *   Enable                                                                    */
8411             __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
8412                                         *   Enable                                                                    */
8413             uint32_t             : 1;
8414             __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
8415                                         *   Disable                                                                   */
8416             __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
8417                                         *   Disable                                                                   */
8418             __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
8419                                         *   Disable                                                                   */
8420             __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
8421                                         *   Disable                                                                   */
8422             __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
8423                                         *   Disable                                                                   */
8424             __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
8425                                         *   Transfer Disable                                                          */
8426             uint32_t             : 2;
8427             __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
8428             __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
8429             __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
8430             __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
8431             uint32_t             : 2;
8432         } GTBER2_b;
8433     };
8434 
8435     union
8436     {
8437         __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
8438 
8439         struct
8440         {
8441             __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
8442             uint32_t              : 11;
8443             __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
8444             uint32_t              : 11;
8445         } GTOLBR_b;
8446     };
8447     __IM uint32_t RESERVED2;
8448 
8449     union
8450     {
8451         __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
8452                                         *                  Capture Control Register                                   */
8453 
8454         struct
8455         {
8456             __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
8457                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
8458             __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
8459                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
8460             __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
8461                                         *   Channel GTCCRA Input Capture Source Enable                                */
8462             __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
8463                                         *   Channel GTCCRA Input Capture Source Enable                                */
8464             __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
8465                                         *   Channel GTCCRA Input Capture Source Enable                                */
8466             __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
8467                                         *   Channel GTCCRA Input Capture Source Enable                                */
8468             __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
8469                                         *   Source Enable                                                             */
8470             __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
8471                                         *   Source Enable                                                             */
8472             __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
8473                                         *   Capture Source Enable                                                     */
8474             uint32_t              : 5;
8475             __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
8476             __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
8477                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
8478             __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
8479                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
8480             __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
8481                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8482             __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
8483                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8484             __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
8485                                         *   Other Channel GTCCRb Input Capture Source Enable                          */
8486             __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
8487                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8488             __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
8489                                         *   Source Enable                                                             */
8490             __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
8491                                         *   Capture Source Enable                                                     */
8492             __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
8493                                         *   Capture Source Enable                                                     */
8494             uint32_t              : 5;
8495             __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
8496         } GTICCR_b;
8497     };
8498 } R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
8499 
8500 /* =========================================================================================================================== */
8501 /* ================                                         R_GPT_OPS                                         ================ */
8502 /* =========================================================================================================================== */
8503 
8504 /**
8505  * @brief Output Phase Switching for GPT (R_GPT_OPS)
8506  */
8507 
8508 typedef struct                         /*!< (@ 0x40323F00) R_GPT_OPS Structure                                        */
8509 {
8510     union
8511     {
8512         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
8513 
8514         struct
8515         {
8516             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
8517                                         *   by the software settings.This bit setting is valid when
8518                                         *   the OPSCR.FB bit = 1.                                                     */
8519             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
8520                                         *   by the software settings.This bit setting is valid when
8521                                         *   the OPSCR.FB bit = 1.                                                     */
8522             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
8523                                         *   by the software settings.This bit setting is valid when
8524                                         *   the OPSCR.FB bit = 1.                                                     */
8525             uint32_t        : 1;
8526             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
8527                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8528                                         *   e settings (UF/VF/WF)                                                     */
8529             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
8530                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8531                                         *   e settings (UF/VF/WF)                                                     */
8532             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
8533                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8534                                         *   e settings (UF/VF/WF)                                                     */
8535             uint32_t          : 1;
8536             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
8537             uint32_t          : 7;
8538             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
8539                                         *   input phase from the software settings and external input.                */
8540             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
8541             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
8542             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
8543             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
8544             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
8545             uint32_t             : 2;
8546             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
8547             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
8548             uint32_t             : 2;
8549             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
8550             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
8551                                         *   sampling clock setting of the external input.                             */
8552         } OPSCR_b;
8553     };
8554 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
8555 
8556 /* =========================================================================================================================== */
8557 /* ================                                        R_GPT_POEG0                                        ================ */
8558 /* =========================================================================================================================== */
8559 
8560 /**
8561  * @brief Port Output Enable for GPT (R_GPT_POEG0)
8562  */
8563 
8564 typedef struct                          /*!< (@ 0x40212000) R_GPT_POEG0 Structure                                      */
8565 {
8566     union
8567     {
8568         __IOM uint32_t POEGG;           /*!< (@ 0x00000000) POEG Group Setting Register                                */
8569 
8570         struct
8571         {
8572             __IOM uint32_t PIDF  : 1;   /*!< [0..0] Port Input Detection Flag                                          */
8573             __IOM uint32_t IOCF  : 1;   /*!< [1..1] Real Time Overcurrent Detection Flag                               */
8574             __IOM uint32_t OSTPF : 1;   /*!< [2..2] Oscillation Stop Detection Flag                                    */
8575             __IOM uint32_t SSF   : 1;   /*!< [3..3] Software Stop Flag                                                 */
8576             __IOM uint32_t PIDE  : 1;   /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
8577                                          *   once after a reset.                                                       */
8578             __IOM uint32_t IOCE : 1;    /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
8579                                          *   only once after a reset.                                                  */
8580             __IOM uint32_t OSTPE : 1;   /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
8581                                          *   only once after a reset.                                                  */
8582             uint32_t             : 1;
8583             __IOM uint32_t CDRE0 : 1;   /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
8584                                          *   only once after a reset.                                                  */
8585             __IOM uint32_t CDRE1 : 1;   /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
8586                                          *   only once after a reset.                                                  */
8587             __IOM uint32_t CDRE2 : 1;   /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
8588                                          *   only once after a reset.                                                  */
8589             __IOM uint32_t CDRE3 : 1;   /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
8590                                          *   only once after a reset.                                                  */
8591             __IOM uint32_t CDRE4 : 1;   /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
8592                                          *   only once after a reset.                                                  */
8593             __IOM uint32_t CDRE5 : 1;   /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
8594                                          *   only once after a reset.                                                  */
8595             uint32_t               : 2;
8596             __IM uint32_t ST       : 1; /*!< [16..16] GTETRG Input Status Flag                                         */
8597             uint32_t               : 7;
8598             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag                                      */
8599             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag                                      */
8600             __IOM uint32_t DERR0E  : 1; /*!< [26..26] DSMIF0 Error Detection Enable                                    */
8601             __IOM uint32_t DERR1E  : 1; /*!< [27..27] DSMIF1 Error Detection Enable                                    */
8602             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRG Input Reverse                                             */
8603             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise Filter Enable                                              */
8604             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise Filter Clock Select                                        */
8605         } POEGG_b;
8606     };
8607     __IM uint32_t RESERVED[15];
8608 
8609     union
8610     {
8611         __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
8612                                         *                  Register                                                   */
8613 
8614         struct
8615         {
8616             __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
8617             uint16_t             : 7;
8618             __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
8619         } GTONCWP_b;
8620     };
8621     __IM uint16_t RESERVED1;
8622 
8623     union
8624     {
8625         __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
8626                                         *                  Register                                                   */
8627 
8628         struct
8629         {
8630             __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
8631             uint16_t           : 3;
8632             __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
8633             __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
8634             uint16_t           : 7;
8635         } GTONCCR_b;
8636     };
8637     __IM uint16_t RESERVED2;
8638 } R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */
8639 
8640 /* =========================================================================================================================== */
8641 /* ================                                           R_ICU                                           ================ */
8642 /* =========================================================================================================================== */
8643 
8644 /**
8645  * @brief Interrupt Controller Unit (R_ICU)
8646  */
8647 
8648 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
8649 {
8650     union
8651     {
8652         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
8653 
8654         struct
8655         {
8656             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
8657             uint8_t               : 2;
8658             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
8659             uint8_t               : 1;
8660             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
8661         } IRQCR_b[16];
8662     };
8663 
8664     union
8665     {
8666         __IM uint8_t NMICR;             /*!< (@ 0x00000010) NMI Pin Interrupt Control Register                         */
8667 
8668         struct
8669         {
8670             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
8671             uint8_t                : 3;
8672             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock                                  */
8673             uint8_t                : 1;
8674             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
8675         } NMICR_b;
8676     };
8677     __IM uint8_t  RESERVED;
8678     __IM uint16_t RESERVED1;
8679     __IM uint32_t RESERVED2[6143];
8680 
8681     union
8682     {
8683         __IOM uint8_t SWIRQ_S;         /*!< (@ 0x00006010) Software Interrupt Request Register for Secure
8684                                         *                  Interrupt                                                  */
8685 
8686         struct
8687         {
8688             __IOM uint8_t SWIRQS : 1;  /*!< [0..0] Generates an interrupt for the other CPU subsystem.                */
8689             uint8_t              : 7;
8690         } SWIRQ_S_b;
8691     };
8692     __IM uint8_t  RESERVED3;
8693     __IM uint16_t RESERVED4;
8694     __IM uint32_t RESERVED5[3];
8695 
8696     union
8697     {
8698         __IOM uint8_t SWIRQ_NS;        /*!< (@ 0x00006020) Software Interrupt Request Register for Non-secure
8699                                         *                  Interrupt                                                  */
8700 
8701         struct
8702         {
8703             __IOM uint8_t SWIRQNS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem.                */
8704             uint8_t               : 7;
8705         } SWIRQ_NS_b;
8706     };
8707     __IM uint8_t  RESERVED6;
8708     __IM uint16_t RESERVED7;
8709     __IM uint32_t RESERVED8[15];
8710 
8711     union
8712     {
8713         __IOM uint16_t IENMIER;        /*!< (@ 0x00006060) Integrated Error NMI Interrupt Enable Registe
8714                                         *                  for CPU                                                    */
8715 
8716         struct
8717         {
8718             __IOM uint16_t CMEN  : 1;  /*!< [0..0] Integrated Common Memory error nmi Enable                          */
8719             __IOM uint16_t LMEN  : 1;  /*!< [1..1] Integrated Local Memory error nmi Enable                           */
8720             __IOM uint16_t BUSEN : 1;  /*!< [2..2] Integrated BUS error nmi Enable                                    */
8721             uint16_t             : 13;
8722         } IENMIER_b;
8723     };
8724     __IM uint16_t RESERVED9;
8725     __IM uint32_t RESERVED10[39];
8726 
8727     union
8728     {
8729         __IOM uint16_t NMIER;          /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register                     */
8730 
8731         struct
8732         {
8733             __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
8734             __IOM uint16_t WDTEN  : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
8735             __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
8736             __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
8737             uint16_t              : 2;
8738             __IOM uint16_t OSTEN  : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
8739             __IOM uint16_t NMIEN  : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
8740             uint16_t              : 4;
8741             __IOM uint16_t BUSEN  : 1; /*!< [12..12] BUS error Interrupt Enable                                       */
8742             __IOM uint16_t CMEN   : 1; /*!< [13..13] Common Memory error Interrupt Enable                             */
8743             uint16_t              : 1;
8744             __IOM uint16_t LUEN   : 1; /*!< [15..15] LockUp Interrupt Enable                                          */
8745         } NMIER_b;
8746     };
8747     __IM uint16_t RESERVED11;
8748     __IM uint32_t RESERVED12[3];
8749 
8750     union
8751     {
8752         __IOM uint16_t NMICLR;          /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register               */
8753 
8754         struct
8755         {
8756             __IOM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear                                                         */
8757             __IOM uint16_t WDTCLR  : 1; /*!< [1..1] WDT Clear                                                          */
8758             __IOM uint16_t LVD1CLR : 1; /*!< [2..2] PVD1 Clear                                                         */
8759             __IOM uint16_t LVD2CLR : 1; /*!< [3..3] PVD2 Clear                                                         */
8760             uint16_t               : 2;
8761             __IOM uint16_t OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
8762             __IOM uint16_t NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
8763             uint16_t               : 4;
8764             __IOM uint16_t BUSCLR  : 1; /*!< [12..12] Bus Clear                                                        */
8765             __IOM uint16_t CMCLR   : 1; /*!< [13..13] CM Clear                                                         */
8766             uint16_t               : 1;
8767             __IOM uint16_t LUCLR   : 1; /*!< [15..15] LU Clear                                                         */
8768         } NMICLR_b;
8769     };
8770     __IM uint16_t RESERVED13;
8771     __IM uint32_t RESERVED14[3];
8772 
8773     union
8774     {
8775         __IM uint16_t NMISR;           /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register                     */
8776 
8777         struct
8778         {
8779             __IM uint16_t IWDTST : 1;  /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
8780             __IM uint16_t WDTST  : 1;  /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
8781             __IM uint16_t LVD1ST : 1;  /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
8782             __IM uint16_t LVD2ST : 1;  /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
8783             uint16_t             : 2;
8784             __IM uint16_t OSTST  : 1;  /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
8785             __IM uint16_t NMIST  : 1;  /*!< [7..7] NMI Status Flag                                                    */
8786             uint16_t             : 4;
8787             __IM uint16_t BUSST  : 1;  /*!< [12..12] BUS error Interrupt Status Flag                                  */
8788             __IM uint16_t CMST   : 1;  /*!< [13..13] Common Memory error Interrupt Status Flag                        */
8789             uint16_t             : 1;
8790             __IM uint16_t LUST   : 1;  /*!< [15..15] LockUp Interrupt Status Flag                                     */
8791         } NMISR_b;
8792     };
8793     __IM uint16_t RESERVED15;
8794     __IM uint32_t RESERVED16[31];
8795 
8796     union
8797     {
8798         __IOM uint32_t WUPEN;               /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register                          */
8799 
8800         struct
8801         {
8802             __IOM uint32_t IRQWUPEN0 : 1;   /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable
8803                                              *   bit                                                                       */
8804             __IOM uint32_t IRQWUPEN1 : 1;   /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable
8805                                              *   bit                                                                       */
8806             __IOM uint32_t IRQWUPEN2 : 1;   /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable
8807                                              *   bit                                                                       */
8808             __IOM uint32_t IRQWUPEN3 : 1;   /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable
8809                                              *   bit                                                                       */
8810             __IOM uint32_t IRQWUPEN4 : 1;   /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable
8811                                              *   bit                                                                       */
8812             __IOM uint32_t IRQWUPEN5 : 1;   /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable
8813                                              *   bit                                                                       */
8814             __IOM uint32_t IRQWUPEN6 : 1;   /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable
8815                                              *   bit                                                                       */
8816             __IOM uint32_t IRQWUPEN7 : 1;   /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable
8817                                              *   bit                                                                       */
8818             __IOM uint32_t IRQWUPEN8 : 1;   /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable
8819                                              *   bit                                                                       */
8820             __IOM uint32_t IRQWUPEN9 : 1;   /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable
8821                                              *   bit                                                                       */
8822             __IOM uint32_t IRQWUPEN10 : 1;  /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns
8823                                              *   Enable bit                                                                */
8824             __IOM uint32_t IRQWUPEN11 : 1;  /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns
8825                                              *   Enable bit                                                                */
8826             __IOM uint32_t IRQWUPEN12 : 1;  /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns
8827                                              *   Enable bit                                                                */
8828             __IOM uint32_t IRQWUPEN13 : 1;  /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns
8829                                              *   Enable bit                                                                */
8830             __IOM uint32_t IRQWUPEN14 : 1;  /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns
8831                                              *   Enable bit                                                                */
8832             __IOM uint32_t IRQWUPEN15 : 1;  /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns
8833                                              *   Enable bit                                                                */
8834             __IOM uint32_t IWDTWUPEN : 1;   /*!< [16..16] IWDT Interrupt Deep Sleep/Software Standby Returns
8835                                              *   Enable bit                                                                */
8836             uint32_t                 : 1;
8837             __IOM uint32_t LVD1WUPEN : 1;   /*!< [18..18] PVD1 Interrupt Deep Sleep/Software Standby Returns
8838                                              *   Enable bit                                                                */
8839             __IOM uint32_t LVD2WUPEN : 1;   /*!< [19..19] PVD2 Interrupt Deep Sleep/Software Standby Returns
8840                                              *   Enable bit                                                                */
8841             __IOM uint32_t VBATTWUPEN : 1;  /*!< [20..20] VBATT Monitor Interrupt Deep Sleep/Software Standby
8842                                              *   Returns Enable bit                                                        */
8843             uint32_t                   : 3;
8844             __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC Alarm Interrupt Deep Sleep/Software Standby Returns
8845                                              *   Enable bit                                                                */
8846             __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT Period Interrupt Deep Sleep/Software Standby Returns
8847                                              *   Enable bit                                                                */
8848             __IOM uint32_t USBHSWUPEN : 1;  /*!< [26..26] USBHS Interrupt Deep Sleep/Software Standby Returns
8849                                              *   Enable bit                                                                */
8850             __IOM uint32_t USBFSWUPEN : 1;  /*!< [27..27] USBFS0 Interrupt Deep Sleep/Software Standby Returns
8851                                              *   Enable bit                                                                */
8852             __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 Underflow Interrupt Deep Sleep/Software Standby
8853                                              *   Returns Enable bit                                                        */
8854             __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 Compare Match A Interrupt Deep Sleep/Software
8855                                              *   Standby Returns Enable bit                                                */
8856             __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 Compare Match B Interrupt Deep Sleep/Software
8857                                              *   Standby Returns Enable bit                                                */
8858             __IOM uint32_t RIIC0WUPEN : 1;  /*!< [31..31] RIIC0 Address Match Interrupt Deep Sleep/Software Standby
8859                                              *   Returns Enable bit                                                        */
8860         } WUPEN_b;
8861     };
8862 
8863     union
8864     {
8865         __IOM uint32_t WUPEN1;         /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1                        */
8866 
8867         struct
8868         {
8869             uint32_t                    : 3;
8870             __IOM uint32_t COMPHS0WUPEN : 1; /*!< [3..3] Comparator-HS0 Interrupt Deep Sleep/Software Standby
8871                                               *   Returns Enable bit                                                        */
8872             uint32_t                  : 4;
8873             __IOM uint32_t ULP0UWUPEN : 1;   /*!< [8..8] ULPT0 Underflow Interrupt Deep Sleep/Software Standby
8874                                               *   Returns Enable bit                                                        */
8875             __IOM uint32_t ULP0AWUPEN : 1;   /*!< [9..9] ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby
8876                                               *   Returns Enable bit                                                        */
8877             __IOM uint32_t ULP0BWUPEN : 1;   /*!< [10..10] ULPT0 Compare Match B Interrupt Deep Sleep/Software
8878                                               *   Standby Returns Enable bit                                                */
8879             __IOM uint32_t I3CWUPEN : 1;     /*!< [11..11] I3C Wakeup Condition Detection Interrupt Deep Sleep/Software
8880                                               *   Standby Returns Enable bit                                                */
8881             __IOM uint32_t ULP1UWUPEN : 1;   /*!< [12..12] ULPT1 Underflow Interrupt Deep Sleep/Software Standby
8882                                               *   Returns Enable bit                                                        */
8883             __IOM uint32_t ULP1AWUPEN : 1;   /*!< [13..13] ULPT1 Compare Match A Interrupt Deep Sleep/Software
8884                                               *   Standby Returns Enable bit                                                */
8885             __IOM uint32_t ULP1BWUPEN : 1;   /*!< [14..14] ULPT1 Compare Match B Interrupt Deep Sleep/Software
8886                                               *   Standby Returns Enable bit                                                */
8887             uint32_t : 17;
8888         } WUPEN1_b;
8889     };
8890     __IM uint32_t RESERVED17[86];
8891 
8892     union
8893     {
8894         __IOM uint32_t IELSR[96];      /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95]                    */
8895 
8896         struct
8897         {
8898             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
8899                                         *   signal to be linked .                                                     */
8900             uint32_t            : 7;
8901             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
8902             uint32_t            : 7;
8903             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
8904             uint32_t            : 7;
8905         } IELSR_b[96];
8906     };
8907 } R_ICU_Type;                          /*!< Size = 25728 (0x6480)                                                     */
8908 
8909 /* =========================================================================================================================== */
8910 /* ================                                          R_IIC0                                           ================ */
8911 /* =========================================================================================================================== */
8912 
8913 /**
8914  * @brief I2C Bus Interface (R_IIC0)
8915  */
8916 
8917 typedef struct                         /*!< (@ 0x4025E000) R_IIC0 Structure                                           */
8918 {
8919     union
8920     {
8921         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
8922 
8923         struct
8924         {
8925             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
8926             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
8927             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
8928             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
8929             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
8930             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
8931             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
8932                                         *   is initiated using the IICRST bit for a bus hang-up occurred
8933                                         *   during communication with the master device in slave mode,
8934                                         *   the states may become different between the slave device
8935                                         *   and the master device (due to the difference in the bit
8936                                         *   counter information).                                                     */
8937             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
8938         } ICCR1_b;
8939     };
8940 
8941     union
8942     {
8943         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
8944 
8945         struct
8946         {
8947             uint8_t          : 1;
8948             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
8949                                         *   condition issuance request) when the BBSY flag is set to
8950                                         *   0 (bus free state).                                                       */
8951             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
8952                                         *   RS bit to 1 while issuing a stop condition.                               */
8953             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
8954                                         *   bit is not possible while the setting of the BBSY flag
8955                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
8956                                         *   while a restart condition is being issued.                                */
8957             uint8_t            : 1;
8958             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
8959             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
8960             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
8961         } ICCR2_b;
8962     };
8963 
8964     union
8965     {
8966         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
8967 
8968         struct
8969         {
8970             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
8971             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
8972             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
8973                                         *   / 2^CKS )                                                                 */
8974             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
8975         } ICMR1_b;
8976     };
8977 
8978     union
8979     {
8980         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
8981 
8982         struct
8983         {
8984             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
8985             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
8986             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
8987             uint8_t            : 1;
8988             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
8989             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
8990         } ICMR2_b;
8991     };
8992 
8993     union
8994     {
8995         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
8996 
8997         struct
8998         {
8999             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
9000             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
9001             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
9002             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
9003             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
9004             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
9005                                         *   be sure to read the ICDRR beforehand.                                     */
9006             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
9007         } ICMR3_b;
9008     };
9009 
9010     union
9011     {
9012         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
9013 
9014         struct
9015         {
9016             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
9017             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
9018             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
9019             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
9020             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
9021             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
9022             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
9023             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
9024         } ICFER_b;
9025     };
9026 
9027     union
9028     {
9029         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
9030 
9031         struct
9032         {
9033             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
9034             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
9035             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
9036             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
9037             uint8_t             : 1;
9038             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
9039             uint8_t             : 1;
9040             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
9041         } ICSER_b;
9042     };
9043 
9044     union
9045     {
9046         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
9047 
9048         struct
9049         {
9050             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
9051             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
9052             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
9053             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
9054             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
9055             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
9056             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
9057             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
9058         } ICIER_b;
9059     };
9060 
9061     union
9062     {
9063         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
9064 
9065         struct
9066         {
9067             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
9068             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
9069             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
9070             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
9071             uint8_t            : 1;
9072             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
9073             uint8_t            : 1;
9074             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
9075         } ICSR1_b;
9076     };
9077 
9078     union
9079     {
9080         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
9081 
9082         struct
9083         {
9084             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
9085             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
9086             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
9087             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
9088             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
9089             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
9090             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
9091             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
9092         } ICSR2_b;
9093     };
9094     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
9095 
9096     union
9097     {
9098         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
9099 
9100         struct
9101         {
9102             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
9103             uint8_t           : 3;
9104         } ICBRL_b;
9105     };
9106 
9107     union
9108     {
9109         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
9110 
9111         struct
9112         {
9113             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
9114             uint8_t           : 3;
9115         } ICBRH_b;
9116     };
9117 
9118     union
9119     {
9120         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
9121 
9122         struct
9123         {
9124             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
9125         } ICDRT_b;
9126     };
9127 
9128     union
9129     {
9130         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
9131 
9132         struct
9133         {
9134             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
9135         } ICDRR_b;
9136     };
9137     __IM uint8_t RESERVED[2];
9138 
9139     union
9140     {
9141         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
9142 
9143         struct
9144         {
9145             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
9146             uint8_t             : 3;
9147             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
9148             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
9149             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
9150             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
9151         } ICWUR_b;
9152     };
9153 
9154     union
9155     {
9156         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
9157 
9158         struct
9159         {
9160             __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
9161             __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
9162             __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
9163             uint8_t              : 5;
9164         } ICWUR2_b;
9165     };
9166 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
9167 
9168 /* =========================================================================================================================== */
9169 /* ================                                          R_IWDT                                           ================ */
9170 /* =========================================================================================================================== */
9171 
9172 /**
9173  * @brief Independent Watchdog Timer (R_IWDT)
9174  */
9175 
9176 typedef struct                         /*!< (@ 0x40202200) R_IWDT Structure                                           */
9177 {
9178     union
9179     {
9180         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
9181 
9182         struct
9183         {
9184             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
9185                                         *   0xFF to this register.                                                    */
9186         } IWDTRR_b;
9187     };
9188     __IM uint8_t RESERVED;
9189 
9190     union
9191     {
9192         __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
9193 
9194         struct
9195         {
9196             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
9197             uint16_t            : 2;
9198             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
9199             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
9200             uint16_t            : 2;
9201             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
9202             uint16_t            : 2;
9203         } IWDTCR_b;
9204     };
9205 
9206     union
9207     {
9208         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
9209 
9210         struct
9211         {
9212             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
9213             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
9214             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
9215         } IWDTSR_b;
9216     };
9217 
9218     union
9219     {
9220         __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
9221 
9222         struct
9223         {
9224             uint8_t               : 7;
9225             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
9226         } IWDTRCR_b;
9227     };
9228     __IM uint8_t RESERVED1;
9229 
9230     union
9231     {
9232         __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
9233 
9234         struct
9235         {
9236             uint8_t              : 7;
9237             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
9238         } IWDTCSTPR_b;
9239     };
9240     __IM uint8_t  RESERVED2;
9241     __IM uint16_t RESERVED3;
9242 } R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
9243 
9244 /* =========================================================================================================================== */
9245 /* ================                                          R_I3C0                                           ================ */
9246 /* =========================================================================================================================== */
9247 
9248 /**
9249  * @brief I3C Bus Interface (R_I3C0)
9250  */
9251 
9252 typedef struct                         /*!< (@ 0x4035F000) R_I3C0 Structure                                           */
9253 {
9254     union
9255     {
9256         __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
9257 
9258         struct
9259         {
9260             __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
9261             uint32_t             : 31;
9262         } PRTS_b;
9263     };
9264     __IM uint32_t RESERVED[3];
9265 
9266     union
9267     {
9268         __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
9269 
9270         struct
9271         {
9272             __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
9273             uint32_t            : 31;
9274         } CECTL_b;
9275     };
9276 
9277     union
9278     {
9279         __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
9280 
9281         struct
9282         {
9283             __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
9284             uint32_t                : 6;
9285             __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
9286             __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
9287             uint32_t                : 20;
9288             __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
9289             __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
9290             __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
9291         } BCTL_b;
9292     };
9293 
9294     union
9295     {
9296         __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
9297 
9298         struct
9299         {
9300             uint32_t              : 16;
9301             __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
9302             uint32_t              : 8;
9303             __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
9304         } MSDVAD_b;
9305     };
9306     __IM uint32_t RESERVED1;
9307 
9308     union
9309     {
9310         __IOM uint32_t RSTCTL;          /*!< (@ 0x00000020) Reset Control Register                                     */
9311 
9312         struct
9313         {
9314             __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset                                                 */
9315             __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset                                       */
9316             __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset                                      */
9317             __IOM uint32_t TDBRST  : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
9318             __IOM uint32_t RDBRST  : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
9319             __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset                                           */
9320             __IOM uint32_t RSQRST  : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
9321             uint32_t               : 9;
9322             __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset                                          */
9323             uint32_t               : 15;
9324         } RSTCTL_b;
9325     };
9326 
9327     union
9328     {
9329         __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
9330 
9331         struct
9332         {
9333             uint32_t              : 2;
9334             __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
9335             uint32_t              : 1;
9336             __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
9337             uint32_t              : 2;
9338             __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
9339             uint32_t              : 24;
9340         } PRSST_b;
9341     };
9342     __IM uint32_t RESERVED2[2];
9343 
9344     union
9345     {
9346         __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
9347 
9348         struct
9349         {
9350             uint32_t            : 10;
9351             __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
9352             uint32_t            : 21;
9353         } INST_b;
9354     };
9355 
9356     union
9357     {
9358         __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
9359 
9360         struct
9361         {
9362             uint32_t            : 10;
9363             __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
9364             uint32_t            : 21;
9365         } INSTE_b;
9366     };
9367 
9368     union
9369     {
9370         __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
9371 
9372         struct
9373         {
9374             uint32_t             : 10;
9375             __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
9376             uint32_t             : 21;
9377         } INIE_b;
9378     };
9379 
9380     union
9381     {
9382         __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
9383 
9384         struct
9385         {
9386             uint32_t            : 10;
9387             __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
9388             uint32_t            : 21;
9389         } INSTFC_b;
9390     };
9391     __IM uint32_t RESERVED3;
9392 
9393     union
9394     {
9395         __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
9396 
9397         struct
9398         {
9399             uint32_t          : 19;
9400             __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
9401             uint32_t          : 8;
9402         } DVCT_b;
9403     };
9404     __IM uint32_t RESERVED4[4];
9405 
9406     union
9407     {
9408         __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
9409 
9410         struct
9411         {
9412             __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
9413             __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
9414             uint32_t                : 1;
9415             __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
9416             uint32_t                : 28;
9417         } IBINCTL_b;
9418     };
9419     __IM uint32_t RESERVED5;
9420 
9421     union
9422     {
9423         __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
9424 
9425         struct
9426         {
9427             __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
9428             __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
9429             __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
9430             uint32_t              : 5;
9431             __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
9432             uint32_t              : 3;
9433             __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
9434             uint32_t              : 1;
9435             __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
9436             __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
9437             uint32_t              : 16;
9438         } BFCTL_b;
9439     };
9440 
9441     union
9442     {
9443         __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
9444 
9445         struct
9446         {
9447             __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
9448             uint32_t             : 4;
9449             __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
9450             __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
9451             uint32_t             : 8;
9452             __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
9453             __IOM uint32_t SVAEn : 1;  /*!< [16..16] Slave Address Enable n (n = 0)                                   */
9454             uint32_t             : 15;
9455         } SVCTL_b;
9456     };
9457     __IM uint32_t RESERVED6[2];
9458 
9459     union
9460     {
9461         __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
9462 
9463         struct
9464         {
9465             __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
9466             uint32_t               : 29;
9467         } REFCKCTL_b;
9468     };
9469 
9470     union
9471     {
9472         __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
9473 
9474         struct
9475         {
9476             __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
9477             __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
9478             __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
9479             uint32_t              : 2;
9480             __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
9481             uint32_t              : 1;
9482             __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
9483         } STDBR_b;
9484     };
9485 
9486     union
9487     {
9488         __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
9489 
9490         struct
9491         {
9492             __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
9493             __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
9494             __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
9495             uint32_t             : 2;
9496             __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull                     */
9497             uint32_t             : 2;
9498         } EXTBR_b;
9499     };
9500 
9501     union
9502     {
9503         __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
9504 
9505         struct
9506         {
9507             __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
9508             uint32_t              : 23;
9509         } BFRECDT_b;
9510     };
9511 
9512     union
9513     {
9514         __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
9515 
9516         struct
9517         {
9518             __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
9519             uint32_t              : 23;
9520         } BAVLCDT_b;
9521     };
9522 
9523     union
9524     {
9525         __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
9526 
9527         struct
9528         {
9529             __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
9530             uint32_t              : 14;
9531         } BIDLCDT_b;
9532     };
9533 
9534     union
9535     {
9536         __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
9537 
9538         struct
9539         {
9540             __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
9541             __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
9542             __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
9543             uint32_t              : 1;
9544             __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
9545             uint32_t              : 3;
9546             __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
9547             uint32_t              : 4;
9548             __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
9549             uint32_t              : 16;
9550         } OUTCTL_b;
9551     };
9552 
9553     union
9554     {
9555         __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
9556 
9557         struct
9558         {
9559             __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
9560             __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
9561             uint32_t            : 27;
9562         } INCTL_b;
9563     };
9564 
9565     union
9566     {
9567         __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
9568 
9569         struct
9570         {
9571             __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
9572             uint32_t              : 2;
9573             __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
9574             __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
9575             __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
9576             uint32_t              : 24;
9577         } TMOCTL_b;
9578     };
9579     __IM uint32_t RESERVED7;
9580 
9581     union
9582     {
9583         __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
9584 
9585         struct
9586         {
9587             __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
9588             uint32_t               : 3;
9589             __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
9590             uint32_t               : 1;
9591             __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
9592             __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
9593             uint32_t               : 24;
9594         } WUCTL_b;
9595     };
9596     __IM uint32_t RESERVED8;
9597 
9598     union
9599     {
9600         __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
9601 
9602         struct
9603         {
9604             __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
9605             __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
9606             __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
9607             uint32_t              : 29;
9608         } ACKCTL_b;
9609     };
9610 
9611     union
9612     {
9613         __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
9614 
9615         struct
9616         {
9617             __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
9618             __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
9619             uint32_t              : 30;
9620         } SCSTRCTL_b;
9621     };
9622     __IM uint32_t RESERVED9[2];
9623 
9624     union
9625     {
9626         __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
9627 
9628         struct
9629         {
9630             __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
9631             uint32_t              : 12;
9632             __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
9633             __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
9634             __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
9635             __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
9636         } SCSTLCTL_b;
9637     };
9638     __IM uint32_t RESERVED10[3];
9639 
9640     union
9641     {
9642         __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
9643 
9644         struct
9645         {
9646             uint32_t             : 16;
9647             __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
9648         } SVTDLG0_b;
9649     };
9650     __IM uint32_t RESERVED11[31];
9651 
9652     union
9653     {
9654         __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
9655 
9656         struct
9657         {
9658             __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
9659             __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
9660             __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
9661             uint32_t             : 29;
9662         } CNDCTL_b;
9663     };
9664     __IM uint32_t  RESERVED12[3];
9665     __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
9666     __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
9667     __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
9668     __IM uint32_t  RESERVED13[8];
9669     __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
9670     __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
9671     __IM uint32_t  RESERVED14[3];
9672 
9673     union
9674     {
9675         __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
9676 
9677         struct
9678         {
9679             __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
9680             __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
9681             __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
9682             __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
9683         } NQTHCTL_b;
9684     };
9685 
9686     union
9687     {
9688         __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
9689                                         *                  Register 0                                                 */
9690 
9691         struct
9692         {
9693             __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
9694             uint32_t              : 5;
9695             __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
9696             uint32_t              : 5;
9697             __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
9698             uint32_t              : 5;
9699             __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
9700             uint32_t              : 5;
9701         } NTBTHCTL0_b;
9702     };
9703     __IM uint32_t RESERVED15[10];
9704 
9705     union
9706     {
9707         __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
9708                                         *                  Register                                                   */
9709 
9710         struct
9711         {
9712             __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
9713             uint32_t             : 24;
9714         } NRQTHCTL_b;
9715     };
9716     __IM uint32_t RESERVED16[3];
9717 
9718     union
9719     {
9720         __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
9721 
9722         struct
9723         {
9724             __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
9725             __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
9726             __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
9727             uint32_t               : 1;
9728             __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
9729             uint32_t               : 3;
9730             __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
9731             uint32_t               : 7;
9732             __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
9733             uint32_t               : 3;
9734             __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
9735             uint32_t               : 11;
9736         } BST_b;
9737     };
9738 
9739     union
9740     {
9741         __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
9742 
9743         struct
9744         {
9745             __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
9746             __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
9747             __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
9748             uint32_t               : 1;
9749             __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
9750             uint32_t               : 3;
9751             __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
9752             uint32_t               : 7;
9753             __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
9754             uint32_t               : 3;
9755             __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
9756             uint32_t               : 11;
9757         } BSTE_b;
9758     };
9759 
9760     union
9761     {
9762         __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
9763 
9764         struct
9765         {
9766             __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
9767             __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
9768             __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
9769             uint32_t                : 1;
9770             __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
9771             uint32_t                : 3;
9772             __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
9773             uint32_t                : 7;
9774             __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
9775             uint32_t                : 3;
9776             __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
9777             uint32_t                : 11;
9778         } BIE_b;
9779     };
9780 
9781     union
9782     {
9783         __IOM uint32_t BSTFC;           /*!< (@ 0x000001DC) Bus Status Force Register                                  */
9784 
9785         struct
9786         {
9787             __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force                                    */
9788             __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force                                     */
9789             __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
9790             uint32_t               : 1;
9791             __OM uint32_t NACKDFC  : 1; /*!< [4..4] NACK Detection Force                                               */
9792             uint32_t               : 3;
9793             __OM uint32_t TENDFC   : 1; /*!< [8..8] Transmit End Force                                                 */
9794             uint32_t               : 7;
9795             __OM uint32_t ALFC     : 1; /*!< [16..16] Arbitration Lost Force                                           */
9796             uint32_t               : 3;
9797             __OM uint32_t TODFC    : 1; /*!< [20..20] Timeout Detection Force                                          */
9798             uint32_t               : 11;
9799         } BSTFC_b;
9800     };
9801 
9802     union
9803     {
9804         __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
9805 
9806         struct
9807         {
9808             __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
9809             __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
9810             __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
9811             __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
9812             __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
9813             __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
9814             uint32_t               : 3;
9815             __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
9816             uint32_t               : 10;
9817             __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
9818             uint32_t               : 11;
9819         } NTST_b;
9820     };
9821 
9822     union
9823     {
9824         __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
9825 
9826         struct
9827         {
9828             __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
9829             __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
9830             __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
9831             __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
9832             __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
9833             __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
9834             uint32_t               : 3;
9835             __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
9836             uint32_t               : 10;
9837             __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
9838             uint32_t               : 11;
9839         } NTSTE_b;
9840     };
9841 
9842     union
9843     {
9844         __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
9845 
9846         struct
9847         {
9848             __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
9849             __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
9850             __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
9851             __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
9852             __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
9853             __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
9854             uint32_t                : 3;
9855             __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
9856             uint32_t                : 10;
9857             __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
9858             uint32_t                : 11;
9859         } NTIE_b;
9860     };
9861 
9862     union
9863     {
9864         __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
9865 
9866         struct
9867         {
9868             __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
9869             __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
9870             __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
9871             __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
9872             __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
9873             __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
9874             uint32_t               : 3;
9875             __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
9876             uint32_t               : 10;
9877             __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
9878             uint32_t               : 11;
9879         } NTSTFC_b;
9880     };
9881     __IM uint32_t RESERVED17[8];
9882 
9883     union
9884     {
9885         __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
9886 
9887         struct
9888         {
9889             __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
9890             __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
9891             __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
9892             uint32_t            : 29;
9893         } BCST_b;
9894     };
9895 
9896     union
9897     {
9898         __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
9899 
9900         struct
9901         {
9902             __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
9903             uint32_t             : 4;
9904             __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
9905             __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
9906             uint32_t             : 8;
9907             __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
9908             __IOM uint32_t SVAFn : 1;  /*!< [16..16] Slave Address Detection Flag n (n = 0)                           */
9909             uint32_t             : 15;
9910         } SVST_b;
9911     };
9912 
9913     union
9914     {
9915         __IOM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Control Register                              */
9916 
9917         struct
9918         {
9919             __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
9920             uint32_t               : 31;
9921         } WUST_b;
9922     };
9923     __IM uint32_t RESERVED18[2];
9924 
9925     union
9926     {
9927         __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
9928 
9929         struct
9930         {
9931             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
9932             uint32_t               : 5;
9933             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
9934             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
9935             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
9936             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
9937             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
9938             uint32_t               : 5;
9939             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
9940             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
9941         } DATBAS0_b;
9942     };
9943     __IM uint32_t RESERVED19;
9944 
9945     union
9946     {
9947         __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
9948 
9949         struct
9950         {
9951             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
9952             uint32_t               : 5;
9953             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
9954             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
9955             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
9956             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
9957             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
9958             uint32_t               : 5;
9959             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
9960             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
9961         } DATBAS1_b;
9962     };
9963     __IM uint32_t RESERVED20;
9964 
9965     union
9966     {
9967         __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
9968 
9969         struct
9970         {
9971             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
9972             uint32_t               : 5;
9973             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
9974             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
9975             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
9976             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
9977             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
9978             uint32_t               : 5;
9979             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
9980             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
9981         } DATBAS2_b;
9982     };
9983     __IM uint32_t RESERVED21;
9984 
9985     union
9986     {
9987         __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
9988 
9989         struct
9990         {
9991             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
9992             uint32_t               : 5;
9993             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
9994             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
9995             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
9996             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
9997             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
9998             uint32_t               : 5;
9999             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10000             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10001         } DATBAS3_b;
10002     };
10003     __IM uint32_t RESERVED22[24];
10004 
10005     union
10006     {
10007         __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
10008 
10009         struct
10010         {
10011             __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
10012             uint32_t              : 9;
10013             __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
10014             uint32_t              : 5;
10015             __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
10016             __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
10017         } EXDATBAS_b;
10018     };
10019     __IM uint32_t RESERVED23[3];
10020 
10021     union
10022     {
10023         __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
10024 
10025         struct
10026         {
10027             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10028             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10029             uint32_t               : 1;
10030             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10031             uint32_t               : 3;
10032             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10033             uint32_t               : 9;
10034         } SDATBAS0_b;
10035     };
10036 
10037     union
10038     {
10039         __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
10040 
10041         struct
10042         {
10043             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10044             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10045             uint32_t               : 1;
10046             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10047             uint32_t               : 3;
10048             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10049             uint32_t               : 9;
10050         } SDATBAS1_b;
10051     };
10052 
10053     union
10054     {
10055         __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
10056 
10057         struct
10058         {
10059             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10060             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10061             uint32_t               : 1;
10062             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10063             uint32_t               : 3;
10064             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10065             uint32_t               : 9;
10066         } SDATBAS2_b;
10067     };
10068     __IM uint32_t RESERVED24[5];
10069 
10070     union
10071     {
10072         __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
10073 
10074         struct
10075         {
10076             uint32_t              : 8;
10077             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10078             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10079             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10080             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10081             uint32_t              : 2;
10082             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10083             uint32_t              : 16;
10084         } MSDCT0_b;
10085     };
10086 
10087     union
10088     {
10089         __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
10090 
10091         struct
10092         {
10093             uint32_t              : 8;
10094             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10095             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10096             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10097             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10098             uint32_t              : 2;
10099             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10100             uint32_t              : 16;
10101         } MSDCT1_b;
10102     };
10103 
10104     union
10105     {
10106         __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
10107 
10108         struct
10109         {
10110             uint32_t              : 8;
10111             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10112             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10113             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10114             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10115             uint32_t              : 2;
10116             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10117             uint32_t              : 16;
10118         } MSDCT2_b;
10119     };
10120 
10121     union
10122     {
10123         __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
10124 
10125         struct
10126         {
10127             uint32_t              : 8;
10128             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10129             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10130             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10131             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10132             uint32_t              : 2;
10133             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10134             uint32_t              : 16;
10135         } MSDCT3_b;
10136     };
10137     __IM uint32_t RESERVED25[16];
10138 
10139     union
10140     {
10141         __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
10142 
10143         struct
10144         {
10145             __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
10146             __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10147             __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10148             __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10149             __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10150             uint32_t              : 2;
10151             __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
10152             uint32_t              : 16;
10153         } SVDCT_b;
10154     };
10155     __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
10156                                         *                  ID Low Register                                            */
10157     __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
10158                                         *                  ID High Register                                           */
10159     __IM uint32_t RESERVED26;
10160 
10161     union
10162     {
10163         __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
10164 
10165         struct
10166         {
10167             uint32_t             : 16;
10168             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
10169             uint32_t             : 1;
10170             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
10171             uint32_t             : 2;
10172             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
10173             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
10174         } SVDVAD0_b;
10175     };
10176     __IM uint32_t RESERVED27[7];
10177 
10178     union
10179     {
10180         __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
10181 
10182         struct
10183         {
10184             __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
10185             __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
10186             uint32_t              : 1;
10187             __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
10188             uint32_t              : 28;
10189         } CSECMD_b;
10190     };
10191 
10192     union
10193     {
10194         __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
10195 
10196         struct
10197         {
10198             __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
10199             uint32_t             : 28;
10200         } CEACTST_b;
10201     };
10202 
10203     union
10204     {
10205         __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
10206 
10207         struct
10208         {
10209             __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
10210             uint32_t            : 16;
10211         } CMWLG_b;
10212     };
10213 
10214     union
10215     {
10216         __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
10217 
10218         struct
10219         {
10220             __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
10221             __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
10222             uint32_t              : 8;
10223         } CMRLG_b;
10224     };
10225 
10226     union
10227     {
10228         __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
10229 
10230         struct
10231         {
10232             __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
10233             uint32_t            : 24;
10234         } CETSTMD_b;
10235     };
10236 
10237     union
10238     {
10239         __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
10240 
10241         struct
10242         {
10243             __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
10244             uint32_t              : 1;
10245             __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
10246             __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
10247             __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
10248             uint32_t              : 16;
10249         } CGDVST_b;
10250     };
10251 
10252     union
10253     {
10254         __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
10255 
10256         struct
10257         {
10258             __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
10259             uint32_t             : 29;
10260         } CMDSPW_b;
10261     };
10262 
10263     union
10264     {
10265         __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
10266 
10267         struct
10268         {
10269             __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
10270             __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
10271             uint32_t              : 26;
10272         } CMDSPR_b;
10273     };
10274 
10275     union
10276     {
10277         __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
10278 
10279         struct
10280         {
10281             __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
10282             uint32_t              : 7;
10283             __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
10284         } CMDSPT_b;
10285     };
10286 
10287     union
10288     {
10289         __IOM uint32_t CETSM;          /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
10290                                         *                  Register                                                   */
10291 
10292         struct
10293         {
10294             uint32_t            : 8;
10295             __IOM uint32_t FREQ : 8;   /*!< [15..8] Frequency Byte                                                    */
10296             __IOM uint32_t INAC : 8;   /*!< [23..16] Inaccuracy Byte                                                  */
10297             uint32_t            : 8;
10298         } CETSM_b;
10299     };
10300     __IM uint32_t RESERVED28[2];
10301 
10302     union
10303     {
10304         __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
10305 
10306         struct
10307         {
10308             __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
10309             uint32_t             : 2;
10310             __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
10311             uint32_t             : 24;
10312         } BITCNT_b;
10313     };
10314     __IM uint32_t RESERVED29[4];
10315 
10316     union
10317     {
10318         __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
10319 
10320         struct
10321         {
10322             __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
10323             __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
10324             __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
10325             __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
10326             uint32_t              : 3;
10327         } NQSTLV_b;
10328     };
10329 
10330     union
10331     {
10332         __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register                   */
10333 
10334         struct
10335         {
10336             __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
10337             __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
10338             uint32_t             : 16;
10339         } NDBSTLV0_b;
10340     };
10341     __IM uint32_t RESERVED30[9];
10342 
10343     union
10344     {
10345         __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
10346 
10347         struct
10348         {
10349             __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
10350             uint32_t            : 24;
10351         } NRSQSTLV_b;
10352     };
10353     __IM uint32_t RESERVED31[2];
10354 
10355     union
10356     {
10357         __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
10358 
10359         struct
10360         {
10361             __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
10362             __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
10363             __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
10364             __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
10365             uint32_t            : 28;
10366         } PRSTDBG_b;
10367     };
10368 
10369     union
10370     {
10371         __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
10372 
10373         struct
10374         {
10375             __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
10376             uint32_t             : 24;
10377         } MSERRCNT_b;
10378     };
10379 } R_I3C0_Type;                         /*!< Size = 980 (0x3d4)                                                        */
10380 
10381 /* =========================================================================================================================== */
10382 /* ================                                        R_MPU_MMPU                                         ================ */
10383 /* =========================================================================================================================== */
10384 
10385 /**
10386  * @brief Bus Master MPU (R_MPU_MMPU)
10387  */
10388 
10389 typedef struct                         /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
10390 {
10391     union
10392     {
10393         __IOM uint16_t OAD;            /*!< (@ 0x00000000) MMPU Operation After Detection Register                    */
10394 
10395         struct
10396         {
10397             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
10398             uint16_t           : 7;
10399             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
10400                                         *   stored.                                                                   */
10401         } OAD_b;
10402     };
10403     __IM uint16_t RESERVED;
10404 
10405     union
10406     {
10407         __IOM uint16_t OADPT;           /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register            */
10408 
10409         struct
10410         {
10411             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
10412             uint16_t               : 7;
10413             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
10414                                          *   stored.                                                                   */
10415         } OADPT_b;
10416     };
10417     __IM uint16_t               RESERVED1;
10418     __IM uint32_t               RESERVED2[62];
10419     __IOM R_MPU_MMPU_GROUP_Type DMAC0;    /*!< (@ 0x00000100) DMAC0 MMPU Registers                                       */
10420     __IOM R_MPU_MMPU_GROUP_Type DMAC1;    /*!< (@ 0x00000300) DMAC1 MMPU Registers                                       */
10421     __IOM R_MPU_MMPU_GROUP_Type EDMAC;    /*!< (@ 0x00000500) EDMAC MMPU Registers                                       */
10422     __IOM R_MPU_MMPU_GROUP_Type GLCDC;    /*!< (@ 0x00000700) GLCDC MMPU Registers                                       */
10423     __IOM R_MPU_MMPU_GROUP_Type DRW;      /*!< (@ 0x00000900) DRW MMPU Registers                                         */
10424     __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers                                    */
10425     __IOM R_MPU_MMPU_GROUP_Type CEU;      /*!< (@ 0x00000D00) CEU MMPU Registers                                         */
10426     __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers                                    */
10427     __IOM R_MPU_MMPU_GROUP_Type NPU;      /*!< (@ 0x00001100) NPU MMPU Registers                                         */
10428 } R_MPU_MMPU_Type;                        /*!< Size = 4864 (0x1300)                                                      */
10429 
10430 /* =========================================================================================================================== */
10431 /* ================                                        R_MPU_SPMON                                        ================ */
10432 /* =========================================================================================================================== */
10433 
10434 /**
10435  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
10436  */
10437 
10438 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
10439 {
10440     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
10441 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
10442 
10443 /* =========================================================================================================================== */
10444 /* ================                                          R_MSTP                                           ================ */
10445 /* =========================================================================================================================== */
10446 
10447 /**
10448  * @brief System-Module Stop (R_MSTP)
10449  */
10450 
10451 typedef struct                          /*!< (@ 0x40203000) R_MSTP Structure                                           */
10452 {
10453     union
10454     {
10455         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
10456 
10457         struct
10458         {
10459             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10460             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10461             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10462             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10463             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10464             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10465             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10466             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10467             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10468             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10469             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10470                                          *   usage.                                                                    */
10471             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10472                                          *   usage.                                                                    */
10473             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10474                                          *   usage.                                                                    */
10475             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10476                                          *   usage.                                                                    */
10477             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10478                                          *   usage.                                                                    */
10479             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10480                                          *   usage.                                                                    */
10481             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10482                                          *   usage.                                                                    */
10483             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10484                                          *   usage.                                                                    */
10485             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10486                                          *   usage.                                                                    */
10487             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10488                                          *   usage.                                                                    */
10489             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10490                                          *   usage.                                                                    */
10491             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10492                                          *   usage.                                                                    */
10493             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10494                                          *   usage.                                                                    */
10495             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10496                                          *   usage.                                                                    */
10497             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10498                                          *   usage.                                                                    */
10499             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10500                                          *   usage.                                                                    */
10501             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10502                                          *   usage.                                                                    */
10503             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10504                                          *   usage.                                                                    */
10505             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10506                                          *   usage.                                                                    */
10507             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10508                                          *   usage.                                                                    */
10509             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10510                                          *   usage.                                                                    */
10511             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10512                                          *   usage.                                                                    */
10513         } MSTPCRA_b;
10514     };
10515 
10516     union
10517     {
10518         __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */
10519 
10520         struct
10521         {
10522             __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10523             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10524             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10525             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10526             __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10527             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10528             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10529             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10530             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10531             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10532             __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10533                                          *   usage.                                                                    */
10534             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10535                                          *   usage.                                                                    */
10536             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10537                                          *   usage.                                                                    */
10538             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10539                                          *   usage.                                                                    */
10540             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10541                                          *   usage.                                                                    */
10542             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10543                                          *   usage.                                                                    */
10544             __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10545                                          *   usage.                                                                    */
10546             __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10547                                          *   usage.                                                                    */
10548             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10549                                          *   usage.                                                                    */
10550             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10551                                          *   usage.                                                                    */
10552             __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10553                                          *   usage.                                                                    */
10554             __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10555                                          *   usage.                                                                    */
10556             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10557                                          *   usage.                                                                    */
10558             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10559                                          *   usage.                                                                    */
10560             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10561                                          *   usage.                                                                    */
10562             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10563                                          *   usage.                                                                    */
10564             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10565                                          *   usage.                                                                    */
10566             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10567                                          *   usage.                                                                    */
10568             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10569                                          *   usage.                                                                    */
10570             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10571                                          *   usage.                                                                    */
10572             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10573                                          *   usage.                                                                    */
10574             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10575                                          *   usage.                                                                    */
10576         } MSTPCRB_b;
10577     };
10578 
10579     union
10580     {
10581         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
10582 
10583         struct
10584         {
10585             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10586             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10587             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10588             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10589             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10590             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10591             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10592             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10593             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10594             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10595             __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10596                                          *   usage.                                                                    */
10597             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10598                                          *   usage.                                                                    */
10599             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10600                                          *   usage.                                                                    */
10601             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10602                                          *   usage.                                                                    */
10603             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10604                                          *   usage.                                                                    */
10605             __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10606                                          *   usage.                                                                    */
10607             __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10608                                          *   usage.                                                                    */
10609             __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10610                                          *   usage.                                                                    */
10611             __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10612                                          *   usage.                                                                    */
10613             __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10614                                          *   usage.                                                                    */
10615             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10616                                          *   usage.                                                                    */
10617             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10618                                          *   usage.                                                                    */
10619             __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10620                                          *   usage.                                                                    */
10621             __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10622                                          *   usage.                                                                    */
10623             __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10624                                          *   usage.                                                                    */
10625             __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10626                                          *   usage.                                                                    */
10627             __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10628                                          *   usage.                                                                    */
10629             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10630                                          *   usage.                                                                    */
10631             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10632                                          *   usage.                                                                    */
10633             __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10634                                          *   usage.                                                                    */
10635             __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10636                                          *   usage.                                                                    */
10637             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10638                                          *   usage.                                                                    */
10639         } MSTPCRC_b;
10640     };
10641 
10642     union
10643     {
10644         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
10645 
10646         struct
10647         {
10648             __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10649             __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10650             __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10651             __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10652             __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10653             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10654             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10655             __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10656             __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10657             __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10658             __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10659                                          *   usage.                                                                    */
10660             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10661                                          *   usage.                                                                    */
10662             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10663                                          *   usage.                                                                    */
10664             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10665                                          *   usage.                                                                    */
10666             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10667                                          *   usage.                                                                    */
10668             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10669                                          *   usage.                                                                    */
10670             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10671                                          *   usage.                                                                    */
10672             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10673                                          *   usage.                                                                    */
10674             __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10675                                          *   usage.                                                                    */
10676             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10677                                          *   usage.                                                                    */
10678             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10679                                          *   usage.                                                                    */
10680             __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10681                                          *   usage.                                                                    */
10682             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10683                                          *   usage.                                                                    */
10684             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10685                                          *   usage.                                                                    */
10686             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10687                                          *   usage.                                                                    */
10688             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10689                                          *   usage.                                                                    */
10690             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10691                                          *   usage.                                                                    */
10692             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10693                                          *   usage.                                                                    */
10694             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10695                                          *   usage.                                                                    */
10696             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10697                                          *   usage.                                                                    */
10698             __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10699                                          *   usage.                                                                    */
10700             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10701                                          *   usage.                                                                    */
10702         } MSTPCRD_b;
10703     };
10704 
10705     union
10706     {
10707         union
10708         {
10709             __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */
10710 
10711             struct
10712             {
10713                 __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10714                 __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10715                 __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10716                 __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10717                 __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10718                 __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10719                 __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10720                 __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10721                 __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10722                 __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10723                 __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10724                                              *   usage.                                                                    */
10725                 __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10726                                              *   usage.                                                                    */
10727                 __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10728                                              *   usage.                                                                    */
10729                 __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10730                                              *   usage.                                                                    */
10731                 __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10732                                              *   usage.                                                                    */
10733                 __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10734                                              *   usage.                                                                    */
10735                 __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10736                                              *   usage.                                                                    */
10737                 __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10738                                              *   usage.                                                                    */
10739                 __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10740                                              *   usage.                                                                    */
10741                 __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10742                                              *   usage.                                                                    */
10743                 __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10744                                              *   usage.                                                                    */
10745                 __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10746                                              *   usage.                                                                    */
10747                 __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10748                                              *   usage.                                                                    */
10749                 __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10750                                              *   usage.                                                                    */
10751                 __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10752                                              *   usage.                                                                    */
10753                 __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10754                                              *   usage.                                                                    */
10755                 __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10756                                              *   usage.                                                                    */
10757                 __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10758                                              *   usage.                                                                    */
10759                 __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10760                                              *   usage.                                                                    */
10761                 __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10762                                              *   usage.                                                                    */
10763                 __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10764                                              *   usage.                                                                    */
10765                 __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10766                                              *   usage.                                                                    */
10767             } MSTPCRE_b;
10768         };
10769 
10770         union
10771         {
10772             __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */
10773 
10774             struct
10775             {
10776                 __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
10777                 __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
10778                 __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
10779                 uint16_t                : 4;
10780                 __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
10781                 __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
10782             } LSMRWDIS_b;
10783         };
10784     };
10785 } R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */
10786 
10787 /* =========================================================================================================================== */
10788 /* ================                                          R_PORT0                                          ================ */
10789 /* =========================================================================================================================== */
10790 
10791 /**
10792  * @brief I/O Ports (R_PORT0)
10793  */
10794 
10795 typedef struct                         /*!< (@ 0x40400000) R_PORT0 Structure                                          */
10796 {
10797     union
10798     {
10799         union
10800         {
10801             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
10802 
10803             struct
10804             {
10805                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
10806                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
10807             } PCNTR1_b;
10808         };
10809 
10810         struct
10811         {
10812             union
10813             {
10814                 __IOM uint16_t PDR;           /*!< (@ 0x00000000) Data direction register                                    */
10815 
10816                 struct
10817                 {
10818                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
10819                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
10820                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
10821                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
10822                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
10823                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
10824                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
10825                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
10826                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
10827                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
10828                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
10829                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
10830                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
10831                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
10832                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
10833                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
10834                 } PDR_b;
10835             };
10836 
10837             union
10838             {
10839                 __IOM uint16_t PODR;           /*!< (@ 0x00000002) Output data register                                       */
10840 
10841                 struct
10842                 {
10843                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
10844                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
10845                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
10846                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
10847                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
10848                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
10849                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
10850                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
10851                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
10852                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
10853                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
10854                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
10855                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
10856                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
10857                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
10858                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
10859                 } PODR_b;
10860             };
10861         };
10862     };
10863 
10864     union
10865     {
10866         union
10867         {
10868             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
10869 
10870             struct
10871             {
10872                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
10873                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
10874             } PCNTR2_b;
10875         };
10876 
10877         struct
10878         {
10879             union
10880             {
10881                 __IM uint16_t PIDR;           /*!< (@ 0x00000004) Input data register                                        */
10882 
10883                 struct
10884                 {
10885                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
10886                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
10887                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
10888                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
10889                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
10890                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
10891                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
10892                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
10893                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
10894                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
10895                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
10896                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
10897                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
10898                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
10899                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
10900                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
10901                 } PIDR_b;
10902             };
10903 
10904             union
10905             {
10906                 __IM uint16_t EIDR;           /*!< (@ 0x00000006) Event input data register                                  */
10907 
10908                 struct
10909                 {
10910                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
10911                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
10912                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
10913                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
10914                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
10915                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
10916                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
10917                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
10918                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
10919                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
10920                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
10921                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
10922                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
10923                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
10924                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
10925                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
10926                 } EIDR_b;
10927             };
10928         };
10929     };
10930 
10931     union
10932     {
10933         union
10934         {
10935             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
10936 
10937             struct
10938             {
10939                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
10940                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
10941             } PCNTR3_b;
10942         };
10943 
10944         struct
10945         {
10946             union
10947             {
10948                 __OM uint16_t POSR;           /*!< (@ 0x00000008) Output reset register                                      */
10949 
10950                 struct
10951                 {
10952                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
10953                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
10954                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
10955                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
10956                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
10957                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
10958                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
10959                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
10960                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
10961                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
10962                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
10963                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
10964                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
10965                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
10966                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
10967                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
10968                 } POSR_b;
10969             };
10970 
10971             union
10972             {
10973                 __OM uint16_t PORR;           /*!< (@ 0x0000000A) Output set register                                        */
10974 
10975                 struct
10976                 {
10977                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
10978                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
10979                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
10980                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
10981                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
10982                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
10983                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
10984                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
10985                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
10986                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
10987                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
10988                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
10989                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
10990                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
10991                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
10992                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
10993                 } PORR_b;
10994             };
10995         };
10996     };
10997 
10998     union
10999     {
11000         union
11001         {
11002             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
11003 
11004             struct
11005             {
11006                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
11007                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
11008             } PCNTR4_b;
11009         };
11010 
11011         struct
11012         {
11013             union
11014             {
11015                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000C) Event output reset register                                */
11016 
11017                 struct
11018                 {
11019                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
11020                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
11021                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
11022                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
11023                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
11024                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
11025                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
11026                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
11027                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
11028                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
11029                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
11030                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
11031                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
11032                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
11033                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
11034                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
11035                 } EOSR_b;
11036             };
11037 
11038             union
11039             {
11040                 __IOM uint16_t EORR;           /*!< (@ 0x0000000E) Event output set register                                  */
11041 
11042                 struct
11043                 {
11044                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
11045                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
11046                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
11047                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
11048                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
11049                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
11050                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
11051                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
11052                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
11053                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
11054                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
11055                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
11056                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
11057                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
11058                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
11059                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
11060                 } EORR_b;
11061             };
11062         };
11063     };
11064 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
11065 
11066 /* =========================================================================================================================== */
11067 /* ================                                           R_PFS                                           ================ */
11068 /* =========================================================================================================================== */
11069 
11070 /**
11071  * @brief I/O Ports-PFS (R_PFS)
11072  */
11073 
11074 typedef struct                         /*!< (@ 0x40400800) R_PFS Structure                                            */
11075 {
11076     __IOM R_PFS_PORT_Type PORT[15];    /*!< (@ 0x00000000) Port [0..14]                                               */
11077 } R_PFS_Type;                          /*!< Size = 960 (0x3c0)                                                        */
11078 
11079 /* =========================================================================================================================== */
11080 /* ================                                          R_PMISC                                          ================ */
11081 /* =========================================================================================================================== */
11082 
11083 /**
11084  * @brief I/O Ports-MISC (R_PMISC)
11085  */
11086 
11087 typedef struct                         /*!< (@ 0x40400D00) R_PMISC Structure                                          */
11088 {
11089     union
11090     {
11091         __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
11092 
11093         struct
11094         {
11095             uint8_t                : 4;
11096             __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
11097             uint8_t                : 3;
11098         } PFENET_b;
11099     };
11100     __IM uint8_t  RESERVED;
11101     __IM uint16_t RESERVED1[5];
11102 
11103     union
11104     {
11105         __IOM uint8_t PWPR;            /*!< (@ 0x0000000C) Write-Protect Register                                     */
11106 
11107         struct
11108         {
11109             uint8_t             : 6;
11110             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
11111             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
11112         } PWPR_b;
11113     };
11114     __IM uint8_t  RESERVED2;
11115     __IM uint16_t RESERVED3[3];
11116 
11117     union
11118     {
11119         __IOM uint8_t PWPRS;           /*!< (@ 0x00000014) Write-Protect Register for Secure                          */
11120 
11121         struct
11122         {
11123             uint8_t             : 6;
11124             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
11125             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
11126         } PWPRS_b;
11127     };
11128     __IM uint8_t             RESERVED4;
11129     __IM uint16_t            RESERVED5[13];
11130     __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register                         */
11131 } R_PMISC_Type;                         /*!< Size = 108 (0x6c)                                                         */
11132 
11133 /* =========================================================================================================================== */
11134 /* ================                                           R_RTC                                           ================ */
11135 /* =========================================================================================================================== */
11136 
11137 /**
11138  * @brief Realtime Clock (R_RTC)
11139  */
11140 
11141 typedef struct                         /*!< (@ 0x40202000) R_RTC Structure                                            */
11142 {
11143     union
11144     {
11145         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
11146 
11147         struct
11148         {
11149             __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
11150             __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
11151             __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
11152             __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
11153             __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
11154             __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
11155             __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
11156             uint8_t            : 1;
11157         } R64CNT_b;
11158     };
11159     __IM uint8_t RESERVED;
11160 
11161     union
11162     {
11163         union
11164         {
11165             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
11166 
11167             struct
11168             {
11169                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
11170                                           *   counter b7 to b0.                                                         */
11171             } BCNT0_b;
11172         };
11173 
11174         union
11175         {
11176             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
11177 
11178             struct
11179             {
11180                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
11181                                           *   a carry is generated, 1 is added to the tens place.                       */
11182                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
11183                 uint8_t             : 1;
11184             } RSECCNT_b;
11185         };
11186     };
11187     __IM uint8_t RESERVED1;
11188 
11189     union
11190     {
11191         union
11192         {
11193             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
11194 
11195             struct
11196             {
11197                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
11198                                           *   counter b15 to b8.                                                        */
11199             } BCNT1_b;
11200         };
11201 
11202         union
11203         {
11204             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
11205 
11206             struct
11207             {
11208                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
11209                                           *   a carry is generated, 1 is added to the tens place.                       */
11210                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
11211                 uint8_t             : 1;
11212             } RMINCNT_b;
11213         };
11214     };
11215     __IM uint8_t RESERVED2;
11216 
11217     union
11218     {
11219         union
11220         {
11221             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
11222 
11223             struct
11224             {
11225                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
11226                                           *   counter b23 to b16.                                                       */
11227             } BCNT2_b;
11228         };
11229 
11230         union
11231         {
11232             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
11233 
11234             struct
11235             {
11236                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
11237                                          *   carry is generated, 1 is added to the tens place.                         */
11238                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
11239                                          *   the ones place.                                                           */
11240                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
11241                 uint8_t          : 1;
11242             } RHRCNT_b;
11243         };
11244     };
11245     __IM uint8_t RESERVED3;
11246 
11247     union
11248     {
11249         union
11250         {
11251             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
11252 
11253             struct
11254             {
11255                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
11256                                           *   counter b31 to b24.                                                       */
11257             } BCNT3_b;
11258         };
11259 
11260         union
11261         {
11262             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
11263 
11264             struct
11265             {
11266                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
11267                 uint8_t            : 5;
11268             } RWKCNT_b;
11269         };
11270     };
11271     __IM uint8_t RESERVED4;
11272 
11273     union
11274     {
11275         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
11276 
11277         struct
11278         {
11279             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
11280                                         *   is generated, 1 is added to the tens place.                               */
11281             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
11282                                         *   ones place.                                                               */
11283             uint8_t : 2;
11284         } RDAYCNT_b;
11285     };
11286     __IM uint8_t RESERVED5;
11287 
11288     union
11289     {
11290         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
11291 
11292         struct
11293         {
11294             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
11295                                         *   a carry is generated, 1 is added to the tens place.                       */
11296             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
11297                                         *   the ones place.                                                           */
11298             uint8_t : 3;
11299         } RMONCNT_b;
11300     };
11301     __IM uint8_t RESERVED6;
11302 
11303     union
11304     {
11305         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
11306 
11307         struct
11308         {
11309             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
11310                                         *   carry is generated, 1 is added to the tens place.                         */
11311             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
11312                                         *   ones place. When a carry is generated in the tens place,
11313                                         *   1 is added to the hundreds place.                                         */
11314             uint16_t : 8;
11315         } RYRCNT_b;
11316     };
11317 
11318     union
11319     {
11320         union
11321         {
11322             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
11323 
11324             struct
11325             {
11326                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
11327                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
11328             } BCNT0AR_b;
11329         };
11330 
11331         union
11332         {
11333             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
11334 
11335             struct
11336             {
11337                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
11338                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
11339                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
11340             } RSECAR_b;
11341         };
11342     };
11343     __IM uint8_t RESERVED7;
11344 
11345     union
11346     {
11347         union
11348         {
11349             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
11350 
11351             struct
11352             {
11353                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
11354                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
11355             } BCNT1AR_b;
11356         };
11357 
11358         union
11359         {
11360             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
11361 
11362             struct
11363             {
11364                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
11365                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
11366                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
11367             } RMINAR_b;
11368         };
11369     };
11370     __IM uint8_t RESERVED8;
11371 
11372     union
11373     {
11374         union
11375         {
11376             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
11377 
11378             struct
11379             {
11380                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
11381                                             *   counter b23 to b16.                                                       */
11382             } BCNT2AR_b;
11383         };
11384 
11385         union
11386         {
11387             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
11388 
11389             struct
11390             {
11391                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
11392                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
11393                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
11394                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
11395             } RHRAR_b;
11396         };
11397     };
11398     __IM uint8_t RESERVED9;
11399 
11400     union
11401     {
11402         union
11403         {
11404             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
11405 
11406             struct
11407             {
11408                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
11409                                             *   counter b31 to b24.                                                       */
11410             } BCNT3AR_b;
11411         };
11412 
11413         union
11414         {
11415             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
11416 
11417             struct
11418             {
11419                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
11420                 uint8_t            : 4;
11421                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
11422             } RWKAR_b;
11423         };
11424     };
11425     __IM uint8_t RESERVED10;
11426 
11427     union
11428     {
11429         union
11430         {
11431             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
11432 
11433             struct
11434             {
11435                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
11436                                         *   for setting the alarm enable corresponding to 32-bit binary
11437                                         *   counter b7 to b0.                                                         */
11438             } BCNT0AER_b;
11439         };
11440 
11441         union
11442         {
11443             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
11444 
11445             struct
11446             {
11447                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
11448                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
11449                 uint8_t              : 1;
11450                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
11451             } RDAYAR_b;
11452         };
11453     };
11454     __IM uint8_t RESERVED11;
11455 
11456     union
11457     {
11458         union
11459         {
11460             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
11461 
11462             struct
11463             {
11464                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
11465                                         *   for setting the alarm enable corresponding to 32-bit binary
11466                                         *   counter b15 to b8.                                                        */
11467             } BCNT1AER_b;
11468         };
11469 
11470         union
11471         {
11472             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
11473 
11474             struct
11475             {
11476                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
11477                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
11478                 uint8_t             : 2;
11479                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
11480             } RMONAR_b;
11481         };
11482     };
11483     __IM uint8_t RESERVED12;
11484 
11485     union
11486     {
11487         union
11488         {
11489             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
11490 
11491             struct
11492             {
11493                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
11494                                          *   for setting the alarm enable corresponding to 32-bit binary
11495                                          *   counter b23 to b16.                                                       */
11496                 uint16_t : 8;
11497             } BCNT2AER_b;
11498         };
11499 
11500         union
11501         {
11502             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
11503 
11504             struct
11505             {
11506                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
11507                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
11508                 uint16_t            : 8;
11509             } RYRAR_b;
11510         };
11511     };
11512 
11513     union
11514     {
11515         union
11516         {
11517             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
11518 
11519             struct
11520             {
11521                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
11522                                         *   for setting the alarm enable corresponding to 32-bit binary
11523                                         *   counter b31 to b24.                                                       */
11524             } BCNT3AER_b;
11525         };
11526 
11527         union
11528         {
11529             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
11530 
11531             struct
11532             {
11533                 uint8_t           : 7;
11534                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
11535             } RYRAREN_b;
11536         };
11537     };
11538     __IM uint8_t  RESERVED13;
11539     __IM uint16_t RESERVED14;
11540 
11541     union
11542     {
11543         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
11544 
11545         struct
11546         {
11547             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
11548             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
11549             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
11550             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
11551             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
11552         } RCR1_b;
11553     };
11554     __IM uint8_t RESERVED15;
11555 
11556     union
11557     {
11558         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
11559 
11560         struct
11561         {
11562             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
11563             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
11564             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
11565             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
11566             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
11567                                         *   the setting of this bit is disabled.)                                     */
11568             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
11569                                         *   is selected, the setting of this bit is disabled.)                        */
11570             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
11571             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
11572         } RCR2_b;
11573     };
11574     __IM uint8_t  RESERVED16;
11575     __IM uint16_t RESERVED17;
11576 
11577     union
11578     {
11579         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
11580 
11581         struct
11582         {
11583             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
11584             uint8_t              : 6;
11585             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
11586         } RCR4_b;
11587     };
11588     __IM uint8_t RESERVED18;
11589 
11590     union
11591     {
11592         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
11593 
11594         struct
11595         {
11596             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
11597                                         *   clock from the LOCOclock, this bit sets the comparison
11598                                         *   value of the 128-Hz clock cycle.                                          */
11599             uint16_t : 15;
11600         } RFRH_b;
11601     };
11602 
11603     union
11604     {
11605         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
11606 
11607         struct
11608         {
11609             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
11610                                         *   clock from the main clock, this bit sets the comparison
11611                                         *   value of the 128-Hz clock cycle.                                          */
11612         } RFRL_b;
11613     };
11614 
11615     union
11616     {
11617         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
11618 
11619         struct
11620         {
11621             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
11622                                         *   from the prescaler.                                                       */
11623             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
11624         } RADJ_b;
11625     };
11626     __IM uint8_t           RESERVED19;
11627     __IM uint16_t          RESERVED20[8];
11628     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
11629     __IM uint16_t          RESERVED21[5];
11630     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
11631 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
11632 
11633 /* =========================================================================================================================== */
11634 /* ================                                          R_SCI0                                           ================ */
11635 /* =========================================================================================================================== */
11636 
11637 /**
11638  * @brief Serial Communications Interface (R_SCI0)
11639  */
11640 
11641 typedef struct                         /*!< (@ 0x40358000) R_SCI0 Structure                                           */
11642 {
11643     union
11644     {
11645         union
11646         {
11647             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
11648 
11649             struct
11650             {
11651                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
11652                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
11653                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
11654                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
11655                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
11656                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
11657                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
11658             } SMR_b;
11659         };
11660 
11661         union
11662         {
11663             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
11664 
11665             struct
11666             {
11667                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
11668                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
11669                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
11670                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
11671                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
11672                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
11673             } SMR_SMCI_b;
11674         };
11675     };
11676 
11677     union
11678     {
11679         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
11680 
11681         struct
11682         {
11683             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
11684         } BRR_b;
11685     };
11686 
11687     union
11688     {
11689         union
11690         {
11691             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
11692 
11693             struct
11694             {
11695                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
11696                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
11697                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
11698                                          *   mode when SMR.MP = 1)                                                     */
11699                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
11700                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
11701                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
11702                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
11703             } SCR_b;
11704         };
11705 
11706         union
11707         {
11708             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
11709 
11710             struct
11711             {
11712                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
11713                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
11714                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
11715                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
11716                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
11717                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
11718                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
11719             } SCR_SMCI_b;
11720         };
11721     };
11722 
11723     union
11724     {
11725         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
11726 
11727         struct
11728         {
11729             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
11730         } TDR_b;
11731     };
11732 
11733     union
11734     {
11735         union
11736         {
11737             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
11738 
11739             struct
11740             {
11741                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
11742                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
11743                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
11744                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
11745                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
11746                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
11747                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
11748                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
11749             } SSR_b;
11750         };
11751 
11752         union
11753         {
11754             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
11755 
11756             struct
11757             {
11758                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
11759                                          *   multi-processor) and FIFO selected)                                       */
11760                 uint8_t            : 1;
11761                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
11762                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
11763                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
11764                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
11765                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
11766                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
11767             } SSR_FIFO_b;
11768         };
11769 
11770         union
11771         {
11772             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
11773 
11774             struct
11775             {
11776                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
11777                                          *   card interface mode.                                                      */
11778                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
11779                                          *   mode.                                                                     */
11780                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
11781                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
11782                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
11783                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
11784                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
11785                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
11786             } SSR_SMCI_b;
11787         };
11788     };
11789 
11790     union
11791     {
11792         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
11793 
11794         struct
11795         {
11796             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
11797         } RDR_b;
11798     };
11799 
11800     union
11801     {
11802         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
11803 
11804         struct
11805         {
11806             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
11807             uint8_t            : 1;
11808             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
11809                                         *   operation is to be in simple I2C mode.                                    */
11810             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
11811                                         *   setting is invalid and a fixed data length of 8 bits is
11812                                         *   used in modes other than asynchronous mode.Set this bit
11813                                         *   to 1 if operation is to be in simple I2C mode.                            */
11814             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
11815             uint8_t            : 2;
11816             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
11817                                         *   in combination with the SMR.BCP[1:0] bits                                 */
11818         } SCMR_b;
11819     };
11820 
11821     union
11822     {
11823         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
11824 
11825         struct
11826         {
11827             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
11828                                         *   asynchronous mode).                                                       */
11829             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
11830                                         *   mode).                                                                    */
11831             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
11832             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
11833                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
11834             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
11835                                         *   mode)                                                                     */
11836             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
11837                                         *   be 0 without simple I2C mode and asynchronous mode.)In
11838                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
11839                                         *   for RXDn/TxDn input.                                                      */
11840             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
11841                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
11842             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
11843                                         *   in asynchronous mode)                                                     */
11844         } SEMR_b;
11845     };
11846 
11847     union
11848     {
11849         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
11850 
11851         struct
11852         {
11853             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
11854             uint8_t            : 5;
11855         } SNFR_b;
11856     };
11857 
11858     union
11859     {
11860         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
11861 
11862         struct
11863         {
11864             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
11865             uint8_t             : 2;
11866             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
11867                                         *   signal from the on-chip baud rate generator.                              */
11868         } SIMR1_b;
11869     };
11870 
11871     union
11872     {
11873         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
11874 
11875         struct
11876         {
11877             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
11878             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
11879             uint8_t               : 3;
11880             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
11881             uint8_t               : 2;
11882         } SIMR2_b;
11883     };
11884 
11885     union
11886     {
11887         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
11888 
11889         struct
11890         {
11891             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
11892             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
11893             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
11894             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
11895                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
11896             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
11897             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
11898         } SIMR3_b;
11899     };
11900 
11901     union
11902     {
11903         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
11904 
11905         struct
11906         {
11907             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
11908             uint8_t              : 7;
11909         } SISR_b;
11910     };
11911 
11912     union
11913     {
11914         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
11915 
11916         struct
11917         {
11918             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
11919             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
11920             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
11921             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
11922             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
11923             uint8_t              : 1;
11924             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
11925             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
11926         } SPMR_b;
11927     };
11928 
11929     union
11930     {
11931         union
11932         {
11933             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
11934 
11935             struct
11936             {
11937                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
11938             } TDRHL_b;
11939         };
11940 
11941         union
11942         {
11943             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
11944 
11945             struct
11946             {
11947                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
11948                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
11949                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
11950                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
11951                 uint16_t : 6;
11952             } FTDRHL_b;
11953         };
11954 
11955         struct
11956         {
11957             union
11958             {
11959                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
11960 
11961                 struct
11962                 {
11963                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
11964                                              *   mode(including multi-processor) or clock synchronous mode,
11965                                              *   and FIFO selected)                                                        */
11966                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
11967                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
11968                     uint8_t : 6;
11969                 } FTDRH_b;
11970             };
11971 
11972             union
11973             {
11974                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
11975 
11976                 struct
11977                 {
11978                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
11979                                              *   mode(including multi-processor) or clock synchronous mode,
11980                                              *   and FIFO selected)                                                        */
11981                 } FTDRL_b;
11982             };
11983         };
11984     };
11985 
11986     union
11987     {
11988         union
11989         {
11990             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
11991 
11992             struct
11993             {
11994                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
11995             } RDRHL_b;
11996         };
11997 
11998         union
11999         {
12000             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
12001 
12002             struct
12003             {
12004                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
12005                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12006                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
12007                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
12008                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
12009                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
12010                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
12011                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
12012                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
12013                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
12014                 uint16_t           : 1;
12015             } FRDRHL_b;
12016         };
12017 
12018         struct
12019         {
12020             union
12021             {
12022                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
12023 
12024                 struct
12025                 {
12026                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
12027                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12028                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
12029                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
12030                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
12031                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
12032                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
12033                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
12034                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
12035                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
12036                     uint8_t           : 1;
12037                 } FRDRH_b;
12038             };
12039 
12040             union
12041             {
12042                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
12043 
12044                 struct
12045                 {
12046                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
12047                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
12048                                              *   When reading both of FRDRH register and FRDRL register,
12049                                              *   please read by an order of the FRDRH register and the FRDRL
12050                                              *   register.                                                                 */
12051                 } FRDRL_b;
12052             };
12053         };
12054     };
12055 
12056     union
12057     {
12058         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
12059 
12060         struct
12061         {
12062             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
12063         } MDDR_b;
12064     };
12065 
12066     union
12067     {
12068         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
12069 
12070         struct
12071         {
12072             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
12073             uint8_t             : 2;
12074             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
12075             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
12076             uint8_t             : 1;
12077             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
12078                                         *   multi-processor)                                                          */
12079             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
12080                                         *   mode(including multi-processor)                                           */
12081         } DCCR_b;
12082     };
12083 
12084     union
12085     {
12086         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
12087 
12088         struct
12089         {
12090             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
12091                                         *   multi-processor) or clock synchronous mode)                               */
12092             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
12093             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
12094             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
12095                                         *   reception data ready, the interrupt request is selected.)                 */
12096             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
12097                                         *   mode(including multi-processor) or clock synchronous mode)                */
12098             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
12099                                         *   mode(including multi-processor) or clock synchronous mode)                */
12100             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
12101                                         *   in asynchronous mode(including multi-processor) or clock
12102                                         *   synchronous mode)                                                         */
12103         } FCR_b;
12104     };
12105 
12106     union
12107     {
12108         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
12109 
12110         struct
12111         {
12112             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
12113                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
12114                                         *   mode(including multi-processor) or clock synchronous mode,
12115                                         *   while FCR.FM=1)                                                           */
12116             uint16_t        : 3;
12117             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
12118                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
12119                                         *   mode(including multi-processor) or clock synchronous mode,
12120                                         *   while FCR.FM=1)                                                           */
12121             uint16_t : 3;
12122         } FDR_b;
12123     };
12124 
12125     union
12126     {
12127         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
12128 
12129         struct
12130         {
12131             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
12132                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12133             uint16_t           : 1;
12134             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
12135                                         *   a framing error among the receive data stored in the receive
12136                                         *   FIFO data register (FRDRH and FRDRL).                                     */
12137             uint16_t           : 1;
12138             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
12139                                         *   a parity error among the receive data stored in the receive
12140                                         *   FIFO data register (FRDRH and FRDRL).                                     */
12141             uint16_t : 3;
12142         } LSR_b;
12143     };
12144 
12145     union
12146     {
12147         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
12148 
12149         struct
12150         {
12151             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
12152                                         *   wake-up function                                                          */
12153             uint16_t : 7;
12154         } CDR_b;
12155     };
12156 
12157     union
12158     {
12159         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
12160 
12161         struct
12162         {
12163             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
12164                                         *   is shown.)                                                                */
12165             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
12166                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
12167             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
12168                                         *   of SPB2DT is output to TxD terminal.)                                     */
12169             uint8_t            : 1;
12170             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
12171             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
12172             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
12173             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
12174         } SPTR_b;
12175     };
12176 
12177     union
12178     {
12179         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
12180 
12181         struct
12182         {
12183             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
12184             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
12185             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
12186             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
12187         } ACTR_b;
12188     };
12189     __IM uint16_t RESERVED;
12190 
12191     union
12192     {
12193         __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
12194 
12195         struct
12196         {
12197             __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
12198             uint8_t            : 7;
12199         } ESMER_b;
12200     };
12201 
12202     union
12203     {
12204         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
12205 
12206         struct
12207         {
12208             uint8_t             : 1;
12209             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
12210             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
12211             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
12212             uint8_t             : 4;
12213         } CR0_b;
12214     };
12215 
12216     union
12217     {
12218         __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
12219 
12220         struct
12221         {
12222             __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
12223             __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
12224             __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
12225             __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
12226             __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
12227         } CR1_b;
12228     };
12229 
12230     union
12231     {
12232         __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
12233 
12234         struct
12235         {
12236             __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
12237             uint8_t            : 1;
12238             __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
12239             __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
12240         } CR2_b;
12241     };
12242 
12243     union
12244     {
12245         __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
12246 
12247         struct
12248         {
12249             __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
12250             uint8_t            : 7;
12251         } CR3_b;
12252     };
12253 
12254     union
12255     {
12256         __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
12257 
12258         struct
12259         {
12260             __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
12261             __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
12262             uint8_t              : 2;
12263             __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
12264             uint8_t              : 3;
12265         } PCR_b;
12266     };
12267 
12268     union
12269     {
12270         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
12271 
12272         struct
12273         {
12274             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
12275             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
12276             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
12277             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
12278             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
12279             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
12280             uint8_t              : 2;
12281         } ICR_b;
12282     };
12283 
12284     union
12285     {
12286         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
12287 
12288         struct
12289         {
12290             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
12291             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
12292             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
12293             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
12294             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
12295             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
12296             uint8_t            : 2;
12297         } STR_b;
12298     };
12299 
12300     union
12301     {
12302         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
12303 
12304         struct
12305         {
12306             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
12307             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
12308             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
12309             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
12310             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
12311             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
12312             uint8_t              : 2;
12313         } STCR_b;
12314     };
12315     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
12316 
12317     union
12318     {
12319         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
12320 
12321         struct
12322         {
12323             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
12324             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
12325             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
12326             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
12327             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
12328             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
12329             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
12330             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
12331         } CF0CR_b;
12332     };
12333     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
12334     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
12335     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
12336 
12337     union
12338     {
12339         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
12340 
12341         struct
12342         {
12343             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
12344             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
12345             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
12346             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
12347             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
12348             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
12349             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
12350             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
12351         } CF1CR_b;
12352     };
12353     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
12354 
12355     union
12356     {
12357         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
12358 
12359         struct
12360         {
12361             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
12362             uint8_t            : 7;
12363         } TCR_b;
12364     };
12365 
12366     union
12367     {
12368         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
12369 
12370         struct
12371         {
12372             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
12373             uint8_t            : 1;
12374             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
12375             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
12376             uint8_t            : 1;
12377         } TMR_b;
12378     };
12379     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
12380     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
12381 } R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
12382 
12383 /* =========================================================================================================================== */
12384 /* ================                                          R_SDHI0                                          ================ */
12385 /* =========================================================================================================================== */
12386 
12387 /**
12388  * @brief SD/MMC Host Interface (R_SDHI0)
12389  */
12390 
12391 typedef struct                          /*!< (@ 0x40252000) R_SDHI0 Structure                                          */
12392 {
12393     union
12394     {
12395         __IOM uint32_t SD_CMD;          /*!< (@ 0x00000000) Command Type Register                                      */
12396 
12397         struct
12398         {
12399             __IOM uint32_t CMDIDX : 6;  /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
12400                                          *   (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
12401                                          *   SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101              */
12402             __IOM uint32_t ACMD  : 2;   /*!< [7..6] Command Type Select                                                */
12403             __IOM uint32_t RSPTP : 3;   /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
12404                                          *   in normal mode, see section 1.4.10, Example of SD_CMD Register
12405                                          *   Setting to select mode/response type.                                     */
12406             __IOM uint32_t CMDTP : 1;   /*!< [11..11] Data Mode (Command Type)                                         */
12407             __IOM uint32_t CMDRW : 1;   /*!< [12..12] Write/Read Mode (enabled when the command with data
12408                                          *   is handled)                                                               */
12409             __IOM uint32_t TRSTP : 1;   /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
12410                                          *   with data is handled)                                                     */
12411             __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
12412                                          *   transfer)                                                                 */
12413             uint32_t : 16;
12414         } SD_CMD_b;
12415     };
12416     __IM uint32_t RESERVED;
12417 
12418     union
12419     {
12420         __IOM uint32_t SD_ARG;          /*!< (@ 0x00000008) SD Command Argument Register                               */
12421 
12422         struct
12423         {
12424             __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument)              */
12425         } SD_ARG_b;
12426     };
12427 
12428     union
12429     {
12430         __IOM uint32_t SD_ARG1;          /*!< (@ 0x0000000C) SD Command Argument Register 1                             */
12431 
12432         struct
12433         {
12434             __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument)           */
12435             uint32_t               : 16;
12436         } SD_ARG1_b;
12437     };
12438 
12439     union
12440     {
12441         __IOM uint32_t SD_STOP;        /*!< (@ 0x00000010) Data Stop Register                                         */
12442 
12443         struct
12444         {
12445             __IOM uint32_t STP : 1;    /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
12446                                         *   CMD12 is issued to halt the transfer through the SD host
12447                                         *   interface.However, if a command sequence is halted because
12448                                         *   of a communications error or timeout, CMD12 is not issued.
12449                                         *   Although continued buffer access is possible even after
12450                                         *   STP has been set to 1, the buffer access error bit (ERR5
12451                                         *   or ERR4) in SD_INFO2 will be set accordingly.- When STP
12452                                         *   has been set to 1 during transfer for single block write,
12453                                         *   the access end flag is set when SD_BUF becomes emp                        */
12454             uint32_t           : 7;
12455             __IOM uint32_t SEC : 1;    /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
12456                                         *   SD_CMD is set as follows to start the command sequence
12457                                         *   while SEC is set to 1, CMD12 is automatically issued to
12458                                         *   stop multi-block transfer with the number of blocks which
12459                                         *   is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
12460                                         *   = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
12461                                         *   automatically issued, multiple block transfer)When the
12462                                         *   command sequence is halted because of a communications
12463                                         *   error or timeout, CMD12 is not automatically i                            */
12464             uint32_t : 23;
12465         } SD_STOP_b;
12466     };
12467 
12468     union
12469     {
12470         __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000014) Block Count Register                                       */
12471 
12472         struct
12473         {
12474             __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
12475                                             *   of this bit when the CBSY bit in SD_INFO2 is set to 1.                    */
12476         } SD_SECCNT_b;
12477     };
12478 
12479     union
12480     {
12481         __IM uint32_t SD_RSP10;          /*!< (@ 0x00000018) SD Card Response Register 10                               */
12482 
12483         struct
12484         {
12485             __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
12486         } SD_RSP10_b;
12487     };
12488 
12489     union
12490     {
12491         __IM uint32_t SD_RSP1;          /*!< (@ 0x0000001C) SD Card Response Register 1                                */
12492 
12493         struct
12494         {
12495             __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
12496             uint32_t              : 16;
12497         } SD_RSP1_b;
12498     };
12499 
12500     union
12501     {
12502         __IM uint32_t SD_RSP32;          /*!< (@ 0x00000020) SD Card Response Register 32                               */
12503 
12504         struct
12505         {
12506             __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
12507         } SD_RSP32_b;
12508     };
12509 
12510     union
12511     {
12512         __IM uint32_t SD_RSP3;          /*!< (@ 0x00000024) SD Card Response Register 3                                */
12513 
12514         struct
12515         {
12516             __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
12517             uint32_t              : 16;
12518         } SD_RSP3_b;
12519     };
12520 
12521     union
12522     {
12523         __IM uint32_t SD_RSP54;          /*!< (@ 0x00000028) SD Card Response Register 54                               */
12524 
12525         struct
12526         {
12527             __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
12528         } SD_RSP54_b;
12529     };
12530 
12531     union
12532     {
12533         __IM uint32_t SD_RSP5;          /*!< (@ 0x0000002C) SD Card Response Register 5                                */
12534 
12535         struct
12536         {
12537             __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
12538             uint32_t              : 16;
12539         } SD_RSP5_b;
12540     };
12541 
12542     union
12543     {
12544         __IM uint32_t SD_RSP76;          /*!< (@ 0x00000030) SD Card Response Register 76                               */
12545 
12546         struct
12547         {
12548             __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC                           */
12549             uint32_t               : 8;
12550         } SD_RSP76_b;
12551     };
12552 
12553     union
12554     {
12555         __IM uint32_t SD_RSP7;         /*!< (@ 0x00000034) SD Card Response Register 7                                */
12556 
12557         struct
12558         {
12559             __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC                            */
12560             uint32_t              : 24;
12561         } SD_RSP7_b;
12562     };
12563 
12564     union
12565     {
12566         __IOM uint32_t SD_INFO1;        /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1                          */
12567 
12568         struct
12569         {
12570             __IOM uint32_t RSPEND  : 1; /*!< [0..0] Response End Detection                                             */
12571             uint32_t               : 1;
12572             __IOM uint32_t ACEND   : 1; /*!< [2..2] Access End                                                         */
12573             __IOM uint32_t SDCDRM  : 1; /*!< [3..3] SDnCD Card Removal                                                 */
12574             __IOM uint32_t SDCDIN  : 1; /*!< [4..4] SDnCD Card Insertion                                               */
12575             __IM uint32_t  SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state                                          */
12576             uint32_t               : 1;
12577             __IM uint32_t  SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state                                          */
12578             __IOM uint32_t SDD3RM  : 1; /*!< [8..8] SDnDAT3 Card Removal                                               */
12579             __IOM uint32_t SDD3IN  : 1; /*!< [9..9] SDnDAT3 Card Insertion                                             */
12580             __IM uint32_t  SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State                                      */
12581             uint32_t               : 21;
12582         } SD_INFO1_b;
12583     };
12584 
12585     union
12586     {
12587         __IOM uint32_t SD_INFO2;             /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2                          */
12588 
12589         struct
12590         {
12591             __IOM uint32_t CMDE    : 1;      /*!< [0..0] Command Error                                                      */
12592             __IOM uint32_t CRCE    : 1;      /*!< [1..1] CRC Error                                                          */
12593             __IOM uint32_t ENDE    : 1;      /*!< [2..2] END Error                                                          */
12594             __IOM uint32_t DTO     : 1;      /*!< [3..3] Data Timeout                                                       */
12595             __IOM uint32_t ILW     : 1;      /*!< [4..4] SD_BUF Illegal Write Access                                        */
12596             __IOM uint32_t ILR     : 1;      /*!< [5..5] SD_BUF Illegal Read Access                                         */
12597             __IOM uint32_t RSPTO   : 1;      /*!< [6..6] Response Timeout                                                   */
12598             __IM uint32_t  SDD0MON : 1;      /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
12599                                               *   by SD_PORTSEL.                                                            */
12600             __IOM uint32_t BRE          : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
12601             __IOM uint32_t BWE          : 1; /*!< [9..9] SD_BUF Write Enable                                                */
12602             uint32_t                    : 3;
12603             __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
12604                                               *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
12605                                               *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
12606                                               *   cycles of SDCLK have elapsed after setting of the CBSY
12607                                               *   bit to 0 due to completion of the command sequence.                       */
12608             __IM uint32_t  CBSY : 1;         /*!< [14..14] Command Type Register Busy                                       */
12609             __IOM uint32_t ILA  : 1;         /*!< [15..15] Illegal Access Error                                             */
12610             uint32_t            : 16;
12611         } SD_INFO2_b;
12612     };
12613 
12614     union
12615     {
12616         __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register                           */
12617 
12618         struct
12619         {
12620             __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask                                */
12621             uint32_t               : 1;
12622             __IOM uint32_t ACENDM  : 1; /*!< [2..2] Access End Interrupt Request Mask                                  */
12623             __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask                          */
12624             __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask                        */
12625             uint32_t               : 3;
12626             __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask                        */
12627             __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask                      */
12628             uint32_t               : 22;
12629         } SD_INFO1_MASK_b;
12630     };
12631 
12632     union
12633     {
12634         __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register                           */
12635 
12636         struct
12637         {
12638             __IOM uint32_t CMDEM  : 1; /*!< [0..0] Command Error Interrupt Request Mask                               */
12639             __IOM uint32_t CRCEM  : 1; /*!< [1..1] CRC Error Interrupt Request Mask                                   */
12640             __IOM uint32_t ENDEM  : 1; /*!< [2..2] End Bit Error Interrupt Request Mask                               */
12641             __IOM uint32_t DTOM   : 1; /*!< [3..3] Data Timeout Interrupt Request Mask                                */
12642             __IOM uint32_t ILWM   : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask               */
12643             __IOM uint32_t ILRM   : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask                */
12644             __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask                            */
12645             uint32_t              : 1;
12646             __IOM uint32_t BREM   : 1; /*!< [8..8] BRE Interrupt Request Mask                                         */
12647             __IOM uint32_t BWEM   : 1; /*!< [9..9] BWE Interrupt Request Mask                                         */
12648             uint32_t              : 5;
12649             __IOM uint32_t ILAM   : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask                      */
12650             uint32_t              : 16;
12651         } SD_INFO2_MASK_b;
12652     };
12653 
12654     union
12655     {
12656         __IOM uint32_t SD_CLK_CTRL;       /*!< (@ 0x00000048) SD Clock Control Register                                  */
12657 
12658         struct
12659         {
12660             __IOM uint32_t CLKSEL    : 8; /*!< [7..0] SDHI Clock Frequency Select                                        */
12661             __IOM uint32_t CLKEN     : 1; /*!< [8..8] SD/MMC Clock Output Control Enable                                 */
12662             __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable                       */
12663             uint32_t                 : 22;
12664         } SD_CLK_CTRL_b;
12665     };
12666 
12667     union
12668     {
12669         __IOM uint32_t SD_SIZE;        /*!< (@ 0x0000004C) Transfer Data Length Register                              */
12670 
12671         struct
12672         {
12673             __IOM uint32_t LEN : 10;   /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
12674                                         *   and 512 bytes for the transfer of single blocks.In cases
12675                                         *   of multiple block transfer with automatic issuing of CMD12
12676                                         *   (CMD18 and CMD25), the only specifiable transfer data size
12677                                         *   is 512 bytes. Furthermore, in cases of multiple block transfer
12678                                         *   without automatic issuing of CMD12, as well as 512 bytes,
12679                                         *   32, 64, 128, and 256 bytes are specifiable. However, in
12680                                         *   the reading of 32, 64, 128, and 256 bytes for the transfer
12681                                         *   of multiple blocks, this is restricted to mult                            */
12682             uint32_t : 22;
12683         } SD_SIZE_b;
12684     };
12685 
12686     union
12687     {
12688         __IOM uint32_t SD_OPTION;        /*!< (@ 0x00000050) SD Card Access Control Option Register                     */
12689 
12690         struct
12691         {
12692             __IOM uint32_t CTOP     : 4; /*!< [3..0] Card Detect Time Counter                                           */
12693             __IOM uint32_t TOP      : 4; /*!< [7..4] Timeout Counter                                                    */
12694             __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
12695                                           *   timeout, software reset should be executed to terminate
12696                                           *   command sequence.                                                         */
12697             uint32_t              : 4;
12698             __IOM uint32_t WIDTH8 : 1;   /*!< [13..13] Bus Widthsee b15, WIDTH bit                                      */
12699             uint32_t              : 1;
12700             __IOM uint32_t WIDTH  : 1;   /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
12701                                           *   and when the SOFT_RST.SDRST flag is 0.                                    */
12702             uint32_t : 16;
12703         } SD_OPTION_b;
12704     };
12705     __IM uint32_t RESERVED1;
12706 
12707     union
12708     {
12709         __IM uint32_t SD_ERR_STS1;      /*!< (@ 0x00000058) SD Error Status Register 1                                 */
12710 
12711         struct
12712         {
12713             __IM uint32_t CMDE0 : 1;    /*!< [0..0] Command Error 0NOTE: other than a response to a command
12714                                          *   issued within a command sequence                                          */
12715             __IM uint32_t CMDE1 : 1;    /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
12716                                          *   setting a command index in SD_CMD, this is Indicated in
12717                                          *   CMDE0.                                                                    */
12718             __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
12719                                          *   a command issued within a command sequence                                */
12720             __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
12721                                          *   issued by setting a command index in SD_CMD, this is indicated
12722                                          *   in RSPLENE0.                                                              */
12723             __IM uint32_t RDLENE   : 1; /*!< [4..4] Read Data Length Error                                             */
12724             __IM uint32_t CRCLENE  : 1; /*!< [5..5] CRC Status Token Length Error                                      */
12725             uint32_t               : 2;
12726             __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
12727                                          *   command issued within a command sequence                                  */
12728             __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
12729                                          *   by setting a command index in SD_CMD, this is indicated
12730                                          *   in RSPCRCE0.                                                              */
12731             __IM uint32_t RDCRCE : 1;   /*!< [10..10] Read Data CRC Error                                              */
12732             __IM uint32_t CRCTKE : 1;   /*!< [11..11] CRC Status Token Error                                           */
12733             __IM uint32_t CRCTK  : 3;   /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
12734                                          *   value is 010b)                                                            */
12735             uint32_t : 17;
12736         } SD_ERR_STS1_b;
12737     };
12738 
12739     union
12740     {
12741         __IM uint32_t SD_ERR_STS2;      /*!< (@ 0x0000005C) SD Error Status Register 2                                 */
12742 
12743         struct
12744         {
12745             __IM uint32_t RSPTO0   : 1; /*!< [0..0] Response Timeout 0                                                 */
12746             __IM uint32_t RSPTO1   : 1; /*!< [1..1] Response Timeout 1                                                 */
12747             __IM uint32_t BSYTO0   : 1; /*!< [2..2] Busy Timeout 0                                                     */
12748             __IM uint32_t BSYTO1   : 1; /*!< [3..3] Busy Timeout 1                                                     */
12749             __IM uint32_t RDTO     : 1; /*!< [4..4] Read Data Timeout                                                  */
12750             __IM uint32_t CRCTO    : 1; /*!< [5..5] CRC Status Token Timeout                                           */
12751             __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout                                      */
12752             uint32_t               : 25;
12753         } SD_ERR_STS2_b;
12754     };
12755 
12756     union
12757     {
12758         __IOM uint32_t SD_BUF0;         /*!< (@ 0x00000060) SD Buffer Register                                         */
12759 
12760         struct
12761         {
12762             __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
12763                                          *   data is written to this register. When reading from the
12764                                          *   SD card, the read data is read from this register. This
12765                                          *   register is internally connected to two 512-byte buffers.If
12766                                          *   both buffers are not empty when executing multiple block
12767                                          *   read, SD/MMC clock is stopped to suspend receiving data.
12768                                          *   When one of buffers is empty, SD/MMC clock is supplied
12769                                          *   to resume receiving data.                                                 */
12770         } SD_BUF0_b;
12771     };
12772     __IM uint32_t RESERVED2;
12773 
12774     union
12775     {
12776         __IOM uint32_t SDIO_MODE;      /*!< (@ 0x00000068) SDIO Mode Control Register                                 */
12777 
12778         struct
12779         {
12780             __IOM uint32_t INTEN  : 1; /*!< [0..0] SDIO Mode                                                          */
12781             uint32_t              : 1;
12782             __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
12783             uint32_t              : 5;
12784             __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO AbortNOTE: See manual                                         */
12785             __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual                                    */
12786             uint32_t              : 22;
12787         } SDIO_MODE_b;
12788     };
12789 
12790     union
12791     {
12792         __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1                             */
12793 
12794         struct
12795         {
12796             __IOM uint32_t IOIRQ   : 1; /*!< [0..0] SDIO Interrupt Status                                              */
12797             uint32_t               : 13;
12798             __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual                              */
12799             __IOM uint32_t EXWT    : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual                                 */
12800             uint32_t               : 16;
12801         } SDIO_INFO1_b;
12802     };
12803 
12804     union
12805     {
12806         __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register                         */
12807 
12808         struct
12809         {
12810             __IOM uint32_t IOIRQM   : 1; /*!< [0..0] IOIRQ Interrupt Mask Control                                       */
12811             uint32_t                : 13;
12812             __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control                           */
12813             __IOM uint32_t EXWTM    : 1; /*!< [15..15] EXWT Interrupt Request Mask Control                              */
12814             uint32_t                : 16;
12815         } SDIO_INFO1_MASK_b;
12816     };
12817     __IM uint32_t RESERVED3[79];
12818 
12819     union
12820     {
12821         __IOM uint32_t SD_DMAEN;       /*!< (@ 0x000001B0) DMA Mode Enable Register                                   */
12822 
12823         struct
12824         {
12825             uint32_t             : 1;
12826             __IOM uint32_t DMAEN : 1;  /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
12827             uint32_t             : 30;
12828         } SD_DMAEN_b;
12829     };
12830     __IM uint32_t RESERVED4[3];
12831 
12832     union
12833     {
12834         __IOM uint32_t SOFT_RST;       /*!< (@ 0x000001C0) Software Reset Register                                    */
12835 
12836         struct
12837         {
12838             __IOM uint32_t SDRST : 1;  /*!< [0..0] Software Reset of SD I/F Unit                                      */
12839             uint32_t             : 31;
12840         } SOFT_RST_b;
12841     };
12842     __IM uint32_t RESERVED5[2];
12843 
12844     union
12845     {
12846         __IOM uint32_t SDIF_MODE;      /*!< (@ 0x000001CC) SD Interface Mode Setting Register                         */
12847 
12848         struct
12849         {
12850             uint32_t               : 8;
12851             __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands)                             */
12852             uint32_t               : 23;
12853         } SDIF_MODE_b;
12854     };
12855     __IM uint32_t RESERVED6[4];
12856 
12857     union
12858     {
12859         __IOM uint32_t EXT_SWAP;       /*!< (@ 0x000001E0) Swap Control Register                                      */
12860 
12861         struct
12862         {
12863             uint32_t             : 6;
12864             __IOM uint32_t BWSWP : 1;  /*!< [6..6] SD_BUF0 Swap Write                                                 */
12865             __IOM uint32_t BRSWP : 1;  /*!< [7..7] SD_BUF0 Swap Read                                                  */
12866             uint32_t             : 24;
12867         } EXT_SWAP_b;
12868     };
12869 } R_SDHI0_Type;                        /*!< Size = 484 (0x1e4)                                                        */
12870 
12871 /* =========================================================================================================================== */
12872 /* ================                                          R_SPI0                                           ================ */
12873 /* =========================================================================================================================== */
12874 
12875 /**
12876  * @brief Serial Peripheral Interface (R_SPI0)
12877  */
12878 
12879 typedef struct                         /*!< (@ 0x4035C000) R_SPI0 Structure                                           */
12880 {
12881     union
12882     {
12883         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
12884 
12885         struct
12886         {
12887             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
12888             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
12889             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
12890             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
12891             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
12892             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
12893             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
12894             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
12895         } SPCR_b;
12896     };
12897 
12898     union
12899     {
12900         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
12901 
12902         struct
12903         {
12904             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
12905             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
12906             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
12907             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
12908             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
12909             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
12910             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
12911             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
12912         } SSLP_b;
12913     };
12914 
12915     union
12916     {
12917         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
12918 
12919         struct
12920         {
12921             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
12922             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
12923             uint8_t             : 2;
12924             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
12925             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
12926             uint8_t             : 2;
12927         } SPPCR_b;
12928     };
12929 
12930     union
12931     {
12932         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
12933 
12934         struct
12935         {
12936             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
12937             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
12938             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
12939             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
12940             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
12941             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
12942             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
12943             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
12944         } SPSR_b;
12945     };
12946 
12947     union
12948     {
12949         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
12950         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
12951         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
12952     };
12953 
12954     union
12955     {
12956         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
12957 
12958         struct
12959         {
12960             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
12961                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
12962                                         *   changed in accordance with the sequence length that is
12963                                         *   set in these bits. The relationship among the setting of
12964                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
12965                                         *   referenced by the RSPI is shown above. However, the RSPI
12966                                         *   in slave mode always references SPCMD0.                                   */
12967             uint8_t : 5;
12968         } SPSCR_b;
12969     };
12970 
12971     union
12972     {
12973         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
12974 
12975         struct
12976         {
12977             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
12978             uint8_t            : 1;
12979             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
12980             uint8_t            : 1;
12981         } SPSSR_b;
12982     };
12983 
12984     union
12985     {
12986         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
12987 
12988         struct
12989         {
12990             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
12991         } SPBR_b;
12992     };
12993 
12994     union
12995     {
12996         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
12997 
12998         struct
12999         {
13000             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
13001             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
13002             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
13003             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
13004             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
13005             uint8_t              : 1;
13006         } SPDCR_b;
13007     };
13008 
13009     union
13010     {
13011         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
13012 
13013         struct
13014         {
13015             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
13016             uint8_t             : 5;
13017         } SPCKD_b;
13018     };
13019 
13020     union
13021     {
13022         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
13023 
13024         struct
13025         {
13026             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
13027             uint8_t             : 5;
13028         } SSLND_b;
13029     };
13030 
13031     union
13032     {
13033         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
13034 
13035         struct
13036         {
13037             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
13038             uint8_t             : 5;
13039         } SPND_b;
13040     };
13041 
13042     union
13043     {
13044         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
13045 
13046         struct
13047         {
13048             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
13049             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
13050             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
13051             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
13052             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
13053             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
13054         } SPCR2_b;
13055     };
13056 
13057     union
13058     {
13059         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
13060 
13061         struct
13062         {
13063             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
13064             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
13065             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
13066             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
13067             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
13068             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
13069             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
13070             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
13071             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
13072             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
13073         } SPCMD_b[8];
13074     };
13075 
13076     union
13077     {
13078         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
13079 
13080         struct
13081         {
13082             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
13083             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
13084             uint8_t            : 6;
13085         } SPDCR2_b;
13086     };
13087 
13088     union
13089     {
13090         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
13091 
13092         struct
13093         {
13094             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
13095             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
13096             uint8_t              : 2;
13097             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
13098             uint8_t              : 3;
13099         } SPCR3_b;
13100     };
13101     __IM uint16_t RESERVED;
13102     __IM uint32_t RESERVED1[6];
13103     __IM uint16_t RESERVED2;
13104 
13105     union
13106     {
13107         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
13108 
13109         struct
13110         {
13111             uint16_t              : 4;
13112             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
13113             uint16_t              : 3;
13114             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
13115             uint16_t              : 1;
13116             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
13117         } SPPR_b;
13118     };
13119 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
13120 
13121 /* =========================================================================================================================== */
13122 /* ================                                          R_SRAM                                           ================ */
13123 /* =========================================================================================================================== */
13124 
13125 /**
13126  * @brief SRAM (R_SRAM)
13127  */
13128 
13129 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
13130 {
13131     union
13132     {
13133         __IOM uint16_t SRAMPRCR;       /*!< (@ 0x00000000) SRAM Protection Control Register for Secure                */
13134 
13135         struct
13136         {
13137             __IOM uint16_t PR : 1;     /*!< [0..0] Register Write Control                                             */
13138             uint16_t          : 7;
13139             __OM uint16_t KW  : 8;     /*!< [15..8] Write Key Code                                                    */
13140         } SRAMPRCR_b;
13141     };
13142     __IM uint16_t RESERVED;
13143 
13144     union
13145     {
13146         __IOM uint16_t SRAMPRCR_NS;    /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure            */
13147 
13148         struct
13149         {
13150             __IOM uint16_t PR : 1;     /*!< [0..0] Register Write Control                                             */
13151             uint16_t          : 7;
13152             __OM uint16_t KW  : 8;     /*!< [15..8] Write Key Code                                                    */
13153         } SRAMPRCR_NS_b;
13154     };
13155     __IM uint16_t RESERVED1;
13156 
13157     union
13158     {
13159         __IOM uint8_t SRAMWTSC;        /*!< (@ 0x00000008) SRAM Wait State Control Register                           */
13160 
13161         struct
13162         {
13163             __IOM uint8_t WTEN : 1;    /*!< [0..0] Wait enable                                                        */
13164             uint8_t            : 7;
13165         } SRAMWTSC_b;
13166     };
13167     __IM uint8_t  RESERVED2;
13168     __IM uint16_t RESERVED3;
13169     __IM uint32_t RESERVED4;
13170 
13171     union
13172     {
13173         __IOM uint8_t SRAMCR0;         /*!< (@ 0x00000010) SRAM Control Register 0                                    */
13174 
13175         struct
13176         {
13177             __IOM uint8_t OAD     : 1; /*!< [0..0] Operation after detection for 1-bit ECC error detection            */
13178             uint8_t               : 1;
13179             __IOM uint8_t ECCMOD  : 2; /*!< [3..2] ECC Operating Mode Select                                          */
13180             __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable                          */
13181             uint8_t               : 2;
13182             __IOM uint8_t TSTBYP  : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select                                */
13183         } SRAMCR0_b;
13184     };
13185     __IM uint8_t  RESERVED5;
13186     __IM uint16_t RESERVED6;
13187 
13188     union
13189     {
13190         __IOM uint8_t SRAMCR1;         /*!< (@ 0x00000014) SRAM Control Register 1                                    */
13191 
13192         struct
13193         {
13194             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after detection for parity error detection               */
13195             uint8_t           : 7;
13196         } SRAMCR1_b;
13197     };
13198     __IM uint8_t  RESERVED7;
13199     __IM uint16_t RESERVED8;
13200     __IM uint32_t RESERVED9[6];
13201 
13202     union
13203     {
13204         __IOM uint8_t SRAMECCRGN0;     /*!< (@ 0x00000030) SRAM0 ECC Region Control Register                          */
13205 
13206         struct
13207         {
13208             __IOM uint8_t ECCRGN : 2;  /*!< [1..0] ECC Region                                                         */
13209             uint8_t              : 6;
13210         } SRAMECCRGN0_b;
13211     };
13212     __IM uint8_t  RESERVED10;
13213     __IM uint16_t RESERVED11;
13214     __IM uint32_t RESERVED12[3];
13215 
13216     union
13217     {
13218         __IM uint16_t SRAMESR;         /*!< (@ 0x00000040) SRAM Error Status Register                                 */
13219 
13220         struct
13221         {
13222             __IM uint16_t ERR00 : 1;   /*!< [0..0] SRAM0 1-bit ECC Error Status                                       */
13223             __IM uint16_t ERR01 : 1;   /*!< [1..1] SRAM0 2-bit ECC Error Status                                       */
13224             __IM uint16_t ERR1  : 1;   /*!< [2..2] SRAM1 Parity Error Status                                          */
13225             uint16_t            : 11;
13226             __IM uint16_t ERRS  : 1;   /*!< [14..14] Standby SRAM Parity Error status                                 */
13227             uint16_t            : 1;
13228         } SRAMESR_b;
13229     };
13230     __IM uint16_t RESERVED13;
13231     __IM uint32_t RESERVED14;
13232 
13233     union
13234     {
13235         __IOM uint16_t SRAMESCLR;      /*!< (@ 0x00000048) SRAM Error Status Clear Register                           */
13236 
13237         struct
13238         {
13239             __IOM uint16_t CLR00 : 1;  /*!< [0..0] SRAM0 1-bit ECC Error Status Clear                                 */
13240             __IOM uint16_t CLR01 : 1;  /*!< [1..1] SRAM0 2-bit ECC Error Status Clear                                 */
13241             __IOM uint16_t CLR1  : 1;  /*!< [2..2] SRAM1 Parity Error Status Clear                                    */
13242             uint16_t             : 11;
13243             __IOM uint16_t CLRS  : 1;  /*!< [14..14] Standby SRAM Parity Error Status Clear                           */
13244             uint16_t             : 1;
13245         } SRAMESCLR_b;
13246     };
13247     __IM uint16_t RESERVED15;
13248     __IM uint32_t RESERVED16;
13249 
13250     union
13251     {
13252         __IM uint32_t SRAMEAR0;        /*!< (@ 0x00000050) SRAM Error Address Register                                */
13253 
13254         struct
13255         {
13256             uint32_t         : 3;
13257             __IM uint32_t EA : 17;     /*!< [19..3] SRAM Error Address                                                */
13258             uint32_t         : 12;
13259         } SRAMEAR0_b;
13260     };
13261 
13262     union
13263     {
13264         __IM uint32_t SRAMEAR1;        /*!< (@ 0x00000054) SRAM Error Address Register                                */
13265 
13266         struct
13267         {
13268             uint32_t         : 3;
13269             __IM uint32_t EA : 17;     /*!< [19..3] SRAM Error Address                                                */
13270             uint32_t         : 12;
13271         } SRAMEAR1_b;
13272     };
13273 
13274     union
13275     {
13276         __IM uint32_t SRAMEAR2;        /*!< (@ 0x00000058) SRAM Error Address Register                                */
13277 
13278         struct
13279         {
13280             uint32_t         : 3;
13281             __IM uint32_t EA : 17;     /*!< [19..3] SRAM Error Address                                                */
13282             uint32_t         : 12;
13283         } SRAMEAR2_b;
13284     };
13285     __IM uint32_t RESERVED17[45];
13286 
13287     union
13288     {
13289         __IOM uint8_t STBRAMCR;        /*!< (@ 0x00000110) Standby SRAM Control Register                              */
13290 
13291         struct
13292         {
13293             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after detection                                          */
13294             uint8_t           : 7;
13295         } STBRAMCR_b;
13296     };
13297     __IM uint8_t  RESERVED18;
13298     __IM uint16_t RESERVED19;
13299     __IM uint32_t RESERVED20[15];
13300 
13301     union
13302     {
13303         __IM uint32_t STBRAMEAR;       /*!< (@ 0x00000150) Standby SRAM Error Address Register                        */
13304 
13305         struct
13306         {
13307             uint32_t         : 2;
13308             __IM uint32_t EA : 8;      /*!< [9..2] SRAM Error Address                                                 */
13309             uint32_t         : 22;
13310         } STBRAMEAR_b;
13311     };
13312 } R_SRAM_Type;                         /*!< Size = 340 (0x154)                                                        */
13313 
13314 /* =========================================================================================================================== */
13315 /* ================                                          R_SSI0                                           ================ */
13316 /* =========================================================================================================================== */
13317 
13318 /**
13319  * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
13320  */
13321 
13322 typedef struct                         /*!< (@ 0x4025D000) R_SSI0 Structure                                           */
13323 {
13324     union
13325     {
13326         __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
13327 
13328         struct
13329         {
13330             __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
13331             __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
13332             uint32_t            : 1;
13333             __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
13334                                         *   of outputting serial data is rewritten to 0 but data transmission
13335                                         *   is not stopped. Write dummy data to the SSIFTDR not to
13336                                         *   generate a transmit underflow because the number of data
13337                                         *   in the transmit FIFO is decreasing.                                       */
13338             __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
13339             __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
13340             __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
13341             __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
13342             __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
13343             __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
13344             __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
13345             __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
13346                                         *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
13347                                         *   are prohibited.                                                           */
13348             uint32_t           : 1;
13349             __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
13350                                         *   bit clock frequency/2 fs.                                                 */
13351             __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
13352             __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
13353             uint32_t             : 1;
13354             __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
13355             __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
13356             __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
13357             __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
13358             __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
13359             __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
13360             uint32_t             : 1;
13361         } SSICR_b;
13362     };
13363 
13364     union
13365     {
13366         __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
13367 
13368         struct
13369         {
13370             __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
13371             __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
13372             __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
13373             __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
13374             __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
13375             uint32_t             : 18;
13376             __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
13377             __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
13378                                         *   Writable only to clear the flag. Confirm the value is 1
13379                                         *   and then write 0.                                                         */
13380             __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
13381                                         *   Writable only to clear the flag. Confirm the value is 1
13382                                         *   and then write 0.                                                         */
13383             __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
13384                                         *   Writable only to clear the flag. Confirm the value is 1
13385                                         *   and then write 0.                                                         */
13386             __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
13387                                         *   Writable only to clear the flag. Confirm the value is 1
13388                                         *   and then write 0.                                                         */
13389             uint32_t : 2;
13390         } SSISR_b;
13391     };
13392     __IM uint32_t RESERVED[2];
13393 
13394     union
13395     {
13396         __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
13397 
13398         struct
13399         {
13400             __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
13401             __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
13402             __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
13403                                         *   clearing either the RDF flag (see the description of the
13404                                         *   RDF bit for details) or RIE bit.                                          */
13405             __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
13406                                         *   clearing either the TDE flag (see the description of the
13407                                         *   TDE bit for details) or TIE bit.                                          */
13408             __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
13409             __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
13410                                         *   are the number of empty stages in SSIFTDR at which the
13411                                         *   TDE flag is set.                                                          */
13412             uint32_t              : 3;
13413             __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
13414             uint32_t              : 4;
13415             __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
13416             uint32_t              : 14;
13417             __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
13418         } SSIFCR_b;
13419     };
13420 
13421     union
13422     {
13423         __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
13424 
13425         struct
13426         {
13427             __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
13428                                         *   is a 32-byte FIFO register, the maximum number of data
13429                                         *   bytes that can be read from it while the RDF flag is 1
13430                                         *   is indicated in the RDC[3:0] flags. If reading data from
13431                                         *   the SSIFRDR register is continued after all the data is
13432                                         *   read, undefined values will be read.                                      */
13433             uint32_t          : 7;
13434             __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
13435                                         *   units stored in SSIFRDR)                                                  */
13436             uint32_t           : 2;
13437             __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
13438                                         *   is a 32-byte FIFO register, the maximum number of bytes
13439                                         *   that can be written to it while the TDE flag is 1 is 8
13440                                         *   - TDC[3:0]. If writing data to the SSIFTDR register is
13441                                         *   continued after all the data is written, writing will be
13442                                         *   invalid and an overflow occurs.                                           */
13443             uint32_t          : 7;
13444             __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
13445                                         *   data units stored in SSIFTDR)                                             */
13446             uint32_t : 2;
13447         } SSIFSR_b;
13448     };
13449 
13450     union
13451     {
13452         union
13453         {
13454             __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
13455 
13456             struct
13457             {
13458                 __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
13459                                              *   eight stages of 32-bit registers for storing data to be
13460                                              *   serially transmitted. NOTE: that when the SSIFTDR register
13461                                              *   is full of data (32 bytes), the next data cannot be written
13462                                              *   to it. If writing is attempted, it will be ignored and
13463                                              *   an overflow occurs.                                                       */
13464             } SSIFTDR_b;
13465         };
13466         __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
13467         __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
13468     };
13469 
13470     union
13471     {
13472         union
13473         {
13474             __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
13475 
13476             struct
13477             {
13478                 __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
13479                                              *   stages of 32-bit registers for storing serially received
13480                                              *   data.                                                                     */
13481             } SSIFRDR_b;
13482         };
13483         __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
13484         __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
13485     };
13486 
13487     union
13488     {
13489         __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
13490 
13491         struct
13492         {
13493             __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
13494             uint32_t               : 6;
13495             __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
13496             __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
13497                                          *   Idle Status                                                               */
13498             uint32_t : 22;
13499         } SSIOFR_b;
13500     };
13501 
13502     union
13503     {
13504         __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
13505 
13506         struct
13507         {
13508             __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
13509             uint32_t            : 3;
13510             __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
13511             uint32_t            : 19;
13512         } SSISCR_b;
13513     };
13514 } R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
13515 
13516 /* =========================================================================================================================== */
13517 /* ================                                         R_SYSTEM                                          ================ */
13518 /* =========================================================================================================================== */
13519 
13520 /**
13521  * @brief System Pins (R_SYSTEM)
13522  */
13523 
13524 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
13525 {
13526     __IM uint32_t RESERVED[3];
13527 
13528     union
13529     {
13530         __IOM uint8_t SBYCR;           /*!< (@ 0x0000000C) Standby Control Register                                   */
13531 
13532         struct
13533         {
13534             uint8_t           : 6;
13535             __IOM uint8_t OPE : 1;     /*!< [6..6] Output Port Enable                                                 */
13536             uint8_t           : 1;
13537         } SBYCR_b;
13538     };
13539     __IM uint8_t RESERVED1;
13540 
13541     union
13542     {
13543         __IOM uint8_t SSCR2;           /*!< (@ 0x0000000E) Software Standby Control Register 2                        */
13544 
13545         struct
13546         {
13547             __IM uint8_t SS1RSF : 1;   /*!< [0..0] Software Standby 1 regulator status flag                           */
13548             uint8_t             : 7;
13549         } SSCR2_b;
13550     };
13551     __IM uint8_t RESERVED2;
13552 
13553     union
13554     {
13555         __IOM uint8_t FLSCR;           /*!< (@ 0x00000010) Flash Standby Control Register                             */
13556 
13557         struct
13558         {
13559             __IOM uint8_t FLSWCF : 1;  /*!< [0..0] Flash Stabilization wait completion flag                           */
13560             uint8_t              : 7;
13561         } FLSCR_b;
13562     };
13563     __IM uint8_t  RESERVED3;
13564     __IM uint16_t RESERVED4;
13565     __IM uint32_t RESERVED5[2];
13566 
13567     union
13568     {
13569         __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
13570 
13571         struct
13572         {
13573             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
13574             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
13575             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
13576             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
13577             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
13578             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
13579             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
13580             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
13581             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
13582             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
13583             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
13584                                          *   usage.                                                                    */
13585             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
13586                                          *   usage.                                                                    */
13587             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
13588                                          *   usage.                                                                    */
13589             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
13590                                          *   usage.                                                                    */
13591             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
13592                                          *   usage.                                                                    */
13593             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
13594                                          *   usage.                                                                    */
13595             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
13596                                          *   usage.                                                                    */
13597             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
13598                                          *   usage.                                                                    */
13599             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
13600                                          *   usage.                                                                    */
13601             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
13602                                          *   usage.                                                                    */
13603             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
13604                                          *   usage.                                                                    */
13605             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
13606                                          *   usage.                                                                    */
13607             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
13608                                          *   usage.                                                                    */
13609             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
13610                                          *   usage.                                                                    */
13611             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
13612                                          *   usage.                                                                    */
13613             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
13614                                          *   usage.                                                                    */
13615             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
13616                                          *   usage.                                                                    */
13617             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
13618                                          *   usage.                                                                    */
13619             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
13620                                          *   usage.                                                                    */
13621             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
13622                                          *   usage.                                                                    */
13623             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
13624                                          *   usage.                                                                    */
13625             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
13626                                          *   usage.                                                                    */
13627         } MSTPCRA_b;
13628     };
13629 
13630     union
13631     {
13632         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
13633 
13634         struct
13635         {
13636             __IOM uint32_t PCKD : 4;   /*!< [3..0] Peripheral Module Clock D (PCLKD) Select                           */
13637             __IOM uint32_t PCKC : 4;   /*!< [7..4] Peripheral Module Clock C (PCLKC) Select                           */
13638             __IOM uint32_t PCKB : 4;   /*!< [11..8] Peripheral Module Clock B (PCLKB) Select                          */
13639             __IOM uint32_t PCKA : 4;   /*!< [15..12] Peripheral Module Clock A (PCLKA) Select                         */
13640             __IOM uint32_t BCK  : 4;   /*!< [19..16] External Bus Clock (BCLK) Select                                 */
13641             __IOM uint32_t PCKE : 4;   /*!< [23..20] Peripheral Module Clock E (PCLKE) Select                         */
13642             __IOM uint32_t ICK  : 4;   /*!< [27..24] System Clock (ICLK) Select                                       */
13643             __IOM uint32_t FCK  : 4;   /*!< [31..28] Flash IF Clock (FCLK) Select                                     */
13644         } SCKDIVCR_b;
13645     };
13646 
13647     union
13648     {
13649         __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
13650 
13651         struct
13652         {
13653             __IOM uint8_t CPUCK  : 4;  /*!< [3..0] CPU Clock (CPUCLK) Select                                          */
13654             __IOM uint8_t CPUCK1 : 4;  /*!< [7..4] CPU1 Clock (CPUCLK1) Select                                        */
13655         } SCKDIVCR2_b;
13656     };
13657     __IM uint8_t RESERVED6;
13658 
13659     union
13660     {
13661         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
13662 
13663         struct
13664         {
13665             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
13666             uint8_t             : 5;
13667         } SCKSCR_b;
13668     };
13669     __IM uint8_t RESERVED7;
13670 
13671     union
13672     {
13673         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
13674 
13675         struct
13676         {
13677             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select                         */
13678             uint16_t                : 2;
13679             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select                                           */
13680             uint16_t                : 1;
13681             __IOM uint16_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select             */
13682             __IOM uint16_t PLLMUL   : 8; /*!< [15..8] PLL1 Frequency Multiplication Factor Select                       */
13683         } PLLCCR_b;
13684     };
13685 
13686     union
13687     {
13688         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
13689 
13690         struct
13691         {
13692             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
13693             uint8_t              : 7;
13694         } PLLCR_b;
13695     };
13696     __IM uint8_t  RESERVED8;
13697     __IM uint32_t RESERVED9;
13698 
13699     union
13700     {
13701         __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
13702 
13703         struct
13704         {
13705             __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
13706             uint8_t               : 7;
13707         } BCKCR_b;
13708     };
13709     __IM uint8_t RESERVED10;
13710 
13711     union
13712     {
13713         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
13714 
13715         struct
13716         {
13717             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
13718             uint8_t             : 7;
13719         } MOSCCR_b;
13720     };
13721     __IM uint8_t  RESERVED11;
13722     __IM uint16_t RESERVED12;
13723 
13724     union
13725     {
13726         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
13727 
13728         struct
13729         {
13730             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
13731             uint8_t             : 7;
13732         } HOCOCR_b;
13733     };
13734     __IM uint8_t RESERVED13;
13735 
13736     union
13737     {
13738         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
13739 
13740         struct
13741         {
13742             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
13743             uint8_t             : 7;
13744         } MOCOCR_b;
13745     };
13746 
13747     union
13748     {
13749         __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
13750 
13751         struct
13752         {
13753             __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
13754             uint8_t             : 7;
13755         } FLLCR1_b;
13756     };
13757 
13758     union
13759     {
13760         __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
13761 
13762         struct
13763         {
13764             __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control                                        */
13765             uint16_t               : 5;
13766         } FLLCR2_b;
13767     };
13768 
13769     union
13770     {
13771         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
13772 
13773         struct
13774         {
13775             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
13776                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
13777                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
13778             uint8_t             : 2;
13779             __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
13780             uint8_t             : 1;
13781             __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag                          */
13782             __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
13783             uint8_t             : 1;
13784         } OSCSF_b;
13785     };
13786     __IM uint8_t RESERVED14;
13787 
13788     union
13789     {
13790         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
13791 
13792         struct
13793         {
13794             uint8_t              : 4;
13795             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
13796             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
13797         } CKOCR_b;
13798     };
13799 
13800     union
13801     {
13802         __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
13803 
13804         struct
13805         {
13806             __IOM uint8_t TRCK    : 4; /*!< [3..0] Trace Clock operating frequency select                             */
13807             __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock source select                                          */
13808             uint8_t               : 2;
13809             __IOM uint8_t TRCKEN  : 1; /*!< [7..7] Trace Clock operating Enable                                       */
13810         } TRCKCR_b;
13811     };
13812 
13813     union
13814     {
13815         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
13816 
13817         struct
13818         {
13819             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
13820             uint8_t              : 6;
13821             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
13822         } OSTDCR_b;
13823     };
13824 
13825     union
13826     {
13827         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
13828 
13829         struct
13830         {
13831             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
13832             uint8_t             : 7;
13833         } OSTDSR_b;
13834     };
13835     __IM uint8_t RESERVED15;
13836 
13837     union
13838     {
13839         __IM uint8_t OSCMONR;          /*!< (@ 0x00000043) Oscillator Monitor Register                                */
13840 
13841         struct
13842         {
13843             uint8_t              : 1;
13844             __IM uint8_t MOCOMON : 1;  /*!< [1..1] MOCO operation monitor                                             */
13845             __IM uint8_t LOCOMON : 1;  /*!< [2..2] LOCO operation monitor                                             */
13846             uint8_t              : 5;
13847         } OSCMONR_b;
13848     };
13849     __IM uint32_t RESERVED16;
13850 
13851     union
13852     {
13853         __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
13854 
13855         struct
13856         {
13857             __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
13858             uint16_t                 : 2;
13859             __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
13860             uint16_t                 : 1;
13861             __IOM uint16_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select             */
13862             __IOM uint16_t PLL2MUL   : 8; /*!< [15..8] PLL2 Frequency Multiplication Factor Select                       */
13863         } PLL2CCR_b;
13864     };
13865 
13866     union
13867     {
13868         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
13869 
13870         struct
13871         {
13872             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
13873             uint8_t               : 7;
13874         } PLL2CR_b;
13875     };
13876     __IM uint8_t RESERVED17;
13877 
13878     union
13879     {
13880         __IOM uint16_t PLLCCR2;         /*!< (@ 0x0000004C) PLL Clock Control Register 2                               */
13881 
13882         struct
13883         {
13884             __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output
13885                                          *   clock P                                                                   */
13886             __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output
13887                                          *   clock Q                                                                   */
13888             __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output
13889                                          *   clock R                                                                   */
13890             uint16_t : 4;
13891         } PLLCCR2_b;
13892     };
13893 
13894     union
13895     {
13896         __IOM uint16_t PLL2CCR2;         /*!< (@ 0x0000004E) PLL2 Clock Control Register 2                              */
13897 
13898         struct
13899         {
13900             __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output
13901                                           *   clock P                                                                   */
13902             __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output
13903                                           *   clock Q                                                                   */
13904             __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output
13905                                           *   clock R                                                                   */
13906             uint16_t : 4;
13907         } PLL2CCR2_b;
13908     };
13909     __IM uint16_t RESERVED18;
13910 
13911     union
13912     {
13913         __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
13914 
13915         struct
13916         {
13917             __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
13918             uint8_t               : 7;
13919         } EBCKOCR_b;
13920     };
13921 
13922     union
13923     {
13924         __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
13925 
13926         struct
13927         {
13928             __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
13929             uint8_t               : 7;
13930         } SDCKOCR_b;
13931     };
13932 
13933     union
13934     {
13935         __IOM uint8_t SCICKDIVCR;      /*!< (@ 0x00000054) SCI clock Division control register                        */
13936 
13937         struct
13938         {
13939             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
13940             uint8_t             : 5;
13941         } SCICKDIVCR_b;
13942     };
13943 
13944     union
13945     {
13946         __IOM uint8_t SCICKCR;          /*!< (@ 0x00000055) SCI clock control register                                 */
13947 
13948         struct
13949         {
13950             __IOM uint8_t SCICKSEL : 4; /*!< [3..0] Clock Source Select                                                */
13951             uint8_t                : 2;
13952             __IOM uint8_t CKSREQ   : 1; /*!< [6..6] Clock Switching Request                                            */
13953             __IM uint8_t  CKSRDY   : 1; /*!< [7..7] Clock Switching Ready state flag                                   */
13954         } SCICKCR_b;
13955     };
13956 
13957     union
13958     {
13959         __IOM uint8_t SPICKDIVCR;      /*!< (@ 0x00000056) SPI clock Division control register                        */
13960 
13961         struct
13962         {
13963             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
13964             uint8_t             : 5;
13965         } SPICKDIVCR_b;
13966     };
13967 
13968     union
13969     {
13970         __IOM uint8_t SPICKCR;         /*!< (@ 0x00000057) SPI clock control register                                 */
13971 
13972         struct
13973         {
13974             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
13975             uint8_t              : 2;
13976             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
13977             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
13978         } SPICKCR_b;
13979     };
13980     __IM uint16_t RESERVED19;
13981 
13982     union
13983     {
13984         __IOM uint8_t ADCCKDIVCR;      /*!< (@ 0x0000005A) ADC clock Division control register                        */
13985 
13986         struct
13987         {
13988             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
13989             uint8_t             : 5;
13990         } ADCCKDIVCR_b;
13991     };
13992 
13993     union
13994     {
13995         __IOM uint8_t ADCCKCR;         /*!< (@ 0x0000005B) ADC clock control register                                 */
13996 
13997         struct
13998         {
13999             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
14000             uint8_t              : 2;
14001             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
14002             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
14003         } ADCCKCR_b;
14004     };
14005 
14006     union
14007     {
14008         __IOM uint8_t GPTCKDIVCR;      /*!< (@ 0x0000005C) GPT clock Division control register                        */
14009 
14010         struct
14011         {
14012             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
14013             uint8_t             : 5;
14014         } GPTCKDIVCR_b;
14015     };
14016 
14017     union
14018     {
14019         __IOM uint8_t GPTCKCR;         /*!< (@ 0x0000005D) GPT clock control register                                 */
14020 
14021         struct
14022         {
14023             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
14024             uint8_t              : 2;
14025             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
14026             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
14027         } GPTCKCR_b;
14028     };
14029 
14030     union
14031     {
14032         __IOM uint8_t LCDCKDIVCR;      /*!< (@ 0x0000005E) LCD clock Division control register                        */
14033 
14034         struct
14035         {
14036             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
14037             uint8_t             : 5;
14038         } LCDCKDIVCR_b;
14039     };
14040 
14041     union
14042     {
14043         __IOM uint8_t LCDCKCR;         /*!< (@ 0x0000005F) LCD clock control register                                 */
14044 
14045         struct
14046         {
14047             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
14048             uint8_t              : 2;
14049             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
14050             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
14051         } LCDCKCR_b;
14052     };
14053     __IM uint8_t RESERVED20;
14054 
14055     union
14056     {
14057         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
14058 
14059         struct
14060         {
14061             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
14062                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
14063                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
14064                                          +126 0111_1111 : +127These bits are added to original MOCO
14065                                          *   trimming bits                                                             */
14066         } MOCOUTCR_b;
14067     };
14068 
14069     union
14070     {
14071         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
14072 
14073         struct
14074         {
14075             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
14076                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
14077                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
14078                                          +126 0111_1111 : +127These bits are added to original HOCO
14079                                          *   trimming bits                                                             */
14080         } HOCOUTCR_b;
14081     };
14082     __IM uint8_t  RESERVED21;
14083     __IM uint32_t RESERVED22[2];
14084 
14085     union
14086     {
14087         __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB clock Division control register                        */
14088 
14089         struct
14090         {
14091             __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB clock (USBCLK) Division Select                                 */
14092             uint8_t                : 5;
14093         } USBCKDIVCR_b;
14094     };
14095 
14096     union
14097     {
14098         __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI clock Division control register                  */
14099 
14100         struct
14101         {
14102             __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI clock (OCTACLK) Division Select                          */
14103             uint8_t                 : 5;
14104         } OCTACKDIVCR_b;
14105     };
14106 
14107     union
14108     {
14109         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Core clock Division control register                 */
14110 
14111         struct
14112         {
14113             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Core clock (CANFDCLK) Division Select                        */
14114             uint8_t                  : 5;
14115         } CANFDCKDIVCR_b;
14116     };
14117 
14118     union
14119     {
14120         __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 clock Division control register                      */
14121 
14122         struct
14123         {
14124             __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
14125             uint8_t                  : 5;
14126         } USB60CKDIVCR_b;
14127     };
14128 
14129     union
14130     {
14131         __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000070) I3C clock Division control register                        */
14132 
14133         struct
14134         {
14135             __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
14136             uint8_t                : 5;
14137         } I3CCKDIVCR_b;
14138     };
14139     __IM uint8_t  RESERVED23;
14140     __IM uint16_t RESERVED24;
14141 
14142     union
14143     {
14144         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB clock control register                                 */
14145 
14146         struct
14147         {
14148             __IOM uint8_t USBCKSEL  : 4; /*!< [3..0] USB clock (USBCLK) Source Select                                   */
14149             uint8_t                 : 2;
14150             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB clock (USBCLK) Switching Request                               */
14151             __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB clock (USBCLK) Switching Ready state flag                      */
14152         } USBCKCR_b;
14153     };
14154 
14155     union
14156     {
14157         __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI clock control register                           */
14158 
14159         struct
14160         {
14161             __IOM uint8_t OCTACKSEL  : 4; /*!< [3..0] Octal-SPI clock (OCTACLK) Source Select                            */
14162             uint8_t                  : 2;
14163             __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI clock (OCTACLK) Switching Request                        */
14164             __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI clock (OCTACLK) Switching Ready state flag               */
14165         } OCTACKCR_b;
14166     };
14167 
14168     union
14169     {
14170         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Core clock control register                          */
14171 
14172         struct
14173         {
14174             __IOM uint8_t CANFDCKSEL  : 4; /*!< [3..0] CANFD Core clock (CANFDCLK) Source Select                          */
14175             uint8_t                   : 2;
14176             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Core clock (CANFDCLK) Switching Request                      */
14177             __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Core clock (CANFDCLK) Switching Ready state flag             */
14178         } CANFDCKCR_b;
14179     };
14180 
14181     union
14182     {
14183         __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
14184 
14185         struct
14186         {
14187             __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
14188             uint8_t                   : 2;
14189             __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
14190             __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
14191         } USB60CKCR_b;
14192     };
14193 
14194     union
14195     {
14196         __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000078) I3C clock control register                                 */
14197 
14198         struct
14199         {
14200             __IOM uint8_t I3CCKSEL  : 4; /*!< [3..0] I3C clock (I3CCLK) Source Select                                   */
14201             uint8_t                 : 2;
14202             __IOM uint8_t I3CCKREQ  : 1; /*!< [6..6] I3C clock (I3CCLK) Switching Request                               */
14203             __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) Switching Ready state flag                      */
14204         } I3CCKCR_b;
14205     };
14206     __IM uint8_t  RESERVED25;
14207     __IM uint16_t RESERVED26;
14208 
14209     union
14210     {
14211         __IOM uint8_t MOSCSCR;          /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register             */
14212 
14213         struct
14214         {
14215             __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select              */
14216             uint8_t                : 7;
14217         } MOSCSCR_b;
14218     };
14219 
14220     union
14221     {
14222         __IOM uint8_t HOCOSCR;          /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control
14223                                          *                  Register                                                   */
14224 
14225         struct
14226         {
14227             __IOM uint8_t HOCOSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select                               */
14228             uint8_t                : 7;
14229         } HOCOSCR_b;
14230     };
14231     __IM uint16_t RESERVED27;
14232     __IM uint32_t RESERVED28[8];
14233 
14234     union
14235     {
14236         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
14237 
14238         struct
14239         {
14240             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
14241             uint8_t              : 2;
14242             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
14243             uint8_t              : 3;
14244         } OPCCR_b;
14245     };
14246     __IM uint8_t RESERVED29;
14247 
14248     union
14249     {
14250         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
14251 
14252         struct
14253         {
14254             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
14255             uint8_t            : 4;
14256         } MOSCWTCR_b;
14257     };
14258     __IM uint8_t RESERVED30[2];
14259 
14260     union
14261     {
14262         __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
14263 
14264         struct
14265         {
14266             __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
14267                                         *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
14268             uint8_t : 5;
14269         } HOCOWTCR_b;
14270     };
14271     __IM uint16_t RESERVED31[2];
14272 
14273     union
14274     {
14275         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
14276 
14277         struct
14278         {
14279             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
14280             uint8_t               : 3;
14281             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
14282             uint8_t               : 3;
14283         } SOPCCR_b;
14284     };
14285     __IM uint8_t  RESERVED32;
14286     __IM uint32_t RESERVED33[5];
14287 
14288     union
14289     {
14290         __IOM uint32_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
14291 
14292         struct
14293         {
14294             __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag. NOTE: Writable
14295                                         *   only to clear the flag. Confirm the value is 1 and then
14296                                         *   write 0.                                                                  */
14297             __IOM uint32_t WDTRF : 1;  /*!< [1..1] Watchdog Timer0 Reset Detect Flag. NOTE: Writable only
14298                                         *   to clear the flag. Confirm the value is 1 and then write
14299                                         *   0.                                                                        */
14300             __IOM uint32_t SWRF : 1;   /*!< [2..2] Software Reset Detect Flag. NOTE: Writable only to clear
14301                                         *   the flag. Confirm the value is 1 and then write 0.                        */
14302             uint32_t              : 1;
14303             __IOM uint32_t CLU0RF : 1; /*!< [4..4] CPU0 Lockup Reset Detect Flag. NOTE: Writable only to
14304                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
14305             __IOM uint32_t LM0RF : 1;  /*!< [5..5] Local memory 0 error Reset Detect Flag. NOTE: Writable
14306                                         *   only to clear the flag. Confirm the value is 1 and then
14307                                         *   write 0.                                                                  */
14308             uint32_t             : 4;
14309             __IOM uint32_t BUSRF : 1;  /*!< [10..10] Bus error Reset Detect Flag. NOTE: Writable only to
14310                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
14311             uint32_t            : 3;
14312             __IOM uint32_t CMRF : 1;   /*!< [14..14] Common memory error Reset Detect Flag. NOTE: Writable
14313                                         *   only to clear the flag. Confirm the value is 1 and then
14314                                         *   write 0.                                                                  */
14315             uint32_t              : 2;
14316             __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only
14317                                         *   to clear the flag. Confirm the value is 1 and then write
14318                                         *   0.                                                                        */
14319             uint32_t              : 2;
14320             __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only
14321                                         *   to clear the flag. Confirm the value is 1 and then write
14322                                         *   0.                                                                        */
14323             __IOM uint32_t LM1RF : 1;  /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable
14324                                         *   only to clear the flag. Confirm the value is 1 and then
14325                                         *   write 0.                                                                  */
14326             __IOM uint32_t NWRF : 1;   /*!< [22..22] Network Reset Detect Flag. NOTE: Writable only to clear
14327                                         *   the flag. Confirm the value is 1 and then write 0.                        */
14328             uint32_t : 9;
14329         } RSTSR1_b;
14330     };
14331     __IM uint32_t RESERVED34[2];
14332 
14333     union
14334     {
14335         __IOM uint8_t SYRACCR;         /*!< (@ 0x000000CC) System Register Access Control Register                    */
14336 
14337         struct
14338         {
14339             __IOM uint8_t BUSY : 1;    /*!< [0..0] Access Ready monitor                                               */
14340             uint8_t            : 7;
14341         } SYRACCR_b;
14342     };
14343     __IM uint8_t  RESERVED35;
14344     __IM uint16_t RESERVED36;
14345     __IM uint32_t RESERVED37[4];
14346 
14347     union
14348     {
14349         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
14350 
14351         struct
14352         {
14353             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
14354             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
14355             uint8_t              : 5;
14356         } LVD1CR1_b;
14357     };
14358 
14359     union
14360     {
14361         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
14362 
14363         struct
14364         {
14365             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
14366                                         *   0 can be written to this bit. After writing 0 to this bit,
14367                                         *   it takes 2 system clock cycles for the bit to be read as
14368                                         *   0.                                                                        */
14369             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor Signal Monitor Flag                                */
14370             uint8_t          : 6;
14371         } LVD1SR_b;
14372     };
14373 
14374     union
14375     {
14376         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
14377 
14378         struct
14379         {
14380             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
14381             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
14382             uint8_t              : 5;
14383         } LVD2CR1_b;
14384     };
14385 
14386     union
14387     {
14388         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
14389 
14390         struct
14391         {
14392             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
14393                                         *   0 can be written to this bit. After writing 0 to this bit,
14394                                         *   it takes 2 system clock cycles for the bit to be read as
14395                                         *   0.                                                                        */
14396             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor Signal Monitor Flag                                */
14397             uint8_t          : 6;
14398         } LVD2SR_b;
14399     };
14400     __IM uint32_t RESERVED38[3];
14401 
14402     union
14403     {
14404         __IOM uint8_t CRVSYSCR;        /*!< (@ 0x000000F0) Clock Recovery System Control Register                     */
14405 
14406         struct
14407         {
14408             __IOM uint8_t CRVEN : 1;   /*!< [0..0] Clock Recovery Enable                                              */
14409             uint8_t             : 7;
14410         } CRVSYSCR_b;
14411     };
14412     __IM uint8_t  RESERVED39;
14413     __IM uint16_t RESERVED40;
14414     __IM uint32_t RESERVED41[7];
14415 
14416     union
14417     {
14418         __IOM uint8_t PDCTRGD;         /*!< (@ 0x00000110) Graphics Power Domain Control Register                     */
14419 
14420         struct
14421         {
14422             __IOM uint8_t PDDE  : 1;   /*!< [0..0] Power control enable                                               */
14423             uint8_t             : 5;
14424             __IM uint8_t PDCSF  : 1;   /*!< [6..6] Power control status flag                                          */
14425             __IM uint8_t PDPGSF : 1;   /*!< [7..7] Power gating status flag                                           */
14426         } PDCTRGD_b;
14427     };
14428     __IM uint8_t   RESERVED42;
14429     __IM uint16_t  RESERVED43;
14430     __IM uint32_t  RESERVED44[11];
14431     __IOM uint16_t PDRAMSCR0;          /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0               */
14432     __IOM uint8_t  PDRAMSCR1;          /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1               */
14433     __IM uint8_t   RESERVED45;
14434     __IM uint32_t  RESERVED46[155];
14435 
14436     union
14437     {
14438         __IOM uint16_t VBRSABAR;       /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary
14439                                         *                  Address Register                                           */
14440 
14441         struct
14442         {
14443             __IOM uint16_t SABA : 16;  /*!< [15..0] Security Attribute Boundary Address                               */
14444         } VBRSABAR_b;
14445     };
14446     __IM uint16_t RESERVED47;
14447 
14448     union
14449     {
14450         __IOM uint16_t VBRPABARS;      /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary
14451                                         *                  Address Register for Secure Region                         */
14452 
14453         struct
14454         {
14455             __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region            */
14456         } VBRPABARS_b;
14457     };
14458     __IM uint16_t RESERVED48;
14459 
14460     union
14461     {
14462         __IOM uint16_t VBRPABARNS;      /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary
14463                                          *                  Address Register for Non-secure Region                     */
14464 
14465         struct
14466         {
14467             __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure
14468                                          *   Region                                                                    */
14469         } VBRPABARNS_b;
14470     };
14471     __IM uint16_t RESERVED49;
14472     __IM uint32_t RESERVED50;
14473 
14474     union
14475     {
14476         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
14477                                           *                  Register                                                   */
14478 
14479         struct
14480         {
14481             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
14482             uint32_t                : 1;
14483             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non-secure Attribute bit 2                                         */
14484             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non-secure Attribute bit 3                                         */
14485             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non-secure Attribute bit 4                                         */
14486             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non-secure Attribute bit 5                                         */
14487             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non-secure Attribute bit 6                                         */
14488             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non-secure Attribute bit 7                                         */
14489             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non-secure Attribute bit 8                                         */
14490             __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non-secure Attribute bit 9                                         */
14491             uint32_t                : 1;
14492             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11                                      */
14493             __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12                                      */
14494             __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13                                      */
14495             uint32_t                : 2;
14496             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16                                      */
14497             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17                                      */
14498             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18                                      */
14499             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19                                      */
14500             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20                                      */
14501             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21                                      */
14502             __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22                                      */
14503             uint32_t                : 1;
14504             __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24                                      */
14505             __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25                                      */
14506             __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26                                      */
14507             uint32_t                : 5;
14508         } CGFSAR_b;
14509     };
14510 
14511     union
14512     {
14513         __IOM uint32_t RSTSAR;          /*!< (@ 0x000003C4) Reset Security Attribution Register                        */
14514 
14515         struct
14516         {
14517             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
14518             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1                                         */
14519             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2                                         */
14520             __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3                                         */
14521             uint32_t               : 28;
14522         } RSTSAR_b;
14523     };
14524 
14525     union
14526     {
14527         __IOM uint32_t LPMSAR;           /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
14528 
14529         struct
14530         {
14531             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non-secure Attribute bit 00                                        */
14532             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non-secure Attribute bit 01                                        */
14533             __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non-secure Attribute bit 02                                        */
14534             __IOM uint32_t NONSEC3  : 1; /*!< [3..3] Non-secure Attribute bit 03                                        */
14535             uint32_t                : 4;
14536             __IOM uint32_t NONSEC8  : 1; /*!< [8..8] Non-secure Attribute bit 08                                        */
14537             uint32_t                : 7;
14538             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16                                      */
14539             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17                                      */
14540             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18                                      */
14541             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19                                      */
14542             uint32_t                : 1;
14543             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21                                      */
14544             uint32_t                : 10;
14545         } LPMSAR_b;
14546     };
14547 
14548     union
14549     {
14550         __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Programable Voltage Detection Security Attribution
14551                                          *                  Register                                                   */
14552 
14553         struct
14554         {
14555             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
14556             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1                                         */
14557             uint32_t               : 30;
14558         } LVDSAR_b;
14559     };
14560 
14561     union
14562     {
14563         __IOM uint32_t BBFSAR;          /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
14564 
14565         struct
14566         {
14567             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
14568             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1                                         */
14569             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2                                         */
14570             __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3                                         */
14571             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4                                         */
14572             uint32_t               : 27;
14573         } BBFSAR_b;
14574     };
14575     __IM uint32_t RESERVED51;
14576 
14577     union
14578     {
14579         __IOM uint32_t PGCSAR;         /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register         */
14580 
14581         struct
14582         {
14583             uint32_t               : 1;
14584             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01                                        */
14585             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02                                        */
14586             uint32_t               : 29;
14587         } PGCSAR_b;
14588     };
14589     __IM uint32_t RESERVED52;
14590 
14591     union
14592     {
14593         __IOM uint32_t DPFSAR;         /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
14594                                         *                  Register                                                   */
14595 
14596         struct
14597         {
14598             uint32_t               : 16;
14599             __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
14600                                          *   16                                                                        */
14601             __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
14602                                          *   17                                                                        */
14603             __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
14604                                          *   18                                                                        */
14605             __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
14606                                          *   19                                                                        */
14607             __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
14608                                          *   20                                                                        */
14609             uint32_t               : 3;
14610             __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
14611                                          *   24                                                                        */
14612             __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit
14613                                          *   25                                                                        */
14614             __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
14615                                          *   26                                                                        */
14616             __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
14617                                          *   27                                                                        */
14618             uint32_t               : 1;
14619             __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit
14620                                          *   29                                                                        */
14621             uint32_t               : 1;
14622             __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit
14623                                          *   31                                                                        */
14624         } DPFSAR_b;
14625     };
14626 
14627     union
14628     {
14629         __IOM uint32_t RSCSAR;          /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register          */
14630 
14631         struct
14632         {
14633             __IOM uint32_t RSCSA0  : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 00                      */
14634             __IOM uint32_t RSCSA1  : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 01                      */
14635             __IOM uint32_t RSCSA2  : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 02                      */
14636             __IOM uint32_t RSCSA3  : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 03                      */
14637             __IOM uint32_t RSCSA4  : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 04                      */
14638             __IOM uint32_t RSCSA5  : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 05                      */
14639             __IOM uint32_t RSCSA6  : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 06                      */
14640             __IOM uint32_t RSCSA7  : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 07                      */
14641             __IOM uint32_t RSCSA8  : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 08                      */
14642             __IOM uint32_t RSCSA9  : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 09                      */
14643             __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10                    */
14644             __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11                    */
14645             __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12                    */
14646             __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13                    */
14647             __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14                    */
14648             uint32_t               : 1;
14649             __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16                    */
14650             __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17                    */
14651             uint32_t               : 14;
14652         } RSCSAR_b;
14653     };
14654     __IM uint32_t RESERVED53[4];
14655     __IM uint16_t RESERVED54;
14656 
14657     union
14658     {
14659         __IOM uint16_t PRCR;           /*!< (@ 0x000003FA) Protect Register for Secure Register                       */
14660 
14661         struct
14662         {
14663             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
14664                                         *   generation circuit.                                                       */
14665             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
14666                                         *   modes, the low power modes, and the battery backup function.              */
14667             uint16_t            : 1;
14668             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the PVD.               */
14669             __IOM uint16_t PRC4 : 1;   /*!< [4..4] Enables writing to the registers related to the security
14670                                         *   and privilege setting registers.                                          */
14671             __IOM uint16_t PRC5 : 1;   /*!< [5..5] Enables writing to the registers related the reset control.        */
14672             uint16_t            : 2;
14673             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
14674         } PRCR_b;
14675     };
14676     __IM uint16_t RESERVED55;
14677 
14678     union
14679     {
14680         __IOM uint16_t PRCR_NS;        /*!< (@ 0x000003FE) Protect Register for Non-secure Register                   */
14681 
14682         struct
14683         {
14684             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
14685                                         *   generation circuit.                                                       */
14686             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
14687                                         *   modes, the low power modes, and the battery backup function.              */
14688             uint16_t            : 1;
14689             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the PVD.               */
14690             __IOM uint16_t PRC4 : 1;   /*!< [4..4] Enables writing to the registers related to the privilege
14691                                         *   setting registers.                                                        */
14692             uint16_t            : 3;
14693             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
14694         } PRCR_NS_b;
14695     };
14696 
14697     union
14698     {
14699         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register              */
14700 
14701         struct
14702         {
14703             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
14704             uint8_t             : 7;
14705         } LOCOCR_b;
14706     };
14707     __IM uint8_t RESERVED56;
14708 
14709     union
14710     {
14711         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000402) LOCO User Trimming Control Register                        */
14712 
14713         struct
14714         {
14715             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming                                                 */
14716         } LOCOUTCR_b;
14717     };
14718     __IM uint8_t  RESERVED57;
14719     __IM uint32_t RESERVED58[2];
14720     __IM uint16_t RESERVED59;
14721     __IM uint8_t  RESERVED60;
14722 
14723     union
14724     {
14725         __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
14726 
14727         struct
14728         {
14729             __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
14730             uint8_t             : 6;
14731         } STCONR_b;
14732     };
14733     __IM uint32_t RESERVED61[380];
14734 
14735     union
14736     {
14737         __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000A00) Deep Standby Control Register                              */
14738 
14739         struct
14740         {
14741             uint8_t                : 2;
14742             __IOM uint8_t DCSSMODE : 1; /*!< [2..2] DCDC SSMODE                                                        */
14743             uint8_t                : 1;
14744             __IOM uint8_t SRKEEP   : 1; /*!< [4..4] Standby RAM Retention                                              */
14745             uint8_t                : 1;
14746             __IOM uint8_t IOKEEP   : 1; /*!< [6..6] I/O Port Retention                                                 */
14747             __IOM uint8_t DPSBY    : 1; /*!< [7..7] Deep Software Standby                                              */
14748         } DPSBYCR_b;
14749     };
14750     __IM uint8_t  RESERVED62;
14751     __IM uint16_t RESERVED63;
14752 
14753     union
14754     {
14755         __IOM uint8_t DPSWCR;          /*!< (@ 0x00000A04) Deep Standby Wait Control Register                         */
14756 
14757         struct
14758         {
14759             __IOM uint8_t WTSTS : 8;   /*!< [7..0] Deep Software Wait Standby Time Setting Bit                        */
14760         } DPSWCR_b;
14761     };
14762     __IM uint8_t  RESERVED64;
14763     __IM uint16_t RESERVED65;
14764 
14765     union
14766     {
14767         __IOM uint8_t DPSIER0;         /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0                   */
14768 
14769         struct
14770         {
14771             __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ0-DS Pin Enable                                                 */
14772             __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ1-DS Pin Enable                                                 */
14773             __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ2-DS Pin Enable                                                 */
14774             __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ3-DS Pin Enable                                                 */
14775             __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ4-DS Pin Enable                                                 */
14776             __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ5-DS Pin Enable                                                 */
14777             __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ6-DS Pin Enable                                                 */
14778             __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ7-DS Pin Enable                                                 */
14779         } DPSIER0_b;
14780     };
14781     __IM uint8_t  RESERVED66;
14782     __IM uint16_t RESERVED67;
14783 
14784     union
14785     {
14786         __IOM uint8_t DPSIER1;         /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1                   */
14787 
14788         struct
14789         {
14790             __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ8-DS Pin Enable                                                 */
14791             __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ9-DS Pin Enable                                                 */
14792             __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ10-DS Pin Enable                                                */
14793             __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ11-DS Pin Enable                                                */
14794             __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ12-DS Pin Enable                                                */
14795             __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ13-DS Pin Enable                                                */
14796             __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ14-DS Pin Enable                                                */
14797             __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ15-DS Pin Enable                                                */
14798         } DPSIER1_b;
14799     };
14800     __IM uint8_t  RESERVED68;
14801     __IM uint16_t RESERVED69;
14802 
14803     union
14804     {
14805         __IOM uint8_t DPSIER2;          /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2                   */
14806 
14807         struct
14808         {
14809             __IOM uint8_t DPVD1IE  : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable                             */
14810             __IOM uint8_t DPVD2IE  : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable                             */
14811             __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
14812             __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
14813             __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
14814             uint8_t                : 3;
14815         } DPSIER2_b;
14816     };
14817     __IM uint8_t  RESERVED70;
14818     __IM uint16_t RESERVED71;
14819 
14820     union
14821     {
14822         __IOM uint8_t DPSIER3;            /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3                   */
14823 
14824         struct
14825         {
14826             __IOM uint8_t DUSBFSIE   : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
14827             __IOM uint8_t DUSBHSIE   : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
14828             __IOM uint8_t DULPT0IE   : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable                   */
14829             __IOM uint8_t DULPT1IE   : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable                   */
14830             uint8_t                  : 1;
14831             __IOM uint8_t DIWDTIE    : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable                    */
14832             uint8_t                  : 1;
14833             __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable           */
14834         } DPSIER3_b;
14835     };
14836     __IM uint8_t  RESERVED72;
14837     __IM uint16_t RESERVED73;
14838 
14839     union
14840     {
14841         __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0                     */
14842 
14843         struct
14844         {
14845             __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ0-DS Pin Deep Standby Cancel Flag                               */
14846             __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ1-DS Pin Deep Standby Cancel Flag                               */
14847             __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ2-DS Pin Deep Standby Cancel Flag                               */
14848             __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ3-DS Pin Deep Standby Cancel Flag                               */
14849             __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ4-DS Pin Deep Standby Cancel Flag                               */
14850             __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ5-DS Pin Deep Standby Cancel Flag                               */
14851             __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ6-DS Pin Deep Standby Cancel Flag                               */
14852             __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ7-DS Pin Deep Standby Cancel Flag                               */
14853         } DPSIFR0_b;
14854     };
14855     __IM uint8_t  RESERVED74;
14856     __IM uint16_t RESERVED75;
14857 
14858     union
14859     {
14860         __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1                     */
14861 
14862         struct
14863         {
14864             __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ8-DS Pin Deep Standby Cancel Flag                               */
14865             __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ9-DS Pin Deep Standby Cancel Flag                               */
14866             __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ10-DS Pin Deep Standby Cancel Flag                              */
14867             __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ11-DS Pin Deep Standby Cancel Flag                              */
14868             __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ12-DS Pin Deep Standby Cancel Flag                              */
14869             __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ13-DS Pin Deep Standby Cancel Flag                              */
14870             __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ14-DS Pin Deep Standby Cancel Flag                              */
14871             __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ15-DS Pin Deep Standby Cancel Flag                              */
14872         } DPSIFR1_b;
14873     };
14874     __IM uint8_t  RESERVED76;
14875     __IM uint16_t RESERVED77;
14876 
14877     union
14878     {
14879         __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2                     */
14880 
14881         struct
14882         {
14883             __IOM uint8_t DPVD1IF  : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag                                      */
14884             __IOM uint8_t DPVD2IF  : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag                                      */
14885             __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
14886             __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
14887             __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
14888             uint8_t                : 3;
14889         } DPSIFR2_b;
14890     };
14891     __IM uint8_t  RESERVED78;
14892     __IM uint16_t RESERVED79;
14893 
14894     union
14895     {
14896         __IOM uint8_t DPSIFR3;            /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3                     */
14897 
14898         struct
14899         {
14900             __IOM uint8_t DUSBFSIF   : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
14901             __IOM uint8_t DUSBHSIF   : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
14902             __IOM uint8_t DULPT0IF   : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag                            */
14903             __IOM uint8_t DULPT1IF   : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag                            */
14904             uint8_t                  : 1;
14905             __IOM uint8_t DIWDTIF    : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag                             */
14906             uint8_t                  : 1;
14907             __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag                    */
14908         } DPSIFR3_b;
14909     };
14910     __IM uint8_t  RESERVED80;
14911     __IM uint16_t RESERVED81;
14912 
14913     union
14914     {
14915         __IOM uint8_t DPSIEGR0;        /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0                     */
14916 
14917         struct
14918         {
14919             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ0-DS Pin Edge Select                                            */
14920             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ1-DS Pin Edge Select                                            */
14921             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ2-DS Pin Edge Select                                            */
14922             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ3-DS Pin Edge Select                                            */
14923             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ4-DS Pin Edge Select                                            */
14924             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ5-DS Pin Edge Select                                            */
14925             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ6-DS Pin Edge Select                                            */
14926             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ7-DS Pin Edge Select                                            */
14927         } DPSIEGR0_b;
14928     };
14929     __IM uint8_t  RESERVED82;
14930     __IM uint16_t RESERVED83;
14931 
14932     union
14933     {
14934         __IOM uint8_t DPSIEGR1;         /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1                     */
14935 
14936         struct
14937         {
14938             __IOM uint8_t DIRQ8EG  : 1; /*!< [0..0] IRQ8-DS Pin Edge Select                                            */
14939             __IOM uint8_t DIRQ9EG  : 1; /*!< [1..1] IRQ9-DS Pin Edge Select                                            */
14940             __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ10-DS Pin Edge Select                                           */
14941             __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ11-DS Pin Edge Select                                           */
14942             __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ12-DS Pin Edge Select                                           */
14943             __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ13-DS Pin Edge Select                                           */
14944             __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ14-DS Pin Edge Select                                           */
14945             __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ15-DS Pin Edge Select                                           */
14946         } DPSIEGR1_b;
14947     };
14948     __IM uint8_t  RESERVED84;
14949     __IM uint16_t RESERVED85;
14950 
14951     union
14952     {
14953         __IOM uint8_t DPSIEGR2;        /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2                     */
14954 
14955         struct
14956         {
14957             __IOM uint8_t DPVD1EG : 1; /*!< [0..0] PVD1 Edge Select                                                   */
14958             __IOM uint8_t DPVD2EG : 1; /*!< [1..1] PVD2 Edge Select                                                   */
14959             uint8_t               : 2;
14960             __IOM uint8_t DNMIEG  : 1; /*!< [4..4] NMI Pin Edge Select                                                */
14961             uint8_t               : 3;
14962         } DPSIEGR2_b;
14963     };
14964     __IM uint8_t  RESERVED86;
14965     __IM uint16_t RESERVED87;
14966     __IM uint32_t RESERVED88;
14967 
14968     union
14969     {
14970         __IOM uint8_t SYOCDCR;         /*!< (@ 0x00000A38) System Control OCD Control Register                        */
14971 
14972         struct
14973         {
14974             __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
14975             uint8_t             : 6;
14976             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
14977         } SYOCDCR_b;
14978     };
14979     __IM uint8_t  RESERVED89;
14980     __IM uint16_t RESERVED90;
14981     __IM uint32_t RESERVED91;
14982 
14983     union
14984     {
14985         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000A40) Reset Status Register 0                                    */
14986 
14987         struct
14988         {
14989             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect Flag. NOTE: Writable only to clear
14990                                         *   the flag. Confirm the value is 1 and then write 0.                        */
14991             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect Flag. NOTE: Writable only
14992                                         *   to clear the flag. Confirm the value is 1 and then write
14993                                         *   0.                                                                        */
14994             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect Flag. NOTE: Writable only
14995                                         *   to clear the flag. Confirm the value is 1 and then write
14996                                         *   0.                                                                        */
14997             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect Flag. NOTE: Writable only
14998                                         *   to clear the flag. Confirm the value is 1 and then write
14999                                         *   0.                                                                        */
15000             __IOM uint8_t LVD3RF : 1;  /*!< [4..4] Voltage Monitor 3 Reset Detect Flag. NOTE: Writable only
15001                                         *   to clear the flag. Confirm the value is 1 and then write
15002                                         *   0.                                                                        */
15003             __IOM uint8_t LVD4RF : 1;  /*!< [5..5] Voltage Monitor 4 Reset Detect Flag. NOTE: Writable only
15004                                         *   to clear the flag. Confirm the value is 1 and then write
15005                                         *   0.                                                                        */
15006             __IOM uint8_t LVD5RF : 1;  /*!< [6..6] Voltage Monitor 5 Reset Detect Flag. NOTE: Writable only
15007                                         *   to clear the flag. Confirm the value is 1 and then write
15008                                         *   0.                                                                        */
15009             __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag. NOTE: Writable only
15010                                         *   to clear the flag. Confirm the value is 1 and then write
15011                                         *   0.                                                                        */
15012         } RSTSR0_b;
15013     };
15014     __IM uint8_t  RESERVED92;
15015     __IM uint16_t RESERVED93;
15016 
15017     union
15018     {
15019         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000A44) Reset Status Register 2                                    */
15020 
15021         struct
15022         {
15023             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
15024             uint8_t            : 7;
15025         } RSTSR2_b;
15026     };
15027     __IM uint8_t  RESERVED94;
15028     __IM uint16_t RESERVED95;
15029 
15030     union
15031     {
15032         __IOM uint8_t RSTSR3;          /*!< (@ 0x00000A48) Reset Status Register 3                                    */
15033 
15034         struct
15035         {
15036             uint8_t             : 4;
15037             __IOM uint8_t OCPRF : 1;   /*!< [4..4] Overcurrent protection reset Detect Flag                           */
15038             uint8_t             : 3;
15039         } RSTSR3_b;
15040     };
15041     __IM uint8_t  RESERVED96;
15042     __IM uint16_t RESERVED97;
15043     __IM uint32_t RESERVED98;
15044 
15045     union
15046     {
15047         __IOM uint8_t MOMCR;           /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control
15048                                         *                  Register                                                   */
15049 
15050         struct
15051         {
15052             uint8_t              : 1;
15053             __IOM uint8_t MODRV0 : 3;  /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching                 */
15054             uint8_t              : 2;
15055             __IOM uint8_t MOSEL  : 1;  /*!< [6..6] Main Clock Oscillator Switching                                    */
15056             uint8_t              : 1;
15057         } MOMCR_b;
15058     };
15059     __IM uint8_t  RESERVED99;
15060     __IM uint16_t RESERVED100;
15061 
15062     union
15063     {
15064         __IOM uint8_t FWEPROR;         /*!< (@ 0x00000A54) Flash Write Erase Protect Register                         */
15065 
15066         struct
15067         {
15068             __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programing and Erasure                                       */
15069             uint8_t            : 6;
15070         } FWEPROR_b;
15071     };
15072     __IM uint8_t  RESERVED101;
15073     __IM uint16_t RESERVED102;
15074 
15075     union
15076     {
15077         union
15078         {
15079             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000A58) Voltage Monitor Circuit Control Register                   */
15080 
15081             struct
15082             {
15083                 uint8_t             : 5;
15084                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
15085                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
15086                 uint8_t             : 1;
15087             } LVCMPCR_b;
15088         };
15089 
15090         union
15091         {
15092             __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000A58) Voltage Monitor 1 Comparator Control Register              */
15093 
15094             struct
15095             {
15096                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Detection Voltage 1 Level Select(Standard voltage during
15097                                             *   drop in voltage)                                                          */
15098                 uint8_t             : 2;
15099                 __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
15100             } LVD1CMPCR_b;
15101         };
15102     };
15103     __IM uint8_t  RESERVED103;
15104     __IM uint16_t RESERVED104;
15105 
15106     union
15107     {
15108         __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000A5C) Voltage Monitor 2 Comparator Control Register              */
15109 
15110         struct
15111         {
15112             __IOM uint8_t LVD2LVL : 5; /*!< [4..0] Detection Voltage 2 Level Select(Standard voltage during
15113                                         *   drop in voltage)                                                          */
15114             uint8_t             : 2;
15115             __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
15116         } LVD2CMPCR_b;
15117     };
15118     __IM uint8_t  RESERVED105;
15119     __IM uint16_t RESERVED106;
15120     __IM uint32_t RESERVED107[4];
15121 
15122     union
15123     {
15124         __IOM uint8_t LVD1CR0;         /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0               */
15125 
15126         struct
15127         {
15128             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
15129             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
15130             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
15131             uint8_t             : 1;
15132             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
15133             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
15134             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
15135         } LVD1CR0_b;
15136     };
15137     __IM uint8_t  RESERVED108;
15138     __IM uint16_t RESERVED109;
15139 
15140     union
15141     {
15142         __IOM uint8_t LVD2CR0;         /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0               */
15143 
15144         struct
15145         {
15146             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
15147             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
15148             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
15149             uint8_t             : 1;
15150             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
15151             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
15152             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
15153         } LVD2CR0_b;
15154     };
15155     __IM uint8_t  RESERVED110;
15156     __IM uint16_t RESERVED111;
15157     __IM uint32_t RESERVED112[3];
15158 
15159     union
15160     {
15161         __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select
15162                                            *                  Register                                                   */
15163 
15164         struct
15165         {
15166             __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Voltage Monitor Function Select Bit                          */
15167             uint8_t                  : 7;
15168         } VBATTMNSELR_b;
15169     };
15170     __IM uint8_t  RESERVED113;
15171     __IM uint16_t RESERVED114;
15172 
15173     union
15174     {
15175         __IOM uint8_t VBTBPCR1;         /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1              */
15176 
15177         struct
15178         {
15179             __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop                                   */
15180             uint8_t                : 7;
15181         } VBTBPCR1_b;
15182     };
15183     __IM uint8_t  RESERVED115;
15184     __IM uint16_t RESERVED116;
15185     __IM uint32_t RESERVED117;
15186 
15187     union
15188     {
15189         __IOM uint8_t LPSCR;           /*!< (@ 0x00000A90) Low Power State Control Register                           */
15190 
15191         struct
15192         {
15193             __IOM uint8_t LPMD : 4;    /*!< [3..0] Low power mode setting bit                                         */
15194             uint8_t            : 4;
15195         } LPSCR_b;
15196     };
15197     __IM uint8_t  RESERVED118;
15198     __IM uint16_t RESERVED119;
15199     __IM uint32_t RESERVED120;
15200 
15201     union
15202     {
15203         __IOM uint8_t SSCR1;           /*!< (@ 0x00000A98) Software Standby Control Register 1                        */
15204 
15205         struct
15206         {
15207             __IOM uint8_t SS1FR : 1;   /*!< [0..0] Software Standby 1 Fast Return                                     */
15208             uint8_t             : 7;
15209         } SSCR1_b;
15210     };
15211     __IM uint8_t  RESERVED121;
15212     __IM uint16_t RESERVED122;
15213     __IM uint32_t RESERVED123[5];
15214 
15215     union
15216     {
15217         __IOM uint8_t LVOCR;           /*!< (@ 0x00000AB0) Low Power State Control Register                           */
15218 
15219         struct
15220         {
15221             __IOM uint8_t LVO0E : 1;   /*!< [0..0] Low Voltage Operation 0 Enable                                     */
15222             __IOM uint8_t LVO1E : 1;   /*!< [1..1] Low Voltage Operation 1 Enable                                     */
15223             uint8_t             : 6;
15224         } LVOCR_b;
15225     };
15226     __IM uint8_t  RESERVED124;
15227     __IM uint16_t RESERVED125;
15228     __IM uint32_t RESERVED126[7];
15229 
15230     union
15231     {
15232         __IOM uint8_t SYRSTMSK0;         /*!< (@ 0x00000AD0) System Reset Mask Control Register0                        */
15233 
15234         struct
15235         {
15236             __IOM uint8_t IWDTMASK  : 1; /*!< [0..0] Independent watchdog timer Reset Mask                              */
15237             __IOM uint8_t WDT0MASK  : 1; /*!< [1..1] CPU0 Watchdog timer Reset Mask                                     */
15238             __IOM uint8_t SWMASK    : 1; /*!< [2..2] Software Reset Mask                                                */
15239             uint8_t                 : 1;
15240             __IOM uint8_t CLUP0MASK : 1; /*!< [4..4] CPU0 Lockup Reset Mask                                             */
15241             __IOM uint8_t LM0MASK   : 1; /*!< [5..5] Local memory 0 error Reset Mask                                    */
15242             __IOM uint8_t CMMASK    : 1; /*!< [6..6] Common memory error Reset Mask                                     */
15243             __IOM uint8_t BUSMASK   : 1; /*!< [7..7] BUS error Reset Mask                                               */
15244         } SYRSTMSK0_b;
15245     };
15246     __IM uint8_t  RESERVED127;
15247     __IM uint16_t RESERVED128;
15248 
15249     union
15250     {
15251         __IOM uint8_t SYRSTMSK1;       /*!< (@ 0x00000AD4) System Reset Mask Control Register1                        */
15252 
15253         struct
15254         {
15255             uint8_t                 : 1;
15256             __IOM uint8_t WDT1MASK  : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask                                     */
15257             uint8_t                 : 2;
15258             __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask                                             */
15259             __IOM uint8_t LM1MASK   : 1; /*!< [5..5] Local memory 1 error Reset Mask                                    */
15260             uint8_t                 : 1;
15261             __IOM uint8_t NWMASK    : 1; /*!< [7..7] Network Reset Mask                                                 */
15262         } SYRSTMSK1_b;
15263     };
15264     __IM uint8_t  RESERVED129;
15265     __IM uint16_t RESERVED130;
15266 
15267     union
15268     {
15269         __IOM uint8_t SYRSTMSK2;        /*!< (@ 0x00000AD8) System Reset Mask Control Register2                        */
15270 
15271         struct
15272         {
15273             __IOM uint8_t LVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask                                       */
15274             __IOM uint8_t LVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask                                       */
15275             __IOM uint8_t LVD3MASK : 1; /*!< [2..2] Voltage Monitor 3 Reset Mask                                       */
15276             __IOM uint8_t LVD4MASK : 1; /*!< [3..3] Voltage Monitor 4 Reset Mask                                       */
15277             __IOM uint8_t LVD5MASK : 1; /*!< [4..4] Voltage Monitor 5 Reset Mask                                       */
15278             uint8_t                : 3;
15279         } SYRSTMSK2_b;
15280     };
15281     __IM uint8_t  RESERVED131;
15282     __IM uint16_t RESERVED132;
15283     __IM uint32_t RESERVED133[10];
15284 
15285     union
15286     {
15287         __IOM uint8_t PLL1LDOCR;       /*!< (@ 0x00000B04) PLL1-LDO Control Register                                  */
15288 
15289         struct
15290         {
15291             __IOM uint8_t LDOSTP : 1;  /*!< [0..0] LDO Stop                                                           */
15292             __IOM uint8_t SKEEP  : 1;  /*!< [1..1] STBY Keep                                                          */
15293             uint8_t              : 6;
15294         } PLL1LDOCR_b;
15295     };
15296     __IM uint8_t  RESERVED134;
15297     __IM uint16_t RESERVED135;
15298 
15299     union
15300     {
15301         __IOM uint8_t PLL2LDOCR;       /*!< (@ 0x00000B08) PLL2-LDO Control Register                                  */
15302 
15303         struct
15304         {
15305             __IOM uint8_t LDOSTP : 1;  /*!< [0..0] LDO Stop                                                           */
15306             __IOM uint8_t SKEEP  : 1;  /*!< [1..1] STBY Keep                                                          */
15307             uint8_t              : 6;
15308         } PLL2LDOCR_b;
15309     };
15310     __IM uint8_t  RESERVED136;
15311     __IM uint16_t RESERVED137;
15312 
15313     union
15314     {
15315         __IOM uint8_t HOCOLDOCR;       /*!< (@ 0x00000B0C) HOCO-LDO Control Register                                  */
15316 
15317         struct
15318         {
15319             __IOM uint8_t LDOSTP : 1;  /*!< [0..0] LDO Stop                                                           */
15320             __IOM uint8_t SKEEP  : 1;  /*!< [1..1] STBY Keep                                                          */
15321             uint8_t              : 6;
15322         } HOCOLDOCR_b;
15323     };
15324     __IM uint8_t  RESERVED138;
15325     __IM uint16_t RESERVED139;
15326     __IM uint32_t RESERVED140[4];
15327 
15328     union
15329     {
15330         __IOM uint8_t LVD1FCR;         /*!< (@ 0x00000B20) Voltage Monitor % Function Control Register                */
15331 
15332         struct
15333         {
15334             __IOM uint8_t RHSEL : 1;   /*!< [0..0] Rise Hysteresis Select                                             */
15335             uint8_t             : 7;
15336         } LVD1FCR_b;
15337     };
15338     __IM uint8_t  RESERVED141;
15339     __IM uint16_t RESERVED142;
15340 
15341     union
15342     {
15343         __IOM uint8_t LVD2FCR;         /*!< (@ 0x00000B24) Voltage Monitor % Function Control Register                */
15344 
15345         struct
15346         {
15347             __IOM uint8_t RHSEL : 1;   /*!< [0..0] Rise Hysteresis Select                                             */
15348             uint8_t             : 7;
15349         } LVD2FCR_b;
15350     };
15351     __IM uint8_t  RESERVED143;
15352     __IM uint16_t RESERVED144;
15353     __IM uint32_t RESERVED145[54];
15354 
15355     union
15356     {
15357         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000C00) Sub-clock oscillator control register                      */
15358 
15359         struct
15360         {
15361             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
15362             uint8_t             : 7;
15363         } SOSCCR_b;
15364     };
15365 
15366     union
15367     {
15368         __IOM uint8_t SOMCR;           /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register                 */
15369 
15370         struct
15371         {
15372             __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub Clock Oscillator Drive Capability Switching                    */
15373             uint8_t             : 4;
15374             __IOM uint8_t SOSEL : 1;   /*!< [6..6] Sub Clock Oscillator Switching                                     */
15375             uint8_t             : 1;
15376         } SOMCR_b;
15377     };
15378     __IM uint16_t RESERVED146;
15379     __IM uint32_t RESERVED147[15];
15380 
15381     union
15382     {
15383         __IOM uint8_t VBTBER;          /*!< (@ 0x00000C40) VBATT Backup Enable Register                               */
15384 
15385         struct
15386         {
15387             uint8_t            : 3;
15388             __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
15389             uint8_t            : 4;
15390         } VBTBER_b;
15391     };
15392     __IM uint8_t  RESERVED148;
15393     __IM uint16_t RESERVED149;
15394     __IM uint8_t  RESERVED150;
15395 
15396     union
15397     {
15398         __IOM uint8_t VBTBPCR2;        /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2              */
15399 
15400         struct
15401         {
15402             __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select                                               */
15403             uint8_t               : 1;
15404             __IOM uint8_t VDETE   : 1; /*!< [4..4] Voltage drop detection enable                                      */
15405             uint8_t               : 3;
15406         } VBTBPCR2_b;
15407     };
15408 
15409     union
15410     {
15411         __IOM uint8_t VBTBPSR;         /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register                 */
15412 
15413         struct
15414         {
15415             __IOM uint8_t VBPORF : 1;  /*!< [0..0] VBATT_POR Flag                                                     */
15416             uint8_t              : 3;
15417             __IOM uint8_t VBPORM : 1;  /*!< [4..4] VBATT_POR Monitor                                                  */
15418             __IOM uint8_t BPWSWM : 1;  /*!< [5..5] Battery Power Supply Switch Status Monitor                         */
15419             uint8_t              : 2;
15420         } VBTBPSR_b;
15421     };
15422     __IM uint8_t RESERVED151;
15423 
15424     union
15425     {
15426         __IOM uint8_t VBTADSR;         /*!< (@ 0x00000C48) VBATT Tamper detection Status Register                     */
15427 
15428         struct
15429         {
15430             __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0                                      */
15431             __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1                                      */
15432             __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2                                      */
15433             uint8_t               : 5;
15434         } VBTADSR_b;
15435     };
15436 
15437     union
15438     {
15439         __IOM uint8_t VBTADCR1;          /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1                  */
15440 
15441         struct
15442         {
15443             __IOM uint8_t VBTADIE0  : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0                          */
15444             __IOM uint8_t VBTADIE1  : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1                          */
15445             __IOM uint8_t VBTADIE2  : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2                          */
15446             uint8_t                 : 1;
15447             __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0              */
15448             __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1              */
15449             __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2              */
15450             uint8_t                 : 1;
15451         } VBTADCR1_b;
15452     };
15453 
15454     union
15455     {
15456         __IOM uint8_t VBTADCR2;         /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2                  */
15457 
15458         struct
15459         {
15460             __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0                       */
15461             __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1                       */
15462             __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2                       */
15463             uint8_t                : 5;
15464         } VBTADCR2_b;
15465     };
15466     __IM uint8_t RESERVED152;
15467 
15468     union
15469     {
15470         __IOM uint8_t VBTICTLR;         /*!< (@ 0x00000C4C) VBATT Input Control Register                               */
15471 
15472         struct
15473         {
15474             __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
15475             __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
15476             __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
15477             uint8_t                : 5;
15478         } VBTICTLR_b;
15479     };
15480 
15481     union
15482     {
15483         __IOM uint8_t VBTICTLR2;       /*!< (@ 0x00000C4D) VBATT Input Control Register 2                             */
15484 
15485         struct
15486         {
15487             __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable                              */
15488             __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable                              */
15489             __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable                              */
15490             uint8_t               : 1;
15491             __IOM uint8_t VCH0EG  : 1; /*!< [4..4] VBATT CH0 Input Edge Select                                        */
15492             __IOM uint8_t VCH1EG  : 1; /*!< [5..5] VBATT CH1 Input Edge Select                                        */
15493             __IOM uint8_t VCH2EG  : 1; /*!< [6..6] VBATT CH2 Input Edge Select                                        */
15494             uint8_t               : 1;
15495         } VBTICTLR2_b;
15496     };
15497 
15498     union
15499     {
15500         __IOM uint8_t VBTIMONR;        /*!< (@ 0x00000C4E) VBATT Input Monitor Register                               */
15501 
15502         struct
15503         {
15504             __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor                                            */
15505             __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor                                            */
15506             __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor                                            */
15507             uint8_t               : 5;
15508         } VBTIMONR_b;
15509     };
15510     __IM uint8_t  RESERVED153;
15511     __IM uint32_t RESERVED154[44];
15512 
15513     union
15514     {
15515         __IOM uint8_t VBTBKR0;         /*!< (@ 0x00000D00) VBATT Backup Register 0                                    */
15516 
15517         struct
15518         {
15519             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15520         } VBTBKR0_b;
15521     };
15522 
15523     union
15524     {
15525         __IOM uint8_t VBTBKR1;         /*!< (@ 0x00000D01) VBATT Backup Register 1                                    */
15526 
15527         struct
15528         {
15529             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15530         } VBTBKR1_b;
15531     };
15532 
15533     union
15534     {
15535         __IOM uint8_t VBTBKR2;         /*!< (@ 0x00000D02) VBATT Backup Register 2                                    */
15536 
15537         struct
15538         {
15539             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15540         } VBTBKR2_b;
15541     };
15542 
15543     union
15544     {
15545         __IOM uint8_t VBTBKR3;         /*!< (@ 0x00000D03) VBATT Backup Register 3                                    */
15546 
15547         struct
15548         {
15549             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15550         } VBTBKR3_b;
15551     };
15552 
15553     union
15554     {
15555         __IOM uint8_t VBTBKR4;         /*!< (@ 0x00000D04) VBATT Backup Register 4                                    */
15556 
15557         struct
15558         {
15559             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15560         } VBTBKR4_b;
15561     };
15562 
15563     union
15564     {
15565         __IOM uint8_t VBTBKR5;         /*!< (@ 0x00000D05) VBATT Backup Register 5                                    */
15566 
15567         struct
15568         {
15569             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15570         } VBTBKR5_b;
15571     };
15572 
15573     union
15574     {
15575         __IOM uint8_t VBTBKR6;         /*!< (@ 0x00000D06) VBATT Backup Register 6                                    */
15576 
15577         struct
15578         {
15579             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15580         } VBTBKR6_b;
15581     };
15582 
15583     union
15584     {
15585         __IOM uint8_t VBTBKR7;         /*!< (@ 0x00000D07) VBATT Backup Register 7                                    */
15586 
15587         struct
15588         {
15589             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15590         } VBTBKR7_b;
15591     };
15592 
15593     union
15594     {
15595         __IOM uint8_t VBTBKR8;         /*!< (@ 0x00000D08) VBATT Backup Register 8                                    */
15596 
15597         struct
15598         {
15599             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15600         } VBTBKR8_b;
15601     };
15602 
15603     union
15604     {
15605         __IOM uint8_t VBTBKR9;         /*!< (@ 0x00000D09) VBATT Backup Register 9                                    */
15606 
15607         struct
15608         {
15609             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15610         } VBTBKR9_b;
15611     };
15612 
15613     union
15614     {
15615         __IOM uint8_t VBTBKR10;        /*!< (@ 0x00000D0A) VBATT Backup Register 10                                   */
15616 
15617         struct
15618         {
15619             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15620         } VBTBKR10_b;
15621     };
15622 
15623     union
15624     {
15625         __IOM uint8_t VBTBKR11;        /*!< (@ 0x00000D0B) VBATT Backup Register 11                                   */
15626 
15627         struct
15628         {
15629             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15630         } VBTBKR11_b;
15631     };
15632 
15633     union
15634     {
15635         __IOM uint8_t VBTBKR12;        /*!< (@ 0x00000D0C) VBATT Backup Register 12                                   */
15636 
15637         struct
15638         {
15639             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15640         } VBTBKR12_b;
15641     };
15642 
15643     union
15644     {
15645         __IOM uint8_t VBTBKR13;        /*!< (@ 0x00000D0D) VBATT Backup Register 13                                   */
15646 
15647         struct
15648         {
15649             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15650         } VBTBKR13_b;
15651     };
15652 
15653     union
15654     {
15655         __IOM uint8_t VBTBKR14;        /*!< (@ 0x00000D0E) VBATT Backup Register 14                                   */
15656 
15657         struct
15658         {
15659             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15660         } VBTBKR14_b;
15661     };
15662 
15663     union
15664     {
15665         __IOM uint8_t VBTBKR15;        /*!< (@ 0x00000D0F) VBATT Backup Register 15                                   */
15666 
15667         struct
15668         {
15669             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15670         } VBTBKR15_b;
15671     };
15672 
15673     union
15674     {
15675         __IOM uint8_t VBTBKR16;        /*!< (@ 0x00000D10) VBATT Backup Register 16                                   */
15676 
15677         struct
15678         {
15679             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15680         } VBTBKR16_b;
15681     };
15682 
15683     union
15684     {
15685         __IOM uint8_t VBTBKR17;        /*!< (@ 0x00000D11) VBATT Backup Register 17                                   */
15686 
15687         struct
15688         {
15689             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15690         } VBTBKR17_b;
15691     };
15692 
15693     union
15694     {
15695         __IOM uint8_t VBTBKR18;        /*!< (@ 0x00000D12) VBATT Backup Register 18                                   */
15696 
15697         struct
15698         {
15699             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15700         } VBTBKR18_b;
15701     };
15702 
15703     union
15704     {
15705         __IOM uint8_t VBTBKR19;        /*!< (@ 0x00000D13) VBATT Backup Register 19                                   */
15706 
15707         struct
15708         {
15709             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15710         } VBTBKR19_b;
15711     };
15712 
15713     union
15714     {
15715         __IOM uint8_t VBTBKR20;        /*!< (@ 0x00000D14) VBATT Backup Register 20                                   */
15716 
15717         struct
15718         {
15719             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15720         } VBTBKR20_b;
15721     };
15722 
15723     union
15724     {
15725         __IOM uint8_t VBTBKR21;        /*!< (@ 0x00000D15) VBATT Backup Register 21                                   */
15726 
15727         struct
15728         {
15729             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15730         } VBTBKR21_b;
15731     };
15732 
15733     union
15734     {
15735         __IOM uint8_t VBTBKR22;        /*!< (@ 0x00000D16) VBATT Backup Register 22                                   */
15736 
15737         struct
15738         {
15739             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15740         } VBTBKR22_b;
15741     };
15742 
15743     union
15744     {
15745         __IOM uint8_t VBTBKR23;        /*!< (@ 0x00000D17) VBATT Backup Register 23                                   */
15746 
15747         struct
15748         {
15749             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15750         } VBTBKR23_b;
15751     };
15752 
15753     union
15754     {
15755         __IOM uint8_t VBTBKR24;        /*!< (@ 0x00000D18) VBATT Backup Register 24                                   */
15756 
15757         struct
15758         {
15759             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15760         } VBTBKR24_b;
15761     };
15762 
15763     union
15764     {
15765         __IOM uint8_t VBTBKR25;        /*!< (@ 0x00000D19) VBATT Backup Register 25                                   */
15766 
15767         struct
15768         {
15769             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15770         } VBTBKR25_b;
15771     };
15772 
15773     union
15774     {
15775         __IOM uint8_t VBTBKR26;        /*!< (@ 0x00000D1A) VBATT Backup Register 26                                   */
15776 
15777         struct
15778         {
15779             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15780         } VBTBKR26_b;
15781     };
15782 
15783     union
15784     {
15785         __IOM uint8_t VBTBKR27;        /*!< (@ 0x00000D1B) VBATT Backup Register 27                                   */
15786 
15787         struct
15788         {
15789             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15790         } VBTBKR27_b;
15791     };
15792 
15793     union
15794     {
15795         __IOM uint8_t VBTBKR28;        /*!< (@ 0x00000D1C) VBATT Backup Register 28                                   */
15796 
15797         struct
15798         {
15799             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15800         } VBTBKR28_b;
15801     };
15802 
15803     union
15804     {
15805         __IOM uint8_t VBTBKR29;        /*!< (@ 0x00000D1D) VBATT Backup Register 29                                   */
15806 
15807         struct
15808         {
15809             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15810         } VBTBKR29_b;
15811     };
15812 
15813     union
15814     {
15815         __IOM uint8_t VBTBKR30;        /*!< (@ 0x00000D1E) VBATT Backup Register 30                                   */
15816 
15817         struct
15818         {
15819             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15820         } VBTBKR30_b;
15821     };
15822 
15823     union
15824     {
15825         __IOM uint8_t VBTBKR31;        /*!< (@ 0x00000D1F) VBATT Backup Register 31                                   */
15826 
15827         struct
15828         {
15829             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15830         } VBTBKR31_b;
15831     };
15832 
15833     union
15834     {
15835         __IOM uint8_t VBTBKR32;        /*!< (@ 0x00000D20) VBATT Backup Register 32                                   */
15836 
15837         struct
15838         {
15839             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15840         } VBTBKR32_b;
15841     };
15842 
15843     union
15844     {
15845         __IOM uint8_t VBTBKR33;        /*!< (@ 0x00000D21) VBATT Backup Register 33                                   */
15846 
15847         struct
15848         {
15849             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15850         } VBTBKR33_b;
15851     };
15852 
15853     union
15854     {
15855         __IOM uint8_t VBTBKR34;        /*!< (@ 0x00000D22) VBATT Backup Register 34                                   */
15856 
15857         struct
15858         {
15859             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15860         } VBTBKR34_b;
15861     };
15862 
15863     union
15864     {
15865         __IOM uint8_t VBTBKR35;        /*!< (@ 0x00000D23) VBATT Backup Register 35                                   */
15866 
15867         struct
15868         {
15869             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15870         } VBTBKR35_b;
15871     };
15872 
15873     union
15874     {
15875         __IOM uint8_t VBTBKR36;        /*!< (@ 0x00000D24) VBATT Backup Register 36                                   */
15876 
15877         struct
15878         {
15879             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15880         } VBTBKR36_b;
15881     };
15882 
15883     union
15884     {
15885         __IOM uint8_t VBTBKR37;        /*!< (@ 0x00000D25) VBATT Backup Register 37                                   */
15886 
15887         struct
15888         {
15889             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15890         } VBTBKR37_b;
15891     };
15892 
15893     union
15894     {
15895         __IOM uint8_t VBTBKR38;        /*!< (@ 0x00000D26) VBATT Backup Register 38                                   */
15896 
15897         struct
15898         {
15899             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15900         } VBTBKR38_b;
15901     };
15902 
15903     union
15904     {
15905         __IOM uint8_t VBTBKR39;        /*!< (@ 0x00000D27) VBATT Backup Register 39                                   */
15906 
15907         struct
15908         {
15909             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15910         } VBTBKR39_b;
15911     };
15912 
15913     union
15914     {
15915         __IOM uint8_t VBTBKR40;        /*!< (@ 0x00000D28) VBATT Backup Register 40                                   */
15916 
15917         struct
15918         {
15919             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15920         } VBTBKR40_b;
15921     };
15922 
15923     union
15924     {
15925         __IOM uint8_t VBTBKR41;        /*!< (@ 0x00000D29) VBATT Backup Register 41                                   */
15926 
15927         struct
15928         {
15929             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15930         } VBTBKR41_b;
15931     };
15932 
15933     union
15934     {
15935         __IOM uint8_t VBTBKR42;        /*!< (@ 0x00000D2A) VBATT Backup Register 42                                   */
15936 
15937         struct
15938         {
15939             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15940         } VBTBKR42_b;
15941     };
15942 
15943     union
15944     {
15945         __IOM uint8_t VBTBKR43;        /*!< (@ 0x00000D2B) VBATT Backup Register 43                                   */
15946 
15947         struct
15948         {
15949             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15950         } VBTBKR43_b;
15951     };
15952 
15953     union
15954     {
15955         __IOM uint8_t VBTBKR44;        /*!< (@ 0x00000D2C) VBATT Backup Register 44                                   */
15956 
15957         struct
15958         {
15959             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15960         } VBTBKR44_b;
15961     };
15962 
15963     union
15964     {
15965         __IOM uint8_t VBTBKR45;        /*!< (@ 0x00000D2D) VBATT Backup Register 45                                   */
15966 
15967         struct
15968         {
15969             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15970         } VBTBKR45_b;
15971     };
15972 
15973     union
15974     {
15975         __IOM uint8_t VBTBKR46;        /*!< (@ 0x00000D2E) VBATT Backup Register 46                                   */
15976 
15977         struct
15978         {
15979             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15980         } VBTBKR46_b;
15981     };
15982 
15983     union
15984     {
15985         __IOM uint8_t VBTBKR47;        /*!< (@ 0x00000D2F) VBATT Backup Register 47                                   */
15986 
15987         struct
15988         {
15989             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
15990         } VBTBKR47_b;
15991     };
15992 
15993     union
15994     {
15995         __IOM uint8_t VBTBKR48;        /*!< (@ 0x00000D30) VBATT Backup Register 48                                   */
15996 
15997         struct
15998         {
15999             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16000         } VBTBKR48_b;
16001     };
16002 
16003     union
16004     {
16005         __IOM uint8_t VBTBKR49;        /*!< (@ 0x00000D31) VBATT Backup Register 49                                   */
16006 
16007         struct
16008         {
16009             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16010         } VBTBKR49_b;
16011     };
16012 
16013     union
16014     {
16015         __IOM uint8_t VBTBKR50;        /*!< (@ 0x00000D32) VBATT Backup Register 50                                   */
16016 
16017         struct
16018         {
16019             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16020         } VBTBKR50_b;
16021     };
16022 
16023     union
16024     {
16025         __IOM uint8_t VBTBKR51;        /*!< (@ 0x00000D33) VBATT Backup Register 51                                   */
16026 
16027         struct
16028         {
16029             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16030         } VBTBKR51_b;
16031     };
16032 
16033     union
16034     {
16035         __IOM uint8_t VBTBKR52;        /*!< (@ 0x00000D34) VBATT Backup Register 52                                   */
16036 
16037         struct
16038         {
16039             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16040         } VBTBKR52_b;
16041     };
16042 
16043     union
16044     {
16045         __IOM uint8_t VBTBKR53;        /*!< (@ 0x00000D35) VBATT Backup Register 53                                   */
16046 
16047         struct
16048         {
16049             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16050         } VBTBKR53_b;
16051     };
16052 
16053     union
16054     {
16055         __IOM uint8_t VBTBKR54;        /*!< (@ 0x00000D36) VBATT Backup Register 54                                   */
16056 
16057         struct
16058         {
16059             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16060         } VBTBKR54_b;
16061     };
16062 
16063     union
16064     {
16065         __IOM uint8_t VBTBKR55;        /*!< (@ 0x00000D37) VBATT Backup Register 55                                   */
16066 
16067         struct
16068         {
16069             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16070         } VBTBKR55_b;
16071     };
16072 
16073     union
16074     {
16075         __IOM uint8_t VBTBKR56;        /*!< (@ 0x00000D38) VBATT Backup Register 56                                   */
16076 
16077         struct
16078         {
16079             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16080         } VBTBKR56_b;
16081     };
16082 
16083     union
16084     {
16085         __IOM uint8_t VBTBKR57;        /*!< (@ 0x00000D39) VBATT Backup Register 57                                   */
16086 
16087         struct
16088         {
16089             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16090         } VBTBKR57_b;
16091     };
16092 
16093     union
16094     {
16095         __IOM uint8_t VBTBKR58;        /*!< (@ 0x00000D3A) VBATT Backup Register 58                                   */
16096 
16097         struct
16098         {
16099             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16100         } VBTBKR58_b;
16101     };
16102 
16103     union
16104     {
16105         __IOM uint8_t VBTBKR59;        /*!< (@ 0x00000D3B) VBATT Backup Register 59                                   */
16106 
16107         struct
16108         {
16109             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16110         } VBTBKR59_b;
16111     };
16112 
16113     union
16114     {
16115         __IOM uint8_t VBTBKR60;        /*!< (@ 0x00000D3C) VBATT Backup Register 60                                   */
16116 
16117         struct
16118         {
16119             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16120         } VBTBKR60_b;
16121     };
16122 
16123     union
16124     {
16125         __IOM uint8_t VBTBKR61;        /*!< (@ 0x00000D3D) VBATT Backup Register 61                                   */
16126 
16127         struct
16128         {
16129             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16130         } VBTBKR61_b;
16131     };
16132 
16133     union
16134     {
16135         __IOM uint8_t VBTBKR62;        /*!< (@ 0x00000D3E) VBATT Backup Register 62                                   */
16136 
16137         struct
16138         {
16139             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16140         } VBTBKR62_b;
16141     };
16142 
16143     union
16144     {
16145         __IOM uint8_t VBTBKR63;        /*!< (@ 0x00000D3F) VBATT Backup Register 63                                   */
16146 
16147         struct
16148         {
16149             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16150         } VBTBKR63_b;
16151     };
16152 
16153     union
16154     {
16155         __IOM uint8_t VBTBKR64;        /*!< (@ 0x00000D40) VBATT Backup Register 64                                   */
16156 
16157         struct
16158         {
16159             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16160         } VBTBKR64_b;
16161     };
16162 
16163     union
16164     {
16165         __IOM uint8_t VBTBKR65;        /*!< (@ 0x00000D41) VBATT Backup Register 65                                   */
16166 
16167         struct
16168         {
16169             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16170         } VBTBKR65_b;
16171     };
16172 
16173     union
16174     {
16175         __IOM uint8_t VBTBKR66;        /*!< (@ 0x00000D42) VBATT Backup Register 66                                   */
16176 
16177         struct
16178         {
16179             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16180         } VBTBKR66_b;
16181     };
16182 
16183     union
16184     {
16185         __IOM uint8_t VBTBKR67;        /*!< (@ 0x00000D43) VBATT Backup Register 67                                   */
16186 
16187         struct
16188         {
16189             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16190         } VBTBKR67_b;
16191     };
16192 
16193     union
16194     {
16195         __IOM uint8_t VBTBKR68;        /*!< (@ 0x00000D44) VBATT Backup Register 68                                   */
16196 
16197         struct
16198         {
16199             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16200         } VBTBKR68_b;
16201     };
16202 
16203     union
16204     {
16205         __IOM uint8_t VBTBKR69;        /*!< (@ 0x00000D45) VBATT Backup Register 69                                   */
16206 
16207         struct
16208         {
16209             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16210         } VBTBKR69_b;
16211     };
16212 
16213     union
16214     {
16215         __IOM uint8_t VBTBKR70;        /*!< (@ 0x00000D46) VBATT Backup Register 70                                   */
16216 
16217         struct
16218         {
16219             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16220         } VBTBKR70_b;
16221     };
16222 
16223     union
16224     {
16225         __IOM uint8_t VBTBKR71;        /*!< (@ 0x00000D47) VBATT Backup Register 71                                   */
16226 
16227         struct
16228         {
16229             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16230         } VBTBKR71_b;
16231     };
16232 
16233     union
16234     {
16235         __IOM uint8_t VBTBKR72;        /*!< (@ 0x00000D48) VBATT Backup Register 72                                   */
16236 
16237         struct
16238         {
16239             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16240         } VBTBKR72_b;
16241     };
16242 
16243     union
16244     {
16245         __IOM uint8_t VBTBKR73;        /*!< (@ 0x00000D49) VBATT Backup Register 73                                   */
16246 
16247         struct
16248         {
16249             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16250         } VBTBKR73_b;
16251     };
16252 
16253     union
16254     {
16255         __IOM uint8_t VBTBKR74;        /*!< (@ 0x00000D4A) VBATT Backup Register 74                                   */
16256 
16257         struct
16258         {
16259             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16260         } VBTBKR74_b;
16261     };
16262 
16263     union
16264     {
16265         __IOM uint8_t VBTBKR75;        /*!< (@ 0x00000D4B) VBATT Backup Register 75                                   */
16266 
16267         struct
16268         {
16269             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16270         } VBTBKR75_b;
16271     };
16272 
16273     union
16274     {
16275         __IOM uint8_t VBTBKR76;        /*!< (@ 0x00000D4C) VBATT Backup Register 76                                   */
16276 
16277         struct
16278         {
16279             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16280         } VBTBKR76_b;
16281     };
16282 
16283     union
16284     {
16285         __IOM uint8_t VBTBKR77;        /*!< (@ 0x00000D4D) VBATT Backup Register 77                                   */
16286 
16287         struct
16288         {
16289             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16290         } VBTBKR77_b;
16291     };
16292 
16293     union
16294     {
16295         __IOM uint8_t VBTBKR78;        /*!< (@ 0x00000D4E) VBATT Backup Register 78                                   */
16296 
16297         struct
16298         {
16299             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16300         } VBTBKR78_b;
16301     };
16302 
16303     union
16304     {
16305         __IOM uint8_t VBTBKR79;        /*!< (@ 0x00000D4F) VBATT Backup Register 79                                   */
16306 
16307         struct
16308         {
16309             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16310         } VBTBKR79_b;
16311     };
16312 
16313     union
16314     {
16315         __IOM uint8_t VBTBKR80;        /*!< (@ 0x00000D50) VBATT Backup Register 80                                   */
16316 
16317         struct
16318         {
16319             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16320         } VBTBKR80_b;
16321     };
16322 
16323     union
16324     {
16325         __IOM uint8_t VBTBKR81;        /*!< (@ 0x00000D51) VBATT Backup Register 81                                   */
16326 
16327         struct
16328         {
16329             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16330         } VBTBKR81_b;
16331     };
16332 
16333     union
16334     {
16335         __IOM uint8_t VBTBKR82;        /*!< (@ 0x00000D52) VBATT Backup Register 82                                   */
16336 
16337         struct
16338         {
16339             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16340         } VBTBKR82_b;
16341     };
16342 
16343     union
16344     {
16345         __IOM uint8_t VBTBKR83;        /*!< (@ 0x00000D53) VBATT Backup Register 83                                   */
16346 
16347         struct
16348         {
16349             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16350         } VBTBKR83_b;
16351     };
16352 
16353     union
16354     {
16355         __IOM uint8_t VBTBKR84;        /*!< (@ 0x00000D54) VBATT Backup Register 84                                   */
16356 
16357         struct
16358         {
16359             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16360         } VBTBKR84_b;
16361     };
16362 
16363     union
16364     {
16365         __IOM uint8_t VBTBKR85;        /*!< (@ 0x00000D55) VBATT Backup Register 85                                   */
16366 
16367         struct
16368         {
16369             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16370         } VBTBKR85_b;
16371     };
16372 
16373     union
16374     {
16375         __IOM uint8_t VBTBKR86;        /*!< (@ 0x00000D56) VBATT Backup Register 86                                   */
16376 
16377         struct
16378         {
16379             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16380         } VBTBKR86_b;
16381     };
16382 
16383     union
16384     {
16385         __IOM uint8_t VBTBKR87;        /*!< (@ 0x00000D57) VBATT Backup Register 87                                   */
16386 
16387         struct
16388         {
16389             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16390         } VBTBKR87_b;
16391     };
16392 
16393     union
16394     {
16395         __IOM uint8_t VBTBKR88;        /*!< (@ 0x00000D58) VBATT Backup Register 88                                   */
16396 
16397         struct
16398         {
16399             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16400         } VBTBKR88_b;
16401     };
16402 
16403     union
16404     {
16405         __IOM uint8_t VBTBKR89;        /*!< (@ 0x00000D59) VBATT Backup Register 89                                   */
16406 
16407         struct
16408         {
16409             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16410         } VBTBKR89_b;
16411     };
16412 
16413     union
16414     {
16415         __IOM uint8_t VBTBKR90;        /*!< (@ 0x00000D5A) VBATT Backup Register 90                                   */
16416 
16417         struct
16418         {
16419             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16420         } VBTBKR90_b;
16421     };
16422 
16423     union
16424     {
16425         __IOM uint8_t VBTBKR91;        /*!< (@ 0x00000D5B) VBATT Backup Register 91                                   */
16426 
16427         struct
16428         {
16429             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16430         } VBTBKR91_b;
16431     };
16432 
16433     union
16434     {
16435         __IOM uint8_t VBTBKR92;        /*!< (@ 0x00000D5C) VBATT Backup Register 92                                   */
16436 
16437         struct
16438         {
16439             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16440         } VBTBKR92_b;
16441     };
16442 
16443     union
16444     {
16445         __IOM uint8_t VBTBKR93;        /*!< (@ 0x00000D5D) VBATT Backup Register 93                                   */
16446 
16447         struct
16448         {
16449             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16450         } VBTBKR93_b;
16451     };
16452 
16453     union
16454     {
16455         __IOM uint8_t VBTBKR94;        /*!< (@ 0x00000D5E) VBATT Backup Register 94                                   */
16456 
16457         struct
16458         {
16459             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16460         } VBTBKR94_b;
16461     };
16462 
16463     union
16464     {
16465         __IOM uint8_t VBTBKR95;        /*!< (@ 0x00000D5F) VBATT Backup Register 95                                   */
16466 
16467         struct
16468         {
16469             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16470         } VBTBKR95_b;
16471     };
16472 
16473     union
16474     {
16475         __IOM uint8_t VBTBKR96;        /*!< (@ 0x00000D60) VBATT Backup Register 96                                   */
16476 
16477         struct
16478         {
16479             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16480         } VBTBKR96_b;
16481     };
16482 
16483     union
16484     {
16485         __IOM uint8_t VBTBKR97;        /*!< (@ 0x00000D61) VBATT Backup Register 97                                   */
16486 
16487         struct
16488         {
16489             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16490         } VBTBKR97_b;
16491     };
16492 
16493     union
16494     {
16495         __IOM uint8_t VBTBKR98;        /*!< (@ 0x00000D62) VBATT Backup Register 98                                   */
16496 
16497         struct
16498         {
16499             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16500         } VBTBKR98_b;
16501     };
16502 
16503     union
16504     {
16505         __IOM uint8_t VBTBKR99;        /*!< (@ 0x00000D63) VBATT Backup Register 99                                   */
16506 
16507         struct
16508         {
16509             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16510         } VBTBKR99_b;
16511     };
16512 
16513     union
16514     {
16515         __IOM uint8_t VBTBKR100;       /*!< (@ 0x00000D64) VBATT Backup Register 100                                  */
16516 
16517         struct
16518         {
16519             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16520         } VBTBKR100_b;
16521     };
16522 
16523     union
16524     {
16525         __IOM uint8_t VBTBKR101;       /*!< (@ 0x00000D65) VBATT Backup Register 101                                  */
16526 
16527         struct
16528         {
16529             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16530         } VBTBKR101_b;
16531     };
16532 
16533     union
16534     {
16535         __IOM uint8_t VBTBKR102;       /*!< (@ 0x00000D66) VBATT Backup Register 102                                  */
16536 
16537         struct
16538         {
16539             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16540         } VBTBKR102_b;
16541     };
16542 
16543     union
16544     {
16545         __IOM uint8_t VBTBKR103;       /*!< (@ 0x00000D67) VBATT Backup Register 103                                  */
16546 
16547         struct
16548         {
16549             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16550         } VBTBKR103_b;
16551     };
16552 
16553     union
16554     {
16555         __IOM uint8_t VBTBKR104;       /*!< (@ 0x00000D68) VBATT Backup Register 104                                  */
16556 
16557         struct
16558         {
16559             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16560         } VBTBKR104_b;
16561     };
16562 
16563     union
16564     {
16565         __IOM uint8_t VBTBKR105;       /*!< (@ 0x00000D69) VBATT Backup Register 105                                  */
16566 
16567         struct
16568         {
16569             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16570         } VBTBKR105_b;
16571     };
16572 
16573     union
16574     {
16575         __IOM uint8_t VBTBKR106;       /*!< (@ 0x00000D6A) VBATT Backup Register 106                                  */
16576 
16577         struct
16578         {
16579             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16580         } VBTBKR106_b;
16581     };
16582 
16583     union
16584     {
16585         __IOM uint8_t VBTBKR107;       /*!< (@ 0x00000D6B) VBATT Backup Register 107                                  */
16586 
16587         struct
16588         {
16589             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16590         } VBTBKR107_b;
16591     };
16592 
16593     union
16594     {
16595         __IOM uint8_t VBTBKR108;       /*!< (@ 0x00000D6C) VBATT Backup Register 108                                  */
16596 
16597         struct
16598         {
16599             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16600         } VBTBKR108_b;
16601     };
16602 
16603     union
16604     {
16605         __IOM uint8_t VBTBKR109;       /*!< (@ 0x00000D6D) VBATT Backup Register 109                                  */
16606 
16607         struct
16608         {
16609             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16610         } VBTBKR109_b;
16611     };
16612 
16613     union
16614     {
16615         __IOM uint8_t VBTBKR110;       /*!< (@ 0x00000D6E) VBATT Backup Register 110                                  */
16616 
16617         struct
16618         {
16619             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16620         } VBTBKR110_b;
16621     };
16622 
16623     union
16624     {
16625         __IOM uint8_t VBTBKR111;       /*!< (@ 0x00000D6F) VBATT Backup Register 111                                  */
16626 
16627         struct
16628         {
16629             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16630         } VBTBKR111_b;
16631     };
16632 
16633     union
16634     {
16635         __IOM uint8_t VBTBKR112;       /*!< (@ 0x00000D70) VBATT Backup Register 112                                  */
16636 
16637         struct
16638         {
16639             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16640         } VBTBKR112_b;
16641     };
16642 
16643     union
16644     {
16645         __IOM uint8_t VBTBKR113;       /*!< (@ 0x00000D71) VBATT Backup Register 113                                  */
16646 
16647         struct
16648         {
16649             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16650         } VBTBKR113_b;
16651     };
16652 
16653     union
16654     {
16655         __IOM uint8_t VBTBKR114;       /*!< (@ 0x00000D72) VBATT Backup Register 114                                  */
16656 
16657         struct
16658         {
16659             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16660         } VBTBKR114_b;
16661     };
16662 
16663     union
16664     {
16665         __IOM uint8_t VBTBKR115;       /*!< (@ 0x00000D73) VBATT Backup Register 115                                  */
16666 
16667         struct
16668         {
16669             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16670         } VBTBKR115_b;
16671     };
16672 
16673     union
16674     {
16675         __IOM uint8_t VBTBKR116;       /*!< (@ 0x00000D74) VBATT Backup Register 116                                  */
16676 
16677         struct
16678         {
16679             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16680         } VBTBKR116_b;
16681     };
16682 
16683     union
16684     {
16685         __IOM uint8_t VBTBKR117;       /*!< (@ 0x00000D75) VBATT Backup Register 117                                  */
16686 
16687         struct
16688         {
16689             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16690         } VBTBKR117_b;
16691     };
16692 
16693     union
16694     {
16695         __IOM uint8_t VBTBKR118;       /*!< (@ 0x00000D76) VBATT Backup Register 118                                  */
16696 
16697         struct
16698         {
16699             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16700         } VBTBKR118_b;
16701     };
16702 
16703     union
16704     {
16705         __IOM uint8_t VBTBKR119;       /*!< (@ 0x00000D77) VBATT Backup Register 119                                  */
16706 
16707         struct
16708         {
16709             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16710         } VBTBKR119_b;
16711     };
16712 
16713     union
16714     {
16715         __IOM uint8_t VBTBKR120;       /*!< (@ 0x00000D78) VBATT Backup Register 120                                  */
16716 
16717         struct
16718         {
16719             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16720         } VBTBKR120_b;
16721     };
16722 
16723     union
16724     {
16725         __IOM uint8_t VBTBKR121;       /*!< (@ 0x00000D79) VBATT Backup Register 121                                  */
16726 
16727         struct
16728         {
16729             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16730         } VBTBKR121_b;
16731     };
16732 
16733     union
16734     {
16735         __IOM uint8_t VBTBKR122;       /*!< (@ 0x00000D7A) VBATT Backup Register 122                                  */
16736 
16737         struct
16738         {
16739             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16740         } VBTBKR122_b;
16741     };
16742 
16743     union
16744     {
16745         __IOM uint8_t VBTBKR123;       /*!< (@ 0x00000D7B) VBATT Backup Register 123                                  */
16746 
16747         struct
16748         {
16749             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16750         } VBTBKR123_b;
16751     };
16752 
16753     union
16754     {
16755         __IOM uint8_t VBTBKR124;       /*!< (@ 0x00000D7C) VBATT Backup Register 124                                  */
16756 
16757         struct
16758         {
16759             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16760         } VBTBKR124_b;
16761     };
16762 
16763     union
16764     {
16765         __IOM uint8_t VBTBKR125;       /*!< (@ 0x00000D7D) VBATT Backup Register 125                                  */
16766 
16767         struct
16768         {
16769             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16770         } VBTBKR125_b;
16771     };
16772 
16773     union
16774     {
16775         __IOM uint8_t VBTBKR126;       /*!< (@ 0x00000D7E) VBATT Backup Register 126                                  */
16776 
16777         struct
16778         {
16779             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16780         } VBTBKR126_b;
16781     };
16782 
16783     union
16784     {
16785         __IOM uint8_t VBTBKR127;       /*!< (@ 0x00000D7F) VBATT Backup Register 127                                  */
16786 
16787         struct
16788         {
16789             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
16790         } VBTBKR127_b;
16791     };
16792 } R_SYSTEM_Type;                       /*!< Size = 3456 (0xd80)                                                       */
16793 
16794 /* =========================================================================================================================== */
16795 /* ================                                         R_TSN_CAL                                         ================ */
16796 /* =========================================================================================================================== */
16797 
16798 /**
16799  * @brief Temperature Sensor (R_TSN_CAL)
16800  */
16801 
16802 typedef struct                         /*!< (@ 0x4011B17C) R_TSN_CAL Structure                                        */
16803 {
16804     union
16805     {
16806         __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
16807 
16808         struct
16809         {
16810             __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
16811                                         *   calibration converted value.                                              */
16812         } TSCDR_b;
16813     };
16814 } R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
16815 
16816 /* =========================================================================================================================== */
16817 /* ================                                        R_TSN_CTRL                                         ================ */
16818 /* =========================================================================================================================== */
16819 
16820 /**
16821  * @brief Temperature Sensor (R_TSN_CTRL)
16822  */
16823 
16824 typedef struct                         /*!< (@ 0x40235000) R_TSN_CTRL Structure                                       */
16825 {
16826     union
16827     {
16828         __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
16829 
16830         struct
16831         {
16832             uint8_t            : 4;
16833             __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
16834             uint8_t            : 2;
16835             __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
16836         } TSCR_b;
16837     };
16838 } R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
16839 
16840 /* =========================================================================================================================== */
16841 /* ================                                         R_USB_FS0                                         ================ */
16842 /* =========================================================================================================================== */
16843 
16844 /**
16845  * @brief USB 2.0 Module (R_USB_FS0)
16846  */
16847 
16848 typedef struct                         /*!< (@ 0x40250000) R_USB_FS0 Structure                                        */
16849 {
16850     union
16851     {
16852         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
16853 
16854         struct
16855         {
16856             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
16857             uint16_t             : 2;
16858             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
16859             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
16860             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
16861             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
16862             uint16_t             : 1;
16863             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
16864             uint16_t             : 1;
16865             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
16866             uint16_t             : 5;
16867         } SYSCFG_b;
16868     };
16869 
16870     union
16871     {
16872         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
16873 
16874         struct
16875         {
16876             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
16877                                         *   access cycles)                                                            */
16878             uint16_t : 12;
16879         } BUSWAIT_b;
16880     };
16881 
16882     union
16883     {
16884         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
16885 
16886         struct
16887         {
16888             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
16889             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
16890             uint16_t            : 2;
16891             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
16892                                         *   Selected.                                                                 */
16893             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
16894             uint16_t             : 7;
16895             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
16896                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
16897                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
16898                                         *   pin.                                                                      */
16899         } SYSSTS0_b;
16900     };
16901 
16902     union
16903     {
16904         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
16905 
16906         struct
16907         {
16908             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
16909             uint16_t              : 15;
16910         } PLLSTA_b;
16911     };
16912 
16913     union
16914     {
16915         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
16916 
16917         struct
16918         {
16919             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
16920             uint16_t               : 1;
16921             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
16922             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
16923             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
16924             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
16925             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
16926             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
16927             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
16928             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
16929                                          *   used when switching from device B to device A while in
16930                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
16931                                          *   control keeps the suspended state until the HNP processing
16932                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
16933                                          *   set.                                                                      */
16934             uint16_t : 4;
16935         } DVSTCTR0_b;
16936     };
16937     __IM uint16_t RESERVED;
16938 
16939     union
16940     {
16941         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
16942 
16943         struct
16944         {
16945             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
16946             uint16_t            : 12;
16947         } TESTMODE_b;
16948     };
16949     __IM uint16_t RESERVED1;
16950     __IM uint32_t RESERVED2;
16951 
16952     union
16953     {
16954         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
16955 
16956         struct
16957         {
16958             union
16959             {
16960                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
16961                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
16962             };
16963 
16964             union
16965             {
16966                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
16967 
16968                 struct
16969                 {
16970                     __IM uint8_t  RESERVED3;
16971                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
16972                 };
16973             };
16974         };
16975     };
16976 
16977     union
16978     {
16979         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
16980 
16981         struct
16982         {
16983             union
16984             {
16985                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
16986                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
16987             };
16988 
16989             union
16990             {
16991                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
16992 
16993                 struct
16994                 {
16995                     __IM uint8_t  RESERVED4;
16996                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
16997                 };
16998             };
16999         };
17000     };
17001 
17002     union
17003     {
17004         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
17005 
17006         struct
17007         {
17008             union
17009             {
17010                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
17011                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
17012             };
17013 
17014             union
17015             {
17016                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
17017 
17018                 struct
17019                 {
17020                     __IM uint8_t  RESERVED5;
17021                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
17022                 };
17023             };
17024         };
17025     };
17026 
17027     union
17028     {
17029         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
17030 
17031         struct
17032         {
17033             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
17034             uint16_t               : 1;
17035             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
17036             uint16_t               : 2;
17037             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
17038             uint16_t               : 1;
17039             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
17040             uint16_t               : 2;
17041             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
17042             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
17043         } CFIFOSEL_b;
17044     };
17045 
17046     union
17047     {
17048         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
17049 
17050         struct
17051         {
17052             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
17053                                         *   data.                                                                     */
17054             uint16_t            : 1;
17055             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
17056             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
17057             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
17058         } CFIFOCTR_b;
17059     };
17060     __IM uint32_t RESERVED6;
17061 
17062     union
17063     {
17064         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
17065 
17066         struct
17067         {
17068             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
17069             uint16_t               : 4;
17070             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
17071             uint16_t               : 1;
17072             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
17073             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
17074             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
17075                                          *   Pipe Data is Read                                                         */
17076             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
17077             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
17078         } D0FIFOSEL_b;
17079     };
17080 
17081     union
17082     {
17083         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
17084 
17085         struct
17086         {
17087             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
17088                                         *   data.                                                                     */
17089             uint16_t            : 1;
17090             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
17091             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
17092             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
17093         } D0FIFOCTR_b;
17094     };
17095 
17096     union
17097     {
17098         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
17099 
17100         struct
17101         {
17102             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
17103             uint16_t               : 4;
17104             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
17105             uint16_t               : 1;
17106             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
17107             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
17108             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
17109                                          *   Pipe Data is Read                                                         */
17110             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
17111             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
17112         } D1FIFOSEL_b;
17113     };
17114 
17115     union
17116     {
17117         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
17118 
17119         struct
17120         {
17121             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
17122                                         *   data.                                                                     */
17123             uint16_t            : 1;
17124             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
17125             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
17126             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
17127         } D1FIFOCTR_b;
17128     };
17129 
17130     union
17131     {
17132         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
17133 
17134         struct
17135         {
17136             uint16_t             : 8;
17137             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
17138             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
17139             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
17140             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
17141             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
17142             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
17143             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
17144             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
17145         } INTENB0_b;
17146     };
17147 
17148     union
17149     {
17150         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
17151 
17152         struct
17153         {
17154             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
17155             uint16_t                  : 3;
17156             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
17157             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
17158             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
17159             uint16_t                  : 4;
17160             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
17161             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
17162             uint16_t                  : 1;
17163             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
17164             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
17165         } INTENB1_b;
17166     };
17167     __IM uint16_t RESERVED7;
17168 
17169     union
17170     {
17171         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
17172 
17173         struct
17174         {
17175             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
17176             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
17177             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
17178             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
17179             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
17180             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
17181             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
17182             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
17183             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
17184             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
17185             uint16_t                  : 6;
17186         } BRDYENB_b;
17187     };
17188 
17189     union
17190     {
17191         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
17192 
17193         struct
17194         {
17195             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
17196             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
17197             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
17198             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
17199             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
17200             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
17201             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
17202             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
17203             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
17204             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
17205             uint16_t                  : 6;
17206         } NRDYENB_b;
17207     };
17208 
17209     union
17210     {
17211         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
17212 
17213         struct
17214         {
17215             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
17216             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
17217             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
17218             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
17219             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
17220             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
17221             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
17222             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
17223             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
17224             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
17225             uint16_t                  : 6;
17226         } BEMPENB_b;
17227     };
17228 
17229     union
17230     {
17231         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
17232 
17233         struct
17234         {
17235             uint16_t                : 4;
17236             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
17237             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
17238             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
17239             uint16_t                : 1;
17240             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
17241             uint16_t                : 7;
17242         } SOFCFG_b;
17243     };
17244 
17245     union
17246     {
17247         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
17248 
17249         struct
17250         {
17251             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
17252             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
17253             uint16_t                : 1;
17254             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
17255             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
17256             uint16_t                : 2;
17257             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
17258             uint16_t                : 1;
17259             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
17260             uint16_t                : 3;
17261             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
17262         } PHYSET_b;
17263     };
17264 
17265     union
17266     {
17267         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
17268 
17269         struct
17270         {
17271             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
17272             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
17273             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
17274             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
17275             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
17276             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
17277             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
17278             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
17279             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
17280             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
17281             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
17282             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
17283         } INTSTS0_b;
17284     };
17285 
17286     union
17287     {
17288         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
17289 
17290         struct
17291         {
17292             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
17293             uint16_t                 : 3;
17294             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
17295             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
17296             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
17297             uint16_t                 : 1;
17298             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
17299             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
17300             uint16_t                 : 1;
17301             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
17302             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
17303             uint16_t                 : 1;
17304             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
17305             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
17306         } INTSTS1_b;
17307     };
17308     __IM uint16_t RESERVED8;
17309 
17310     union
17311     {
17312         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
17313 
17314         struct
17315         {
17316             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
17317             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
17318             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
17319             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
17320             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
17321             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
17322             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
17323             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
17324             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
17325             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
17326             uint16_t                 : 6;
17327         } BRDYSTS_b;
17328     };
17329 
17330     union
17331     {
17332         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
17333 
17334         struct
17335         {
17336             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
17337             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
17338             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
17339             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
17340             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
17341             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
17342             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
17343             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
17344             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
17345             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
17346             uint16_t                 : 6;
17347         } NRDYSTS_b;
17348     };
17349 
17350     union
17351     {
17352         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
17353 
17354         struct
17355         {
17356             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
17357             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
17358             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
17359             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
17360             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
17361             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
17362             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
17363             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
17364             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
17365             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
17366             uint16_t                 : 6;
17367         } BEMPSTS_b;
17368     };
17369 
17370     union
17371     {
17372         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
17373 
17374         struct
17375         {
17376             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
17377             uint16_t            : 3;
17378             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
17379             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
17380         } FRMNUM_b;
17381     };
17382 
17383     union
17384     {
17385         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
17386 
17387         struct
17388         {
17389             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
17390             uint16_t             : 12;
17391             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
17392         } UFRMNUM_b;
17393     };
17394 
17395     union
17396     {
17397         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
17398 
17399         struct
17400         {
17401             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
17402                                            *   the USB address assigned by the host when the USBHS processed
17403                                            *   the SET_ADDRESS request successfully.                                     */
17404             uint16_t                 : 1;
17405             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
17406             uint16_t                 : 5;
17407         } USBADDR_b;
17408     };
17409     __IM uint16_t RESERVED9;
17410 
17411     union
17412     {
17413         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
17414 
17415         struct
17416         {
17417             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
17418                                                *   value.                                                                    */
17419             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
17420         } USBREQ_b;
17421     };
17422 
17423     union
17424     {
17425         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
17426 
17427         struct
17428         {
17429             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
17430         } USBVAL_b;
17431     };
17432 
17433     union
17434     {
17435         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
17436 
17437         struct
17438         {
17439             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
17440         } USBINDX_b;
17441     };
17442 
17443     union
17444     {
17445         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
17446 
17447         struct
17448         {
17449             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
17450         } USBLENG_b;
17451     };
17452 
17453     union
17454     {
17455         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
17456 
17457         struct
17458         {
17459             uint16_t              : 4;
17460             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
17461             uint16_t              : 2;
17462             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
17463             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
17464             uint16_t              : 7;
17465         } DCPCFG_b;
17466     };
17467 
17468     union
17469     {
17470         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
17471 
17472         struct
17473         {
17474             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
17475                                         *   of data (maximum packet size) in payloads for the DCP.                    */
17476             uint16_t              : 5;
17477             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
17478         } DCPMAXP_b;
17479     };
17480 
17481     union
17482     {
17483         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
17484 
17485         struct
17486         {
17487             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
17488             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
17489             uint16_t                : 2;
17490             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
17491             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
17492             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
17493             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
17494             uint16_t                : 2;
17495             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
17496             uint16_t                : 2;
17497             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
17498             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
17499         } DCPCTR_b;
17500     };
17501     __IM uint16_t RESERVED10;
17502 
17503     union
17504     {
17505         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
17506 
17507         struct
17508         {
17509             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
17510             uint16_t               : 12;
17511         } PIPESEL_b;
17512     };
17513     __IM uint16_t RESERVED11;
17514 
17515     union
17516     {
17517         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
17518 
17519         struct
17520         {
17521             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
17522                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
17523             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
17524             uint16_t              : 2;
17525             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
17526             uint16_t              : 1;
17527             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
17528             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
17529             uint16_t              : 3;
17530             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
17531         } PIPECFG_b;
17532     };
17533     __IM uint16_t RESERVED12;
17534 
17535     union
17536     {
17537         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
17538 
17539         struct
17540         {
17541             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
17542                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
17543                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
17544                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
17545                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
17546             uint16_t              : 3;
17547             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
17548         } PIPEMAXP_b;
17549     };
17550 
17551     union
17552     {
17553         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
17554 
17555         struct
17556         {
17557             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
17558                                         *   error detection timing for the selected pipe in terms of
17559                                         *   frames, which is expressed as nth power of 2.                             */
17560             uint16_t            : 9;
17561             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
17562             uint16_t            : 3;
17563         } PIPEPERI_b;
17564     };
17565 
17566     union
17567     {
17568         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
17569 
17570         struct
17571         {
17572             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
17573             uint16_t              : 3;
17574             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
17575             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
17576             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
17577             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
17578             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
17579             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
17580             uint16_t              : 1;
17581             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
17582                                         *   Split Transaction of the relevant pipe                                    */
17583             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
17584                                         *   the CSSTS bit of the relevant pipe                                        */
17585             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
17586             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
17587         } PIPE_CTR_b[9];
17588     };
17589     __IM uint16_t                RESERVED13;
17590     __IM uint32_t                RESERVED14[3];
17591     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
17592     __IM uint32_t                RESERVED15[3];
17593 
17594     union
17595     {
17596         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
17597 
17598         struct
17599         {
17600             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
17601             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
17602             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
17603             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
17604             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
17605             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
17606             uint16_t                  : 1;
17607             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
17608             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
17609             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
17610             uint16_t                  : 6;
17611         } USBBCCTRL0_b;
17612     };
17613     __IM uint16_t RESERVED16;
17614     __IM uint32_t RESERVED17[4];
17615 
17616     union
17617     {
17618         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
17619 
17620         struct
17621         {
17622             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
17623             uint16_t               : 15;
17624         } UCKSEL_b;
17625     };
17626     __IM uint16_t RESERVED18;
17627     __IM uint32_t RESERVED19;
17628 
17629     union
17630     {
17631         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
17632 
17633         struct
17634         {
17635             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
17636             uint16_t               : 6;
17637             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
17638             uint16_t               : 8;
17639         } USBMC_b;
17640     };
17641     __IM uint16_t RESERVED20;
17642 
17643     union
17644     {
17645         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
17646 
17647         struct
17648         {
17649             uint16_t               : 6;
17650             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
17651             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
17652             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
17653             uint16_t               : 1;
17654         } DEVADD_b[10];
17655     };
17656     __IM uint32_t RESERVED21[3];
17657 
17658     union
17659     {
17660         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
17661 
17662         struct
17663         {
17664             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
17665             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
17666             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
17667             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
17668             uint32_t               : 28;
17669         } PHYSLEW_b;
17670     };
17671     __IM uint32_t RESERVED22[3];
17672 
17673     union
17674     {
17675         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
17676 
17677         struct
17678         {
17679             uint16_t             : 7;
17680             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
17681             uint16_t             : 8;
17682         } LPCTRL_b;
17683     };
17684 
17685     union
17686     {
17687         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
17688 
17689         struct
17690         {
17691             uint16_t                : 14;
17692             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
17693             uint16_t                : 1;
17694         } LPSTS_b;
17695     };
17696     __IM uint32_t RESERVED23[15];
17697 
17698     union
17699     {
17700         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
17701 
17702         struct
17703         {
17704             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
17705             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
17706             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
17707             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
17708             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
17709             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
17710             uint16_t                : 2;
17711             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
17712             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
17713             uint16_t                : 6;
17714         } BCCTRL_b;
17715     };
17716     __IM uint16_t RESERVED24;
17717 
17718     union
17719     {
17720         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
17721 
17722         struct
17723         {
17724             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
17725             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
17726             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
17727                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
17728             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
17729                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
17730             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
17731                                           *   value used for L1NEGOMD.The format is the same as the HIRD
17732                                           *   field in HL1CTRL.                                                         */
17733             uint16_t               : 2;
17734             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
17735             uint16_t               : 1;
17736         } PL1CTRL1_b;
17737     };
17738 
17739     union
17740     {
17741         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
17742 
17743         struct
17744         {
17745             uint16_t               : 8;
17746             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
17747             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
17748             uint16_t               : 3;
17749         } PL1CTRL2_b;
17750     };
17751 
17752     union
17753     {
17754         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
17755 
17756         struct
17757         {
17758             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
17759             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
17760             uint16_t                : 13;
17761         } HL1CTRL1_b;
17762     };
17763 
17764     union
17765     {
17766         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
17767 
17768         struct
17769         {
17770             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
17771                                         *   be set in the ADDR field of LPM token.                                    */
17772             uint16_t             : 4;
17773             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
17774             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
17775                                         *   value to be set in the RWE field of LPM token.                            */
17776             uint16_t            : 2;
17777             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
17778                                         *   period at the time of L1 Resume.                                          */
17779         } HL1CTRL2_b;
17780     };
17781     __IM uint32_t RESERVED25[5];
17782 
17783     union
17784     {
17785         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
17786                                         *                  Register                                                   */
17787 
17788         struct
17789         {
17790             uint32_t              : 20;
17791             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
17792                                          *   HS side of USB port.                                                      */
17793             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
17794                                          *   HS side of USB port.                                                      */
17795             uint32_t               : 1;
17796             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
17797                                          *   of USB port.                                                              */
17798             uint32_t : 8;
17799         } DPUSR0R_b;
17800     };
17801 
17802     union
17803     {
17804         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
17805 
17806         struct
17807         {
17808             uint32_t                : 4;
17809             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
17810             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
17811             uint32_t                : 1;
17812             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
17813             uint32_t                : 12;
17814             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
17815             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
17816             uint32_t                : 1;
17817             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
17818             uint32_t                : 8;
17819         } DPUSR1R_b;
17820     };
17821 
17822     union
17823     {
17824         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
17825 
17826         struct
17827         {
17828             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
17829             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
17830             uint16_t            : 2;
17831             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
17832                                         *   port.                                                                     */
17833             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
17834                                         *   port.                                                                     */
17835             uint16_t              : 2;
17836             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
17837             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
17838             uint16_t              : 6;
17839         } DPUSR2R_b;
17840     };
17841 
17842     union
17843     {
17844         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
17845 
17846         struct
17847         {
17848             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
17849             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
17850             uint16_t                : 14;
17851         } DPUSRCR_b;
17852     };
17853     __IM uint32_t RESERVED26[165];
17854 
17855     union
17856     {
17857         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
17858                                          *                  Monitor Register                                           */
17859 
17860         struct
17861         {
17862             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
17863             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
17864             uint32_t               : 1;
17865             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
17866             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
17867             uint32_t               : 11;
17868             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
17869             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
17870             uint32_t               : 2;
17871             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
17872                                          *   of the USB.                                                               */
17873             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
17874                                          *   of the USB.                                                               */
17875             uint32_t              : 1;
17876             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
17877                                          *   USB.                                                                      */
17878             uint32_t : 8;
17879         } DPUSR0R_FS_b;
17880     };
17881 
17882     union
17883     {
17884         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
17885                                            *                  Register                                                   */
17886 
17887         struct
17888         {
17889             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
17890             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
17891             uint32_t                 : 2;
17892             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
17893             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
17894             uint32_t                 : 1;
17895             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
17896             uint32_t                 : 8;
17897             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
17898             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
17899             uint32_t                 : 2;
17900             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
17901             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
17902             uint32_t                 : 1;
17903             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
17904             uint32_t                 : 8;
17905         } DPUSR1R_FS_b;
17906     };
17907 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
17908 
17909 /* =========================================================================================================================== */
17910 /* ================                                           R_WDT                                           ================ */
17911 /* =========================================================================================================================== */
17912 
17913 /**
17914  * @brief Watchdog Timer (R_WDT)
17915  */
17916 
17917 typedef struct                         /*!< (@ 0x40202600) R_WDT Structure                                            */
17918 {
17919     union
17920     {
17921         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
17922 
17923         struct
17924         {
17925             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
17926                                         *   of the WDT.                                                               */
17927         } WDTRR_b;
17928     };
17929     __IM uint8_t RESERVED;
17930 
17931     union
17932     {
17933         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
17934 
17935         struct
17936         {
17937             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
17938             uint16_t            : 2;
17939             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
17940             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
17941             uint16_t            : 2;
17942             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
17943             uint16_t            : 2;
17944         } WDTCR_b;
17945     };
17946 
17947     union
17948     {
17949         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
17950 
17951         struct
17952         {
17953             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
17954             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
17955             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
17956         } WDTSR_b;
17957     };
17958 
17959     union
17960     {
17961         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
17962 
17963         struct
17964         {
17965             uint8_t               : 7;
17966             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
17967         } WDTRCR_b;
17968     };
17969     __IM uint8_t RESERVED1;
17970 
17971     union
17972     {
17973         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
17974 
17975         struct
17976         {
17977             uint8_t              : 7;
17978             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
17979         } WDTCSTPR_b;
17980     };
17981     __IM uint8_t  RESERVED2;
17982     __IM uint16_t RESERVED3;
17983 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
17984 
17985 /* =========================================================================================================================== */
17986 /* ================                                           R_TZF                                           ================ */
17987 /* =========================================================================================================================== */
17988 
17989 /**
17990  * @brief TrustZone Filter (R_TZF)
17991  */
17992 
17993 typedef struct                         /*!< (@ 0x40004000) R_TZF Structure                                            */
17994 {
17995     __IM uint16_t RESERVED[8];
17996 
17997     union
17998     {
17999         __IOM uint16_t TZFOAD;         /*!< (@ 0x00000010) TrustZone Filter Operation After Detection register        */
18000 
18001         struct
18002         {
18003             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
18004             uint16_t           : 7;
18005             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code                                                          */
18006         } TZFOAD_b;
18007     };
18008     __IM uint16_t RESERVED1;
18009 
18010     union
18011     {
18012         __IOM uint16_t TZFPT;           /*!< (@ 0x00000014) TrustZone Filter Protect register                          */
18013 
18014         struct
18015         {
18016             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
18017             uint16_t               : 7;
18018             __OM uint16_t KEY      : 8; /*!< [15..8] Key Code                                                          */
18019         } TZFPT_b;
18020     };
18021 } R_TZF_Type;                           /*!< Size = 22 (0x16)                                                          */
18022 
18023 /* =========================================================================================================================== */
18024 /* ================                                          R_CPSCU                                          ================ */
18025 /* =========================================================================================================================== */
18026 
18027 /**
18028  * @brief CPU System Security Control Unit (R_CPSCU)
18029  */
18030 
18031 typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
18032 {
18033     union
18034     {
18035         __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
18036 
18037         struct
18038         {
18039             __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
18040             __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
18041             __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
18042             uint32_t                : 29;
18043         } CSAR_b;
18044     };
18045     __IM uint32_t RESERVED[3];
18046 
18047     union
18048     {
18049         __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
18050 
18051         struct
18052         {
18053             __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
18054             __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
18055                                          *   2                                                                         */
18056             __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
18057             uint32_t               : 29;
18058         } SRAMSAR_b;
18059     };
18060 
18061     union
18062     {
18063         __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
18064 
18065         struct
18066         {
18067             __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
18068             uint32_t               : 28;
18069         } STBRAMSAR_b;
18070     };
18071     __IM uint32_t RESERVED1[6];
18072 
18073     union
18074     {
18075         __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
18076 
18077         struct
18078         {
18079             __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
18080             uint32_t               : 31;
18081         } DTCSAR_b;
18082     };
18083 
18084     union
18085     {
18086         __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
18087 
18088         struct
18089         {
18090             __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
18091             uint32_t               : 31;
18092         } DMACSAR_b;
18093     };
18094     __IM uint32_t RESERVED2[2];
18095 
18096     union
18097     {
18098         __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
18099 
18100         struct
18101         {
18102             __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
18103             uint32_t                : 16;
18104         } ICUSARA_b;
18105     };
18106 
18107     union
18108     {
18109         __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
18110 
18111         struct
18112         {
18113             __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
18114             uint32_t             : 31;
18115         } ICUSARB_b;
18116     };
18117 
18118     union
18119     {
18120         __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
18121 
18122         struct
18123         {
18124             __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
18125             uint32_t               : 24;
18126         } ICUSARC_b;
18127     };
18128 
18129     union
18130     {
18131         __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
18132 
18133         struct
18134         {
18135             __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
18136             uint32_t                : 31;
18137         } ICUSARD_b;
18138     };
18139 
18140     union
18141     {
18142         __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
18143 
18144         struct
18145         {
18146             uint32_t                   : 16;
18147             __IOM uint32_t SAIWDTWUP   : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
18148             uint32_t                   : 1;
18149             __IOM uint32_t SALVD1WUP   : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
18150             __IOM uint32_t SALVD2WUP   : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
18151             __IOM uint32_t SAVBATTWUP  : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
18152             uint32_t                   : 3;
18153             __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
18154             __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
18155             uint32_t                   : 1;
18156             __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
18157             __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
18158             __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
18159             __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
18160             __IOM uint32_t SAIIC0WUP   : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
18161         } ICUSARE_b;
18162     };
18163 
18164     union
18165     {
18166         __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
18167 
18168         struct
18169         {
18170             __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
18171             __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
18172             __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
18173             __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
18174             uint32_t                    : 4;
18175             __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
18176             __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
18177             __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
18178             __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
18179             __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
18180             __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
18181             __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
18182             uint32_t                    : 17;
18183         } ICUSARF_b;
18184     };
18185     __IM uint32_t RESERVED3[6];
18186 
18187     union
18188     {
18189         __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
18190 
18191         struct
18192         {
18193             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
18194         } ICUSARG_b;
18195     };
18196 
18197     union
18198     {
18199         __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
18200 
18201         struct
18202         {
18203             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
18204         } ICUSARH_b;
18205     };
18206 
18207     union
18208     {
18209         __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
18210 
18211         struct
18212         {
18213             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
18214         } ICUSARI_b;
18215     };
18216     __IM uint32_t RESERVED4[33];
18217 
18218     union
18219     {
18220         __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
18221 
18222         struct
18223         {
18224             __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
18225             uint32_t              : 31;
18226         } BUSSARA_b;
18227     };
18228 
18229     union
18230     {
18231         __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
18232 
18233         struct
18234         {
18235             __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
18236             uint32_t              : 31;
18237         } BUSSARB_b;
18238     };
18239     __IM uint32_t RESERVED5[10];
18240 
18241     union
18242     {
18243         __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
18244                                           *                  Register A                                                 */
18245 
18246         struct
18247         {
18248             __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
18249             uint32_t                : 24;
18250         } MMPUSARA_b;
18251     };
18252 
18253     union
18254     {
18255         __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
18256                                           *                  Register B                                                 */
18257 
18258         struct
18259         {
18260             __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
18261             uint32_t                : 31;
18262         } MMPUSARB_b;
18263     };
18264     __IM uint32_t RESERVED6[26];
18265 
18266     union
18267     {
18268         __IOM uint32_t DMACCHSAR;          /*!< (@ 0x000001A0) DMA channel Security Attribution Register                  */
18269 
18270         struct
18271         {
18272             __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
18273                                             *   channel                                                                   */
18274             uint32_t : 24;
18275         } DMACCHSAR_b;
18276     };
18277     __IM uint32_t RESERVED7[3];
18278 
18279     union
18280     {
18281         __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
18282 
18283         struct
18284         {
18285             __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
18286             uint32_t               : 31;
18287         } CPUDSAR_b;
18288     };
18289     __IM uint32_t RESERVED8[147];
18290 
18291     union
18292     {
18293         __IOM uint32_t SRAMSABAR0;     /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register
18294                                         *                  0                                                          */
18295 
18296         struct
18297         {
18298             uint32_t                 : 13;
18299             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
18300                                            *   address of non-secure region).                                            */
18301             uint32_t : 11;
18302         } SRAMSABAR0_b;
18303     };
18304 
18305     union
18306     {
18307         __IOM uint32_t SRAMSABAR1;     /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register
18308                                         *                  1                                                          */
18309 
18310         struct
18311         {
18312             uint32_t                 : 13;
18313             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
18314                                            *   address of non-secure region).                                            */
18315             uint32_t : 11;
18316         } SRAMSABAR1_b;
18317     };
18318     __IM uint32_t RESERVED9[126];
18319 
18320     union
18321     {
18322         __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */
18323 
18324         struct
18325         {
18326             __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
18327                                         *   and ELCSRn                                                                */
18328             uint32_t : 31;
18329         } TEVTRCR_b;
18330     };
18331 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
18332 
18333 /* =========================================================================================================================== */
18334 /* ================                                          R_DOC_B                                          ================ */
18335 /* =========================================================================================================================== */
18336 
18337 /**
18338  * @brief Data Operation Circuit (R_DOC_B)
18339  */
18340 
18341 typedef struct                         /*!< (@ 0x40311000) R_DOC_B Structure                                          */
18342 {
18343     union
18344     {
18345         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
18346 
18347         struct
18348         {
18349             __IOM uint8_t OMS   : 2;   /*!< [1..0] Operating Mode Select                                              */
18350             uint8_t             : 1;
18351             __IOM uint8_t DOBW  : 1;   /*!< [3..3] Data Operation Bit Width Select                                    */
18352             __IOM uint8_t DCSEL : 3;   /*!< [6..4] Detection Condition Select                                         */
18353             uint8_t             : 1;
18354         } DOCR_b;
18355     };
18356     __IM uint8_t  RESERVED;
18357     __IM uint16_t RESERVED1;
18358 
18359     union
18360     {
18361         __IOM uint8_t DOSR;            /*!< (@ 0x00000004) DOC Flag Status Register                                   */
18362 
18363         struct
18364         {
18365             __IM uint8_t DOPCF : 1;    /*!< [0..0] Data Operation Circuit Flag                                        */
18366             uint8_t            : 7;
18367         } DOSR_b;
18368     };
18369     __IM uint8_t  RESERVED2;
18370     __IM uint16_t RESERVED3;
18371 
18372     union
18373     {
18374         __IOM uint8_t DOSCR;           /*!< (@ 0x00000008) DOC Flag Status Clear Register                             */
18375 
18376         struct
18377         {
18378             __OM uint8_t DOPCFCL : 1;  /*!< [0..0] DOPCF Clear                                                        */
18379             uint8_t              : 7;
18380         } DOSCR_b;
18381     };
18382     __IM uint8_t   RESERVED4;
18383     __IM uint16_t  RESERVED5;
18384     __IOM uint32_t DODIR;              /*!< (@ 0x0000000C) DOC Data Input Register                                    */
18385     __IOM uint32_t DODSR0;             /*!< (@ 0x00000010) DOC Data Setting Register 0                                */
18386     __IOM uint32_t DODSR1;             /*!< (@ 0x00000014) DOC Data Setting Register 1                                */
18387 } R_DOC_B_Type;                        /*!< Size = 24 (0x18)                                                          */
18388 
18389 /* =========================================================================================================================== */
18390 /* ================                                         R_SCI_B0                                          ================ */
18391 /* =========================================================================================================================== */
18392 
18393 /**
18394  * @brief Serial Communication Interface 0 (R_SCI_B0)
18395  */
18396 
18397 typedef struct                         /*!< (@ 0x40358000) R_SCI_B0 Structure                                         */
18398 {
18399     union
18400     {
18401         union
18402         {
18403             __IM uint32_t RDR;          /*!< (@ 0x00000000) Receive Data Register                                      */
18404 
18405             struct
18406             {
18407                 __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data                                                */
18408                 __IM uint32_t MPB  : 1; /*!< [9..9] Multi-processor flag                                               */
18409                 __IM uint32_t DR   : 1; /*!< [10..10] Receive data ready flag                                          */
18410                 __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag                                           */
18411                 __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag                                          */
18412                 uint32_t           : 11;
18413                 __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag                                               */
18414                 uint32_t           : 2;
18415                 __IM uint32_t PER  : 1; /*!< [27..27] Parity error flag                                                */
18416                 __IM uint32_t FER  : 1; /*!< [28..28] Framing error flag                                               */
18417                 uint32_t           : 3;
18418             } RDR_b;
18419         };
18420 
18421         union
18422         {
18423             __IOM uint8_t RDR_BY;       /*!< (@ 0x00000000) Receive Data Register (byte access)                        */
18424 
18425             struct
18426             {
18427                 __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data                                                */
18428             } RDR_BY_b;
18429         };
18430     };
18431 
18432     union
18433     {
18434         union
18435         {
18436             __IOM uint32_t TDR;           /*!< (@ 0x00000004) Transmit Data Register                                     */
18437 
18438             struct
18439             {
18440                 __IOM uint32_t TDAT  : 9; /*!< [8..0] Serial transmit data                                               */
18441                 __IOM uint32_t MPBT  : 1; /*!< [9..9] Multi-processor transfer bit flag                                  */
18442                 uint32_t             : 2;
18443                 __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data                                               */
18444                 uint32_t             : 19;
18445             } TDR_b;
18446         };
18447 
18448         union
18449         {
18450             __IOM uint8_t TDR_BY;       /*!< (@ 0x00000004) Transmit Data Register (byte access)                       */
18451 
18452             struct
18453             {
18454                 __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data                                               */
18455             } TDR_BY_b;
18456         };
18457     };
18458 
18459     union
18460     {
18461         __IOM uint32_t CCR0;           /*!< (@ 0x00000008) Common Control Register 0                                  */
18462 
18463         struct
18464         {
18465             __IOM uint32_t RE    : 1;  /*!< [0..0] Receive Enable                                                     */
18466             uint32_t             : 3;
18467             __IOM uint32_t TE    : 1;  /*!< [4..4] Transmit Enable                                                    */
18468             uint32_t             : 3;
18469             __IOM uint32_t MPIE  : 1;  /*!< [8..8] Multi-Processor Interrupt Enable                                   */
18470             __IOM uint32_t DCME  : 1;  /*!< [9..9] Data Compare Match Enable                                          */
18471             __IOM uint32_t IDSEL : 1;  /*!< [10..10] ID frame select                                                  */
18472             uint32_t             : 5;
18473             __IOM uint32_t RIE   : 1;  /*!< [16..16] Receive Interrupt Enable                                         */
18474             uint32_t             : 3;
18475             __IOM uint32_t TIE   : 1;  /*!< [20..20] Transmit Interrupt Enable                                        */
18476             __IOM uint32_t TEIE  : 1;  /*!< [21..21] Transmit End Interrupt Enable                                    */
18477             uint32_t             : 2;
18478             __IOM uint32_t SSE   : 1;  /*!< [24..24] SSn Pin Function Enable                                          */
18479             uint32_t             : 7;
18480         } CCR0_b;
18481     };
18482 
18483     union
18484     {
18485         __IOM uint32_t CCR1;           /*!< (@ 0x0000000C) Common Control Register 1                                  */
18486 
18487         struct
18488         {
18489             __IOM uint32_t CTSE   : 1; /*!< [0..0] CTS Enable                                                         */
18490             __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable                                            */
18491             uint32_t              : 2;
18492             __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select                                      */
18493             __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O                                              */
18494             uint32_t              : 2;
18495             __IOM uint32_t PE     : 1; /*!< [8..8] Parity Enable                                                      */
18496             __IOM uint32_t PM     : 1; /*!< [9..9] Parity Mode                                                        */
18497             uint32_t              : 2;
18498             __IOM uint32_t TINV   : 1; /*!< [12..12] TXD invert                                                       */
18499             __IOM uint32_t RINV   : 1; /*!< [13..13] RXD invert                                                       */
18500             uint32_t              : 2;
18501             __IOM uint32_t SPLP   : 1; /*!< [16..16] Loopback Control                                                 */
18502             uint32_t              : 3;
18503             __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select                                 */
18504             uint32_t              : 3;
18505             __IOM uint32_t NFCS   : 3; /*!< [26..24] Noise Filter Clock Select                                        */
18506             uint32_t              : 1;
18507             __IOM uint32_t NFEN   : 1; /*!< [28..28] Digital Noise Filter Function Enable                             */
18508             uint32_t              : 3;
18509         } CCR1_b;
18510     };
18511 
18512     union
18513     {
18514         __IOM uint32_t CCR2;           /*!< (@ 0x00000010) Common Control Register 2                                  */
18515 
18516         struct
18517         {
18518             __IOM uint32_t BCP   : 3;  /*!< [2..0] Base Clock Pulse                                                   */
18519             uint32_t             : 1;
18520             __IOM uint32_t BGDM  : 1;  /*!< [4..4] Baud Rate Generator Double-Speed Mode Select                       */
18521             __IOM uint32_t ABCS  : 1;  /*!< [5..5] Asynchronous Mode Base Clock Select                                */
18522             __IOM uint32_t ABCSE : 1;  /*!< [6..6] Asynchronous Mode Extended Base Clock Select                       */
18523             uint32_t             : 1;
18524             __IOM uint32_t BRR   : 8;  /*!< [15..8] Bit rate setting                                                  */
18525             __IOM uint32_t BRME  : 1;  /*!< [16..16] Bit Modulation Enable                                            */
18526             uint32_t             : 3;
18527             __IOM uint32_t CKS   : 2;  /*!< [21..20] Clock Select                                                     */
18528             uint32_t             : 2;
18529             __IOM uint32_t MDDR  : 8;  /*!< [31..24] Modulation Duty Setting                                          */
18530         } CCR2_b;
18531     };
18532 
18533     union
18534     {
18535         __IOM uint32_t CCR3;            /*!< (@ 0x00000014) Common Control Register 3                                  */
18536 
18537         struct
18538         {
18539             __IOM uint32_t CPHA    : 1; /*!< [0..0] Clock Phase Select                                                 */
18540             __IOM uint32_t CPOL    : 1; /*!< [1..1] Clock Polarity Select                                              */
18541             uint32_t               : 5;
18542             __IOM uint32_t BPEN    : 1; /*!< [7..7] Synchronizer bypass enable                                         */
18543             __IOM uint32_t CHR     : 2; /*!< [9..8] Character Length                                                   */
18544             uint32_t               : 2;
18545             __IOM uint32_t LSBF    : 1; /*!< [12..12] LSB First select                                                 */
18546             __IOM uint32_t SINV    : 1; /*!< [13..13] Transmitted/Received Data Invert                                 */
18547             __IOM uint32_t STP     : 1; /*!< [14..14] Stop Bit Length                                                  */
18548             __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select                     */
18549             __IOM uint32_t MOD     : 3; /*!< [18..16] Communication mode select                                        */
18550             __IOM uint32_t MP      : 1; /*!< [19..19] Multi-Processor Mode                                             */
18551             __IOM uint32_t FM      : 1; /*!< [20..20] FIFO Mode select                                                 */
18552             __IOM uint32_t DEN     : 1; /*!< [21..21] Driver enable                                                    */
18553             uint32_t               : 2;
18554             __IOM uint32_t CKE     : 2; /*!< [25..24] Clock enable                                                     */
18555             uint32_t               : 2;
18556             __IOM uint32_t GM      : 1; /*!< [28..28] GSM Mode                                                         */
18557             __IOM uint32_t BLK     : 1; /*!< [29..29] Block Transfer Mode                                              */
18558             uint32_t               : 2;
18559         } CCR3_b;
18560     };
18561 
18562     union
18563     {
18564         __IOM uint32_t CCR4;           /*!< (@ 0x00000018) Common Control Register 4                                  */
18565 
18566         struct
18567         {
18568             __IOM uint32_t CMPD   : 9; /*!< [8..0] Compare Match Data                                                 */
18569             uint32_t              : 7;
18570             __IOM uint32_t ASEN   : 1; /*!< [16..16] Adjust receive sampling timing enable                            */
18571             __IOM uint32_t ATEN   : 1; /*!< [17..17] Adjust transmit timing enable                                    */
18572             uint32_t              : 1;
18573             __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit.                              */
18574             uint32_t              : 4;
18575             __IOM uint32_t AST    : 3; /*!< [26..24] Adjustment value for receive Sampling Timing                     */
18576             __IOM uint32_t AJD    : 1; /*!< [27..27] Adjustment Direction for receive sampling timing                 */
18577             __IOM uint32_t ATT    : 3; /*!< [30..28] Adjustment value for Transmit timing                             */
18578             __IOM uint32_t AET    : 1; /*!< [31..31] Adjustment edge for transmit timing                              */
18579         } CCR4_b;
18580     };
18581 
18582     union
18583     {
18584         __IM uint8_t CESR;             /*!< (@ 0x0000001C) Communication Enable Status Register                       */
18585 
18586         struct
18587         {
18588             __IM uint8_t RIST : 1;     /*!< [0..0] RE Internal status                                                 */
18589             uint8_t           : 3;
18590             __IM uint8_t TIST : 1;     /*!< [4..4] TE Internal status                                                 */
18591             uint8_t           : 3;
18592         } CESR_b;
18593     };
18594     __IM uint8_t  RESERVED;
18595     __IM uint16_t RESERVED1;
18596 
18597     union
18598     {
18599         __IOM uint32_t ICR;                /*!< (@ 0x00000020) Simple I2C Control Register                                */
18600 
18601         struct
18602         {
18603             __IOM uint32_t IICDL      : 5; /*!< [4..0] SDA Delay Output Select                                            */
18604             uint32_t                  : 3;
18605             __IOM uint32_t IICINTM    : 1; /*!< [8..8] IIC Interrupt Mode Select                                          */
18606             __IOM uint32_t IICCSC     : 1; /*!< [9..9] Clock Synchronization                                              */
18607             uint32_t                  : 3;
18608             __IOM uint32_t IICACKT    : 1; /*!< [13..13] ACK Transmission Data                                            */
18609             uint32_t                  : 2;
18610             __IOM uint32_t IICSTAREQ  : 1; /*!< [16..16] Start Condition Generation                                       */
18611             __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation                                     */
18612             __IOM uint32_t IICSTPREQ  : 1; /*!< [18..18] Stop Condition Generation                                        */
18613             uint32_t                  : 1;
18614             __IOM uint32_t IICSDAS    : 2; /*!< [21..20] SDA Output Select                                                */
18615             __IOM uint32_t IICSCLS    : 2; /*!< [23..22] SCL Output Select                                                */
18616             uint32_t                  : 8;
18617         } ICR_b;
18618     };
18619 
18620     union
18621     {
18622         __IOM uint32_t FCR;            /*!< (@ 0x00000024) FIFO Control Register                                      */
18623 
18624         struct
18625         {
18626             __IOM uint32_t DRES  : 1;  /*!< [0..0] Receive data ready error select bit                                */
18627             uint32_t             : 7;
18628             __IOM uint32_t TTRG  : 5;  /*!< [12..8] Transmit FIFO data trigger number                                 */
18629             uint32_t             : 2;
18630             __OM uint32_t  TFRST : 1;  /*!< [15..15] Transmit FIFO Data Register Reset                                */
18631             __IOM uint32_t RTRG  : 5;  /*!< [20..16] Receive FIFO data trigger number                                 */
18632             uint32_t             : 2;
18633             __OM uint32_t  RFRST : 1;  /*!< [23..23] Receive FIFO Data Register Reset                                 */
18634             __IOM uint32_t RSTRG : 5;  /*!< [28..24] RTS Output Active Trigger Number Select                          */
18635             uint32_t             : 3;
18636         } FCR_b;
18637     };
18638     __IM uint32_t RESERVED2;
18639 
18640     union
18641     {
18642         __IOM uint32_t MCR;            /*!< (@ 0x0000002C) Manchester Control Register                                */
18643 
18644         struct
18645         {
18646             __IOM uint32_t RMPOL  : 1; /*!< [0..0] Polarity of Received Manchester Code                               */
18647             __IOM uint32_t TMPOL  : 1; /*!< [1..1] Polarity of Transmit Manchester Code                               */
18648             __IOM uint32_t ERTEN  : 1; /*!< [2..2] Manchester Edge Retiming Enable                                    */
18649             uint32_t              : 1;
18650             __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting                                                 */
18651             __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select                                                        */
18652             __IOM uint32_t SBSEL  : 1; /*!< [6..6] Start Bit Select                                                   */
18653             uint32_t              : 1;
18654             __IOM uint32_t TPLEN  : 4; /*!< [11..8] Transmit preface length                                           */
18655             __IOM uint32_t TPPAT  : 2; /*!< [13..12] Transmit preface pattern                                         */
18656             uint32_t              : 2;
18657             __IOM uint32_t RPLEN  : 4; /*!< [19..16] Receive Preface Length                                           */
18658             __IOM uint32_t RPPAT  : 2; /*!< [21..20] Receive Preface Pattern                                          */
18659             uint32_t              : 2;
18660             __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable                                             */
18661             __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable                                        */
18662             __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable                                           */
18663             uint32_t              : 5;
18664         } MCR_b;
18665     };
18666 
18667     union
18668     {
18669         __IOM uint32_t DCR;            /*!< (@ 0x00000030) Driver Control Register                                    */
18670 
18671         struct
18672         {
18673             __IOM uint32_t DEPOL : 1;  /*!< [0..0] Driver effective polarity select                                   */
18674             uint32_t             : 7;
18675             __IOM uint32_t DEAST : 5;  /*!< [12..8] Driver Assertion Time                                             */
18676             uint32_t             : 3;
18677             __IOM uint32_t DENGT : 5;  /*!< [20..16] Driver negate time                                               */
18678             uint32_t             : 11;
18679         } DCR_b;
18680     };
18681 
18682     union
18683     {
18684         __IOM uint32_t XCR0;           /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0                        */
18685 
18686         struct
18687         {
18688             __IOM uint32_t TCSS  : 2;  /*!< [1..0] Timer count clock source selection                                 */
18689             uint32_t             : 6;
18690             __IOM uint32_t BFE   : 1;  /*!< [8..8] Break Field enable                                                 */
18691             __IOM uint32_t CF0RE : 1;  /*!< [9..9] Control Field 0 enable                                             */
18692             __IOM uint32_t CF1DS : 2;  /*!< [11..10] Control Field1 compare data select                               */
18693             __IOM uint32_t PIBE  : 1;  /*!< [12..12] Priority interrupt bit enable                                    */
18694             __IOM uint32_t PIBS  : 3;  /*!< [15..13] Priority interrupt bit select                                    */
18695             __IOM uint32_t BFOIE : 1;  /*!< [16..16] Break Field output completion interrupt enable                   */
18696             __IOM uint32_t BCDIE : 1;  /*!< [17..17] Bus conflict detection interrupt enable                          */
18697             uint32_t             : 2;
18698             __IOM uint32_t BFDIE : 1;  /*!< [20..20] Break Field detection interrupt enable                           */
18699             __IOM uint32_t COFIE : 1;  /*!< [21..21] Counter overflow interrupt enable                                */
18700             __IOM uint32_t AEDIE : 1;  /*!< [22..22] Active edge detection interrupt enable                           */
18701             uint32_t             : 1;
18702             __IOM uint32_t BCCS  : 2;  /*!< [25..24] Bus conflict detection clock selection                           */
18703             uint32_t             : 6;
18704         } XCR0_b;
18705     };
18706 
18707     union
18708     {
18709         __IOM uint32_t XCR1;           /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1                        */
18710 
18711         struct
18712         {
18713             __IOM uint32_t TCST  : 1;  /*!< [0..0] Break Field output timer count start trigger                       */
18714             uint32_t             : 3;
18715             __IOM uint32_t SDST  : 1;  /*!< [4..4] Start Frame detection enable                                       */
18716             __IOM uint32_t BMEN  : 1;  /*!< [5..5] Bit rate measurement enable                                        */
18717             uint32_t             : 2;
18718             __IOM uint32_t PCF1D : 8;  /*!< [15..8] Priority compare data for Control Field 1                         */
18719             __IOM uint32_t SCF1D : 8;  /*!< [23..16] Secondary compare data for Control Field 1                       */
18720             __IOM uint32_t CF1CE : 8;  /*!< [31..24] Control Field 1 compare bit enable                               */
18721         } XCR1_b;
18722     };
18723 
18724     union
18725     {
18726         __IOM uint32_t XCR2;           /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2                        */
18727 
18728         struct
18729         {
18730             __IOM uint32_t CF0D  : 8;  /*!< [7..0] Control Field 0compare data                                        */
18731             __IOM uint32_t CF0CE : 8;  /*!< [15..8] Control Field 0 compare bit enable                                */
18732             __IOM uint32_t BFLW  : 16; /*!< [31..16] Break Field length setting                                       */
18733         } XCR2_b;
18734     };
18735     __IM uint32_t RESERVED3[2];
18736 
18737     union
18738     {
18739         __IM uint32_t CSR;             /*!< (@ 0x00000048) Common Status Register                                     */
18740 
18741         struct
18742         {
18743             uint32_t             : 4;
18744             __IM uint32_t ERS    : 1;  /*!< [4..4] Error Signal Status Flag                                           */
18745             uint32_t             : 10;
18746             __IM uint32_t RXDMON : 1;  /*!< [15..15] Serial input data monitor bit                                    */
18747             __IM uint32_t DCMF   : 1;  /*!< [16..16] Data Compare Match Flag                                          */
18748             __IM uint32_t DPER   : 1;  /*!< [17..17] Data Compare Match Parity Error Flag                             */
18749             __IM uint32_t DFER   : 1;  /*!< [18..18] Data Compare Match Framing Error Flag                            */
18750             uint32_t             : 5;
18751             __IM uint32_t ORER   : 1;  /*!< [24..24] Overrun Error Flag                                               */
18752             uint32_t             : 1;
18753             __IM uint32_t MFF    : 1;  /*!< [26..26] Mode Fault Flag                                                  */
18754             __IM uint32_t PER    : 1;  /*!< [27..27] Parity Error Flag                                                */
18755             __IM uint32_t FER    : 1;  /*!< [28..28] Framing Error Flag                                               */
18756             __IM uint32_t TDRE   : 1;  /*!< [29..29] Transmit Data Empty Flag                                         */
18757             __IM uint32_t TEND   : 1;  /*!< [30..30] Transmit End Flag                                                */
18758             __IM uint32_t RDRF   : 1;  /*!< [31..31] Receive Data Full Flag                                           */
18759         } CSR_b;
18760     };
18761 
18762     union
18763     {
18764         __IM uint32_t ISR;             /*!< (@ 0x0000004C) Simple I2C Status Register                                 */
18765 
18766         struct
18767         {
18768             __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag                                            */
18769             uint32_t              : 2;
18770             __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
18771                                         *   Flag                                                                      */
18772             uint32_t : 28;
18773         } ISR_b;
18774     };
18775 
18776     union
18777     {
18778         __IM uint32_t FRSR;            /*!< (@ 0x00000050) FIFO Receive Status Register                               */
18779 
18780         struct
18781         {
18782             __IM uint32_t DR   : 1;    /*!< [0..0] Receive Data Ready flag                                            */
18783             uint32_t           : 7;
18784             __IM uint32_t R    : 6;    /*!< [13..8] Receive-FIFO Data Count                                           */
18785             uint32_t           : 2;
18786             __IM uint32_t PNUM : 6;    /*!< [21..16] Parity Error Count                                               */
18787             uint32_t           : 2;
18788             __IM uint32_t FNUM : 6;    /*!< [29..24] Framing Error Count                                              */
18789             uint32_t           : 2;
18790         } FRSR_b;
18791     };
18792 
18793     union
18794     {
18795         __IM uint32_t FTSR;            /*!< (@ 0x00000054) FIFO Transmit Status Register                              */
18796 
18797         struct
18798         {
18799             __IM uint32_t T : 6;       /*!< [5..0] Transmit-FIFO Data Count                                           */
18800             uint32_t        : 26;
18801         } FTSR_b;
18802     };
18803 
18804     union
18805     {
18806         __IM uint32_t MSR;             /*!< (@ 0x00000058) Manchester Status Register                                 */
18807 
18808         struct
18809         {
18810             __IM uint32_t PFER  : 1;   /*!< [0..0] Preface Error flag                                                 */
18811             __IM uint32_t SYER  : 1;   /*!< [1..1] SYNC Error flag                                                    */
18812             __IM uint32_t SBER  : 1;   /*!< [2..2] Start Bit Error flag                                               */
18813             uint32_t            : 1;
18814             __IM uint32_t MER   : 1;   /*!< [4..4] Manchester Error Flag                                              */
18815             uint32_t            : 1;
18816             __IM uint32_t RSYNC : 1;   /*!< [6..6] Receive SYNC data bit                                              */
18817             uint32_t            : 25;
18818         } MSR_b;
18819     };
18820 
18821     union
18822     {
18823         __IM uint32_t XSR0;            /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0                        */
18824 
18825         struct
18826         {
18827             __IM uint32_t SFSF  : 1;   /*!< [0..0] Start Frame Status flag                                            */
18828             __IM uint32_t RXDSF : 1;   /*!< [1..1] RXDn input status flag                                             */
18829             uint32_t            : 6;
18830             __IM uint32_t BFOF  : 1;   /*!< [8..8] Break Field Output completion flag                                 */
18831             __IM uint32_t BCDF  : 1;   /*!< [9..9] Bus Conflict detection flag                                        */
18832             __IM uint32_t BFDF  : 1;   /*!< [10..10] Break Field detection flag                                       */
18833             __IM uint32_t CF0MF : 1;   /*!< [11..11] Control Field 0 compare match flag                               */
18834             __IM uint32_t CF1MF : 1;   /*!< [12..12] Control Field 1 compare match flag                               */
18835             __IM uint32_t PIBDF : 1;   /*!< [13..13] Priority interrupt bit detection flag                            */
18836             __IM uint32_t COF   : 1;   /*!< [14..14] Counter Overflow flag                                            */
18837             __IM uint32_t AEDF  : 1;   /*!< [15..15] Active Edge detection flag                                       */
18838             __IM uint32_t CF0RD : 8;   /*!< [23..16] Control Field 0 received data                                    */
18839             __IM uint32_t CF1RD : 8;   /*!< [31..24] Control Field 1 received data                                    */
18840         } XSR0_b;
18841     };
18842 
18843     union
18844     {
18845         __IM uint32_t XSR1;            /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1                         */
18846 
18847         struct
18848         {
18849             __IM uint32_t TCNT : 16;   /*!< [15..0] Timer Count Capture value                                         */
18850             uint32_t           : 16;
18851         } XSR1_b;
18852     };
18853     __IM uint32_t RESERVED4;
18854 
18855     union
18856     {
18857         __OM uint32_t CFCLR;           /*!< (@ 0x00000068) Common Flag Clear Register                                 */
18858 
18859         struct
18860         {
18861             uint32_t            : 4;
18862             __OM uint32_t ERSC  : 1;   /*!< [4..4] ERS clear bit                                                      */
18863             uint32_t            : 11;
18864             __OM uint32_t DCMFC : 1;   /*!< [16..16] DCMF clear bit                                                   */
18865             __OM uint32_t DPERC : 1;   /*!< [17..17] DPER clear bit                                                   */
18866             __OM uint32_t DFERC : 1;   /*!< [18..18] DFER clear bit                                                   */
18867             uint32_t            : 5;
18868             __OM uint32_t ORERC : 1;   /*!< [24..24] ORER clear bit                                                   */
18869             uint32_t            : 1;
18870             __OM uint32_t MFFC  : 1;   /*!< [26..26] MFF clear bit                                                    */
18871             __OM uint32_t PERC  : 1;   /*!< [27..27] PER clear bit                                                    */
18872             __OM uint32_t FERC  : 1;   /*!< [28..28] FER clear bit                                                    */
18873             __OM uint32_t TDREC : 1;   /*!< [29..29] TDRE clear bit                                                   */
18874             uint32_t            : 1;
18875             __OM uint32_t RDRFC : 1;   /*!< [31..31] RDRF clear bit                                                   */
18876         } CFCLR_b;
18877     };
18878 
18879     union
18880     {
18881         __OM uint32_t ICFCLR;          /*!< (@ 0x0000006C) Simple I2C Flag Clear Register                             */
18882 
18883         struct
18884         {
18885             uint32_t               : 3;
18886             __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit                                                  */
18887             uint32_t               : 28;
18888         } ICFCLR_b;
18889     };
18890 
18891     union
18892     {
18893         __OM uint32_t FFCLR;           /*!< (@ 0x00000070) FIFO Flag Clear Register                                   */
18894 
18895         struct
18896         {
18897             __OM uint32_t DRC : 1;     /*!< [0..0] DR clear bit                                                       */
18898             uint32_t          : 31;
18899         } FFCLR_b;
18900     };
18901 
18902     union
18903     {
18904         __OM uint32_t MFCLR;           /*!< (@ 0x00000074) Manchester Flag Clear Register                             */
18905 
18906         struct
18907         {
18908             __OM uint32_t PFERC : 1;   /*!< [0..0] PFER clear bit                                                     */
18909             __OM uint32_t SYERC : 1;   /*!< [1..1] SYER clear bit                                                     */
18910             __OM uint32_t SBERC : 1;   /*!< [2..2] SBER clear bit                                                     */
18911             uint32_t            : 1;
18912             __OM uint32_t MERC  : 1;   /*!< [4..4] MER clear bit                                                      */
18913             uint32_t            : 27;
18914         } MFCLR_b;
18915     };
18916 
18917     union
18918     {
18919         __OM uint32_t XFCLR;           /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register                       */
18920 
18921         struct
18922         {
18923             uint32_t            : 8;
18924             __OM uint32_t BFOC  : 1;   /*!< [8..8] BFOF clear bit                                                     */
18925             __OM uint32_t BCDC  : 1;   /*!< [9..9] BCDF clear bit                                                     */
18926             __OM uint32_t BFDC  : 1;   /*!< [10..10] BFDF clear bit                                                   */
18927             __OM uint32_t CF0MC : 1;   /*!< [11..11] CF0MF clear bit                                                  */
18928             __OM uint32_t CF1MC : 1;   /*!< [12..12] CF1MF clear bit                                                  */
18929             __OM uint32_t PIBDC : 1;   /*!< [13..13] PIBDF clear bit                                                  */
18930             __OM uint32_t COFC  : 1;   /*!< [14..14] COFF clear bit                                                   */
18931             __OM uint32_t AEDC  : 1;   /*!< [15..15] AEDF clear bit                                                   */
18932             uint32_t            : 16;
18933         } XFCLR_b;
18934     };
18935 } R_SCI_B0_Type;                       /*!< Size = 124 (0x7c)                                                         */
18936 
18937 /* =========================================================================================================================== */
18938 /* ================                                         R_SPI_B0                                          ================ */
18939 /* =========================================================================================================================== */
18940 
18941 /**
18942  * @brief Serial Peripheral Interface 0 (R_SPI_B0)
18943  */
18944 
18945 typedef struct                         /*!< (@ 0x4035C000) R_SPI_B0 Structure                                         */
18946 {
18947     __IOM uint32_t SPDR;               /*!< (@ 0x00000000) RSPI Data Register                                         */
18948 
18949     union
18950     {
18951         __IOM uint32_t SPDECR;         /*!< (@ 0x00000004) RSPI Delay Control Register                                */
18952 
18953         struct
18954         {
18955             __IOM uint32_t SCKDL : 3;  /*!< [2..0] RSPCK Delay                                                        */
18956             uint32_t             : 5;
18957             __IOM uint32_t SLNDL : 3;  /*!< [10..8] SSL Negation Delay                                                */
18958             uint32_t             : 5;
18959             __IOM uint32_t SPNDL : 3;  /*!< [18..16] RSPI Next-Access Delay                                           */
18960             uint32_t             : 5;
18961             __IOM uint32_t ARST  : 3;  /*!< [26..24] Receive Sampling Timing Adjustment bits                          */
18962             uint32_t             : 5;
18963         } SPDECR_b;
18964     };
18965 
18966     union
18967     {
18968         __IOM uint32_t SPCR;             /*!< (@ 0x00000008) RSPI Control Register                                      */
18969 
18970         struct
18971         {
18972             __IOM uint32_t SPE      : 1; /*!< [0..0] RSPI Function Enable                                               */
18973             uint32_t                : 6;
18974             __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select                                   */
18975             __IOM uint32_t SPPE     : 1; /*!< [8..8] Parity Enable                                                      */
18976             __IOM uint32_t SPOE     : 1; /*!< [9..9] Parity Mode                                                        */
18977             uint32_t                : 1;
18978             __IOM uint32_t PTE      : 1; /*!< [11..11] Parity Self-Diagnosis Enable                                     */
18979             __IOM uint32_t SCKASE   : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable                                  */
18980             __IOM uint32_t BFDS     : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select                       */
18981             __IOM uint32_t MODFEN   : 1; /*!< [14..14] Mode Fault Error Detection Enable                                */
18982             uint32_t                : 1;
18983             __IOM uint32_t SPEIE    : 1; /*!< [16..16] RSPI Error Interrupt Enable                                      */
18984             __IOM uint32_t SPRIE    : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable                        */
18985             __IOM uint32_t SPIIE    : 1; /*!< [18..18] RSPI Idle Interrupt Enable                                       */
18986             __IOM uint32_t SPDRES   : 1; /*!< [19..19] RSPI receive data ready error select                             */
18987             __IOM uint32_t SPTIE    : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable                      */
18988             __IOM uint32_t CENDIE   : 1; /*!< [21..21] RSPI Communication End Interrupt Enable                          */
18989             uint32_t                : 2;
18990             __IOM uint32_t SPMS     : 1; /*!< [24..24] RSPI Mode Select                                                 */
18991             __IOM uint32_t SPFRF    : 1; /*!< [25..25] RSPI Frame Format Select                                         */
18992             uint32_t                : 2;
18993             __IOM uint32_t TXMD     : 2; /*!< [29..28] Communication Mode Select                                        */
18994             __IOM uint32_t MSTR     : 1; /*!< [30..30] RSPI Master/Slave Mode Select                                    */
18995             __IOM uint32_t BPEN     : 1; /*!< [31..31] Synchronization Circuit Bypass Enable                            */
18996         } SPCR_b;
18997     };
18998 
18999     union
19000     {
19001         __IOM uint32_t SPCR2;          /*!< (@ 0x0000000C) RSPI Control Register 2                                    */
19002 
19003         struct
19004         {
19005             __IOM uint32_t RMFM   : 5; /*!< [4..0] Frame processing count setting in Master Receive only              */
19006             uint32_t              : 1;
19007             __OM uint32_t  RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only                                 */
19008             __OM uint32_t  RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only                               */
19009             __IOM uint32_t SPDRC  : 8; /*!< [15..8] RSPI received data ready detect adjustment                        */
19010             __IOM uint32_t SPLP   : 1; /*!< [16..16] RSPI Loopback                                                    */
19011             __IOM uint32_t SPLP2  : 1; /*!< [17..17] RSPI Loopback 2                                                  */
19012             uint32_t              : 2;
19013             __IOM uint32_t MOIFV  : 1; /*!< [20..20] MOSI Idle Fixed Value                                            */
19014             __IOM uint32_t MOIFE  : 1; /*!< [21..21] MOSI Idle Fixed Value Enable                                     */
19015             uint32_t              : 10;
19016         } SPCR2_b;
19017     };
19018 
19019     union
19020     {
19021         __IOM uint32_t SPCR3;          /*!< (@ 0x00000010) RSPI Control Register 3                                    */
19022 
19023         struct
19024         {
19025             __IOM uint32_t SSL0P : 1;  /*!< [0..0] SSL0 Signal Polarity                                               */
19026             __IOM uint32_t SSL1P : 1;  /*!< [1..1] SSL1 Signal Polarity                                               */
19027             __IOM uint32_t SSL2P : 1;  /*!< [2..2] SSL2 Signal Polarity                                               */
19028             __IOM uint32_t SSL3P : 1;  /*!< [3..3] SSL3 Signal Polarity                                               */
19029             uint32_t             : 4;
19030             __IOM uint32_t SPBR  : 8;  /*!< [15..8] SPI Bit Rate                                                      */
19031             uint32_t             : 8;
19032             __IOM uint32_t SPSLN : 3;  /*!< [26..24] RSPI Sequence Length                                             */
19033             uint32_t             : 5;
19034         } SPCR3_b;
19035     };
19036 
19037     union
19038     {
19039         __IOM uint32_t SPCMD0;         /*!< (@ 0x00000014) RSPI Command Register                                      */
19040 
19041         struct
19042         {
19043             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19044             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19045             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19046             uint32_t              : 3;
19047             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19048             uint32_t              : 4;
19049             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19050             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19051             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19052             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19053             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19054             uint32_t              : 3;
19055             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19056             uint32_t              : 5;
19057         } SPCMD0_b;
19058     };
19059 
19060     union
19061     {
19062         __IOM uint32_t SPCMD1;         /*!< (@ 0x00000018) RSPI Command Register                                      */
19063 
19064         struct
19065         {
19066             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19067             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19068             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19069             uint32_t              : 3;
19070             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19071             uint32_t              : 4;
19072             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19073             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19074             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19075             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19076             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19077             uint32_t              : 3;
19078             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19079             uint32_t              : 5;
19080         } SPCMD1_b;
19081     };
19082 
19083     union
19084     {
19085         __IOM uint32_t SPCMD2;         /*!< (@ 0x0000001C) RSPI Command Register                                      */
19086 
19087         struct
19088         {
19089             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19090             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19091             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19092             uint32_t              : 3;
19093             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19094             uint32_t              : 4;
19095             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19096             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19097             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19098             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19099             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19100             uint32_t              : 3;
19101             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19102             uint32_t              : 5;
19103         } SPCMD2_b;
19104     };
19105 
19106     union
19107     {
19108         __IOM uint32_t SPCMD3;         /*!< (@ 0x00000020) RSPI Command Register                                      */
19109 
19110         struct
19111         {
19112             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19113             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19114             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19115             uint32_t              : 3;
19116             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19117             uint32_t              : 4;
19118             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19119             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19120             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19121             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19122             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19123             uint32_t              : 3;
19124             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19125             uint32_t              : 5;
19126         } SPCMD3_b;
19127     };
19128 
19129     union
19130     {
19131         __IOM uint32_t SPCMD4;         /*!< (@ 0x00000024) RSPI Command Register                                      */
19132 
19133         struct
19134         {
19135             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19136             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19137             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19138             uint32_t              : 3;
19139             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19140             uint32_t              : 4;
19141             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19142             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19143             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19144             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19145             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19146             uint32_t              : 3;
19147             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19148             uint32_t              : 5;
19149         } SPCMD4_b;
19150     };
19151 
19152     union
19153     {
19154         __IOM uint32_t SPCMD5;         /*!< (@ 0x00000028) RSPI Command Register                                      */
19155 
19156         struct
19157         {
19158             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19159             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19160             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19161             uint32_t              : 3;
19162             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19163             uint32_t              : 4;
19164             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19165             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19166             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19167             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19168             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19169             uint32_t              : 3;
19170             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19171             uint32_t              : 5;
19172         } SPCMD5_b;
19173     };
19174 
19175     union
19176     {
19177         __IOM uint32_t SPCMD6;         /*!< (@ 0x0000002C) RSPI Command Register                                      */
19178 
19179         struct
19180         {
19181             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19182             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19183             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19184             uint32_t              : 3;
19185             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19186             uint32_t              : 4;
19187             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19188             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19189             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19190             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19191             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19192             uint32_t              : 3;
19193             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19194             uint32_t              : 5;
19195         } SPCMD6_b;
19196     };
19197 
19198     union
19199     {
19200         __IOM uint32_t SPCMD7;         /*!< (@ 0x00000030) RSPI Command Register                                      */
19201 
19202         struct
19203         {
19204             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
19205             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
19206             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
19207             uint32_t              : 3;
19208             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
19209             uint32_t              : 4;
19210             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
19211             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
19212             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
19213             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
19214             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
19215             uint32_t              : 3;
19216             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
19217             uint32_t              : 5;
19218         } SPCMD7_b;
19219     };
19220     __IM uint32_t RESERVED[3];
19221 
19222     union
19223     {
19224         __IOM uint32_t SPDCR;          /*!< (@ 0x00000040) RSPI Data Control Register                                 */
19225 
19226         struct
19227         {
19228             __IOM uint32_t BYSW   : 1; /*!< [0..0] Byte Swap Operating Mode Select                                    */
19229             uint32_t              : 2;
19230             __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select                          */
19231             __IOM uint32_t SINV   : 1; /*!< [4..4] Serial data invert bit                                             */
19232             uint32_t              : 3;
19233             __IOM uint32_t SPFC   : 2; /*!< [9..8] Frame Count                                                        */
19234             uint32_t              : 22;
19235         } SPDCR_b;
19236     };
19237 
19238     union
19239     {
19240         __IOM uint32_t SPDCR2;         /*!< (@ 0x00000044) RSPI Data Control Register 2                               */
19241 
19242         struct
19243         {
19244             __IOM uint32_t RTRG : 2;   /*!< [1..0] Receive FIFO threshold setting                                     */
19245             uint32_t            : 6;
19246             __IOM uint32_t TTRG : 2;   /*!< [9..8] Transmission FIFO threshold setting                                */
19247             uint32_t            : 22;
19248         } SPDCR2_b;
19249     };
19250     __IM uint32_t RESERVED1[2];
19251 
19252     union
19253     {
19254         __IM uint32_t SPSR;            /*!< (@ 0x00000050) SPI Status Register                                        */
19255 
19256         struct
19257         {
19258             uint32_t            : 8;
19259             __IM uint32_t SPCP  : 3;   /*!< [10..8] RSPI Command Pointer                                              */
19260             uint32_t            : 1;
19261             __IM uint32_t SPECM : 3;   /*!< [14..12] RSPI Error Command                                               */
19262             uint32_t            : 8;
19263             __IM uint32_t SPDRF : 1;   /*!< [23..23] RSPI Receive Data Ready Flag                                     */
19264             __IM uint32_t OVRF  : 1;   /*!< [24..24] Overrun Error Flag                                               */
19265             __IM uint32_t IDLNF : 1;   /*!< [25..25] RSPI Idle Flag                                                   */
19266             __IM uint32_t MODF  : 1;   /*!< [26..26] Mode Fault Error Flag                                            */
19267             __IM uint32_t PERF  : 1;   /*!< [27..27] Parity Error Flag                                                */
19268             __IM uint32_t UDRF  : 1;   /*!< [28..28] Underrun Error Flag                                              */
19269             __IM uint32_t SPTEF : 1;   /*!< [29..29] RSPI Transmit Buffer Empty Flag                                  */
19270             __IM uint32_t CENDF : 1;   /*!< [30..30] Communication End Flag                                           */
19271             __IM uint32_t SPRF  : 1;   /*!< [31..31] RSPI Receive Buffer Full Flag                                    */
19272         } SPSR_b;
19273     };
19274     __IM uint32_t RESERVED2;
19275 
19276     union
19277     {
19278         __IM uint32_t SPTFSR;          /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register                         */
19279 
19280         struct
19281         {
19282             __IM uint32_t TFDN : 3;    /*!< [2..0] Transmit FIFO data empty stage number                              */
19283             uint32_t           : 29;
19284         } SPTFSR_b;
19285     };
19286 
19287     union
19288     {
19289         __IM uint32_t SPRFSR;          /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register                          */
19290 
19291         struct
19292         {
19293             __IM uint32_t RFDN : 3;    /*!< [2..0] Receive FIFO data store stage number                               */
19294             uint32_t           : 29;
19295         } SPRFSR_b;
19296     };
19297 
19298     union
19299     {
19300         __IM uint32_t SPPSR;           /*!< (@ 0x00000060) RSPI Poling Register                                       */
19301 
19302         struct
19303         {
19304             __IM uint32_t SPEPS : 1;   /*!< [0..0] RSPI Poling Status                                                 */
19305             uint32_t            : 31;
19306         } SPPSR_b;
19307     };
19308     __IM uint32_t RESERVED3;
19309 
19310     union
19311     {
19312         __IOM uint32_t SPSRC;          /*!< (@ 0x00000068) RSPI Status Clear Register                                 */
19313 
19314         struct
19315         {
19316             uint32_t             : 23;
19317             __OM uint32_t SPDRFC : 1;  /*!< [23..23] RSPI Receive Data Ready Flag Clear                               */
19318             __OM uint32_t OVRFC  : 1;  /*!< [24..24] Overrun Error Flag Clear                                         */
19319             uint32_t             : 1;
19320             __OM uint32_t MODFC  : 1;  /*!< [26..26] Mode Fault Error Flag Clear                                      */
19321             __OM uint32_t PERFC  : 1;  /*!< [27..27] Parity Error Flag Clear                                          */
19322             __OM uint32_t UDRFC  : 1;  /*!< [28..28] Underrun Error Flag Clear                                        */
19323             __OM uint32_t SPTEFC : 1;  /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear                            */
19324             __OM uint32_t CENDFC : 1;  /*!< [30..30] Communication End Flag Clear                                     */
19325             __OM uint32_t SPRFC  : 1;  /*!< [31..31] RSPI Receive Buffer Full Flag Clear                              */
19326         } SPSRC_b;
19327     };
19328 
19329     union
19330     {
19331         __IOM uint32_t SPFCR;          /*!< (@ 0x0000006C) RSPI FIFO Clear Register                                   */
19332 
19333         struct
19334         {
19335             __OM uint32_t SPFRST : 1;  /*!< [0..0] RSPI FIFO clear                                                    */
19336             uint32_t             : 31;
19337         } SPFCR_b;
19338     };
19339 } R_SPI_B0_Type;                       /*!< Size = 112 (0x70)                                                         */
19340 
19341 /* =========================================================================================================================== */
19342 /* ================                                          R_XSPI                                           ================ */
19343 /* =========================================================================================================================== */
19344 
19345 /**
19346  * @brief eXpanded SPI (R_XSPI)
19347  */
19348 
19349 typedef struct                           /*!< (@ 0x40268000) R_XSPI Structure                                           */
19350 {
19351     union
19352     {
19353         __IOM uint32_t WRAPCFG;          /*!< (@ 0x00000000) xSPI Wrapper Configuration register                        */
19354 
19355         struct
19356         {
19357             __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0                                                */
19358             uint32_t                : 3;
19359             __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0                                               */
19360             uint32_t                : 3;
19361             __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1                                              */
19362             uint32_t                : 3;
19363             __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1                                              */
19364             uint32_t                : 3;
19365         } WRAPCFG_b;
19366     };
19367 
19368     union
19369     {
19370         __IOM uint32_t COMCFG;              /*!< (@ 0x00000004) xSPI Common Configuration register                         */
19371 
19372         struct
19373         {
19374             __IOM uint32_t ARBMD       : 2; /*!< [1..0] Channel arbitration mode                                           */
19375             uint32_t                   : 2;
19376             __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable                                              */
19377             uint32_t                   : 10;
19378             __IOM uint32_t OEASTEX     : 1; /*!< [16..16] Output Enable Asserting extension                                */
19379             __IOM uint32_t OENEGEX     : 1; /*!< [17..17] Output Enable Negating extension                                 */
19380             uint32_t                   : 14;
19381         } COMCFG_b;
19382     };
19383 
19384     union
19385     {
19386         __IOM uint32_t BMCFGCH[2];        /*!< (@ 0x00000008) xSPI Bridge Map Configuration register                     */
19387 
19388         struct
19389         {
19390             __IOM uint32_t WRMD    : 1;   /*!< [0..0] AHB Write Response mode                                            */
19391             uint32_t               : 6;
19392             __IOM uint32_t MWRCOMB : 1;   /*!< [7..7] Memory Write Combination mode                                      */
19393             __IOM uint32_t MWRSIZE : 8;   /*!< [15..8] Memory Write Size                                                 */
19394             __IOM uint32_t PREEN   : 1;   /*!< [16..16] Prefetch enable                                                  */
19395             uint32_t               : 7;
19396             __IOM uint32_t CMBTIM  : 8;   /*!< [31..24] Combination timer                                                */
19397         } BMCFGCH_b[2];
19398     };
19399     __IOM R_XSPI_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers                   */
19400     __IM uint32_t             RESERVED[8];
19401 
19402     union
19403     {
19404         __IOM uint32_t LIOCFGCS[2];        /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1]              */
19405 
19406         struct
19407         {
19408             __IOM uint32_t PRTMD     : 10; /*!< [9..0] Protocol mode                                                      */
19409             __IOM uint32_t LATEMD    : 1;  /*!< [10..10] Latency mode                                                     */
19410             __IOM uint32_t WRMSKMD   : 1;  /*!< [11..11] Write mask mode                                                  */
19411             uint32_t                 : 4;
19412             __IOM uint32_t CSMIN     : 4;  /*!< [19..16] CS minimum idle term                                             */
19413             __IOM uint32_t CSASTEX   : 1;  /*!< [20..20] CS asserting extension                                           */
19414             __IOM uint32_t CSNEGEX   : 1;  /*!< [21..21] CS negating extension                                            */
19415             __IOM uint32_t SDRDRV    : 1;  /*!< [22..22] SDR driving timing                                               */
19416             __IOM uint32_t SDRSMPMD  : 1;  /*!< [23..23] SDR Sampling mode                                                */
19417             __IOM uint32_t SDRSMPSFT : 4;  /*!< [27..24] SDR Sampling window shift                                        */
19418             __IOM uint32_t DDRSMPEX  : 4;  /*!< [31..28] DDR sampling window extend                                       */
19419         } LIOCFGCS_b[2];
19420     };
19421 
19422     union
19423     {
19424         __IOM uint32_t ABMCFG;         /*!< (@ 0x00000058) xSPI AXI Bridge Map Config                                 */
19425 
19426         struct
19427         {
19428             __IOM uint32_t ODRMD : 2;  /*!< [1..0] AXI Transfer Ordering Mode                                         */
19429             uint32_t             : 14;
19430             __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select                                  */
19431         } ABMCFG_b;
19432     };
19433     __IM uint32_t RESERVED1;
19434 
19435     union
19436     {
19437         __IOM uint32_t BMCTL0;            /*!< (@ 0x00000060) xSPI Bridge Map Control register 0                         */
19438 
19439         struct
19440         {
19441             __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable                 */
19442             __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable                 */
19443             __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable                 */
19444             __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable                 */
19445             uint32_t                 : 24;
19446         } BMCTL0_b;
19447     };
19448 
19449     union
19450     {
19451         __OM uint32_t BMCTL1;          /*!< (@ 0x00000064) xSPI Bridge Map Control register 1                         */
19452 
19453         struct
19454         {
19455             uint32_t                 : 8;
19456             __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0                                     */
19457             __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1                                     */
19458             __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0                                    */
19459             __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1                                    */
19460             uint32_t                 : 20;
19461         } BMCTL1_b;
19462     };
19463 
19464     union
19465     {
19466         __IOM uint32_t CMCTLCH[2];        /*!< (@ 0x00000068) xSPI Command Map Control register                          */
19467 
19468         struct
19469         {
19470             __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code                                                */
19471             __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code                                                */
19472             __IOM uint32_t XIPEN     : 1; /*!< [16..16] XiP mode enable                                                  */
19473             uint32_t                 : 15;
19474         } CMCTLCH_b[2];
19475     };
19476 
19477     union
19478     {
19479         __IOM uint32_t CDCTL0;         /*!< (@ 0x00000070) xSPI Command Manual Control register 0                     */
19480 
19481         struct
19482         {
19483             __IOM uint32_t TRREQ  : 1; /*!< [0..0] Transaction request                                                */
19484             __IOM uint32_t PERMD  : 1; /*!< [1..1] Periodic mode                                                      */
19485             uint32_t              : 1;
19486             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
19487             __IOM uint32_t TRNUM  : 2; /*!< [5..4] Transaction number                                                 */
19488             uint32_t              : 10;
19489             __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval                                    */
19490             uint32_t              : 3;
19491             __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat                                      */
19492             uint32_t              : 4;
19493         } CDCTL0_b;
19494     };
19495 
19496     union
19497     {
19498         __IOM uint32_t CDCTL1;          /*!< (@ 0x00000074) xSPI Command Manual Control register 1                     */
19499 
19500         struct
19501         {
19502             __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value                               */
19503         } CDCTL1_b;
19504     };
19505 
19506     union
19507     {
19508         __IOM uint32_t CDCTL2;          /*!< (@ 0x00000078) xSPI Command Manual Control register 2                     */
19509 
19510         struct
19511         {
19512             __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value                                 */
19513         } CDCTL2_b;
19514     };
19515     __IM uint32_t           RESERVED2;
19516     __IOM R_XSPI_CDBUF_Type CDBUF[4];   /*!< (@ 0x00000080) xSPI BUF register                                          */
19517     __IM uint32_t           RESERVED3[16];
19518 
19519     union
19520     {
19521         __IOM uint32_t LPCTL0;         /*!< (@ 0x00000100) xSPI Link Pattern Control register 0                       */
19522 
19523         struct
19524         {
19525             __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request                                                    */
19526             uint32_t              : 2;
19527             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
19528             __IOM uint32_t XDPIN  : 2; /*!< [5..4] XiP Disable pattern pin                                            */
19529             uint32_t              : 10;
19530             __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length                             */
19531             uint32_t              : 2;
19532             __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value                              */
19533             __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length                             */
19534             uint32_t              : 2;
19535             __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value                              */
19536         } LPCTL0_b;
19537     };
19538 
19539     union
19540     {
19541         __IOM uint32_t LPCTL1;         /*!< (@ 0x00000104) xSPI Link Pattern Control register 1                       */
19542 
19543         struct
19544         {
19545             __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request                                                    */
19546             uint32_t              : 1;
19547             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
19548             __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat                                               */
19549             uint32_t              : 2;
19550             __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width                                               */
19551             uint32_t              : 1;
19552             __IOM uint32_t RSTSU  : 3; /*!< [14..12] Reset pattern data output setup time                             */
19553             uint32_t              : 17;
19554         } LPCTL1_b;
19555     };
19556 
19557     union
19558     {
19559         __IOM uint32_t LIOCTL;         /*!< (@ 0x00000108) xSPI Link I/O Control register                             */
19560 
19561         struct
19562         {
19563             __IOM uint32_t WPCS0  : 1; /*!< [0..0] WP drive for slave 0                                               */
19564             __IOM uint32_t WPCS1  : 1; /*!< [1..1] WP drive for slave 1                                               */
19565             uint32_t              : 14;
19566             __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0                                          */
19567             __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1                                          */
19568             uint32_t              : 14;
19569         } LIOCTL_b;
19570     };
19571     __IM uint32_t             RESERVED4[9];
19572     __IOM R_XSPI_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register                                           */
19573     __IM uint32_t             RESERVED5[4];
19574 
19575     union
19576     {
19577         __IM uint32_t VERSTT;          /*!< (@ 0x00000180) xSPI Version register                                      */
19578 
19579         struct
19580         {
19581             __IM uint32_t VER : 32;    /*!< [31..0] Version                                                           */
19582         } VERSTT_b;
19583     };
19584 
19585     union
19586     {
19587         __IM uint32_t COMSTT;             /*!< (@ 0x00000184) xSPI Common Status register                                */
19588 
19589         struct
19590         {
19591             __IM uint32_t MEMACCCH0  : 1; /*!< [0..0] Memory access ongoing from ch0                                     */
19592             __IM uint32_t MEMACCCH1  : 1; /*!< [1..1] Memory access ongoing from ch1                                     */
19593             uint32_t                 : 2;
19594             __IM uint32_t PBUFNECH0  : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0                                  */
19595             __IM uint32_t PBUFNECH1  : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1                                  */
19596             __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0                                     */
19597             __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1                                     */
19598             uint32_t                 : 8;
19599             __IM uint32_t ECSCS0     : 1; /*!< [16..16] ECS monitor for slave0                                           */
19600             __IM uint32_t INTCS0     : 1; /*!< [17..17] INT monitor for slave0                                           */
19601             __IM uint32_t RSTOCS0    : 1; /*!< [18..18] RSTO monitor for slave0                                          */
19602             uint32_t                 : 1;
19603             __IM uint32_t ECSCS1     : 1; /*!< [20..20] ECS monitor for slave1                                           */
19604             __IM uint32_t INTCS1     : 1; /*!< [21..21] INT monitor for slave1                                           */
19605             __IM uint32_t RSTOCS1    : 1; /*!< [22..22] RSTO monitor for slave1                                          */
19606             uint32_t                 : 9;
19607         } COMSTT_b;
19608     };
19609 
19610     union
19611     {
19612         __IM uint32_t CASTTCS[2];      /*!< (@ 0x00000188) xSPI Calibration Status register                           */
19613 
19614         struct
19615         {
19616             __IM uint32_t CASUC : 32;  /*!< [31..0] Calibration Success                                               */
19617         } CASTTCS_b[2];
19618     };
19619 
19620     union
19621     {
19622         __IM uint32_t INTS;              /*!< (@ 0x00000190) xSPI Interrupt Status register                             */
19623 
19624         struct
19625         {
19626             __IM uint32_t CMDCMP    : 1; /*!< [0..0] Command Completed                                                  */
19627             __IM uint32_t PATCMP    : 1; /*!< [1..1] Pattern Completed                                                  */
19628             __IM uint32_t INICMP    : 1; /*!< [2..2] Initial Sequence Completed                                         */
19629             __IM uint32_t PERTO     : 1; /*!< [3..3] Periodic transaction timeout                                       */
19630             __IM uint32_t DSTOCS0   : 1; /*!< [4..4] DS timeout for slave0                                              */
19631             __IM uint32_t DSTOCS1   : 1; /*!< [5..5] DS timeout for slave1                                              */
19632             uint32_t                : 2;
19633             __IM uint32_t ECSCS0    : 1; /*!< [8..8] ECC error detection for slave0                                     */
19634             __IM uint32_t ECSCS1    : 1; /*!< [9..9] ECC error detection for slave1                                     */
19635             uint32_t                : 2;
19636             __IM uint32_t INTCS0    : 1; /*!< [12..12] Interrupt detection for slave0                                   */
19637             __IM uint32_t INTCS1    : 1; /*!< [13..13] Interrupt detection for slave1                                   */
19638             uint32_t                : 2;
19639             __IM uint32_t BRGOFCH0  : 1; /*!< [16..16] Bridge Buffer overflow for CH0                                   */
19640             __IM uint32_t BRGOFCH1  : 1; /*!< [17..17] Bridge Buffer overflow for CH1                                   */
19641             __IM uint32_t BRGUFCH0  : 1; /*!< [18..18] Bridge Buffer underflow for CH0                                  */
19642             __IM uint32_t BRGUFCH1  : 1; /*!< [19..19] Bridge Buffer underflow for CH1                                  */
19643             __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0                                            */
19644             __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1                                            */
19645             uint32_t                : 6;
19646             __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0                                    */
19647             __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1                                    */
19648             __IM uint32_t CASUCCS0  : 1; /*!< [30..30] Calibration success for slave0                                   */
19649             __IM uint32_t CASUCCS1  : 1; /*!< [31..31] Calibration success for slave1                                   */
19650         } INTS_b;
19651     };
19652 
19653     union
19654     {
19655         __OM uint32_t INTC;               /*!< (@ 0x00000194) xSPI Interrupt Clear register                              */
19656 
19657         struct
19658         {
19659             __OM uint32_t CMDCMPC    : 1; /*!< [0..0] Command Completed interrupt clear                                  */
19660             __OM uint32_t PATCMPC    : 1; /*!< [1..1] Pattern Completed interrupt clear                                  */
19661             __OM uint32_t INICMPC    : 1; /*!< [2..2] Initial Sequence Completed interrupt clear                         */
19662             __OM uint32_t PERTOC     : 1; /*!< [3..3] Periodic transaction timeout interrupt clear                       */
19663             __OM uint32_t DSTOCS0C   : 1; /*!< [4..4] DS timeout for slave0 interrupt clear                              */
19664             __OM uint32_t DSTOCS1C   : 1; /*!< [5..5] DS timeout for slave1 interrupt clear                              */
19665             uint32_t                 : 2;
19666             __OM uint32_t ECSCS0C    : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear                     */
19667             __OM uint32_t ECSCS1C    : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear                     */
19668             uint32_t                 : 2;
19669             __OM uint32_t INTCS0C    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear                   */
19670             __OM uint32_t INTCS1C    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear                   */
19671             uint32_t                 : 2;
19672             __OM uint32_t BRGOFCH0C  : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear                   */
19673             __OM uint32_t BRGOFCH1C  : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear                   */
19674             __OM uint32_t BRGUFCH0C  : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear                  */
19675             __OM uint32_t BRGUFCH1C  : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear                  */
19676             __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear                            */
19677             __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear                            */
19678             uint32_t                 : 6;
19679             __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear                    */
19680             __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear                    */
19681             __OM uint32_t CASUCCS0C  : 1; /*!< [30..30] Calibration success for slave0 interrupt clear                   */
19682             __OM uint32_t CASUCCS1C  : 1; /*!< [31..31] Calibration success for slave1 interrupt clear                   */
19683         } INTC_b;
19684     };
19685 
19686     union
19687     {
19688         __IOM uint32_t INTE;               /*!< (@ 0x00000198) xSPI Interrupt Enable register                             */
19689 
19690         struct
19691         {
19692             __IOM uint32_t CMDCMPE    : 1; /*!< [0..0] Command Completed interrupt enable                                 */
19693             __IOM uint32_t PATCMPE    : 1; /*!< [1..1] Pattern Completed interrupt enable                                 */
19694             __IOM uint32_t INICMPE    : 1; /*!< [2..2] Initial Sequence Completed interrupt enable                        */
19695             __IOM uint32_t PERTOE     : 1; /*!< [3..3] Periodic transaction timeout interrupt enable                      */
19696             __IOM uint32_t DSTOCS0E   : 1; /*!< [4..4] DS timeout for slave0 interrupt enable                             */
19697             __IOM uint32_t DSTOCS1E   : 1; /*!< [5..5] DS timeout for slave1 interrupt enable                             */
19698             uint32_t                  : 2;
19699             __IOM uint32_t ECSCS0E    : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable                    */
19700             __IOM uint32_t ECSCS1E    : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable                    */
19701             uint32_t                  : 2;
19702             __IOM uint32_t INTCS0E    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable                  */
19703             __IOM uint32_t INTCS1E    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable                  */
19704             uint32_t                  : 2;
19705             __IOM uint32_t BRGOFCH0E  : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable                  */
19706             __IOM uint32_t BRGOFCH1E  : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable                  */
19707             __IOM uint32_t BRGUFCH0E  : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable                 */
19708             __IOM uint32_t BRGUFCH1E  : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable                 */
19709             __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable                           */
19710             __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable                           */
19711             uint32_t                  : 6;
19712             __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable                   */
19713             __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable                   */
19714             __IOM uint32_t CASUCCS0E  : 1; /*!< [30..30] Calibration success for slave0 interrupt enable                  */
19715             __IOM uint32_t CASUCCS1E  : 1; /*!< [31..31] Calibration success for slave1 interrupt enable                  */
19716         } INTE_b;
19717     };
19718 } R_XSPI_Type;                             /*!< Size = 412 (0x19c)                                                        */
19719 
19720 /* =========================================================================================================================== */
19721 /* ================                                          R_ULPT0                                          ================ */
19722 /* =========================================================================================================================== */
19723 
19724 /**
19725  * @brief Ultra-Low Power Timer 0 (R_ULPT0)
19726  */
19727 
19728 typedef struct                           /*!< (@ 0x40220000) R_ULPT0 Structure                                          */
19729 {
19730     union
19731     {
19732         __IOM uint32_t ULPTCNT;          /*!< (@ 0x00000000) ULPT Counter Register                                      */
19733 
19734         struct
19735         {
19736             __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written
19737                                           *   to the TSTOP bit in the ULPTCR register, the 32-bit counter
19738                                           *   is forcibly stopped and set to FFFFFFFFH.                                 */
19739         } ULPTCNT_b;
19740     };
19741 
19742     union
19743     {
19744         __IOM uint32_t ULPTCMA;          /*!< (@ 0x00000004) ULPT Compare Match A Register                              */
19745 
19746         struct
19747         {
19748             __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written
19749                                           *   to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH                 */
19750         } ULPTCMA_b;
19751     };
19752 
19753     union
19754     {
19755         __IOM uint32_t ULPTCMB;          /*!< (@ 0x00000008) ULPT Compare Match B Register                              */
19756 
19757         struct
19758         {
19759             __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written
19760                                           *   to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH                 */
19761         } ULPTCMB_b;
19762     };
19763 
19764     union
19765     {
19766         __IOM uint8_t ULPTCR;          /*!< (@ 0x0000000C) ULPT Control Register                                      */
19767 
19768         struct
19769         {
19770             __IOM uint8_t TSTART : 1;  /*!< [0..0] ULPT count start                                                   */
19771             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] ULPT count status flag                                             */
19772             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] ULPT count forced stop                                             */
19773             uint8_t              : 2;
19774             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] ULPT underflow flag                                                */
19775             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] ULPT compare match A flag                                          */
19776             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] ULPT compare match B flag                                          */
19777         } ULPTCR_b;
19778     };
19779 
19780     union
19781     {
19782         __IOM uint8_t ULPTMR1;         /*!< (@ 0x0000000D) ULPT Mode Register 1                                       */
19783 
19784         struct
19785         {
19786             uint8_t              : 1;
19787             __IOM uint8_t TMOD1  : 1;  /*!< [1..1] ULPT operating mode select                                         */
19788             uint8_t              : 1;
19789             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] ULPTEVI edge polarity select                                       */
19790             uint8_t              : 1;
19791             __IOM uint8_t TCK1   : 1;  /*!< [5..5] ULPT count source select                                           */
19792             uint8_t              : 2;
19793         } ULPTMR1_b;
19794     };
19795 
19796     union
19797     {
19798         __IOM uint8_t ULPTMR2;         /*!< (@ 0x0000000E) ULPT Mode Register 2                                       */
19799 
19800         struct
19801         {
19802             __IOM uint8_t CKS : 3;     /*!< [2..0] fsub/LOCO count source clock frequency division ratio
19803                                         *   select                                                                    */
19804             uint8_t           : 4;
19805             __IOM uint8_t LPM : 1;     /*!< [7..7] ULPT Low Power Mode                                                */
19806         } ULPTMR2_b;
19807     };
19808 
19809     union
19810     {
19811         __IOM uint8_t ULPTMR3;         /*!< (@ 0x0000000F) ULPT Mode Register 3                                       */
19812 
19813         struct
19814         {
19815             __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select                                         */
19816             __IOM uint8_t TEVPOL  : 1; /*!< [1..1] ULPTEVI polarity switch                                            */
19817             __IOM uint8_t TOPOL   : 1; /*!< [2..2] ULPTO polarity select                                              */
19818             uint8_t               : 1;
19819             __IOM uint8_t TEECTL  : 2; /*!< [5..4] ULPTEE function select                                             */
19820             __IOM uint8_t TEEPOL  : 2; /*!< [7..6] ULPTEE edge polarity select                                        */
19821         } ULPTMR3_b;
19822     };
19823 
19824     union
19825     {
19826         __IOM uint8_t ULPTIOC;         /*!< (@ 0x00000010) ULPT I/O Control Register                                  */
19827 
19828         struct
19829         {
19830             uint8_t              : 2;
19831             __IOM uint8_t TOE    : 1;  /*!< [2..2] ULPTO output enable                                                */
19832             uint8_t              : 1;
19833             __IOM uint8_t TIPF   : 2;  /*!< [5..4] ULPTEVI input filter select                                        */
19834             __IOM uint8_t TIOGT0 : 1;  /*!< [6..6] ULPTEVI count control                                              */
19835             uint8_t              : 1;
19836         } ULPTIOC_b;
19837     };
19838 
19839     union
19840     {
19841         __IOM uint8_t ULPTISR;         /*!< (@ 0x00000011) ULPT Event Pin Select Register                             */
19842 
19843         struct
19844         {
19845             uint8_t                : 2;
19846             __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection                                           */
19847             uint8_t                : 5;
19848         } ULPTISR_b;
19849     };
19850 
19851     union
19852     {
19853         __IOM uint8_t ULPTCMSR;        /*!< (@ 0x00000012) ULPT Compare Match Function Select Register                */
19854 
19855         struct
19856         {
19857             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
19858             __IOM uint8_t TOEA   : 1;  /*!< [1..1] ULPTOA output enable                                               */
19859             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] ULPTOA polarity select                                             */
19860             uint8_t              : 1;
19861             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
19862             __IOM uint8_t TOEB   : 1;  /*!< [5..5] ULPTOB output enable                                               */
19863             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] ULPTOB polarity select                                             */
19864             uint8_t              : 1;
19865         } ULPTCMSR_b;
19866     };
19867     __IM uint8_t RESERVED;
19868 } R_ULPT0_Type;                        /*!< Size = 20 (0x14)                                                          */
19869 
19870 /* =========================================================================================================================== */
19871 /* ================                                        R_DEBUG_OCD                                        ================ */
19872 /* =========================================================================================================================== */
19873 
19874 /**
19875  * @brief On-Chip Debug Function (R_DEBUG_OCD)
19876  */
19877 
19878 typedef struct                         /*!< (@ 0x40011000) R_DEBUG_OCD Structure                                      */
19879 {
19880     __IM uint32_t RESERVED[192];
19881 
19882     union
19883     {
19884         __IM uint32_t FSBLSTATM;       /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register            */
19885 
19886         struct
19887         {
19888             __IM uint32_t CS : 1;      /*!< [0..0] FSBL completion status.                                            */
19889             __IM uint32_t RS : 1;      /*!< [1..1] FSBL result status.                                                */
19890             uint32_t         : 30;
19891         } FSBLSTATM_b;
19892     };
19893 } R_DEBUG_OCD_Type;                    /*!< Size = 772 (0x304)                                                        */
19894 
19895 /* =========================================================================================================================== */
19896 /* ================                                          R_AGTX0                                          ================ */
19897 /* =========================================================================================================================== */
19898 
19899 /**
19900  * @brief Asynchronous General Purpose Timer (R_AGTX0)
19901  */
19902 
19903 typedef struct                          /*!< (@ 0x40221000) R_AGTX0 Structure                                          */
19904 {
19905     union
19906     {
19907         __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
19908         __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
19909     };
19910 } R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
19911 
19912 /* =========================================================================================================================== */
19913 /* ================                                          R_FLAD                                           ================ */
19914 /* =========================================================================================================================== */
19915 
19916 /**
19917  * @brief Data Flash (R_FLAD)
19918  */
19919 
19920 typedef struct                         /*!< (@ 0x4011C000) R_FLAD Structure                                           */
19921 {
19922     __IM uint8_t RESERVED[64];
19923 
19924     union
19925     {
19926         __IOM uint8_t FCKMHZ;          /*!< (@ 0x00000040) Data Flash Access Frequency Register                       */
19927 
19928         struct
19929         {
19930             __IOM uint8_t FCKMHZ : 8;  /*!< [7..0] Data Flash Access Frequency Register                               */
19931         } FCKMHZ_b;
19932     };
19933 } R_FLAD_Type;                         /*!< Size = 65 (0x41)                                                          */
19934 
19935 /* =========================================================================================================================== */
19936 /* ================                                      R_OFS_DATAFLASH                                      ================ */
19937 /* =========================================================================================================================== */
19938 
19939 /**
19940  * @brief Data Flash Option-Setting Memory (R_OFS_DATAFLASH)
19941  */
19942 
19943 typedef struct                         /*!< (@ 0x27030000) R_OFS_DATAFLASH Structure                                  */
19944 {
19945     __IM uint32_t RESERVED[32];
19946 
19947     union
19948     {
19949         __IM uint32_t FSBLCTRL0;          /*!< (@ 0x00000080) FSBL Control Register 0                                    */
19950 
19951         struct
19952         {
19953             __IM uint32_t FSBLEN     : 3; /*!< [2..0] FSBL Enable                                                        */
19954             __IM uint32_t FSBLSKIPSW : 3; /*!< [5..3] FSBL Skip Enable for Software Reset                                */
19955             __IM uint32_t FSBLSKIPDS : 3; /*!< [8..6] FSBL Skip Enable for Deep Software Standby Reset                   */
19956             __IM uint32_t FSBLCLK    : 3; /*!< [11..9] Clock Frequency Selection during FSBL Execution                   */
19957             uint32_t                 : 20;
19958         } FSBLCTRL0_b;
19959     };
19960 
19961     union
19962     {
19963         __IM uint32_t FSBLCTRL1;        /*!< (@ 0x00000084) FSBL Control Register 1                                    */
19964 
19965         struct
19966         {
19967             __IM uint32_t FSBLEXMD : 2; /*!< [1..0] FSBL Execution Mode                                                */
19968             uint32_t               : 30;
19969         } FSBLCTRL1_b;
19970     };
19971 
19972     union
19973     {
19974         __IM uint32_t FSBLCTRL2;                  /*!< (@ 0x00000088) FSBL Control Register 2                                    */
19975 
19976         struct
19977         {
19978             __IM uint32_t PORTPN : 4;             /*!< [3..0] FSBL Error Notification Port Pin Number                            */
19979             __IM uint32_t PORTGN : 5;             /*!< [8..4] FSBL Error Notification Port Group Name                            */
19980             uint32_t             : 23;
19981         } FSBLCTRL2_b;
19982     };
19983     __IOM uint32_t SACC0;                         /*!< (@ 0x0000008C) Start Address of Code Certification 0                      */
19984     __IOM uint32_t SACC1;                         /*!< (@ 0x00000090) Start Address of Code Certification 1                      */
19985     __IOM uint32_t SAMR;                          /*!< (@ 0x00000094) Start Address of Measurement Report                        */
19986     __IM uint32_t  RESERVED1[178];
19987     __IM uint32_t  HOEMRTPK;                      /*!< (@ 0x00000360) Hask of OEM_ROOT_PK                                        */
19988     __IM uint32_t  RESERVED2[7];
19989     __IOM R_OFS_DATAFLASH_CFGDLOCK_Type CFGDLOCK; /*!< (@ 0x00000380) Configuration Data Lock Bits                               */
19990     __IM uint32_t RESERVED3[11];
19991 
19992     union
19993     {
19994         __IOM uint16_t ARCLS;            /*!< (@ 0x000003C0) Anti-Rollback Counter Lock Setting                         */
19995 
19996         struct
19997         {
19998             __IOM uint16_t ARCS_LK  : 1; /*!< [0..0] ARC_SEC Lock                                                       */
19999             __IOM uint16_t ARCNS_LK : 4; /*!< [4..1] ARC_NSEC Lock                                                      */
20000             __IOM uint16_t ARCBL_LK : 1; /*!< [5..5] ARC_OEMBL Lock                                                     */
20001             uint16_t                : 10;
20002         } ARCLS_b;
20003     };
20004 
20005     union
20006     {
20007         __IOM uint16_t ARCCS;             /*!< (@ 0x000003C2) ARCCS                                                      */
20008 
20009         struct
20010         {
20011             __IOM uint16_t CNF_ARCNS : 2; /*!< [1..0] Configuation setting for ARC_NSEC                                  */
20012             uint16_t                 : 14;
20013         } ARCCS_b;
20014     };
20015     __IM uint32_t RESERVED4[291];
20016 
20017     union
20018     {
20019         __IOM uint32_t ARC_SEC[2];       /*!< (@ 0x00000850) Anti-Rollback Counter for Secure Application
20020                                           *                  n                                                          */
20021 
20022         struct
20023         {
20024             __IOM uint32_t ARC_SEC : 32; /*!< [31..0] ARC_SEC                                                           */
20025         } ARC_SEC_b[2];
20026     };
20027 
20028     union
20029     {
20030         __IOM uint32_t ARC_NSEC[8];       /*!< (@ 0x00000858) Anti-Rollback Counter for Non-Secure Application           */
20031 
20032         struct
20033         {
20034             __IOM uint32_t ARC_NSEC : 32; /*!< [31..0] Anti-Rollback Counter for Non-secure Application                  */
20035         } ARC_NSEC_b[8];
20036     };
20037 
20038     union
20039     {
20040         __IOM uint32_t ARC_OEMBL[2];       /*!< (@ 0x00000878) Anti-Rollback Counter for OEMBL                            */
20041 
20042         struct
20043         {
20044             __IOM uint32_t ARC_OEMBL : 32; /*!< [31..0] Anti-Rollback Counter for OEM_BL Application                      */
20045         } ARC_OEMBL_b[2];
20046     };
20047 } R_OFS_DATAFLASH_Type;                    /*!< Size = 2176 (0x880)                                                       */
20048 
20049 /** @} */ /* End of group Device_Peripheral_peripherals */
20050 
20051 /* =========================================================================================================================== */
20052 /* ================                          Device Specific Peripheral Address Map                           ================ */
20053 /* =========================================================================================================================== */
20054 
20055 /** @addtogroup Device_Peripheral_peripheralAddr
20056  * @{
20057  */
20058 
20059  #if defined(_RA_TZ_NONSECURE)
20060   #define BASE_NS_OFFSET         (BSP_FEATURE_TZ_NS_OFFSET)
20061  #else
20062   #define BASE_NS_OFFSET         0U
20063  #endif
20064 
20065  #define R_ACMPHS0_BASE          (0x40236000UL + BASE_NS_OFFSET)
20066  #define R_ACMPHS1_BASE          (0x40236100UL + BASE_NS_OFFSET)
20067  #define R_ACMPHS2_BASE          (0x40236200UL + BASE_NS_OFFSET)
20068  #define R_ACMPHS3_BASE          (0x40236300UL + BASE_NS_OFFSET)
20069  #define R_ACMPHS4_BASE          (0x40236400UL + BASE_NS_OFFSET)
20070  #define R_ACMPHS5_BASE          (0x40236500UL + BASE_NS_OFFSET)
20071  #define R_ADC0_BASE             (0x40332000UL + BASE_NS_OFFSET)
20072  #define R_ADC1_BASE             (0x40332200UL + BASE_NS_OFFSET)
20073  #define R_PSCU_BASE             (0x40204000UL + BASE_NS_OFFSET)
20074  #define R_BUS_BASE              (0x40003000UL + BASE_NS_OFFSET)
20075  #define R_CAC_BASE              (0x40202400UL + BASE_NS_OFFSET)
20076  #define R_CANFD_BASE            (0x40380000UL + BASE_NS_OFFSET)
20077  #define R_CANFD1_BASE           (0x40382000UL + BASE_NS_OFFSET)
20078  #define R_CRC_BASE              (0x40310000UL + BASE_NS_OFFSET)
20079  #define R_DAC_BASE              (0x40333000UL + BASE_NS_OFFSET)
20080  #define R_DAC1_BASE             (0x40333100UL + BASE_NS_OFFSET)
20081  #define R_DEBUG_BASE            (0x4001B000UL + BASE_NS_OFFSET)
20082  #define R_DMA_BASE              (0x4000A800UL + BASE_NS_OFFSET)
20083  #define R_DMAC0_BASE            (0x4000A000UL + BASE_NS_OFFSET)
20084  #define R_DMAC1_BASE            (0x4000A040UL + BASE_NS_OFFSET)
20085  #define R_DMAC2_BASE            (0x4000A080UL + BASE_NS_OFFSET)
20086  #define R_DMAC3_BASE            (0x4000A0C0UL + BASE_NS_OFFSET)
20087  #define R_DMAC4_BASE            (0x4000A100UL + BASE_NS_OFFSET)
20088  #define R_DMAC5_BASE            (0x4000A140UL + BASE_NS_OFFSET)
20089  #define R_DMAC6_BASE            (0x4000A180UL + BASE_NS_OFFSET)
20090  #define R_DMAC7_BASE            (0x4000A1C0UL + BASE_NS_OFFSET)
20091  #define R_DOC_BASE              (0x40311000UL + BASE_NS_OFFSET)
20092  #define R_DTC_BASE              (0x4000AC00UL + BASE_NS_OFFSET)
20093  #define R_ELC_BASE              (0x40201000UL + BASE_NS_OFFSET)
20094  #define R_ETHERC0_BASE          (0x40354100UL + BASE_NS_OFFSET)
20095  #define R_ETHERC_EDMAC_BASE     (0x40354000UL + BASE_NS_OFFSET)
20096  #define R_FACI_HP_CMD_BASE      (0x40100000UL + BASE_NS_OFFSET)
20097  #define R_FACI_HP_BASE          (0x4011E000UL + BASE_NS_OFFSET)
20098  #define R_FCACHE_BASE           (0x4001C100UL + BASE_NS_OFFSET)
20099  #define R_GPT0_BASE             (0x40322000UL + BASE_NS_OFFSET)
20100  #define R_GPT1_BASE             (0x40322100UL + BASE_NS_OFFSET)
20101  #define R_GPT2_BASE             (0x40322200UL + BASE_NS_OFFSET)
20102  #define R_GPT3_BASE             (0x40322300UL + BASE_NS_OFFSET)
20103  #define R_GPT4_BASE             (0x40322400UL + BASE_NS_OFFSET)
20104  #define R_GPT5_BASE             (0x40322500UL + BASE_NS_OFFSET)
20105  #define R_GPT6_BASE             (0x40322600UL + BASE_NS_OFFSET)
20106  #define R_GPT7_BASE             (0x40322700UL + BASE_NS_OFFSET)
20107  #define R_GPT8_BASE             (0x40322800UL + BASE_NS_OFFSET)
20108  #define R_GPT9_BASE             (0x40322900UL + BASE_NS_OFFSET)
20109  #define R_GPT10_BASE            (0x40322A00UL + BASE_NS_OFFSET)
20110  #define R_GPT11_BASE            (0x40322B00UL + BASE_NS_OFFSET)
20111  #define R_GPT12_BASE            (0x40322C00UL + BASE_NS_OFFSET)
20112  #define R_GPT13_BASE            (0x40322D00UL + BASE_NS_OFFSET)
20113  #define R_GPT_OPS_BASE          (0x40323F00UL + BASE_NS_OFFSET)
20114  #define R_GPT_POEG0_BASE        (0x40212000UL + BASE_NS_OFFSET)
20115  #define R_GPT_POEG1_BASE        (0x40212100UL + BASE_NS_OFFSET)
20116  #define R_GPT_POEG2_BASE        (0x40212200UL + BASE_NS_OFFSET)
20117  #define R_GPT_POEG3_BASE        (0x40212300UL + BASE_NS_OFFSET)
20118  #define R_ICU_BASE              (0x40006000UL + BASE_NS_OFFSET)
20119  #define R_IIC0_BASE             (0x4025E000UL + BASE_NS_OFFSET)
20120  #define R_IIC1_BASE             (0x4025E100UL + BASE_NS_OFFSET)
20121  #define R_IIC2_BASE             (0x4025E200UL + BASE_NS_OFFSET)
20122  #define R_IWDT_BASE             (0x40202200UL + BASE_NS_OFFSET)
20123  #define R_I3C0_BASE             (0x4035F000UL + BASE_NS_OFFSET)
20124  #define R_I3C1_BASE             (0x4035F100UL + BASE_NS_OFFSET)
20125  #define R_MPU_MMPU_BASE         (0x40000000UL + BASE_NS_OFFSET)
20126  #define R_MPU_SPMON_BASE        (0x40000D00UL + BASE_NS_OFFSET)
20127  #define R_MSTP_BASE             (0x40203000UL + BASE_NS_OFFSET)
20128  #define R_PORT0_BASE            (0x40400000UL + BASE_NS_OFFSET)
20129  #define R_PORT1_BASE            (0x40400020UL + BASE_NS_OFFSET)
20130  #define R_PORT2_BASE            (0x40400040UL + BASE_NS_OFFSET)
20131  #define R_PORT3_BASE            (0x40400060UL + BASE_NS_OFFSET)
20132  #define R_PORT4_BASE            (0x40400080UL + BASE_NS_OFFSET)
20133  #define R_PORT5_BASE            (0x404000A0UL + BASE_NS_OFFSET)
20134  #define R_PORT6_BASE            (0x404000C0UL + BASE_NS_OFFSET)
20135  #define R_PORT7_BASE            (0x404000E0UL + BASE_NS_OFFSET)
20136  #define R_PORT8_BASE            (0x40400100UL + BASE_NS_OFFSET)
20137  #define R_PORT9_BASE            (0x40400120UL + BASE_NS_OFFSET)
20138  #define R_PORT10_BASE           (0x40400140UL + BASE_NS_OFFSET)
20139  #define R_PORT11_BASE           (0x40400160UL + BASE_NS_OFFSET)
20140  #define R_PORT12_BASE           (0x40400180UL + BASE_NS_OFFSET)
20141  #define R_PORT13_BASE           (0x404001A0UL + BASE_NS_OFFSET)
20142  #define R_PORT14_BASE           (0x404001C0UL + BASE_NS_OFFSET)
20143  #define R_PFS_BASE              (0x40400800UL + BASE_NS_OFFSET)
20144  #define R_PMISC_BASE            (0x40400D00UL + BASE_NS_OFFSET)
20145  #define R_RTC_BASE              (0x40202000UL + BASE_NS_OFFSET)
20146  #define R_SCI0_BASE             (0x40358000UL + BASE_NS_OFFSET)
20147  #define R_SCI1_BASE             (0x40358100UL + BASE_NS_OFFSET)
20148  #define R_SCI2_BASE             (0x40358200UL + BASE_NS_OFFSET)
20149  #define R_SCI3_BASE             (0x40358300UL + BASE_NS_OFFSET)
20150  #define R_SCI4_BASE             (0x40358400UL + BASE_NS_OFFSET)
20151  #define R_SCI5_BASE             (0x40358500UL + BASE_NS_OFFSET)
20152  #define R_SCI6_BASE             (0x40358600UL + BASE_NS_OFFSET)
20153  #define R_SCI7_BASE             (0x40358700UL + BASE_NS_OFFSET)
20154  #define R_SCI8_BASE             (0x40358800UL + BASE_NS_OFFSET)
20155  #define R_SCI9_BASE             (0x40358900UL + BASE_NS_OFFSET)
20156  #define R_SDHI0_BASE            (0x40252000UL + BASE_NS_OFFSET)
20157  #define R_SDHI1_BASE            (0x40252400UL + BASE_NS_OFFSET)
20158  #define R_SPI0_BASE             (0x4035C000UL + BASE_NS_OFFSET)
20159  #define R_SPI1_BASE             (0x4035C100UL + BASE_NS_OFFSET)
20160  #define R_SRAM_BASE             (0x40002000UL + BASE_NS_OFFSET)
20161  #define R_SSI0_BASE             (0x4025D000UL + BASE_NS_OFFSET)
20162  #define R_SSI1_BASE             (0x4025D100UL + BASE_NS_OFFSET)
20163  #define R_SYSTEM_BASE           (0x4001E000UL + BASE_NS_OFFSET)
20164  #define R_TSN_CAL_BASE          (0x4011B17CUL + BASE_NS_OFFSET)
20165  #define R_TSN_CTRL_BASE         (0x40235000UL + BASE_NS_OFFSET)
20166  #define R_USB_FS0_BASE          (0x40250000UL + BASE_NS_OFFSET)
20167  #define R_WDT_BASE              (0x40202600UL + BASE_NS_OFFSET)
20168  #define R_TZF_BASE              (0x40004000UL + BASE_NS_OFFSET)
20169  #define R_CPSCU_BASE            (0x40008000UL + BASE_NS_OFFSET)
20170  #define R_DOC_B_BASE            (0x40311000UL + BASE_NS_OFFSET)
20171  #define R_SCI_B0_BASE           (0x40358000UL + BASE_NS_OFFSET)
20172  #define R_SCI_B1_BASE           (0x40358100UL + BASE_NS_OFFSET)
20173  #define R_SCI_B2_BASE           (0x40358200UL + BASE_NS_OFFSET)
20174  #define R_SCI_B3_BASE           (0x40358300UL + BASE_NS_OFFSET)
20175  #define R_SCI_B4_BASE           (0x40358400UL + BASE_NS_OFFSET)
20176  #define R_SCI_B9_BASE           (0x40358900UL + BASE_NS_OFFSET)
20177  #define R_SPI_B0_BASE           (0x4035C000UL + BASE_NS_OFFSET)
20178  #define R_SPI_B1_BASE           (0x4035C100UL + BASE_NS_OFFSET)
20179  #define R_XSPI_BASE             (0x40268000UL + BASE_NS_OFFSET)
20180  #define R_ULPT0_BASE            (0x40220000UL + BASE_NS_OFFSET)
20181  #define R_ULPT1_BASE            (0x40220100UL + BASE_NS_OFFSET)
20182  #define R_DEBUG_OCD_BASE        (0x40011000UL + BASE_NS_OFFSET)
20183  #define R_AGTX0_BASE            (0x40221000UL + BASE_NS_OFFSET)
20184  #define R_AGTX1_BASE            (0x40221100UL + BASE_NS_OFFSET)
20185  #define R_AGTX2_BASE            (0x40221200UL + BASE_NS_OFFSET)
20186  #define R_AGTX3_BASE            (0x40221300UL + BASE_NS_OFFSET)
20187  #define R_AGTX4_BASE            (0x40221400UL + BASE_NS_OFFSET)
20188  #define R_AGTX5_BASE            (0x40221500UL + BASE_NS_OFFSET)
20189  #define R_AGTX6_BASE            (0x40221600UL + BASE_NS_OFFSET)
20190  #define R_AGTX7_BASE            (0x40221700UL + BASE_NS_OFFSET)
20191  #define R_AGTX8_BASE            (0x40221800UL + BASE_NS_OFFSET)
20192  #define R_AGTX9_BASE            (0x40221900UL + BASE_NS_OFFSET)
20193  #define R_FLAD_BASE             (0x4011C000UL + BASE_NS_OFFSET)
20194  #define R_OFS_DATAFLASH_BASE    (0x27030000UL + BASE_NS_OFFSET)
20195 
20196 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
20197 
20198 /* =========================================================================================================================== */
20199 /* ================                                  Peripheral declaration                                   ================ */
20200 /* =========================================================================================================================== */
20201 
20202 /** @addtogroup Device_Peripheral_declaration
20203  * @{
20204  */
20205 
20206  #define R_ACMPHS0          ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
20207  #define R_ACMPHS1          ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
20208  #define R_ACMPHS2          ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
20209  #define R_ACMPHS3          ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
20210  #define R_ACMPHS4          ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
20211  #define R_ACMPHS5          ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
20212  #define R_ADC0             ((R_ADC0_Type *) R_ADC0_BASE)
20213  #define R_ADC1             ((R_ADC0_Type *) R_ADC1_BASE)
20214  #define R_PSCU             ((R_PSCU_Type *) R_PSCU_BASE)
20215  #define R_BUS              ((R_BUS_Type *) R_BUS_BASE)
20216  #define R_CAC              ((R_CAC_Type *) R_CAC_BASE)
20217  #define R_CANFD            ((R_CANFD_Type *) R_CANFD_BASE)
20218  #define R_CANFD0           ((R_CANFD_Type *) R_CANFD_BASE)
20219  #define R_CANFD1           ((R_CANFD_Type *) R_CANFD1_BASE)
20220  #define R_CRC              ((R_CRC_Type *) R_CRC_BASE)
20221  #define R_DAC              ((R_DAC_Type *) R_DAC_BASE)
20222  #define R_DAC1             ((R_DAC_Type *) R_DAC1_BASE)
20223  #define R_DEBUG            ((R_DEBUG_Type *) R_DEBUG_BASE)
20224  #define R_DMA              ((R_DMA_Type *) R_DMA_BASE)
20225  #define R_DMAC0            ((R_DMAC0_Type *) R_DMAC0_BASE)
20226  #define R_DMAC1            ((R_DMAC0_Type *) R_DMAC1_BASE)
20227  #define R_DMAC2            ((R_DMAC0_Type *) R_DMAC2_BASE)
20228  #define R_DMAC3            ((R_DMAC0_Type *) R_DMAC3_BASE)
20229  #define R_DMAC4            ((R_DMAC0_Type *) R_DMAC4_BASE)
20230  #define R_DMAC5            ((R_DMAC0_Type *) R_DMAC5_BASE)
20231  #define R_DMAC6            ((R_DMAC0_Type *) R_DMAC6_BASE)
20232  #define R_DMAC7            ((R_DMAC0_Type *) R_DMAC7_BASE)
20233  #define R_DOC              ((R_DOC_Type *) R_DOC_BASE)
20234  #define R_DTC              ((R_DTC_Type *) R_DTC_BASE)
20235  #define R_ELC              ((R_ELC_Type *) R_ELC_BASE)
20236  #define R_ETHERC0          ((R_ETHERC0_Type *) R_ETHERC0_BASE)
20237  #define R_ETHERC_EDMAC     ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
20238  #define R_FACI_HP_CMD      ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
20239  #define R_FACI_HP          ((R_FACI_HP_Type *) R_FACI_HP_BASE)
20240  #define R_FCACHE           ((R_FCACHE_Type *) R_FCACHE_BASE)
20241  #define R_GPT0             ((R_GPT0_Type *) R_GPT0_BASE)
20242  #define R_GPT1             ((R_GPT0_Type *) R_GPT1_BASE)
20243  #define R_GPT2             ((R_GPT0_Type *) R_GPT2_BASE)
20244  #define R_GPT3             ((R_GPT0_Type *) R_GPT3_BASE)
20245  #define R_GPT4             ((R_GPT0_Type *) R_GPT4_BASE)
20246  #define R_GPT5             ((R_GPT0_Type *) R_GPT5_BASE)
20247  #define R_GPT6             ((R_GPT0_Type *) R_GPT6_BASE)
20248  #define R_GPT7             ((R_GPT0_Type *) R_GPT7_BASE)
20249  #define R_GPT8             ((R_GPT0_Type *) R_GPT8_BASE)
20250  #define R_GPT9             ((R_GPT0_Type *) R_GPT9_BASE)
20251  #define R_GPT10            ((R_GPT0_Type *) R_GPT10_BASE)
20252  #define R_GPT11            ((R_GPT0_Type *) R_GPT11_BASE)
20253  #define R_GPT12            ((R_GPT0_Type *) R_GPT12_BASE)
20254  #define R_GPT13            ((R_GPT0_Type *) R_GPT13_BASE)
20255  #define R_GPT_OPS          ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
20256  #define R_GPT_POEG0        ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
20257  #define R_GPT_POEG1        ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
20258  #define R_GPT_POEG2        ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
20259  #define R_GPT_POEG3        ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
20260  #define R_ICU              ((R_ICU_Type *) R_ICU_BASE)
20261  #define R_IIC0             ((R_IIC0_Type *) R_IIC0_BASE)
20262  #define R_IIC1             ((R_IIC0_Type *) R_IIC1_BASE)
20263  #define R_IIC2             ((R_IIC0_Type *) R_IIC2_BASE)
20264  #define R_IWDT             ((R_IWDT_Type *) R_IWDT_BASE)
20265  #define R_I3C0             ((R_I3C0_Type *) R_I3C0_BASE)
20266  #define R_I3C1             ((R_I3C0_Type *) R_I3C1_BASE)
20267  #define R_MPU_MMPU         ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
20268  #define R_MPU_SPMON        ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
20269  #define R_MSTP             ((R_MSTP_Type *) R_MSTP_BASE)
20270  #define R_PORT0            ((R_PORT0_Type *) R_PORT0_BASE)
20271  #define R_PORT1            ((R_PORT0_Type *) R_PORT1_BASE)
20272  #define R_PORT2            ((R_PORT0_Type *) R_PORT2_BASE)
20273  #define R_PORT3            ((R_PORT0_Type *) R_PORT3_BASE)
20274  #define R_PORT4            ((R_PORT0_Type *) R_PORT4_BASE)
20275  #define R_PORT5            ((R_PORT0_Type *) R_PORT5_BASE)
20276  #define R_PORT6            ((R_PORT0_Type *) R_PORT6_BASE)
20277  #define R_PORT7            ((R_PORT0_Type *) R_PORT7_BASE)
20278  #define R_PORT8            ((R_PORT0_Type *) R_PORT8_BASE)
20279  #define R_PORT9            ((R_PORT0_Type *) R_PORT9_BASE)
20280  #define R_PORT10           ((R_PORT0_Type *) R_PORT10_BASE)
20281  #define R_PORT11           ((R_PORT0_Type *) R_PORT11_BASE)
20282  #define R_PORT12           ((R_PORT0_Type *) R_PORT12_BASE)
20283  #define R_PORT13           ((R_PORT0_Type *) R_PORT13_BASE)
20284  #define R_PORT14           ((R_PORT0_Type *) R_PORT14_BASE)
20285  #define R_PFS              ((R_PFS_Type *) R_PFS_BASE)
20286  #define R_PMISC            ((R_PMISC_Type *) R_PMISC_BASE)
20287  #define R_RTC              ((R_RTC_Type *) R_RTC_BASE)
20288  #define R_SCI0             ((R_SCI0_Type *) R_SCI0_BASE)
20289  #define R_SCI1             ((R_SCI0_Type *) R_SCI1_BASE)
20290  #define R_SCI2             ((R_SCI0_Type *) R_SCI2_BASE)
20291  #define R_SCI3             ((R_SCI0_Type *) R_SCI3_BASE)
20292  #define R_SCI4             ((R_SCI0_Type *) R_SCI4_BASE)
20293  #define R_SCI5             ((R_SCI0_Type *) R_SCI5_BASE)
20294  #define R_SCI6             ((R_SCI0_Type *) R_SCI6_BASE)
20295  #define R_SCI7             ((R_SCI0_Type *) R_SCI7_BASE)
20296  #define R_SCI8             ((R_SCI0_Type *) R_SCI8_BASE)
20297  #define R_SCI9             ((R_SCI0_Type *) R_SCI9_BASE)
20298  #define R_SDHI0            ((R_SDHI0_Type *) R_SDHI0_BASE)
20299  #define R_SDHI1            ((R_SDHI0_Type *) R_SDHI1_BASE)
20300  #define R_SPI0             ((R_SPI0_Type *) R_SPI0_BASE)
20301  #define R_SPI1             ((R_SPI0_Type *) R_SPI1_BASE)
20302  #define R_SRAM             ((R_SRAM_Type *) R_SRAM_BASE)
20303  #define R_SSI0             ((R_SSI0_Type *) R_SSI0_BASE)
20304  #define R_SSI1             ((R_SSI0_Type *) R_SSI1_BASE)
20305  #define R_SYSTEM           ((R_SYSTEM_Type *) R_SYSTEM_BASE)
20306  #define R_TSN_CAL          ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
20307  #define R_TSN_CTRL         ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
20308  #define R_USB_FS0          ((R_USB_FS0_Type *) R_USB_FS0_BASE)
20309  #define R_WDT              ((R_WDT_Type *) R_WDT_BASE)
20310  #define R_TZF              ((R_TZF_Type *) R_TZF_BASE)
20311  #define R_CPSCU            ((R_CPSCU_Type *) R_CPSCU_BASE)
20312  #define R_DOC_B            ((R_DOC_B_Type *) R_DOC_B_BASE)
20313  #define R_SCI_B0           ((R_SCI_B0_Type *) R_SCI_B0_BASE)
20314  #define R_SCI_B1           ((R_SCI_B0_Type *) R_SCI_B1_BASE)
20315  #define R_SCI_B2           ((R_SCI_B0_Type *) R_SCI_B2_BASE)
20316  #define R_SCI_B3           ((R_SCI_B0_Type *) R_SCI_B3_BASE)
20317  #define R_SCI_B4           ((R_SCI_B0_Type *) R_SCI_B4_BASE)
20318  #define R_SCI_B9           ((R_SCI_B0_Type *) R_SCI_B9_BASE)
20319  #define R_SPI_B0           ((R_SPI_B0_Type *) R_SPI_B0_BASE)
20320  #define R_SPI_B1           ((R_SPI_B0_Type *) R_SPI_B1_BASE)
20321  #define R_XSPI             ((R_XSPI_Type *) R_XSPI_BASE)
20322  #define R_ULPT0            ((R_ULPT0_Type *) R_ULPT0_BASE)
20323  #define R_ULPT1            ((R_ULPT0_Type *) R_ULPT1_BASE)
20324  #define R_DEBUG_OCD        ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE)
20325  #define R_AGT0             ((R_AGTX0_Type *) R_AGTX0_BASE)
20326  #define R_AGT1             ((R_AGTX0_Type *) R_AGTX1_BASE)
20327  #define R_AGT2             ((R_AGTX0_Type *) R_AGTX2_BASE)
20328  #define R_AGT3             ((R_AGTX0_Type *) R_AGTX3_BASE)
20329  #define R_AGT4             ((R_AGTX0_Type *) R_AGTX4_BASE)
20330  #define R_AGT5             ((R_AGTX0_Type *) R_AGTX5_BASE)
20331  #define R_AGT6             ((R_AGTX0_Type *) R_AGTX6_BASE)
20332  #define R_AGT7             ((R_AGTX0_Type *) R_AGTX7_BASE)
20333  #define R_AGT8             ((R_AGTX0_Type *) R_AGTX8_BASE)
20334  #define R_AGT9             ((R_AGTX0_Type *) R_AGTX9_BASE)
20335  #define R_FLAD             ((R_FLAD_Type *) R_FLAD_BASE)
20336  #define R_OFS_DATAFLASH    ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE)
20337 
20338 /** @} */ /* End of group Device_Peripheral_declaration */
20339 
20340 /* =========================================  End of section using anonymous unions  ========================================= */
20341  #if defined(__CC_ARM)
20342   #pragma pop
20343  #elif defined(__ICCARM__)
20344 
20345 /* leave anonymous unions enabled */
20346  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
20347   #pragma clang diagnostic pop
20348  #elif defined(__GNUC__)
20349 
20350 /* anonymous unions are enabled by default */
20351  #elif defined(__TMS470__)
20352 
20353 /* anonymous unions are enabled by default */
20354  #elif defined(__TASKING__)
20355   #pragma warning restore
20356  #elif defined(__CSMC__)
20357 
20358 /* anonymous unions are enabled by default */
20359  #endif
20360 
20361 /* =========================================================================================================================== */
20362 /* ================                                 Pos/Mask Cluster Section                                  ================ */
20363 /* =========================================================================================================================== */
20364 
20365 /** @addtogroup PosMask_clusters
20366  * @{
20367  */
20368 
20369 /* =========================================================================================================================== */
20370 /* ================                                            CSa                                            ================ */
20371 /* =========================================================================================================================== */
20372 
20373 /* ==========================================================  MOD  ========================================================== */
20374  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
20375  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
20376  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
20377  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
20378  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
20379  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
20380  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
20381  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
20382  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
20383  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
20384 /* =========================================================  WCR1  ========================================================== */
20385  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
20386  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
20387  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
20388  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
20389  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
20390  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
20391  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
20392  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
20393 /* =========================================================  WCR2  ========================================================== */
20394  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
20395  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
20396  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
20397  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
20398  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
20399  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
20400  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
20401  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
20402  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
20403  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
20404  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
20405  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
20406  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
20407  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
20408  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
20409  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
20410 
20411 /* =========================================================================================================================== */
20412 /* ================                                            CSb                                            ================ */
20413 /* =========================================================================================================================== */
20414 
20415 /* ==========================================================  CR  =========================================================== */
20416  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
20417  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
20418  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
20419  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
20420  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
20421  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
20422  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
20423  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
20424 /* ==========================================================  REC  ========================================================== */
20425  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
20426  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
20427  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
20428  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
20429 
20430 /* =========================================================================================================================== */
20431 /* ================                                           SDRAM                                           ================ */
20432 /* =========================================================================================================================== */
20433 
20434 /* =========================================================  SDCCR  ========================================================= */
20435  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
20436  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
20437  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
20438  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
20439 /* ========================================================  SDCMOD  ========================================================= */
20440  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
20441  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
20442 /* ========================================================  SDAMOD  ========================================================= */
20443  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
20444  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
20445 /* ========================================================  SDSELF  ========================================================= */
20446  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
20447  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
20448 /* ========================================================  SDRFCR  ========================================================= */
20449  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
20450  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
20451  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
20452  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
20453 /* ========================================================  SDRFEN  ========================================================= */
20454  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
20455  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
20456 /* =========================================================  SDICR  ========================================================= */
20457  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
20458  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
20459 /* =========================================================  SDIR  ========================================================== */
20460  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
20461  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
20462  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
20463  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
20464  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
20465  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
20466 /* =========================================================  SDADR  ========================================================= */
20467  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
20468  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
20469 /* =========================================================  SDTR  ========================================================== */
20470  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
20471  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
20472  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
20473  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
20474  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
20475  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
20476  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
20477  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
20478  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
20479  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
20480 /* =========================================================  SDMOD  ========================================================= */
20481  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
20482  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
20483 /* =========================================================  SDSR  ========================================================== */
20484  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
20485  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
20486  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
20487  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
20488  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
20489  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
20490 
20491 /* =========================================================================================================================== */
20492 /* ================                                          BUSERRa                                          ================ */
20493 /* =========================================================================================================================== */
20494 
20495 /* ==========================================================  ADD  ========================================================== */
20496  #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
20497  #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
20498 /* =========================================================  STAT  ========================================================== */
20499  #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
20500  #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
20501  #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
20502  #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
20503 /* ==========================================================  RW  =========================================================== */
20504  #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
20505  #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
20506 
20507 /* =========================================================================================================================== */
20508 /* ================                                          BTZFERR                                          ================ */
20509 /* =========================================================================================================================== */
20510 
20511 /* ==========================================================  ADD  ========================================================== */
20512  #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
20513  #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
20514 /* ==========================================================  RW  =========================================================== */
20515  #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
20516  #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
20517 
20518 /* =========================================================================================================================== */
20519 /* ================                                          BUSERRb                                          ================ */
20520 /* =========================================================================================================================== */
20521 
20522 /* =========================================================  STAT  ========================================================== */
20523  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
20524  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
20525  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
20526  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
20527  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
20528  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
20529  #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
20530  #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
20531  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
20532  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
20533 /* ==========================================================  CLR  ========================================================== */
20534  #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
20535  #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
20536  #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
20537  #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
20538  #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
20539  #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
20540  #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
20541  #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
20542  #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
20543  #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
20544 
20545 /* =========================================================================================================================== */
20546 /* ================                                        DMACDTCERR                                         ================ */
20547 /* =========================================================================================================================== */
20548 
20549 /* =========================================================  STAT  ========================================================== */
20550  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
20551  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
20552 /* ==========================================================  CLR  ========================================================== */
20553  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
20554  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
20555 
20556 /* =========================================================================================================================== */
20557 /* ================                                         BUSSABT0                                          ================ */
20558 /* =========================================================================================================================== */
20559 
20560 /* =========================================================  FLBI  ========================================================== */
20561  #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20562  #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20563 /* ========================================================  MRE0BI  ========================================================= */
20564  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
20565  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20566 /* =========================================================  S0BI  ========================================================== */
20567  #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20568  #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20569 /* =========================================================  S1BI  ========================================================== */
20570  #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20571  #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20572 /* =========================================================  S2BI  ========================================================== */
20573  #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20574  #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20575 /* =========================================================  S3BI  ========================================================== */
20576  #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20577  #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20578 /* ========================================================  STBYSBI  ======================================================== */
20579  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20580  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20581 /* =========================================================  ECBI  ========================================================== */
20582  #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20583  #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20584 /* =========================================================  EOBI  ========================================================== */
20585  #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20586  #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20587 /* ========================================================  SPI0BI  ========================================================= */
20588  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
20589  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20590 /* ========================================================  SPI1BI  ========================================================= */
20591  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
20592  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20593 /* =========================================================  PBBI  ========================================================== */
20594  #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20595  #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20596 /* =========================================================  PABI  ========================================================== */
20597  #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20598  #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20599 /* =========================================================  PIBI  ========================================================== */
20600  #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20601  #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20602 /* =========================================================  PSBI  ========================================================== */
20603  #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
20604  #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20605 /* =======================================================  CPU0SAHBI  ======================================================= */
20606  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
20607  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20608 /* =======================================================  CPU1TCMBI  ======================================================= */
20609  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
20610  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
20611 
20612 /* =========================================================================================================================== */
20613 /* ================                                         BUSSABT1                                          ================ */
20614 /* =========================================================================================================================== */
20615 
20616 /* =========================================================  FHBI  ========================================================== */
20617  #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20618  #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20619 /* ========================================================  MRC0BI  ========================================================= */
20620  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
20621  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20622 /* =========================================================  S0BI  ========================================================== */
20623  #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20624  #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20625 /* =========================================================  S1BI  ========================================================== */
20626  #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
20627  #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
20628 
20629 /* =========================================================================================================================== */
20630 /* ================                                          BMSAERR                                          ================ */
20631 /* =========================================================================================================================== */
20632 
20633 /* ==========================================================  ADD  ========================================================== */
20634  #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
20635  #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
20636 /* ==========================================================  RW  =========================================================== */
20637  #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
20638  #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */
20639 
20640 /* =========================================================================================================================== */
20641 /* ================                                            OAD                                            ================ */
20642 /* =========================================================================================================================== */
20643 
20644 /* ========================================================  BUSOAD  ========================================================= */
20645  #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
20646  #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
20647  #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
20648  #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
20649  #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
20650  #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
20651 /* =======================================================  BUSOADPT  ======================================================== */
20652  #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
20653  #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20654  #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
20655  #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20656 /* ========================================================  MSAOAD  ========================================================= */
20657  #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
20658  #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20659  #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
20660  #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
20661 /* =========================================================  MSAPT  ========================================================= */
20662  #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
20663  #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20664  #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
20665  #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20666 
20667 /* =========================================================================================================================== */
20668 /* ================                                          MBWERR                                           ================ */
20669 /* =========================================================================================================================== */
20670 
20671 /* =========================================================  STAT  ========================================================== */
20672  #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
20673  #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
20674 /* ==========================================================  CLR  ========================================================== */
20675  #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
20676  #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
20677 
20678 /* =========================================================================================================================== */
20679 /* ================                                           BUSM                                            ================ */
20680 /* =========================================================================================================================== */
20681 
20682 /* ==========================================================  CNT  ========================================================== */
20683  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
20684  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
20685 
20686 /* =========================================================================================================================== */
20687 /* ================                                           BUSS                                            ================ */
20688 /* =========================================================================================================================== */
20689 
20690 /* ==========================================================  CNT  ========================================================== */
20691  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
20692  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
20693  #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
20694  #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */
20695 
20696 /* =========================================================================================================================== */
20697 /* ================                                           CFDC                                            ================ */
20698 /* =========================================================================================================================== */
20699 
20700 /* =========================================================  NCFG  ========================================================== */
20701  #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
20702  #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
20703  #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
20704  #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
20705  #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
20706  #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
20707  #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
20708  #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
20709 /* ==========================================================  CTR  ========================================================== */
20710  #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
20711  #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
20712  #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
20713  #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
20714  #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
20715  #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
20716  #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
20717  #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
20718  #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
20719  #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
20720  #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
20721  #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
20722  #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
20723  #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
20724  #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
20725  #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
20726  #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
20727  #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
20728  #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
20729  #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
20730  #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
20731  #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
20732  #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
20733  #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
20734  #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
20735  #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
20736  #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
20737  #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
20738  #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
20739  #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
20740  #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
20741  #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
20742  #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
20743  #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
20744  #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
20745  #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
20746  #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
20747  #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
20748  #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
20749  #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
20750  #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
20751  #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
20752 /* ==========================================================  STS  ========================================================== */
20753  #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
20754  #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
20755  #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
20756  #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
20757  #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
20758  #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
20759  #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
20760  #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
20761  #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
20762  #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
20763  #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
20764  #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
20765  #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
20766  #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
20767  #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
20768  #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
20769  #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
20770  #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
20771  #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
20772  #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
20773  #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
20774  #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
20775 /* =========================================================  ERFL  ========================================================== */
20776  #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
20777  #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
20778  #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
20779  #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
20780  #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
20781  #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
20782  #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
20783  #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
20784  #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
20785  #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
20786  #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
20787  #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
20788  #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
20789  #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
20790  #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
20791  #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
20792  #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
20793  #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
20794  #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
20795  #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
20796  #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
20797  #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
20798  #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
20799  #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
20800  #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
20801  #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
20802  #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
20803  #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
20804  #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
20805  #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
20806  #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
20807  #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
20808 
20809 /* =========================================================================================================================== */
20810 /* ================                                           CFDC2                                           ================ */
20811 /* =========================================================================================================================== */
20812 
20813 /* =========================================================  DCFG  ========================================================== */
20814  #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
20815  #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
20816  #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
20817  #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
20818  #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
20819  #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
20820  #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
20821  #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
20822 /* =========================================================  FDCFG  ========================================================= */
20823  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
20824  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
20825  #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
20826  #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
20827  #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
20828  #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
20829  #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
20830  #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
20831  #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
20832  #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
20833  #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
20834  #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
20835  #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
20836  #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
20837  #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
20838  #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
20839 /* =========================================================  FDCTR  ========================================================= */
20840  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
20841  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
20842  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
20843  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
20844 /* =========================================================  FDSTS  ========================================================= */
20845  #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
20846  #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
20847  #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
20848  #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
20849  #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
20850  #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
20851  #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
20852  #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
20853  #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
20854  #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
20855  #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
20856  #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
20857 /* =========================================================  FDCRC  ========================================================= */
20858  #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
20859  #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
20860  #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
20861  #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
20862 
20863 /* =========================================================================================================================== */
20864 /* ================                                          CFDGAFL                                          ================ */
20865 /* =========================================================================================================================== */
20866 
20867 /* ==========================================================  ID  =========================================================== */
20868  #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
20869  #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
20870  #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
20871  #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
20872  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
20873  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
20874  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
20875  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
20876 /* ===========================================================  M  =========================================================== */
20877  #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
20878  #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
20879  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
20880  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
20881  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
20882  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
20883  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
20884  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
20885 /* ==========================================================  P0  =========================================================== */
20886  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
20887  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
20888  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
20889  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
20890  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
20891  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
20892  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
20893  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
20894  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
20895  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
20896 /* ==========================================================  P1  =========================================================== */
20897  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
20898  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */
20899 
20900 /* =========================================================================================================================== */
20901 /* ================                                          CFDTHL                                           ================ */
20902 /* =========================================================================================================================== */
20903 
20904 /* =========================================================  ACC0  ========================================================== */
20905  #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
20906  #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
20907  #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
20908  #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
20909  #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
20910  #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
20911 /* =========================================================  ACC1  ========================================================== */
20912  #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
20913  #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
20914  #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
20915  #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
20916 
20917 /* =========================================================================================================================== */
20918 /* ================                                           CFDRF                                           ================ */
20919 /* =========================================================================================================================== */
20920 
20921 /* ==========================================================  ID  =========================================================== */
20922  #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
20923  #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
20924  #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
20925  #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
20926  #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
20927  #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
20928 /* ==========================================================  PTR  ========================================================== */
20929  #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
20930  #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
20931  #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
20932  #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
20933 /* =========================================================  FDSTS  ========================================================= */
20934  #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
20935  #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
20936  #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
20937  #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
20938  #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
20939  #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
20940  #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
20941  #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
20942  #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
20943  #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
20944 /* ==========================================================  DF  =========================================================== */
20945  #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
20946  #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
20947 
20948 /* =========================================================================================================================== */
20949 /* ================                                           CFDCF                                           ================ */
20950 /* =========================================================================================================================== */
20951 
20952 /* ==========================================================  ID  =========================================================== */
20953  #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
20954  #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
20955  #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
20956  #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
20957  #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
20958  #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
20959 /* ==========================================================  PTR  ========================================================== */
20960  #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
20961  #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
20962  #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
20963  #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
20964 /* =========================================================  FDSTS  ========================================================= */
20965  #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
20966  #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
20967  #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
20968  #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
20969  #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
20970  #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
20971  #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
20972  #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
20973  #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
20974  #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
20975 /* ==========================================================  DF  =========================================================== */
20976  #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
20977  #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
20978 
20979 /* =========================================================================================================================== */
20980 /* ================                                           CFDTM                                           ================ */
20981 /* =========================================================================================================================== */
20982 
20983 /* ==========================================================  ID  =========================================================== */
20984  #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
20985  #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
20986  #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
20987  #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
20988  #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
20989  #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
20990 /* ==========================================================  PTR  ========================================================== */
20991  #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
20992  #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
20993  #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
20994  #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
20995 /* =========================================================  FDCTR  ========================================================= */
20996  #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
20997  #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
20998  #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
20999  #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
21000  #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
21001  #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
21002  #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
21003  #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
21004  #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
21005  #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
21006 /* ==========================================================  DF  =========================================================== */
21007  #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
21008  #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
21009 
21010 /* =========================================================================================================================== */
21011 /* ================                                            RM                                             ================ */
21012 /* =========================================================================================================================== */
21013 
21014 /* ==========================================================  ID  =========================================================== */
21015  #define R_CANFD_CFDRM_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
21016  #define R_CANFD_CFDRM_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
21017  #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
21018  #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
21019  #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
21020  #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
21021 /* ==========================================================  PTR  ========================================================== */
21022  #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
21023  #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
21024  #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
21025  #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
21026 /* =========================================================  FDSTS  ========================================================= */
21027  #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
21028  #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
21029  #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
21030  #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
21031  #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
21032  #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
21033  #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
21034  #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
21035  #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
21036  #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
21037 /* ==========================================================  DF  =========================================================== */
21038  #define R_CANFD_CFDRM_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
21039  #define R_CANFD_CFDRM_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
21040 
21041 /* =========================================================================================================================== */
21042 /* ================                                           CFDRM                                           ================ */
21043 /* =========================================================================================================================== */
21044 
21045 /* =========================================================================================================================== */
21046 /* ================                                          ELSEGR                                           ================ */
21047 /* =========================================================================================================================== */
21048 
21049 /* ==========================================================  BY  =========================================================== */
21050  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
21051  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
21052  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
21053  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
21054  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
21055  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
21056 
21057 /* =========================================================================================================================== */
21058 /* ================                                           ELSR                                            ================ */
21059 /* =========================================================================================================================== */
21060 
21061 /* ==========================================================  HA  =========================================================== */
21062  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
21063  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
21064 
21065 /* =========================================================================================================================== */
21066 /* ================                                            SAR                                            ================ */
21067 /* =========================================================================================================================== */
21068 
21069 /* ===========================================================  L  =========================================================== */
21070  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
21071  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
21072 /* ===========================================================  U  =========================================================== */
21073  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
21074  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
21075  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
21076  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
21077  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
21078  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
21079 
21080 /* =========================================================================================================================== */
21081 /* ================                                          REGION                                           ================ */
21082 /* =========================================================================================================================== */
21083 
21084 /* ==========================================================  AC  =========================================================== */
21085  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos        (3UL)          /*!< PP (Bit 3)                                            */
21086  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk        (0x8UL)        /*!< PP (Bitfield-Mask: 0x01)                              */
21087  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
21088  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
21089  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
21090  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
21091  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
21092  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
21093 /* ===========================================================  S  =========================================================== */
21094  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
21095  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
21096 /* ===========================================================  E  =========================================================== */
21097  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
21098  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */
21099 
21100 /* =========================================================================================================================== */
21101 /* ================                                           GROUP                                           ================ */
21102 /* =========================================================================================================================== */
21103 
21104 /* ==========================================================  EN  =========================================================== */
21105  #define R_MPU_MMPU_GROUP_EN_KEY_Pos             (8UL)      /*!< KEY (Bit 8)                                           */
21106  #define R_MPU_MMPU_GROUP_EN_KEY_Msk             (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
21107  #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos          (0UL)      /*!< ENABLE (Bit 0)                                        */
21108  #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk          (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
21109 /* =========================================================  ENPT  ========================================================== */
21110  #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
21111  #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
21112  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
21113  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
21114 /* ==========================================================  RPT  ========================================================== */
21115  #define R_MPU_MMPU_GROUP_RPT_KEY_Pos            (8UL)      /*!< KEY (Bit 8)                                           */
21116  #define R_MPU_MMPU_GROUP_RPT_KEY_Msk            (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
21117  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos        (0UL)      /*!< PROTECT (Bit 0)                                       */
21118  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk        (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
21119 /* ========================================================  RPT_SEC  ======================================================== */
21120  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
21121  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
21122  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
21123  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
21124 
21125 /* =========================================================================================================================== */
21126 /* ================                                            SP                                             ================ */
21127 /* =========================================================================================================================== */
21128 
21129 /* ==========================================================  OAD  ========================================================== */
21130  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
21131  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
21132  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
21133  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
21134 /* ==========================================================  CTL  ========================================================== */
21135  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
21136  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
21137  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
21138  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
21139 /* ==========================================================  PT  =========================================================== */
21140  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
21141  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
21142  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
21143  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
21144 /* ==========================================================  SA  =========================================================== */
21145  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
21146  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
21147 /* ==========================================================  EA  =========================================================== */
21148  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
21149  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
21150 
21151 /* =========================================================================================================================== */
21152 /* ================                                            PIN                                            ================ */
21153 /* =========================================================================================================================== */
21154 
21155 /* =======================================================  PmnPFS_BY  ======================================================= */
21156  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
21157  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
21158  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
21159  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
21160  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
21161  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
21162  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
21163  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
21164  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
21165  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
21166 /* =======================================================  PmnPFS_HA  ======================================================= */
21167  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
21168  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
21169  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
21170  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
21171  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
21172  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
21173  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
21174  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
21175  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
21176  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
21177  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
21178  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
21179  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
21180  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
21181  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
21182  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
21183  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
21184  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
21185 /* ========================================================  PmnPFS  ========================================================= */
21186  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
21187  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
21188  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
21189  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
21190  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
21191  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
21192  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
21193  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
21194  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
21195  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
21196  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
21197  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
21198  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
21199  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
21200  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
21201  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
21202  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
21203  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
21204  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
21205  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
21206  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
21207  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
21208 
21209 /* =========================================================================================================================== */
21210 /* ================                                           PORT                                            ================ */
21211 /* =========================================================================================================================== */
21212 
21213 /* =========================================================================================================================== */
21214 /* ================                                           PMSAR                                           ================ */
21215 /* =========================================================================================================================== */
21216 
21217 /* =========================================================  PMSAR  ========================================================= */
21218 
21219 /* =========================================================================================================================== */
21220 /* ================                                           RTCCR                                           ================ */
21221 /* =========================================================================================================================== */
21222 
21223 /* =========================================================  RTCCR  ========================================================= */
21224  #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
21225  #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
21226  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
21227  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
21228  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
21229  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
21230  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
21231  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
21232 
21233 /* =========================================================================================================================== */
21234 /* ================                                            CP                                             ================ */
21235 /* =========================================================================================================================== */
21236 
21237 /* =========================================================  RSEC  ========================================================== */
21238  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
21239  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
21240  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
21241  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
21242 /* =========================================================  BCNT0  ========================================================= */
21243  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
21244  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
21245 /* =========================================================  RMIN  ========================================================== */
21246  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
21247  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
21248  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
21249  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
21250 /* =========================================================  BCNT1  ========================================================= */
21251  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
21252  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
21253 /* ==========================================================  RHR  ========================================================== */
21254  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
21255  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
21256  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
21257  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
21258  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
21259  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
21260 /* =========================================================  BCNT2  ========================================================= */
21261  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
21262  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
21263 /* =========================================================  RDAY  ========================================================== */
21264  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
21265  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
21266  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
21267  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
21268 /* =========================================================  BCNT3  ========================================================= */
21269  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
21270  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
21271 /* =========================================================  RMON  ========================================================== */
21272  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
21273  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
21274  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
21275  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
21276 
21277 /* =========================================================================================================================== */
21278 /* ================                                          PIPE_TR                                          ================ */
21279 /* =========================================================================================================================== */
21280 
21281 /* ===========================================================  E  =========================================================== */
21282  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
21283  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
21284  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
21285  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
21286 /* ===========================================================  N  =========================================================== */
21287  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
21288  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
21289 
21290 /* =========================================================================================================================== */
21291 /* ================                                          CMCFGCS                                          ================ */
21292 /* =========================================================================================================================== */
21293 
21294 /* ========================================================  CMCFG0  ========================================================= */
21295  #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Pos       (0UL)          /*!< FFMT (Bit 0)                                          */
21296  #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Msk       (0x3UL)        /*!< FFMT (Bitfield-Mask: 0x03)                            */
21297  #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Pos    (2UL)          /*!< ADDSIZE (Bit 2)                                       */
21298  #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Msk    (0xcUL)        /*!< ADDSIZE (Bitfield-Mask: 0x03)                         */
21299  #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Pos    (4UL)          /*!< WPBSTMD (Bit 4)                                       */
21300  #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Msk    (0x10UL)       /*!< WPBSTMD (Bitfield-Mask: 0x01)                         */
21301  #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Pos     (5UL)          /*!< ARYAMD (Bit 5)                                        */
21302  #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Msk     (0x20UL)       /*!< ARYAMD (Bitfield-Mask: 0x01)                          */
21303  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Pos    (16UL)         /*!< ADDRPEN (Bit 16)                                      */
21304  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Msk    (0xff0000UL)   /*!< ADDRPEN (Bitfield-Mask: 0xff)                         */
21305  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Pos    (24UL)         /*!< ADDRPCD (Bit 24)                                      */
21306  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Msk    (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff)                         */
21307 /* ========================================================  CMCFG1  ========================================================= */
21308  #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Pos      (0UL)          /*!< RDCMD (Bit 0)                                         */
21309  #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Msk      (0xffffUL)     /*!< RDCMD (Bitfield-Mask: 0xffff)                         */
21310  #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Pos     (16UL)         /*!< RDLATE (Bit 16)                                       */
21311  #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Msk     (0x1f0000UL)   /*!< RDLATE (Bitfield-Mask: 0x1f)                          */
21312 /* ========================================================  CMCFG2  ========================================================= */
21313  #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Pos      (0UL)          /*!< WRCMD (Bit 0)                                         */
21314  #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Msk      (0xffffUL)     /*!< WRCMD (Bitfield-Mask: 0xffff)                         */
21315  #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Pos     (16UL)         /*!< WRLATE (Bit 16)                                       */
21316  #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Msk     (0x1f0000UL)   /*!< WRLATE (Bitfield-Mask: 0x1f)                          */
21317 
21318 /* =========================================================================================================================== */
21319 /* ================                                           CDBUF                                           ================ */
21320 /* =========================================================================================================================== */
21321 
21322 /* ==========================================================  CDT  ========================================================== */
21323  #define R_XSPI_CDBUF_CDT_CMDSIZE_Pos     (0UL)          /*!< CMDSIZE (Bit 0)                                       */
21324  #define R_XSPI_CDBUF_CDT_CMDSIZE_Msk     (0x3UL)        /*!< CMDSIZE (Bitfield-Mask: 0x03)                         */
21325  #define R_XSPI_CDBUF_CDT_ADDSIZE_Pos     (2UL)          /*!< ADDSIZE (Bit 2)                                       */
21326  #define R_XSPI_CDBUF_CDT_ADDSIZE_Msk     (0x1cUL)       /*!< ADDSIZE (Bitfield-Mask: 0x07)                         */
21327  #define R_XSPI_CDBUF_CDT_DATASIZE_Pos    (5UL)          /*!< DATASIZE (Bit 5)                                      */
21328  #define R_XSPI_CDBUF_CDT_DATASIZE_Msk    (0x1e0UL)      /*!< DATASIZE (Bitfield-Mask: 0x0f)                        */
21329  #define R_XSPI_CDBUF_CDT_LATE_Pos        (9UL)          /*!< LATE (Bit 9)                                          */
21330  #define R_XSPI_CDBUF_CDT_LATE_Msk        (0x3e00UL)     /*!< LATE (Bitfield-Mask: 0x1f)                            */
21331  #define R_XSPI_CDBUF_CDT_TRTYPE_Pos      (15UL)         /*!< TRTYPE (Bit 15)                                       */
21332  #define R_XSPI_CDBUF_CDT_TRTYPE_Msk      (0x8000UL)     /*!< TRTYPE (Bitfield-Mask: 0x01)                          */
21333  #define R_XSPI_CDBUF_CDT_CMD_Pos         (16UL)         /*!< CMD (Bit 16)                                          */
21334  #define R_XSPI_CDBUF_CDT_CMD_Msk         (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff)                           */
21335 /* ==========================================================  CDA  ========================================================== */
21336  #define R_XSPI_CDBUF_CDA_ADD_Pos         (0UL)          /*!< ADD (Bit 0)                                           */
21337  #define R_XSPI_CDBUF_CDA_ADD_Msk         (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff)                       */
21338 /* =========================================================  CDD0  ========================================================== */
21339  #define R_XSPI_CDBUF_CDD0_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
21340  #define R_XSPI_CDBUF_CDD0_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
21341 /* =========================================================  CDD1  ========================================================== */
21342  #define R_XSPI_CDBUF_CDD1_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
21343  #define R_XSPI_CDBUF_CDD1_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
21344 
21345 /* =========================================================================================================================== */
21346 /* ================                                          CCCTLCS                                          ================ */
21347 /* =========================================================================================================================== */
21348 
21349 /* ========================================================  CCCTL0  ========================================================= */
21350  #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Pos          (0UL)          /*!< CAEN (Bit 0)                                          */
21351  #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Msk          (0x1UL)        /*!< CAEN (Bitfield-Mask: 0x01)                            */
21352  #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Pos        (1UL)          /*!< CANOWR (Bit 1)                                        */
21353  #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Msk        (0x2UL)        /*!< CANOWR (Bitfield-Mask: 0x01)                          */
21354  #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Pos         (8UL)          /*!< CAITV (Bit 8)                                         */
21355  #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Msk         (0x1f00UL)     /*!< CAITV (Bitfield-Mask: 0x1f)                           */
21356  #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Pos      (16UL)         /*!< CASFTSTA (Bit 16)                                     */
21357  #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Msk      (0x1f0000UL)   /*!< CASFTSTA (Bitfield-Mask: 0x1f)                        */
21358  #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Pos      (24UL)         /*!< CASFTEND (Bit 24)                                     */
21359  #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Msk      (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f)                        */
21360 /* ========================================================  CCCTL1  ========================================================= */
21361  #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Pos     (0UL)          /*!< CACMDSIZE (Bit 0)                                     */
21362  #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Msk     (0x3UL)        /*!< CACMDSIZE (Bitfield-Mask: 0x03)                       */
21363  #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Pos     (2UL)          /*!< CAADDSIZE (Bit 2)                                     */
21364  #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Msk     (0x1cUL)       /*!< CAADDSIZE (Bitfield-Mask: 0x07)                       */
21365  #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Pos    (5UL)          /*!< CADATASIZE (Bit 5)                                    */
21366  #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Msk    (0x1e0UL)      /*!< CADATASIZE (Bitfield-Mask: 0x0f)                      */
21367  #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Pos      (16UL)         /*!< CAWRLATE (Bit 16)                                     */
21368  #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Msk      (0x1f0000UL)   /*!< CAWRLATE (Bitfield-Mask: 0x1f)                        */
21369  #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Pos      (24UL)         /*!< CARDLATE (Bit 24)                                     */
21370  #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Msk      (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f)                        */
21371 /* ========================================================  CCCTL2  ========================================================= */
21372  #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Pos       (0UL)          /*!< CAWRCMD (Bit 0)                                       */
21373  #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Msk       (0xffffUL)     /*!< CAWRCMD (Bitfield-Mask: 0xffff)                       */
21374  #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Pos       (16UL)         /*!< CARDCMD (Bit 16)                                      */
21375  #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Msk       (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff)                       */
21376 /* ========================================================  CCCTL3  ========================================================= */
21377  #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Pos         (0UL)          /*!< CAADD (Bit 0)                                         */
21378  #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Msk         (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff)                     */
21379 /* ========================================================  CCCTL4  ========================================================= */
21380  #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
21381  #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
21382 /* ========================================================  CCCTL5  ========================================================= */
21383  #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
21384  #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
21385 /* ========================================================  CCCTL6  ========================================================= */
21386  #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
21387  #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
21388 /* ========================================================  CCCTL7  ========================================================= */
21389  #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
21390  #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
21391 
21392 /* =========================================================================================================================== */
21393 /* ================                                           CTRL                                            ================ */
21394 /* =========================================================================================================================== */
21395 
21396 /* =========================================================  AGTCR  ========================================================= */
21397  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
21398  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
21399  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
21400  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
21401  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
21402  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
21403  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
21404  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
21405  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
21406  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
21407  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
21408  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
21409  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
21410  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
21411 /* ========================================================  AGTMR1  ========================================================= */
21412  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
21413  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
21414  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
21415  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
21416  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
21417  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
21418 /* ========================================================  AGTMR2  ========================================================= */
21419  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
21420  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
21421  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
21422  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
21423 /* =====================================================  AGTIOSEL_ALT  ====================================================== */
21424  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
21425  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
21426  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
21427  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
21428 /* ========================================================  AGTIOC  ========================================================= */
21429  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
21430  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
21431  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
21432  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
21433  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
21434  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
21435  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
21436  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
21437 /* ========================================================  AGTISR  ========================================================= */
21438  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
21439  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
21440 /* ========================================================  AGTCMSR  ======================================================== */
21441  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
21442  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
21443  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
21444  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
21445  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
21446  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
21447  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
21448  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
21449  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
21450  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
21451  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
21452  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
21453 /* =======================================================  AGTIOSEL  ======================================================== */
21454  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
21455  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
21456  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
21457  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
21458 
21459 /* =========================================================================================================================== */
21460 /* ================                                           AGT16                                           ================ */
21461 /* =========================================================================================================================== */
21462 
21463 /* ==========================================================  AGT  ========================================================== */
21464  #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
21465  #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
21466 /* ========================================================  AGTCMA  ========================================================= */
21467  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
21468  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
21469 /* ========================================================  AGTCMB  ========================================================= */
21470  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
21471  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
21472 
21473 /* =========================================================================================================================== */
21474 /* ================                                           AGT32                                           ================ */
21475 /* =========================================================================================================================== */
21476 
21477 /* ==========================================================  AGT  ========================================================== */
21478  #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
21479  #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
21480 /* ========================================================  AGTCMA  ========================================================= */
21481  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
21482  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
21483 /* ========================================================  AGTCMB  ========================================================= */
21484  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
21485  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
21486 
21487 /* =========================================================================================================================== */
21488 /* ================                                           CFGD                                            ================ */
21489 /* =========================================================================================================================== */
21490 
21491 /* ========================================================  CFGD_L  ========================================================= */
21492  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Pos    (0UL)   /*!< CDLK (Bit 0)                                          */
21493  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Msk    (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01)                            */
21494 /* ========================================================  CFGD_H  ========================================================= */
21495  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Pos    (0UL)   /*!< CDLK (Bit 0)                                          */
21496  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Msk    (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01)                            */
21497 
21498 /* =========================================================================================================================== */
21499 /* ================                                         CFGDLOCK                                          ================ */
21500 /* =========================================================================================================================== */
21501 
21502 /* =========================================================  CFGD2  ========================================================= */
21503  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Pos    (0UL)   /*!< CDLK (Bit 0)                                          */
21504  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Msk    (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01)                            */
21505 
21506 /** @} */ /* End of group PosMask_clusters */
21507 
21508 /* =========================================================================================================================== */
21509 /* ================                                Pos/Mask Peripheral Section                                ================ */
21510 /* =========================================================================================================================== */
21511 
21512 /** @addtogroup PosMask_peripherals
21513  * @{
21514  */
21515 
21516 /* =========================================================================================================================== */
21517 /* ================                                         R_ACMPHS0                                         ================ */
21518 /* =========================================================================================================================== */
21519 
21520 /* ========================================================  CMPCTL  ========================================================= */
21521  #define R_ACMPHS0_CMPCTL_HCMPON_Pos     (7UL)    /*!< HCMPON (Bit 7)                                        */
21522  #define R_ACMPHS0_CMPCTL_HCMPON_Msk     (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01)                          */
21523  #define R_ACMPHS0_CMPCTL_CDFS_Pos       (5UL)    /*!< CDFS (Bit 5)                                          */
21524  #define R_ACMPHS0_CMPCTL_CDFS_Msk       (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03)                            */
21525  #define R_ACMPHS0_CMPCTL_CEG_Pos        (3UL)    /*!< CEG (Bit 3)                                           */
21526  #define R_ACMPHS0_CMPCTL_CEG_Msk        (0x18UL) /*!< CEG (Bitfield-Mask: 0x03)                             */
21527  #define R_ACMPHS0_CMPCTL_CSTEN_Pos      (2UL)    /*!< CSTEN (Bit 2)                                         */
21528  #define R_ACMPHS0_CMPCTL_CSTEN_Msk      (0x4UL)  /*!< CSTEN (Bitfield-Mask: 0x01)                           */
21529  #define R_ACMPHS0_CMPCTL_COE_Pos        (1UL)    /*!< COE (Bit 1)                                           */
21530  #define R_ACMPHS0_CMPCTL_COE_Msk        (0x2UL)  /*!< COE (Bitfield-Mask: 0x01)                             */
21531  #define R_ACMPHS0_CMPCTL_CINV_Pos       (0UL)    /*!< CINV (Bit 0)                                          */
21532  #define R_ACMPHS0_CMPCTL_CINV_Msk       (0x1UL)  /*!< CINV (Bitfield-Mask: 0x01)                            */
21533 /* ========================================================  CMPSEL0  ======================================================== */
21534  #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos    (0UL)    /*!< CMPSEL (Bit 0)                                        */
21535  #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk    (0xfUL)  /*!< CMPSEL (Bitfield-Mask: 0x0f)                          */
21536 /* ========================================================  CMPSEL1  ======================================================== */
21537  #define R_ACMPHS0_CMPSEL1_CRVS_Pos      (0UL)    /*!< CRVS (Bit 0)                                          */
21538  #define R_ACMPHS0_CMPSEL1_CRVS_Msk      (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f)                            */
21539 /* ========================================================  CMPMON  ========================================================= */
21540  #define R_ACMPHS0_CMPMON_CMPMON_Pos     (0UL)    /*!< CMPMON (Bit 0)                                        */
21541  #define R_ACMPHS0_CMPMON_CMPMON_Msk     (0x1UL)  /*!< CMPMON (Bitfield-Mask: 0x01)                          */
21542 /* =========================================================  CPIOC  ========================================================= */
21543  #define R_ACMPHS0_CPIOC_VREFEN_Pos      (7UL)    /*!< VREFEN (Bit 7)                                        */
21544  #define R_ACMPHS0_CPIOC_VREFEN_Msk      (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01)                          */
21545  #define R_ACMPHS0_CPIOC_CPOE_Pos        (0UL)    /*!< CPOE (Bit 0)                                          */
21546  #define R_ACMPHS0_CPIOC_CPOE_Msk        (0x1UL)  /*!< CPOE (Bitfield-Mask: 0x01)                            */
21547 
21548 /* =========================================================================================================================== */
21549 /* ================                                          R_ADC0                                           ================ */
21550 /* =========================================================================================================================== */
21551 
21552 /* =========================================================  ADCSR  ========================================================= */
21553  #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
21554  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
21555  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
21556  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
21557  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
21558  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
21559  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
21560  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
21561  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
21562  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
21563  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
21564  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
21565  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
21566  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
21567  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
21568  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
21569  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
21570  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
21571 /* ========================================================  ADANSA  ========================================================= */
21572  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
21573  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
21574 /* =========================================================  ADADS  ========================================================= */
21575  #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
21576  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
21577 /* =========================================================  ADADC  ========================================================= */
21578  #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
21579  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
21580  #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
21581  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
21582 /* =========================================================  ADCER  ========================================================= */
21583  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
21584  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
21585  #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
21586  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
21587  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
21588  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
21589  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
21590  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
21591  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
21592  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
21593  #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
21594  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
21595  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
21596  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
21597  #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
21598  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
21599 /* ========================================================  ADSTRGR  ======================================================== */
21600  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
21601  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
21602  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
21603  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
21604 /* ========================================================  ADEXICR  ======================================================== */
21605  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
21606  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
21607  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
21608  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
21609  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
21610  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
21611  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
21612  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
21613  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
21614  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
21615  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
21616  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
21617  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
21618  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
21619  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
21620  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
21621 /* ========================================================  ADANSB  ========================================================= */
21622  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
21623  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
21624 /* ========================================================  ADDBLDR  ======================================================== */
21625  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
21626  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
21627 /* ========================================================  ADTSDR  ========================================================= */
21628  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
21629  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
21630 /* ========================================================  ADOCDR  ========================================================= */
21631  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
21632  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
21633 /* ======================================================  ADRD_RIGHT  ======================================================= */
21634  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
21635  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
21636  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
21637  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
21638 /* =======================================================  ADRD_LEFT  ======================================================= */
21639  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
21640  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
21641  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
21642  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
21643 /* =========================================================  ADDR  ========================================================== */
21644  #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
21645  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
21646 /* ========================================================  ADSHCR  ========================================================= */
21647  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
21648  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
21649  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
21650  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
21651  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
21652  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
21653  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
21654  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
21655 /* ========================================================  ADDISCR  ======================================================== */
21656  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
21657  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
21658  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
21659  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
21660 /* ========================================================  ADSHMSR  ======================================================== */
21661  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
21662  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
21663 /* ========================================================  ADACSR  ========================================================= */
21664  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
21665  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
21666 /* ========================================================  ADGSPCR  ======================================================== */
21667  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
21668  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
21669  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
21670  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
21671  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
21672  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
21673  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
21674  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
21675 /* =========================================================  ADICR  ========================================================= */
21676  #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
21677  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
21678 /* =======================================================  ADDBLDRA  ======================================================== */
21679  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
21680  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
21681 /* =======================================================  ADDBLDRB  ======================================================== */
21682  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
21683  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
21684 /* ======================================================  ADHVREFCNT  ======================================================= */
21685  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
21686  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
21687  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
21688  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
21689  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
21690  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
21691 /* =======================================================  ADWINMON  ======================================================== */
21692  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
21693  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
21694  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
21695  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
21696  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
21697  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
21698 /* ========================================================  ADCMPCR  ======================================================== */
21699  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
21700  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
21701  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
21702  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
21703  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
21704  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
21705  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
21706  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
21707  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
21708  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
21709  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
21710  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
21711 /* ======================================================  ADCMPANSER  ======================================================= */
21712  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
21713  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
21714  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
21715  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
21716 /* =======================================================  ADCMPLER  ======================================================== */
21717  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
21718  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
21719  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
21720  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
21721 /* =======================================================  ADCMPANSR  ======================================================= */
21722  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
21723  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
21724 /* ========================================================  ADCMPLR  ======================================================== */
21725  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
21726  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
21727 /* =======================================================  ADCMPDR0  ======================================================== */
21728  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
21729  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
21730 /* =======================================================  ADCMPDR1  ======================================================== */
21731  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
21732  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
21733 /* ========================================================  ADCMPSR  ======================================================== */
21734  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
21735  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
21736 /* =======================================================  ADCMPSER  ======================================================== */
21737  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
21738  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
21739  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
21740  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
21741 /* =======================================================  ADCMPBNSR  ======================================================= */
21742  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
21743  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
21744  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
21745  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
21746 /* =======================================================  ADWINLLB  ======================================================== */
21747  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
21748  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
21749 /* =======================================================  ADWINULB  ======================================================== */
21750  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
21751  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
21752 /* =======================================================  ADCMPBSR  ======================================================== */
21753  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
21754  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
21755 /* ========================================================  ADSSTRL  ======================================================== */
21756  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
21757  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21758 /* ========================================================  ADSSTRT  ======================================================== */
21759  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
21760  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21761 /* ========================================================  ADSSTRO  ======================================================== */
21762  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
21763  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21764 /* ========================================================  ADSSTR  ========================================================= */
21765  #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
21766  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
21767 /* ========================================================  ADPGACR  ======================================================== */
21768  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
21769  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
21770  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
21771  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
21772  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
21773  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
21774  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
21775  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
21776  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
21777  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
21778  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
21779  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
21780  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
21781  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
21782  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
21783  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
21784  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
21785  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
21786  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
21787  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
21788  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
21789  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
21790  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
21791  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
21792  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
21793  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
21794  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
21795  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
21796  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
21797  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
21798  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
21799  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
21800 /* =========================================================  ADRD  ========================================================== */
21801  #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
21802  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
21803 /* =========================================================  ADRST  ========================================================= */
21804  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
21805  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
21806 /* ======================================================  VREFAMPCNT  ======================================================= */
21807  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
21808  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
21809  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
21810  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
21811  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
21812  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
21813  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
21814  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
21815  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
21816  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
21817 /* =======================================================  ADCALEXE  ======================================================== */
21818  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
21819  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
21820  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
21821  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
21822 /* ========================================================  ADANIM  ========================================================= */
21823  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
21824  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
21825 /* =======================================================  ADPGAGS0  ======================================================== */
21826  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
21827  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
21828  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
21829  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
21830  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
21831  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
21832  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
21833  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
21834 /* =======================================================  ADPGADCR0  ======================================================= */
21835  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
21836  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
21837  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
21838  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
21839  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
21840  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
21841  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
21842  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
21843  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
21844  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
21845  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
21846  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
21847  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
21848  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
21849  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
21850  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
21851 /* =========================================================  ADREF  ========================================================= */
21852  #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
21853  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
21854  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
21855  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
21856 /* ========================================================  ADEXREF  ======================================================== */
21857  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
21858  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
21859 /* =======================================================  ADAMPOFF  ======================================================== */
21860  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
21861  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
21862 /* ========================================================  ADTSTPR  ======================================================== */
21863  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
21864  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
21865  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
21866  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
21867 /* =======================================================  ADDDACER  ======================================================== */
21868  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
21869  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
21870  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
21871  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
21872  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
21873  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
21874 /* =======================================================  ADEXTSTR  ======================================================== */
21875  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
21876  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
21877  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
21878  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
21879  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
21880  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
21881  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
21882  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
21883  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
21884  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
21885  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
21886  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
21887 /* ========================================================  ADTSTRA  ======================================================== */
21888  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
21889  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
21890  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
21891  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
21892  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
21893  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
21894  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
21895  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
21896  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
21897  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
21898  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
21899  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
21900 /* ========================================================  ADTSTRB  ======================================================== */
21901  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
21902  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
21903 /* ========================================================  ADTSTRC  ======================================================== */
21904  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
21905  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
21906  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
21907  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
21908 /* ========================================================  ADTSTRD  ======================================================== */
21909  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
21910  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
21911 /* =======================================================  ADSWTSTR0  ======================================================= */
21912  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
21913  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
21914  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
21915  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
21916  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
21917  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
21918  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
21919  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
21920  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
21921  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
21922  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
21923  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
21924 /* =======================================================  ADSWTSTR1  ======================================================= */
21925  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
21926  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
21927  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
21928  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
21929  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
21930  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
21931  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
21932  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
21933  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
21934  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
21935  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
21936  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
21937 /* =======================================================  ADSWTSTR2  ======================================================= */
21938  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
21939  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
21940  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
21941  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
21942  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
21943  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
21944  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
21945  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
21946  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
21947  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
21948  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
21949  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
21950  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
21951  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
21952  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
21953  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
21954  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
21955  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
21956  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
21957  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
21958 /* ========================================================  ADSWCR  ========================================================= */
21959  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
21960  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
21961  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
21962  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
21963 /* ========================================================  ADGSCS  ========================================================= */
21964  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
21965  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
21966  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
21967  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
21968 /* =========================================================  ADSER  ========================================================= */
21969  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
21970  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
21971 /* ========================================================  ADBUF0  ========================================================= */
21972  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21973  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21974 /* ========================================================  ADBUF1  ========================================================= */
21975  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21976  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21977 /* ========================================================  ADBUF2  ========================================================= */
21978  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21979  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21980 /* ========================================================  ADBUF3  ========================================================= */
21981  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21982  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21983 /* ========================================================  ADBUF4  ========================================================= */
21984  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21985  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21986 /* ========================================================  ADBUF5  ========================================================= */
21987  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21988  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21989 /* ========================================================  ADBUF6  ========================================================= */
21990  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21991  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21992 /* ========================================================  ADBUF7  ========================================================= */
21993  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21994  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21995 /* ========================================================  ADBUF8  ========================================================= */
21996  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21997  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21998 /* ========================================================  ADBUF9  ========================================================= */
21999  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
22000  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22001 /* ========================================================  ADBUF10  ======================================================== */
22002  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
22003  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22004 /* ========================================================  ADBUF11  ======================================================== */
22005  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
22006  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22007 /* ========================================================  ADBUF12  ======================================================== */
22008  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
22009  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22010 /* ========================================================  ADBUF13  ======================================================== */
22011  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
22012  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22013 /* ========================================================  ADBUF14  ======================================================== */
22014  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
22015  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22016 /* ========================================================  ADBUF15  ======================================================== */
22017  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
22018  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
22019 /* ========================================================  ADBUFEN  ======================================================== */
22020  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
22021  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
22022 /* =======================================================  ADBUFPTR  ======================================================== */
22023  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
22024  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
22025  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
22026  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
22027 /* =======================================================  ADPGADBS0  ======================================================= */
22028  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
22029  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
22030 /* =======================================================  ADPGADBS1  ======================================================= */
22031  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
22032  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
22033 /* =======================================================  ADREFMON  ======================================================== */
22034  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
22035  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
22036  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
22037  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
22038 
22039 /* =========================================================================================================================== */
22040 /* ================                                          R_PSCU                                           ================ */
22041 /* =========================================================================================================================== */
22042 
22043 /* =========================================================  PSARB  ========================================================= */
22044  #define R_PSCU_PSARB_PSARB4_Pos     (4UL)          /*!< PSARB4 (Bit 4)                                        */
22045  #define R_PSCU_PSARB_PSARB4_Msk     (0x10UL)       /*!< PSARB4 (Bitfield-Mask: 0x01)                          */
22046  #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
22047  #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
22048  #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
22049  #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
22050  #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
22051  #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
22052  #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
22053  #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
22054  #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
22055  #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
22056  #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
22057  #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
22058  #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
22059  #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
22060  #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
22061  #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
22062  #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
22063  #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
22064  #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
22065  #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
22066  #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
22067  #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
22068  #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
22069  #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
22070  #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
22071  #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
22072  #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
22073  #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
22074 /* =========================================================  PSARC  ========================================================= */
22075  #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
22076  #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
22077  #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
22078  #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
22079  #define R_PSCU_PSARC_PSARC7_Pos     (7UL)          /*!< PSARC7 (Bit 7)                                        */
22080  #define R_PSCU_PSARC_PSARC7_Msk     (0x80UL)       /*!< PSARC7 (Bitfield-Mask: 0x01)                          */
22081  #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
22082  #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
22083  #define R_PSCU_PSARC_PSARC11_Pos    (11UL)         /*!< PSARC11 (Bit 11)                                      */
22084  #define R_PSCU_PSARC_PSARC11_Msk    (0x800UL)      /*!< PSARC11 (Bitfield-Mask: 0x01)                         */
22085  #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
22086  #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
22087  #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
22088  #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
22089  #define R_PSCU_PSARC_PSARC15_Pos    (15UL)         /*!< PSARC15 (Bit 15)                                      */
22090  #define R_PSCU_PSARC_PSARC15_Msk    (0x8000UL)     /*!< PSARC15 (Bitfield-Mask: 0x01)                         */
22091  #define R_PSCU_PSARC_PSARC16_Pos    (16UL)         /*!< PSARC16 (Bit 16)                                      */
22092  #define R_PSCU_PSARC_PSARC16_Msk    (0x10000UL)    /*!< PSARC16 (Bitfield-Mask: 0x01)                         */
22093  #define R_PSCU_PSARC_PSARC26_Pos    (26UL)         /*!< PSARC26 (Bit 26)                                      */
22094  #define R_PSCU_PSARC_PSARC26_Msk    (0x4000000UL)  /*!< PSARC26 (Bitfield-Mask: 0x01)                         */
22095  #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
22096  #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
22097  #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
22098  #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
22099 /* =========================================================  PSARD  ========================================================= */
22100  #define R_PSCU_PSARD_PSARD4_Pos     (4UL)          /*!< PSARD4 (Bit 4)                                        */
22101  #define R_PSCU_PSARD_PSARD4_Msk     (0x10UL)       /*!< PSARD4 (Bitfield-Mask: 0x01)                          */
22102  #define R_PSCU_PSARD_PSARD5_Pos     (5UL)          /*!< PSARD5 (Bit 5)                                        */
22103  #define R_PSCU_PSARD_PSARD5_Msk     (0x20UL)       /*!< PSARD5 (Bitfield-Mask: 0x01)                          */
22104  #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
22105  #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
22106  #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
22107  #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
22108  #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
22109  #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
22110  #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
22111  #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
22112  #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
22113  #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
22114  #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
22115  #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
22116  #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
22117  #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
22118  #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
22119  #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
22120  #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
22121  #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
22122  #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
22123  #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
22124 /* =========================================================  PSARE  ========================================================= */
22125  #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
22126  #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
22127  #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
22128  #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
22129  #define R_PSCU_PSARE_PSARE3_Pos     (3UL)          /*!< PSARE3 (Bit 3)                                        */
22130  #define R_PSCU_PSARE_PSARE3_Msk     (0x8UL)        /*!< PSARE3 (Bitfield-Mask: 0x01)                          */
22131  #define R_PSCU_PSARE_PSARE8_Pos     (8UL)          /*!< PSARE8 (Bit 8)                                        */
22132  #define R_PSCU_PSARE_PSARE8_Msk     (0x100UL)      /*!< PSARE8 (Bitfield-Mask: 0x01)                          */
22133  #define R_PSCU_PSARE_PSARE9_Pos     (9UL)          /*!< PSARE9 (Bit 9)                                        */
22134  #define R_PSCU_PSARE_PSARE9_Msk     (0x200UL)      /*!< PSARE9 (Bitfield-Mask: 0x01)                          */
22135  #define R_PSCU_PSARE_PSARE18_Pos    (18UL)         /*!< PSARE18 (Bit 18)                                      */
22136  #define R_PSCU_PSARE_PSARE18_Msk    (0x40000UL)    /*!< PSARE18 (Bitfield-Mask: 0x01)                         */
22137  #define R_PSCU_PSARE_PSARE19_Pos    (19UL)         /*!< PSARE19 (Bit 19)                                      */
22138  #define R_PSCU_PSARE_PSARE19_Msk    (0x80000UL)    /*!< PSARE19 (Bitfield-Mask: 0x01)                         */
22139  #define R_PSCU_PSARE_PSARE20_Pos    (20UL)         /*!< PSARE20 (Bit 20)                                      */
22140  #define R_PSCU_PSARE_PSARE20_Msk    (0x100000UL)   /*!< PSARE20 (Bitfield-Mask: 0x01)                         */
22141  #define R_PSCU_PSARE_PSARE21_Pos    (21UL)         /*!< PSARE21 (Bit 21)                                      */
22142  #define R_PSCU_PSARE_PSARE21_Msk    (0x200000UL)   /*!< PSARE21 (Bitfield-Mask: 0x01)                         */
22143  #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
22144  #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
22145  #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
22146  #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
22147  #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
22148  #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
22149  #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
22150  #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
22151  #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
22152  #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
22153  #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
22154  #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
22155  #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
22156  #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
22157  #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
22158  #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
22159  #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
22160  #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
22161  #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
22162  #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
22163 /* =========================================================  MSSAR  ========================================================= */
22164  #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
22165  #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
22166  #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
22167  #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
22168  #define R_PSCU_MSSAR_MSSAR11_Pos    (11UL)         /*!< MSSAR11 (Bit 11)                                      */
22169  #define R_PSCU_MSSAR_MSSAR11_Msk    (0x800UL)      /*!< MSSAR11 (Bitfield-Mask: 0x01)                         */
22170  #define R_PSCU_MSSAR_MSSAR13_Pos    (13UL)         /*!< MSSAR13 (Bit 13)                                      */
22171  #define R_PSCU_MSSAR_MSSAR13_Msk    (0x2000UL)     /*!< MSSAR13 (Bitfield-Mask: 0x01)                         */
22172  #define R_PSCU_MSSAR_MSSAR15_Pos    (15UL)         /*!< MSSAR15 (Bit 15)                                      */
22173  #define R_PSCU_MSSAR_MSSAR15_Msk    (0x8000UL)     /*!< MSSAR15 (Bitfield-Mask: 0x01)                         */
22174  #define R_PSCU_MSSAR_MSSAR22_Pos    (22UL)         /*!< MSSAR22 (Bit 22)                                      */
22175  #define R_PSCU_MSSAR_MSSAR22_Msk    (0x400000UL)   /*!< MSSAR22 (Bitfield-Mask: 0x01)                         */
22176  #define R_PSCU_MSSAR_MSSAR31_Pos    (31UL)         /*!< MSSAR31 (Bit 31)                                      */
22177  #define R_PSCU_MSSAR_MSSAR31_Msk    (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01)                         */
22178 /* =========================================================  PPARB  ========================================================= */
22179  #define R_PSCU_PPARB_PPARB4_Pos     (4UL)          /*!< PPARB4 (Bit 4)                                        */
22180  #define R_PSCU_PPARB_PPARB4_Msk     (0x10UL)       /*!< PPARB4 (Bitfield-Mask: 0x01)                          */
22181  #define R_PSCU_PPARB_PPARB8_Pos     (8UL)          /*!< PPARB8 (Bit 8)                                        */
22182  #define R_PSCU_PPARB_PPARB8_Msk     (0x100UL)      /*!< PPARB8 (Bitfield-Mask: 0x01)                          */
22183  #define R_PSCU_PPARB_PPARB9_Pos     (9UL)          /*!< PPARB9 (Bit 9)                                        */
22184  #define R_PSCU_PPARB_PPARB9_Msk     (0x200UL)      /*!< PPARB9 (Bitfield-Mask: 0x01)                          */
22185  #define R_PSCU_PPARB_PPARB11_Pos    (11UL)         /*!< PPARB11 (Bit 11)                                      */
22186  #define R_PSCU_PPARB_PPARB11_Msk    (0x800UL)      /*!< PPARB11 (Bitfield-Mask: 0x01)                         */
22187  #define R_PSCU_PPARB_PPARB12_Pos    (12UL)         /*!< PPARB12 (Bit 12)                                      */
22188  #define R_PSCU_PPARB_PPARB12_Msk    (0x1000UL)     /*!< PPARB12 (Bitfield-Mask: 0x01)                         */
22189  #define R_PSCU_PPARB_PPARB15_Pos    (15UL)         /*!< PPARB15 (Bit 15)                                      */
22190  #define R_PSCU_PPARB_PPARB15_Msk    (0x8000UL)     /*!< PPARB15 (Bitfield-Mask: 0x01)                         */
22191  #define R_PSCU_PPARB_PPARB16_Pos    (16UL)         /*!< PPARB16 (Bit 16)                                      */
22192  #define R_PSCU_PPARB_PPARB16_Msk    (0x10000UL)    /*!< PPARB16 (Bitfield-Mask: 0x01)                         */
22193  #define R_PSCU_PPARB_PPARB18_Pos    (18UL)         /*!< PPARB18 (Bit 18)                                      */
22194  #define R_PSCU_PPARB_PPARB18_Msk    (0x40000UL)    /*!< PPARB18 (Bitfield-Mask: 0x01)                         */
22195  #define R_PSCU_PPARB_PPARB19_Pos    (19UL)         /*!< PPARB19 (Bit 19)                                      */
22196  #define R_PSCU_PPARB_PPARB19_Msk    (0x80000UL)    /*!< PPARB19 (Bitfield-Mask: 0x01)                         */
22197  #define R_PSCU_PPARB_PPARB22_Pos    (22UL)         /*!< PPARB22 (Bit 22)                                      */
22198  #define R_PSCU_PPARB_PPARB22_Msk    (0x400000UL)   /*!< PPARB22 (Bitfield-Mask: 0x01)                         */
22199  #define R_PSCU_PPARB_PPARB27_Pos    (27UL)         /*!< PPARB27 (Bit 27)                                      */
22200  #define R_PSCU_PPARB_PPARB27_Msk    (0x8000000UL)  /*!< PPARB27 (Bitfield-Mask: 0x01)                         */
22201  #define R_PSCU_PPARB_PPARB28_Pos    (28UL)         /*!< PPARB28 (Bit 28)                                      */
22202  #define R_PSCU_PPARB_PPARB28_Msk    (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01)                         */
22203  #define R_PSCU_PPARB_PPARB29_Pos    (29UL)         /*!< PPARB29 (Bit 29)                                      */
22204  #define R_PSCU_PPARB_PPARB29_Msk    (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01)                         */
22205  #define R_PSCU_PPARB_PPARB30_Pos    (30UL)         /*!< PPARB30 (Bit 30)                                      */
22206  #define R_PSCU_PPARB_PPARB30_Msk    (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01)                         */
22207  #define R_PSCU_PPARB_PPARB31_Pos    (31UL)         /*!< PPARB31 (Bit 31)                                      */
22208  #define R_PSCU_PPARB_PPARB31_Msk    (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01)                         */
22209 /* =========================================================  PPARC  ========================================================= */
22210  #define R_PSCU_PPARC_PPARC0_Pos     (0UL)          /*!< PPARC0 (Bit 0)                                        */
22211  #define R_PSCU_PPARC_PPARC0_Msk     (0x1UL)        /*!< PPARC0 (Bitfield-Mask: 0x01)                          */
22212  #define R_PSCU_PPARC_PPARC1_Pos     (1UL)          /*!< PPARC1 (Bit 1)                                        */
22213  #define R_PSCU_PPARC_PPARC1_Msk     (0x2UL)        /*!< PPARC1 (Bitfield-Mask: 0x01)                          */
22214  #define R_PSCU_PPARC_PPARC7_Pos     (7UL)          /*!< PPARC7 (Bit 7)                                        */
22215  #define R_PSCU_PPARC_PPARC7_Msk     (0x80UL)       /*!< PPARC7 (Bitfield-Mask: 0x01)                          */
22216  #define R_PSCU_PPARC_PPARC8_Pos     (8UL)          /*!< PPARC8 (Bit 8)                                        */
22217  #define R_PSCU_PPARC_PPARC8_Msk     (0x100UL)      /*!< PPARC8 (Bitfield-Mask: 0x01)                          */
22218  #define R_PSCU_PPARC_PPARC11_Pos    (11UL)         /*!< PPARC11 (Bit 11)                                      */
22219  #define R_PSCU_PPARC_PPARC11_Msk    (0x800UL)      /*!< PPARC11 (Bitfield-Mask: 0x01)                         */
22220  #define R_PSCU_PPARC_PPARC12_Pos    (12UL)         /*!< PPARC12 (Bit 12)                                      */
22221  #define R_PSCU_PPARC_PPARC12_Msk    (0x1000UL)     /*!< PPARC12 (Bitfield-Mask: 0x01)                         */
22222  #define R_PSCU_PPARC_PPARC13_Pos    (13UL)         /*!< PPARC13 (Bit 13)                                      */
22223  #define R_PSCU_PPARC_PPARC13_Msk    (0x2000UL)     /*!< PPARC13 (Bitfield-Mask: 0x01)                         */
22224  #define R_PSCU_PPARC_PPARC15_Pos    (15UL)         /*!< PPARC15 (Bit 15)                                      */
22225  #define R_PSCU_PPARC_PPARC15_Msk    (0x8000UL)     /*!< PPARC15 (Bitfield-Mask: 0x01)                         */
22226  #define R_PSCU_PPARC_PPARC16_Pos    (16UL)         /*!< PPARC16 (Bit 16)                                      */
22227  #define R_PSCU_PPARC_PPARC16_Msk    (0x10000UL)    /*!< PPARC16 (Bitfield-Mask: 0x01)                         */
22228  #define R_PSCU_PPARC_PPARC26_Pos    (26UL)         /*!< PPARC26 (Bit 26)                                      */
22229  #define R_PSCU_PPARC_PPARC26_Msk    (0x4000000UL)  /*!< PPARC26 (Bitfield-Mask: 0x01)                         */
22230  #define R_PSCU_PPARC_PPARC27_Pos    (27UL)         /*!< PPARC27 (Bit 27)                                      */
22231  #define R_PSCU_PPARC_PPARC27_Msk    (0x8000000UL)  /*!< PPARC27 (Bitfield-Mask: 0x01)                         */
22232  #define R_PSCU_PPARC_PPARC31_Pos    (31UL)         /*!< PPARC31 (Bit 31)                                      */
22233  #define R_PSCU_PPARC_PPARC31_Msk    (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01)                         */
22234 /* =========================================================  PPARD  ========================================================= */
22235  #define R_PSCU_PPARD_PPARD4_Pos     (4UL)          /*!< PPARD4 (Bit 4)                                        */
22236  #define R_PSCU_PPARD_PPARD4_Msk     (0x10UL)       /*!< PPARD4 (Bitfield-Mask: 0x01)                          */
22237  #define R_PSCU_PPARD_PPARD5_Pos     (5UL)          /*!< PPARD5 (Bit 5)                                        */
22238  #define R_PSCU_PPARD_PPARD5_Msk     (0x20UL)       /*!< PPARD5 (Bitfield-Mask: 0x01)                          */
22239  #define R_PSCU_PPARD_PPARD11_Pos    (11UL)         /*!< PPARD11 (Bit 11)                                      */
22240  #define R_PSCU_PPARD_PPARD11_Msk    (0x800UL)      /*!< PPARD11 (Bitfield-Mask: 0x01)                         */
22241  #define R_PSCU_PPARD_PPARD12_Pos    (12UL)         /*!< PPARD12 (Bit 12)                                      */
22242  #define R_PSCU_PPARD_PPARD12_Msk    (0x1000UL)     /*!< PPARD12 (Bitfield-Mask: 0x01)                         */
22243  #define R_PSCU_PPARD_PPARD13_Pos    (13UL)         /*!< PPARD13 (Bit 13)                                      */
22244  #define R_PSCU_PPARD_PPARD13_Msk    (0x2000UL)     /*!< PPARD13 (Bitfield-Mask: 0x01)                         */
22245  #define R_PSCU_PPARD_PPARD14_Pos    (14UL)         /*!< PPARD14 (Bit 14)                                      */
22246  #define R_PSCU_PPARD_PPARD14_Msk    (0x4000UL)     /*!< PPARD14 (Bitfield-Mask: 0x01)                         */
22247  #define R_PSCU_PPARD_PPARD15_Pos    (15UL)         /*!< PPARD15 (Bit 15)                                      */
22248  #define R_PSCU_PPARD_PPARD15_Msk    (0x8000UL)     /*!< PPARD15 (Bitfield-Mask: 0x01)                         */
22249  #define R_PSCU_PPARD_PPARD16_Pos    (16UL)         /*!< PPARD16 (Bit 16)                                      */
22250  #define R_PSCU_PPARD_PPARD16_Msk    (0x10000UL)    /*!< PPARD16 (Bitfield-Mask: 0x01)                         */
22251  #define R_PSCU_PPARD_PPARD20_Pos    (20UL)         /*!< PPARD20 (Bit 20)                                      */
22252  #define R_PSCU_PPARD_PPARD20_Msk    (0x100000UL)   /*!< PPARD20 (Bitfield-Mask: 0x01)                         */
22253  #define R_PSCU_PPARD_PPARD22_Pos    (22UL)         /*!< PPARD22 (Bit 22)                                      */
22254  #define R_PSCU_PPARD_PPARD22_Msk    (0x400000UL)   /*!< PPARD22 (Bitfield-Mask: 0x01)                         */
22255  #define R_PSCU_PPARD_PPARD27_Pos    (27UL)         /*!< PPARD27 (Bit 27)                                      */
22256  #define R_PSCU_PPARD_PPARD27_Msk    (0x8000000UL)  /*!< PPARD27 (Bitfield-Mask: 0x01)                         */
22257  #define R_PSCU_PPARD_PPARD28_Pos    (28UL)         /*!< PPARD28 (Bit 28)                                      */
22258  #define R_PSCU_PPARD_PPARD28_Msk    (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01)                         */
22259 /* =========================================================  PPARE  ========================================================= */
22260  #define R_PSCU_PPARE_PPARE1_Pos     (1UL)          /*!< PPARE1 (Bit 1)                                        */
22261  #define R_PSCU_PPARE_PPARE1_Msk     (0x2UL)        /*!< PPARE1 (Bitfield-Mask: 0x01)                          */
22262  #define R_PSCU_PPARE_PPARE2_Pos     (2UL)          /*!< PPARE2 (Bit 2)                                        */
22263  #define R_PSCU_PPARE_PPARE2_Msk     (0x4UL)        /*!< PPARE2 (Bitfield-Mask: 0x01)                          */
22264  #define R_PSCU_PPARE_PPARE3_Pos     (3UL)          /*!< PPARE3 (Bit 3)                                        */
22265  #define R_PSCU_PPARE_PPARE3_Msk     (0x8UL)        /*!< PPARE3 (Bitfield-Mask: 0x01)                          */
22266  #define R_PSCU_PPARE_PPARE8_Pos     (8UL)          /*!< PPARE8 (Bit 8)                                        */
22267  #define R_PSCU_PPARE_PPARE8_Msk     (0x100UL)      /*!< PPARE8 (Bitfield-Mask: 0x01)                          */
22268  #define R_PSCU_PPARE_PPARE9_Pos     (9UL)          /*!< PPARE9 (Bit 9)                                        */
22269  #define R_PSCU_PPARE_PPARE9_Msk     (0x200UL)      /*!< PPARE9 (Bitfield-Mask: 0x01)                          */
22270  #define R_PSCU_PPARE_PPARE18_Pos    (18UL)         /*!< PPARE18 (Bit 18)                                      */
22271  #define R_PSCU_PPARE_PPARE18_Msk    (0x40000UL)    /*!< PPARE18 (Bitfield-Mask: 0x01)                         */
22272  #define R_PSCU_PPARE_PPARE19_Pos    (19UL)         /*!< PPARE19 (Bit 19)                                      */
22273  #define R_PSCU_PPARE_PPARE19_Msk    (0x80000UL)    /*!< PPARE19 (Bitfield-Mask: 0x01)                         */
22274  #define R_PSCU_PPARE_PPARE20_Pos    (20UL)         /*!< PPARE20 (Bit 20)                                      */
22275  #define R_PSCU_PPARE_PPARE20_Msk    (0x100000UL)   /*!< PPARE20 (Bitfield-Mask: 0x01)                         */
22276  #define R_PSCU_PPARE_PPARE21_Pos    (21UL)         /*!< PPARE21 (Bit 21)                                      */
22277  #define R_PSCU_PPARE_PPARE21_Msk    (0x200000UL)   /*!< PPARE21 (Bitfield-Mask: 0x01)                         */
22278  #define R_PSCU_PPARE_PPARE22_Pos    (22UL)         /*!< PPARE22 (Bit 22)                                      */
22279  #define R_PSCU_PPARE_PPARE22_Msk    (0x400000UL)   /*!< PPARE22 (Bitfield-Mask: 0x01)                         */
22280  #define R_PSCU_PPARE_PPARE23_Pos    (23UL)         /*!< PPARE23 (Bit 23)                                      */
22281  #define R_PSCU_PPARE_PPARE23_Msk    (0x800000UL)   /*!< PPARE23 (Bitfield-Mask: 0x01)                         */
22282  #define R_PSCU_PPARE_PPARE24_Pos    (24UL)         /*!< PPARE24 (Bit 24)                                      */
22283  #define R_PSCU_PPARE_PPARE24_Msk    (0x1000000UL)  /*!< PPARE24 (Bitfield-Mask: 0x01)                         */
22284  #define R_PSCU_PPARE_PPARE25_Pos    (25UL)         /*!< PPARE25 (Bit 25)                                      */
22285  #define R_PSCU_PPARE_PPARE25_Msk    (0x2000000UL)  /*!< PPARE25 (Bitfield-Mask: 0x01)                         */
22286  #define R_PSCU_PPARE_PPARE26_Pos    (26UL)         /*!< PPARE26 (Bit 26)                                      */
22287  #define R_PSCU_PPARE_PPARE26_Msk    (0x4000000UL)  /*!< PPARE26 (Bitfield-Mask: 0x01)                         */
22288  #define R_PSCU_PPARE_PPARE27_Pos    (27UL)         /*!< PPARE27 (Bit 27)                                      */
22289  #define R_PSCU_PPARE_PPARE27_Msk    (0x8000000UL)  /*!< PPARE27 (Bitfield-Mask: 0x01)                         */
22290  #define R_PSCU_PPARE_PPARE28_Pos    (28UL)         /*!< PPARE28 (Bit 28)                                      */
22291  #define R_PSCU_PPARE_PPARE28_Msk    (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01)                         */
22292  #define R_PSCU_PPARE_PPARE29_Pos    (29UL)         /*!< PPARE29 (Bit 29)                                      */
22293  #define R_PSCU_PPARE_PPARE29_Msk    (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01)                         */
22294  #define R_PSCU_PPARE_PPARE30_Pos    (30UL)         /*!< PPARE30 (Bit 30)                                      */
22295  #define R_PSCU_PPARE_PPARE30_Msk    (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01)                         */
22296  #define R_PSCU_PPARE_PPARE31_Pos    (31UL)         /*!< PPARE31 (Bit 31)                                      */
22297  #define R_PSCU_PPARE_PPARE31_Msk    (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01)                         */
22298 /* =========================================================  MSPAR  ========================================================= */
22299  #define R_PSCU_MSPAR_MSPAR31_Pos    (31UL)         /*!< MSPAR31 (Bit 31)                                      */
22300  #define R_PSCU_MSPAR_MSPAR31_Msk    (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01)                         */
22301 /* =======================================================  CFSAMONA  ======================================================== */
22302  #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
22303  #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
22304 /* ========================================================  DFSAMON  ======================================================== */
22305  #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
22306  #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
22307 /* ========================================================  DLMMON  ========================================================= */
22308  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
22309  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
22310 
22311 /* =========================================================================================================================== */
22312 /* ================                                           R_BUS                                           ================ */
22313 /* =========================================================================================================================== */
22314 
22315 /* ========================================================  CSRECEN  ======================================================== */
22316  #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
22317  #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
22318  #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
22319  #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
22320 /* ========================================================  BUSMABT  ======================================================== */
22321  #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
22322  #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
22323 /* =======================================================  BUSDIVBYP  ======================================================= */
22324  #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
22325  #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
22326  #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
22327  #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
22328  #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
22329  #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
22330 
22331 /* =========================================================================================================================== */
22332 /* ================                                           R_CAC                                           ================ */
22333 /* =========================================================================================================================== */
22334 
22335 /* =========================================================  CACR0  ========================================================= */
22336  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
22337  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
22338 /* =========================================================  CACR1  ========================================================= */
22339  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
22340  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
22341  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
22342  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
22343  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
22344  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
22345  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
22346  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
22347 /* =========================================================  CACR2  ========================================================= */
22348  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
22349  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
22350  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
22351  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
22352  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
22353  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
22354  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
22355  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
22356 /* =========================================================  CAICR  ========================================================= */
22357  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
22358  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
22359  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
22360  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
22361  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
22362  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
22363  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
22364  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
22365  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
22366  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
22367  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
22368  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
22369 /* =========================================================  CASTR  ========================================================= */
22370  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
22371  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
22372  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
22373  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
22374  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
22375  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
22376 /* ========================================================  CAULVR  ========================================================= */
22377  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
22378  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
22379 /* ========================================================  CALLVR  ========================================================= */
22380  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
22381  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
22382 /* ========================================================  CACNTBR  ======================================================== */
22383  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
22384  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
22385 
22386 /* =========================================================================================================================== */
22387 /* ================                                         R_CANFD0                                          ================ */
22388 /* =========================================================================================================================== */
22389 
22390 /* ========================================================  CFDGCFG  ======================================================== */
22391  #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
22392  #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
22393  #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
22394  #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
22395  #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
22396  #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
22397  #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
22398  #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
22399  #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
22400  #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
22401  #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
22402  #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
22403  #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
22404  #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
22405  #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
22406  #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
22407  #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
22408  #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
22409 /* ========================================================  CFDGCTR  ======================================================== */
22410  #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
22411  #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
22412  #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
22413  #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
22414  #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
22415  #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
22416  #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
22417  #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
22418  #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
22419  #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
22420  #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
22421  #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
22422  #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
22423  #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
22424 /* ========================================================  CFDGSTS  ======================================================== */
22425  #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
22426  #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
22427  #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
22428  #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
22429  #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
22430  #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
22431  #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
22432  #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
22433 /* =======================================================  CFDGERFL  ======================================================== */
22434  #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
22435  #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
22436  #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
22437  #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
22438  #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
22439  #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
22440  #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
22441  #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
22442  #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
22443  #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
22444 /* ========================================================  CFDGTSC  ======================================================== */
22445  #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
22446  #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
22447 /* ======================================================  CFDGAFLECTR  ====================================================== */
22448  #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
22449  #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
22450  #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
22451  #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
22452 /* ======================================================  CFDGAFLCFG0  ====================================================== */
22453  #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
22454  #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
22455  #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
22456  #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
22457 /* ========================================================  CFDRMNB  ======================================================== */
22458  #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
22459  #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
22460  #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
22461  #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
22462 /* =======================================================  CFDRMND0  ======================================================== */
22463  #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
22464  #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
22465 /* =======================================================  CFDRMIEC  ======================================================== */
22466  #define R_CANFD_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
22467  #define R_CANFD_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
22468 /* ========================================================  CFDRFCC  ======================================================== */
22469  #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
22470  #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
22471  #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
22472  #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
22473  #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
22474  #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
22475  #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
22476  #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
22477  #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
22478  #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
22479  #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
22480  #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
22481 /* =======================================================  CFDRFSTS  ======================================================== */
22482  #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
22483  #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
22484  #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
22485  #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
22486  #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
22487  #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
22488  #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
22489  #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
22490  #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
22491  #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
22492 /* =======================================================  CFDRFPCTR  ======================================================= */
22493  #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
22494  #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
22495 /* ========================================================  CFDCFCC  ======================================================== */
22496  #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
22497  #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
22498  #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
22499  #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
22500  #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
22501  #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
22502  #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
22503  #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
22504  #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
22505  #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
22506  #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
22507  #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
22508  #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
22509  #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
22510  #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
22511  #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
22512  #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
22513  #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
22514  #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
22515  #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
22516  #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
22517  #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
22518  #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
22519  #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
22520 /* =======================================================  CFDCFSTS  ======================================================== */
22521  #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
22522  #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
22523  #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
22524  #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
22525  #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
22526  #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
22527  #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
22528  #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
22529  #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
22530  #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
22531  #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
22532  #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
22533 /* =======================================================  CFDCFPCTR  ======================================================= */
22534  #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
22535  #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
22536 /* =======================================================  CFDFESTS  ======================================================== */
22537  #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
22538  #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
22539  #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
22540  #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
22541 /* =======================================================  CFDFFSTS  ======================================================== */
22542  #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
22543  #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
22544  #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
22545  #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
22546 /* =======================================================  CFDFMSTS  ======================================================== */
22547  #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
22548  #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
22549  #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
22550  #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
22551 /* =======================================================  CFDRFISTS  ======================================================= */
22552  #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
22553  #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0x1UL)        /*!< RFXIF (Bitfield-Mask: 0x01)                           */
22554 /* ========================================================  CFDTMC  ========================================================= */
22555  #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
22556  #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
22557  #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
22558  #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
22559  #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
22560  #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
22561 /* =======================================================  CFDTMSTS  ======================================================== */
22562  #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
22563  #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
22564  #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
22565  #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
22566  #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
22567  #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
22568  #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
22569  #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
22570 /* ======================================================  CFDTMTRSTS  ======================================================= */
22571  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
22572  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
22573 /* ======================================================  CFDTMTARSTS  ====================================================== */
22574  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
22575  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
22576 /* ======================================================  CFDTMTCSTS  ======================================================= */
22577  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
22578  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
22579 /* ======================================================  CFDTMTASTS  ======================================================= */
22580  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
22581  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
22582 /* =======================================================  CFDTMIEC  ======================================================== */
22583  #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
22584  #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
22585 /* =======================================================  CFDTXQCC0  ======================================================= */
22586  #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
22587  #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
22588  #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
22589  #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
22590  #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
22591  #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
22592  #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
22593  #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
22594 /* ======================================================  CFDTXQSTS0  ======================================================= */
22595  #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
22596  #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
22597  #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
22598  #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
22599  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
22600  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
22601  #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
22602  #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
22603 /* ======================================================  CFDTXQPCTR0  ====================================================== */
22604  #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
22605  #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
22606 /* =======================================================  CFDTHLCC  ======================================================== */
22607  #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
22608  #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
22609  #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
22610  #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
22611  #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
22612  #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
22613  #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
22614  #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
22615 /* =======================================================  CFDTHLSTS  ======================================================= */
22616  #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
22617  #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
22618  #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
22619  #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
22620  #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
22621  #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
22622  #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
22623  #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
22624  #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
22625  #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
22626 /* ======================================================  CFDTHLPCTR  ======================================================= */
22627  #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
22628  #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
22629 /* =====================================================  CFDGTINTSTS0  ====================================================== */
22630  #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
22631  #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
22632  #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
22633  #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
22634  #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
22635  #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
22636  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
22637  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
22638  #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
22639  #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
22640 /* ======================================================  CFDGTSTCFG  ======================================================= */
22641  #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
22642  #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
22643 /* ======================================================  CFDGTSTCTR  ======================================================= */
22644  #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
22645  #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
22646 /* =======================================================  CFDGFDCFG  ======================================================= */
22647  #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
22648  #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
22649  #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
22650  #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
22651 /* =======================================================  CFDGLOCKK  ======================================================= */
22652  #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
22653  #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
22654 /* =====================================================  CFDGAFLIGNENT  ===================================================== */
22655  #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
22656  #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
22657 /* =====================================================  CFDGAFLIGNCTR  ===================================================== */
22658  #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
22659  #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
22660  #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
22661  #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22662 /* =======================================================  CFDCDTCT  ======================================================== */
22663  #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
22664  #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
22665  #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
22666  #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
22667  #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
22668  #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
22669 /* =======================================================  CFDCDTSTS  ======================================================= */
22670  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
22671  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
22672  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
22673  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
22674  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
22675  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
22676 /* =======================================================  CFDGRSTC  ======================================================== */
22677  #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
22678  #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
22679  #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
22680  #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22681 /* =======================================================  CFDRPGACC  ======================================================= */
22682  #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
22683  #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
22684 
22685 /* =========================================================================================================================== */
22686 /* ================                                           R_CRC                                           ================ */
22687 /* =========================================================================================================================== */
22688 
22689 /* ========================================================  CRCCR0  ========================================================= */
22690  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
22691  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
22692  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
22693  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
22694  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
22695  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
22696 /* ========================================================  CRCCR1  ========================================================= */
22697  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
22698  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
22699  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
22700  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
22701 /* ========================================================  CRCDIR  ========================================================= */
22702  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
22703  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
22704 /* =======================================================  CRCDIR_BY  ======================================================= */
22705  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
22706  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
22707 /* ========================================================  CRCDOR  ========================================================= */
22708  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
22709  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
22710 /* =======================================================  CRCDOR_HA  ======================================================= */
22711  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
22712  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
22713 /* =======================================================  CRCDOR_BY  ======================================================= */
22714  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
22715  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
22716 /* ========================================================  CRCSAR  ========================================================= */
22717  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
22718  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
22719 
22720 /* =========================================================================================================================== */
22721 /* ================                                           R_DAC                                           ================ */
22722 /* =========================================================================================================================== */
22723 
22724 /* =========================================================  DACR  ========================================================== */
22725  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
22726  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
22727  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
22728  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
22729 /* =========================================================  DADR  ========================================================== */
22730  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
22731  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
22732 /* =========================================================  DADPR  ========================================================= */
22733  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
22734  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
22735 /* ========================================================  DAADSCR  ======================================================== */
22736  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
22737  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
22738 /* =======================================================  DAVREFCR  ======================================================== */
22739  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
22740  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
22741 /* =========================================================  DAPC  ========================================================== */
22742  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
22743  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
22744 /* ========================================================  DAAMPCR  ======================================================== */
22745  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
22746  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
22747 /* ========================================================  DAASWCR  ======================================================== */
22748  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
22749  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
22750  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
22751  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
22752 /* ========================================================  DAADUSR  ======================================================== */
22753  #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
22754  #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
22755  #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
22756  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
22757 
22758 /* =========================================================================================================================== */
22759 /* ================                                          R_DEBUG                                          ================ */
22760 /* =========================================================================================================================== */
22761 
22762 /* ========================================================  DBGSTR  ========================================================= */
22763  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
22764  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
22765  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
22766  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
22767 /* =======================================================  DBGSTOPCR  ======================================================= */
22768  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
22769  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
22770  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
22771  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
22772  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
22773  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
22774  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
22775  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
22776  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
22777  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
22778  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
22779  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
22780  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
22781  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
22782  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
22783  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
22784 /* =======================================================  FSBLSTAT  ======================================================== */
22785  #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
22786  #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
22787  #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
22788  #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
22789  #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
22790  #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
22791 
22792 /* =========================================================================================================================== */
22793 /* ================                                           R_DMA                                           ================ */
22794 /* =========================================================================================================================== */
22795 
22796 /* =========================================================  DMAST  ========================================================= */
22797  #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
22798  #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
22799 /* ========================================================  DMECHR  ========================================================= */
22800  #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
22801  #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
22802  #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
22803  #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
22804  #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
22805  #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
22806 /* =========================================================  DELSR  ========================================================= */
22807  #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
22808  #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
22809  #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
22810  #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
22811 
22812 /* =========================================================================================================================== */
22813 /* ================                                          R_DMAC0                                          ================ */
22814 /* =========================================================================================================================== */
22815 
22816 /* =========================================================  DMSAR  ========================================================= */
22817  #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
22818  #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
22819 /* =========================================================  DMDAR  ========================================================= */
22820  #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
22821  #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
22822 /* =========================================================  DMCRA  ========================================================= */
22823  #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
22824  #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
22825  #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
22826  #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
22827 /* =========================================================  DMCRB  ========================================================= */
22828  #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
22829  #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
22830  #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
22831  #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
22832 /* =========================================================  DMTMD  ========================================================= */
22833  #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
22834  #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
22835  #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
22836  #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
22837  #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
22838  #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
22839  #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
22840  #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
22841  #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
22842  #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
22843 /* =========================================================  DMINT  ========================================================= */
22844  #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
22845  #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
22846  #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
22847  #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
22848  #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
22849  #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
22850  #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
22851  #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
22852  #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
22853  #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
22854 /* =========================================================  DMAMD  ========================================================= */
22855  #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
22856  #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
22857  #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
22858  #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
22859  #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
22860  #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
22861  #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
22862  #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
22863  #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
22864  #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
22865  #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
22866  #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
22867 /* =========================================================  DMOFR  ========================================================= */
22868  #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
22869  #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
22870 /* =========================================================  DMCNT  ========================================================= */
22871  #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
22872  #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
22873 /* =========================================================  DMREQ  ========================================================= */
22874  #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
22875  #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
22876  #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
22877  #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
22878 /* =========================================================  DMSTS  ========================================================= */
22879  #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
22880  #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
22881  #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
22882  #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
22883  #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
22884  #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
22885 /* =========================================================  DMSRR  ========================================================= */
22886 /* =========================================================  DMDRR  ========================================================= */
22887 /* =========================================================  DMSBS  ========================================================= */
22888  #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
22889  #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
22890  #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
22891  #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
22892 /* =========================================================  DMDBS  ========================================================= */
22893  #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
22894  #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
22895  #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
22896  #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
22897 /* =========================================================  DMBWR  ========================================================= */
22898  #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
22899  #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
22900 
22901 /* =========================================================================================================================== */
22902 /* ================                                           R_DOC                                           ================ */
22903 /* =========================================================================================================================== */
22904 
22905 /* =========================================================  DOCR  ========================================================== */
22906  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
22907  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
22908  #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
22909  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
22910  #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
22911  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
22912  #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
22913  #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
22914 /* =========================================================  DODIR  ========================================================= */
22915  #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
22916  #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
22917 /* =========================================================  DODSR  ========================================================= */
22918  #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
22919  #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
22920 
22921 /* =========================================================================================================================== */
22922 /* ================                                           R_DTC                                           ================ */
22923 /* =========================================================================================================================== */
22924 
22925 /* =========================================================  DTCCR  ========================================================= */
22926  #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
22927  #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
22928 /* ========================================================  DTCVBR  ========================================================= */
22929  #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
22930  #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
22931 /* =========================================================  DTCST  ========================================================= */
22932  #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
22933  #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
22934 /* ========================================================  DTCSTS  ========================================================= */
22935  #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
22936  #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
22937  #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
22938  #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
22939 /* =======================================================  DTCCR_SEC  ======================================================= */
22940  #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
22941  #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
22942 /* ======================================================  DTCVBR_SEC  ======================================================= */
22943 /* =========================================================  DTEVR  ========================================================= */
22944  #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
22945  #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
22946  #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
22947  #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
22948  #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
22949  #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
22950 
22951 /* =========================================================================================================================== */
22952 /* ================                                           R_ELC                                           ================ */
22953 /* =========================================================================================================================== */
22954 
22955 /* =========================================================  ELCR  ========================================================== */
22956  #define R_ELC_ELCR_ELCON_Pos         (7UL)          /*!< ELCON (Bit 7)                                         */
22957  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)       /*!< ELCON (Bitfield-Mask: 0x01)                           */
22958 /* ========================================================  ELCSARA  ======================================================== */
22959  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)          /*!< ELCR (Bit 0)                                          */
22960  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)        /*!< ELCR (Bitfield-Mask: 0x01)                            */
22961  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)          /*!< ELSEGR0 (Bit 1)                                       */
22962  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)        /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
22963  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)          /*!< ELSEGR1 (Bit 2)                                       */
22964  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)        /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
22965 /* ========================================================  ELCSARB  ======================================================== */
22966  #define R_ELC_ELCSARB_ELSR_Pos       (0UL)          /*!< ELSR (Bit 0)                                          */
22967  #define R_ELC_ELCSARB_ELSR_Msk       (0x1UL)        /*!< ELSR (Bitfield-Mask: 0x01)                            */
22968  #define R_ELC_ELCSARB_ELSR30_Pos     (30UL)         /*!< ELSR30 (Bit 30)                                       */
22969  #define R_ELC_ELCSARB_ELSR30_Msk     (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01)                          */
22970 /* ========================================================  ELCPARA  ======================================================== */
22971  #define R_ELC_ELCPARA_ELCR_Pos       (0UL)          /*!< ELCR (Bit 0)                                          */
22972  #define R_ELC_ELCPARA_ELCR_Msk       (0x1UL)        /*!< ELCR (Bitfield-Mask: 0x01)                            */
22973  #define R_ELC_ELCPARA_ELSEGR0_Pos    (1UL)          /*!< ELSEGR0 (Bit 1)                                       */
22974  #define R_ELC_ELCPARA_ELSEGR0_Msk    (0x2UL)        /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
22975  #define R_ELC_ELCPARA_ELSEGR1_Pos    (2UL)          /*!< ELSEGR1 (Bit 2)                                       */
22976  #define R_ELC_ELCPARA_ELSEGR1_Msk    (0x4UL)        /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
22977 /* ========================================================  ELCPARB  ======================================================== */
22978  #define R_ELC_ELCPARB_ELSR_Pos       (0UL)          /*!< ELSR (Bit 0)                                          */
22979  #define R_ELC_ELCPARB_ELSR_Msk       (0x1UL)        /*!< ELSR (Bitfield-Mask: 0x01)                            */
22980  #define R_ELC_ELCPARB_ELSR30_Pos     (30UL)         /*!< ELSR30 (Bit 30)                                       */
22981  #define R_ELC_ELCPARB_ELSR30_Msk     (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01)                          */
22982 
22983 /* =========================================================================================================================== */
22984 /* ================                                         R_ETHERC0                                         ================ */
22985 /* =========================================================================================================================== */
22986 
22987 /* =========================================================  ECMR  ========================================================== */
22988  #define R_ETHERC0_ECMR_TPC_Pos          (20UL)         /*!< TPC (Bit 20)                                          */
22989  #define R_ETHERC0_ECMR_TPC_Msk          (0x100000UL)   /*!< TPC (Bitfield-Mask: 0x01)                             */
22990  #define R_ETHERC0_ECMR_ZPF_Pos          (19UL)         /*!< ZPF (Bit 19)                                          */
22991  #define R_ETHERC0_ECMR_ZPF_Msk          (0x80000UL)    /*!< ZPF (Bitfield-Mask: 0x01)                             */
22992  #define R_ETHERC0_ECMR_PFR_Pos          (18UL)         /*!< PFR (Bit 18)                                          */
22993  #define R_ETHERC0_ECMR_PFR_Msk          (0x40000UL)    /*!< PFR (Bitfield-Mask: 0x01)                             */
22994  #define R_ETHERC0_ECMR_RXF_Pos          (17UL)         /*!< RXF (Bit 17)                                          */
22995  #define R_ETHERC0_ECMR_RXF_Msk          (0x20000UL)    /*!< RXF (Bitfield-Mask: 0x01)                             */
22996  #define R_ETHERC0_ECMR_TXF_Pos          (16UL)         /*!< TXF (Bit 16)                                          */
22997  #define R_ETHERC0_ECMR_TXF_Msk          (0x10000UL)    /*!< TXF (Bitfield-Mask: 0x01)                             */
22998  #define R_ETHERC0_ECMR_PRCEF_Pos        (12UL)         /*!< PRCEF (Bit 12)                                        */
22999  #define R_ETHERC0_ECMR_PRCEF_Msk        (0x1000UL)     /*!< PRCEF (Bitfield-Mask: 0x01)                           */
23000  #define R_ETHERC0_ECMR_MPDE_Pos         (9UL)          /*!< MPDE (Bit 9)                                          */
23001  #define R_ETHERC0_ECMR_MPDE_Msk         (0x200UL)      /*!< MPDE (Bitfield-Mask: 0x01)                            */
23002  #define R_ETHERC0_ECMR_RE_Pos           (6UL)          /*!< RE (Bit 6)                                            */
23003  #define R_ETHERC0_ECMR_RE_Msk           (0x40UL)       /*!< RE (Bitfield-Mask: 0x01)                              */
23004  #define R_ETHERC0_ECMR_TE_Pos           (5UL)          /*!< TE (Bit 5)                                            */
23005  #define R_ETHERC0_ECMR_TE_Msk           (0x20UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
23006  #define R_ETHERC0_ECMR_ILB_Pos          (3UL)          /*!< ILB (Bit 3)                                           */
23007  #define R_ETHERC0_ECMR_ILB_Msk          (0x8UL)        /*!< ILB (Bitfield-Mask: 0x01)                             */
23008  #define R_ETHERC0_ECMR_RTM_Pos          (2UL)          /*!< RTM (Bit 2)                                           */
23009  #define R_ETHERC0_ECMR_RTM_Msk          (0x4UL)        /*!< RTM (Bitfield-Mask: 0x01)                             */
23010  #define R_ETHERC0_ECMR_DM_Pos           (1UL)          /*!< DM (Bit 1)                                            */
23011  #define R_ETHERC0_ECMR_DM_Msk           (0x2UL)        /*!< DM (Bitfield-Mask: 0x01)                              */
23012  #define R_ETHERC0_ECMR_PRM_Pos          (0UL)          /*!< PRM (Bit 0)                                           */
23013  #define R_ETHERC0_ECMR_PRM_Msk          (0x1UL)        /*!< PRM (Bitfield-Mask: 0x01)                             */
23014 /* =========================================================  RFLR  ========================================================== */
23015  #define R_ETHERC0_RFLR_RFL_Pos          (0UL)          /*!< RFL (Bit 0)                                           */
23016  #define R_ETHERC0_RFLR_RFL_Msk          (0xfffUL)      /*!< RFL (Bitfield-Mask: 0xfff)                            */
23017 /* =========================================================  ECSR  ========================================================== */
23018  #define R_ETHERC0_ECSR_BFR_Pos          (5UL)          /*!< BFR (Bit 5)                                           */
23019  #define R_ETHERC0_ECSR_BFR_Msk          (0x20UL)       /*!< BFR (Bitfield-Mask: 0x01)                             */
23020  #define R_ETHERC0_ECSR_PSRTO_Pos        (4UL)          /*!< PSRTO (Bit 4)                                         */
23021  #define R_ETHERC0_ECSR_PSRTO_Msk        (0x10UL)       /*!< PSRTO (Bitfield-Mask: 0x01)                           */
23022  #define R_ETHERC0_ECSR_LCHNG_Pos        (2UL)          /*!< LCHNG (Bit 2)                                         */
23023  #define R_ETHERC0_ECSR_LCHNG_Msk        (0x4UL)        /*!< LCHNG (Bitfield-Mask: 0x01)                           */
23024  #define R_ETHERC0_ECSR_MPD_Pos          (1UL)          /*!< MPD (Bit 1)                                           */
23025  #define R_ETHERC0_ECSR_MPD_Msk          (0x2UL)        /*!< MPD (Bitfield-Mask: 0x01)                             */
23026  #define R_ETHERC0_ECSR_ICD_Pos          (0UL)          /*!< ICD (Bit 0)                                           */
23027  #define R_ETHERC0_ECSR_ICD_Msk          (0x1UL)        /*!< ICD (Bitfield-Mask: 0x01)                             */
23028 /* ========================================================  ECSIPR  ========================================================= */
23029  #define R_ETHERC0_ECSIPR_BFSIPR_Pos     (5UL)          /*!< BFSIPR (Bit 5)                                        */
23030  #define R_ETHERC0_ECSIPR_BFSIPR_Msk     (0x20UL)       /*!< BFSIPR (Bitfield-Mask: 0x01)                          */
23031  #define R_ETHERC0_ECSIPR_PSRTOIP_Pos    (4UL)          /*!< PSRTOIP (Bit 4)                                       */
23032  #define R_ETHERC0_ECSIPR_PSRTOIP_Msk    (0x10UL)       /*!< PSRTOIP (Bitfield-Mask: 0x01)                         */
23033  #define R_ETHERC0_ECSIPR_LCHNGIP_Pos    (2UL)          /*!< LCHNGIP (Bit 2)                                       */
23034  #define R_ETHERC0_ECSIPR_LCHNGIP_Msk    (0x4UL)        /*!< LCHNGIP (Bitfield-Mask: 0x01)                         */
23035  #define R_ETHERC0_ECSIPR_MPDIP_Pos      (1UL)          /*!< MPDIP (Bit 1)                                         */
23036  #define R_ETHERC0_ECSIPR_MPDIP_Msk      (0x2UL)        /*!< MPDIP (Bitfield-Mask: 0x01)                           */
23037  #define R_ETHERC0_ECSIPR_ICDIP_Pos      (0UL)          /*!< ICDIP (Bit 0)                                         */
23038  #define R_ETHERC0_ECSIPR_ICDIP_Msk      (0x1UL)        /*!< ICDIP (Bitfield-Mask: 0x01)                           */
23039 /* ==========================================================  PIR  ========================================================== */
23040  #define R_ETHERC0_PIR_MDI_Pos           (3UL)          /*!< MDI (Bit 3)                                           */
23041  #define R_ETHERC0_PIR_MDI_Msk           (0x8UL)        /*!< MDI (Bitfield-Mask: 0x01)                             */
23042  #define R_ETHERC0_PIR_MDO_Pos           (2UL)          /*!< MDO (Bit 2)                                           */
23043  #define R_ETHERC0_PIR_MDO_Msk           (0x4UL)        /*!< MDO (Bitfield-Mask: 0x01)                             */
23044  #define R_ETHERC0_PIR_MMD_Pos           (1UL)          /*!< MMD (Bit 1)                                           */
23045  #define R_ETHERC0_PIR_MMD_Msk           (0x2UL)        /*!< MMD (Bitfield-Mask: 0x01)                             */
23046  #define R_ETHERC0_PIR_MDC_Pos           (0UL)          /*!< MDC (Bit 0)                                           */
23047  #define R_ETHERC0_PIR_MDC_Msk           (0x1UL)        /*!< MDC (Bitfield-Mask: 0x01)                             */
23048 /* ==========================================================  PSR  ========================================================== */
23049  #define R_ETHERC0_PSR_LMON_Pos          (0UL)          /*!< LMON (Bit 0)                                          */
23050  #define R_ETHERC0_PSR_LMON_Msk          (0x1UL)        /*!< LMON (Bitfield-Mask: 0x01)                            */
23051 /* =========================================================  RDMLR  ========================================================= */
23052  #define R_ETHERC0_RDMLR_RMD_Pos         (0UL)          /*!< RMD (Bit 0)                                           */
23053  #define R_ETHERC0_RDMLR_RMD_Msk         (0xfffffUL)    /*!< RMD (Bitfield-Mask: 0xfffff)                          */
23054 /* =========================================================  IPGR  ========================================================== */
23055  #define R_ETHERC0_IPGR_IPG_Pos          (0UL)          /*!< IPG (Bit 0)                                           */
23056  #define R_ETHERC0_IPGR_IPG_Msk          (0x1fUL)       /*!< IPG (Bitfield-Mask: 0x1f)                             */
23057 /* ==========================================================  APR  ========================================================== */
23058  #define R_ETHERC0_APR_AP_Pos            (0UL)          /*!< AP (Bit 0)                                            */
23059  #define R_ETHERC0_APR_AP_Msk            (0xffffUL)     /*!< AP (Bitfield-Mask: 0xffff)                            */
23060 /* ==========================================================  MPR  ========================================================== */
23061  #define R_ETHERC0_MPR_MP_Pos            (0UL)          /*!< MP (Bit 0)                                            */
23062  #define R_ETHERC0_MPR_MP_Msk            (0xffffUL)     /*!< MP (Bitfield-Mask: 0xffff)                            */
23063 /* =========================================================  RFCF  ========================================================== */
23064  #define R_ETHERC0_RFCF_RPAUSE_Pos       (0UL)          /*!< RPAUSE (Bit 0)                                        */
23065  #define R_ETHERC0_RFCF_RPAUSE_Msk       (0xffUL)       /*!< RPAUSE (Bitfield-Mask: 0xff)                          */
23066 /* ========================================================  TPAUSER  ======================================================== */
23067  #define R_ETHERC0_TPAUSER_TPAUSE_Pos    (0UL)          /*!< TPAUSE (Bit 0)                                        */
23068  #define R_ETHERC0_TPAUSER_TPAUSE_Msk    (0xffffUL)     /*!< TPAUSE (Bitfield-Mask: 0xffff)                        */
23069 /* =======================================================  TPAUSECR  ======================================================== */
23070 /* =========================================================  BCFRR  ========================================================= */
23071  #define R_ETHERC0_BCFRR_BCF_Pos         (0UL)          /*!< BCF (Bit 0)                                           */
23072  #define R_ETHERC0_BCFRR_BCF_Msk         (0xffffUL)     /*!< BCF (Bitfield-Mask: 0xffff)                           */
23073 /* =========================================================  MAHR  ========================================================== */
23074  #define R_ETHERC0_MAHR_MAHR_Pos         (0UL)          /*!< MAHR (Bit 0)                                          */
23075  #define R_ETHERC0_MAHR_MAHR_Msk         (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff)                      */
23076 /* =========================================================  MALR  ========================================================== */
23077  #define R_ETHERC0_MALR_MALR_Pos         (0UL)          /*!< MALR (Bit 0)                                          */
23078  #define R_ETHERC0_MALR_MALR_Msk         (0xffffUL)     /*!< MALR (Bitfield-Mask: 0xffff)                          */
23079 /* =========================================================  TROCR  ========================================================= */
23080  #define R_ETHERC0_TROCR_TROCR_Pos       (0UL)          /*!< TROCR (Bit 0)                                         */
23081  #define R_ETHERC0_TROCR_TROCR_Msk       (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff)                     */
23082 /* =========================================================  CDCR  ========================================================== */
23083 /* =========================================================  LCCR  ========================================================== */
23084  #define R_ETHERC0_LCCR_LCCR_Pos         (0UL)          /*!< LCCR (Bit 0)                                          */
23085  #define R_ETHERC0_LCCR_LCCR_Msk         (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff)                      */
23086 /* =========================================================  CNDCR  ========================================================= */
23087  #define R_ETHERC0_CNDCR_CNDCR_Pos       (0UL)          /*!< CNDCR (Bit 0)                                         */
23088  #define R_ETHERC0_CNDCR_CNDCR_Msk       (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff)                     */
23089 /* =========================================================  CEFCR  ========================================================= */
23090  #define R_ETHERC0_CEFCR_CEFCR_Pos       (0UL)          /*!< CEFCR (Bit 0)                                         */
23091  #define R_ETHERC0_CEFCR_CEFCR_Msk       (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff)                     */
23092 /* =========================================================  FRECR  ========================================================= */
23093  #define R_ETHERC0_FRECR_FRECR_Pos       (0UL)          /*!< FRECR (Bit 0)                                         */
23094  #define R_ETHERC0_FRECR_FRECR_Msk       (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff)                     */
23095 /* ========================================================  TSFRCR  ========================================================= */
23096  #define R_ETHERC0_TSFRCR_TSFRCR_Pos     (0UL)          /*!< TSFRCR (Bit 0)                                        */
23097  #define R_ETHERC0_TSFRCR_TSFRCR_Msk     (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff)                    */
23098 /* ========================================================  TLFRCR  ========================================================= */
23099  #define R_ETHERC0_TLFRCR_TLFRCR_Pos     (0UL)          /*!< TLFRCR (Bit 0)                                        */
23100  #define R_ETHERC0_TLFRCR_TLFRCR_Msk     (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff)                    */
23101 /* =========================================================  RFCR  ========================================================== */
23102  #define R_ETHERC0_RFCR_RFCR_Pos         (0UL)          /*!< RFCR (Bit 0)                                          */
23103  #define R_ETHERC0_RFCR_RFCR_Msk         (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff)                      */
23104 /* =========================================================  MAFCR  ========================================================= */
23105  #define R_ETHERC0_MAFCR_MAFCR_Pos       (0UL)          /*!< MAFCR (Bit 0)                                         */
23106  #define R_ETHERC0_MAFCR_MAFCR_Msk       (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff)                     */
23107 
23108 /* =========================================================================================================================== */
23109 /* ================                                      R_ETHERC_EDMAC                                       ================ */
23110 /* =========================================================================================================================== */
23111 
23112 /* =========================================================  EDMR  ========================================================== */
23113  #define R_ETHERC_EDMAC_EDMR_DE_Pos           (6UL)          /*!< DE (Bit 6)                                            */
23114  #define R_ETHERC_EDMAC_EDMR_DE_Msk           (0x40UL)       /*!< DE (Bitfield-Mask: 0x01)                              */
23115  #define R_ETHERC_EDMAC_EDMR_DL_Pos           (4UL)          /*!< DL (Bit 4)                                            */
23116  #define R_ETHERC_EDMAC_EDMR_DL_Msk           (0x30UL)       /*!< DL (Bitfield-Mask: 0x03)                              */
23117  #define R_ETHERC_EDMAC_EDMR_SWR_Pos          (0UL)          /*!< SWR (Bit 0)                                           */
23118  #define R_ETHERC_EDMAC_EDMR_SWR_Msk          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
23119 /* =========================================================  EDTRR  ========================================================= */
23120  #define R_ETHERC_EDMAC_EDTRR_TR_Pos          (0UL)          /*!< TR (Bit 0)                                            */
23121  #define R_ETHERC_EDMAC_EDTRR_TR_Msk          (0x1UL)        /*!< TR (Bitfield-Mask: 0x01)                              */
23122 /* =========================================================  EDRRR  ========================================================= */
23123  #define R_ETHERC_EDMAC_EDRRR_RR_Pos          (0UL)          /*!< RR (Bit 0)                                            */
23124  #define R_ETHERC_EDMAC_EDRRR_RR_Msk          (0x1UL)        /*!< RR (Bitfield-Mask: 0x01)                              */
23125 /* =========================================================  TDLAR  ========================================================= */
23126  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos       (0UL)          /*!< TDLAR (Bit 0)                                         */
23127  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk       (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff)                     */
23128 /* =========================================================  RDLAR  ========================================================= */
23129  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos       (0UL)          /*!< RDLAR (Bit 0)                                         */
23130  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk       (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff)                     */
23131 /* =========================================================  EESR  ========================================================== */
23132  #define R_ETHERC_EDMAC_EESR_TWB_Pos          (30UL)         /*!< TWB (Bit 30)                                          */
23133  #define R_ETHERC_EDMAC_EESR_TWB_Msk          (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01)                             */
23134  #define R_ETHERC_EDMAC_EESR_TABT_Pos         (26UL)         /*!< TABT (Bit 26)                                         */
23135  #define R_ETHERC_EDMAC_EESR_TABT_Msk         (0x4000000UL)  /*!< TABT (Bitfield-Mask: 0x01)                            */
23136  #define R_ETHERC_EDMAC_EESR_RABT_Pos         (25UL)         /*!< RABT (Bit 25)                                         */
23137  #define R_ETHERC_EDMAC_EESR_RABT_Msk         (0x2000000UL)  /*!< RABT (Bitfield-Mask: 0x01)                            */
23138  #define R_ETHERC_EDMAC_EESR_RFCOF_Pos        (24UL)         /*!< RFCOF (Bit 24)                                        */
23139  #define R_ETHERC_EDMAC_EESR_RFCOF_Msk        (0x1000000UL)  /*!< RFCOF (Bitfield-Mask: 0x01)                           */
23140  #define R_ETHERC_EDMAC_EESR_ADE_Pos          (23UL)         /*!< ADE (Bit 23)                                          */
23141  #define R_ETHERC_EDMAC_EESR_ADE_Msk          (0x800000UL)   /*!< ADE (Bitfield-Mask: 0x01)                             */
23142  #define R_ETHERC_EDMAC_EESR_ECI_Pos          (22UL)         /*!< ECI (Bit 22)                                          */
23143  #define R_ETHERC_EDMAC_EESR_ECI_Msk          (0x400000UL)   /*!< ECI (Bitfield-Mask: 0x01)                             */
23144  #define R_ETHERC_EDMAC_EESR_TC_Pos           (21UL)         /*!< TC (Bit 21)                                           */
23145  #define R_ETHERC_EDMAC_EESR_TC_Msk           (0x200000UL)   /*!< TC (Bitfield-Mask: 0x01)                              */
23146  #define R_ETHERC_EDMAC_EESR_TDE_Pos          (20UL)         /*!< TDE (Bit 20)                                          */
23147  #define R_ETHERC_EDMAC_EESR_TDE_Msk          (0x100000UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
23148  #define R_ETHERC_EDMAC_EESR_TFUF_Pos         (19UL)         /*!< TFUF (Bit 19)                                         */
23149  #define R_ETHERC_EDMAC_EESR_TFUF_Msk         (0x80000UL)    /*!< TFUF (Bitfield-Mask: 0x01)                            */
23150  #define R_ETHERC_EDMAC_EESR_FR_Pos           (18UL)         /*!< FR (Bit 18)                                           */
23151  #define R_ETHERC_EDMAC_EESR_FR_Msk           (0x40000UL)    /*!< FR (Bitfield-Mask: 0x01)                              */
23152  #define R_ETHERC_EDMAC_EESR_RDE_Pos          (17UL)         /*!< RDE (Bit 17)                                          */
23153  #define R_ETHERC_EDMAC_EESR_RDE_Msk          (0x20000UL)    /*!< RDE (Bitfield-Mask: 0x01)                             */
23154  #define R_ETHERC_EDMAC_EESR_RFOF_Pos         (16UL)         /*!< RFOF (Bit 16)                                         */
23155  #define R_ETHERC_EDMAC_EESR_RFOF_Msk         (0x10000UL)    /*!< RFOF (Bitfield-Mask: 0x01)                            */
23156  #define R_ETHERC_EDMAC_EESR_CND_Pos          (11UL)         /*!< CND (Bit 11)                                          */
23157  #define R_ETHERC_EDMAC_EESR_CND_Msk          (0x800UL)      /*!< CND (Bitfield-Mask: 0x01)                             */
23158  #define R_ETHERC_EDMAC_EESR_DLC_Pos          (10UL)         /*!< DLC (Bit 10)                                          */
23159  #define R_ETHERC_EDMAC_EESR_DLC_Msk          (0x400UL)      /*!< DLC (Bitfield-Mask: 0x01)                             */
23160  #define R_ETHERC_EDMAC_EESR_CD_Pos           (9UL)          /*!< CD (Bit 9)                                            */
23161  #define R_ETHERC_EDMAC_EESR_CD_Msk           (0x200UL)      /*!< CD (Bitfield-Mask: 0x01)                              */
23162  #define R_ETHERC_EDMAC_EESR_TRO_Pos          (8UL)          /*!< TRO (Bit 8)                                           */
23163  #define R_ETHERC_EDMAC_EESR_TRO_Msk          (0x100UL)      /*!< TRO (Bitfield-Mask: 0x01)                             */
23164  #define R_ETHERC_EDMAC_EESR_RMAF_Pos         (7UL)          /*!< RMAF (Bit 7)                                          */
23165  #define R_ETHERC_EDMAC_EESR_RMAF_Msk         (0x80UL)       /*!< RMAF (Bitfield-Mask: 0x01)                            */
23166  #define R_ETHERC_EDMAC_EESR_RRF_Pos          (4UL)          /*!< RRF (Bit 4)                                           */
23167  #define R_ETHERC_EDMAC_EESR_RRF_Msk          (0x10UL)       /*!< RRF (Bitfield-Mask: 0x01)                             */
23168  #define R_ETHERC_EDMAC_EESR_RTLF_Pos         (3UL)          /*!< RTLF (Bit 3)                                          */
23169  #define R_ETHERC_EDMAC_EESR_RTLF_Msk         (0x8UL)        /*!< RTLF (Bitfield-Mask: 0x01)                            */
23170  #define R_ETHERC_EDMAC_EESR_RTSF_Pos         (2UL)          /*!< RTSF (Bit 2)                                          */
23171  #define R_ETHERC_EDMAC_EESR_RTSF_Msk         (0x4UL)        /*!< RTSF (Bitfield-Mask: 0x01)                            */
23172  #define R_ETHERC_EDMAC_EESR_PRE_Pos          (1UL)          /*!< PRE (Bit 1)                                           */
23173  #define R_ETHERC_EDMAC_EESR_PRE_Msk          (0x2UL)        /*!< PRE (Bitfield-Mask: 0x01)                             */
23174  #define R_ETHERC_EDMAC_EESR_CERF_Pos         (0UL)          /*!< CERF (Bit 0)                                          */
23175  #define R_ETHERC_EDMAC_EESR_CERF_Msk         (0x1UL)        /*!< CERF (Bitfield-Mask: 0x01)                            */
23176 /* ========================================================  EESIPR  ========================================================= */
23177  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos      (30UL)         /*!< TWBIP (Bit 30)                                        */
23178  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk      (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01)                           */
23179  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos     (26UL)         /*!< TABTIP (Bit 26)                                       */
23180  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk     (0x4000000UL)  /*!< TABTIP (Bitfield-Mask: 0x01)                          */
23181  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos     (25UL)         /*!< RABTIP (Bit 25)                                       */
23182  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk     (0x2000000UL)  /*!< RABTIP (Bitfield-Mask: 0x01)                          */
23183  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos    (24UL)         /*!< RFCOFIP (Bit 24)                                      */
23184  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk    (0x1000000UL)  /*!< RFCOFIP (Bitfield-Mask: 0x01)                         */
23185  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos      (23UL)         /*!< ADEIP (Bit 23)                                        */
23186  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk      (0x800000UL)   /*!< ADEIP (Bitfield-Mask: 0x01)                           */
23187  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos      (22UL)         /*!< ECIIP (Bit 22)                                        */
23188  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk      (0x400000UL)   /*!< ECIIP (Bitfield-Mask: 0x01)                           */
23189  #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos       (21UL)         /*!< TCIP (Bit 21)                                         */
23190  #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk       (0x200000UL)   /*!< TCIP (Bitfield-Mask: 0x01)                            */
23191  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos      (20UL)         /*!< TDEIP (Bit 20)                                        */
23192  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk      (0x100000UL)   /*!< TDEIP (Bitfield-Mask: 0x01)                           */
23193  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos     (19UL)         /*!< TFUFIP (Bit 19)                                       */
23194  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk     (0x80000UL)    /*!< TFUFIP (Bitfield-Mask: 0x01)                          */
23195  #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos       (18UL)         /*!< FRIP (Bit 18)                                         */
23196  #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk       (0x40000UL)    /*!< FRIP (Bitfield-Mask: 0x01)                            */
23197  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos      (17UL)         /*!< RDEIP (Bit 17)                                        */
23198  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk      (0x20000UL)    /*!< RDEIP (Bitfield-Mask: 0x01)                           */
23199  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos     (16UL)         /*!< RFOFIP (Bit 16)                                       */
23200  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk     (0x10000UL)    /*!< RFOFIP (Bitfield-Mask: 0x01)                          */
23201  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos      (11UL)         /*!< CNDIP (Bit 11)                                        */
23202  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk      (0x800UL)      /*!< CNDIP (Bitfield-Mask: 0x01)                           */
23203  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos      (10UL)         /*!< DLCIP (Bit 10)                                        */
23204  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk      (0x400UL)      /*!< DLCIP (Bitfield-Mask: 0x01)                           */
23205  #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos       (9UL)          /*!< CDIP (Bit 9)                                          */
23206  #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk       (0x200UL)      /*!< CDIP (Bitfield-Mask: 0x01)                            */
23207  #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos      (8UL)          /*!< TROIP (Bit 8)                                         */
23208  #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk      (0x100UL)      /*!< TROIP (Bitfield-Mask: 0x01)                           */
23209  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos     (7UL)          /*!< RMAFIP (Bit 7)                                        */
23210  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk     (0x80UL)       /*!< RMAFIP (Bitfield-Mask: 0x01)                          */
23211  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos      (4UL)          /*!< RRFIP (Bit 4)                                         */
23212  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk      (0x10UL)       /*!< RRFIP (Bitfield-Mask: 0x01)                           */
23213  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos     (3UL)          /*!< RTLFIP (Bit 3)                                        */
23214  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk     (0x8UL)        /*!< RTLFIP (Bitfield-Mask: 0x01)                          */
23215  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos     (2UL)          /*!< RTSFIP (Bit 2)                                        */
23216  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk     (0x4UL)        /*!< RTSFIP (Bitfield-Mask: 0x01)                          */
23217  #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos      (1UL)          /*!< PREIP (Bit 1)                                         */
23218  #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk      (0x2UL)        /*!< PREIP (Bitfield-Mask: 0x01)                           */
23219  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos     (0UL)          /*!< CERFIP (Bit 0)                                        */
23220  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk     (0x1UL)        /*!< CERFIP (Bitfield-Mask: 0x01)                          */
23221 /* ========================================================  TRSCER  ========================================================= */
23222  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos     (7UL)          /*!< RMAFCE (Bit 7)                                        */
23223  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk     (0x80UL)       /*!< RMAFCE (Bitfield-Mask: 0x01)                          */
23224  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos      (4UL)          /*!< RRFCE (Bit 4)                                         */
23225  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk      (0x10UL)       /*!< RRFCE (Bitfield-Mask: 0x01)                           */
23226 /* =========================================================  RMFCR  ========================================================= */
23227  #define R_ETHERC_EDMAC_RMFCR_MFC_Pos         (0UL)          /*!< MFC (Bit 0)                                           */
23228  #define R_ETHERC_EDMAC_RMFCR_MFC_Msk         (0xffffUL)     /*!< MFC (Bitfield-Mask: 0xffff)                           */
23229 /* =========================================================  TFTR  ========================================================== */
23230  #define R_ETHERC_EDMAC_TFTR_TFT_Pos          (0UL)          /*!< TFT (Bit 0)                                           */
23231  #define R_ETHERC_EDMAC_TFTR_TFT_Msk          (0x7ffUL)      /*!< TFT (Bitfield-Mask: 0x7ff)                            */
23232 /* ==========================================================  FDR  ========================================================== */
23233  #define R_ETHERC_EDMAC_FDR_TFD_Pos           (8UL)          /*!< TFD (Bit 8)                                           */
23234  #define R_ETHERC_EDMAC_FDR_TFD_Msk           (0x1f00UL)     /*!< TFD (Bitfield-Mask: 0x1f)                             */
23235  #define R_ETHERC_EDMAC_FDR_RFD_Pos           (0UL)          /*!< RFD (Bit 0)                                           */
23236  #define R_ETHERC_EDMAC_FDR_RFD_Msk           (0x1fUL)       /*!< RFD (Bitfield-Mask: 0x1f)                             */
23237 /* =========================================================  RMCR  ========================================================== */
23238  #define R_ETHERC_EDMAC_RMCR_RNR_Pos          (0UL)          /*!< RNR (Bit 0)                                           */
23239  #define R_ETHERC_EDMAC_RMCR_RNR_Msk          (0x1UL)        /*!< RNR (Bitfield-Mask: 0x01)                             */
23240 /* =========================================================  TFUCR  ========================================================= */
23241  #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos       (0UL)          /*!< UNDER (Bit 0)                                         */
23242  #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk       (0xffffUL)     /*!< UNDER (Bitfield-Mask: 0xffff)                         */
23243 /* =========================================================  RFOCR  ========================================================= */
23244  #define R_ETHERC_EDMAC_RFOCR_OVER_Pos        (0UL)          /*!< OVER (Bit 0)                                          */
23245  #define R_ETHERC_EDMAC_RFOCR_OVER_Msk        (0xffffUL)     /*!< OVER (Bitfield-Mask: 0xffff)                          */
23246 /* =========================================================  IOSR  ========================================================== */
23247  #define R_ETHERC_EDMAC_IOSR_ELB_Pos          (0UL)          /*!< ELB (Bit 0)                                           */
23248  #define R_ETHERC_EDMAC_IOSR_ELB_Msk          (0x1UL)        /*!< ELB (Bitfield-Mask: 0x01)                             */
23249 /* =========================================================  FCFTR  ========================================================= */
23250  #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos        (16UL)         /*!< RFFO (Bit 16)                                         */
23251  #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk        (0x70000UL)    /*!< RFFO (Bitfield-Mask: 0x07)                            */
23252  #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos        (0UL)          /*!< RFDO (Bit 0)                                          */
23253  #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk        (0x7UL)        /*!< RFDO (Bitfield-Mask: 0x07)                            */
23254 /* ========================================================  RPADIR  ========================================================= */
23255  #define R_ETHERC_EDMAC_RPADIR_PADS_Pos       (16UL)         /*!< PADS (Bit 16)                                         */
23256  #define R_ETHERC_EDMAC_RPADIR_PADS_Msk       (0x30000UL)    /*!< PADS (Bitfield-Mask: 0x03)                            */
23257  #define R_ETHERC_EDMAC_RPADIR_PADR_Pos       (0UL)          /*!< PADR (Bit 0)                                          */
23258  #define R_ETHERC_EDMAC_RPADIR_PADR_Msk       (0x3fUL)       /*!< PADR (Bitfield-Mask: 0x3f)                            */
23259 /* =========================================================  TRIMD  ========================================================= */
23260  #define R_ETHERC_EDMAC_TRIMD_TIM_Pos         (4UL)          /*!< TIM (Bit 4)                                           */
23261  #define R_ETHERC_EDMAC_TRIMD_TIM_Msk         (0x10UL)       /*!< TIM (Bitfield-Mask: 0x01)                             */
23262  #define R_ETHERC_EDMAC_TRIMD_TIS_Pos         (0UL)          /*!< TIS (Bit 0)                                           */
23263  #define R_ETHERC_EDMAC_TRIMD_TIS_Msk         (0x1UL)        /*!< TIS (Bitfield-Mask: 0x01)                             */
23264 /* =========================================================  RBWAR  ========================================================= */
23265  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos       (0UL)          /*!< RBWAR (Bit 0)                                         */
23266  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk       (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff)                     */
23267 /* =========================================================  RDFAR  ========================================================= */
23268  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos       (0UL)          /*!< RDFAR (Bit 0)                                         */
23269  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk       (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff)                     */
23270 /* =========================================================  TBRAR  ========================================================= */
23271  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos       (0UL)          /*!< TBRAR (Bit 0)                                         */
23272  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk       (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff)                     */
23273 /* =========================================================  TDFAR  ========================================================= */
23274  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos       (0UL)          /*!< TDFAR (Bit 0)                                         */
23275  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk       (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff)                     */
23276 
23277 /* =========================================================================================================================== */
23278 /* ================                                       R_FACI_HP_CMD                                       ================ */
23279 /* =========================================================================================================================== */
23280 
23281 /* ======================================================  FACI_CMD16  ======================================================= */
23282 /* =======================================================  FACI_CMD8  ======================================================= */
23283 
23284 /* =========================================================================================================================== */
23285 /* ================                                         R_FACI_HP                                         ================ */
23286 /* =========================================================================================================================== */
23287 
23288 /* ========================================================  FASTAT  ========================================================= */
23289  #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
23290  #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
23291  #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
23292  #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
23293  #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
23294  #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
23295 /* ========================================================  FAEINT  ========================================================= */
23296  #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
23297  #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
23298  #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
23299  #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
23300  #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
23301  #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
23302 /* ========================================================  FRDYIE  ========================================================= */
23303  #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
23304  #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
23305 /* ========================================================  FSADDR  ========================================================= */
23306  #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
23307  #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
23308 /* ========================================================  FEADDR  ========================================================= */
23309  #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
23310  #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
23311 /* ========================================================  FMEPROT  ======================================================== */
23312  #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
23313  #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23314  #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
23315  #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
23316 /* ========================================================  FBPROT0  ======================================================== */
23317  #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
23318  #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23319  #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
23320  #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
23321 /* ========================================================  FBPROT1  ======================================================== */
23322  #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
23323  #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23324  #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
23325  #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
23326 /* ========================================================  FSTATR  ========================================================= */
23327  #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
23328  #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
23329  #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
23330  #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
23331  #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
23332  #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
23333  #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
23334  #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
23335  #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
23336  #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
23337  #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
23338  #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
23339  #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
23340  #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
23341  #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
23342  #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
23343  #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
23344  #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
23345  #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
23346  #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
23347  #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
23348  #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
23349  #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
23350  #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
23351  #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
23352  #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
23353 /* ========================================================  FENTRYR  ======================================================== */
23354  #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
23355  #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23356  #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
23357  #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
23358  #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
23359  #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
23360 /* =======================================================  FSUINITR  ======================================================== */
23361  #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
23362  #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23363  #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
23364  #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
23365 /* =========================================================  FCMDR  ========================================================= */
23366  #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
23367  #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
23368  #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
23369  #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
23370 /* ========================================================  FBCCNT  ========================================================= */
23371  #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
23372  #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
23373 /* ========================================================  FBCSTAT  ======================================================== */
23374  #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
23375  #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
23376 /* ========================================================  FPSADDR  ======================================================== */
23377  #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
23378  #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
23379 /* ========================================================  FAWMON  ========================================================= */
23380  #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
23381  #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
23382  #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
23383  #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
23384  #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
23385  #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
23386  #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
23387  #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
23388 /* =========================================================  FCPSR  ========================================================= */
23389  #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
23390  #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
23391 /* ========================================================  FPCKAR  ========================================================= */
23392  #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
23393  #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23394  #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
23395  #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
23396 /* ========================================================  FSUACR  ========================================================= */
23397  #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
23398  #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
23399  #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
23400  #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
23401 
23402 /* =========================================================================================================================== */
23403 /* ================                                         R_FCACHE                                          ================ */
23404 /* =========================================================================================================================== */
23405 
23406 /* ========================================================  FCACHEE  ======================================================== */
23407  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
23408  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
23409 /* =======================================================  FCACHEIV  ======================================================== */
23410  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
23411  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
23412 /* =========================================================  FLWT  ========================================================== */
23413  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
23414  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
23415 /* =========================================================  FSAR  ========================================================== */
23416  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
23417  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
23418  #define R_FCACHE_FSAR_FCACHEENSA_Pos      (1UL)     /*!< FCACHEENSA (Bit 1)                                    */
23419  #define R_FCACHE_FSAR_FCACHEENSA_Msk      (0x2UL)   /*!< FCACHEENSA (Bitfield-Mask: 0x01)                      */
23420  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
23421  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
23422  #define R_FCACHE_FSAR_FACICOMISA_Pos      (9UL)     /*!< FACICOMISA (Bit 9)                                    */
23423  #define R_FCACHE_FSAR_FACICOMISA_Msk      (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01)                      */
23424  #define R_FCACHE_FSAR_FACICOMRSA_Pos      (10UL)    /*!< FACICOMRSA (Bit 10)                                   */
23425  #define R_FCACHE_FSAR_FACICOMRSA_Msk      (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01)                      */
23426  #define R_FCACHE_FSAR_FACITRSA_Pos        (11UL)    /*!< FACITRSA (Bit 11)                                     */
23427  #define R_FCACHE_FSAR_FACITRSA_Msk        (0x800UL) /*!< FACITRSA (Bitfield-Mask: 0x01)                        */
23428 
23429 /* =========================================================================================================================== */
23430 /* ================                                          R_GPT0                                           ================ */
23431 /* =========================================================================================================================== */
23432 
23433 /* =========================================================  GTWP  ========================================================== */
23434  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
23435  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
23436  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
23437  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
23438  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
23439  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
23440  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
23441  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
23442  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
23443  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
23444  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
23445  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
23446 /* =========================================================  GTSTR  ========================================================= */
23447  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
23448  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
23449 /* =========================================================  GTSTP  ========================================================= */
23450  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
23451  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
23452 /* =========================================================  GTCLR  ========================================================= */
23453  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
23454  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
23455 /* =========================================================  GTSSR  ========================================================= */
23456  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
23457  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
23458  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
23459  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
23460  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
23461  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
23462  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
23463  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
23464  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
23465  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
23466  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
23467  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
23468  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
23469  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
23470  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
23471  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
23472  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
23473  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
23474  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
23475  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
23476  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
23477  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
23478  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
23479  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
23480 /* =========================================================  GTPSR  ========================================================= */
23481  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
23482  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
23483  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
23484  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
23485  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
23486  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
23487  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
23488  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
23489  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
23490  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
23491  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
23492  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
23493  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
23494  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
23495  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
23496  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
23497  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
23498  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
23499  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
23500  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
23501  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
23502  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
23503  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
23504  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
23505 /* =========================================================  GTCSR  ========================================================= */
23506  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
23507  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
23508  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
23509  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
23510  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
23511  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
23512  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
23513  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
23514  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
23515  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
23516  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
23517  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
23518  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
23519  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
23520  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
23521  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
23522  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
23523  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
23524  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
23525  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
23526  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
23527  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
23528  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
23529  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
23530  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
23531  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
23532  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
23533  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
23534 /* ========================================================  GTUPSR  ========================================================= */
23535  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
23536  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
23537  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
23538  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
23539  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
23540  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
23541  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
23542  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
23543  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
23544  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
23545  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
23546  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
23547  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
23548  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
23549  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
23550  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
23551  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
23552  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
23553  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
23554  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
23555  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
23556  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
23557  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
23558  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
23559 /* ========================================================  GTDNSR  ========================================================= */
23560  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
23561  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
23562  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
23563  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
23564  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
23565  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
23566  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
23567  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
23568  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
23569  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
23570  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
23571  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
23572  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
23573  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
23574  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
23575  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
23576  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
23577  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
23578  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
23579  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
23580  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
23581  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
23582  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
23583  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
23584 /* ========================================================  GTICASR  ======================================================== */
23585  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
23586  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
23587  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
23588  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
23589  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
23590  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
23591  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
23592  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
23593  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
23594  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
23595  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
23596  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
23597  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
23598  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
23599  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
23600  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
23601  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
23602  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
23603  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
23604  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
23605  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
23606  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
23607 /* ========================================================  GTICBSR  ======================================================== */
23608  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
23609  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
23610  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
23611  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
23612  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
23613  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
23614  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
23615  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
23616  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
23617  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
23618  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
23619  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
23620  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
23621  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
23622  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
23623  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
23624  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
23625  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
23626  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
23627  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
23628  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
23629  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
23630 /* =========================================================  GTCR  ========================================================== */
23631  #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
23632  #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
23633  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
23634  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
23635  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
23636  #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
23637  #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
23638  #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
23639  #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
23640  #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
23641  #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
23642  #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
23643  #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
23644  #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
23645  #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
23646  #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
23647  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
23648  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
23649 /* =======================================================  GTUDDTYC  ======================================================== */
23650  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
23651  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
23652  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
23653  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
23654  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
23655  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
23656  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
23657  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
23658  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
23659  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
23660  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
23661  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
23662  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
23663  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
23664  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
23665  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
23666 /* =========================================================  GTIOR  ========================================================= */
23667  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
23668  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
23669  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
23670  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
23671  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
23672  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
23673  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
23674  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
23675  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
23676  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
23677  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
23678  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
23679  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
23680  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
23681  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
23682  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
23683  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
23684  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
23685  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
23686  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
23687  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
23688  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
23689  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
23690  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
23691  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
23692  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
23693  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
23694  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
23695  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
23696  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
23697  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
23698  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
23699  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
23700  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
23701  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
23702  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
23703 /* ========================================================  GTINTAD  ======================================================== */
23704  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
23705  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
23706  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
23707  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
23708  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
23709  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
23710  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
23711  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
23712  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
23713  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
23714  #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
23715  #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
23716  #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
23717  #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
23718  #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
23719  #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
23720  #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
23721  #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
23722  #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
23723  #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
23724 /* =========================================================  GTST  ========================================================== */
23725  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
23726  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
23727  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
23728  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
23729  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
23730  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
23731  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
23732  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
23733  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
23734  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
23735  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
23736  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
23737  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
23738  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
23739  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
23740  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
23741  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
23742  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
23743  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
23744  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
23745  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
23746  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
23747  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
23748  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
23749  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
23750  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
23751  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
23752  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
23753  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
23754  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
23755  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
23756  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
23757  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
23758  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
23759  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
23760  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
23761  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
23762  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
23763 /* =========================================================  GTBER  ========================================================= */
23764  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
23765  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
23766  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
23767  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
23768  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
23769  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
23770  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
23771  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
23772  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
23773  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
23774  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
23775  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
23776  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
23777  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
23778  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
23779  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
23780  #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
23781  #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
23782  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
23783  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
23784  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
23785  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
23786  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
23787  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
23788  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
23789  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
23790 /* =========================================================  GTITC  ========================================================= */
23791  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
23792  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
23793  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
23794  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
23795  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
23796  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
23797  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
23798  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
23799  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
23800  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
23801  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
23802  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
23803  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
23804  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
23805  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
23806  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
23807  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
23808  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
23809  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
23810  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
23811 /* =========================================================  GTCNT  ========================================================= */
23812  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
23813  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
23814 /* =========================================================  GTCCR  ========================================================= */
23815  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
23816  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
23817 /* =========================================================  GTPR  ========================================================== */
23818  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
23819  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
23820 /* =========================================================  GTPBR  ========================================================= */
23821  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
23822  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
23823 /* ========================================================  GTPDBR  ========================================================= */
23824  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
23825  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
23826 /* ========================================================  GTADTRA  ======================================================== */
23827  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
23828  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
23829 /* ========================================================  GTADTRB  ======================================================== */
23830  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
23831  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
23832 /* =======================================================  GTADTBRA  ======================================================== */
23833  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
23834  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
23835 /* =======================================================  GTADTBRB  ======================================================== */
23836  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
23837  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
23838 /* =======================================================  GTADTDBRA  ======================================================= */
23839  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
23840  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
23841 /* =======================================================  GTADTDBRB  ======================================================= */
23842  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
23843  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
23844 /* ========================================================  GTDTCR  ========================================================= */
23845  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
23846  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
23847  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
23848  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
23849  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
23850  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
23851  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
23852  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
23853 /* =========================================================  GTDVU  ========================================================= */
23854  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
23855  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
23856 /* =========================================================  GTDVD  ========================================================= */
23857  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
23858  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
23859 /* =========================================================  GTDBU  ========================================================= */
23860  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
23861  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
23862 /* =========================================================  GTDBD  ========================================================= */
23863  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
23864  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
23865 /* =========================================================  GTSOS  ========================================================= */
23866  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
23867  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
23868 /* ========================================================  GTSOTR  ========================================================= */
23869  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
23870  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
23871 /* ========================================================  GTADSMR  ======================================================== */
23872  #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
23873  #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
23874  #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
23875  #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
23876  #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
23877  #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
23878  #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
23879  #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
23880 /* ========================================================  GTEITC  ========================================================= */
23881  #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
23882  #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
23883  #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
23884  #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
23885  #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
23886  #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
23887  #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
23888  #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
23889  #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
23890  #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
23891  #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
23892  #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
23893  #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
23894  #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
23895 /* =======================================================  GTEITLI1  ======================================================== */
23896  #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
23897  #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
23898  #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
23899  #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
23900  #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
23901  #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
23902  #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
23903  #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
23904  #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
23905  #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
23906  #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
23907  #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
23908  #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
23909  #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
23910  #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
23911  #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
23912 /* =======================================================  GTEITLI2  ======================================================== */
23913  #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
23914  #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
23915  #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
23916  #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
23917 /* ========================================================  GTEITLB  ======================================================== */
23918  #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
23919  #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
23920  #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
23921  #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
23922  #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
23923  #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
23924  #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
23925  #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
23926  #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
23927  #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
23928  #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
23929  #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
23930  #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
23931  #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
23932 /* ========================================================  GTICLF  ========================================================= */
23933  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
23934  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
23935  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
23936  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
23937  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
23938  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
23939  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
23940  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
23941 /* =========================================================  GTPC  ========================================================== */
23942  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
23943  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
23944  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
23945  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
23946  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
23947  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
23948 /* ========================================================  GTSECSR  ======================================================== */
23949  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
23950  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
23951  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
23952  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
23953  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
23954  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
23955  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
23956  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
23957  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
23958  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
23959  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
23960  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
23961  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
23962  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
23963  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
23964  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
23965  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
23966  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
23967  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
23968  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
23969 /* ========================================================  GTSECR  ========================================================= */
23970  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
23971  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
23972  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
23973  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
23974  #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
23975  #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
23976  #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
23977  #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
23978  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
23979  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
23980  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
23981  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
23982  #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
23983  #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
23984  #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
23985  #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
23986  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
23987  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
23988  #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
23989  #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
23990  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
23991  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
23992  #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
23993  #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
23994 /* ========================================================  GTBER2  ========================================================= */
23995  #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
23996  #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
23997  #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
23998  #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
23999  #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
24000  #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
24001  #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
24002  #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
24003  #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
24004  #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
24005  #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
24006  #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
24007  #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
24008  #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
24009  #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
24010  #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
24011  #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
24012  #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
24013  #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
24014  #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
24015  #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
24016  #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
24017  #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
24018  #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
24019  #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
24020  #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
24021  #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
24022  #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
24023  #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
24024  #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
24025  #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
24026  #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
24027  #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
24028  #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
24029  #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
24030  #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
24031  #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
24032  #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
24033  #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
24034  #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
24035 /* ========================================================  GTOLBR  ========================================================= */
24036  #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
24037  #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
24038  #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
24039  #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
24040 /* ========================================================  GTICCR  ========================================================= */
24041  #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
24042  #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
24043  #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
24044  #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
24045  #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
24046  #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
24047  #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
24048  #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
24049  #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
24050  #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
24051  #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
24052  #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
24053  #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
24054  #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
24055  #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
24056  #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
24057  #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
24058  #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
24059  #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
24060  #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
24061  #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
24062  #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
24063  #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
24064  #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
24065  #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
24066  #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
24067  #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
24068  #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
24069  #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
24070  #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
24071  #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
24072  #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
24073  #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
24074  #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
24075  #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
24076  #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
24077  #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
24078  #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
24079  #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
24080  #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
24081 
24082 /* =========================================================================================================================== */
24083 /* ================                                         R_GPT_OPS                                         ================ */
24084 /* =========================================================================================================================== */
24085 
24086 /* =========================================================  OPSCR  ========================================================= */
24087  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
24088  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
24089  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
24090  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
24091  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
24092  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
24093  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
24094  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
24095  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
24096  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
24097  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
24098  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
24099  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
24100  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
24101  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
24102  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
24103  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
24104  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
24105  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
24106  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
24107  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
24108  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
24109  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
24110  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
24111  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
24112  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
24113  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
24114  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
24115  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
24116  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
24117  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
24118  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
24119  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
24120  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
24121 
24122 /* =========================================================================================================================== */
24123 /* ================                                        R_GPT_POEG0                                        ================ */
24124 /* =========================================================================================================================== */
24125 
24126 /* =========================================================  POEGG  ========================================================= */
24127  #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
24128  #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
24129  #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
24130  #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
24131  #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
24132  #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
24133  #define R_GPT_POEG0_POEGG_DERRE_Pos      (26UL)         /*!< DERRE (Bit 26)                                        */
24134  #define R_GPT_POEG0_POEGG_DERRE_Msk      (0x4000000UL)  /*!< DERRE (Bitfield-Mask: 0x01)                           */
24135  #define R_GPT_POEG0_POEGG_DERRST_Pos     (24UL)         /*!< DERRST (Bit 24)                                       */
24136  #define R_GPT_POEG0_POEGG_DERRST_Msk     (0x1000000UL)  /*!< DERRST (Bitfield-Mask: 0x01)                          */
24137  #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
24138  #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
24139  #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
24140  #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
24141  #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
24142  #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
24143  #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
24144  #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
24145  #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
24146  #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
24147  #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
24148  #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
24149  #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
24150  #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
24151  #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
24152  #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
24153  #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
24154  #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
24155 /* ========================================================  GTONCWP  ======================================================== */
24156  #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
24157  #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
24158  #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
24159  #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
24160 /* ========================================================  GTONCCR  ======================================================== */
24161  #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
24162  #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
24163  #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
24164  #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
24165  #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
24166  #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */
24167 
24168 /* =========================================================================================================================== */
24169 /* ================                                           R_ICU                                           ================ */
24170 /* =========================================================================================================================== */
24171 
24172 /* =========================================================  IRQCR  ========================================================= */
24173  #define R_ICU_IRQCR_FLTEN_Pos            (7UL)          /*!< FLTEN (Bit 7)                                         */
24174  #define R_ICU_IRQCR_FLTEN_Msk            (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
24175  #define R_ICU_IRQCR_FCLKSEL_Pos          (4UL)          /*!< FCLKSEL (Bit 4)                                       */
24176  #define R_ICU_IRQCR_FCLKSEL_Msk          (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
24177  #define R_ICU_IRQCR_IRQMD_Pos            (0UL)          /*!< IRQMD (Bit 0)                                         */
24178  #define R_ICU_IRQCR_IRQMD_Msk            (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
24179 /* =========================================================  NMICR  ========================================================= */
24180  #define R_ICU_NMICR_NMIMD_Pos            (0UL)          /*!< NMIMD (Bit 0)                                         */
24181  #define R_ICU_NMICR_NMIMD_Msk            (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
24182  #define R_ICU_NMICR_NFCLKSEL_Pos         (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
24183  #define R_ICU_NMICR_NFCLKSEL_Msk         (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
24184  #define R_ICU_NMICR_NFLTEN_Pos           (7UL)          /*!< NFLTEN (Bit 7)                                        */
24185  #define R_ICU_NMICR_NFLTEN_Msk           (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
24186 /* ========================================================  SWIRQ_S  ======================================================== */
24187  #define R_ICU_SWIRQ_S_SWIRQS_Pos         (0UL)          /*!< SWIRQS (Bit 0)                                        */
24188  #define R_ICU_SWIRQ_S_SWIRQS_Msk         (0x1UL)        /*!< SWIRQS (Bitfield-Mask: 0x01)                          */
24189 /* =======================================================  SWIRQ_NS  ======================================================== */
24190  #define R_ICU_SWIRQ_NS_SWIRQNS_Pos       (0UL)          /*!< SWIRQNS (Bit 0)                                       */
24191  #define R_ICU_SWIRQ_NS_SWIRQNS_Msk       (0x1UL)        /*!< SWIRQNS (Bitfield-Mask: 0x01)                         */
24192 /* ========================================================  IENMIER  ======================================================== */
24193  #define R_ICU_IENMIER_CMEN_Pos           (0UL)          /*!< CMEN (Bit 0)                                          */
24194  #define R_ICU_IENMIER_CMEN_Msk           (0x1UL)        /*!< CMEN (Bitfield-Mask: 0x01)                            */
24195  #define R_ICU_IENMIER_LMEN_Pos           (1UL)          /*!< LMEN (Bit 1)                                          */
24196  #define R_ICU_IENMIER_LMEN_Msk           (0x2UL)        /*!< LMEN (Bitfield-Mask: 0x01)                            */
24197  #define R_ICU_IENMIER_BUSEN_Pos          (2UL)          /*!< BUSEN (Bit 2)                                         */
24198  #define R_ICU_IENMIER_BUSEN_Msk          (0x4UL)        /*!< BUSEN (Bitfield-Mask: 0x01)                           */
24199 /* =========================================================  NMIER  ========================================================= */
24200  #define R_ICU_NMIER_IWDTEN_Pos           (0UL)          /*!< IWDTEN (Bit 0)                                        */
24201  #define R_ICU_NMIER_IWDTEN_Msk           (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
24202  #define R_ICU_NMIER_WDTEN_Pos            (1UL)          /*!< WDTEN (Bit 1)                                         */
24203  #define R_ICU_NMIER_WDTEN_Msk            (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
24204  #define R_ICU_NMIER_LVD1EN_Pos           (2UL)          /*!< LVD1EN (Bit 2)                                        */
24205  #define R_ICU_NMIER_LVD1EN_Msk           (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
24206  #define R_ICU_NMIER_LVD2EN_Pos           (3UL)          /*!< LVD2EN (Bit 3)                                        */
24207  #define R_ICU_NMIER_LVD2EN_Msk           (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
24208  #define R_ICU_NMIER_OSTEN_Pos            (6UL)          /*!< OSTEN (Bit 6)                                         */
24209  #define R_ICU_NMIER_OSTEN_Msk            (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
24210  #define R_ICU_NMIER_NMIEN_Pos            (7UL)          /*!< NMIEN (Bit 7)                                         */
24211  #define R_ICU_NMIER_NMIEN_Msk            (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
24212  #define R_ICU_NMIER_BUSEN_Pos            (12UL)         /*!< BUSEN (Bit 12)                                        */
24213  #define R_ICU_NMIER_BUSEN_Msk            (0x1000UL)     /*!< BUSEN (Bitfield-Mask: 0x01)                           */
24214  #define R_ICU_NMIER_CMEN_Pos             (13UL)         /*!< CMEN (Bit 13)                                         */
24215  #define R_ICU_NMIER_CMEN_Msk             (0x2000UL)     /*!< CMEN (Bitfield-Mask: 0x01)                            */
24216  #define R_ICU_NMIER_LUEN_Pos             (15UL)         /*!< LUEN (Bit 15)                                         */
24217  #define R_ICU_NMIER_LUEN_Msk             (0x8000UL)     /*!< LUEN (Bitfield-Mask: 0x01)                            */
24218 /* ========================================================  NMICLR  ========================================================= */
24219  #define R_ICU_NMICLR_IWDTCLR_Pos         (0UL)          /*!< IWDTCLR (Bit 0)                                       */
24220  #define R_ICU_NMICLR_IWDTCLR_Msk         (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
24221  #define R_ICU_NMICLR_WDTCLR_Pos          (1UL)          /*!< WDTCLR (Bit 1)                                        */
24222  #define R_ICU_NMICLR_WDTCLR_Msk          (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
24223  #define R_ICU_NMICLR_LVD1CLR_Pos         (2UL)          /*!< LVD1CLR (Bit 2)                                       */
24224  #define R_ICU_NMICLR_LVD1CLR_Msk         (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
24225  #define R_ICU_NMICLR_LVD2CLR_Pos         (3UL)          /*!< LVD2CLR (Bit 3)                                       */
24226  #define R_ICU_NMICLR_LVD2CLR_Msk         (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
24227  #define R_ICU_NMICLR_OSTCLR_Pos          (6UL)          /*!< OSTCLR (Bit 6)                                        */
24228  #define R_ICU_NMICLR_OSTCLR_Msk          (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
24229  #define R_ICU_NMICLR_NMICLR_Pos          (7UL)          /*!< NMICLR (Bit 7)                                        */
24230  #define R_ICU_NMICLR_NMICLR_Msk          (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
24231  #define R_ICU_NMICLR_BUSCLR_Pos          (12UL)         /*!< BUSCLR (Bit 12)                                       */
24232  #define R_ICU_NMICLR_BUSCLR_Msk          (0x1000UL)     /*!< BUSCLR (Bitfield-Mask: 0x01)                          */
24233  #define R_ICU_NMICLR_CMCLR_Pos           (13UL)         /*!< CMCLR (Bit 13)                                        */
24234  #define R_ICU_NMICLR_CMCLR_Msk           (0x2000UL)     /*!< CMCLR (Bitfield-Mask: 0x01)                           */
24235  #define R_ICU_NMICLR_LUCLR_Pos           (15UL)         /*!< LUCLR (Bit 15)                                        */
24236  #define R_ICU_NMICLR_LUCLR_Msk           (0x8000UL)     /*!< LUCLR (Bitfield-Mask: 0x01)                           */
24237 /* =========================================================  NMISR  ========================================================= */
24238  #define R_ICU_NMISR_IWDTST_Pos           (0UL)          /*!< IWDTST (Bit 0)                                        */
24239  #define R_ICU_NMISR_IWDTST_Msk           (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
24240  #define R_ICU_NMISR_WDTST_Pos            (1UL)          /*!< WDTST (Bit 1)                                         */
24241  #define R_ICU_NMISR_WDTST_Msk            (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
24242  #define R_ICU_NMISR_LVD1ST_Pos           (2UL)          /*!< LVD1ST (Bit 2)                                        */
24243  #define R_ICU_NMISR_LVD1ST_Msk           (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
24244  #define R_ICU_NMISR_LVD2ST_Pos           (3UL)          /*!< LVD2ST (Bit 3)                                        */
24245  #define R_ICU_NMISR_LVD2ST_Msk           (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
24246  #define R_ICU_NMISR_OSTST_Pos            (6UL)          /*!< OSTST (Bit 6)                                         */
24247  #define R_ICU_NMISR_OSTST_Msk            (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
24248  #define R_ICU_NMISR_NMIST_Pos            (7UL)          /*!< NMIST (Bit 7)                                         */
24249  #define R_ICU_NMISR_NMIST_Msk            (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
24250  #define R_ICU_NMISR_BUSST_Pos            (12UL)         /*!< BUSST (Bit 12)                                        */
24251  #define R_ICU_NMISR_BUSST_Msk            (0x1000UL)     /*!< BUSST (Bitfield-Mask: 0x01)                           */
24252  #define R_ICU_NMISR_CMST_Pos             (13UL)         /*!< CMST (Bit 13)                                         */
24253  #define R_ICU_NMISR_CMST_Msk             (0x2000UL)     /*!< CMST (Bitfield-Mask: 0x01)                            */
24254  #define R_ICU_NMISR_LUST_Pos             (15UL)         /*!< LUST (Bit 15)                                         */
24255  #define R_ICU_NMISR_LUST_Msk             (0x8000UL)     /*!< LUST (Bitfield-Mask: 0x01)                            */
24256 /* =========================================================  WUPEN  ========================================================= */
24257  #define R_ICU_WUPEN_IRQWUPEN0_Pos        (0UL)          /*!< IRQWUPEN0 (Bit 0)                                     */
24258  #define R_ICU_WUPEN_IRQWUPEN0_Msk        (0x1UL)        /*!< IRQWUPEN0 (Bitfield-Mask: 0x01)                       */
24259  #define R_ICU_WUPEN_IRQWUPEN1_Pos        (1UL)          /*!< IRQWUPEN1 (Bit 1)                                     */
24260  #define R_ICU_WUPEN_IRQWUPEN1_Msk        (0x2UL)        /*!< IRQWUPEN1 (Bitfield-Mask: 0x01)                       */
24261  #define R_ICU_WUPEN_IRQWUPEN2_Pos        (2UL)          /*!< IRQWUPEN2 (Bit 2)                                     */
24262  #define R_ICU_WUPEN_IRQWUPEN2_Msk        (0x4UL)        /*!< IRQWUPEN2 (Bitfield-Mask: 0x01)                       */
24263  #define R_ICU_WUPEN_IRQWUPEN3_Pos        (3UL)          /*!< IRQWUPEN3 (Bit 3)                                     */
24264  #define R_ICU_WUPEN_IRQWUPEN3_Msk        (0x8UL)        /*!< IRQWUPEN3 (Bitfield-Mask: 0x01)                       */
24265  #define R_ICU_WUPEN_IRQWUPEN4_Pos        (4UL)          /*!< IRQWUPEN4 (Bit 4)                                     */
24266  #define R_ICU_WUPEN_IRQWUPEN4_Msk        (0x10UL)       /*!< IRQWUPEN4 (Bitfield-Mask: 0x01)                       */
24267  #define R_ICU_WUPEN_IRQWUPEN5_Pos        (5UL)          /*!< IRQWUPEN5 (Bit 5)                                     */
24268  #define R_ICU_WUPEN_IRQWUPEN5_Msk        (0x20UL)       /*!< IRQWUPEN5 (Bitfield-Mask: 0x01)                       */
24269  #define R_ICU_WUPEN_IRQWUPEN6_Pos        (6UL)          /*!< IRQWUPEN6 (Bit 6)                                     */
24270  #define R_ICU_WUPEN_IRQWUPEN6_Msk        (0x40UL)       /*!< IRQWUPEN6 (Bitfield-Mask: 0x01)                       */
24271  #define R_ICU_WUPEN_IRQWUPEN7_Pos        (7UL)          /*!< IRQWUPEN7 (Bit 7)                                     */
24272  #define R_ICU_WUPEN_IRQWUPEN7_Msk        (0x80UL)       /*!< IRQWUPEN7 (Bitfield-Mask: 0x01)                       */
24273  #define R_ICU_WUPEN_IRQWUPEN8_Pos        (8UL)          /*!< IRQWUPEN8 (Bit 8)                                     */
24274  #define R_ICU_WUPEN_IRQWUPEN8_Msk        (0x100UL)      /*!< IRQWUPEN8 (Bitfield-Mask: 0x01)                       */
24275  #define R_ICU_WUPEN_IRQWUPEN9_Pos        (9UL)          /*!< IRQWUPEN9 (Bit 9)                                     */
24276  #define R_ICU_WUPEN_IRQWUPEN9_Msk        (0x200UL)      /*!< IRQWUPEN9 (Bitfield-Mask: 0x01)                       */
24277  #define R_ICU_WUPEN_IRQWUPEN10_Pos       (10UL)         /*!< IRQWUPEN10 (Bit 10)                                   */
24278  #define R_ICU_WUPEN_IRQWUPEN10_Msk       (0x400UL)      /*!< IRQWUPEN10 (Bitfield-Mask: 0x01)                      */
24279  #define R_ICU_WUPEN_IRQWUPEN11_Pos       (11UL)         /*!< IRQWUPEN11 (Bit 11)                                   */
24280  #define R_ICU_WUPEN_IRQWUPEN11_Msk       (0x800UL)      /*!< IRQWUPEN11 (Bitfield-Mask: 0x01)                      */
24281  #define R_ICU_WUPEN_IRQWUPEN12_Pos       (12UL)         /*!< IRQWUPEN12 (Bit 12)                                   */
24282  #define R_ICU_WUPEN_IRQWUPEN12_Msk       (0x1000UL)     /*!< IRQWUPEN12 (Bitfield-Mask: 0x01)                      */
24283  #define R_ICU_WUPEN_IRQWUPEN13_Pos       (13UL)         /*!< IRQWUPEN13 (Bit 13)                                   */
24284  #define R_ICU_WUPEN_IRQWUPEN13_Msk       (0x2000UL)     /*!< IRQWUPEN13 (Bitfield-Mask: 0x01)                      */
24285  #define R_ICU_WUPEN_IRQWUPEN14_Pos       (14UL)         /*!< IRQWUPEN14 (Bit 14)                                   */
24286  #define R_ICU_WUPEN_IRQWUPEN14_Msk       (0x4000UL)     /*!< IRQWUPEN14 (Bitfield-Mask: 0x01)                      */
24287  #define R_ICU_WUPEN_IRQWUPEN15_Pos       (15UL)         /*!< IRQWUPEN15 (Bit 15)                                   */
24288  #define R_ICU_WUPEN_IRQWUPEN15_Msk       (0x8000UL)     /*!< IRQWUPEN15 (Bitfield-Mask: 0x01)                      */
24289  #define R_ICU_WUPEN_IWDTWUPEN_Pos        (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
24290  #define R_ICU_WUPEN_IWDTWUPEN_Msk        (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
24291  #define R_ICU_WUPEN_LVD1WUPEN_Pos        (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
24292  #define R_ICU_WUPEN_LVD1WUPEN_Msk        (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
24293  #define R_ICU_WUPEN_LVD2WUPEN_Pos        (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
24294  #define R_ICU_WUPEN_LVD2WUPEN_Msk        (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
24295  #define R_ICU_WUPEN_VBATTWUPEN_Pos       (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
24296  #define R_ICU_WUPEN_VBATTWUPEN_Msk       (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
24297  #define R_ICU_WUPEN_RTCALMWUPEN_Pos      (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
24298  #define R_ICU_WUPEN_RTCALMWUPEN_Msk      (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
24299  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos      (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
24300  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk      (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
24301  #define R_ICU_WUPEN_USBHSWUPEN_Pos       (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
24302  #define R_ICU_WUPEN_USBHSWUPEN_Msk       (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
24303  #define R_ICU_WUPEN_USBFSWUPEN_Pos       (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
24304  #define R_ICU_WUPEN_USBFSWUPEN_Msk       (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
24305  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos      (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
24306  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk      (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
24307  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos      (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
24308  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk      (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
24309  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos      (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
24310  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk      (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
24311  #define R_ICU_WUPEN_RIIC0WUPEN_Pos       (31UL)         /*!< RIIC0WUPEN (Bit 31)                                   */
24312  #define R_ICU_WUPEN_RIIC0WUPEN_Msk       (0x80000000UL) /*!< RIIC0WUPEN (Bitfield-Mask: 0x01)                      */
24313 /* ========================================================  WUPEN1  ========================================================= */
24314  #define R_ICU_WUPEN1_COMPHS0WUPEN_Pos    (3UL)          /*!< COMPHS0WUPEN (Bit 3)                                  */
24315  #define R_ICU_WUPEN1_COMPHS0WUPEN_Msk    (0x8UL)        /*!< COMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
24316  #define R_ICU_WUPEN1_ULP0UWUPEN_Pos      (8UL)          /*!< ULP0UWUPEN (Bit 8)                                    */
24317  #define R_ICU_WUPEN1_ULP0UWUPEN_Msk      (0x100UL)      /*!< ULP0UWUPEN (Bitfield-Mask: 0x01)                      */
24318  #define R_ICU_WUPEN1_ULP0AWUPEN_Pos      (9UL)          /*!< ULP0AWUPEN (Bit 9)                                    */
24319  #define R_ICU_WUPEN1_ULP0AWUPEN_Msk      (0x200UL)      /*!< ULP0AWUPEN (Bitfield-Mask: 0x01)                      */
24320  #define R_ICU_WUPEN1_ULP0BWUPEN_Pos      (10UL)         /*!< ULP0BWUPEN (Bit 10)                                   */
24321  #define R_ICU_WUPEN1_ULP0BWUPEN_Msk      (0x400UL)      /*!< ULP0BWUPEN (Bitfield-Mask: 0x01)                      */
24322  #define R_ICU_WUPEN1_I3CWUPEN_Pos        (11UL)         /*!< I3CWUPEN (Bit 11)                                     */
24323  #define R_ICU_WUPEN1_I3CWUPEN_Msk        (0x800UL)      /*!< I3CWUPEN (Bitfield-Mask: 0x01)                        */
24324  #define R_ICU_WUPEN1_ULP1UWUPEN_Pos      (12UL)         /*!< ULP1UWUPEN (Bit 12)                                   */
24325  #define R_ICU_WUPEN1_ULP1UWUPEN_Msk      (0x1000UL)     /*!< ULP1UWUPEN (Bitfield-Mask: 0x01)                      */
24326  #define R_ICU_WUPEN1_ULP1AWUPEN_Pos      (13UL)         /*!< ULP1AWUPEN (Bit 13)                                   */
24327  #define R_ICU_WUPEN1_ULP1AWUPEN_Msk      (0x2000UL)     /*!< ULP1AWUPEN (Bitfield-Mask: 0x01)                      */
24328  #define R_ICU_WUPEN1_ULP1BWUPEN_Pos      (14UL)         /*!< ULP1BWUPEN (Bit 14)                                   */
24329  #define R_ICU_WUPEN1_ULP1BWUPEN_Msk      (0x4000UL)     /*!< ULP1BWUPEN (Bitfield-Mask: 0x01)                      */
24330 /* =========================================================  IELSR  ========================================================= */
24331  #define R_ICU_IELSR_DTCE_Pos             (24UL)         /*!< DTCE (Bit 24)                                         */
24332  #define R_ICU_IELSR_DTCE_Msk             (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
24333  #define R_ICU_IELSR_IR_Pos               (16UL)         /*!< IR (Bit 16)                                           */
24334  #define R_ICU_IELSR_IR_Msk               (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
24335  #define R_ICU_IELSR_IELS_Pos             (0UL)          /*!< IELS (Bit 0)                                          */
24336  #define R_ICU_IELSR_IELS_Msk             (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
24337 
24338 /* =========================================================================================================================== */
24339 /* ================                                          R_IIC0                                           ================ */
24340 /* =========================================================================================================================== */
24341 
24342 /* =========================================================  ICCR1  ========================================================= */
24343  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
24344  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
24345  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
24346  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
24347  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
24348  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
24349  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
24350  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
24351  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
24352  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
24353  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
24354  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
24355  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
24356  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
24357  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
24358  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
24359 /* =========================================================  ICCR2  ========================================================= */
24360  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
24361  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
24362  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
24363  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
24364  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
24365  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
24366  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
24367  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
24368  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
24369  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
24370  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
24371  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
24372 /* =========================================================  ICMR1  ========================================================= */
24373  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
24374  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
24375  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
24376  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
24377  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
24378  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
24379  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
24380  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
24381 /* =========================================================  ICMR2  ========================================================= */
24382  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
24383  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
24384  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
24385  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
24386  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
24387  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
24388  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
24389  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
24390  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
24391  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
24392 /* =========================================================  ICMR3  ========================================================= */
24393  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
24394  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
24395  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
24396  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
24397  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
24398  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
24399  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
24400  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
24401  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
24402  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
24403  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
24404  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
24405  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
24406  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
24407 /* =========================================================  ICFER  ========================================================= */
24408  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
24409  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
24410  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
24411  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
24412  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
24413  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
24414  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
24415  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
24416  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
24417  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
24418  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
24419  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
24420  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
24421  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
24422  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
24423  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
24424 /* =========================================================  ICSER  ========================================================= */
24425  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
24426  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
24427  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
24428  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
24429  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
24430  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
24431  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
24432  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
24433  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
24434  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
24435  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
24436  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
24437 /* =========================================================  ICIER  ========================================================= */
24438  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
24439  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
24440  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
24441  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
24442  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
24443  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
24444  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
24445  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
24446  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
24447  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
24448  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
24449  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
24450  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
24451  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
24452  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
24453  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
24454 /* =========================================================  ICSR1  ========================================================= */
24455  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
24456  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
24457  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
24458  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
24459  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
24460  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
24461  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
24462  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
24463  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
24464  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
24465  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
24466  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
24467 /* =========================================================  ICSR2  ========================================================= */
24468  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
24469  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
24470  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
24471  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
24472  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
24473  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
24474  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
24475  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
24476  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
24477  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
24478  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
24479  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
24480  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
24481  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
24482  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
24483  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
24484 /* =========================================================  ICBRL  ========================================================= */
24485  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
24486  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
24487 /* =========================================================  ICBRH  ========================================================= */
24488  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
24489  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
24490 /* =========================================================  ICDRT  ========================================================= */
24491  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
24492  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
24493 /* =========================================================  ICDRR  ========================================================= */
24494  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
24495  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
24496 /* =========================================================  ICWUR  ========================================================= */
24497  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
24498  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
24499  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
24500  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
24501  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
24502  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
24503  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
24504  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
24505  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
24506  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
24507 /* ========================================================  ICWUR2  ========================================================= */
24508  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
24509  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
24510  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
24511  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
24512  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
24513  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
24514 
24515 /* =========================================================================================================================== */
24516 /* ================                                          R_IWDT                                           ================ */
24517 /* =========================================================================================================================== */
24518 
24519 /* ========================================================  IWDTRR  ========================================================= */
24520  #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
24521  #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
24522 /* ========================================================  IWDTCR  ========================================================= */
24523  #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
24524  #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
24525  #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
24526  #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
24527  #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
24528  #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
24529  #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
24530  #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
24531 /* ========================================================  IWDTSR  ========================================================= */
24532  #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
24533  #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
24534  #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
24535  #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
24536  #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
24537  #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
24538 /* ========================================================  IWDTRCR  ======================================================== */
24539  #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
24540  #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
24541 /* =======================================================  IWDTCSTPR  ======================================================= */
24542  #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
24543  #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
24544 
24545 /* =========================================================================================================================== */
24546 /* ================                                          R_I3C0                                           ================ */
24547 /* =========================================================================================================================== */
24548 
24549 /* =========================================================  PRTS  ========================================================== */
24550  #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
24551  #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
24552 /* =========================================================  CECTL  ========================================================= */
24553  #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
24554  #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
24555 /* =========================================================  BCTL  ========================================================== */
24556  #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
24557  #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
24558  #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
24559  #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
24560  #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
24561  #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
24562  #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
24563  #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
24564  #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
24565  #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
24566  #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
24567  #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
24568 /* ========================================================  MSDVAD  ========================================================= */
24569  #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
24570  #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
24571  #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
24572  #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
24573 /* ========================================================  RSTCTL  ========================================================= */
24574  #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
24575  #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
24576  #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
24577  #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
24578  #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
24579  #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
24580  #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
24581  #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
24582  #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
24583  #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
24584  #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
24585  #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
24586  #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
24587  #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
24588  #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
24589  #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
24590 /* =========================================================  PRSST  ========================================================= */
24591  #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
24592  #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
24593  #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
24594  #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
24595  #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
24596  #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
24597 /* =========================================================  INST  ========================================================== */
24598  #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
24599  #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
24600 /* =========================================================  INSTE  ========================================================= */
24601  #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
24602  #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
24603 /* =========================================================  INIE  ========================================================== */
24604  #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
24605  #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
24606 /* ========================================================  INSTFC  ========================================================= */
24607  #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
24608  #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
24609 /* =========================================================  DVCT  ========================================================== */
24610  #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
24611  #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
24612 /* ========================================================  IBINCTL  ======================================================== */
24613  #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
24614  #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
24615  #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
24616  #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
24617  #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
24618  #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
24619 /* =========================================================  BFCTL  ========================================================= */
24620  #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
24621  #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
24622  #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
24623  #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
24624  #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
24625  #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
24626  #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
24627  #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
24628  #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
24629  #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
24630  #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
24631  #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
24632  #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
24633  #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
24634 /* =========================================================  SVCTL  ========================================================= */
24635  #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
24636  #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
24637  #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
24638  #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
24639  #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
24640  #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
24641  #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
24642  #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
24643  #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
24644  #define R_I3C0_SVCTL_SVAEn_Msk         (0x10000UL)    /*!< SVAEn (Bitfield-Mask: 0x01)                           */
24645 /* =======================================================  REFCKCTL  ======================================================== */
24646  #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
24647  #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
24648 /* =========================================================  STDBR  ========================================================= */
24649  #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
24650  #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
24651  #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
24652  #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
24653  #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
24654  #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
24655  #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
24656  #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
24657  #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
24658  #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
24659 /* =========================================================  EXTBR  ========================================================= */
24660  #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
24661  #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
24662  #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
24663  #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
24664  #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
24665  #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
24666  #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
24667  #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
24668 /* ========================================================  BFRECDT  ======================================================== */
24669  #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
24670  #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
24671 /* ========================================================  BAVLCDT  ======================================================== */
24672  #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
24673  #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
24674 /* ========================================================  BIDLCDT  ======================================================== */
24675  #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
24676  #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
24677 /* ========================================================  OUTCTL  ========================================================= */
24678  #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
24679  #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
24680  #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
24681  #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
24682  #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
24683  #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
24684  #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
24685  #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
24686  #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
24687  #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
24688  #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
24689  #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
24690 /* =========================================================  INCTL  ========================================================= */
24691  #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
24692  #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
24693  #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
24694  #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
24695 /* ========================================================  TMOCTL  ========================================================= */
24696  #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
24697  #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
24698  #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
24699  #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
24700  #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
24701  #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
24702  #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
24703  #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
24704 /* =========================================================  WUCTL  ========================================================= */
24705  #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
24706  #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
24707  #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
24708  #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
24709  #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
24710  #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
24711  #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
24712  #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
24713 /* ========================================================  ACKCTL  ========================================================= */
24714  #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
24715  #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
24716  #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
24717  #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
24718  #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
24719  #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
24720 /* =======================================================  SCSTRCTL  ======================================================== */
24721  #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
24722  #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
24723  #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
24724  #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
24725 /* =======================================================  SCSTLCTL  ======================================================== */
24726  #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
24727  #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
24728  #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
24729  #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
24730  #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
24731  #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
24732  #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
24733  #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
24734  #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
24735  #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
24736 /* ========================================================  SVTDLG0  ======================================================== */
24737  #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
24738  #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
24739 /* ========================================================  CNDCTL  ========================================================= */
24740  #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
24741  #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
24742  #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
24743  #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
24744  #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
24745  #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
24746 /* ========================================================  NCMDQP  ========================================================= */
24747 /* ========================================================  NRSPQP  ========================================================= */
24748 /* ========================================================  NTDTBP0  ======================================================== */
24749 /* ========================================================  NIBIQP  ========================================================= */
24750 /* =========================================================  NRSQP  ========================================================= */
24751 /* ========================================================  NQTHCTL  ======================================================== */
24752  #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
24753  #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
24754  #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
24755  #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
24756  #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
24757  #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
24758  #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
24759  #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
24760 /* =======================================================  NTBTHCTL0  ======================================================= */
24761  #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
24762  #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
24763  #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
24764  #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
24765  #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
24766  #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
24767  #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
24768  #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
24769 /* =======================================================  NRQTHCTL  ======================================================== */
24770  #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
24771  #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
24772 /* ==========================================================  BST  ========================================================== */
24773  #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
24774  #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
24775  #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
24776  #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
24777  #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
24778  #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
24779  #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
24780  #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
24781  #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
24782  #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
24783  #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
24784  #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
24785  #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
24786  #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
24787 /* =========================================================  BSTE  ========================================================== */
24788  #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
24789  #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
24790  #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
24791  #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
24792  #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
24793  #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
24794  #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
24795  #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
24796  #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
24797  #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
24798  #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
24799  #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
24800  #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
24801  #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
24802 /* ==========================================================  BIE  ========================================================== */
24803  #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
24804  #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
24805  #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
24806  #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
24807  #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
24808  #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
24809  #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
24810  #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
24811  #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
24812  #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
24813  #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
24814  #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
24815  #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
24816  #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
24817 /* =========================================================  BSTFC  ========================================================= */
24818  #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
24819  #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
24820  #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
24821  #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
24822  #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
24823  #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
24824  #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
24825  #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
24826  #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
24827  #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
24828  #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
24829  #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
24830  #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
24831  #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
24832 /* =========================================================  NTST  ========================================================== */
24833  #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
24834  #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
24835  #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
24836  #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
24837  #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
24838  #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
24839  #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
24840  #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
24841  #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
24842  #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
24843  #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
24844  #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
24845  #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
24846  #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
24847  #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
24848  #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
24849 /* =========================================================  NTSTE  ========================================================= */
24850  #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
24851  #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
24852  #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
24853  #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
24854  #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
24855  #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
24856  #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
24857  #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
24858  #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
24859  #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
24860  #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
24861  #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
24862  #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
24863  #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
24864  #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
24865  #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
24866 /* =========================================================  NTIE  ========================================================== */
24867  #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
24868  #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
24869  #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
24870  #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
24871  #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
24872  #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
24873  #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
24874  #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
24875  #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
24876  #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
24877  #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
24878  #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
24879  #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
24880  #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
24881  #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
24882  #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
24883 /* ========================================================  NTSTFC  ========================================================= */
24884  #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
24885  #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
24886  #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
24887  #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
24888  #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
24889  #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
24890  #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
24891  #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
24892  #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
24893  #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
24894  #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
24895  #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
24896  #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
24897  #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
24898  #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
24899  #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
24900 /* =========================================================  BCST  ========================================================== */
24901  #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
24902  #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
24903  #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
24904  #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
24905  #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
24906  #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
24907 /* =========================================================  SVST  ========================================================== */
24908  #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
24909  #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
24910  #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
24911  #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
24912  #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
24913  #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
24914  #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
24915  #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
24916  #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
24917  #define R_I3C0_SVST_SVAFn_Msk          (0x10000UL)    /*!< SVAFn (Bitfield-Mask: 0x01)                           */
24918 /* =========================================================  WUST  ========================================================== */
24919  #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
24920  #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
24921 /* ========================================================  DATBAS0  ======================================================== */
24922  #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24923  #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24924  #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24925  #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24926  #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24927  #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24928  #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24929  #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24930  #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24931  #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24932  #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24933  #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24934  #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24935  #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24936  #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24937  #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24938 /* ========================================================  DATBAS1  ======================================================== */
24939  #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24940  #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24941  #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24942  #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24943  #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24944  #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24945  #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24946  #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24947  #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24948  #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24949  #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24950  #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24951  #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24952  #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24953  #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24954  #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24955 /* ========================================================  DATBAS2  ======================================================== */
24956  #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24957  #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24958  #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24959  #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24960  #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24961  #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24962  #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24963  #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24964  #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24965  #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24966  #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24967  #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24968  #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24969  #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24970  #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24971  #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24972 /* ========================================================  DATBAS3  ======================================================== */
24973  #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24974  #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24975  #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24976  #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24977  #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24978  #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24979  #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24980  #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24981  #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24982  #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24983  #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24984  #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24985  #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24986  #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24987  #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24988  #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24989 /* =======================================================  EXDATBAS  ======================================================== */
24990  #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
24991  #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
24992  #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
24993  #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
24994  #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
24995  #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
24996  #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
24997  #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
24998 /* =======================================================  SDATBAS0  ======================================================== */
24999  #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
25000  #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
25001  #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
25002  #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
25003  #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
25004  #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
25005  #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
25006  #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
25007 /* =======================================================  SDATBAS1  ======================================================== */
25008  #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
25009  #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
25010  #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
25011  #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
25012  #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
25013  #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
25014  #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
25015  #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
25016 /* =======================================================  SDATBAS2  ======================================================== */
25017  #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
25018  #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
25019  #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
25020  #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
25021  #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
25022  #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
25023  #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
25024  #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
25025 /* ========================================================  MSDCT0  ========================================================= */
25026  #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
25027  #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
25028  #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
25029  #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
25030  #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
25031  #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
25032  #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
25033  #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
25034  #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
25035  #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
25036 /* ========================================================  MSDCT1  ========================================================= */
25037  #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
25038  #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
25039  #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
25040  #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
25041  #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
25042  #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
25043  #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
25044  #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
25045  #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
25046  #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
25047 /* ========================================================  MSDCT2  ========================================================= */
25048  #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
25049  #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
25050  #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
25051  #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
25052  #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
25053  #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
25054  #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
25055  #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
25056  #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
25057  #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
25058 /* ========================================================  MSDCT3  ========================================================= */
25059  #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
25060  #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
25061  #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
25062  #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
25063  #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
25064  #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
25065  #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
25066  #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
25067  #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
25068  #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
25069 /* =========================================================  SVDCT  ========================================================= */
25070  #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
25071  #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
25072  #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
25073  #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
25074  #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
25075  #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
25076  #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
25077  #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
25078  #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
25079  #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
25080  #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
25081  #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
25082 /* =======================================================  SDCTPIDL  ======================================================== */
25083 /* =======================================================  SDCTPIDH  ======================================================== */
25084 /* ========================================================  SVDVAD0  ======================================================== */
25085  #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
25086  #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
25087  #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
25088  #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
25089  #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
25090  #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
25091  #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
25092  #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
25093 /* ========================================================  CSECMD  ========================================================= */
25094  #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
25095  #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
25096  #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
25097  #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
25098  #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
25099  #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
25100 /* ========================================================  CEACTST  ======================================================== */
25101  #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
25102  #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
25103 /* =========================================================  CMWLG  ========================================================= */
25104  #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
25105  #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
25106 /* =========================================================  CMRLG  ========================================================= */
25107  #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
25108  #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
25109  #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
25110  #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
25111 /* ========================================================  CETSTMD  ======================================================== */
25112  #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
25113  #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
25114 /* ========================================================  CGDVST  ========================================================= */
25115  #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
25116  #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
25117  #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
25118  #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
25119  #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
25120  #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
25121  #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
25122  #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
25123 /* ========================================================  CMDSPW  ========================================================= */
25124  #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
25125  #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
25126 /* ========================================================  CMDSPR  ========================================================= */
25127  #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
25128  #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
25129  #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
25130  #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
25131 /* ========================================================  CMDSPT  ========================================================= */
25132  #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
25133  #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
25134  #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
25135  #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
25136 /* =========================================================  CETSM  ========================================================= */
25137  #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
25138  #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
25139  #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
25140  #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
25141 /* ========================================================  BITCNT  ========================================================= */
25142  #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
25143  #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
25144  #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
25145  #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
25146 /* ========================================================  NQSTLV  ========================================================= */
25147  #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
25148  #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
25149  #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
25150  #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
25151  #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
25152  #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
25153  #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
25154  #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
25155 /* =======================================================  NDBSTLV0  ======================================================== */
25156  #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
25157  #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
25158  #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
25159  #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
25160 /* =======================================================  NRSQSTLV  ======================================================== */
25161  #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
25162  #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
25163 /* ========================================================  PRSTDBG  ======================================================== */
25164  #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
25165  #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
25166  #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
25167  #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
25168  #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
25169  #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
25170  #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
25171  #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
25172 /* =======================================================  MSERRCNT  ======================================================== */
25173  #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
25174  #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
25175 
25176 /* =========================================================================================================================== */
25177 /* ================                                        R_MPU_MMPU                                         ================ */
25178 /* =========================================================================================================================== */
25179 
25180 /* ==========================================================  OAD  ========================================================== */
25181  #define R_MPU_MMPU_OAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
25182  #define R_MPU_MMPU_OAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25183  #define R_MPU_MMPU_OAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
25184  #define R_MPU_MMPU_OAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
25185 /* =========================================================  OADPT  ========================================================= */
25186  #define R_MPU_MMPU_OADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
25187  #define R_MPU_MMPU_OADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25188  #define R_MPU_MMPU_OADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
25189  #define R_MPU_MMPU_OADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
25190 
25191 /* =========================================================================================================================== */
25192 /* ================                                        R_MPU_SPMON                                        ================ */
25193 /* =========================================================================================================================== */
25194 
25195 /* =========================================================================================================================== */
25196 /* ================                                          R_MSTP                                           ================ */
25197 /* =========================================================================================================================== */
25198 
25199 /* ========================================================  MSTPCRA  ======================================================== */
25200  #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
25201  #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
25202 /* ========================================================  MSTPCRB  ======================================================== */
25203  #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
25204  #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
25205 /* ========================================================  MSTPCRC  ======================================================== */
25206  #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
25207  #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
25208 /* ========================================================  MSTPCRD  ======================================================== */
25209  #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
25210  #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
25211 /* ========================================================  MSTPCRE  ======================================================== */
25212  #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
25213  #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
25214 /* =======================================================  LSMRWDIS  ======================================================== */
25215  #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
25216  #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
25217  #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
25218  #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
25219  #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
25220  #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
25221  #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
25222  #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
25223  #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
25224  #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
25225 
25226 /* =========================================================================================================================== */
25227 /* ================                                          R_PORT0                                          ================ */
25228 /* =========================================================================================================================== */
25229 
25230 /* ========================================================  PCNTR1  ========================================================= */
25231  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
25232  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
25233  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
25234  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
25235 /* ==========================================================  PDR  ========================================================== */
25236  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
25237  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
25238 /* =========================================================  PODR  ========================================================== */
25239  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
25240  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
25241 /* ========================================================  PCNTR2  ========================================================= */
25242  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
25243  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
25244  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
25245  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
25246 /* =========================================================  PIDR  ========================================================== */
25247  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
25248  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
25249 /* =========================================================  EIDR  ========================================================== */
25250  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
25251  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
25252 /* ========================================================  PCNTR3  ========================================================= */
25253  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
25254  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
25255  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
25256  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
25257 /* =========================================================  POSR  ========================================================== */
25258  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
25259  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
25260 /* =========================================================  PORR  ========================================================== */
25261  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
25262  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
25263 /* ========================================================  PCNTR4  ========================================================= */
25264  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
25265  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
25266  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
25267  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
25268 /* =========================================================  EOSR  ========================================================== */
25269  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
25270  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
25271 /* =========================================================  EORR  ========================================================== */
25272  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
25273  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
25274 
25275 /* =========================================================================================================================== */
25276 /* ================                                           R_PFS                                           ================ */
25277 /* =========================================================================================================================== */
25278 
25279 /* =========================================================================================================================== */
25280 /* ================                                          R_PMISC                                          ================ */
25281 /* =========================================================================================================================== */
25282 
25283 /* ========================================================  PFENET  ========================================================= */
25284  #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
25285  #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
25286 /* =========================================================  PWPR  ========================================================== */
25287  #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
25288  #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
25289  #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
25290  #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
25291 /* =========================================================  PWPRS  ========================================================= */
25292  #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
25293  #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
25294  #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
25295  #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
25296 
25297 /* =========================================================================================================================== */
25298 /* ================                                           R_RTC                                           ================ */
25299 /* =========================================================================================================================== */
25300 
25301 /* ========================================================  R64CNT  ========================================================= */
25302  #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
25303  #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
25304  #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
25305  #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
25306  #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
25307  #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
25308  #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
25309  #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
25310  #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
25311  #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
25312  #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
25313  #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
25314  #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
25315  #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
25316 /* =========================================================  BCNT0  ========================================================= */
25317  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
25318  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
25319 /* ========================================================  RSECCNT  ======================================================== */
25320  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
25321  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
25322  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
25323  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
25324 /* =========================================================  BCNT1  ========================================================= */
25325  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
25326  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
25327 /* ========================================================  RMINCNT  ======================================================== */
25328  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
25329  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
25330  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
25331  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
25332 /* =========================================================  BCNT2  ========================================================= */
25333  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
25334  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
25335 /* ========================================================  RHRCNT  ========================================================= */
25336  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
25337  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
25338  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
25339  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
25340  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
25341  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
25342 /* =========================================================  BCNT3  ========================================================= */
25343  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
25344  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
25345 /* ========================================================  RWKCNT  ========================================================= */
25346  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
25347  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
25348 /* ========================================================  RDAYCNT  ======================================================== */
25349  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
25350  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
25351  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
25352  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
25353 /* ========================================================  RMONCNT  ======================================================== */
25354  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
25355  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
25356  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
25357  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
25358 /* ========================================================  RYRCNT  ========================================================= */
25359  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
25360  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
25361  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
25362  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
25363 /* ========================================================  BCNT0AR  ======================================================== */
25364  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
25365  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
25366 /* ========================================================  RSECAR  ========================================================= */
25367  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25368  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25369  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
25370  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
25371  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
25372  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
25373 /* ========================================================  BCNT1AR  ======================================================== */
25374  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
25375  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
25376 /* ========================================================  RMINAR  ========================================================= */
25377  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25378  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25379  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
25380  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
25381  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
25382  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
25383 /* ========================================================  BCNT2AR  ======================================================== */
25384  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
25385  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
25386 /* =========================================================  RHRAR  ========================================================= */
25387  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
25388  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25389  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
25390  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
25391  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
25392  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
25393  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
25394  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
25395 /* ========================================================  BCNT3AR  ======================================================== */
25396  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
25397  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
25398 /* =========================================================  RWKAR  ========================================================= */
25399  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
25400  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25401  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
25402  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
25403 /* =======================================================  BCNT0AER  ======================================================== */
25404  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25405  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25406 /* ========================================================  RDAYAR  ========================================================= */
25407  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25408  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25409  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
25410  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
25411  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
25412  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
25413 /* =======================================================  BCNT1AER  ======================================================== */
25414  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25415  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25416 /* ========================================================  RMONAR  ========================================================= */
25417  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
25418  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25419  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
25420  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
25421  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
25422  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
25423 /* =======================================================  BCNT2AER  ======================================================== */
25424  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25425  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25426 /* =========================================================  RYRAR  ========================================================= */
25427  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
25428  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
25429  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
25430  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
25431 /* =======================================================  BCNT3AER  ======================================================== */
25432  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
25433  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
25434 /* ========================================================  RYRAREN  ======================================================== */
25435  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
25436  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
25437 /* =========================================================  RCR1  ========================================================== */
25438  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
25439  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
25440  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
25441  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
25442  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
25443  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
25444  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
25445  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
25446  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
25447  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
25448 /* =========================================================  RCR2  ========================================================== */
25449  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
25450  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
25451  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
25452  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
25453  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
25454  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
25455  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
25456  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
25457  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
25458  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
25459  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
25460  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
25461  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
25462  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
25463  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
25464  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
25465 /* =========================================================  RCR4  ========================================================== */
25466  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
25467  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
25468  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
25469  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
25470 /* =========================================================  RFRH  ========================================================== */
25471  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
25472  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
25473 /* =========================================================  RFRL  ========================================================== */
25474  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
25475  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
25476 /* =========================================================  RADJ  ========================================================== */
25477  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
25478  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
25479  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
25480  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
25481 
25482 /* =========================================================================================================================== */
25483 /* ================                                          R_SCI0                                           ================ */
25484 /* =========================================================================================================================== */
25485 
25486 /* ==========================================================  SMR  ========================================================== */
25487  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
25488  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
25489  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
25490  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
25491  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
25492  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
25493  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
25494  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
25495  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
25496  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
25497  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
25498  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
25499  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
25500  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
25501 /* =======================================================  SMR_SMCI  ======================================================== */
25502  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
25503  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
25504  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
25505  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
25506  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
25507  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
25508  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
25509  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
25510  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
25511  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
25512  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
25513  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
25514 /* ==========================================================  BRR  ========================================================== */
25515  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
25516  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
25517 /* ==========================================================  SCR  ========================================================== */
25518  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
25519  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
25520  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
25521  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
25522  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
25523  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
25524  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
25525  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
25526  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
25527  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
25528  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
25529  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
25530  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
25531  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
25532 /* =======================================================  SCR_SMCI  ======================================================== */
25533  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
25534  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
25535  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
25536  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
25537  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
25538  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
25539  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
25540  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
25541  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
25542  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
25543  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
25544  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
25545  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
25546  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
25547 /* ==========================================================  TDR  ========================================================== */
25548  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
25549  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
25550 /* ==========================================================  SSR  ========================================================== */
25551  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
25552  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
25553  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
25554  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
25555  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
25556  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25557  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
25558  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
25559  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
25560  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25561  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
25562  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
25563  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
25564  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
25565  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
25566  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
25567 /* =======================================================  SSR_FIFO  ======================================================== */
25568  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
25569  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
25570  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
25571  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
25572  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
25573  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25574  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
25575  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
25576  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
25577  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25578  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
25579  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
25580  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
25581  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
25582 /* =======================================================  SSR_SMCI  ======================================================== */
25583  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
25584  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
25585  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
25586  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
25587  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
25588  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25589  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
25590  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
25591  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
25592  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25593  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
25594  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
25595  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
25596  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
25597  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
25598  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
25599 /* ==========================================================  RDR  ========================================================== */
25600  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
25601  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
25602 /* =========================================================  SCMR  ========================================================== */
25603  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
25604  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
25605  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
25606  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
25607  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
25608  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
25609  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
25610  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
25611  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
25612  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
25613 /* =========================================================  SEMR  ========================================================== */
25614  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
25615  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
25616  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
25617  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
25618  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
25619  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
25620  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
25621  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
25622  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
25623  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
25624  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
25625  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
25626  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
25627  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
25628  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
25629  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
25630 /* =========================================================  SNFR  ========================================================== */
25631  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
25632  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
25633 /* =========================================================  SIMR1  ========================================================= */
25634  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
25635  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
25636  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
25637  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
25638 /* =========================================================  SIMR2  ========================================================= */
25639  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
25640  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
25641  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
25642  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
25643  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
25644  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
25645 /* =========================================================  SIMR3  ========================================================= */
25646  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
25647  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
25648  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
25649  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
25650  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
25651  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
25652  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
25653  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
25654  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
25655  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
25656  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
25657  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
25658 /* =========================================================  SISR  ========================================================== */
25659  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
25660  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
25661 /* =========================================================  SPMR  ========================================================== */
25662  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
25663  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
25664  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
25665  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
25666  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
25667  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
25668  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
25669  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
25670  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
25671  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
25672  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
25673  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
25674  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
25675  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
25676 /* =========================================================  TDRHL  ========================================================= */
25677  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
25678  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
25679 /* ========================================================  FTDRHL  ========================================================= */
25680  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
25681  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
25682  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
25683  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
25684 /* =========================================================  FTDRH  ========================================================= */
25685  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
25686  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
25687  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
25688  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
25689 /* =========================================================  FTDRL  ========================================================= */
25690  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
25691  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
25692 /* =========================================================  RDRHL  ========================================================= */
25693  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
25694  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
25695 /* ========================================================  FRDRHL  ========================================================= */
25696  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
25697  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
25698  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
25699  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
25700  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
25701  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
25702  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
25703  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
25704  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
25705  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
25706  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
25707  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
25708  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
25709  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
25710 /* =========================================================  FRDRH  ========================================================= */
25711  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
25712  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
25713  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
25714  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25715  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
25716  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
25717  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
25718  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25719  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
25720  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
25721  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
25722  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
25723  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
25724  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
25725 /* =========================================================  FRDRL  ========================================================= */
25726  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
25727  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
25728 /* =========================================================  MDDR  ========================================================== */
25729  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
25730  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
25731 /* =========================================================  DCCR  ========================================================== */
25732  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
25733  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
25734  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
25735  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
25736  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
25737  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
25738  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
25739  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
25740  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
25741  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
25742 /* ==========================================================  FCR  ========================================================== */
25743  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
25744  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
25745  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
25746  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
25747  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
25748  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
25749  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
25750  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
25751  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
25752  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
25753  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
25754  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
25755  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
25756  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
25757 /* ==========================================================  FDR  ========================================================== */
25758  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
25759  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
25760  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
25761  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
25762 /* ==========================================================  LSR  ========================================================== */
25763  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
25764  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
25765  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
25766  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
25767  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
25768  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
25769 /* ==========================================================  CDR  ========================================================== */
25770  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
25771  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
25772 /* =========================================================  SPTR  ========================================================== */
25773  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
25774  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
25775  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
25776  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
25777  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
25778  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
25779  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
25780  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
25781  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
25782  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
25783  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
25784  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
25785  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
25786  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
25787 /* =========================================================  ACTR  ========================================================== */
25788  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
25789  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
25790  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
25791  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
25792  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
25793  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
25794  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
25795  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
25796 /* =========================================================  ESMER  ========================================================= */
25797  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
25798  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
25799 /* ==========================================================  CR0  ========================================================== */
25800  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
25801  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
25802  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
25803  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
25804  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
25805  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
25806 /* ==========================================================  CR1  ========================================================== */
25807  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
25808  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
25809  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
25810  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
25811  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
25812  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
25813  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
25814  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
25815  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
25816  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
25817 /* ==========================================================  CR2  ========================================================== */
25818  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
25819  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
25820  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
25821  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
25822  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
25823  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
25824 /* ==========================================================  CR3  ========================================================== */
25825  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
25826  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
25827 /* ==========================================================  PCR  ========================================================== */
25828  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
25829  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
25830  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
25831  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
25832  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
25833  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
25834 /* ==========================================================  ICR  ========================================================== */
25835  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
25836  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
25837  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
25838  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
25839  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
25840  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
25841  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
25842  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
25843  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
25844  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
25845  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
25846  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
25847 /* ==========================================================  STR  ========================================================== */
25848  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
25849  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
25850  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
25851  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
25852  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
25853  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
25854  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
25855  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
25856  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
25857  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
25858  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
25859  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
25860 /* =========================================================  STCR  ========================================================== */
25861  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
25862  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
25863  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
25864  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
25865  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
25866  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
25867  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
25868  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
25869  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
25870  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
25871  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
25872  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
25873 /* =========================================================  CF0DR  ========================================================= */
25874 /* =========================================================  CF0CR  ========================================================= */
25875  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
25876  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
25877  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
25878  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
25879  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
25880  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
25881  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
25882  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
25883  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
25884  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
25885  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
25886  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
25887  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
25888  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
25889  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
25890  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
25891 /* =========================================================  CF0RR  ========================================================= */
25892 /* ========================================================  PCF1DR  ========================================================= */
25893 /* ========================================================  SCF1DR  ========================================================= */
25894 /* =========================================================  CF1CR  ========================================================= */
25895  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
25896  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
25897  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
25898  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
25899  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
25900  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
25901  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
25902  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
25903  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
25904  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
25905  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
25906  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
25907  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
25908  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
25909  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
25910  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
25911 /* =========================================================  CF1RR  ========================================================= */
25912 /* ==========================================================  TCR  ========================================================== */
25913  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
25914  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
25915 /* ==========================================================  TMR  ========================================================== */
25916  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
25917  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
25918  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
25919  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
25920  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
25921  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
25922 /* =========================================================  TPRE  ========================================================== */
25923 /* =========================================================  TCNT  ========================================================== */
25924 
25925 /* =========================================================================================================================== */
25926 /* ================                                          R_SDHI0                                          ================ */
25927 /* =========================================================================================================================== */
25928 
25929 /* ========================================================  SD_CMD  ========================================================= */
25930  #define R_SDHI0_SD_CMD_CMD12AT_Pos              (14UL)         /*!< CMD12AT (Bit 14)                                      */
25931  #define R_SDHI0_SD_CMD_CMD12AT_Msk              (0xc000UL)     /*!< CMD12AT (Bitfield-Mask: 0x03)                         */
25932  #define R_SDHI0_SD_CMD_TRSTP_Pos                (13UL)         /*!< TRSTP (Bit 13)                                        */
25933  #define R_SDHI0_SD_CMD_TRSTP_Msk                (0x2000UL)     /*!< TRSTP (Bitfield-Mask: 0x01)                           */
25934  #define R_SDHI0_SD_CMD_CMDRW_Pos                (12UL)         /*!< CMDRW (Bit 12)                                        */
25935  #define R_SDHI0_SD_CMD_CMDRW_Msk                (0x1000UL)     /*!< CMDRW (Bitfield-Mask: 0x01)                           */
25936  #define R_SDHI0_SD_CMD_CMDTP_Pos                (11UL)         /*!< CMDTP (Bit 11)                                        */
25937  #define R_SDHI0_SD_CMD_CMDTP_Msk                (0x800UL)      /*!< CMDTP (Bitfield-Mask: 0x01)                           */
25938  #define R_SDHI0_SD_CMD_RSPTP_Pos                (8UL)          /*!< RSPTP (Bit 8)                                         */
25939  #define R_SDHI0_SD_CMD_RSPTP_Msk                (0x700UL)      /*!< RSPTP (Bitfield-Mask: 0x07)                           */
25940  #define R_SDHI0_SD_CMD_ACMD_Pos                 (6UL)          /*!< ACMD (Bit 6)                                          */
25941  #define R_SDHI0_SD_CMD_ACMD_Msk                 (0xc0UL)       /*!< ACMD (Bitfield-Mask: 0x03)                            */
25942  #define R_SDHI0_SD_CMD_CMDIDX_Pos               (0UL)          /*!< CMDIDX (Bit 0)                                        */
25943  #define R_SDHI0_SD_CMD_CMDIDX_Msk               (0x3fUL)       /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
25944 /* ========================================================  SD_ARG  ========================================================= */
25945  #define R_SDHI0_SD_ARG_SD_ARG_Pos               (0UL)          /*!< SD_ARG (Bit 0)                                        */
25946  #define R_SDHI0_SD_ARG_SD_ARG_Msk               (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff)                    */
25947 /* ========================================================  SD_ARG1  ======================================================== */
25948  #define R_SDHI0_SD_ARG1_SD_ARG1_Pos             (0UL)          /*!< SD_ARG1 (Bit 0)                                       */
25949  #define R_SDHI0_SD_ARG1_SD_ARG1_Msk             (0xffffUL)     /*!< SD_ARG1 (Bitfield-Mask: 0xffff)                       */
25950 /* ========================================================  SD_STOP  ======================================================== */
25951  #define R_SDHI0_SD_STOP_SEC_Pos                 (8UL)          /*!< SEC (Bit 8)                                           */
25952  #define R_SDHI0_SD_STOP_SEC_Msk                 (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
25953  #define R_SDHI0_SD_STOP_STP_Pos                 (0UL)          /*!< STP (Bit 0)                                           */
25954  #define R_SDHI0_SD_STOP_STP_Msk                 (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
25955 /* =======================================================  SD_SECCNT  ======================================================= */
25956  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos         (0UL)          /*!< SD_SECCNT (Bit 0)                                     */
25957  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk         (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff)                 */
25958 /* =======================================================  SD_RSP10  ======================================================== */
25959  #define R_SDHI0_SD_RSP10_SD_RSP10_Pos           (0UL)          /*!< SD_RSP10 (Bit 0)                                      */
25960  #define R_SDHI0_SD_RSP10_SD_RSP10_Msk           (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff)                  */
25961 /* ========================================================  SD_RSP1  ======================================================== */
25962  #define R_SDHI0_SD_RSP1_SD_RSP1_Pos             (0UL)          /*!< SD_RSP1 (Bit 0)                                       */
25963  #define R_SDHI0_SD_RSP1_SD_RSP1_Msk             (0xffffUL)     /*!< SD_RSP1 (Bitfield-Mask: 0xffff)                       */
25964 /* =======================================================  SD_RSP32  ======================================================== */
25965  #define R_SDHI0_SD_RSP32_SD_RSP32_Pos           (0UL)          /*!< SD_RSP32 (Bit 0)                                      */
25966  #define R_SDHI0_SD_RSP32_SD_RSP32_Msk           (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff)                  */
25967 /* ========================================================  SD_RSP3  ======================================================== */
25968  #define R_SDHI0_SD_RSP3_SD_RSP3_Pos             (0UL)          /*!< SD_RSP3 (Bit 0)                                       */
25969  #define R_SDHI0_SD_RSP3_SD_RSP3_Msk             (0xffffUL)     /*!< SD_RSP3 (Bitfield-Mask: 0xffff)                       */
25970 /* =======================================================  SD_RSP54  ======================================================== */
25971  #define R_SDHI0_SD_RSP54_SD_RSP54_Pos           (0UL)          /*!< SD_RSP54 (Bit 0)                                      */
25972  #define R_SDHI0_SD_RSP54_SD_RSP54_Msk           (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff)                  */
25973 /* ========================================================  SD_RSP5  ======================================================== */
25974  #define R_SDHI0_SD_RSP5_SD_RSP5_Pos             (0UL)          /*!< SD_RSP5 (Bit 0)                                       */
25975  #define R_SDHI0_SD_RSP5_SD_RSP5_Msk             (0xffffUL)     /*!< SD_RSP5 (Bitfield-Mask: 0xffff)                       */
25976 /* =======================================================  SD_RSP76  ======================================================== */
25977  #define R_SDHI0_SD_RSP76_SD_RSP76_Pos           (0UL)          /*!< SD_RSP76 (Bit 0)                                      */
25978  #define R_SDHI0_SD_RSP76_SD_RSP76_Msk           (0xffffffUL)   /*!< SD_RSP76 (Bitfield-Mask: 0xffffff)                    */
25979 /* ========================================================  SD_RSP7  ======================================================== */
25980  #define R_SDHI0_SD_RSP7_SD_RSP7_Pos             (0UL)          /*!< SD_RSP7 (Bit 0)                                       */
25981  #define R_SDHI0_SD_RSP7_SD_RSP7_Msk             (0xffUL)       /*!< SD_RSP7 (Bitfield-Mask: 0xff)                         */
25982 /* =======================================================  SD_INFO1  ======================================================== */
25983  #define R_SDHI0_SD_INFO1_SDD3MON_Pos            (10UL)         /*!< SDD3MON (Bit 10)                                      */
25984  #define R_SDHI0_SD_INFO1_SDD3MON_Msk            (0x400UL)      /*!< SDD3MON (Bitfield-Mask: 0x01)                         */
25985  #define R_SDHI0_SD_INFO1_SDD3IN_Pos             (9UL)          /*!< SDD3IN (Bit 9)                                        */
25986  #define R_SDHI0_SD_INFO1_SDD3IN_Msk             (0x200UL)      /*!< SDD3IN (Bitfield-Mask: 0x01)                          */
25987  #define R_SDHI0_SD_INFO1_SDD3RM_Pos             (8UL)          /*!< SDD3RM (Bit 8)                                        */
25988  #define R_SDHI0_SD_INFO1_SDD3RM_Msk             (0x100UL)      /*!< SDD3RM (Bitfield-Mask: 0x01)                          */
25989  #define R_SDHI0_SD_INFO1_SDWPMON_Pos            (7UL)          /*!< SDWPMON (Bit 7)                                       */
25990  #define R_SDHI0_SD_INFO1_SDWPMON_Msk            (0x80UL)       /*!< SDWPMON (Bitfield-Mask: 0x01)                         */
25991  #define R_SDHI0_SD_INFO1_SDCDMON_Pos            (5UL)          /*!< SDCDMON (Bit 5)                                       */
25992  #define R_SDHI0_SD_INFO1_SDCDMON_Msk            (0x20UL)       /*!< SDCDMON (Bitfield-Mask: 0x01)                         */
25993  #define R_SDHI0_SD_INFO1_SDCDIN_Pos             (4UL)          /*!< SDCDIN (Bit 4)                                        */
25994  #define R_SDHI0_SD_INFO1_SDCDIN_Msk             (0x10UL)       /*!< SDCDIN (Bitfield-Mask: 0x01)                          */
25995  #define R_SDHI0_SD_INFO1_SDCDRM_Pos             (3UL)          /*!< SDCDRM (Bit 3)                                        */
25996  #define R_SDHI0_SD_INFO1_SDCDRM_Msk             (0x8UL)        /*!< SDCDRM (Bitfield-Mask: 0x01)                          */
25997  #define R_SDHI0_SD_INFO1_ACEND_Pos              (2UL)          /*!< ACEND (Bit 2)                                         */
25998  #define R_SDHI0_SD_INFO1_ACEND_Msk              (0x4UL)        /*!< ACEND (Bitfield-Mask: 0x01)                           */
25999  #define R_SDHI0_SD_INFO1_RSPEND_Pos             (0UL)          /*!< RSPEND (Bit 0)                                        */
26000  #define R_SDHI0_SD_INFO1_RSPEND_Msk             (0x1UL)        /*!< RSPEND (Bitfield-Mask: 0x01)                          */
26001 /* =======================================================  SD_INFO2  ======================================================== */
26002  #define R_SDHI0_SD_INFO2_ILA_Pos                (15UL)         /*!< ILA (Bit 15)                                          */
26003  #define R_SDHI0_SD_INFO2_ILA_Msk                (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
26004  #define R_SDHI0_SD_INFO2_CBSY_Pos               (14UL)         /*!< CBSY (Bit 14)                                         */
26005  #define R_SDHI0_SD_INFO2_CBSY_Msk               (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
26006  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos      (13UL)         /*!< SD_CLK_CTRLEN (Bit 13)                                */
26007  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk      (0x2000UL)     /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01)                   */
26008  #define R_SDHI0_SD_INFO2_BWE_Pos                (9UL)          /*!< BWE (Bit 9)                                           */
26009  #define R_SDHI0_SD_INFO2_BWE_Msk                (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
26010  #define R_SDHI0_SD_INFO2_BRE_Pos                (8UL)          /*!< BRE (Bit 8)                                           */
26011  #define R_SDHI0_SD_INFO2_BRE_Msk                (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
26012  #define R_SDHI0_SD_INFO2_SDD0MON_Pos            (7UL)          /*!< SDD0MON (Bit 7)                                       */
26013  #define R_SDHI0_SD_INFO2_SDD0MON_Msk            (0x80UL)       /*!< SDD0MON (Bitfield-Mask: 0x01)                         */
26014  #define R_SDHI0_SD_INFO2_RSPTO_Pos              (6UL)          /*!< RSPTO (Bit 6)                                         */
26015  #define R_SDHI0_SD_INFO2_RSPTO_Msk              (0x40UL)       /*!< RSPTO (Bitfield-Mask: 0x01)                           */
26016  #define R_SDHI0_SD_INFO2_ILR_Pos                (5UL)          /*!< ILR (Bit 5)                                           */
26017  #define R_SDHI0_SD_INFO2_ILR_Msk                (0x20UL)       /*!< ILR (Bitfield-Mask: 0x01)                             */
26018  #define R_SDHI0_SD_INFO2_ILW_Pos                (4UL)          /*!< ILW (Bit 4)                                           */
26019  #define R_SDHI0_SD_INFO2_ILW_Msk                (0x10UL)       /*!< ILW (Bitfield-Mask: 0x01)                             */
26020  #define R_SDHI0_SD_INFO2_DTO_Pos                (3UL)          /*!< DTO (Bit 3)                                           */
26021  #define R_SDHI0_SD_INFO2_DTO_Msk                (0x8UL)        /*!< DTO (Bitfield-Mask: 0x01)                             */
26022  #define R_SDHI0_SD_INFO2_ENDE_Pos               (2UL)          /*!< ENDE (Bit 2)                                          */
26023  #define R_SDHI0_SD_INFO2_ENDE_Msk               (0x4UL)        /*!< ENDE (Bitfield-Mask: 0x01)                            */
26024  #define R_SDHI0_SD_INFO2_CRCE_Pos               (1UL)          /*!< CRCE (Bit 1)                                          */
26025  #define R_SDHI0_SD_INFO2_CRCE_Msk               (0x2UL)        /*!< CRCE (Bitfield-Mask: 0x01)                            */
26026  #define R_SDHI0_SD_INFO2_CMDE_Pos               (0UL)          /*!< CMDE (Bit 0)                                          */
26027  #define R_SDHI0_SD_INFO2_CMDE_Msk               (0x1UL)        /*!< CMDE (Bitfield-Mask: 0x01)                            */
26028 /* =====================================================  SD_INFO1_MASK  ===================================================== */
26029  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos       (9UL)          /*!< SDD3INM (Bit 9)                                       */
26030  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk       (0x200UL)      /*!< SDD3INM (Bitfield-Mask: 0x01)                         */
26031  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos       (8UL)          /*!< SDD3RMM (Bit 8)                                       */
26032  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk       (0x100UL)      /*!< SDD3RMM (Bitfield-Mask: 0x01)                         */
26033  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos       (4UL)          /*!< SDCDINM (Bit 4)                                       */
26034  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk       (0x10UL)       /*!< SDCDINM (Bitfield-Mask: 0x01)                         */
26035  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos       (3UL)          /*!< SDCDRMM (Bit 3)                                       */
26036  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk       (0x8UL)        /*!< SDCDRMM (Bitfield-Mask: 0x01)                         */
26037  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos        (2UL)          /*!< ACENDM (Bit 2)                                        */
26038  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk        (0x4UL)        /*!< ACENDM (Bitfield-Mask: 0x01)                          */
26039  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos       (0UL)          /*!< RSPENDM (Bit 0)                                       */
26040  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk       (0x1UL)        /*!< RSPENDM (Bitfield-Mask: 0x01)                         */
26041 /* =====================================================  SD_INFO2_MASK  ===================================================== */
26042  #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos          (15UL)         /*!< ILAM (Bit 15)                                         */
26043  #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk          (0x8000UL)     /*!< ILAM (Bitfield-Mask: 0x01)                            */
26044  #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos          (9UL)          /*!< BWEM (Bit 9)                                          */
26045  #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk          (0x200UL)      /*!< BWEM (Bitfield-Mask: 0x01)                            */
26046  #define R_SDHI0_SD_INFO2_MASK_BREM_Pos          (8UL)          /*!< BREM (Bit 8)                                          */
26047  #define R_SDHI0_SD_INFO2_MASK_BREM_Msk          (0x100UL)      /*!< BREM (Bitfield-Mask: 0x01)                            */
26048  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos        (6UL)          /*!< RSPTOM (Bit 6)                                        */
26049  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk        (0x40UL)       /*!< RSPTOM (Bitfield-Mask: 0x01)                          */
26050  #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos          (5UL)          /*!< ILRM (Bit 5)                                          */
26051  #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk          (0x20UL)       /*!< ILRM (Bitfield-Mask: 0x01)                            */
26052  #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos          (4UL)          /*!< ILWM (Bit 4)                                          */
26053  #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk          (0x10UL)       /*!< ILWM (Bitfield-Mask: 0x01)                            */
26054  #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos          (3UL)          /*!< DTOM (Bit 3)                                          */
26055  #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk          (0x8UL)        /*!< DTOM (Bitfield-Mask: 0x01)                            */
26056  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos         (2UL)          /*!< ENDEM (Bit 2)                                         */
26057  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk         (0x4UL)        /*!< ENDEM (Bitfield-Mask: 0x01)                           */
26058  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos         (1UL)          /*!< CRCEM (Bit 1)                                         */
26059  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk         (0x2UL)        /*!< CRCEM (Bitfield-Mask: 0x01)                           */
26060  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos         (0UL)          /*!< CMDEM (Bit 0)                                         */
26061  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk         (0x1UL)        /*!< CMDEM (Bitfield-Mask: 0x01)                           */
26062 /* ======================================================  SD_CLK_CTRL  ====================================================== */
26063  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos       (9UL)          /*!< CLKCTRLEN (Bit 9)                                     */
26064  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk       (0x200UL)      /*!< CLKCTRLEN (Bitfield-Mask: 0x01)                       */
26065  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos           (8UL)          /*!< CLKEN (Bit 8)                                         */
26066  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk           (0x100UL)      /*!< CLKEN (Bitfield-Mask: 0x01)                           */
26067  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos          (0UL)          /*!< CLKSEL (Bit 0)                                        */
26068  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk          (0xffUL)       /*!< CLKSEL (Bitfield-Mask: 0xff)                          */
26069 /* ========================================================  SD_SIZE  ======================================================== */
26070  #define R_SDHI0_SD_SIZE_LEN_Pos                 (0UL)          /*!< LEN (Bit 0)                                           */
26071  #define R_SDHI0_SD_SIZE_LEN_Msk                 (0x3ffUL)      /*!< LEN (Bitfield-Mask: 0x3ff)                            */
26072 /* =======================================================  SD_OPTION  ======================================================= */
26073  #define R_SDHI0_SD_OPTION_WIDTH_Pos             (15UL)         /*!< WIDTH (Bit 15)                                        */
26074  #define R_SDHI0_SD_OPTION_WIDTH_Msk             (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
26075  #define R_SDHI0_SD_OPTION_WIDTH8_Pos            (13UL)         /*!< WIDTH8 (Bit 13)                                       */
26076  #define R_SDHI0_SD_OPTION_WIDTH8_Msk            (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
26077  #define R_SDHI0_SD_OPTION_TOUTMASK_Pos          (8UL)          /*!< TOUTMASK (Bit 8)                                      */
26078  #define R_SDHI0_SD_OPTION_TOUTMASK_Msk          (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
26079  #define R_SDHI0_SD_OPTION_TOP_Pos               (4UL)          /*!< TOP (Bit 4)                                           */
26080  #define R_SDHI0_SD_OPTION_TOP_Msk               (0xf0UL)       /*!< TOP (Bitfield-Mask: 0x0f)                             */
26081  #define R_SDHI0_SD_OPTION_CTOP_Pos              (0UL)          /*!< CTOP (Bit 0)                                          */
26082  #define R_SDHI0_SD_OPTION_CTOP_Msk              (0xfUL)        /*!< CTOP (Bitfield-Mask: 0x0f)                            */
26083 /* ======================================================  SD_ERR_STS1  ====================================================== */
26084  #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos           (12UL)         /*!< CRCTK (Bit 12)                                        */
26085  #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk           (0x7000UL)     /*!< CRCTK (Bitfield-Mask: 0x07)                           */
26086  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos          (11UL)         /*!< CRCTKE (Bit 11)                                       */
26087  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk          (0x800UL)      /*!< CRCTKE (Bitfield-Mask: 0x01)                          */
26088  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos          (10UL)         /*!< RDCRCE (Bit 10)                                       */
26089  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk          (0x400UL)      /*!< RDCRCE (Bitfield-Mask: 0x01)                          */
26090  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos        (9UL)          /*!< RSPCRCE1 (Bit 9)                                      */
26091  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk        (0x200UL)      /*!< RSPCRCE1 (Bitfield-Mask: 0x01)                        */
26092  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos        (8UL)          /*!< RSPCRCE0 (Bit 8)                                      */
26093  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk        (0x100UL)      /*!< RSPCRCE0 (Bitfield-Mask: 0x01)                        */
26094  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos         (5UL)          /*!< CRCLENE (Bit 5)                                       */
26095  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk         (0x20UL)       /*!< CRCLENE (Bitfield-Mask: 0x01)                         */
26096  #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos          (4UL)          /*!< RDLENE (Bit 4)                                        */
26097  #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk          (0x10UL)       /*!< RDLENE (Bitfield-Mask: 0x01)                          */
26098  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos        (3UL)          /*!< RSPLENE1 (Bit 3)                                      */
26099  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk        (0x8UL)        /*!< RSPLENE1 (Bitfield-Mask: 0x01)                        */
26100  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos        (2UL)          /*!< RSPLENE0 (Bit 2)                                      */
26101  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk        (0x4UL)        /*!< RSPLENE0 (Bitfield-Mask: 0x01)                        */
26102  #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos           (1UL)          /*!< CMDE1 (Bit 1)                                         */
26103  #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk           (0x2UL)        /*!< CMDE1 (Bitfield-Mask: 0x01)                           */
26104  #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos           (0UL)          /*!< CMDE0 (Bit 0)                                         */
26105  #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk           (0x1UL)        /*!< CMDE0 (Bitfield-Mask: 0x01)                           */
26106 /* ======================================================  SD_ERR_STS2  ====================================================== */
26107  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos        (6UL)          /*!< CRCBSYTO (Bit 6)                                      */
26108  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk        (0x40UL)       /*!< CRCBSYTO (Bitfield-Mask: 0x01)                        */
26109  #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos           (5UL)          /*!< CRCTO (Bit 5)                                         */
26110  #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk           (0x20UL)       /*!< CRCTO (Bitfield-Mask: 0x01)                           */
26111  #define R_SDHI0_SD_ERR_STS2_RDTO_Pos            (4UL)          /*!< RDTO (Bit 4)                                          */
26112  #define R_SDHI0_SD_ERR_STS2_RDTO_Msk            (0x10UL)       /*!< RDTO (Bitfield-Mask: 0x01)                            */
26113  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos          (3UL)          /*!< BSYTO1 (Bit 3)                                        */
26114  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk          (0x8UL)        /*!< BSYTO1 (Bitfield-Mask: 0x01)                          */
26115  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos          (2UL)          /*!< BSYTO0 (Bit 2)                                        */
26116  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk          (0x4UL)        /*!< BSYTO0 (Bitfield-Mask: 0x01)                          */
26117  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos          (1UL)          /*!< RSPTO1 (Bit 1)                                        */
26118  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk          (0x2UL)        /*!< RSPTO1 (Bitfield-Mask: 0x01)                          */
26119  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos          (0UL)          /*!< RSPTO0 (Bit 0)                                        */
26120  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk          (0x1UL)        /*!< RSPTO0 (Bitfield-Mask: 0x01)                          */
26121 /* ========================================================  SD_BUF0  ======================================================== */
26122  #define R_SDHI0_SD_BUF0_SD_BUF_Pos              (0UL)          /*!< SD_BUF (Bit 0)                                        */
26123  #define R_SDHI0_SD_BUF0_SD_BUF_Msk              (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff)                    */
26124 /* =======================================================  SDIO_MODE  ======================================================= */
26125  #define R_SDHI0_SDIO_MODE_C52PUB_Pos            (9UL)          /*!< C52PUB (Bit 9)                                        */
26126  #define R_SDHI0_SDIO_MODE_C52PUB_Msk            (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
26127  #define R_SDHI0_SDIO_MODE_IOABT_Pos             (8UL)          /*!< IOABT (Bit 8)                                         */
26128  #define R_SDHI0_SDIO_MODE_IOABT_Msk             (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
26129  #define R_SDHI0_SDIO_MODE_RWREQ_Pos             (2UL)          /*!< RWREQ (Bit 2)                                         */
26130  #define R_SDHI0_SDIO_MODE_RWREQ_Msk             (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
26131  #define R_SDHI0_SDIO_MODE_INTEN_Pos             (0UL)          /*!< INTEN (Bit 0)                                         */
26132  #define R_SDHI0_SDIO_MODE_INTEN_Msk             (0x1UL)        /*!< INTEN (Bitfield-Mask: 0x01)                           */
26133 /* ======================================================  SDIO_INFO1  ======================================================= */
26134  #define R_SDHI0_SDIO_INFO1_EXWT_Pos             (15UL)         /*!< EXWT (Bit 15)                                         */
26135  #define R_SDHI0_SDIO_INFO1_EXWT_Msk             (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
26136  #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos          (14UL)         /*!< EXPUB52 (Bit 14)                                      */
26137  #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk          (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
26138  #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos            (0UL)          /*!< IOIRQ (Bit 0)                                         */
26139  #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk            (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
26140 /* ====================================================  SDIO_INFO1_MASK  ==================================================== */
26141  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos       (15UL)         /*!< EXWTM (Bit 15)                                        */
26142  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk       (0x8000UL)     /*!< EXWTM (Bitfield-Mask: 0x01)                           */
26143  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos    (14UL)         /*!< EXPUB52M (Bit 14)                                     */
26144  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk    (0x4000UL)     /*!< EXPUB52M (Bitfield-Mask: 0x01)                        */
26145  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos      (0UL)          /*!< IOIRQM (Bit 0)                                        */
26146  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk      (0x1UL)        /*!< IOIRQM (Bitfield-Mask: 0x01)                          */
26147 /* =======================================================  SD_DMAEN  ======================================================== */
26148  #define R_SDHI0_SD_DMAEN_DMAEN_Pos              (1UL)          /*!< DMAEN (Bit 1)                                         */
26149  #define R_SDHI0_SD_DMAEN_DMAEN_Msk              (0x2UL)        /*!< DMAEN (Bitfield-Mask: 0x01)                           */
26150 /* =======================================================  SOFT_RST  ======================================================== */
26151  #define R_SDHI0_SOFT_RST_SDRST_Pos              (0UL)          /*!< SDRST (Bit 0)                                         */
26152  #define R_SDHI0_SOFT_RST_SDRST_Msk              (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
26153 /* =======================================================  SDIF_MODE  ======================================================= */
26154  #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos           (8UL)          /*!< NOCHKCR (Bit 8)                                       */
26155  #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk           (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
26156 /* =======================================================  EXT_SWAP  ======================================================== */
26157  #define R_SDHI0_EXT_SWAP_BRSWP_Pos              (7UL)          /*!< BRSWP (Bit 7)                                         */
26158  #define R_SDHI0_EXT_SWAP_BRSWP_Msk              (0x80UL)       /*!< BRSWP (Bitfield-Mask: 0x01)                           */
26159  #define R_SDHI0_EXT_SWAP_BWSWP_Pos              (6UL)          /*!< BWSWP (Bit 6)                                         */
26160  #define R_SDHI0_EXT_SWAP_BWSWP_Msk              (0x40UL)       /*!< BWSWP (Bitfield-Mask: 0x01)                           */
26161 
26162 /* =========================================================================================================================== */
26163 /* ================                                          R_SPI0                                           ================ */
26164 /* =========================================================================================================================== */
26165 
26166 /* =========================================================  SPCR  ========================================================== */
26167  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
26168  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
26169  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
26170  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
26171  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
26172  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
26173  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
26174  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
26175  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
26176  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
26177  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
26178  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
26179  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
26180  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
26181  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
26182  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
26183 /* =========================================================  SSLP  ========================================================== */
26184  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
26185  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
26186  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
26187  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
26188  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
26189  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
26190  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
26191  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
26192  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
26193  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
26194  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
26195  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
26196  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
26197  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
26198  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
26199  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
26200 /* =========================================================  SPPCR  ========================================================= */
26201  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
26202  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
26203  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
26204  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
26205  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
26206  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
26207  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
26208  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
26209 /* =========================================================  SPSR  ========================================================== */
26210  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
26211  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
26212  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
26213  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
26214  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
26215  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
26216  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
26217  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
26218  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
26219  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
26220  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
26221  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
26222  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
26223  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
26224  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
26225  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
26226 /* =========================================================  SPDR  ========================================================== */
26227 /* ========================================================  SPDR_HA  ======================================================== */
26228 /* ========================================================  SPDR_BY  ======================================================== */
26229 /* =========================================================  SPSCR  ========================================================= */
26230  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
26231  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
26232 /* =========================================================  SPBR  ========================================================== */
26233  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
26234  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
26235 /* =========================================================  SPDCR  ========================================================= */
26236  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
26237  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
26238  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
26239  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
26240  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
26241  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
26242  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
26243  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
26244  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
26245  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
26246 /* =========================================================  SPCKD  ========================================================= */
26247  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
26248  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
26249 /* =========================================================  SSLND  ========================================================= */
26250  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
26251  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
26252 /* =========================================================  SPND  ========================================================== */
26253  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
26254  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
26255 /* =========================================================  SPCR2  ========================================================= */
26256  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
26257  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
26258  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
26259  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
26260  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
26261  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
26262  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
26263  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
26264  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
26265  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
26266  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
26267  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
26268 /* =========================================================  SPCMD  ========================================================= */
26269  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
26270  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
26271  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
26272  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
26273  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
26274  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
26275  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
26276  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
26277  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
26278  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
26279  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
26280  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
26281  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
26282  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
26283  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
26284  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
26285  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
26286  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
26287  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
26288  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
26289 /* ========================================================  SPDCR2  ========================================================= */
26290  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
26291  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
26292  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
26293  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
26294 /* =========================================================  SPSSR  ========================================================= */
26295  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
26296  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
26297  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
26298  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
26299 /* =========================================================  SPCR3  ========================================================= */
26300  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
26301  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
26302  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
26303  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
26304  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
26305  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
26306 /* =========================================================  SPPR  ========================================================== */
26307  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
26308  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
26309  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
26310  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
26311  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
26312  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
26313 
26314 /* =========================================================================================================================== */
26315 /* ================                                          R_SRAM                                           ================ */
26316 /* =========================================================================================================================== */
26317 
26318 /* =======================================================  SRAMPRCR  ======================================================== */
26319  #define R_SRAM_SRAMPRCR_PR_Pos           (0UL)       /*!< PR (Bit 0)                                            */
26320  #define R_SRAM_SRAMPRCR_PR_Msk           (0x1UL)     /*!< PR (Bitfield-Mask: 0x01)                              */
26321  #define R_SRAM_SRAMPRCR_KW_Pos           (8UL)       /*!< KW (Bit 8)                                            */
26322  #define R_SRAM_SRAMPRCR_KW_Msk           (0xff00UL)  /*!< KW (Bitfield-Mask: 0xff)                              */
26323 /* ======================================================  SRAMPRCR_NS  ====================================================== */
26324  #define R_SRAM_SRAMPRCR_NS_PR_Pos        (0UL)       /*!< PR (Bit 0)                                            */
26325  #define R_SRAM_SRAMPRCR_NS_PR_Msk        (0x1UL)     /*!< PR (Bitfield-Mask: 0x01)                              */
26326  #define R_SRAM_SRAMPRCR_NS_KW_Pos        (8UL)       /*!< KW (Bit 8)                                            */
26327  #define R_SRAM_SRAMPRCR_NS_KW_Msk        (0xff00UL)  /*!< KW (Bitfield-Mask: 0xff)                              */
26328 /* =======================================================  SRAMWTSC  ======================================================== */
26329  #define R_SRAM_SRAMWTSC_WTEN_Pos         (0UL)       /*!< WTEN (Bit 0)                                          */
26330  #define R_SRAM_SRAMWTSC_WTEN_Msk         (0x1UL)     /*!< WTEN (Bitfield-Mask: 0x01)                            */
26331 /* ========================================================  SRAMCR0  ======================================================== */
26332  #define R_SRAM_SRAMCR0_OAD_Pos           (0UL)       /*!< OAD (Bit 0)                                           */
26333  #define R_SRAM_SRAMCR0_OAD_Msk           (0x1UL)     /*!< OAD (Bitfield-Mask: 0x01)                             */
26334  #define R_SRAM_SRAMCR0_ECCMOD_Pos        (2UL)       /*!< ECCMOD (Bit 2)                                        */
26335  #define R_SRAM_SRAMCR0_ECCMOD_Msk        (0xcUL)     /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
26336  #define R_SRAM_SRAMCR0_E1STSEN_Pos       (4UL)       /*!< E1STSEN (Bit 4)                                       */
26337  #define R_SRAM_SRAMCR0_E1STSEN_Msk       (0x10UL)    /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
26338  #define R_SRAM_SRAMCR0_TSTBYP_Pos        (7UL)       /*!< TSTBYP (Bit 7)                                        */
26339  #define R_SRAM_SRAMCR0_TSTBYP_Msk        (0x80UL)    /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
26340 /* ========================================================  SRAMCR1  ======================================================== */
26341  #define R_SRAM_SRAMCR1_OAD_Pos           (0UL)       /*!< OAD (Bit 0)                                           */
26342  #define R_SRAM_SRAMCR1_OAD_Msk           (0x1UL)     /*!< OAD (Bitfield-Mask: 0x01)                             */
26343 /* ======================================================  SRAMECCRGN0  ====================================================== */
26344  #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos    (0UL)       /*!< ECCRGN (Bit 0)                                        */
26345  #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk    (0x3UL)     /*!< ECCRGN (Bitfield-Mask: 0x03)                          */
26346 /* ========================================================  SRAMESR  ======================================================== */
26347  #define R_SRAM_SRAMESR_ERR00_Pos         (0UL)       /*!< ERR00 (Bit 0)                                         */
26348  #define R_SRAM_SRAMESR_ERR00_Msk         (0x1UL)     /*!< ERR00 (Bitfield-Mask: 0x01)                           */
26349  #define R_SRAM_SRAMESR_ERR01_Pos         (1UL)       /*!< ERR01 (Bit 1)                                         */
26350  #define R_SRAM_SRAMESR_ERR01_Msk         (0x2UL)     /*!< ERR01 (Bitfield-Mask: 0x01)                           */
26351  #define R_SRAM_SRAMESR_ERR1_Pos          (2UL)       /*!< ERR1 (Bit 2)                                          */
26352  #define R_SRAM_SRAMESR_ERR1_Msk          (0x4UL)     /*!< ERR1 (Bitfield-Mask: 0x01)                            */
26353  #define R_SRAM_SRAMESR_ERRS_Pos          (14UL)      /*!< ERRS (Bit 14)                                         */
26354  #define R_SRAM_SRAMESR_ERRS_Msk          (0x4000UL)  /*!< ERRS (Bitfield-Mask: 0x01)                            */
26355 /* =======================================================  SRAMESCLR  ======================================================= */
26356  #define R_SRAM_SRAMESCLR_CLR00_Pos       (0UL)       /*!< CLR00 (Bit 0)                                         */
26357  #define R_SRAM_SRAMESCLR_CLR00_Msk       (0x1UL)     /*!< CLR00 (Bitfield-Mask: 0x01)                           */
26358  #define R_SRAM_SRAMESCLR_CLR01_Pos       (1UL)       /*!< CLR01 (Bit 1)                                         */
26359  #define R_SRAM_SRAMESCLR_CLR01_Msk       (0x2UL)     /*!< CLR01 (Bitfield-Mask: 0x01)                           */
26360  #define R_SRAM_SRAMESCLR_CLR1_Pos        (2UL)       /*!< CLR1 (Bit 2)                                          */
26361  #define R_SRAM_SRAMESCLR_CLR1_Msk        (0x4UL)     /*!< CLR1 (Bitfield-Mask: 0x01)                            */
26362  #define R_SRAM_SRAMESCLR_CLRS_Pos        (14UL)      /*!< CLRS (Bit 14)                                         */
26363  #define R_SRAM_SRAMESCLR_CLRS_Msk        (0x4000UL)  /*!< CLRS (Bitfield-Mask: 0x01)                            */
26364 /* =======================================================  SRAMEAR0  ======================================================== */
26365  #define R_SRAM_SRAMEAR0_EA_Pos           (3UL)       /*!< EA (Bit 3)                                            */
26366  #define R_SRAM_SRAMEAR0_EA_Msk           (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff)                           */
26367 /* =======================================================  SRAMEAR1  ======================================================== */
26368  #define R_SRAM_SRAMEAR1_EA_Pos           (3UL)       /*!< EA (Bit 3)                                            */
26369  #define R_SRAM_SRAMEAR1_EA_Msk           (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff)                           */
26370 /* =======================================================  SRAMEAR2  ======================================================== */
26371  #define R_SRAM_SRAMEAR2_EA_Pos           (3UL)       /*!< EA (Bit 3)                                            */
26372  #define R_SRAM_SRAMEAR2_EA_Msk           (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff)                           */
26373 /* =======================================================  STBRAMCR  ======================================================== */
26374  #define R_SRAM_STBRAMCR_OAD_Pos          (0UL)       /*!< OAD (Bit 0)                                           */
26375  #define R_SRAM_STBRAMCR_OAD_Msk          (0x1UL)     /*!< OAD (Bitfield-Mask: 0x01)                             */
26376 /* =======================================================  STBRAMEAR  ======================================================= */
26377  #define R_SRAM_STBRAMEAR_EA_Pos          (2UL)       /*!< EA (Bit 2)                                            */
26378  #define R_SRAM_STBRAMEAR_EA_Msk          (0x3fcUL)   /*!< EA (Bitfield-Mask: 0xff)                              */
26379 
26380 /* =========================================================================================================================== */
26381 /* ================                                          R_SSI0                                           ================ */
26382 /* =========================================================================================================================== */
26383 
26384 /* =========================================================  SSICR  ========================================================= */
26385  #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
26386  #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
26387  #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
26388  #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
26389  #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
26390  #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
26391  #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
26392  #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
26393  #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
26394  #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
26395  #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
26396  #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
26397  #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
26398  #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
26399  #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
26400  #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
26401  #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
26402  #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
26403  #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
26404  #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
26405  #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
26406  #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
26407  #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
26408  #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
26409  #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
26410  #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
26411  #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
26412  #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
26413  #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
26414  #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
26415  #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
26416  #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
26417  #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
26418  #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
26419  #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
26420  #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
26421  #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
26422  #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
26423  #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
26424  #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
26425 /* =========================================================  SSISR  ========================================================= */
26426  #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
26427  #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
26428  #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
26429  #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
26430  #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
26431  #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
26432  #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
26433  #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
26434  #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
26435  #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
26436  #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
26437  #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
26438  #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
26439  #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
26440  #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
26441  #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
26442  #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
26443  #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
26444  #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
26445  #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
26446 /* ========================================================  SSIFCR  ========================================================= */
26447  #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
26448  #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
26449  #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
26450  #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
26451  #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
26452  #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
26453  #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
26454  #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
26455  #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
26456  #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
26457  #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
26458  #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
26459  #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
26460  #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
26461  #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
26462  #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
26463  #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
26464  #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
26465 /* ========================================================  SSIFSR  ========================================================= */
26466  #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
26467  #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
26468  #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
26469  #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
26470  #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
26471  #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
26472  #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
26473  #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
26474 /* ========================================================  SSIFTDR  ======================================================== */
26475  #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
26476  #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
26477 /* =======================================================  SSIFTDR16  ======================================================= */
26478 /* =======================================================  SSIFTDR8  ======================================================== */
26479 /* ========================================================  SSIFRDR  ======================================================== */
26480  #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
26481  #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
26482 /* =======================================================  SSIFRDR16  ======================================================= */
26483 /* =======================================================  SSIFRDR8  ======================================================== */
26484 /* ========================================================  SSIOFR  ========================================================= */
26485  #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
26486  #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
26487  #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
26488  #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
26489  #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
26490  #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
26491 /* ========================================================  SSISCR  ========================================================= */
26492  #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
26493  #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
26494  #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
26495  #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
26496 
26497 /* =========================================================================================================================== */
26498 /* ================                                         R_SYSTEM                                          ================ */
26499 /* =========================================================================================================================== */
26500 
26501 /* =========================================================  SBYCR  ========================================================= */
26502  #define R_SYSTEM_SBYCR_OPE_Pos                  (6UL)          /*!< OPE (Bit 6)                                           */
26503  #define R_SYSTEM_SBYCR_OPE_Msk                  (0x40UL)       /*!< OPE (Bitfield-Mask: 0x01)                             */
26504 /* =========================================================  SSCR2  ========================================================= */
26505  #define R_SYSTEM_SSCR2_SS1RSF_Pos               (0UL)          /*!< SS1RSF (Bit 0)                                        */
26506  #define R_SYSTEM_SSCR2_SS1RSF_Msk               (0x1UL)        /*!< SS1RSF (Bitfield-Mask: 0x01)                          */
26507 /* =========================================================  FLSCR  ========================================================= */
26508  #define R_SYSTEM_FLSCR_FLSWCF_Pos               (0UL)          /*!< FLSWCF (Bit 0)                                        */
26509  #define R_SYSTEM_FLSCR_FLSWCF_Msk               (0x1UL)        /*!< FLSWCF (Bitfield-Mask: 0x01)                          */
26510 /* ========================================================  MSTPCRA  ======================================================== */
26511  #define R_SYSTEM_MSTPCRA_MSTPA_Pos              (0UL)          /*!< MSTPA (Bit 0)                                         */
26512  #define R_SYSTEM_MSTPCRA_MSTPA_Msk              (0x1UL)        /*!< MSTPA (Bitfield-Mask: 0x01)                           */
26513 /* =======================================================  SCKDIVCR  ======================================================== */
26514  #define R_SYSTEM_SCKDIVCR_FCK_Pos               (28UL)         /*!< FCK (Bit 28)                                          */
26515  #define R_SYSTEM_SCKDIVCR_FCK_Msk               (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f)                             */
26516  #define R_SYSTEM_SCKDIVCR_ICK_Pos               (24UL)         /*!< ICK (Bit 24)                                          */
26517  #define R_SYSTEM_SCKDIVCR_ICK_Msk               (0xf000000UL)  /*!< ICK (Bitfield-Mask: 0x0f)                             */
26518  #define R_SYSTEM_SCKDIVCR_PCKE_Pos              (20UL)         /*!< PCKE (Bit 20)                                         */
26519  #define R_SYSTEM_SCKDIVCR_PCKE_Msk              (0xf00000UL)   /*!< PCKE (Bitfield-Mask: 0x0f)                            */
26520  #define R_SYSTEM_SCKDIVCR_BCK_Pos               (16UL)         /*!< BCK (Bit 16)                                          */
26521  #define R_SYSTEM_SCKDIVCR_BCK_Msk               (0xf0000UL)    /*!< BCK (Bitfield-Mask: 0x0f)                             */
26522  #define R_SYSTEM_SCKDIVCR_PCKA_Pos              (12UL)         /*!< PCKA (Bit 12)                                         */
26523  #define R_SYSTEM_SCKDIVCR_PCKA_Msk              (0xf000UL)     /*!< PCKA (Bitfield-Mask: 0x0f)                            */
26524  #define R_SYSTEM_SCKDIVCR_PCKB_Pos              (8UL)          /*!< PCKB (Bit 8)                                          */
26525  #define R_SYSTEM_SCKDIVCR_PCKB_Msk              (0xf00UL)      /*!< PCKB (Bitfield-Mask: 0x0f)                            */
26526  #define R_SYSTEM_SCKDIVCR_PCKC_Pos              (4UL)          /*!< PCKC (Bit 4)                                          */
26527  #define R_SYSTEM_SCKDIVCR_PCKC_Msk              (0xf0UL)       /*!< PCKC (Bitfield-Mask: 0x0f)                            */
26528  #define R_SYSTEM_SCKDIVCR_PCKD_Pos              (0UL)          /*!< PCKD (Bit 0)                                          */
26529  #define R_SYSTEM_SCKDIVCR_PCKD_Msk              (0xfUL)        /*!< PCKD (Bitfield-Mask: 0x0f)                            */
26530 /* =======================================================  SCKDIVCR2  ======================================================= */
26531  #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos            (0UL)          /*!< CPUCK (Bit 0)                                         */
26532  #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk            (0xfUL)        /*!< CPUCK (Bitfield-Mask: 0x0f)                           */
26533  #define R_SYSTEM_SCKDIVCR2_CPUCK1_Pos           (4UL)          /*!< CPUCK1 (Bit 4)                                        */
26534  #define R_SYSTEM_SCKDIVCR2_CPUCK1_Msk           (0xf0UL)       /*!< CPUCK1 (Bitfield-Mask: 0x0f)                          */
26535 /* ========================================================  SCKSCR  ========================================================= */
26536  #define R_SYSTEM_SCKSCR_CKSEL_Pos               (0UL)          /*!< CKSEL (Bit 0)                                         */
26537  #define R_SYSTEM_SCKSCR_CKSEL_Msk               (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
26538 /* ========================================================  PLLCCR  ========================================================= */
26539  #define R_SYSTEM_PLLCCR_PLIDIV_Pos              (0UL)          /*!< PLIDIV (Bit 0)                                        */
26540  #define R_SYSTEM_PLLCCR_PLIDIV_Msk              (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
26541  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos            (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
26542  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk            (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
26543  #define R_SYSTEM_PLLCCR_PLLMULNF_Pos            (6UL)          /*!< PLLMULNF (Bit 6)                                      */
26544  #define R_SYSTEM_PLLCCR_PLLMULNF_Msk            (0xc0UL)       /*!< PLLMULNF (Bitfield-Mask: 0x03)                        */
26545  #define R_SYSTEM_PLLCCR_PLLMUL_Pos              (8UL)          /*!< PLLMUL (Bit 8)                                        */
26546  #define R_SYSTEM_PLLCCR_PLLMUL_Msk              (0xff00UL)     /*!< PLLMUL (Bitfield-Mask: 0xff)                          */
26547 /* =========================================================  PLLCR  ========================================================= */
26548  #define R_SYSTEM_PLLCR_PLLSTP_Pos               (0UL)          /*!< PLLSTP (Bit 0)                                        */
26549  #define R_SYSTEM_PLLCR_PLLSTP_Msk               (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
26550 /* =========================================================  BCKCR  ========================================================= */
26551  #define R_SYSTEM_BCKCR_BCLKDIV_Pos              (0UL)          /*!< BCLKDIV (Bit 0)                                       */
26552  #define R_SYSTEM_BCKCR_BCLKDIV_Msk              (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
26553 /* ========================================================  MOSCCR  ========================================================= */
26554  #define R_SYSTEM_MOSCCR_MOSTP_Pos               (0UL)          /*!< MOSTP (Bit 0)                                         */
26555  #define R_SYSTEM_MOSCCR_MOSTP_Msk               (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
26556 /* ========================================================  HOCOCR  ========================================================= */
26557  #define R_SYSTEM_HOCOCR_HCSTP_Pos               (0UL)          /*!< HCSTP (Bit 0)                                         */
26558  #define R_SYSTEM_HOCOCR_HCSTP_Msk               (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
26559 /* ========================================================  MOCOCR  ========================================================= */
26560  #define R_SYSTEM_MOCOCR_MCSTP_Pos               (0UL)          /*!< MCSTP (Bit 0)                                         */
26561  #define R_SYSTEM_MOCOCR_MCSTP_Msk               (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
26562 /* ========================================================  FLLCR1  ========================================================= */
26563  #define R_SYSTEM_FLLCR1_FLLEN_Pos               (0UL)          /*!< FLLEN (Bit 0)                                         */
26564  #define R_SYSTEM_FLLCR1_FLLEN_Msk               (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
26565 /* ========================================================  FLLCR2  ========================================================= */
26566  #define R_SYSTEM_FLLCR2_FLLCNTL_Pos             (0UL)          /*!< FLLCNTL (Bit 0)                                       */
26567  #define R_SYSTEM_FLLCR2_FLLCNTL_Msk             (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
26568 /* =========================================================  OSCSF  ========================================================= */
26569  #define R_SYSTEM_OSCSF_HOCOSF_Pos               (0UL)          /*!< HOCOSF (Bit 0)                                        */
26570  #define R_SYSTEM_OSCSF_HOCOSF_Msk               (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
26571  #define R_SYSTEM_OSCSF_MOSCSF_Pos               (3UL)          /*!< MOSCSF (Bit 3)                                        */
26572  #define R_SYSTEM_OSCSF_MOSCSF_Msk               (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
26573  #define R_SYSTEM_OSCSF_PLLSF_Pos                (5UL)          /*!< PLLSF (Bit 5)                                         */
26574  #define R_SYSTEM_OSCSF_PLLSF_Msk                (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
26575  #define R_SYSTEM_OSCSF_PLL2SF_Pos               (6UL)          /*!< PLL2SF (Bit 6)                                        */
26576  #define R_SYSTEM_OSCSF_PLL2SF_Msk               (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
26577 /* =========================================================  CKOCR  ========================================================= */
26578  #define R_SYSTEM_CKOCR_CKODIV_Pos               (4UL)          /*!< CKODIV (Bit 4)                                        */
26579  #define R_SYSTEM_CKOCR_CKODIV_Msk               (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
26580  #define R_SYSTEM_CKOCR_CKOEN_Pos                (7UL)          /*!< CKOEN (Bit 7)                                         */
26581  #define R_SYSTEM_CKOCR_CKOEN_Msk                (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
26582 /* ========================================================  TRCKCR  ========================================================= */
26583  #define R_SYSTEM_TRCKCR_TRCK_Pos                (0UL)          /*!< TRCK (Bit 0)                                          */
26584  #define R_SYSTEM_TRCKCR_TRCK_Msk                (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
26585  #define R_SYSTEM_TRCKCR_TRCKSEL_Pos             (4UL)          /*!< TRCKSEL (Bit 4)                                       */
26586  #define R_SYSTEM_TRCKCR_TRCKSEL_Msk             (0x10UL)       /*!< TRCKSEL (Bitfield-Mask: 0x01)                         */
26587  #define R_SYSTEM_TRCKCR_TRCKEN_Pos              (7UL)          /*!< TRCKEN (Bit 7)                                        */
26588  #define R_SYSTEM_TRCKCR_TRCKEN_Msk              (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
26589 /* ========================================================  OSTDCR  ========================================================= */
26590  #define R_SYSTEM_OSTDCR_OSTDIE_Pos              (0UL)          /*!< OSTDIE (Bit 0)                                        */
26591  #define R_SYSTEM_OSTDCR_OSTDIE_Msk              (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
26592  #define R_SYSTEM_OSTDCR_OSTDE_Pos               (7UL)          /*!< OSTDE (Bit 7)                                         */
26593  #define R_SYSTEM_OSTDCR_OSTDE_Msk               (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
26594 /* ========================================================  OSTDSR  ========================================================= */
26595  #define R_SYSTEM_OSTDSR_OSTDF_Pos               (0UL)          /*!< OSTDF (Bit 0)                                         */
26596  #define R_SYSTEM_OSTDSR_OSTDF_Msk               (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
26597 /* ========================================================  OSCMONR  ======================================================== */
26598  #define R_SYSTEM_OSCMONR_MOCOMON_Pos            (1UL)          /*!< MOCOMON (Bit 1)                                       */
26599  #define R_SYSTEM_OSCMONR_MOCOMON_Msk            (0x2UL)        /*!< MOCOMON (Bitfield-Mask: 0x01)                         */
26600  #define R_SYSTEM_OSCMONR_LOCOMON_Pos            (2UL)          /*!< LOCOMON (Bit 2)                                       */
26601  #define R_SYSTEM_OSCMONR_LOCOMON_Msk            (0x4UL)        /*!< LOCOMON (Bitfield-Mask: 0x01)                         */
26602 /* ========================================================  PLL2CCR  ======================================================== */
26603  #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos            (0UL)          /*!< PL2IDIV (Bit 0)                                       */
26604  #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk            (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
26605  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos          (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
26606  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk          (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
26607  #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos          (6UL)          /*!< PLL2MULNF (Bit 6)                                     */
26608  #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk          (0xc0UL)       /*!< PLL2MULNF (Bitfield-Mask: 0x03)                       */
26609  #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos            (8UL)          /*!< PLL2MUL (Bit 8)                                       */
26610  #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk            (0xff00UL)     /*!< PLL2MUL (Bitfield-Mask: 0xff)                         */
26611 /* ========================================================  PLL2CR  ========================================================= */
26612  #define R_SYSTEM_PLL2CR_PLL2STP_Pos             (0UL)          /*!< PLL2STP (Bit 0)                                       */
26613  #define R_SYSTEM_PLL2CR_PLL2STP_Msk             (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
26614 /* ========================================================  PLLCCR2  ======================================================== */
26615  #define R_SYSTEM_PLLCCR2_PLODIVP_Pos            (0UL)          /*!< PLODIVP (Bit 0)                                       */
26616  #define R_SYSTEM_PLLCCR2_PLODIVP_Msk            (0xfUL)        /*!< PLODIVP (Bitfield-Mask: 0x0f)                         */
26617  #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos            (4UL)          /*!< PLODIVQ (Bit 4)                                       */
26618  #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk            (0xf0UL)       /*!< PLODIVQ (Bitfield-Mask: 0x0f)                         */
26619  #define R_SYSTEM_PLLCCR2_PLODIVR_Pos            (8UL)          /*!< PLODIVR (Bit 8)                                       */
26620  #define R_SYSTEM_PLLCCR2_PLODIVR_Msk            (0xf00UL)      /*!< PLODIVR (Bitfield-Mask: 0x0f)                         */
26621 /* =======================================================  PLL2CCR2  ======================================================== */
26622  #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos          (0UL)          /*!< PL2ODIVP (Bit 0)                                      */
26623  #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk          (0xfUL)        /*!< PL2ODIVP (Bitfield-Mask: 0x0f)                        */
26624  #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos          (4UL)          /*!< PL2ODIVQ (Bit 4)                                      */
26625  #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk          (0xf0UL)       /*!< PL2ODIVQ (Bitfield-Mask: 0x0f)                        */
26626  #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos          (8UL)          /*!< PL2ODIVR (Bit 8)                                      */
26627  #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk          (0xf00UL)      /*!< PL2ODIVR (Bitfield-Mask: 0x0f)                        */
26628 /* ========================================================  EBCKOCR  ======================================================== */
26629  #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos            (0UL)          /*!< EBCKOEN (Bit 0)                                       */
26630  #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk            (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
26631 /* ========================================================  SDCKOCR  ======================================================== */
26632  #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos            (0UL)          /*!< SDCKOEN (Bit 0)                                       */
26633  #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk            (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
26634 /* ======================================================  SCICKDIVCR  ======================================================= */
26635  #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
26636  #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
26637 /* ========================================================  SCICKCR  ======================================================== */
26638  #define R_SYSTEM_SCICKCR_SCICKSEL_Pos           (0UL)          /*!< SCICKSEL (Bit 0)                                      */
26639  #define R_SYSTEM_SCICKCR_SCICKSEL_Msk           (0xfUL)        /*!< SCICKSEL (Bitfield-Mask: 0x0f)                        */
26640  #define R_SYSTEM_SCICKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
26641  #define R_SYSTEM_SCICKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
26642  #define R_SYSTEM_SCICKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
26643  #define R_SYSTEM_SCICKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
26644 /* ======================================================  SPICKDIVCR  ======================================================= */
26645  #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
26646  #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
26647 /* ========================================================  SPICKCR  ======================================================== */
26648  #define R_SYSTEM_SPICKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
26649  #define R_SYSTEM_SPICKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
26650  #define R_SYSTEM_SPICKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
26651  #define R_SYSTEM_SPICKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
26652  #define R_SYSTEM_SPICKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
26653  #define R_SYSTEM_SPICKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
26654 /* ======================================================  ADCCKDIVCR  ======================================================= */
26655  #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
26656  #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
26657 /* ========================================================  ADCCKCR  ======================================================== */
26658  #define R_SYSTEM_ADCCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
26659  #define R_SYSTEM_ADCCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
26660  #define R_SYSTEM_ADCCKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
26661  #define R_SYSTEM_ADCCKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
26662  #define R_SYSTEM_ADCCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
26663  #define R_SYSTEM_ADCCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
26664 /* ======================================================  GPTCKDIVCR  ======================================================= */
26665  #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
26666  #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
26667 /* ========================================================  GPTCKCR  ======================================================== */
26668  #define R_SYSTEM_GPTCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
26669  #define R_SYSTEM_GPTCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
26670  #define R_SYSTEM_GPTCKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
26671  #define R_SYSTEM_GPTCKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
26672  #define R_SYSTEM_GPTCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
26673  #define R_SYSTEM_GPTCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
26674 /* ======================================================  LCDCKDIVCR  ======================================================= */
26675  #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
26676  #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
26677 /* ========================================================  LCDCKCR  ======================================================== */
26678  #define R_SYSTEM_LCDCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
26679  #define R_SYSTEM_LCDCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
26680  #define R_SYSTEM_LCDCKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
26681  #define R_SYSTEM_LCDCKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
26682  #define R_SYSTEM_LCDCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
26683  #define R_SYSTEM_LCDCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
26684 /* =======================================================  MOCOUTCR  ======================================================== */
26685  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos          (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
26686  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk          (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
26687 /* =======================================================  HOCOUTCR  ======================================================== */
26688  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos          (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
26689  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk          (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
26690 /* ======================================================  USBCKDIVCR  ======================================================= */
26691  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos        (0UL)          /*!< USBCKDIV (Bit 0)                                      */
26692  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk        (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
26693 /* ======================================================  OCTACKDIVCR  ====================================================== */
26694  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos      (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
26695  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk      (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
26696 /* =====================================================  CANFDCKDIVCR  ====================================================== */
26697  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos    (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
26698  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk    (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
26699 /* =====================================================  USB60CKDIVCR  ====================================================== */
26700  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos    (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
26701  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk    (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
26702 /* ======================================================  I3CCKDIVCR  ======================================================= */
26703  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos        (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
26704  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk        (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
26705 /* ========================================================  USBCKCR  ======================================================== */
26706  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos           (0UL)          /*!< USBCKSEL (Bit 0)                                      */
26707  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk           (0xfUL)        /*!< USBCKSEL (Bitfield-Mask: 0x0f)                        */
26708  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos          (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
26709  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk          (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
26710  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos          (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
26711  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk          (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
26712 /* =======================================================  OCTACKCR  ======================================================== */
26713  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos         (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
26714  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk         (0xfUL)        /*!< OCTACKSEL (Bitfield-Mask: 0x0f)                       */
26715  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos        (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
26716  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk        (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
26717  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos        (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
26718  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk        (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
26719 /* =======================================================  CANFDCKCR  ======================================================= */
26720  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos       (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
26721  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk       (0xfUL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x0f)                      */
26722  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos      (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
26723  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk      (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
26724  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos      (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
26725  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk      (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
26726 /* =======================================================  USB60CKCR  ======================================================= */
26727  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos       (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
26728  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk       (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
26729  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos      (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
26730  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk      (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
26731  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos      (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
26732  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk      (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
26733 /* ========================================================  I3CCKCR  ======================================================== */
26734  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos           (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
26735  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk           (0xfUL)        /*!< I3CCKSEL (Bitfield-Mask: 0x0f)                        */
26736  #define R_SYSTEM_I3CCKCR_I3CCKREQ_Pos           (6UL)          /*!< I3CCKREQ (Bit 6)                                      */
26737  #define R_SYSTEM_I3CCKCR_I3CCKREQ_Msk           (0x40UL)       /*!< I3CCKREQ (Bitfield-Mask: 0x01)                        */
26738  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos          (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
26739  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk          (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
26740 /* ========================================================  MOSCSCR  ======================================================== */
26741  #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos           (0UL)          /*!< MOSCSOKP (Bit 0)                                      */
26742  #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk           (0x1UL)        /*!< MOSCSOKP (Bitfield-Mask: 0x01)                        */
26743 /* ========================================================  HOCOSCR  ======================================================== */
26744  #define R_SYSTEM_HOCOSCR_HOCOSOKP_Pos           (0UL)          /*!< HOCOSOKP (Bit 0)                                      */
26745  #define R_SYSTEM_HOCOSCR_HOCOSOKP_Msk           (0x1UL)        /*!< HOCOSOKP (Bitfield-Mask: 0x01)                        */
26746 /* =========================================================  OPCCR  ========================================================= */
26747  #define R_SYSTEM_OPCCR_OPCMTSF_Pos              (4UL)          /*!< OPCMTSF (Bit 4)                                       */
26748  #define R_SYSTEM_OPCCR_OPCMTSF_Msk              (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
26749  #define R_SYSTEM_OPCCR_OPCM_Pos                 (0UL)          /*!< OPCM (Bit 0)                                          */
26750  #define R_SYSTEM_OPCCR_OPCM_Msk                 (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
26751 /* =======================================================  MOSCWTCR  ======================================================== */
26752  #define R_SYSTEM_MOSCWTCR_MSTS_Pos              (0UL)          /*!< MSTS (Bit 0)                                          */
26753  #define R_SYSTEM_MOSCWTCR_MSTS_Msk              (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
26754 /* =======================================================  HOCOWTCR  ======================================================== */
26755  #define R_SYSTEM_HOCOWTCR_HSTS_Pos              (0UL)          /*!< HSTS (Bit 0)                                          */
26756  #define R_SYSTEM_HOCOWTCR_HSTS_Msk              (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
26757 /* ========================================================  SOPCCR  ========================================================= */
26758  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos            (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
26759  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk            (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
26760  #define R_SYSTEM_SOPCCR_SOPCM_Pos               (0UL)          /*!< SOPCM (Bit 0)                                         */
26761  #define R_SYSTEM_SOPCCR_SOPCM_Msk               (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
26762 /* ========================================================  RSTSR1  ========================================================= */
26763  #define R_SYSTEM_RSTSR1_IWDTRF_Pos              (0UL)          /*!< IWDTRF (Bit 0)                                        */
26764  #define R_SYSTEM_RSTSR1_IWDTRF_Msk              (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
26765  #define R_SYSTEM_RSTSR1_WDTRF_Pos               (1UL)          /*!< WDTRF (Bit 1)                                         */
26766  #define R_SYSTEM_RSTSR1_WDTRF_Msk               (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
26767  #define R_SYSTEM_RSTSR1_SWRF_Pos                (2UL)          /*!< SWRF (Bit 2)                                          */
26768  #define R_SYSTEM_RSTSR1_SWRF_Msk                (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
26769  #define R_SYSTEM_RSTSR1_CLU0RF_Pos              (4UL)          /*!< CLU0RF (Bit 4)                                        */
26770  #define R_SYSTEM_RSTSR1_CLU0RF_Msk              (0x10UL)       /*!< CLU0RF (Bitfield-Mask: 0x01)                          */
26771  #define R_SYSTEM_RSTSR1_LM0RF_Pos               (5UL)          /*!< LM0RF (Bit 5)                                         */
26772  #define R_SYSTEM_RSTSR1_LM0RF_Msk               (0x20UL)       /*!< LM0RF (Bitfield-Mask: 0x01)                           */
26773  #define R_SYSTEM_RSTSR1_BUSRF_Pos               (10UL)         /*!< BUSRF (Bit 10)                                        */
26774  #define R_SYSTEM_RSTSR1_BUSRF_Msk               (0x400UL)      /*!< BUSRF (Bitfield-Mask: 0x01)                           */
26775  #define R_SYSTEM_RSTSR1_CMRF_Pos                (14UL)         /*!< CMRF (Bit 14)                                         */
26776  #define R_SYSTEM_RSTSR1_CMRF_Msk                (0x4000UL)     /*!< CMRF (Bitfield-Mask: 0x01)                            */
26777  #define R_SYSTEM_RSTSR1_WDT1RF_Pos              (17UL)         /*!< WDT1RF (Bit 17)                                       */
26778  #define R_SYSTEM_RSTSR1_WDT1RF_Msk              (0x20000UL)    /*!< WDT1RF (Bitfield-Mask: 0x01)                          */
26779  #define R_SYSTEM_RSTSR1_CLU1RF_Pos              (20UL)         /*!< CLU1RF (Bit 20)                                       */
26780  #define R_SYSTEM_RSTSR1_CLU1RF_Msk              (0x100000UL)   /*!< CLU1RF (Bitfield-Mask: 0x01)                          */
26781  #define R_SYSTEM_RSTSR1_LM1RF_Pos               (21UL)         /*!< LM1RF (Bit 21)                                        */
26782  #define R_SYSTEM_RSTSR1_LM1RF_Msk               (0x200000UL)   /*!< LM1RF (Bitfield-Mask: 0x01)                           */
26783  #define R_SYSTEM_RSTSR1_NWRF_Pos                (22UL)         /*!< NWRF (Bit 22)                                         */
26784  #define R_SYSTEM_RSTSR1_NWRF_Msk                (0x400000UL)   /*!< NWRF (Bitfield-Mask: 0x01)                            */
26785 /* ========================================================  SYRACCR  ======================================================== */
26786  #define R_SYSTEM_SYRACCR_BUSY_Pos               (0UL)          /*!< BUSY (Bit 0)                                          */
26787  #define R_SYSTEM_SYRACCR_BUSY_Msk               (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
26788 /* ========================================================  LVD1CR1  ======================================================== */
26789  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
26790  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
26791  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
26792  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
26793 /* ========================================================  LVD2CR1  ======================================================== */
26794  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
26795  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
26796  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
26797  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
26798 /* ========================================================  LVD1SR  ========================================================= */
26799  #define R_SYSTEM_LVD1SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
26800  #define R_SYSTEM_LVD1SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
26801  #define R_SYSTEM_LVD1SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
26802  #define R_SYSTEM_LVD1SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
26803 /* ========================================================  LVD2SR  ========================================================= */
26804  #define R_SYSTEM_LVD2SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
26805  #define R_SYSTEM_LVD2SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
26806  #define R_SYSTEM_LVD2SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
26807  #define R_SYSTEM_LVD2SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
26808 /* =======================================================  CRVSYSCR  ======================================================== */
26809  #define R_SYSTEM_CRVSYSCR_CRVEN_Pos             (0UL)          /*!< CRVEN (Bit 0)                                         */
26810  #define R_SYSTEM_CRVSYSCR_CRVEN_Msk             (0x1UL)        /*!< CRVEN (Bitfield-Mask: 0x01)                           */
26811 /* ========================================================  PDCTRGD  ======================================================== */
26812  #define R_SYSTEM_PDCTRGD_PDDE_Pos               (0UL)          /*!< PDDE (Bit 0)                                          */
26813  #define R_SYSTEM_PDCTRGD_PDDE_Msk               (0x1UL)        /*!< PDDE (Bitfield-Mask: 0x01)                            */
26814  #define R_SYSTEM_PDCTRGD_PDCSF_Pos              (6UL)          /*!< PDCSF (Bit 6)                                         */
26815  #define R_SYSTEM_PDCTRGD_PDCSF_Msk              (0x40UL)       /*!< PDCSF (Bitfield-Mask: 0x01)                           */
26816  #define R_SYSTEM_PDCTRGD_PDPGSF_Pos             (7UL)          /*!< PDPGSF (Bit 7)                                        */
26817  #define R_SYSTEM_PDCTRGD_PDPGSF_Msk             (0x80UL)       /*!< PDPGSF (Bitfield-Mask: 0x01)                          */
26818 /* =======================================================  PDRAMSCR0  ======================================================= */
26819 /* =======================================================  PDRAMSCR1  ======================================================= */
26820 /* =======================================================  VBRSABAR  ======================================================== */
26821  #define R_SYSTEM_VBRSABAR_SABA_Pos              (0UL)          /*!< SABA (Bit 0)                                          */
26822  #define R_SYSTEM_VBRSABAR_SABA_Msk              (0xffffUL)     /*!< SABA (Bitfield-Mask: 0xffff)                          */
26823 /* =======================================================  VBRPABARS  ======================================================= */
26824  #define R_SYSTEM_VBRPABARS_PABAS_Pos            (0UL)          /*!< PABAS (Bit 0)                                         */
26825  #define R_SYSTEM_VBRPABARS_PABAS_Msk            (0xffffUL)     /*!< PABAS (Bitfield-Mask: 0xffff)                         */
26826 /* ======================================================  VBRPABARNS  ======================================================= */
26827  #define R_SYSTEM_VBRPABARNS_PABANS_Pos          (0UL)          /*!< PABANS (Bit 0)                                        */
26828  #define R_SYSTEM_VBRPABARNS_PABANS_Msk          (0xffffUL)     /*!< PABANS (Bitfield-Mask: 0xffff)                        */
26829 /* ========================================================  CGFSAR  ========================================================= */
26830  #define R_SYSTEM_CGFSAR_NONSEC00_Pos            (0UL)          /*!< NONSEC00 (Bit 0)                                      */
26831  #define R_SYSTEM_CGFSAR_NONSEC00_Msk            (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
26832  #define R_SYSTEM_CGFSAR_NONSEC02_Pos            (2UL)          /*!< NONSEC02 (Bit 2)                                      */
26833  #define R_SYSTEM_CGFSAR_NONSEC02_Msk            (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
26834  #define R_SYSTEM_CGFSAR_NONSEC03_Pos            (3UL)          /*!< NONSEC03 (Bit 3)                                      */
26835  #define R_SYSTEM_CGFSAR_NONSEC03_Msk            (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
26836  #define R_SYSTEM_CGFSAR_NONSEC04_Pos            (4UL)          /*!< NONSEC04 (Bit 4)                                      */
26837  #define R_SYSTEM_CGFSAR_NONSEC04_Msk            (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
26838  #define R_SYSTEM_CGFSAR_NONSEC05_Pos            (5UL)          /*!< NONSEC05 (Bit 5)                                      */
26839  #define R_SYSTEM_CGFSAR_NONSEC05_Msk            (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
26840  #define R_SYSTEM_CGFSAR_NONSEC06_Pos            (6UL)          /*!< NONSEC06 (Bit 6)                                      */
26841  #define R_SYSTEM_CGFSAR_NONSEC06_Msk            (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
26842  #define R_SYSTEM_CGFSAR_NONSEC07_Pos            (7UL)          /*!< NONSEC07 (Bit 7)                                      */
26843  #define R_SYSTEM_CGFSAR_NONSEC07_Msk            (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
26844  #define R_SYSTEM_CGFSAR_NONSEC08_Pos            (8UL)          /*!< NONSEC08 (Bit 8)                                      */
26845  #define R_SYSTEM_CGFSAR_NONSEC08_Msk            (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
26846  #define R_SYSTEM_CGFSAR_NONSEC09_Pos            (9UL)          /*!< NONSEC09 (Bit 9)                                      */
26847  #define R_SYSTEM_CGFSAR_NONSEC09_Msk            (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
26848  #define R_SYSTEM_CGFSAR_NONSEC11_Pos            (11UL)         /*!< NONSEC11 (Bit 11)                                     */
26849  #define R_SYSTEM_CGFSAR_NONSEC11_Msk            (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
26850  #define R_SYSTEM_CGFSAR_NONSEC12_Pos            (12UL)         /*!< NONSEC12 (Bit 12)                                     */
26851  #define R_SYSTEM_CGFSAR_NONSEC12_Msk            (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
26852  #define R_SYSTEM_CGFSAR_NONSEC13_Pos            (13UL)         /*!< NONSEC13 (Bit 13)                                     */
26853  #define R_SYSTEM_CGFSAR_NONSEC13_Msk            (0x2000UL)     /*!< NONSEC13 (Bitfield-Mask: 0x01)                        */
26854  #define R_SYSTEM_CGFSAR_NONSEC16_Pos            (16UL)         /*!< NONSEC16 (Bit 16)                                     */
26855  #define R_SYSTEM_CGFSAR_NONSEC16_Msk            (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
26856  #define R_SYSTEM_CGFSAR_NONSEC17_Pos            (17UL)         /*!< NONSEC17 (Bit 17)                                     */
26857  #define R_SYSTEM_CGFSAR_NONSEC17_Msk            (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
26858  #define R_SYSTEM_CGFSAR_NONSEC18_Pos            (18UL)         /*!< NONSEC18 (Bit 18)                                     */
26859  #define R_SYSTEM_CGFSAR_NONSEC18_Msk            (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
26860  #define R_SYSTEM_CGFSAR_NONSEC19_Pos            (19UL)         /*!< NONSEC19 (Bit 19)                                     */
26861  #define R_SYSTEM_CGFSAR_NONSEC19_Msk            (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
26862  #define R_SYSTEM_CGFSAR_NONSEC20_Pos            (20UL)         /*!< NONSEC20 (Bit 20)                                     */
26863  #define R_SYSTEM_CGFSAR_NONSEC20_Msk            (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
26864  #define R_SYSTEM_CGFSAR_NONSEC21_Pos            (21UL)         /*!< NONSEC21 (Bit 21)                                     */
26865  #define R_SYSTEM_CGFSAR_NONSEC21_Msk            (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
26866  #define R_SYSTEM_CGFSAR_NONSEC22_Pos            (22UL)         /*!< NONSEC22 (Bit 22)                                     */
26867  #define R_SYSTEM_CGFSAR_NONSEC22_Msk            (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
26868  #define R_SYSTEM_CGFSAR_NONSEC24_Pos            (24UL)         /*!< NONSEC24 (Bit 24)                                     */
26869  #define R_SYSTEM_CGFSAR_NONSEC24_Msk            (0x1000000UL)  /*!< NONSEC24 (Bitfield-Mask: 0x01)                        */
26870  #define R_SYSTEM_CGFSAR_NONSEC25_Pos            (25UL)         /*!< NONSEC25 (Bit 25)                                     */
26871  #define R_SYSTEM_CGFSAR_NONSEC25_Msk            (0x2000000UL)  /*!< NONSEC25 (Bitfield-Mask: 0x01)                        */
26872  #define R_SYSTEM_CGFSAR_NONSEC26_Pos            (26UL)         /*!< NONSEC26 (Bit 26)                                     */
26873  #define R_SYSTEM_CGFSAR_NONSEC26_Msk            (0x4000000UL)  /*!< NONSEC26 (Bitfield-Mask: 0x01)                        */
26874 /* ========================================================  RSTSAR  ========================================================= */
26875  #define R_SYSTEM_RSTSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26876  #define R_SYSTEM_RSTSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26877  #define R_SYSTEM_RSTSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26878  #define R_SYSTEM_RSTSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26879  #define R_SYSTEM_RSTSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26880  #define R_SYSTEM_RSTSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26881  #define R_SYSTEM_RSTSAR_NONSEC3_Pos             (3UL)          /*!< NONSEC3 (Bit 3)                                       */
26882  #define R_SYSTEM_RSTSAR_NONSEC3_Msk             (0x8UL)        /*!< NONSEC3 (Bitfield-Mask: 0x01)                         */
26883 /* ========================================================  LPMSAR  ========================================================= */
26884  #define R_SYSTEM_LPMSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26885  #define R_SYSTEM_LPMSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26886  #define R_SYSTEM_LPMSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26887  #define R_SYSTEM_LPMSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26888  #define R_SYSTEM_LPMSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26889  #define R_SYSTEM_LPMSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26890  #define R_SYSTEM_LPMSAR_NONSEC3_Pos             (3UL)          /*!< NONSEC3 (Bit 3)                                       */
26891  #define R_SYSTEM_LPMSAR_NONSEC3_Msk             (0x8UL)        /*!< NONSEC3 (Bitfield-Mask: 0x01)                         */
26892  #define R_SYSTEM_LPMSAR_NONSEC8_Pos             (8UL)          /*!< NONSEC8 (Bit 8)                                       */
26893  #define R_SYSTEM_LPMSAR_NONSEC8_Msk             (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
26894  #define R_SYSTEM_LPMSAR_NONSEC16_Pos            (16UL)         /*!< NONSEC16 (Bit 16)                                     */
26895  #define R_SYSTEM_LPMSAR_NONSEC16_Msk            (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
26896  #define R_SYSTEM_LPMSAR_NONSEC17_Pos            (17UL)         /*!< NONSEC17 (Bit 17)                                     */
26897  #define R_SYSTEM_LPMSAR_NONSEC17_Msk            (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
26898  #define R_SYSTEM_LPMSAR_NONSEC18_Pos            (18UL)         /*!< NONSEC18 (Bit 18)                                     */
26899  #define R_SYSTEM_LPMSAR_NONSEC18_Msk            (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
26900  #define R_SYSTEM_LPMSAR_NONSEC19_Pos            (19UL)         /*!< NONSEC19 (Bit 19)                                     */
26901  #define R_SYSTEM_LPMSAR_NONSEC19_Msk            (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
26902  #define R_SYSTEM_LPMSAR_NONSEC21_Pos            (21UL)         /*!< NONSEC21 (Bit 21)                                     */
26903  #define R_SYSTEM_LPMSAR_NONSEC21_Msk            (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
26904 /* ========================================================  LVDSAR  ========================================================= */
26905  #define R_SYSTEM_LVDSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26906  #define R_SYSTEM_LVDSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26907  #define R_SYSTEM_LVDSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26908  #define R_SYSTEM_LVDSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26909 /* ========================================================  BBFSAR  ========================================================= */
26910  #define R_SYSTEM_BBFSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26911  #define R_SYSTEM_BBFSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26912  #define R_SYSTEM_BBFSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26913  #define R_SYSTEM_BBFSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26914  #define R_SYSTEM_BBFSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26915  #define R_SYSTEM_BBFSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26916  #define R_SYSTEM_BBFSAR_NONSEC3_Pos             (3UL)          /*!< NONSEC3 (Bit 3)                                       */
26917  #define R_SYSTEM_BBFSAR_NONSEC3_Msk             (0x8UL)        /*!< NONSEC3 (Bitfield-Mask: 0x01)                         */
26918  #define R_SYSTEM_BBFSAR_NONSEC4_Pos             (4UL)          /*!< NONSEC4 (Bit 4)                                       */
26919  #define R_SYSTEM_BBFSAR_NONSEC4_Msk             (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
26920 /* ========================================================  PGCSAR  ========================================================= */
26921  #define R_SYSTEM_PGCSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26922  #define R_SYSTEM_PGCSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26923  #define R_SYSTEM_PGCSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26924  #define R_SYSTEM_PGCSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26925 /* ========================================================  DPFSAR  ========================================================= */
26926  #define R_SYSTEM_DPFSAR_DPFSA16_Pos             (16UL)         /*!< DPFSA16 (Bit 16)                                      */
26927  #define R_SYSTEM_DPFSAR_DPFSA16_Msk             (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
26928  #define R_SYSTEM_DPFSAR_DPFSA17_Pos             (17UL)         /*!< DPFSA17 (Bit 17)                                      */
26929  #define R_SYSTEM_DPFSAR_DPFSA17_Msk             (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
26930  #define R_SYSTEM_DPFSAR_DPFSA18_Pos             (18UL)         /*!< DPFSA18 (Bit 18)                                      */
26931  #define R_SYSTEM_DPFSAR_DPFSA18_Msk             (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
26932  #define R_SYSTEM_DPFSAR_DPFSA19_Pos             (19UL)         /*!< DPFSA19 (Bit 19)                                      */
26933  #define R_SYSTEM_DPFSAR_DPFSA19_Msk             (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
26934  #define R_SYSTEM_DPFSAR_DPFSA20_Pos             (20UL)         /*!< DPFSA20 (Bit 20)                                      */
26935  #define R_SYSTEM_DPFSAR_DPFSA20_Msk             (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
26936  #define R_SYSTEM_DPFSAR_DPFSA24_Pos             (24UL)         /*!< DPFSA24 (Bit 24)                                      */
26937  #define R_SYSTEM_DPFSAR_DPFSA24_Msk             (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
26938  #define R_SYSTEM_DPFSAR_DPFSA25_Pos             (25UL)         /*!< DPFSA25 (Bit 25)                                      */
26939  #define R_SYSTEM_DPFSAR_DPFSA25_Msk             (0x2000000UL)  /*!< DPFSA25 (Bitfield-Mask: 0x01)                         */
26940  #define R_SYSTEM_DPFSAR_DPFSA26_Pos             (26UL)         /*!< DPFSA26 (Bit 26)                                      */
26941  #define R_SYSTEM_DPFSAR_DPFSA26_Msk             (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
26942  #define R_SYSTEM_DPFSAR_DPFSA27_Pos             (27UL)         /*!< DPFSA27 (Bit 27)                                      */
26943  #define R_SYSTEM_DPFSAR_DPFSA27_Msk             (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
26944  #define R_SYSTEM_DPFSAR_DPFSA29_Pos             (29UL)         /*!< DPFSA29 (Bit 29)                                      */
26945  #define R_SYSTEM_DPFSAR_DPFSA29_Msk             (0x20000000UL) /*!< DPFSA29 (Bitfield-Mask: 0x01)                         */
26946  #define R_SYSTEM_DPFSAR_DPFSA31_Pos             (31UL)         /*!< DPFSA31 (Bit 31)                                      */
26947  #define R_SYSTEM_DPFSAR_DPFSA31_Msk             (0x80000000UL) /*!< DPFSA31 (Bitfield-Mask: 0x01)                         */
26948 /* ========================================================  RSCSAR  ========================================================= */
26949  #define R_SYSTEM_RSCSAR_RSCSA0_Pos              (0UL)          /*!< RSCSA0 (Bit 0)                                        */
26950  #define R_SYSTEM_RSCSAR_RSCSA0_Msk              (0x1UL)        /*!< RSCSA0 (Bitfield-Mask: 0x01)                          */
26951  #define R_SYSTEM_RSCSAR_RSCSA1_Pos              (1UL)          /*!< RSCSA1 (Bit 1)                                        */
26952  #define R_SYSTEM_RSCSAR_RSCSA1_Msk              (0x2UL)        /*!< RSCSA1 (Bitfield-Mask: 0x01)                          */
26953  #define R_SYSTEM_RSCSAR_RSCSA2_Pos              (2UL)          /*!< RSCSA2 (Bit 2)                                        */
26954  #define R_SYSTEM_RSCSAR_RSCSA2_Msk              (0x4UL)        /*!< RSCSA2 (Bitfield-Mask: 0x01)                          */
26955  #define R_SYSTEM_RSCSAR_RSCSA3_Pos              (3UL)          /*!< RSCSA3 (Bit 3)                                        */
26956  #define R_SYSTEM_RSCSAR_RSCSA3_Msk              (0x8UL)        /*!< RSCSA3 (Bitfield-Mask: 0x01)                          */
26957  #define R_SYSTEM_RSCSAR_RSCSA4_Pos              (4UL)          /*!< RSCSA4 (Bit 4)                                        */
26958  #define R_SYSTEM_RSCSAR_RSCSA4_Msk              (0x10UL)       /*!< RSCSA4 (Bitfield-Mask: 0x01)                          */
26959  #define R_SYSTEM_RSCSAR_RSCSA5_Pos              (5UL)          /*!< RSCSA5 (Bit 5)                                        */
26960  #define R_SYSTEM_RSCSAR_RSCSA5_Msk              (0x20UL)       /*!< RSCSA5 (Bitfield-Mask: 0x01)                          */
26961  #define R_SYSTEM_RSCSAR_RSCSA6_Pos              (6UL)          /*!< RSCSA6 (Bit 6)                                        */
26962  #define R_SYSTEM_RSCSAR_RSCSA6_Msk              (0x40UL)       /*!< RSCSA6 (Bitfield-Mask: 0x01)                          */
26963  #define R_SYSTEM_RSCSAR_RSCSA7_Pos              (7UL)          /*!< RSCSA7 (Bit 7)                                        */
26964  #define R_SYSTEM_RSCSAR_RSCSA7_Msk              (0x80UL)       /*!< RSCSA7 (Bitfield-Mask: 0x01)                          */
26965  #define R_SYSTEM_RSCSAR_RSCSA8_Pos              (8UL)          /*!< RSCSA8 (Bit 8)                                        */
26966  #define R_SYSTEM_RSCSAR_RSCSA8_Msk              (0x100UL)      /*!< RSCSA8 (Bitfield-Mask: 0x01)                          */
26967  #define R_SYSTEM_RSCSAR_RSCSA9_Pos              (9UL)          /*!< RSCSA9 (Bit 9)                                        */
26968  #define R_SYSTEM_RSCSAR_RSCSA9_Msk              (0x200UL)      /*!< RSCSA9 (Bitfield-Mask: 0x01)                          */
26969  #define R_SYSTEM_RSCSAR_RSCSA10_Pos             (10UL)         /*!< RSCSA10 (Bit 10)                                      */
26970  #define R_SYSTEM_RSCSAR_RSCSA10_Msk             (0x400UL)      /*!< RSCSA10 (Bitfield-Mask: 0x01)                         */
26971  #define R_SYSTEM_RSCSAR_RSCSA11_Pos             (11UL)         /*!< RSCSA11 (Bit 11)                                      */
26972  #define R_SYSTEM_RSCSAR_RSCSA11_Msk             (0x800UL)      /*!< RSCSA11 (Bitfield-Mask: 0x01)                         */
26973  #define R_SYSTEM_RSCSAR_RSCSA12_Pos             (12UL)         /*!< RSCSA12 (Bit 12)                                      */
26974  #define R_SYSTEM_RSCSAR_RSCSA12_Msk             (0x1000UL)     /*!< RSCSA12 (Bitfield-Mask: 0x01)                         */
26975  #define R_SYSTEM_RSCSAR_RSCSA13_Pos             (13UL)         /*!< RSCSA13 (Bit 13)                                      */
26976  #define R_SYSTEM_RSCSAR_RSCSA13_Msk             (0x2000UL)     /*!< RSCSA13 (Bitfield-Mask: 0x01)                         */
26977  #define R_SYSTEM_RSCSAR_RSCSA14_Pos             (14UL)         /*!< RSCSA14 (Bit 14)                                      */
26978  #define R_SYSTEM_RSCSAR_RSCSA14_Msk             (0x4000UL)     /*!< RSCSA14 (Bitfield-Mask: 0x01)                         */
26979  #define R_SYSTEM_RSCSAR_RSCSA16_Pos             (16UL)         /*!< RSCSA16 (Bit 16)                                      */
26980  #define R_SYSTEM_RSCSAR_RSCSA16_Msk             (0x10000UL)    /*!< RSCSA16 (Bitfield-Mask: 0x01)                         */
26981  #define R_SYSTEM_RSCSAR_RSCSA17_Pos             (17UL)         /*!< RSCSA17 (Bit 17)                                      */
26982  #define R_SYSTEM_RSCSAR_RSCSA17_Msk             (0x20000UL)    /*!< RSCSA17 (Bitfield-Mask: 0x01)                         */
26983 /* =========================================================  PRCR  ========================================================== */
26984  #define R_SYSTEM_PRCR_PRC0_Pos                  (0UL)          /*!< PRC0 (Bit 0)                                          */
26985  #define R_SYSTEM_PRCR_PRC0_Msk                  (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
26986  #define R_SYSTEM_PRCR_PRC1_Pos                  (1UL)          /*!< PRC1 (Bit 1)                                          */
26987  #define R_SYSTEM_PRCR_PRC1_Msk                  (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
26988  #define R_SYSTEM_PRCR_PRC3_Pos                  (3UL)          /*!< PRC3 (Bit 3)                                          */
26989  #define R_SYSTEM_PRCR_PRC3_Msk                  (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
26990  #define R_SYSTEM_PRCR_PRC4_Pos                  (4UL)          /*!< PRC4 (Bit 4)                                          */
26991  #define R_SYSTEM_PRCR_PRC4_Msk                  (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
26992  #define R_SYSTEM_PRCR_PRC5_Pos                  (5UL)          /*!< PRC5 (Bit 5)                                          */
26993  #define R_SYSTEM_PRCR_PRC5_Msk                  (0x20UL)       /*!< PRC5 (Bitfield-Mask: 0x01)                            */
26994  #define R_SYSTEM_PRCR_PRKEY_Pos                 (8UL)          /*!< PRKEY (Bit 8)                                         */
26995  #define R_SYSTEM_PRCR_PRKEY_Msk                 (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
26996 /* ========================================================  PRCR_NS  ======================================================== */
26997  #define R_SYSTEM_PRCR_NS_PRC0_Pos               (0UL)          /*!< PRC0 (Bit 0)                                          */
26998  #define R_SYSTEM_PRCR_NS_PRC0_Msk               (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
26999  #define R_SYSTEM_PRCR_NS_PRC1_Pos               (1UL)          /*!< PRC1 (Bit 1)                                          */
27000  #define R_SYSTEM_PRCR_NS_PRC1_Msk               (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
27001  #define R_SYSTEM_PRCR_NS_PRC3_Pos               (3UL)          /*!< PRC3 (Bit 3)                                          */
27002  #define R_SYSTEM_PRCR_NS_PRC3_Msk               (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
27003  #define R_SYSTEM_PRCR_NS_PRC4_Pos               (4UL)          /*!< PRC4 (Bit 4)                                          */
27004  #define R_SYSTEM_PRCR_NS_PRC4_Msk               (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
27005  #define R_SYSTEM_PRCR_NS_PRKEY_Pos              (8UL)          /*!< PRKEY (Bit 8)                                         */
27006  #define R_SYSTEM_PRCR_NS_PRKEY_Msk              (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
27007 /* ========================================================  LOCOCR  ========================================================= */
27008  #define R_SYSTEM_LOCOCR_LCSTP_Pos               (0UL)          /*!< LCSTP (Bit 0)                                         */
27009  #define R_SYSTEM_LOCOCR_LCSTP_Msk               (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
27010 /* =======================================================  LOCOUTCR  ======================================================== */
27011  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos          (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
27012  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk          (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
27013 /* ========================================================  STCONR  ========================================================= */
27014  #define R_SYSTEM_STCONR_STCON_Pos               (0UL)          /*!< STCON (Bit 0)                                         */
27015  #define R_SYSTEM_STCONR_STCON_Msk               (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
27016 /* ========================================================  DPSBYCR  ======================================================== */
27017  #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos           (2UL)          /*!< DCSSMODE (Bit 2)                                      */
27018  #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk           (0x4UL)        /*!< DCSSMODE (Bitfield-Mask: 0x01)                        */
27019  #define R_SYSTEM_DPSBYCR_SRKEEP_Pos             (4UL)          /*!< SRKEEP (Bit 4)                                        */
27020  #define R_SYSTEM_DPSBYCR_SRKEEP_Msk             (0x10UL)       /*!< SRKEEP (Bitfield-Mask: 0x01)                          */
27021  #define R_SYSTEM_DPSBYCR_IOKEEP_Pos             (6UL)          /*!< IOKEEP (Bit 6)                                        */
27022  #define R_SYSTEM_DPSBYCR_IOKEEP_Msk             (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
27023  #define R_SYSTEM_DPSBYCR_DPSBY_Pos              (7UL)          /*!< DPSBY (Bit 7)                                         */
27024  #define R_SYSTEM_DPSBYCR_DPSBY_Msk              (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
27025 /* ========================================================  DPSWCR  ========================================================= */
27026  #define R_SYSTEM_DPSWCR_WTSTS_Pos               (0UL)          /*!< WTSTS (Bit 0)                                         */
27027  #define R_SYSTEM_DPSWCR_WTSTS_Msk               (0xffUL)       /*!< WTSTS (Bitfield-Mask: 0xff)                           */
27028 /* ========================================================  DPSIER0  ======================================================== */
27029  #define R_SYSTEM_DPSIER0_DIRQ0E_Pos             (0UL)          /*!< DIRQ0E (Bit 0)                                        */
27030  #define R_SYSTEM_DPSIER0_DIRQ0E_Msk             (0x1UL)        /*!< DIRQ0E (Bitfield-Mask: 0x01)                          */
27031  #define R_SYSTEM_DPSIER0_DIRQ1E_Pos             (1UL)          /*!< DIRQ1E (Bit 1)                                        */
27032  #define R_SYSTEM_DPSIER0_DIRQ1E_Msk             (0x2UL)        /*!< DIRQ1E (Bitfield-Mask: 0x01)                          */
27033  #define R_SYSTEM_DPSIER0_DIRQ2E_Pos             (2UL)          /*!< DIRQ2E (Bit 2)                                        */
27034  #define R_SYSTEM_DPSIER0_DIRQ2E_Msk             (0x4UL)        /*!< DIRQ2E (Bitfield-Mask: 0x01)                          */
27035  #define R_SYSTEM_DPSIER0_DIRQ3E_Pos             (3UL)          /*!< DIRQ3E (Bit 3)                                        */
27036  #define R_SYSTEM_DPSIER0_DIRQ3E_Msk             (0x8UL)        /*!< DIRQ3E (Bitfield-Mask: 0x01)                          */
27037  #define R_SYSTEM_DPSIER0_DIRQ4E_Pos             (4UL)          /*!< DIRQ4E (Bit 4)                                        */
27038  #define R_SYSTEM_DPSIER0_DIRQ4E_Msk             (0x10UL)       /*!< DIRQ4E (Bitfield-Mask: 0x01)                          */
27039  #define R_SYSTEM_DPSIER0_DIRQ5E_Pos             (5UL)          /*!< DIRQ5E (Bit 5)                                        */
27040  #define R_SYSTEM_DPSIER0_DIRQ5E_Msk             (0x20UL)       /*!< DIRQ5E (Bitfield-Mask: 0x01)                          */
27041  #define R_SYSTEM_DPSIER0_DIRQ6E_Pos             (6UL)          /*!< DIRQ6E (Bit 6)                                        */
27042  #define R_SYSTEM_DPSIER0_DIRQ6E_Msk             (0x40UL)       /*!< DIRQ6E (Bitfield-Mask: 0x01)                          */
27043  #define R_SYSTEM_DPSIER0_DIRQ7E_Pos             (7UL)          /*!< DIRQ7E (Bit 7)                                        */
27044  #define R_SYSTEM_DPSIER0_DIRQ7E_Msk             (0x80UL)       /*!< DIRQ7E (Bitfield-Mask: 0x01)                          */
27045 /* ========================================================  DPSIER1  ======================================================== */
27046  #define R_SYSTEM_DPSIER1_DIRQ8E_Pos             (0UL)          /*!< DIRQ8E (Bit 0)                                        */
27047  #define R_SYSTEM_DPSIER1_DIRQ8E_Msk             (0x1UL)        /*!< DIRQ8E (Bitfield-Mask: 0x01)                          */
27048  #define R_SYSTEM_DPSIER1_DIRQ9E_Pos             (1UL)          /*!< DIRQ9E (Bit 1)                                        */
27049  #define R_SYSTEM_DPSIER1_DIRQ9E_Msk             (0x2UL)        /*!< DIRQ9E (Bitfield-Mask: 0x01)                          */
27050  #define R_SYSTEM_DPSIER1_DIRQ10E_Pos            (2UL)          /*!< DIRQ10E (Bit 2)                                       */
27051  #define R_SYSTEM_DPSIER1_DIRQ10E_Msk            (0x4UL)        /*!< DIRQ10E (Bitfield-Mask: 0x01)                         */
27052  #define R_SYSTEM_DPSIER1_DIRQ11E_Pos            (3UL)          /*!< DIRQ11E (Bit 3)                                       */
27053  #define R_SYSTEM_DPSIER1_DIRQ11E_Msk            (0x8UL)        /*!< DIRQ11E (Bitfield-Mask: 0x01)                         */
27054  #define R_SYSTEM_DPSIER1_DIRQ12E_Pos            (4UL)          /*!< DIRQ12E (Bit 4)                                       */
27055  #define R_SYSTEM_DPSIER1_DIRQ12E_Msk            (0x10UL)       /*!< DIRQ12E (Bitfield-Mask: 0x01)                         */
27056  #define R_SYSTEM_DPSIER1_DIRQ13E_Pos            (5UL)          /*!< DIRQ13E (Bit 5)                                       */
27057  #define R_SYSTEM_DPSIER1_DIRQ13E_Msk            (0x20UL)       /*!< DIRQ13E (Bitfield-Mask: 0x01)                         */
27058  #define R_SYSTEM_DPSIER1_DIRQ14E_Pos            (6UL)          /*!< DIRQ14E (Bit 6)                                       */
27059  #define R_SYSTEM_DPSIER1_DIRQ14E_Msk            (0x40UL)       /*!< DIRQ14E (Bitfield-Mask: 0x01)                         */
27060  #define R_SYSTEM_DPSIER1_DIRQ15E_Pos            (7UL)          /*!< DIRQ15E (Bit 7)                                       */
27061  #define R_SYSTEM_DPSIER1_DIRQ15E_Msk            (0x80UL)       /*!< DIRQ15E (Bitfield-Mask: 0x01)                         */
27062 /* ========================================================  DPSIER2  ======================================================== */
27063  #define R_SYSTEM_DPSIER2_DPVD1IE_Pos            (0UL)          /*!< DPVD1IE (Bit 0)                                       */
27064  #define R_SYSTEM_DPSIER2_DPVD1IE_Msk            (0x1UL)        /*!< DPVD1IE (Bitfield-Mask: 0x01)                         */
27065  #define R_SYSTEM_DPSIER2_DPVD2IE_Pos            (1UL)          /*!< DPVD2IE (Bit 1)                                       */
27066  #define R_SYSTEM_DPSIER2_DPVD2IE_Msk            (0x2UL)        /*!< DPVD2IE (Bitfield-Mask: 0x01)                         */
27067  #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos           (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
27068  #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk           (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
27069  #define R_SYSTEM_DPSIER2_DRTCAIE_Pos            (3UL)          /*!< DRTCAIE (Bit 3)                                       */
27070  #define R_SYSTEM_DPSIER2_DRTCAIE_Msk            (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
27071  #define R_SYSTEM_DPSIER2_DNMIE_Pos              (4UL)          /*!< DNMIE (Bit 4)                                         */
27072  #define R_SYSTEM_DPSIER2_DNMIE_Msk              (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
27073 /* ========================================================  DPSIER3  ======================================================== */
27074  #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos           (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
27075  #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk           (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
27076  #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos           (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
27077  #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk           (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
27078  #define R_SYSTEM_DPSIER3_DULPT0IE_Pos           (2UL)          /*!< DULPT0IE (Bit 2)                                      */
27079  #define R_SYSTEM_DPSIER3_DULPT0IE_Msk           (0x4UL)        /*!< DULPT0IE (Bitfield-Mask: 0x01)                        */
27080  #define R_SYSTEM_DPSIER3_DULPT1IE_Pos           (3UL)          /*!< DULPT1IE (Bit 3)                                      */
27081  #define R_SYSTEM_DPSIER3_DULPT1IE_Msk           (0x8UL)        /*!< DULPT1IE (Bitfield-Mask: 0x01)                        */
27082  #define R_SYSTEM_DPSIER3_DIWDTIE_Pos            (5UL)          /*!< DIWDTIE (Bit 5)                                       */
27083  #define R_SYSTEM_DPSIER3_DIWDTIE_Msk            (0x20UL)       /*!< DIWDTIE (Bitfield-Mask: 0x01)                         */
27084  #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos         (7UL)          /*!< DVBATTADIE (Bit 7)                                    */
27085  #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk         (0x80UL)       /*!< DVBATTADIE (Bitfield-Mask: 0x01)                      */
27086 /* ========================================================  DPSIFR0  ======================================================== */
27087  #define R_SYSTEM_DPSIFR0_DIRQ0F_Pos             (0UL)          /*!< DIRQ0F (Bit 0)                                        */
27088  #define R_SYSTEM_DPSIFR0_DIRQ0F_Msk             (0x1UL)        /*!< DIRQ0F (Bitfield-Mask: 0x01)                          */
27089  #define R_SYSTEM_DPSIFR0_DIRQ1F_Pos             (1UL)          /*!< DIRQ1F (Bit 1)                                        */
27090  #define R_SYSTEM_DPSIFR0_DIRQ1F_Msk             (0x2UL)        /*!< DIRQ1F (Bitfield-Mask: 0x01)                          */
27091  #define R_SYSTEM_DPSIFR0_DIRQ2F_Pos             (2UL)          /*!< DIRQ2F (Bit 2)                                        */
27092  #define R_SYSTEM_DPSIFR0_DIRQ2F_Msk             (0x4UL)        /*!< DIRQ2F (Bitfield-Mask: 0x01)                          */
27093  #define R_SYSTEM_DPSIFR0_DIRQ3F_Pos             (3UL)          /*!< DIRQ3F (Bit 3)                                        */
27094  #define R_SYSTEM_DPSIFR0_DIRQ3F_Msk             (0x8UL)        /*!< DIRQ3F (Bitfield-Mask: 0x01)                          */
27095  #define R_SYSTEM_DPSIFR0_DIRQ4F_Pos             (4UL)          /*!< DIRQ4F (Bit 4)                                        */
27096  #define R_SYSTEM_DPSIFR0_DIRQ4F_Msk             (0x10UL)       /*!< DIRQ4F (Bitfield-Mask: 0x01)                          */
27097  #define R_SYSTEM_DPSIFR0_DIRQ5F_Pos             (5UL)          /*!< DIRQ5F (Bit 5)                                        */
27098  #define R_SYSTEM_DPSIFR0_DIRQ5F_Msk             (0x20UL)       /*!< DIRQ5F (Bitfield-Mask: 0x01)                          */
27099  #define R_SYSTEM_DPSIFR0_DIRQ6F_Pos             (6UL)          /*!< DIRQ6F (Bit 6)                                        */
27100  #define R_SYSTEM_DPSIFR0_DIRQ6F_Msk             (0x40UL)       /*!< DIRQ6F (Bitfield-Mask: 0x01)                          */
27101  #define R_SYSTEM_DPSIFR0_DIRQ7F_Pos             (7UL)          /*!< DIRQ7F (Bit 7)                                        */
27102  #define R_SYSTEM_DPSIFR0_DIRQ7F_Msk             (0x80UL)       /*!< DIRQ7F (Bitfield-Mask: 0x01)                          */
27103 /* ========================================================  DPSIFR1  ======================================================== */
27104  #define R_SYSTEM_DPSIFR1_DIRQ8F_Pos             (0UL)          /*!< DIRQ8F (Bit 0)                                        */
27105  #define R_SYSTEM_DPSIFR1_DIRQ8F_Msk             (0x1UL)        /*!< DIRQ8F (Bitfield-Mask: 0x01)                          */
27106  #define R_SYSTEM_DPSIFR1_DIRQ9F_Pos             (1UL)          /*!< DIRQ9F (Bit 1)                                        */
27107  #define R_SYSTEM_DPSIFR1_DIRQ9F_Msk             (0x2UL)        /*!< DIRQ9F (Bitfield-Mask: 0x01)                          */
27108  #define R_SYSTEM_DPSIFR1_DIRQ10F_Pos            (2UL)          /*!< DIRQ10F (Bit 2)                                       */
27109  #define R_SYSTEM_DPSIFR1_DIRQ10F_Msk            (0x4UL)        /*!< DIRQ10F (Bitfield-Mask: 0x01)                         */
27110  #define R_SYSTEM_DPSIFR1_DIRQ11F_Pos            (3UL)          /*!< DIRQ11F (Bit 3)                                       */
27111  #define R_SYSTEM_DPSIFR1_DIRQ11F_Msk            (0x8UL)        /*!< DIRQ11F (Bitfield-Mask: 0x01)                         */
27112  #define R_SYSTEM_DPSIFR1_DIRQ12F_Pos            (4UL)          /*!< DIRQ12F (Bit 4)                                       */
27113  #define R_SYSTEM_DPSIFR1_DIRQ12F_Msk            (0x10UL)       /*!< DIRQ12F (Bitfield-Mask: 0x01)                         */
27114  #define R_SYSTEM_DPSIFR1_DIRQ13F_Pos            (5UL)          /*!< DIRQ13F (Bit 5)                                       */
27115  #define R_SYSTEM_DPSIFR1_DIRQ13F_Msk            (0x20UL)       /*!< DIRQ13F (Bitfield-Mask: 0x01)                         */
27116  #define R_SYSTEM_DPSIFR1_DIRQ14F_Pos            (6UL)          /*!< DIRQ14F (Bit 6)                                       */
27117  #define R_SYSTEM_DPSIFR1_DIRQ14F_Msk            (0x40UL)       /*!< DIRQ14F (Bitfield-Mask: 0x01)                         */
27118  #define R_SYSTEM_DPSIFR1_DIRQ15F_Pos            (7UL)          /*!< DIRQ15F (Bit 7)                                       */
27119  #define R_SYSTEM_DPSIFR1_DIRQ15F_Msk            (0x80UL)       /*!< DIRQ15F (Bitfield-Mask: 0x01)                         */
27120 /* ========================================================  DPSIFR2  ======================================================== */
27121  #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos            (0UL)          /*!< DPVD1IF (Bit 0)                                       */
27122  #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk            (0x1UL)        /*!< DPVD1IF (Bitfield-Mask: 0x01)                         */
27123  #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos            (1UL)          /*!< DPVD2IF (Bit 1)                                       */
27124  #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk            (0x2UL)        /*!< DPVD2IF (Bitfield-Mask: 0x01)                         */
27125  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos           (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
27126  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk           (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
27127  #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos            (3UL)          /*!< DRTCAIF (Bit 3)                                       */
27128  #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk            (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
27129  #define R_SYSTEM_DPSIFR2_DNMIF_Pos              (4UL)          /*!< DNMIF (Bit 4)                                         */
27130  #define R_SYSTEM_DPSIFR2_DNMIF_Msk              (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
27131 /* ========================================================  DPSIFR3  ======================================================== */
27132  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos           (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
27133  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk           (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
27134  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos           (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
27135  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk           (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
27136  #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos           (2UL)          /*!< DULPT0IF (Bit 2)                                      */
27137  #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk           (0x4UL)        /*!< DULPT0IF (Bitfield-Mask: 0x01)                        */
27138  #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos           (3UL)          /*!< DULPT1IF (Bit 3)                                      */
27139  #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk           (0x8UL)        /*!< DULPT1IF (Bitfield-Mask: 0x01)                        */
27140  #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos            (5UL)          /*!< DIWDTIF (Bit 5)                                       */
27141  #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk            (0x20UL)       /*!< DIWDTIF (Bitfield-Mask: 0x01)                         */
27142  #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos         (7UL)          /*!< DVBATTADIF (Bit 7)                                    */
27143  #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk         (0x80UL)       /*!< DVBATTADIF (Bitfield-Mask: 0x01)                      */
27144 /* =======================================================  DPSIEGR0  ======================================================== */
27145  #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos           (0UL)          /*!< DIRQ0EG (Bit 0)                                       */
27146  #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk           (0x1UL)        /*!< DIRQ0EG (Bitfield-Mask: 0x01)                         */
27147  #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos           (1UL)          /*!< DIRQ1EG (Bit 1)                                       */
27148  #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk           (0x2UL)        /*!< DIRQ1EG (Bitfield-Mask: 0x01)                         */
27149  #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos           (2UL)          /*!< DIRQ2EG (Bit 2)                                       */
27150  #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk           (0x4UL)        /*!< DIRQ2EG (Bitfield-Mask: 0x01)                         */
27151  #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos           (3UL)          /*!< DIRQ3EG (Bit 3)                                       */
27152  #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk           (0x8UL)        /*!< DIRQ3EG (Bitfield-Mask: 0x01)                         */
27153  #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos           (4UL)          /*!< DIRQ4EG (Bit 4)                                       */
27154  #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk           (0x10UL)       /*!< DIRQ4EG (Bitfield-Mask: 0x01)                         */
27155  #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos           (5UL)          /*!< DIRQ5EG (Bit 5)                                       */
27156  #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk           (0x20UL)       /*!< DIRQ5EG (Bitfield-Mask: 0x01)                         */
27157  #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos           (6UL)          /*!< DIRQ6EG (Bit 6)                                       */
27158  #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk           (0x40UL)       /*!< DIRQ6EG (Bitfield-Mask: 0x01)                         */
27159  #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos           (7UL)          /*!< DIRQ7EG (Bit 7)                                       */
27160  #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk           (0x80UL)       /*!< DIRQ7EG (Bitfield-Mask: 0x01)                         */
27161 /* =======================================================  DPSIEGR1  ======================================================== */
27162  #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos           (0UL)          /*!< DIRQ8EG (Bit 0)                                       */
27163  #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk           (0x1UL)        /*!< DIRQ8EG (Bitfield-Mask: 0x01)                         */
27164  #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos           (1UL)          /*!< DIRQ9EG (Bit 1)                                       */
27165  #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk           (0x2UL)        /*!< DIRQ9EG (Bitfield-Mask: 0x01)                         */
27166  #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos          (2UL)          /*!< DIRQ10EG (Bit 2)                                      */
27167  #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk          (0x4UL)        /*!< DIRQ10EG (Bitfield-Mask: 0x01)                        */
27168  #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos          (3UL)          /*!< DIRQ11EG (Bit 3)                                      */
27169  #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk          (0x8UL)        /*!< DIRQ11EG (Bitfield-Mask: 0x01)                        */
27170  #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos          (4UL)          /*!< DIRQ12EG (Bit 4)                                      */
27171  #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk          (0x10UL)       /*!< DIRQ12EG (Bitfield-Mask: 0x01)                        */
27172  #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos          (5UL)          /*!< DIRQ13EG (Bit 5)                                      */
27173  #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk          (0x20UL)       /*!< DIRQ13EG (Bitfield-Mask: 0x01)                        */
27174  #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos          (6UL)          /*!< DIRQ14EG (Bit 6)                                      */
27175  #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk          (0x40UL)       /*!< DIRQ14EG (Bitfield-Mask: 0x01)                        */
27176  #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos          (7UL)          /*!< DIRQ15EG (Bit 7)                                      */
27177  #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk          (0x80UL)       /*!< DIRQ15EG (Bitfield-Mask: 0x01)                        */
27178 /* =======================================================  DPSIEGR2  ======================================================== */
27179  #define R_SYSTEM_DPSIEGR2_DPVD1EG_Pos           (0UL)          /*!< DPVD1EG (Bit 0)                                       */
27180  #define R_SYSTEM_DPSIEGR2_DPVD1EG_Msk           (0x1UL)        /*!< DPVD1EG (Bitfield-Mask: 0x01)                         */
27181  #define R_SYSTEM_DPSIEGR2_DPVD2EG_Pos           (1UL)          /*!< DPVD2EG (Bit 1)                                       */
27182  #define R_SYSTEM_DPSIEGR2_DPVD2EG_Msk           (0x2UL)        /*!< DPVD2EG (Bitfield-Mask: 0x01)                         */
27183  #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos            (4UL)          /*!< DNMIEG (Bit 4)                                        */
27184  #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk            (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
27185 /* ========================================================  SYOCDCR  ======================================================== */
27186  #define R_SYSTEM_SYOCDCR_DOCDF_Pos              (0UL)          /*!< DOCDF (Bit 0)                                         */
27187  #define R_SYSTEM_SYOCDCR_DOCDF_Msk              (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
27188  #define R_SYSTEM_SYOCDCR_DBGEN_Pos              (7UL)          /*!< DBGEN (Bit 7)                                         */
27189  #define R_SYSTEM_SYOCDCR_DBGEN_Msk              (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
27190 /* ========================================================  RSTSR0  ========================================================= */
27191  #define R_SYSTEM_RSTSR0_PORF_Pos                (0UL)          /*!< PORF (Bit 0)                                          */
27192  #define R_SYSTEM_RSTSR0_PORF_Msk                (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
27193  #define R_SYSTEM_RSTSR0_LVD0RF_Pos              (1UL)          /*!< LVD0RF (Bit 1)                                        */
27194  #define R_SYSTEM_RSTSR0_LVD0RF_Msk              (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
27195  #define R_SYSTEM_RSTSR0_LVD1RF_Pos              (2UL)          /*!< LVD1RF (Bit 2)                                        */
27196  #define R_SYSTEM_RSTSR0_LVD1RF_Msk              (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
27197  #define R_SYSTEM_RSTSR0_LVD2RF_Pos              (3UL)          /*!< LVD2RF (Bit 3)                                        */
27198  #define R_SYSTEM_RSTSR0_LVD2RF_Msk              (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
27199  #define R_SYSTEM_RSTSR0_LVD3RF_Pos              (4UL)          /*!< LVD3RF (Bit 4)                                        */
27200  #define R_SYSTEM_RSTSR0_LVD3RF_Msk              (0x10UL)       /*!< LVD3RF (Bitfield-Mask: 0x01)                          */
27201  #define R_SYSTEM_RSTSR0_LVD4RF_Pos              (5UL)          /*!< LVD4RF (Bit 5)                                        */
27202  #define R_SYSTEM_RSTSR0_LVD4RF_Msk              (0x20UL)       /*!< LVD4RF (Bitfield-Mask: 0x01)                          */
27203  #define R_SYSTEM_RSTSR0_LVD5RF_Pos              (6UL)          /*!< LVD5RF (Bit 6)                                        */
27204  #define R_SYSTEM_RSTSR0_LVD5RF_Msk              (0x40UL)       /*!< LVD5RF (Bitfield-Mask: 0x01)                          */
27205  #define R_SYSTEM_RSTSR0_DPSRSTF_Pos             (7UL)          /*!< DPSRSTF (Bit 7)                                       */
27206  #define R_SYSTEM_RSTSR0_DPSRSTF_Msk             (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
27207 /* ========================================================  RSTSR2  ========================================================= */
27208  #define R_SYSTEM_RSTSR2_CWSF_Pos                (0UL)          /*!< CWSF (Bit 0)                                          */
27209  #define R_SYSTEM_RSTSR2_CWSF_Msk                (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
27210 /* ========================================================  RSTSR3  ========================================================= */
27211  #define R_SYSTEM_RSTSR3_OCPRF_Pos               (4UL)          /*!< OCPRF (Bit 4)                                         */
27212  #define R_SYSTEM_RSTSR3_OCPRF_Msk               (0x10UL)       /*!< OCPRF (Bitfield-Mask: 0x01)                           */
27213 /* =========================================================  MOMCR  ========================================================= */
27214  #define R_SYSTEM_MOMCR_MODRV0_Pos               (1UL)          /*!< MODRV0 (Bit 1)                                        */
27215  #define R_SYSTEM_MOMCR_MODRV0_Msk               (0xeUL)        /*!< MODRV0 (Bitfield-Mask: 0x07)                          */
27216  #define R_SYSTEM_MOMCR_MOSEL_Pos                (6UL)          /*!< MOSEL (Bit 6)                                         */
27217  #define R_SYSTEM_MOMCR_MOSEL_Msk                (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
27218 /* ========================================================  FWEPROR  ======================================================== */
27219  #define R_SYSTEM_FWEPROR_FLWE_Pos               (0UL)          /*!< FLWE (Bit 0)                                          */
27220  #define R_SYSTEM_FWEPROR_FLWE_Msk               (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
27221 /* ========================================================  LVCMPCR  ======================================================== */
27222  #define R_SYSTEM_LVCMPCR_LVD2E_Pos              (6UL)          /*!< LVD2E (Bit 6)                                         */
27223  #define R_SYSTEM_LVCMPCR_LVD2E_Msk              (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
27224  #define R_SYSTEM_LVCMPCR_LVD1E_Pos              (5UL)          /*!< LVD1E (Bit 5)                                         */
27225  #define R_SYSTEM_LVCMPCR_LVD1E_Msk              (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
27226 /* =======================================================  LVD1CMPCR  ======================================================= */
27227  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos          (0UL)          /*!< LVD1LVL (Bit 0)                                       */
27228  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk          (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
27229  #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos            (7UL)          /*!< LVD1E (Bit 7)                                         */
27230  #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk            (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
27231 /* =======================================================  LVD2CMPCR  ======================================================= */
27232  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos          (0UL)          /*!< LVD2LVL (Bit 0)                                       */
27233  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk          (0x1fUL)       /*!< LVD2LVL (Bitfield-Mask: 0x1f)                         */
27234  #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos            (7UL)          /*!< LVD2E (Bit 7)                                         */
27235  #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk            (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
27236 /* ========================================================  LVD1CR0  ======================================================== */
27237  #define R_SYSTEM_LVD1CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
27238  #define R_SYSTEM_LVD1CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
27239  #define R_SYSTEM_LVD1CR0_DFDIS_Pos              (1UL)          /*!< DFDIS (Bit 1)                                         */
27240  #define R_SYSTEM_LVD1CR0_DFDIS_Msk              (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
27241  #define R_SYSTEM_LVD1CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
27242  #define R_SYSTEM_LVD1CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
27243  #define R_SYSTEM_LVD1CR0_FSAMP_Pos              (4UL)          /*!< FSAMP (Bit 4)                                         */
27244  #define R_SYSTEM_LVD1CR0_FSAMP_Msk              (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
27245  #define R_SYSTEM_LVD1CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
27246  #define R_SYSTEM_LVD1CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
27247  #define R_SYSTEM_LVD1CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
27248  #define R_SYSTEM_LVD1CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
27249 /* ========================================================  LVD2CR0  ======================================================== */
27250  #define R_SYSTEM_LVD2CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
27251  #define R_SYSTEM_LVD2CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
27252  #define R_SYSTEM_LVD2CR0_DFDIS_Pos              (1UL)          /*!< DFDIS (Bit 1)                                         */
27253  #define R_SYSTEM_LVD2CR0_DFDIS_Msk              (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
27254  #define R_SYSTEM_LVD2CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
27255  #define R_SYSTEM_LVD2CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
27256  #define R_SYSTEM_LVD2CR0_FSAMP_Pos              (4UL)          /*!< FSAMP (Bit 4)                                         */
27257  #define R_SYSTEM_LVD2CR0_FSAMP_Msk              (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
27258  #define R_SYSTEM_LVD2CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
27259  #define R_SYSTEM_LVD2CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
27260  #define R_SYSTEM_LVD2CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
27261  #define R_SYSTEM_LVD2CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
27262 /* ======================================================  VBATTMNSELR  ====================================================== */
27263  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos     (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
27264  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk     (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
27265 /* =======================================================  VBTBPCR1  ======================================================== */
27266  #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos          (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
27267  #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk          (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
27268 /* =========================================================  LPSCR  ========================================================= */
27269  #define R_SYSTEM_LPSCR_LPMD_Pos                 (0UL)          /*!< LPMD (Bit 0)                                          */
27270  #define R_SYSTEM_LPSCR_LPMD_Msk                 (0xfUL)        /*!< LPMD (Bitfield-Mask: 0x0f)                            */
27271 /* =========================================================  SSCR1  ========================================================= */
27272  #define R_SYSTEM_SSCR1_SS1FR_Pos                (0UL)          /*!< SS1FR (Bit 0)                                         */
27273  #define R_SYSTEM_SSCR1_SS1FR_Msk                (0x1UL)        /*!< SS1FR (Bitfield-Mask: 0x01)                           */
27274 /* =========================================================  LVOCR  ========================================================= */
27275  #define R_SYSTEM_LVOCR_LVO0E_Pos                (0UL)          /*!< LVO0E (Bit 0)                                         */
27276  #define R_SYSTEM_LVOCR_LVO0E_Msk                (0x1UL)        /*!< LVO0E (Bitfield-Mask: 0x01)                           */
27277  #define R_SYSTEM_LVOCR_LVO1E_Pos                (1UL)          /*!< LVO1E (Bit 1)                                         */
27278  #define R_SYSTEM_LVOCR_LVO1E_Msk                (0x2UL)        /*!< LVO1E (Bitfield-Mask: 0x01)                           */
27279 /* =======================================================  SYRSTMSK0  ======================================================= */
27280  #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos         (0UL)          /*!< IWDTMASK (Bit 0)                                      */
27281  #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk         (0x1UL)        /*!< IWDTMASK (Bitfield-Mask: 0x01)                        */
27282  #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos         (1UL)          /*!< WDT0MASK (Bit 1)                                      */
27283  #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk         (0x2UL)        /*!< WDT0MASK (Bitfield-Mask: 0x01)                        */
27284  #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos           (2UL)          /*!< SWMASK (Bit 2)                                        */
27285  #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk           (0x4UL)        /*!< SWMASK (Bitfield-Mask: 0x01)                          */
27286  #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Pos        (4UL)          /*!< CLUP0MASK (Bit 4)                                     */
27287  #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Msk        (0x10UL)       /*!< CLUP0MASK (Bitfield-Mask: 0x01)                       */
27288  #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos          (5UL)          /*!< LM0MASK (Bit 5)                                       */
27289  #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk          (0x20UL)       /*!< LM0MASK (Bitfield-Mask: 0x01)                         */
27290  #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos           (6UL)          /*!< CMMASK (Bit 6)                                        */
27291  #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk           (0x40UL)       /*!< CMMASK (Bitfield-Mask: 0x01)                          */
27292  #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos          (7UL)          /*!< BUSMASK (Bit 7)                                       */
27293  #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk          (0x80UL)       /*!< BUSMASK (Bitfield-Mask: 0x01)                         */
27294 /* =======================================================  SYRSTMSK1  ======================================================= */
27295  #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos         (1UL)          /*!< WDT1MASK (Bit 1)                                      */
27296  #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk         (0x2UL)        /*!< WDT1MASK (Bitfield-Mask: 0x01)                        */
27297  #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos        (4UL)          /*!< CLUP1MASK (Bit 4)                                     */
27298  #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk        (0x10UL)       /*!< CLUP1MASK (Bitfield-Mask: 0x01)                       */
27299  #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos          (5UL)          /*!< LM1MASK (Bit 5)                                       */
27300  #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk          (0x20UL)       /*!< LM1MASK (Bitfield-Mask: 0x01)                         */
27301  #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos           (7UL)          /*!< NWMASK (Bit 7)                                        */
27302  #define R_SYSTEM_SYRSTMSK1_NWMASK_Msk           (0x80UL)       /*!< NWMASK (Bitfield-Mask: 0x01)                          */
27303 /* =======================================================  SYRSTMSK2  ======================================================= */
27304  #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Pos         (0UL)          /*!< LVD1MASK (Bit 0)                                      */
27305  #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Msk         (0x1UL)        /*!< LVD1MASK (Bitfield-Mask: 0x01)                        */
27306  #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Pos         (1UL)          /*!< LVD2MASK (Bit 1)                                      */
27307  #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Msk         (0x2UL)        /*!< LVD2MASK (Bitfield-Mask: 0x01)                        */
27308  #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Pos         (2UL)          /*!< LVD3MASK (Bit 2)                                      */
27309  #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Msk         (0x4UL)        /*!< LVD3MASK (Bitfield-Mask: 0x01)                        */
27310  #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Pos         (3UL)          /*!< LVD4MASK (Bit 3)                                      */
27311  #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Msk         (0x8UL)        /*!< LVD4MASK (Bitfield-Mask: 0x01)                        */
27312  #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Pos         (4UL)          /*!< LVD5MASK (Bit 4)                                      */
27313  #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Msk         (0x10UL)       /*!< LVD5MASK (Bitfield-Mask: 0x01)                        */
27314 /* =======================================================  PLL1LDOCR  ======================================================= */
27315  #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos           (0UL)          /*!< LDOSTP (Bit 0)                                        */
27316  #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk           (0x1UL)        /*!< LDOSTP (Bitfield-Mask: 0x01)                          */
27317  #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos            (1UL)          /*!< SKEEP (Bit 1)                                         */
27318  #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk            (0x2UL)        /*!< SKEEP (Bitfield-Mask: 0x01)                           */
27319 /* =======================================================  PLL2LDOCR  ======================================================= */
27320  #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos           (0UL)          /*!< LDOSTP (Bit 0)                                        */
27321  #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk           (0x1UL)        /*!< LDOSTP (Bitfield-Mask: 0x01)                          */
27322  #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos            (1UL)          /*!< SKEEP (Bit 1)                                         */
27323  #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk            (0x2UL)        /*!< SKEEP (Bitfield-Mask: 0x01)                           */
27324 /* =======================================================  HOCOLDOCR  ======================================================= */
27325  #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos           (0UL)          /*!< LDOSTP (Bit 0)                                        */
27326  #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk           (0x1UL)        /*!< LDOSTP (Bitfield-Mask: 0x01)                          */
27327  #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos            (1UL)          /*!< SKEEP (Bit 1)                                         */
27328  #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk            (0x2UL)        /*!< SKEEP (Bitfield-Mask: 0x01)                           */
27329 /* ========================================================  LVD1FCR  ======================================================== */
27330  #define R_SYSTEM_LVD1FCR_RHSEL_Pos              (0UL)          /*!< RHSEL (Bit 0)                                         */
27331  #define R_SYSTEM_LVD1FCR_RHSEL_Msk              (0x1UL)        /*!< RHSEL (Bitfield-Mask: 0x01)                           */
27332 /* ========================================================  LVD2FCR  ======================================================== */
27333  #define R_SYSTEM_LVD2FCR_RHSEL_Pos              (0UL)          /*!< RHSEL (Bit 0)                                         */
27334  #define R_SYSTEM_LVD2FCR_RHSEL_Msk              (0x1UL)        /*!< RHSEL (Bitfield-Mask: 0x01)                           */
27335 /* ========================================================  SOSCCR  ========================================================= */
27336  #define R_SYSTEM_SOSCCR_SOSTP_Pos               (0UL)          /*!< SOSTP (Bit 0)                                         */
27337  #define R_SYSTEM_SOSCCR_SOSTP_Msk               (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
27338 /* =========================================================  SOMCR  ========================================================= */
27339  #define R_SYSTEM_SOMCR_SODRV_Pos                (0UL)          /*!< SODRV (Bit 0)                                         */
27340  #define R_SYSTEM_SOMCR_SODRV_Msk                (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
27341  #define R_SYSTEM_SOMCR_SOSEL_Pos                (6UL)          /*!< SOSEL (Bit 6)                                         */
27342  #define R_SYSTEM_SOMCR_SOSEL_Msk                (0x40UL)       /*!< SOSEL (Bitfield-Mask: 0x01)                           */
27343 /* ========================================================  VBTBER  ========================================================= */
27344  #define R_SYSTEM_VBTBER_VBAE_Pos                (3UL)          /*!< VBAE (Bit 3)                                          */
27345  #define R_SYSTEM_VBTBER_VBAE_Msk                (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
27346 /* =======================================================  VBTBPCR2  ======================================================== */
27347  #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos           (0UL)          /*!< VDETLVL (Bit 0)                                       */
27348  #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk           (0x7UL)        /*!< VDETLVL (Bitfield-Mask: 0x07)                         */
27349  #define R_SYSTEM_VBTBPCR2_VDETE_Pos             (4UL)          /*!< VDETE (Bit 4)                                         */
27350  #define R_SYSTEM_VBTBPCR2_VDETE_Msk             (0x10UL)       /*!< VDETE (Bitfield-Mask: 0x01)                           */
27351 /* ========================================================  VBTBPSR  ======================================================== */
27352  #define R_SYSTEM_VBTBPSR_VBPORF_Pos             (0UL)          /*!< VBPORF (Bit 0)                                        */
27353  #define R_SYSTEM_VBTBPSR_VBPORF_Msk             (0x1UL)        /*!< VBPORF (Bitfield-Mask: 0x01)                          */
27354  #define R_SYSTEM_VBTBPSR_VBPORM_Pos             (4UL)          /*!< VBPORM (Bit 4)                                        */
27355  #define R_SYSTEM_VBTBPSR_VBPORM_Msk             (0x10UL)       /*!< VBPORM (Bitfield-Mask: 0x01)                          */
27356  #define R_SYSTEM_VBTBPSR_BPWSWM_Pos             (5UL)          /*!< BPWSWM (Bit 5)                                        */
27357  #define R_SYSTEM_VBTBPSR_BPWSWM_Msk             (0x20UL)       /*!< BPWSWM (Bitfield-Mask: 0x01)                          */
27358 /* ========================================================  VBTADSR  ======================================================== */
27359  #define R_SYSTEM_VBTADSR_VBTADF0_Pos            (0UL)          /*!< VBTADF0 (Bit 0)                                       */
27360  #define R_SYSTEM_VBTADSR_VBTADF0_Msk            (0x1UL)        /*!< VBTADF0 (Bitfield-Mask: 0x01)                         */
27361  #define R_SYSTEM_VBTADSR_VBTADF1_Pos            (1UL)          /*!< VBTADF1 (Bit 1)                                       */
27362  #define R_SYSTEM_VBTADSR_VBTADF1_Msk            (0x2UL)        /*!< VBTADF1 (Bitfield-Mask: 0x01)                         */
27363  #define R_SYSTEM_VBTADSR_VBTADF2_Pos            (2UL)          /*!< VBTADF2 (Bit 2)                                       */
27364  #define R_SYSTEM_VBTADSR_VBTADF2_Msk            (0x4UL)        /*!< VBTADF2 (Bitfield-Mask: 0x01)                         */
27365 /* =======================================================  VBTADCR1  ======================================================== */
27366  #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos          (0UL)          /*!< VBTADIE0 (Bit 0)                                      */
27367  #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk          (0x1UL)        /*!< VBTADIE0 (Bitfield-Mask: 0x01)                        */
27368  #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos          (1UL)          /*!< VBTADIE1 (Bit 1)                                      */
27369  #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk          (0x2UL)        /*!< VBTADIE1 (Bitfield-Mask: 0x01)                        */
27370  #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos          (2UL)          /*!< VBTADIE2 (Bit 2)                                      */
27371  #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk          (0x4UL)        /*!< VBTADIE2 (Bitfield-Mask: 0x01)                        */
27372  #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos         (4UL)          /*!< VBTADCLE0 (Bit 4)                                     */
27373  #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk         (0x10UL)       /*!< VBTADCLE0 (Bitfield-Mask: 0x01)                       */
27374  #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos         (5UL)          /*!< VBTADCLE1 (Bit 5)                                     */
27375  #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk         (0x20UL)       /*!< VBTADCLE1 (Bitfield-Mask: 0x01)                       */
27376  #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos         (6UL)          /*!< VBTADCLE2 (Bit 6)                                     */
27377  #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk         (0x40UL)       /*!< VBTADCLE2 (Bitfield-Mask: 0x01)                       */
27378 /* =======================================================  VBTADCR2  ======================================================== */
27379  #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos          (0UL)          /*!< VBRTCES0 (Bit 0)                                      */
27380  #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk          (0x1UL)        /*!< VBRTCES0 (Bitfield-Mask: 0x01)                        */
27381  #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos          (1UL)          /*!< VBRTCES1 (Bit 1)                                      */
27382  #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk          (0x2UL)        /*!< VBRTCES1 (Bitfield-Mask: 0x01)                        */
27383  #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos          (2UL)          /*!< VBRTCES2 (Bit 2)                                      */
27384  #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk          (0x4UL)        /*!< VBRTCES2 (Bitfield-Mask: 0x01)                        */
27385 /* =======================================================  VBTICTLR  ======================================================== */
27386  #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos          (0UL)          /*!< VCH0INEN (Bit 0)                                      */
27387  #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk          (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
27388  #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos          (1UL)          /*!< VCH1INEN (Bit 1)                                      */
27389  #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk          (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
27390  #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos          (2UL)          /*!< VCH2INEN (Bit 2)                                      */
27391  #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk          (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
27392 /* =======================================================  VBTICTLR2  ======================================================= */
27393  #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos          (0UL)          /*!< VCH0NCE (Bit 0)                                       */
27394  #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk          (0x1UL)        /*!< VCH0NCE (Bitfield-Mask: 0x01)                         */
27395  #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos          (1UL)          /*!< VCH1NCE (Bit 1)                                       */
27396  #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk          (0x2UL)        /*!< VCH1NCE (Bitfield-Mask: 0x01)                         */
27397  #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos          (2UL)          /*!< VCH2NCE (Bit 2)                                       */
27398  #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk          (0x4UL)        /*!< VCH2NCE (Bitfield-Mask: 0x01)                         */
27399  #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos           (4UL)          /*!< VCH0EG (Bit 4)                                        */
27400  #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk           (0x10UL)       /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
27401  #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos           (5UL)          /*!< VCH1EG (Bit 5)                                        */
27402  #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk           (0x20UL)       /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
27403  #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos           (6UL)          /*!< VCH2EG (Bit 6)                                        */
27404  #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk           (0x40UL)       /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
27405 /* =======================================================  VBTIMONR  ======================================================== */
27406  #define R_SYSTEM_VBTIMONR_VCH0MON_Pos           (0UL)          /*!< VCH0MON (Bit 0)                                       */
27407  #define R_SYSTEM_VBTIMONR_VCH0MON_Msk           (0x1UL)        /*!< VCH0MON (Bitfield-Mask: 0x01)                         */
27408  #define R_SYSTEM_VBTIMONR_VCH1MON_Pos           (1UL)          /*!< VCH1MON (Bit 1)                                       */
27409  #define R_SYSTEM_VBTIMONR_VCH1MON_Msk           (0x2UL)        /*!< VCH1MON (Bitfield-Mask: 0x01)                         */
27410  #define R_SYSTEM_VBTIMONR_VCH2MON_Pos           (2UL)          /*!< VCH2MON (Bit 2)                                       */
27411  #define R_SYSTEM_VBTIMONR_VCH2MON_Msk           (0x4UL)        /*!< VCH2MON (Bitfield-Mask: 0x01)                         */
27412 /* ========================================================  VBTBKR0  ======================================================== */
27413  #define R_SYSTEM_VBTBKR0_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27414  #define R_SYSTEM_VBTBKR0_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27415 /* ========================================================  VBTBKR1  ======================================================== */
27416  #define R_SYSTEM_VBTBKR1_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27417  #define R_SYSTEM_VBTBKR1_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27418 /* ========================================================  VBTBKR2  ======================================================== */
27419  #define R_SYSTEM_VBTBKR2_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27420  #define R_SYSTEM_VBTBKR2_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27421 /* ========================================================  VBTBKR3  ======================================================== */
27422  #define R_SYSTEM_VBTBKR3_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27423  #define R_SYSTEM_VBTBKR3_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27424 /* ========================================================  VBTBKR4  ======================================================== */
27425  #define R_SYSTEM_VBTBKR4_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27426  #define R_SYSTEM_VBTBKR4_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27427 /* ========================================================  VBTBKR5  ======================================================== */
27428  #define R_SYSTEM_VBTBKR5_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27429  #define R_SYSTEM_VBTBKR5_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27430 /* ========================================================  VBTBKR6  ======================================================== */
27431  #define R_SYSTEM_VBTBKR6_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27432  #define R_SYSTEM_VBTBKR6_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27433 /* ========================================================  VBTBKR7  ======================================================== */
27434  #define R_SYSTEM_VBTBKR7_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27435  #define R_SYSTEM_VBTBKR7_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27436 /* ========================================================  VBTBKR8  ======================================================== */
27437  #define R_SYSTEM_VBTBKR8_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27438  #define R_SYSTEM_VBTBKR8_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27439 /* ========================================================  VBTBKR9  ======================================================== */
27440  #define R_SYSTEM_VBTBKR9_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
27441  #define R_SYSTEM_VBTBKR9_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27442 /* =======================================================  VBTBKR10  ======================================================== */
27443  #define R_SYSTEM_VBTBKR10_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27444  #define R_SYSTEM_VBTBKR10_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27445 /* =======================================================  VBTBKR11  ======================================================== */
27446  #define R_SYSTEM_VBTBKR11_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27447  #define R_SYSTEM_VBTBKR11_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27448 /* =======================================================  VBTBKR12  ======================================================== */
27449  #define R_SYSTEM_VBTBKR12_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27450  #define R_SYSTEM_VBTBKR12_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27451 /* =======================================================  VBTBKR13  ======================================================== */
27452  #define R_SYSTEM_VBTBKR13_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27453  #define R_SYSTEM_VBTBKR13_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27454 /* =======================================================  VBTBKR14  ======================================================== */
27455  #define R_SYSTEM_VBTBKR14_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27456  #define R_SYSTEM_VBTBKR14_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27457 /* =======================================================  VBTBKR15  ======================================================== */
27458  #define R_SYSTEM_VBTBKR15_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27459  #define R_SYSTEM_VBTBKR15_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27460 /* =======================================================  VBTBKR16  ======================================================== */
27461  #define R_SYSTEM_VBTBKR16_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27462  #define R_SYSTEM_VBTBKR16_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27463 /* =======================================================  VBTBKR17  ======================================================== */
27464  #define R_SYSTEM_VBTBKR17_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27465  #define R_SYSTEM_VBTBKR17_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27466 /* =======================================================  VBTBKR18  ======================================================== */
27467  #define R_SYSTEM_VBTBKR18_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27468  #define R_SYSTEM_VBTBKR18_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27469 /* =======================================================  VBTBKR19  ======================================================== */
27470  #define R_SYSTEM_VBTBKR19_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27471  #define R_SYSTEM_VBTBKR19_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27472 /* =======================================================  VBTBKR20  ======================================================== */
27473  #define R_SYSTEM_VBTBKR20_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27474  #define R_SYSTEM_VBTBKR20_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27475 /* =======================================================  VBTBKR21  ======================================================== */
27476  #define R_SYSTEM_VBTBKR21_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27477  #define R_SYSTEM_VBTBKR21_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27478 /* =======================================================  VBTBKR22  ======================================================== */
27479  #define R_SYSTEM_VBTBKR22_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27480  #define R_SYSTEM_VBTBKR22_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27481 /* =======================================================  VBTBKR23  ======================================================== */
27482  #define R_SYSTEM_VBTBKR23_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27483  #define R_SYSTEM_VBTBKR23_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27484 /* =======================================================  VBTBKR24  ======================================================== */
27485  #define R_SYSTEM_VBTBKR24_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27486  #define R_SYSTEM_VBTBKR24_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27487 /* =======================================================  VBTBKR25  ======================================================== */
27488  #define R_SYSTEM_VBTBKR25_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27489  #define R_SYSTEM_VBTBKR25_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27490 /* =======================================================  VBTBKR26  ======================================================== */
27491  #define R_SYSTEM_VBTBKR26_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27492  #define R_SYSTEM_VBTBKR26_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27493 /* =======================================================  VBTBKR27  ======================================================== */
27494  #define R_SYSTEM_VBTBKR27_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27495  #define R_SYSTEM_VBTBKR27_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27496 /* =======================================================  VBTBKR28  ======================================================== */
27497  #define R_SYSTEM_VBTBKR28_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27498  #define R_SYSTEM_VBTBKR28_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27499 /* =======================================================  VBTBKR29  ======================================================== */
27500  #define R_SYSTEM_VBTBKR29_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27501  #define R_SYSTEM_VBTBKR29_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27502 /* =======================================================  VBTBKR30  ======================================================== */
27503  #define R_SYSTEM_VBTBKR30_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27504  #define R_SYSTEM_VBTBKR30_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27505 /* =======================================================  VBTBKR31  ======================================================== */
27506  #define R_SYSTEM_VBTBKR31_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27507  #define R_SYSTEM_VBTBKR31_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27508 /* =======================================================  VBTBKR32  ======================================================== */
27509  #define R_SYSTEM_VBTBKR32_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27510  #define R_SYSTEM_VBTBKR32_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27511 /* =======================================================  VBTBKR33  ======================================================== */
27512  #define R_SYSTEM_VBTBKR33_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27513  #define R_SYSTEM_VBTBKR33_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27514 /* =======================================================  VBTBKR34  ======================================================== */
27515  #define R_SYSTEM_VBTBKR34_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27516  #define R_SYSTEM_VBTBKR34_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27517 /* =======================================================  VBTBKR35  ======================================================== */
27518  #define R_SYSTEM_VBTBKR35_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27519  #define R_SYSTEM_VBTBKR35_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27520 /* =======================================================  VBTBKR36  ======================================================== */
27521  #define R_SYSTEM_VBTBKR36_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27522  #define R_SYSTEM_VBTBKR36_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27523 /* =======================================================  VBTBKR37  ======================================================== */
27524  #define R_SYSTEM_VBTBKR37_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27525  #define R_SYSTEM_VBTBKR37_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27526 /* =======================================================  VBTBKR38  ======================================================== */
27527  #define R_SYSTEM_VBTBKR38_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27528  #define R_SYSTEM_VBTBKR38_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27529 /* =======================================================  VBTBKR39  ======================================================== */
27530  #define R_SYSTEM_VBTBKR39_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27531  #define R_SYSTEM_VBTBKR39_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27532 /* =======================================================  VBTBKR40  ======================================================== */
27533  #define R_SYSTEM_VBTBKR40_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27534  #define R_SYSTEM_VBTBKR40_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27535 /* =======================================================  VBTBKR41  ======================================================== */
27536  #define R_SYSTEM_VBTBKR41_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27537  #define R_SYSTEM_VBTBKR41_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27538 /* =======================================================  VBTBKR42  ======================================================== */
27539  #define R_SYSTEM_VBTBKR42_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27540  #define R_SYSTEM_VBTBKR42_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27541 /* =======================================================  VBTBKR43  ======================================================== */
27542  #define R_SYSTEM_VBTBKR43_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27543  #define R_SYSTEM_VBTBKR43_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27544 /* =======================================================  VBTBKR44  ======================================================== */
27545  #define R_SYSTEM_VBTBKR44_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27546  #define R_SYSTEM_VBTBKR44_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27547 /* =======================================================  VBTBKR45  ======================================================== */
27548  #define R_SYSTEM_VBTBKR45_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27549  #define R_SYSTEM_VBTBKR45_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27550 /* =======================================================  VBTBKR46  ======================================================== */
27551  #define R_SYSTEM_VBTBKR46_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27552  #define R_SYSTEM_VBTBKR46_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27553 /* =======================================================  VBTBKR47  ======================================================== */
27554  #define R_SYSTEM_VBTBKR47_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27555  #define R_SYSTEM_VBTBKR47_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27556 /* =======================================================  VBTBKR48  ======================================================== */
27557  #define R_SYSTEM_VBTBKR48_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27558  #define R_SYSTEM_VBTBKR48_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27559 /* =======================================================  VBTBKR49  ======================================================== */
27560  #define R_SYSTEM_VBTBKR49_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27561  #define R_SYSTEM_VBTBKR49_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27562 /* =======================================================  VBTBKR50  ======================================================== */
27563  #define R_SYSTEM_VBTBKR50_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27564  #define R_SYSTEM_VBTBKR50_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27565 /* =======================================================  VBTBKR51  ======================================================== */
27566  #define R_SYSTEM_VBTBKR51_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27567  #define R_SYSTEM_VBTBKR51_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27568 /* =======================================================  VBTBKR52  ======================================================== */
27569  #define R_SYSTEM_VBTBKR52_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27570  #define R_SYSTEM_VBTBKR52_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27571 /* =======================================================  VBTBKR53  ======================================================== */
27572  #define R_SYSTEM_VBTBKR53_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27573  #define R_SYSTEM_VBTBKR53_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27574 /* =======================================================  VBTBKR54  ======================================================== */
27575  #define R_SYSTEM_VBTBKR54_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27576  #define R_SYSTEM_VBTBKR54_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27577 /* =======================================================  VBTBKR55  ======================================================== */
27578  #define R_SYSTEM_VBTBKR55_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27579  #define R_SYSTEM_VBTBKR55_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27580 /* =======================================================  VBTBKR56  ======================================================== */
27581  #define R_SYSTEM_VBTBKR56_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27582  #define R_SYSTEM_VBTBKR56_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27583 /* =======================================================  VBTBKR57  ======================================================== */
27584  #define R_SYSTEM_VBTBKR57_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27585  #define R_SYSTEM_VBTBKR57_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27586 /* =======================================================  VBTBKR58  ======================================================== */
27587  #define R_SYSTEM_VBTBKR58_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27588  #define R_SYSTEM_VBTBKR58_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27589 /* =======================================================  VBTBKR59  ======================================================== */
27590  #define R_SYSTEM_VBTBKR59_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27591  #define R_SYSTEM_VBTBKR59_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27592 /* =======================================================  VBTBKR60  ======================================================== */
27593  #define R_SYSTEM_VBTBKR60_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27594  #define R_SYSTEM_VBTBKR60_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27595 /* =======================================================  VBTBKR61  ======================================================== */
27596  #define R_SYSTEM_VBTBKR61_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27597  #define R_SYSTEM_VBTBKR61_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27598 /* =======================================================  VBTBKR62  ======================================================== */
27599  #define R_SYSTEM_VBTBKR62_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27600  #define R_SYSTEM_VBTBKR62_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27601 /* =======================================================  VBTBKR63  ======================================================== */
27602  #define R_SYSTEM_VBTBKR63_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27603  #define R_SYSTEM_VBTBKR63_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27604 /* =======================================================  VBTBKR64  ======================================================== */
27605  #define R_SYSTEM_VBTBKR64_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27606  #define R_SYSTEM_VBTBKR64_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27607 /* =======================================================  VBTBKR65  ======================================================== */
27608  #define R_SYSTEM_VBTBKR65_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27609  #define R_SYSTEM_VBTBKR65_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27610 /* =======================================================  VBTBKR66  ======================================================== */
27611  #define R_SYSTEM_VBTBKR66_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27612  #define R_SYSTEM_VBTBKR66_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27613 /* =======================================================  VBTBKR67  ======================================================== */
27614  #define R_SYSTEM_VBTBKR67_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27615  #define R_SYSTEM_VBTBKR67_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27616 /* =======================================================  VBTBKR68  ======================================================== */
27617  #define R_SYSTEM_VBTBKR68_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27618  #define R_SYSTEM_VBTBKR68_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27619 /* =======================================================  VBTBKR69  ======================================================== */
27620  #define R_SYSTEM_VBTBKR69_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27621  #define R_SYSTEM_VBTBKR69_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27622 /* =======================================================  VBTBKR70  ======================================================== */
27623  #define R_SYSTEM_VBTBKR70_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27624  #define R_SYSTEM_VBTBKR70_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27625 /* =======================================================  VBTBKR71  ======================================================== */
27626  #define R_SYSTEM_VBTBKR71_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27627  #define R_SYSTEM_VBTBKR71_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27628 /* =======================================================  VBTBKR72  ======================================================== */
27629  #define R_SYSTEM_VBTBKR72_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27630  #define R_SYSTEM_VBTBKR72_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27631 /* =======================================================  VBTBKR73  ======================================================== */
27632  #define R_SYSTEM_VBTBKR73_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27633  #define R_SYSTEM_VBTBKR73_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27634 /* =======================================================  VBTBKR74  ======================================================== */
27635  #define R_SYSTEM_VBTBKR74_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27636  #define R_SYSTEM_VBTBKR74_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27637 /* =======================================================  VBTBKR75  ======================================================== */
27638  #define R_SYSTEM_VBTBKR75_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27639  #define R_SYSTEM_VBTBKR75_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27640 /* =======================================================  VBTBKR76  ======================================================== */
27641  #define R_SYSTEM_VBTBKR76_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27642  #define R_SYSTEM_VBTBKR76_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27643 /* =======================================================  VBTBKR77  ======================================================== */
27644  #define R_SYSTEM_VBTBKR77_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27645  #define R_SYSTEM_VBTBKR77_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27646 /* =======================================================  VBTBKR78  ======================================================== */
27647  #define R_SYSTEM_VBTBKR78_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27648  #define R_SYSTEM_VBTBKR78_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27649 /* =======================================================  VBTBKR79  ======================================================== */
27650  #define R_SYSTEM_VBTBKR79_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27651  #define R_SYSTEM_VBTBKR79_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27652 /* =======================================================  VBTBKR80  ======================================================== */
27653  #define R_SYSTEM_VBTBKR80_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27654  #define R_SYSTEM_VBTBKR80_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27655 /* =======================================================  VBTBKR81  ======================================================== */
27656  #define R_SYSTEM_VBTBKR81_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27657  #define R_SYSTEM_VBTBKR81_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27658 /* =======================================================  VBTBKR82  ======================================================== */
27659  #define R_SYSTEM_VBTBKR82_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27660  #define R_SYSTEM_VBTBKR82_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27661 /* =======================================================  VBTBKR83  ======================================================== */
27662  #define R_SYSTEM_VBTBKR83_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27663  #define R_SYSTEM_VBTBKR83_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27664 /* =======================================================  VBTBKR84  ======================================================== */
27665  #define R_SYSTEM_VBTBKR84_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27666  #define R_SYSTEM_VBTBKR84_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27667 /* =======================================================  VBTBKR85  ======================================================== */
27668  #define R_SYSTEM_VBTBKR85_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27669  #define R_SYSTEM_VBTBKR85_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27670 /* =======================================================  VBTBKR86  ======================================================== */
27671  #define R_SYSTEM_VBTBKR86_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27672  #define R_SYSTEM_VBTBKR86_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27673 /* =======================================================  VBTBKR87  ======================================================== */
27674  #define R_SYSTEM_VBTBKR87_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27675  #define R_SYSTEM_VBTBKR87_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27676 /* =======================================================  VBTBKR88  ======================================================== */
27677  #define R_SYSTEM_VBTBKR88_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27678  #define R_SYSTEM_VBTBKR88_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27679 /* =======================================================  VBTBKR89  ======================================================== */
27680  #define R_SYSTEM_VBTBKR89_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27681  #define R_SYSTEM_VBTBKR89_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27682 /* =======================================================  VBTBKR90  ======================================================== */
27683  #define R_SYSTEM_VBTBKR90_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27684  #define R_SYSTEM_VBTBKR90_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27685 /* =======================================================  VBTBKR91  ======================================================== */
27686  #define R_SYSTEM_VBTBKR91_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27687  #define R_SYSTEM_VBTBKR91_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27688 /* =======================================================  VBTBKR92  ======================================================== */
27689  #define R_SYSTEM_VBTBKR92_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27690  #define R_SYSTEM_VBTBKR92_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27691 /* =======================================================  VBTBKR93  ======================================================== */
27692  #define R_SYSTEM_VBTBKR93_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27693  #define R_SYSTEM_VBTBKR93_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27694 /* =======================================================  VBTBKR94  ======================================================== */
27695  #define R_SYSTEM_VBTBKR94_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27696  #define R_SYSTEM_VBTBKR94_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27697 /* =======================================================  VBTBKR95  ======================================================== */
27698  #define R_SYSTEM_VBTBKR95_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27699  #define R_SYSTEM_VBTBKR95_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27700 /* =======================================================  VBTBKR96  ======================================================== */
27701  #define R_SYSTEM_VBTBKR96_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27702  #define R_SYSTEM_VBTBKR96_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27703 /* =======================================================  VBTBKR97  ======================================================== */
27704  #define R_SYSTEM_VBTBKR97_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27705  #define R_SYSTEM_VBTBKR97_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27706 /* =======================================================  VBTBKR98  ======================================================== */
27707  #define R_SYSTEM_VBTBKR98_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27708  #define R_SYSTEM_VBTBKR98_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27709 /* =======================================================  VBTBKR99  ======================================================== */
27710  #define R_SYSTEM_VBTBKR99_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
27711  #define R_SYSTEM_VBTBKR99_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27712 /* =======================================================  VBTBKR100  ======================================================= */
27713  #define R_SYSTEM_VBTBKR100_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27714  #define R_SYSTEM_VBTBKR100_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27715 /* =======================================================  VBTBKR101  ======================================================= */
27716  #define R_SYSTEM_VBTBKR101_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27717  #define R_SYSTEM_VBTBKR101_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27718 /* =======================================================  VBTBKR102  ======================================================= */
27719  #define R_SYSTEM_VBTBKR102_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27720  #define R_SYSTEM_VBTBKR102_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27721 /* =======================================================  VBTBKR103  ======================================================= */
27722  #define R_SYSTEM_VBTBKR103_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27723  #define R_SYSTEM_VBTBKR103_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27724 /* =======================================================  VBTBKR104  ======================================================= */
27725  #define R_SYSTEM_VBTBKR104_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27726  #define R_SYSTEM_VBTBKR104_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27727 /* =======================================================  VBTBKR105  ======================================================= */
27728  #define R_SYSTEM_VBTBKR105_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27729  #define R_SYSTEM_VBTBKR105_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27730 /* =======================================================  VBTBKR106  ======================================================= */
27731  #define R_SYSTEM_VBTBKR106_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27732  #define R_SYSTEM_VBTBKR106_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27733 /* =======================================================  VBTBKR107  ======================================================= */
27734  #define R_SYSTEM_VBTBKR107_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27735  #define R_SYSTEM_VBTBKR107_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27736 /* =======================================================  VBTBKR108  ======================================================= */
27737  #define R_SYSTEM_VBTBKR108_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27738  #define R_SYSTEM_VBTBKR108_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27739 /* =======================================================  VBTBKR109  ======================================================= */
27740  #define R_SYSTEM_VBTBKR109_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27741  #define R_SYSTEM_VBTBKR109_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27742 /* =======================================================  VBTBKR110  ======================================================= */
27743  #define R_SYSTEM_VBTBKR110_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27744  #define R_SYSTEM_VBTBKR110_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27745 /* =======================================================  VBTBKR111  ======================================================= */
27746  #define R_SYSTEM_VBTBKR111_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27747  #define R_SYSTEM_VBTBKR111_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27748 /* =======================================================  VBTBKR112  ======================================================= */
27749  #define R_SYSTEM_VBTBKR112_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27750  #define R_SYSTEM_VBTBKR112_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27751 /* =======================================================  VBTBKR113  ======================================================= */
27752  #define R_SYSTEM_VBTBKR113_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27753  #define R_SYSTEM_VBTBKR113_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27754 /* =======================================================  VBTBKR114  ======================================================= */
27755  #define R_SYSTEM_VBTBKR114_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27756  #define R_SYSTEM_VBTBKR114_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27757 /* =======================================================  VBTBKR115  ======================================================= */
27758  #define R_SYSTEM_VBTBKR115_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27759  #define R_SYSTEM_VBTBKR115_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27760 /* =======================================================  VBTBKR116  ======================================================= */
27761  #define R_SYSTEM_VBTBKR116_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27762  #define R_SYSTEM_VBTBKR116_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27763 /* =======================================================  VBTBKR117  ======================================================= */
27764  #define R_SYSTEM_VBTBKR117_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27765  #define R_SYSTEM_VBTBKR117_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27766 /* =======================================================  VBTBKR118  ======================================================= */
27767  #define R_SYSTEM_VBTBKR118_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27768  #define R_SYSTEM_VBTBKR118_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27769 /* =======================================================  VBTBKR119  ======================================================= */
27770  #define R_SYSTEM_VBTBKR119_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27771  #define R_SYSTEM_VBTBKR119_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27772 /* =======================================================  VBTBKR120  ======================================================= */
27773  #define R_SYSTEM_VBTBKR120_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27774  #define R_SYSTEM_VBTBKR120_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27775 /* =======================================================  VBTBKR121  ======================================================= */
27776  #define R_SYSTEM_VBTBKR121_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27777  #define R_SYSTEM_VBTBKR121_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27778 /* =======================================================  VBTBKR122  ======================================================= */
27779  #define R_SYSTEM_VBTBKR122_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27780  #define R_SYSTEM_VBTBKR122_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27781 /* =======================================================  VBTBKR123  ======================================================= */
27782  #define R_SYSTEM_VBTBKR123_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27783  #define R_SYSTEM_VBTBKR123_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27784 /* =======================================================  VBTBKR124  ======================================================= */
27785  #define R_SYSTEM_VBTBKR124_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27786  #define R_SYSTEM_VBTBKR124_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27787 /* =======================================================  VBTBKR125  ======================================================= */
27788  #define R_SYSTEM_VBTBKR125_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27789  #define R_SYSTEM_VBTBKR125_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27790 /* =======================================================  VBTBKR126  ======================================================= */
27791  #define R_SYSTEM_VBTBKR126_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27792  #define R_SYSTEM_VBTBKR126_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27793 /* =======================================================  VBTBKR127  ======================================================= */
27794  #define R_SYSTEM_VBTBKR127_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
27795  #define R_SYSTEM_VBTBKR127_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
27796 
27797 /* =========================================================================================================================== */
27798 /* ================                                         R_TSN_CAL                                         ================ */
27799 /* =========================================================================================================================== */
27800 
27801 /* =========================================================  TSCDR  ========================================================= */
27802  #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
27803  #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
27804 
27805 /* =========================================================================================================================== */
27806 /* ================                                        R_TSN_CTRL                                         ================ */
27807 /* =========================================================================================================================== */
27808 
27809 /* =========================================================  TSCR  ========================================================== */
27810  #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
27811  #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
27812  #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
27813  #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
27814 
27815 /* =========================================================================================================================== */
27816 /* ================                                         R_USB_FS0                                         ================ */
27817 /* =========================================================================================================================== */
27818 
27819 /* ========================================================  SYSCFG  ========================================================= */
27820  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
27821  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
27822  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
27823  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
27824  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
27825  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
27826  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
27827  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
27828  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
27829  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
27830  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
27831  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
27832  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
27833  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
27834 /* ========================================================  BUSWAIT  ======================================================== */
27835  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
27836  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
27837 /* ========================================================  SYSSTS0  ======================================================== */
27838  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
27839  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
27840  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
27841  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
27842  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
27843  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
27844  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
27845  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
27846  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
27847  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
27848 /* ========================================================  PLLSTA  ========================================================= */
27849  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
27850  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
27851 /* =======================================================  DVSTCTR0  ======================================================== */
27852  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
27853  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
27854  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
27855  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
27856  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
27857  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
27858  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
27859  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
27860  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
27861  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
27862  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
27863  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
27864  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
27865  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
27866  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
27867  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
27868  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
27869  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
27870 /* =======================================================  TESTMODE  ======================================================== */
27871  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
27872  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
27873 /* ========================================================  CFIFOL  ========================================================= */
27874 /* ========================================================  CFIFOLL  ======================================================== */
27875 /* =========================================================  CFIFO  ========================================================= */
27876 /* ========================================================  CFIFOH  ========================================================= */
27877 /* ========================================================  CFIFOHH  ======================================================== */
27878 /* ========================================================  D0FIFOL  ======================================================== */
27879 /* =======================================================  D0FIFOLL  ======================================================== */
27880 /* ========================================================  D0FIFO  ========================================================= */
27881 /* ========================================================  D0FIFOH  ======================================================== */
27882 /* =======================================================  D0FIFOHH  ======================================================== */
27883 /* ========================================================  D1FIFOL  ======================================================== */
27884 /* =======================================================  D1FIFOLL  ======================================================== */
27885 /* ========================================================  D1FIFO  ========================================================= */
27886 /* ========================================================  D1FIFOH  ======================================================== */
27887 /* =======================================================  D1FIFOHH  ======================================================== */
27888 /* =======================================================  CFIFOSEL  ======================================================== */
27889  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
27890  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
27891  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
27892  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
27893  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
27894  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
27895  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
27896  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
27897  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
27898  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
27899  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
27900  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
27901 /* =======================================================  CFIFOCTR  ======================================================== */
27902  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
27903  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
27904  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
27905  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
27906  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
27907  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
27908  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
27909  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
27910 /* =======================================================  D0FIFOSEL  ======================================================= */
27911  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
27912  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
27913  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
27914  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
27915  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
27916  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
27917  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
27918  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
27919  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
27920  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
27921  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
27922  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
27923  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
27924  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
27925 /* =======================================================  D0FIFOCTR  ======================================================= */
27926  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
27927  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
27928  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
27929  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
27930  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
27931  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
27932  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
27933  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
27934 /* =======================================================  D1FIFOSEL  ======================================================= */
27935  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
27936  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
27937  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
27938  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
27939  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
27940  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
27941  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
27942  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
27943  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
27944  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
27945  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
27946  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
27947  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
27948  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
27949 /* =======================================================  D1FIFOCTR  ======================================================= */
27950  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
27951  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
27952  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
27953  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
27954  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
27955  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
27956  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
27957  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
27958 /* ========================================================  INTENB0  ======================================================== */
27959  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
27960  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
27961  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
27962  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
27963  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
27964  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
27965  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
27966  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
27967  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
27968  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
27969  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
27970  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
27971  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
27972  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
27973  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
27974  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
27975 /* ========================================================  INTENB1  ======================================================== */
27976  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
27977  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
27978  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
27979  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
27980  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
27981  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
27982  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
27983  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
27984  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
27985  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
27986  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
27987  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
27988  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
27989  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
27990  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
27991  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
27992 /* ========================================================  BRDYENB  ======================================================== */
27993  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
27994  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
27995 /* ========================================================  NRDYENB  ======================================================== */
27996  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
27997  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
27998 /* ========================================================  BEMPENB  ======================================================== */
27999  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
28000  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
28001 /* ========================================================  SOFCFG  ========================================================= */
28002  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
28003  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
28004  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
28005  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
28006  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
28007  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
28008  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
28009  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
28010 /* ========================================================  PHYSET  ========================================================= */
28011  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
28012  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
28013  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
28014  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
28015  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
28016  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
28017  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
28018  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
28019  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
28020  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
28021  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
28022  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
28023  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
28024  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
28025 /* ========================================================  INTSTS0  ======================================================== */
28026  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
28027  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
28028  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
28029  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
28030  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
28031  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
28032  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
28033  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
28034  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
28035  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
28036  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
28037  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
28038  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
28039  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
28040  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
28041  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
28042  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
28043  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
28044  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
28045  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
28046  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
28047  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
28048  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
28049  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
28050 /* ========================================================  INTSTS1  ======================================================== */
28051  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
28052  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
28053  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
28054  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
28055  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
28056  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
28057  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
28058  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
28059  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
28060  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
28061  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
28062  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
28063  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
28064  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
28065  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
28066  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
28067  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
28068  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
28069  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
28070  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
28071 /* ========================================================  BRDYSTS  ======================================================== */
28072  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
28073  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
28074 /* ========================================================  NRDYSTS  ======================================================== */
28075  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
28076  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
28077 /* ========================================================  BEMPSTS  ======================================================== */
28078  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
28079  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
28080 /* ========================================================  FRMNUM  ========================================================= */
28081  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
28082  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
28083  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
28084  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
28085  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
28086  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
28087 /* ========================================================  UFRMNUM  ======================================================== */
28088  #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
28089  #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
28090  #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
28091  #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
28092 /* ========================================================  USBADDR  ======================================================== */
28093  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
28094  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
28095  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
28096  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
28097 /* ========================================================  USBREQ  ========================================================= */
28098  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
28099  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
28100  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
28101  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
28102 /* ========================================================  USBVAL  ========================================================= */
28103  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
28104  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
28105 /* ========================================================  USBINDX  ======================================================== */
28106  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
28107  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
28108 /* ========================================================  USBLENG  ======================================================== */
28109  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
28110  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
28111 /* ========================================================  DCPCFG  ========================================================= */
28112  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
28113  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
28114  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
28115  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28116  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
28117  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28118 /* ========================================================  DCPMAXP  ======================================================== */
28119  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
28120  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28121  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
28122  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
28123 /* ========================================================  DCPCTR  ========================================================= */
28124  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
28125  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28126  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
28127  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
28128  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
28129  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
28130  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
28131  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28132  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
28133  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28134  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
28135  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28136  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
28137  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28138  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
28139  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
28140  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
28141  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28142 /* ========================================================  PIPESEL  ======================================================== */
28143  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
28144  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
28145 /* ========================================================  PIPECFG  ======================================================== */
28146  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
28147  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
28148  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
28149  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
28150  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
28151  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
28152  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
28153  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28154  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
28155  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28156  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
28157  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
28158 /* =======================================================  PIPEMAXP  ======================================================== */
28159  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
28160  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28161  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
28162  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
28163 /* =======================================================  PIPEPERI  ======================================================== */
28164  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
28165  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
28166  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
28167  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
28168 /* =======================================================  PIPE_CTR  ======================================================== */
28169  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
28170  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28171  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
28172  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
28173  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
28174  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
28175  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
28176  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
28177  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
28178  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
28179  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
28180  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
28181  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
28182  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28183  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
28184  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28185  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
28186  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28187  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
28188  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28189  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
28190  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28191 /* ========================================================  DEVADD  ========================================================= */
28192  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
28193  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
28194  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
28195  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
28196  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
28197  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
28198 /* ======================================================  USBBCCTRL0  ======================================================= */
28199  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
28200  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
28201  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
28202  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
28203  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
28204  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
28205  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
28206  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
28207  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
28208  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
28209  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
28210  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
28211  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
28212  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
28213  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
28214  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
28215  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
28216  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
28217 /* ========================================================  UCKSEL  ========================================================= */
28218  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
28219  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
28220 /* =========================================================  USBMC  ========================================================= */
28221  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
28222  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
28223  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
28224  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
28225 /* ========================================================  PHYSLEW  ======================================================== */
28226  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
28227  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
28228  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
28229  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
28230  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
28231  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
28232  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
28233  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
28234 /* ========================================================  LPCTRL  ========================================================= */
28235  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
28236  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
28237 /* =========================================================  LPSTS  ========================================================= */
28238  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
28239  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
28240 /* ========================================================  BCCTRL  ========================================================= */
28241  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
28242  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
28243  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
28244  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
28245  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
28246  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
28247  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
28248  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
28249  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
28250  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
28251  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
28252  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
28253  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
28254  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
28255  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
28256  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
28257 /* =======================================================  PL1CTRL1  ======================================================== */
28258  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
28259  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
28260  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
28261  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
28262  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
28263  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
28264  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
28265  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
28266  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
28267  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
28268  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
28269  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
28270 /* =======================================================  PL1CTRL2  ======================================================== */
28271  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
28272  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
28273  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
28274  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
28275 /* =======================================================  HL1CTRL1  ======================================================== */
28276  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
28277  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
28278  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
28279  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
28280 /* =======================================================  HL1CTRL2  ======================================================== */
28281  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
28282  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
28283  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
28284  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
28285  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
28286  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
28287  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
28288  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
28289 /* ========================================================  DPUSR0R  ======================================================== */
28290  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
28291  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
28292  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
28293  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
28294  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
28295  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
28296 /* ========================================================  DPUSR1R  ======================================================== */
28297  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
28298  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
28299  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
28300  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
28301  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
28302  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
28303  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
28304  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
28305  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
28306  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
28307  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
28308  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
28309 /* ========================================================  DPUSR2R  ======================================================== */
28310  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
28311  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
28312  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
28313  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
28314  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
28315  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
28316  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
28317  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
28318  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
28319  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
28320  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
28321  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
28322 /* ========================================================  DPUSRCR  ======================================================== */
28323  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
28324  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
28325  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
28326  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
28327 /* ======================================================  DPUSR0R_FS  ======================================================= */
28328  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
28329  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
28330  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
28331  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
28332  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
28333  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
28334  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
28335  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
28336  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
28337  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
28338  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
28339  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
28340  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
28341  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
28342  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
28343  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
28344  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
28345  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
28346 /* ======================================================  DPUSR1R_FS  ======================================================= */
28347  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
28348  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
28349  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
28350  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
28351  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
28352  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
28353  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
28354  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
28355  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
28356  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
28357  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
28358  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
28359  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
28360  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
28361  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
28362  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
28363  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
28364  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
28365  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
28366  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
28367 
28368 /* =========================================================================================================================== */
28369 /* ================                                           R_WDT                                           ================ */
28370 /* =========================================================================================================================== */
28371 
28372 /* =========================================================  WDTRR  ========================================================= */
28373  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
28374  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
28375 /* =========================================================  WDTCR  ========================================================= */
28376  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
28377  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
28378  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
28379  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
28380  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
28381  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
28382  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
28383  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
28384 /* =========================================================  WDTSR  ========================================================= */
28385  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
28386  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
28387  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
28388  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
28389  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
28390  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
28391 /* ========================================================  WDTRCR  ========================================================= */
28392  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
28393  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
28394 /* =======================================================  WDTCSTPR  ======================================================== */
28395  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
28396  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
28397 
28398 /* =========================================================================================================================== */
28399 /* ================                                           R_TZF                                           ================ */
28400 /* =========================================================================================================================== */
28401 
28402 /* ========================================================  TZFOAD  ========================================================= */
28403  #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
28404  #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
28405  #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
28406  #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
28407 /* =========================================================  TZFPT  ========================================================= */
28408  #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
28409  #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
28410  #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
28411  #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
28412 
28413 /* =========================================================================================================================== */
28414 /* ================                                          R_CPSCU                                          ================ */
28415 /* =========================================================================================================================== */
28416 
28417 /* =========================================================  CSAR  ========================================================== */
28418  #define R_CPSCU_CSAR_CACHESA_Pos            (0UL)          /*!< CACHESA (Bit 0)                                       */
28419  #define R_CPSCU_CSAR_CACHESA_Msk            (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
28420  #define R_CPSCU_CSAR_CACHELSA_Pos           (1UL)          /*!< CACHELSA (Bit 1)                                      */
28421  #define R_CPSCU_CSAR_CACHELSA_Msk           (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
28422  #define R_CPSCU_CSAR_CACHEESA_Pos           (2UL)          /*!< CACHEESA (Bit 2)                                      */
28423  #define R_CPSCU_CSAR_CACHEESA_Msk           (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
28424 /* ========================================================  SRAMSAR  ======================================================== */
28425  #define R_CPSCU_SRAMSAR_SRAMSA0_Pos         (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
28426  #define R_CPSCU_SRAMSAR_SRAMSA0_Msk         (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
28427  #define R_CPSCU_SRAMSAR_SRAMSA1_Pos         (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
28428  #define R_CPSCU_SRAMSAR_SRAMSA1_Msk         (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
28429  #define R_CPSCU_SRAMSAR_SRAMSA2_Pos         (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
28430  #define R_CPSCU_SRAMSAR_SRAMSA2_Msk         (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
28431 /* =======================================================  STBRAMSAR  ======================================================= */
28432  #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos       (0UL)          /*!< NSBSTBR (Bit 0)                                       */
28433  #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk       (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
28434 /* ========================================================  DTCSAR  ========================================================= */
28435  #define R_CPSCU_DTCSAR_DTCSTSA_Pos          (0UL)          /*!< DTCSTSA (Bit 0)                                       */
28436  #define R_CPSCU_DTCSAR_DTCSTSA_Msk          (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
28437 /* ========================================================  DMACSAR  ======================================================== */
28438  #define R_CPSCU_DMACSAR_DMASTSA_Pos         (0UL)          /*!< DMASTSA (Bit 0)                                       */
28439  #define R_CPSCU_DMACSAR_DMASTSA_Msk         (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
28440 /* ========================================================  ICUSARA  ======================================================== */
28441  #define R_CPSCU_ICUSARA_SAIRQCRn_Pos        (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
28442  #define R_CPSCU_ICUSARA_SAIRQCRn_Msk        (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
28443 /* ========================================================  ICUSARB  ======================================================== */
28444  #define R_CPSCU_ICUSARB_SANMI_Pos           (0UL)          /*!< SANMI (Bit 0)                                         */
28445  #define R_CPSCU_ICUSARB_SANMI_Msk           (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
28446 /* ========================================================  ICUSARC  ======================================================== */
28447  #define R_CPSCU_ICUSARC_SADMACn_Pos         (0UL)          /*!< SADMACn (Bit 0)                                       */
28448  #define R_CPSCU_ICUSARC_SADMACn_Msk         (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
28449 /* ========================================================  ICUSARD  ======================================================== */
28450  #define R_CPSCU_ICUSARD_SASELSR0_Pos        (0UL)          /*!< SASELSR0 (Bit 0)                                      */
28451  #define R_CPSCU_ICUSARD_SASELSR0_Msk        (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
28452 /* ========================================================  ICUSARE  ======================================================== */
28453  #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos       (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
28454  #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk       (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
28455  #define R_CPSCU_ICUSARE_SALVD1WUP_Pos       (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
28456  #define R_CPSCU_ICUSARE_SALVD1WUP_Msk       (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
28457  #define R_CPSCU_ICUSARE_SALVD2WUP_Pos       (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
28458  #define R_CPSCU_ICUSARE_SALVD2WUP_Msk       (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
28459  #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos      (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
28460  #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk      (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
28461  #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos     (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
28462  #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk     (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
28463  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos     (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
28464  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk     (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
28465  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos     (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
28466  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk     (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
28467  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos     (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
28468  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk     (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
28469  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos     (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
28470  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk     (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
28471  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos     (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
28472  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk     (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
28473  #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos       (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
28474  #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk       (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
28475 /* ========================================================  ICUSARF  ======================================================== */
28476  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos     (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
28477  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk     (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
28478  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos     (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
28479  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk     (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
28480  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos     (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
28481  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk     (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
28482  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos    (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
28483  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk    (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
28484  #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos      (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
28485  #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk      (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
28486  #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos      (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
28487  #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk      (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
28488  #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos      (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
28489  #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk      (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
28490  #define R_CPSCU_ICUSARF_SAI3CWUP_Pos        (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
28491  #define R_CPSCU_ICUSARF_SAI3CWUP_Msk        (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
28492  #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos      (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
28493  #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk      (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
28494  #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos      (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
28495  #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk      (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
28496  #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos      (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
28497  #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk      (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
28498 /* ========================================================  ICUSARG  ======================================================== */
28499  #define R_CPSCU_ICUSARG_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
28500  #define R_CPSCU_ICUSARG_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
28501 /* ========================================================  ICUSARH  ======================================================== */
28502  #define R_CPSCU_ICUSARH_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
28503  #define R_CPSCU_ICUSARH_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
28504 /* ========================================================  ICUSARI  ======================================================== */
28505  #define R_CPSCU_ICUSARI_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
28506  #define R_CPSCU_ICUSARI_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
28507 /* ========================================================  BUSSARA  ======================================================== */
28508  #define R_CPSCU_BUSSARA_BUSSA0_Pos          (0UL)          /*!< BUSSA0 (Bit 0)                                        */
28509  #define R_CPSCU_BUSSARA_BUSSA0_Msk          (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
28510 /* ========================================================  BUSSARB  ======================================================== */
28511  #define R_CPSCU_BUSSARB_BUSSB0_Pos          (0UL)          /*!< BUSSB0 (Bit 0)                                        */
28512  #define R_CPSCU_BUSSARB_BUSSB0_Msk          (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
28513 /* =======================================================  MMPUSARA  ======================================================== */
28514  #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos       (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
28515  #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk       (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
28516 /* =======================================================  MMPUSARB  ======================================================== */
28517  #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos       (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
28518  #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk       (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
28519 /* =======================================================  DMACCHSAR  ======================================================= */
28520  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos    (0UL)          /*!< DMACCHSARn (Bit 0)                                    */
28521  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk    (0xffUL)       /*!< DMACCHSARn (Bitfield-Mask: 0xff)                      */
28522 /* ========================================================  CPUDSAR  ======================================================== */
28523  #define R_CPSCU_CPUDSAR_CPUDSA0_Pos         (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
28524  #define R_CPSCU_CPUDSAR_CPUDSA0_Msk         (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
28525 /* ======================================================  SRAMSABAR0  ======================================================= */
28526  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos    (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
28527  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk    (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
28528 /* ======================================================  SRAMSABAR1  ======================================================= */
28529  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos    (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
28530  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk    (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
28531 /* ========================================================  TEVTRCR  ======================================================== */
28532  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
28533  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
28534 
28535 /* =========================================================================================================================== */
28536 /* ================                                          R_DOC_B                                          ================ */
28537 /* =========================================================================================================================== */
28538 
28539 /* =========================================================  DOCR  ========================================================== */
28540  #define R_DOC_B_DOCR_OMS_Pos         (0UL)    /*!< OMS (Bit 0)                                           */
28541  #define R_DOC_B_DOCR_OMS_Msk         (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
28542  #define R_DOC_B_DOCR_DOBW_Pos        (3UL)    /*!< DOBW (Bit 3)                                          */
28543  #define R_DOC_B_DOCR_DOBW_Msk        (0x8UL)  /*!< DOBW (Bitfield-Mask: 0x01)                            */
28544  #define R_DOC_B_DOCR_DCSEL_Pos       (4UL)    /*!< DCSEL (Bit 4)                                         */
28545  #define R_DOC_B_DOCR_DCSEL_Msk       (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07)                           */
28546 /* =========================================================  DOSR  ========================================================== */
28547  #define R_DOC_B_DOSR_DOPCF_Pos       (0UL)    /*!< DOPCF (Bit 0)                                         */
28548  #define R_DOC_B_DOSR_DOPCF_Msk       (0x1UL)  /*!< DOPCF (Bitfield-Mask: 0x01)                           */
28549 /* =========================================================  DOSCR  ========================================================= */
28550  #define R_DOC_B_DOSCR_DOPCFCL_Pos    (0UL)    /*!< DOPCFCL (Bit 0)                                       */
28551  #define R_DOC_B_DOSCR_DOPCFCL_Msk    (0x1UL)  /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
28552 /* =========================================================  DODIR  ========================================================= */
28553 /* ========================================================  DODSR0  ========================================================= */
28554 /* ========================================================  DODSR1  ========================================================= */
28555 
28556 /* =========================================================================================================================== */
28557 /* ================                                         R_SCI_B0                                          ================ */
28558 /* =========================================================================================================================== */
28559 
28560 /* ==========================================================  RDR  ========================================================== */
28561  #define R_SCI_B0_RDR_RDAT_Pos           (0UL)          /*!< RDAT (Bit 0)                                          */
28562  #define R_SCI_B0_RDR_RDAT_Msk           (0x1ffUL)      /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
28563  #define R_SCI_B0_RDR_MPB_Pos            (9UL)          /*!< MPB (Bit 9)                                           */
28564  #define R_SCI_B0_RDR_MPB_Msk            (0x200UL)      /*!< MPB (Bitfield-Mask: 0x01)                             */
28565  #define R_SCI_B0_RDR_DR_Pos             (10UL)         /*!< DR (Bit 10)                                           */
28566  #define R_SCI_B0_RDR_DR_Msk             (0x400UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
28567  #define R_SCI_B0_RDR_FPER_Pos           (11UL)         /*!< FPER (Bit 11)                                         */
28568  #define R_SCI_B0_RDR_FPER_Msk           (0x800UL)      /*!< FPER (Bitfield-Mask: 0x01)                            */
28569  #define R_SCI_B0_RDR_FFER_Pos           (12UL)         /*!< FFER (Bit 12)                                         */
28570  #define R_SCI_B0_RDR_FFER_Msk           (0x1000UL)     /*!< FFER (Bitfield-Mask: 0x01)                            */
28571  #define R_SCI_B0_RDR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
28572  #define R_SCI_B0_RDR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
28573  #define R_SCI_B0_RDR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
28574  #define R_SCI_B0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
28575  #define R_SCI_B0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
28576  #define R_SCI_B0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
28577 /* ========================================================  RDR_BY  ========================================================= */
28578  #define R_SCI_B0_RDR_BY_RDAT_Pos        (0UL)          /*!< RDAT (Bit 0)                                          */
28579  #define R_SCI_B0_RDR_BY_RDAT_Msk        (0xffUL)       /*!< RDAT (Bitfield-Mask: 0xff)                            */
28580 /* ==========================================================  TDR  ========================================================== */
28581  #define R_SCI_B0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
28582  #define R_SCI_B0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
28583  #define R_SCI_B0_TDR_MPBT_Pos           (9UL)          /*!< MPBT (Bit 9)                                          */
28584  #define R_SCI_B0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
28585  #define R_SCI_B0_TDR_TSYNC_Pos          (12UL)         /*!< TSYNC (Bit 12)                                        */
28586  #define R_SCI_B0_TDR_TSYNC_Msk          (0x1000UL)     /*!< TSYNC (Bitfield-Mask: 0x01)                           */
28587 /* ========================================================  TDR_BY  ========================================================= */
28588  #define R_SCI_B0_TDR_BY_TDAT_Pos        (0UL)          /*!< TDAT (Bit 0)                                          */
28589  #define R_SCI_B0_TDR_BY_TDAT_Msk        (0xffUL)       /*!< TDAT (Bitfield-Mask: 0xff)                            */
28590 /* =========================================================  CCR0  ========================================================== */
28591  #define R_SCI_B0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
28592  #define R_SCI_B0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
28593  #define R_SCI_B0_CCR0_TE_Pos            (4UL)          /*!< TE (Bit 4)                                            */
28594  #define R_SCI_B0_CCR0_TE_Msk            (0x10UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
28595  #define R_SCI_B0_CCR0_MPIE_Pos          (8UL)          /*!< MPIE (Bit 8)                                          */
28596  #define R_SCI_B0_CCR0_MPIE_Msk          (0x100UL)      /*!< MPIE (Bitfield-Mask: 0x01)                            */
28597  #define R_SCI_B0_CCR0_DCME_Pos          (9UL)          /*!< DCME (Bit 9)                                          */
28598  #define R_SCI_B0_CCR0_DCME_Msk          (0x200UL)      /*!< DCME (Bitfield-Mask: 0x01)                            */
28599  #define R_SCI_B0_CCR0_IDSEL_Pos         (10UL)         /*!< IDSEL (Bit 10)                                        */
28600  #define R_SCI_B0_CCR0_IDSEL_Msk         (0x400UL)      /*!< IDSEL (Bitfield-Mask: 0x01)                           */
28601  #define R_SCI_B0_CCR0_RIE_Pos           (16UL)         /*!< RIE (Bit 16)                                          */
28602  #define R_SCI_B0_CCR0_RIE_Msk           (0x10000UL)    /*!< RIE (Bitfield-Mask: 0x01)                             */
28603  #define R_SCI_B0_CCR0_TIE_Pos           (20UL)         /*!< TIE (Bit 20)                                          */
28604  #define R_SCI_B0_CCR0_TIE_Msk           (0x100000UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
28605  #define R_SCI_B0_CCR0_TEIE_Pos          (21UL)         /*!< TEIE (Bit 21)                                         */
28606  #define R_SCI_B0_CCR0_TEIE_Msk          (0x200000UL)   /*!< TEIE (Bitfield-Mask: 0x01)                            */
28607  #define R_SCI_B0_CCR0_SSE_Pos           (24UL)         /*!< SSE (Bit 24)                                          */
28608  #define R_SCI_B0_CCR0_SSE_Msk           (0x1000000UL)  /*!< SSE (Bitfield-Mask: 0x01)                             */
28609 /* =========================================================  CCR1  ========================================================== */
28610  #define R_SCI_B0_CCR1_CTSE_Pos          (0UL)          /*!< CTSE (Bit 0)                                          */
28611  #define R_SCI_B0_CCR1_CTSE_Msk          (0x1UL)        /*!< CTSE (Bitfield-Mask: 0x01)                            */
28612  #define R_SCI_B0_CCR1_CTSPEN_Pos        (1UL)          /*!< CTSPEN (Bit 1)                                        */
28613  #define R_SCI_B0_CCR1_CTSPEN_Msk        (0x2UL)        /*!< CTSPEN (Bitfield-Mask: 0x01)                          */
28614  #define R_SCI_B0_CCR1_SPB2DT_Pos        (4UL)          /*!< SPB2DT (Bit 4)                                        */
28615  #define R_SCI_B0_CCR1_SPB2DT_Msk        (0x10UL)       /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
28616  #define R_SCI_B0_CCR1_SPB2IO_Pos        (5UL)          /*!< SPB2IO (Bit 5)                                        */
28617  #define R_SCI_B0_CCR1_SPB2IO_Msk        (0x20UL)       /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
28618  #define R_SCI_B0_CCR1_PE_Pos            (8UL)          /*!< PE (Bit 8)                                            */
28619  #define R_SCI_B0_CCR1_PE_Msk            (0x100UL)      /*!< PE (Bitfield-Mask: 0x01)                              */
28620  #define R_SCI_B0_CCR1_PM_Pos            (9UL)          /*!< PM (Bit 9)                                            */
28621  #define R_SCI_B0_CCR1_PM_Msk            (0x200UL)      /*!< PM (Bitfield-Mask: 0x01)                              */
28622  #define R_SCI_B0_CCR1_TINV_Pos          (12UL)         /*!< TINV (Bit 12)                                         */
28623  #define R_SCI_B0_CCR1_TINV_Msk          (0x1000UL)     /*!< TINV (Bitfield-Mask: 0x01)                            */
28624  #define R_SCI_B0_CCR1_RINV_Pos          (13UL)         /*!< RINV (Bit 13)                                         */
28625  #define R_SCI_B0_CCR1_RINV_Msk          (0x2000UL)     /*!< RINV (Bitfield-Mask: 0x01)                            */
28626  #define R_SCI_B0_CCR1_SPLP_Pos          (16UL)         /*!< SPLP (Bit 16)                                         */
28627  #define R_SCI_B0_CCR1_SPLP_Msk          (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
28628  #define R_SCI_B0_CCR1_SHARPS_Pos        (20UL)         /*!< SHARPS (Bit 20)                                       */
28629  #define R_SCI_B0_CCR1_SHARPS_Msk        (0x100000UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
28630  #define R_SCI_B0_CCR1_NFCS_Pos          (24UL)         /*!< NFCS (Bit 24)                                         */
28631  #define R_SCI_B0_CCR1_NFCS_Msk          (0x7000000UL)  /*!< NFCS (Bitfield-Mask: 0x07)                            */
28632  #define R_SCI_B0_CCR1_NFEN_Pos          (28UL)         /*!< NFEN (Bit 28)                                         */
28633  #define R_SCI_B0_CCR1_NFEN_Msk          (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
28634 /* =========================================================  CCR2  ========================================================== */
28635  #define R_SCI_B0_CCR2_BCP_Pos           (0UL)          /*!< BCP (Bit 0)                                           */
28636  #define R_SCI_B0_CCR2_BCP_Msk           (0x7UL)        /*!< BCP (Bitfield-Mask: 0x07)                             */
28637  #define R_SCI_B0_CCR2_BGDM_Pos          (4UL)          /*!< BGDM (Bit 4)                                          */
28638  #define R_SCI_B0_CCR2_BGDM_Msk          (0x10UL)       /*!< BGDM (Bitfield-Mask: 0x01)                            */
28639  #define R_SCI_B0_CCR2_ABCS_Pos          (5UL)          /*!< ABCS (Bit 5)                                          */
28640  #define R_SCI_B0_CCR2_ABCS_Msk          (0x20UL)       /*!< ABCS (Bitfield-Mask: 0x01)                            */
28641  #define R_SCI_B0_CCR2_ABCSE_Pos         (6UL)          /*!< ABCSE (Bit 6)                                         */
28642  #define R_SCI_B0_CCR2_ABCSE_Msk         (0x40UL)       /*!< ABCSE (Bitfield-Mask: 0x01)                           */
28643  #define R_SCI_B0_CCR2_BRR_Pos           (8UL)          /*!< BRR (Bit 8)                                           */
28644  #define R_SCI_B0_CCR2_BRR_Msk           (0xff00UL)     /*!< BRR (Bitfield-Mask: 0xff)                             */
28645  #define R_SCI_B0_CCR2_BRME_Pos          (16UL)         /*!< BRME (Bit 16)                                         */
28646  #define R_SCI_B0_CCR2_BRME_Msk          (0x10000UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
28647  #define R_SCI_B0_CCR2_CKS_Pos           (20UL)         /*!< CKS (Bit 20)                                          */
28648  #define R_SCI_B0_CCR2_CKS_Msk           (0x300000UL)   /*!< CKS (Bitfield-Mask: 0x03)                             */
28649  #define R_SCI_B0_CCR2_MDDR_Pos          (24UL)         /*!< MDDR (Bit 24)                                         */
28650  #define R_SCI_B0_CCR2_MDDR_Msk          (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff)                            */
28651 /* =========================================================  CCR3  ========================================================== */
28652  #define R_SCI_B0_CCR3_CPHA_Pos          (0UL)          /*!< CPHA (Bit 0)                                          */
28653  #define R_SCI_B0_CCR3_CPHA_Msk          (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
28654  #define R_SCI_B0_CCR3_CPOL_Pos          (1UL)          /*!< CPOL (Bit 1)                                          */
28655  #define R_SCI_B0_CCR3_CPOL_Msk          (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
28656  #define R_SCI_B0_CCR3_BPEN_Pos          (7UL)          /*!< BPEN (Bit 7)                                          */
28657  #define R_SCI_B0_CCR3_BPEN_Msk          (0x80UL)       /*!< BPEN (Bitfield-Mask: 0x01)                            */
28658  #define R_SCI_B0_CCR3_CHR_Pos           (8UL)          /*!< CHR (Bit 8)                                           */
28659  #define R_SCI_B0_CCR3_CHR_Msk           (0x300UL)      /*!< CHR (Bitfield-Mask: 0x03)                             */
28660  #define R_SCI_B0_CCR3_LSBF_Pos          (12UL)         /*!< LSBF (Bit 12)                                         */
28661  #define R_SCI_B0_CCR3_LSBF_Msk          (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
28662  #define R_SCI_B0_CCR3_SINV_Pos          (13UL)         /*!< SINV (Bit 13)                                         */
28663  #define R_SCI_B0_CCR3_SINV_Msk          (0x2000UL)     /*!< SINV (Bitfield-Mask: 0x01)                            */
28664  #define R_SCI_B0_CCR3_STP_Pos           (14UL)         /*!< STP (Bit 14)                                          */
28665  #define R_SCI_B0_CCR3_STP_Msk           (0x4000UL)     /*!< STP (Bitfield-Mask: 0x01)                             */
28666  #define R_SCI_B0_CCR3_RXDESEL_Pos       (15UL)         /*!< RXDESEL (Bit 15)                                      */
28667  #define R_SCI_B0_CCR3_RXDESEL_Msk       (0x8000UL)     /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
28668  #define R_SCI_B0_CCR3_MOD_Pos           (16UL)         /*!< MOD (Bit 16)                                          */
28669  #define R_SCI_B0_CCR3_MOD_Msk           (0x70000UL)    /*!< MOD (Bitfield-Mask: 0x07)                             */
28670  #define R_SCI_B0_CCR3_MP_Pos            (19UL)         /*!< MP (Bit 19)                                           */
28671  #define R_SCI_B0_CCR3_MP_Msk            (0x80000UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
28672  #define R_SCI_B0_CCR3_FM_Pos            (20UL)         /*!< FM (Bit 20)                                           */
28673  #define R_SCI_B0_CCR3_FM_Msk            (0x100000UL)   /*!< FM (Bitfield-Mask: 0x01)                              */
28674  #define R_SCI_B0_CCR3_DEN_Pos           (21UL)         /*!< DEN (Bit 21)                                          */
28675  #define R_SCI_B0_CCR3_DEN_Msk           (0x200000UL)   /*!< DEN (Bitfield-Mask: 0x01)                             */
28676  #define R_SCI_B0_CCR3_CKE_Pos           (24UL)         /*!< CKE (Bit 24)                                          */
28677  #define R_SCI_B0_CCR3_CKE_Msk           (0x3000000UL)  /*!< CKE (Bitfield-Mask: 0x03)                             */
28678  #define R_SCI_B0_CCR3_GM_Pos            (28UL)         /*!< GM (Bit 28)                                           */
28679  #define R_SCI_B0_CCR3_GM_Msk            (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01)                              */
28680  #define R_SCI_B0_CCR3_BLK_Pos           (29UL)         /*!< BLK (Bit 29)                                          */
28681  #define R_SCI_B0_CCR3_BLK_Msk           (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01)                             */
28682 /* =========================================================  CCR4  ========================================================== */
28683  #define R_SCI_B0_CCR4_CMPD_Pos          (0UL)          /*!< CMPD (Bit 0)                                          */
28684  #define R_SCI_B0_CCR4_CMPD_Msk          (0x1ffUL)      /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
28685  #define R_SCI_B0_CCR4_ASEN_Pos          (16UL)         /*!< ASEN (Bit 16)                                         */
28686  #define R_SCI_B0_CCR4_ASEN_Msk          (0x10000UL)    /*!< ASEN (Bitfield-Mask: 0x01)                            */
28687  #define R_SCI_B0_CCR4_ATEN_Pos          (17UL)         /*!< ATEN (Bit 17)                                         */
28688  #define R_SCI_B0_CCR4_ATEN_Msk          (0x20000UL)    /*!< ATEN (Bitfield-Mask: 0x01)                            */
28689  #define R_SCI_B0_CCR4_SCKSEL_Pos        (19UL)         /*!< SCKSEL (Bit 19)                                       */
28690  #define R_SCI_B0_CCR4_SCKSEL_Msk        (0x80000UL)    /*!< SCKSEL (Bitfield-Mask: 0x01)                          */
28691  #define R_SCI_B0_CCR4_AST_Pos           (24UL)         /*!< AST (Bit 24)                                          */
28692  #define R_SCI_B0_CCR4_AST_Msk           (0x7000000UL)  /*!< AST (Bitfield-Mask: 0x07)                             */
28693  #define R_SCI_B0_CCR4_AJD_Pos           (27UL)         /*!< AJD (Bit 27)                                          */
28694  #define R_SCI_B0_CCR4_AJD_Msk           (0x8000000UL)  /*!< AJD (Bitfield-Mask: 0x01)                             */
28695  #define R_SCI_B0_CCR4_ATT_Pos           (28UL)         /*!< ATT (Bit 28)                                          */
28696  #define R_SCI_B0_CCR4_ATT_Msk           (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07)                             */
28697  #define R_SCI_B0_CCR4_AET_Pos           (31UL)         /*!< AET (Bit 31)                                          */
28698  #define R_SCI_B0_CCR4_AET_Msk           (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01)                             */
28699 /* =========================================================  CESR  ========================================================== */
28700  #define R_SCI_B0_CESR_RIST_Pos          (0UL)          /*!< RIST (Bit 0)                                          */
28701  #define R_SCI_B0_CESR_RIST_Msk          (0x1UL)        /*!< RIST (Bitfield-Mask: 0x01)                            */
28702  #define R_SCI_B0_CESR_TIST_Pos          (4UL)          /*!< TIST (Bit 4)                                          */
28703  #define R_SCI_B0_CESR_TIST_Msk          (0x10UL)       /*!< TIST (Bitfield-Mask: 0x01)                            */
28704 /* ==========================================================  ICR  ========================================================== */
28705  #define R_SCI_B0_ICR_IICDL_Pos          (0UL)          /*!< IICDL (Bit 0)                                         */
28706  #define R_SCI_B0_ICR_IICDL_Msk          (0x1fUL)       /*!< IICDL (Bitfield-Mask: 0x1f)                           */
28707  #define R_SCI_B0_ICR_IICINTM_Pos        (8UL)          /*!< IICINTM (Bit 8)                                       */
28708  #define R_SCI_B0_ICR_IICINTM_Msk        (0x100UL)      /*!< IICINTM (Bitfield-Mask: 0x01)                         */
28709  #define R_SCI_B0_ICR_IICCSC_Pos         (9UL)          /*!< IICCSC (Bit 9)                                        */
28710  #define R_SCI_B0_ICR_IICCSC_Msk         (0x200UL)      /*!< IICCSC (Bitfield-Mask: 0x01)                          */
28711  #define R_SCI_B0_ICR_IICACKT_Pos        (13UL)         /*!< IICACKT (Bit 13)                                      */
28712  #define R_SCI_B0_ICR_IICACKT_Msk        (0x2000UL)     /*!< IICACKT (Bitfield-Mask: 0x01)                         */
28713  #define R_SCI_B0_ICR_IICSTAREQ_Pos      (16UL)         /*!< IICSTAREQ (Bit 16)                                    */
28714  #define R_SCI_B0_ICR_IICSTAREQ_Msk      (0x10000UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
28715  #define R_SCI_B0_ICR_IICRSTAREQ_Pos     (17UL)         /*!< IICRSTAREQ (Bit 17)                                   */
28716  #define R_SCI_B0_ICR_IICRSTAREQ_Msk     (0x20000UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
28717  #define R_SCI_B0_ICR_IICSTPREQ_Pos      (18UL)         /*!< IICSTPREQ (Bit 18)                                    */
28718  #define R_SCI_B0_ICR_IICSTPREQ_Msk      (0x40000UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
28719  #define R_SCI_B0_ICR_IICSDAS_Pos        (20UL)         /*!< IICSDAS (Bit 20)                                      */
28720  #define R_SCI_B0_ICR_IICSDAS_Msk        (0x300000UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
28721  #define R_SCI_B0_ICR_IICSCLS_Pos        (22UL)         /*!< IICSCLS (Bit 22)                                      */
28722  #define R_SCI_B0_ICR_IICSCLS_Msk        (0xc00000UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
28723 /* ==========================================================  FCR  ========================================================== */
28724  #define R_SCI_B0_FCR_DRES_Pos           (0UL)          /*!< DRES (Bit 0)                                          */
28725  #define R_SCI_B0_FCR_DRES_Msk           (0x1UL)        /*!< DRES (Bitfield-Mask: 0x01)                            */
28726  #define R_SCI_B0_FCR_TTRG_Pos           (8UL)          /*!< TTRG (Bit 8)                                          */
28727  #define R_SCI_B0_FCR_TTRG_Msk           (0x1f00UL)     /*!< TTRG (Bitfield-Mask: 0x1f)                            */
28728  #define R_SCI_B0_FCR_TFRST_Pos          (15UL)         /*!< TFRST (Bit 15)                                        */
28729  #define R_SCI_B0_FCR_TFRST_Msk          (0x8000UL)     /*!< TFRST (Bitfield-Mask: 0x01)                           */
28730  #define R_SCI_B0_FCR_RTRG_Pos           (16UL)         /*!< RTRG (Bit 16)                                         */
28731  #define R_SCI_B0_FCR_RTRG_Msk           (0x1f0000UL)   /*!< RTRG (Bitfield-Mask: 0x1f)                            */
28732  #define R_SCI_B0_FCR_RFRST_Pos          (23UL)         /*!< RFRST (Bit 23)                                        */
28733  #define R_SCI_B0_FCR_RFRST_Msk          (0x800000UL)   /*!< RFRST (Bitfield-Mask: 0x01)                           */
28734  #define R_SCI_B0_FCR_RSTRG_Pos          (24UL)         /*!< RSTRG (Bit 24)                                        */
28735  #define R_SCI_B0_FCR_RSTRG_Msk          (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f)                           */
28736 /* ==========================================================  MCR  ========================================================== */
28737  #define R_SCI_B0_MCR_RMPOL_Pos          (0UL)          /*!< RMPOL (Bit 0)                                         */
28738  #define R_SCI_B0_MCR_RMPOL_Msk          (0x1UL)        /*!< RMPOL (Bitfield-Mask: 0x01)                           */
28739  #define R_SCI_B0_MCR_TMPOL_Pos          (1UL)          /*!< TMPOL (Bit 1)                                         */
28740  #define R_SCI_B0_MCR_TMPOL_Msk          (0x2UL)        /*!< TMPOL (Bitfield-Mask: 0x01)                           */
28741  #define R_SCI_B0_MCR_ERTEN_Pos          (2UL)          /*!< ERTEN (Bit 2)                                         */
28742  #define R_SCI_B0_MCR_ERTEN_Msk          (0x4UL)        /*!< ERTEN (Bitfield-Mask: 0x01)                           */
28743  #define R_SCI_B0_MCR_SYNVAL_Pos         (4UL)          /*!< SYNVAL (Bit 4)                                        */
28744  #define R_SCI_B0_MCR_SYNVAL_Msk         (0x10UL)       /*!< SYNVAL (Bitfield-Mask: 0x01)                          */
28745  #define R_SCI_B0_MCR_SYNSEL_Pos         (5UL)          /*!< SYNSEL (Bit 5)                                        */
28746  #define R_SCI_B0_MCR_SYNSEL_Msk         (0x20UL)       /*!< SYNSEL (Bitfield-Mask: 0x01)                          */
28747  #define R_SCI_B0_MCR_SBSEL_Pos          (6UL)          /*!< SBSEL (Bit 6)                                         */
28748  #define R_SCI_B0_MCR_SBSEL_Msk          (0x40UL)       /*!< SBSEL (Bitfield-Mask: 0x01)                           */
28749  #define R_SCI_B0_MCR_TPLEN_Pos          (8UL)          /*!< TPLEN (Bit 8)                                         */
28750  #define R_SCI_B0_MCR_TPLEN_Msk          (0xf00UL)      /*!< TPLEN (Bitfield-Mask: 0x0f)                           */
28751  #define R_SCI_B0_MCR_TPPAT_Pos          (12UL)         /*!< TPPAT (Bit 12)                                        */
28752  #define R_SCI_B0_MCR_TPPAT_Msk          (0x3000UL)     /*!< TPPAT (Bitfield-Mask: 0x03)                           */
28753  #define R_SCI_B0_MCR_RPLEN_Pos          (16UL)         /*!< RPLEN (Bit 16)                                        */
28754  #define R_SCI_B0_MCR_RPLEN_Msk          (0xf0000UL)    /*!< RPLEN (Bitfield-Mask: 0x0f)                           */
28755  #define R_SCI_B0_MCR_RPPAT_Pos          (20UL)         /*!< RPPAT (Bit 20)                                        */
28756  #define R_SCI_B0_MCR_RPPAT_Msk          (0x300000UL)   /*!< RPPAT (Bitfield-Mask: 0x03)                           */
28757  #define R_SCI_B0_MCR_PFEREN_Pos         (24UL)         /*!< PFEREN (Bit 24)                                       */
28758  #define R_SCI_B0_MCR_PFEREN_Msk         (0x1000000UL)  /*!< PFEREN (Bitfield-Mask: 0x01)                          */
28759  #define R_SCI_B0_MCR_SYEREN_Pos         (25UL)         /*!< SYEREN (Bit 25)                                       */
28760  #define R_SCI_B0_MCR_SYEREN_Msk         (0x2000000UL)  /*!< SYEREN (Bitfield-Mask: 0x01)                          */
28761  #define R_SCI_B0_MCR_SBEREN_Pos         (26UL)         /*!< SBEREN (Bit 26)                                       */
28762  #define R_SCI_B0_MCR_SBEREN_Msk         (0x4000000UL)  /*!< SBEREN (Bitfield-Mask: 0x01)                          */
28763 /* ==========================================================  DCR  ========================================================== */
28764  #define R_SCI_B0_DCR_DEPOL_Pos          (0UL)          /*!< DEPOL (Bit 0)                                         */
28765  #define R_SCI_B0_DCR_DEPOL_Msk          (0x1UL)        /*!< DEPOL (Bitfield-Mask: 0x01)                           */
28766  #define R_SCI_B0_DCR_DEAST_Pos          (8UL)          /*!< DEAST (Bit 8)                                         */
28767  #define R_SCI_B0_DCR_DEAST_Msk          (0x1f00UL)     /*!< DEAST (Bitfield-Mask: 0x1f)                           */
28768  #define R_SCI_B0_DCR_DENGT_Pos          (16UL)         /*!< DENGT (Bit 16)                                        */
28769  #define R_SCI_B0_DCR_DENGT_Msk          (0x1f0000UL)   /*!< DENGT (Bitfield-Mask: 0x1f)                           */
28770 /* =========================================================  XCR0  ========================================================== */
28771  #define R_SCI_B0_XCR0_TCSS_Pos          (0UL)          /*!< TCSS (Bit 0)                                          */
28772  #define R_SCI_B0_XCR0_TCSS_Msk          (0x3UL)        /*!< TCSS (Bitfield-Mask: 0x03)                            */
28773  #define R_SCI_B0_XCR0_BFE_Pos           (8UL)          /*!< BFE (Bit 8)                                           */
28774  #define R_SCI_B0_XCR0_BFE_Msk           (0x100UL)      /*!< BFE (Bitfield-Mask: 0x01)                             */
28775  #define R_SCI_B0_XCR0_CF0RE_Pos         (9UL)          /*!< CF0RE (Bit 9)                                         */
28776  #define R_SCI_B0_XCR0_CF0RE_Msk         (0x200UL)      /*!< CF0RE (Bitfield-Mask: 0x01)                           */
28777  #define R_SCI_B0_XCR0_CF1DS_Pos         (10UL)         /*!< CF1DS (Bit 10)                                        */
28778  #define R_SCI_B0_XCR0_CF1DS_Msk         (0xc00UL)      /*!< CF1DS (Bitfield-Mask: 0x03)                           */
28779  #define R_SCI_B0_XCR0_PIBE_Pos          (12UL)         /*!< PIBE (Bit 12)                                         */
28780  #define R_SCI_B0_XCR0_PIBE_Msk          (0x1000UL)     /*!< PIBE (Bitfield-Mask: 0x01)                            */
28781  #define R_SCI_B0_XCR0_PIBS_Pos          (13UL)         /*!< PIBS (Bit 13)                                         */
28782  #define R_SCI_B0_XCR0_PIBS_Msk          (0xe000UL)     /*!< PIBS (Bitfield-Mask: 0x07)                            */
28783  #define R_SCI_B0_XCR0_BFOIE_Pos         (16UL)         /*!< BFOIE (Bit 16)                                        */
28784  #define R_SCI_B0_XCR0_BFOIE_Msk         (0x10000UL)    /*!< BFOIE (Bitfield-Mask: 0x01)                           */
28785  #define R_SCI_B0_XCR0_BCDIE_Pos         (17UL)         /*!< BCDIE (Bit 17)                                        */
28786  #define R_SCI_B0_XCR0_BCDIE_Msk         (0x20000UL)    /*!< BCDIE (Bitfield-Mask: 0x01)                           */
28787  #define R_SCI_B0_XCR0_BFDIE_Pos         (20UL)         /*!< BFDIE (Bit 20)                                        */
28788  #define R_SCI_B0_XCR0_BFDIE_Msk         (0x100000UL)   /*!< BFDIE (Bitfield-Mask: 0x01)                           */
28789  #define R_SCI_B0_XCR0_COFIE_Pos         (21UL)         /*!< COFIE (Bit 21)                                        */
28790  #define R_SCI_B0_XCR0_COFIE_Msk         (0x200000UL)   /*!< COFIE (Bitfield-Mask: 0x01)                           */
28791  #define R_SCI_B0_XCR0_AEDIE_Pos         (22UL)         /*!< AEDIE (Bit 22)                                        */
28792  #define R_SCI_B0_XCR0_AEDIE_Msk         (0x400000UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
28793  #define R_SCI_B0_XCR0_BCCS_Pos          (24UL)         /*!< BCCS (Bit 24)                                         */
28794  #define R_SCI_B0_XCR0_BCCS_Msk          (0x3000000UL)  /*!< BCCS (Bitfield-Mask: 0x03)                            */
28795 /* =========================================================  XCR1  ========================================================== */
28796  #define R_SCI_B0_XCR1_TCST_Pos          (0UL)          /*!< TCST (Bit 0)                                          */
28797  #define R_SCI_B0_XCR1_TCST_Msk          (0x1UL)        /*!< TCST (Bitfield-Mask: 0x01)                            */
28798  #define R_SCI_B0_XCR1_SDST_Pos          (4UL)          /*!< SDST (Bit 4)                                          */
28799  #define R_SCI_B0_XCR1_SDST_Msk          (0x10UL)       /*!< SDST (Bitfield-Mask: 0x01)                            */
28800  #define R_SCI_B0_XCR1_BMEN_Pos          (5UL)          /*!< BMEN (Bit 5)                                          */
28801  #define R_SCI_B0_XCR1_BMEN_Msk          (0x20UL)       /*!< BMEN (Bitfield-Mask: 0x01)                            */
28802  #define R_SCI_B0_XCR1_PCF1D_Pos         (8UL)          /*!< PCF1D (Bit 8)                                         */
28803  #define R_SCI_B0_XCR1_PCF1D_Msk         (0xff00UL)     /*!< PCF1D (Bitfield-Mask: 0xff)                           */
28804  #define R_SCI_B0_XCR1_SCF1D_Pos         (16UL)         /*!< SCF1D (Bit 16)                                        */
28805  #define R_SCI_B0_XCR1_SCF1D_Msk         (0xff0000UL)   /*!< SCF1D (Bitfield-Mask: 0xff)                           */
28806  #define R_SCI_B0_XCR1_CF1CE_Pos         (24UL)         /*!< CF1CE (Bit 24)                                        */
28807  #define R_SCI_B0_XCR1_CF1CE_Msk         (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff)                           */
28808 /* =========================================================  XCR2  ========================================================== */
28809  #define R_SCI_B0_XCR2_CF0D_Pos          (0UL)          /*!< CF0D (Bit 0)                                          */
28810  #define R_SCI_B0_XCR2_CF0D_Msk          (0xffUL)       /*!< CF0D (Bitfield-Mask: 0xff)                            */
28811  #define R_SCI_B0_XCR2_CF0CE_Pos         (8UL)          /*!< CF0CE (Bit 8)                                         */
28812  #define R_SCI_B0_XCR2_CF0CE_Msk         (0xff00UL)     /*!< CF0CE (Bitfield-Mask: 0xff)                           */
28813  #define R_SCI_B0_XCR2_BFLW_Pos          (16UL)         /*!< BFLW (Bit 16)                                         */
28814  #define R_SCI_B0_XCR2_BFLW_Msk          (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff)                          */
28815 /* ==========================================================  CSR  ========================================================== */
28816  #define R_SCI_B0_CSR_ERS_Pos            (4UL)          /*!< ERS (Bit 4)                                           */
28817  #define R_SCI_B0_CSR_ERS_Msk            (0x10UL)       /*!< ERS (Bitfield-Mask: 0x01)                             */
28818  #define R_SCI_B0_CSR_RXDMON_Pos         (15UL)         /*!< RXDMON (Bit 15)                                       */
28819  #define R_SCI_B0_CSR_RXDMON_Msk         (0x8000UL)     /*!< RXDMON (Bitfield-Mask: 0x01)                          */
28820  #define R_SCI_B0_CSR_DCMF_Pos           (16UL)         /*!< DCMF (Bit 16)                                         */
28821  #define R_SCI_B0_CSR_DCMF_Msk           (0x10000UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
28822  #define R_SCI_B0_CSR_DPER_Pos           (17UL)         /*!< DPER (Bit 17)                                         */
28823  #define R_SCI_B0_CSR_DPER_Msk           (0x20000UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
28824  #define R_SCI_B0_CSR_DFER_Pos           (18UL)         /*!< DFER (Bit 18)                                         */
28825  #define R_SCI_B0_CSR_DFER_Msk           (0x40000UL)    /*!< DFER (Bitfield-Mask: 0x01)                            */
28826  #define R_SCI_B0_CSR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
28827  #define R_SCI_B0_CSR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
28828  #define R_SCI_B0_CSR_MFF_Pos            (26UL)         /*!< MFF (Bit 26)                                          */
28829  #define R_SCI_B0_CSR_MFF_Msk            (0x4000000UL)  /*!< MFF (Bitfield-Mask: 0x01)                             */
28830  #define R_SCI_B0_CSR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
28831  #define R_SCI_B0_CSR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
28832  #define R_SCI_B0_CSR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
28833  #define R_SCI_B0_CSR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
28834  #define R_SCI_B0_CSR_TDRE_Pos           (29UL)         /*!< TDRE (Bit 29)                                         */
28835  #define R_SCI_B0_CSR_TDRE_Msk           (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
28836  #define R_SCI_B0_CSR_TEND_Pos           (30UL)         /*!< TEND (Bit 30)                                         */
28837  #define R_SCI_B0_CSR_TEND_Msk           (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
28838  #define R_SCI_B0_CSR_RDRF_Pos           (31UL)         /*!< RDRF (Bit 31)                                         */
28839  #define R_SCI_B0_CSR_RDRF_Msk           (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
28840 /* ==========================================================  ISR  ========================================================== */
28841  #define R_SCI_B0_ISR_IICACKR_Pos        (0UL)          /*!< IICACKR (Bit 0)                                       */
28842  #define R_SCI_B0_ISR_IICACKR_Msk        (0x1UL)        /*!< IICACKR (Bitfield-Mask: 0x01)                         */
28843  #define R_SCI_B0_ISR_IICSTIF_Pos        (3UL)          /*!< IICSTIF (Bit 3)                                       */
28844  #define R_SCI_B0_ISR_IICSTIF_Msk        (0x8UL)        /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
28845 /* =========================================================  FRSR  ========================================================== */
28846  #define R_SCI_B0_FRSR_DR_Pos            (0UL)          /*!< DR (Bit 0)                                            */
28847  #define R_SCI_B0_FRSR_DR_Msk            (0x1UL)        /*!< DR (Bitfield-Mask: 0x01)                              */
28848  #define R_SCI_B0_FRSR_R_Pos             (8UL)          /*!< R (Bit 8)                                             */
28849  #define R_SCI_B0_FRSR_R_Msk             (0x3f00UL)     /*!< R (Bitfield-Mask: 0x3f)                               */
28850  #define R_SCI_B0_FRSR_PNUM_Pos          (16UL)         /*!< PNUM (Bit 16)                                         */
28851  #define R_SCI_B0_FRSR_PNUM_Msk          (0x3f0000UL)   /*!< PNUM (Bitfield-Mask: 0x3f)                            */
28852  #define R_SCI_B0_FRSR_FNUM_Pos          (24UL)         /*!< FNUM (Bit 24)                                         */
28853  #define R_SCI_B0_FRSR_FNUM_Msk          (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f)                            */
28854 /* =========================================================  FTSR  ========================================================== */
28855  #define R_SCI_B0_FTSR_T_Pos             (0UL)          /*!< T (Bit 0)                                             */
28856  #define R_SCI_B0_FTSR_T_Msk             (0x3fUL)       /*!< T (Bitfield-Mask: 0x3f)                               */
28857 /* ==========================================================  MSR  ========================================================== */
28858  #define R_SCI_B0_MSR_PFER_Pos           (0UL)          /*!< PFER (Bit 0)                                          */
28859  #define R_SCI_B0_MSR_PFER_Msk           (0x1UL)        /*!< PFER (Bitfield-Mask: 0x01)                            */
28860  #define R_SCI_B0_MSR_SYER_Pos           (1UL)          /*!< SYER (Bit 1)                                          */
28861  #define R_SCI_B0_MSR_SYER_Msk           (0x2UL)        /*!< SYER (Bitfield-Mask: 0x01)                            */
28862  #define R_SCI_B0_MSR_SBER_Pos           (2UL)          /*!< SBER (Bit 2)                                          */
28863  #define R_SCI_B0_MSR_SBER_Msk           (0x4UL)        /*!< SBER (Bitfield-Mask: 0x01)                            */
28864  #define R_SCI_B0_MSR_MER_Pos            (4UL)          /*!< MER (Bit 4)                                           */
28865  #define R_SCI_B0_MSR_MER_Msk            (0x10UL)       /*!< MER (Bitfield-Mask: 0x01)                             */
28866  #define R_SCI_B0_MSR_RSYNC_Pos          (6UL)          /*!< RSYNC (Bit 6)                                         */
28867  #define R_SCI_B0_MSR_RSYNC_Msk          (0x40UL)       /*!< RSYNC (Bitfield-Mask: 0x01)                           */
28868 /* =========================================================  XSR0  ========================================================== */
28869  #define R_SCI_B0_XSR0_SFSF_Pos          (0UL)          /*!< SFSF (Bit 0)                                          */
28870  #define R_SCI_B0_XSR0_SFSF_Msk          (0x1UL)        /*!< SFSF (Bitfield-Mask: 0x01)                            */
28871  #define R_SCI_B0_XSR0_RXDSF_Pos         (1UL)          /*!< RXDSF (Bit 1)                                         */
28872  #define R_SCI_B0_XSR0_RXDSF_Msk         (0x2UL)        /*!< RXDSF (Bitfield-Mask: 0x01)                           */
28873  #define R_SCI_B0_XSR0_BFOF_Pos          (8UL)          /*!< BFOF (Bit 8)                                          */
28874  #define R_SCI_B0_XSR0_BFOF_Msk          (0x100UL)      /*!< BFOF (Bitfield-Mask: 0x01)                            */
28875  #define R_SCI_B0_XSR0_BCDF_Pos          (9UL)          /*!< BCDF (Bit 9)                                          */
28876  #define R_SCI_B0_XSR0_BCDF_Msk          (0x200UL)      /*!< BCDF (Bitfield-Mask: 0x01)                            */
28877  #define R_SCI_B0_XSR0_BFDF_Pos          (10UL)         /*!< BFDF (Bit 10)                                         */
28878  #define R_SCI_B0_XSR0_BFDF_Msk          (0x400UL)      /*!< BFDF (Bitfield-Mask: 0x01)                            */
28879  #define R_SCI_B0_XSR0_CF0MF_Pos         (11UL)         /*!< CF0MF (Bit 11)                                        */
28880  #define R_SCI_B0_XSR0_CF0MF_Msk         (0x800UL)      /*!< CF0MF (Bitfield-Mask: 0x01)                           */
28881  #define R_SCI_B0_XSR0_CF1MF_Pos         (12UL)         /*!< CF1MF (Bit 12)                                        */
28882  #define R_SCI_B0_XSR0_CF1MF_Msk         (0x1000UL)     /*!< CF1MF (Bitfield-Mask: 0x01)                           */
28883  #define R_SCI_B0_XSR0_PIBDF_Pos         (13UL)         /*!< PIBDF (Bit 13)                                        */
28884  #define R_SCI_B0_XSR0_PIBDF_Msk         (0x2000UL)     /*!< PIBDF (Bitfield-Mask: 0x01)                           */
28885  #define R_SCI_B0_XSR0_COF_Pos           (14UL)         /*!< COF (Bit 14)                                          */
28886  #define R_SCI_B0_XSR0_COF_Msk           (0x4000UL)     /*!< COF (Bitfield-Mask: 0x01)                             */
28887  #define R_SCI_B0_XSR0_AEDF_Pos          (15UL)         /*!< AEDF (Bit 15)                                         */
28888  #define R_SCI_B0_XSR0_AEDF_Msk          (0x8000UL)     /*!< AEDF (Bitfield-Mask: 0x01)                            */
28889  #define R_SCI_B0_XSR0_CF0RD_Pos         (16UL)         /*!< CF0RD (Bit 16)                                        */
28890  #define R_SCI_B0_XSR0_CF0RD_Msk         (0xff0000UL)   /*!< CF0RD (Bitfield-Mask: 0xff)                           */
28891  #define R_SCI_B0_XSR0_CF1RD_Pos         (24UL)         /*!< CF1RD (Bit 24)                                        */
28892  #define R_SCI_B0_XSR0_CF1RD_Msk         (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff)                           */
28893 /* =========================================================  XSR1  ========================================================== */
28894  #define R_SCI_B0_XSR1_TCNT_Pos          (0UL)          /*!< TCNT (Bit 0)                                          */
28895  #define R_SCI_B0_XSR1_TCNT_Msk          (0xffffUL)     /*!< TCNT (Bitfield-Mask: 0xffff)                          */
28896 /* =========================================================  CFCLR  ========================================================= */
28897  #define R_SCI_B0_CFCLR_ERSC_Pos         (4UL)          /*!< ERSC (Bit 4)                                          */
28898  #define R_SCI_B0_CFCLR_ERSC_Msk         (0x10UL)       /*!< ERSC (Bitfield-Mask: 0x01)                            */
28899  #define R_SCI_B0_CFCLR_DCMFC_Pos        (16UL)         /*!< DCMFC (Bit 16)                                        */
28900  #define R_SCI_B0_CFCLR_DCMFC_Msk        (0x10000UL)    /*!< DCMFC (Bitfield-Mask: 0x01)                           */
28901  #define R_SCI_B0_CFCLR_DPERC_Pos        (17UL)         /*!< DPERC (Bit 17)                                        */
28902  #define R_SCI_B0_CFCLR_DPERC_Msk        (0x20000UL)    /*!< DPERC (Bitfield-Mask: 0x01)                           */
28903  #define R_SCI_B0_CFCLR_DFERC_Pos        (18UL)         /*!< DFERC (Bit 18)                                        */
28904  #define R_SCI_B0_CFCLR_DFERC_Msk        (0x40000UL)    /*!< DFERC (Bitfield-Mask: 0x01)                           */
28905  #define R_SCI_B0_CFCLR_ORERC_Pos        (24UL)         /*!< ORERC (Bit 24)                                        */
28906  #define R_SCI_B0_CFCLR_ORERC_Msk        (0x1000000UL)  /*!< ORERC (Bitfield-Mask: 0x01)                           */
28907  #define R_SCI_B0_CFCLR_MFFC_Pos         (26UL)         /*!< MFFC (Bit 26)                                         */
28908  #define R_SCI_B0_CFCLR_MFFC_Msk         (0x4000000UL)  /*!< MFFC (Bitfield-Mask: 0x01)                            */
28909  #define R_SCI_B0_CFCLR_PERC_Pos         (27UL)         /*!< PERC (Bit 27)                                         */
28910  #define R_SCI_B0_CFCLR_PERC_Msk         (0x8000000UL)  /*!< PERC (Bitfield-Mask: 0x01)                            */
28911  #define R_SCI_B0_CFCLR_FERC_Pos         (28UL)         /*!< FERC (Bit 28)                                         */
28912  #define R_SCI_B0_CFCLR_FERC_Msk         (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01)                            */
28913  #define R_SCI_B0_CFCLR_TDREC_Pos        (29UL)         /*!< TDREC (Bit 29)                                        */
28914  #define R_SCI_B0_CFCLR_TDREC_Msk        (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01)                           */
28915  #define R_SCI_B0_CFCLR_RDRFC_Pos        (31UL)         /*!< RDRFC (Bit 31)                                        */
28916  #define R_SCI_B0_CFCLR_RDRFC_Msk        (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01)                           */
28917 /* ========================================================  ICFCLR  ========================================================= */
28918  #define R_SCI_B0_ICFCLR_IICSTIFC_Pos    (3UL)          /*!< IICSTIFC (Bit 3)                                      */
28919  #define R_SCI_B0_ICFCLR_IICSTIFC_Msk    (0x8UL)        /*!< IICSTIFC (Bitfield-Mask: 0x01)                        */
28920 /* =========================================================  FFCLR  ========================================================= */
28921  #define R_SCI_B0_FFCLR_DRC_Pos          (0UL)          /*!< DRC (Bit 0)                                           */
28922  #define R_SCI_B0_FFCLR_DRC_Msk          (0x1UL)        /*!< DRC (Bitfield-Mask: 0x01)                             */
28923 /* =========================================================  MFCLR  ========================================================= */
28924  #define R_SCI_B0_MFCLR_PFERC_Pos        (0UL)          /*!< PFERC (Bit 0)                                         */
28925  #define R_SCI_B0_MFCLR_PFERC_Msk        (0x1UL)        /*!< PFERC (Bitfield-Mask: 0x01)                           */
28926  #define R_SCI_B0_MFCLR_SYERC_Pos        (1UL)          /*!< SYERC (Bit 1)                                         */
28927  #define R_SCI_B0_MFCLR_SYERC_Msk        (0x2UL)        /*!< SYERC (Bitfield-Mask: 0x01)                           */
28928  #define R_SCI_B0_MFCLR_SBERC_Pos        (2UL)          /*!< SBERC (Bit 2)                                         */
28929  #define R_SCI_B0_MFCLR_SBERC_Msk        (0x4UL)        /*!< SBERC (Bitfield-Mask: 0x01)                           */
28930  #define R_SCI_B0_MFCLR_MERC_Pos         (4UL)          /*!< MERC (Bit 4)                                          */
28931  #define R_SCI_B0_MFCLR_MERC_Msk         (0x10UL)       /*!< MERC (Bitfield-Mask: 0x01)                            */
28932 /* =========================================================  XFCLR  ========================================================= */
28933  #define R_SCI_B0_XFCLR_BFOC_Pos         (8UL)          /*!< BFOC (Bit 8)                                          */
28934  #define R_SCI_B0_XFCLR_BFOC_Msk         (0x100UL)      /*!< BFOC (Bitfield-Mask: 0x01)                            */
28935  #define R_SCI_B0_XFCLR_BCDC_Pos         (9UL)          /*!< BCDC (Bit 9)                                          */
28936  #define R_SCI_B0_XFCLR_BCDC_Msk         (0x200UL)      /*!< BCDC (Bitfield-Mask: 0x01)                            */
28937  #define R_SCI_B0_XFCLR_BFDC_Pos         (10UL)         /*!< BFDC (Bit 10)                                         */
28938  #define R_SCI_B0_XFCLR_BFDC_Msk         (0x400UL)      /*!< BFDC (Bitfield-Mask: 0x01)                            */
28939  #define R_SCI_B0_XFCLR_CF0MC_Pos        (11UL)         /*!< CF0MC (Bit 11)                                        */
28940  #define R_SCI_B0_XFCLR_CF0MC_Msk        (0x800UL)      /*!< CF0MC (Bitfield-Mask: 0x01)                           */
28941  #define R_SCI_B0_XFCLR_CF1MC_Pos        (12UL)         /*!< CF1MC (Bit 12)                                        */
28942  #define R_SCI_B0_XFCLR_CF1MC_Msk        (0x1000UL)     /*!< CF1MC (Bitfield-Mask: 0x01)                           */
28943  #define R_SCI_B0_XFCLR_PIBDC_Pos        (13UL)         /*!< PIBDC (Bit 13)                                        */
28944  #define R_SCI_B0_XFCLR_PIBDC_Msk        (0x2000UL)     /*!< PIBDC (Bitfield-Mask: 0x01)                           */
28945  #define R_SCI_B0_XFCLR_COFC_Pos         (14UL)         /*!< COFC (Bit 14)                                         */
28946  #define R_SCI_B0_XFCLR_COFC_Msk         (0x4000UL)     /*!< COFC (Bitfield-Mask: 0x01)                            */
28947  #define R_SCI_B0_XFCLR_AEDC_Pos         (15UL)         /*!< AEDC (Bit 15)                                         */
28948  #define R_SCI_B0_XFCLR_AEDC_Msk         (0x8000UL)     /*!< AEDC (Bitfield-Mask: 0x01)                            */
28949 
28950 /* =========================================================================================================================== */
28951 /* ================                                         R_SPI_B0                                          ================ */
28952 /* =========================================================================================================================== */
28953 
28954 /* =========================================================  SPDR  ========================================================== */
28955 /* ========================================================  SPDECR  ========================================================= */
28956  #define R_SPI_B0_SPDECR_SCKDL_Pos     (0UL)          /*!< SCKDL (Bit 0)                                         */
28957  #define R_SPI_B0_SPDECR_SCKDL_Msk     (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
28958  #define R_SPI_B0_SPDECR_SLNDL_Pos     (8UL)          /*!< SLNDL (Bit 8)                                         */
28959  #define R_SPI_B0_SPDECR_SLNDL_Msk     (0x700UL)      /*!< SLNDL (Bitfield-Mask: 0x07)                           */
28960  #define R_SPI_B0_SPDECR_SPNDL_Pos     (16UL)         /*!< SPNDL (Bit 16)                                        */
28961  #define R_SPI_B0_SPDECR_SPNDL_Msk     (0x70000UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
28962  #define R_SPI_B0_SPDECR_ARST_Pos      (24UL)         /*!< ARST (Bit 24)                                         */
28963  #define R_SPI_B0_SPDECR_ARST_Msk      (0x7000000UL)  /*!< ARST (Bitfield-Mask: 0x07)                            */
28964 /* =========================================================  SPCR  ========================================================== */
28965  #define R_SPI_B0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
28966  #define R_SPI_B0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
28967  #define R_SPI_B0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
28968  #define R_SPI_B0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
28969  #define R_SPI_B0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
28970  #define R_SPI_B0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
28971  #define R_SPI_B0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
28972  #define R_SPI_B0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
28973  #define R_SPI_B0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
28974  #define R_SPI_B0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
28975  #define R_SPI_B0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
28976  #define R_SPI_B0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
28977  #define R_SPI_B0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
28978  #define R_SPI_B0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
28979  #define R_SPI_B0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
28980  #define R_SPI_B0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
28981  #define R_SPI_B0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
28982  #define R_SPI_B0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
28983  #define R_SPI_B0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
28984  #define R_SPI_B0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
28985  #define R_SPI_B0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
28986  #define R_SPI_B0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
28987  #define R_SPI_B0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
28988  #define R_SPI_B0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
28989  #define R_SPI_B0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
28990  #define R_SPI_B0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
28991  #define R_SPI_B0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
28992  #define R_SPI_B0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
28993  #define R_SPI_B0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
28994  #define R_SPI_B0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
28995  #define R_SPI_B0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
28996  #define R_SPI_B0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
28997  #define R_SPI_B0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
28998  #define R_SPI_B0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
28999  #define R_SPI_B0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
29000  #define R_SPI_B0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
29001  #define R_SPI_B0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
29002  #define R_SPI_B0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
29003 /* =========================================================  SPCR2  ========================================================= */
29004  #define R_SPI_B0_SPCR2_RMFM_Pos       (0UL)          /*!< RMFM (Bit 0)                                          */
29005  #define R_SPI_B0_SPCR2_RMFM_Msk       (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
29006  #define R_SPI_B0_SPCR2_RMEDTG_Pos     (6UL)          /*!< RMEDTG (Bit 6)                                        */
29007  #define R_SPI_B0_SPCR2_RMEDTG_Msk     (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
29008  #define R_SPI_B0_SPCR2_RMSTTG_Pos     (7UL)          /*!< RMSTTG (Bit 7)                                        */
29009  #define R_SPI_B0_SPCR2_RMSTTG_Msk     (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
29010  #define R_SPI_B0_SPCR2_SPDRC_Pos      (8UL)          /*!< SPDRC (Bit 8)                                         */
29011  #define R_SPI_B0_SPCR2_SPDRC_Msk      (0xff00UL)     /*!< SPDRC (Bitfield-Mask: 0xff)                           */
29012  #define R_SPI_B0_SPCR2_SPLP_Pos       (16UL)         /*!< SPLP (Bit 16)                                         */
29013  #define R_SPI_B0_SPCR2_SPLP_Msk       (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
29014  #define R_SPI_B0_SPCR2_SPLP2_Pos      (17UL)         /*!< SPLP2 (Bit 17)                                        */
29015  #define R_SPI_B0_SPCR2_SPLP2_Msk      (0x20000UL)    /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
29016  #define R_SPI_B0_SPCR2_MOIFV_Pos      (20UL)         /*!< MOIFV (Bit 20)                                        */
29017  #define R_SPI_B0_SPCR2_MOIFV_Msk      (0x100000UL)   /*!< MOIFV (Bitfield-Mask: 0x01)                           */
29018  #define R_SPI_B0_SPCR2_MOIFE_Pos      (21UL)         /*!< MOIFE (Bit 21)                                        */
29019  #define R_SPI_B0_SPCR2_MOIFE_Msk      (0x200000UL)   /*!< MOIFE (Bitfield-Mask: 0x01)                           */
29020 /* =========================================================  SPCR3  ========================================================= */
29021  #define R_SPI_B0_SPCR3_SSL0P_Pos      (0UL)          /*!< SSL0P (Bit 0)                                         */
29022  #define R_SPI_B0_SPCR3_SSL0P_Msk      (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
29023  #define R_SPI_B0_SPCR3_SSL1P_Pos      (1UL)          /*!< SSL1P (Bit 1)                                         */
29024  #define R_SPI_B0_SPCR3_SSL1P_Msk      (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
29025  #define R_SPI_B0_SPCR3_SSL2P_Pos      (2UL)          /*!< SSL2P (Bit 2)                                         */
29026  #define R_SPI_B0_SPCR3_SSL2P_Msk      (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
29027  #define R_SPI_B0_SPCR3_SSL3P_Pos      (3UL)          /*!< SSL3P (Bit 3)                                         */
29028  #define R_SPI_B0_SPCR3_SSL3P_Msk      (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
29029  #define R_SPI_B0_SPCR3_SPBR_Pos       (8UL)          /*!< SPBR (Bit 8)                                          */
29030  #define R_SPI_B0_SPCR3_SPBR_Msk       (0xff00UL)     /*!< SPBR (Bitfield-Mask: 0xff)                            */
29031  #define R_SPI_B0_SPCR3_SPSLN_Pos      (24UL)         /*!< SPSLN (Bit 24)                                        */
29032  #define R_SPI_B0_SPCR3_SPSLN_Msk      (0x7000000UL)  /*!< SPSLN (Bitfield-Mask: 0x07)                           */
29033 /* ========================================================  SPCMD0  ========================================================= */
29034  #define R_SPI_B0_SPCMD0_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29035  #define R_SPI_B0_SPCMD0_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29036  #define R_SPI_B0_SPCMD0_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29037  #define R_SPI_B0_SPCMD0_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29038  #define R_SPI_B0_SPCMD0_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29039  #define R_SPI_B0_SPCMD0_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29040  #define R_SPI_B0_SPCMD0_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29041  #define R_SPI_B0_SPCMD0_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29042  #define R_SPI_B0_SPCMD0_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29043  #define R_SPI_B0_SPCMD0_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29044  #define R_SPI_B0_SPCMD0_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29045  #define R_SPI_B0_SPCMD0_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29046  #define R_SPI_B0_SPCMD0_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29047  #define R_SPI_B0_SPCMD0_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29048  #define R_SPI_B0_SPCMD0_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29049  #define R_SPI_B0_SPCMD0_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29050  #define R_SPI_B0_SPCMD0_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29051  #define R_SPI_B0_SPCMD0_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29052  #define R_SPI_B0_SPCMD0_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29053  #define R_SPI_B0_SPCMD0_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29054 /* ========================================================  SPCMD1  ========================================================= */
29055  #define R_SPI_B0_SPCMD1_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29056  #define R_SPI_B0_SPCMD1_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29057  #define R_SPI_B0_SPCMD1_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29058  #define R_SPI_B0_SPCMD1_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29059  #define R_SPI_B0_SPCMD1_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29060  #define R_SPI_B0_SPCMD1_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29061  #define R_SPI_B0_SPCMD1_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29062  #define R_SPI_B0_SPCMD1_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29063  #define R_SPI_B0_SPCMD1_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29064  #define R_SPI_B0_SPCMD1_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29065  #define R_SPI_B0_SPCMD1_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29066  #define R_SPI_B0_SPCMD1_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29067  #define R_SPI_B0_SPCMD1_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29068  #define R_SPI_B0_SPCMD1_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29069  #define R_SPI_B0_SPCMD1_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29070  #define R_SPI_B0_SPCMD1_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29071  #define R_SPI_B0_SPCMD1_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29072  #define R_SPI_B0_SPCMD1_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29073  #define R_SPI_B0_SPCMD1_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29074  #define R_SPI_B0_SPCMD1_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29075 /* ========================================================  SPCMD2  ========================================================= */
29076  #define R_SPI_B0_SPCMD2_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29077  #define R_SPI_B0_SPCMD2_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29078  #define R_SPI_B0_SPCMD2_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29079  #define R_SPI_B0_SPCMD2_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29080  #define R_SPI_B0_SPCMD2_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29081  #define R_SPI_B0_SPCMD2_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29082  #define R_SPI_B0_SPCMD2_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29083  #define R_SPI_B0_SPCMD2_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29084  #define R_SPI_B0_SPCMD2_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29085  #define R_SPI_B0_SPCMD2_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29086  #define R_SPI_B0_SPCMD2_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29087  #define R_SPI_B0_SPCMD2_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29088  #define R_SPI_B0_SPCMD2_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29089  #define R_SPI_B0_SPCMD2_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29090  #define R_SPI_B0_SPCMD2_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29091  #define R_SPI_B0_SPCMD2_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29092  #define R_SPI_B0_SPCMD2_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29093  #define R_SPI_B0_SPCMD2_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29094  #define R_SPI_B0_SPCMD2_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29095  #define R_SPI_B0_SPCMD2_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29096 /* ========================================================  SPCMD3  ========================================================= */
29097  #define R_SPI_B0_SPCMD3_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29098  #define R_SPI_B0_SPCMD3_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29099  #define R_SPI_B0_SPCMD3_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29100  #define R_SPI_B0_SPCMD3_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29101  #define R_SPI_B0_SPCMD3_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29102  #define R_SPI_B0_SPCMD3_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29103  #define R_SPI_B0_SPCMD3_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29104  #define R_SPI_B0_SPCMD3_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29105  #define R_SPI_B0_SPCMD3_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29106  #define R_SPI_B0_SPCMD3_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29107  #define R_SPI_B0_SPCMD3_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29108  #define R_SPI_B0_SPCMD3_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29109  #define R_SPI_B0_SPCMD3_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29110  #define R_SPI_B0_SPCMD3_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29111  #define R_SPI_B0_SPCMD3_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29112  #define R_SPI_B0_SPCMD3_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29113  #define R_SPI_B0_SPCMD3_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29114  #define R_SPI_B0_SPCMD3_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29115  #define R_SPI_B0_SPCMD3_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29116  #define R_SPI_B0_SPCMD3_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29117 /* ========================================================  SPCMD4  ========================================================= */
29118  #define R_SPI_B0_SPCMD4_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29119  #define R_SPI_B0_SPCMD4_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29120  #define R_SPI_B0_SPCMD4_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29121  #define R_SPI_B0_SPCMD4_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29122  #define R_SPI_B0_SPCMD4_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29123  #define R_SPI_B0_SPCMD4_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29124  #define R_SPI_B0_SPCMD4_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29125  #define R_SPI_B0_SPCMD4_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29126  #define R_SPI_B0_SPCMD4_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29127  #define R_SPI_B0_SPCMD4_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29128  #define R_SPI_B0_SPCMD4_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29129  #define R_SPI_B0_SPCMD4_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29130  #define R_SPI_B0_SPCMD4_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29131  #define R_SPI_B0_SPCMD4_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29132  #define R_SPI_B0_SPCMD4_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29133  #define R_SPI_B0_SPCMD4_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29134  #define R_SPI_B0_SPCMD4_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29135  #define R_SPI_B0_SPCMD4_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29136  #define R_SPI_B0_SPCMD4_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29137  #define R_SPI_B0_SPCMD4_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29138 /* ========================================================  SPCMD5  ========================================================= */
29139  #define R_SPI_B0_SPCMD5_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29140  #define R_SPI_B0_SPCMD5_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29141  #define R_SPI_B0_SPCMD5_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29142  #define R_SPI_B0_SPCMD5_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29143  #define R_SPI_B0_SPCMD5_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29144  #define R_SPI_B0_SPCMD5_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29145  #define R_SPI_B0_SPCMD5_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29146  #define R_SPI_B0_SPCMD5_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29147  #define R_SPI_B0_SPCMD5_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29148  #define R_SPI_B0_SPCMD5_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29149  #define R_SPI_B0_SPCMD5_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29150  #define R_SPI_B0_SPCMD5_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29151  #define R_SPI_B0_SPCMD5_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29152  #define R_SPI_B0_SPCMD5_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29153  #define R_SPI_B0_SPCMD5_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29154  #define R_SPI_B0_SPCMD5_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29155  #define R_SPI_B0_SPCMD5_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29156  #define R_SPI_B0_SPCMD5_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29157  #define R_SPI_B0_SPCMD5_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29158  #define R_SPI_B0_SPCMD5_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29159 /* ========================================================  SPCMD6  ========================================================= */
29160  #define R_SPI_B0_SPCMD6_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29161  #define R_SPI_B0_SPCMD6_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29162  #define R_SPI_B0_SPCMD6_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29163  #define R_SPI_B0_SPCMD6_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29164  #define R_SPI_B0_SPCMD6_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29165  #define R_SPI_B0_SPCMD6_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29166  #define R_SPI_B0_SPCMD6_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29167  #define R_SPI_B0_SPCMD6_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29168  #define R_SPI_B0_SPCMD6_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29169  #define R_SPI_B0_SPCMD6_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29170  #define R_SPI_B0_SPCMD6_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29171  #define R_SPI_B0_SPCMD6_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29172  #define R_SPI_B0_SPCMD6_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29173  #define R_SPI_B0_SPCMD6_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29174  #define R_SPI_B0_SPCMD6_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29175  #define R_SPI_B0_SPCMD6_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29176  #define R_SPI_B0_SPCMD6_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29177  #define R_SPI_B0_SPCMD6_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29178  #define R_SPI_B0_SPCMD6_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29179  #define R_SPI_B0_SPCMD6_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29180 /* ========================================================  SPCMD7  ========================================================= */
29181  #define R_SPI_B0_SPCMD7_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
29182  #define R_SPI_B0_SPCMD7_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
29183  #define R_SPI_B0_SPCMD7_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
29184  #define R_SPI_B0_SPCMD7_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
29185  #define R_SPI_B0_SPCMD7_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
29186  #define R_SPI_B0_SPCMD7_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
29187  #define R_SPI_B0_SPCMD7_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
29188  #define R_SPI_B0_SPCMD7_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
29189  #define R_SPI_B0_SPCMD7_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
29190  #define R_SPI_B0_SPCMD7_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
29191  #define R_SPI_B0_SPCMD7_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
29192  #define R_SPI_B0_SPCMD7_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
29193  #define R_SPI_B0_SPCMD7_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
29194  #define R_SPI_B0_SPCMD7_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
29195  #define R_SPI_B0_SPCMD7_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
29196  #define R_SPI_B0_SPCMD7_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
29197  #define R_SPI_B0_SPCMD7_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
29198  #define R_SPI_B0_SPCMD7_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
29199  #define R_SPI_B0_SPCMD7_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
29200  #define R_SPI_B0_SPCMD7_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
29201 /* =========================================================  SPDCR  ========================================================= */
29202  #define R_SPI_B0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
29203  #define R_SPI_B0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
29204  #define R_SPI_B0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
29205  #define R_SPI_B0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
29206  #define R_SPI_B0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
29207  #define R_SPI_B0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
29208  #define R_SPI_B0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
29209  #define R_SPI_B0_SPDCR_SPFC_Msk       (0x300UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
29210 /* ========================================================  SPDCR2  ========================================================= */
29211  #define R_SPI_B0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
29212  #define R_SPI_B0_SPDCR2_RTRG_Msk      (0x3UL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
29213  #define R_SPI_B0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
29214  #define R_SPI_B0_SPDCR2_TTRG_Msk      (0x300UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
29215 /* =========================================================  SPSR  ========================================================== */
29216  #define R_SPI_B0_SPSR_SPCP_Pos        (8UL)          /*!< SPCP (Bit 8)                                          */
29217  #define R_SPI_B0_SPSR_SPCP_Msk        (0x700UL)      /*!< SPCP (Bitfield-Mask: 0x07)                            */
29218  #define R_SPI_B0_SPSR_SPECM_Pos       (12UL)         /*!< SPECM (Bit 12)                                        */
29219  #define R_SPI_B0_SPSR_SPECM_Msk       (0x7000UL)     /*!< SPECM (Bitfield-Mask: 0x07)                           */
29220  #define R_SPI_B0_SPSR_SPDRF_Pos       (23UL)         /*!< SPDRF (Bit 23)                                        */
29221  #define R_SPI_B0_SPSR_SPDRF_Msk       (0x800000UL)   /*!< SPDRF (Bitfield-Mask: 0x01)                           */
29222  #define R_SPI_B0_SPSR_OVRF_Pos        (24UL)         /*!< OVRF (Bit 24)                                         */
29223  #define R_SPI_B0_SPSR_OVRF_Msk        (0x1000000UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
29224  #define R_SPI_B0_SPSR_IDLNF_Pos       (25UL)         /*!< IDLNF (Bit 25)                                        */
29225  #define R_SPI_B0_SPSR_IDLNF_Msk       (0x2000000UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
29226  #define R_SPI_B0_SPSR_MODF_Pos        (26UL)         /*!< MODF (Bit 26)                                         */
29227  #define R_SPI_B0_SPSR_MODF_Msk        (0x4000000UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
29228  #define R_SPI_B0_SPSR_PERF_Pos        (27UL)         /*!< PERF (Bit 27)                                         */
29229  #define R_SPI_B0_SPSR_PERF_Msk        (0x8000000UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
29230  #define R_SPI_B0_SPSR_UDRF_Pos        (28UL)         /*!< UDRF (Bit 28)                                         */
29231  #define R_SPI_B0_SPSR_UDRF_Msk        (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
29232  #define R_SPI_B0_SPSR_SPTEF_Pos       (29UL)         /*!< SPTEF (Bit 29)                                        */
29233  #define R_SPI_B0_SPSR_SPTEF_Msk       (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
29234  #define R_SPI_B0_SPSR_CENDF_Pos       (30UL)         /*!< CENDF (Bit 30)                                        */
29235  #define R_SPI_B0_SPSR_CENDF_Msk       (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
29236  #define R_SPI_B0_SPSR_SPRF_Pos        (31UL)         /*!< SPRF (Bit 31)                                         */
29237  #define R_SPI_B0_SPSR_SPRF_Msk        (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
29238 /* ========================================================  SPTFSR  ========================================================= */
29239  #define R_SPI_B0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
29240  #define R_SPI_B0_SPTFSR_TFDN_Msk      (0x7UL)        /*!< TFDN (Bitfield-Mask: 0x07)                            */
29241 /* ========================================================  SPRFSR  ========================================================= */
29242  #define R_SPI_B0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
29243  #define R_SPI_B0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
29244 /* =========================================================  SPPSR  ========================================================= */
29245  #define R_SPI_B0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
29246  #define R_SPI_B0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
29247 /* =========================================================  SPSRC  ========================================================= */
29248  #define R_SPI_B0_SPSRC_SPDRFC_Pos     (23UL)         /*!< SPDRFC (Bit 23)                                       */
29249  #define R_SPI_B0_SPSRC_SPDRFC_Msk     (0x800000UL)   /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
29250  #define R_SPI_B0_SPSRC_OVRFC_Pos      (24UL)         /*!< OVRFC (Bit 24)                                        */
29251  #define R_SPI_B0_SPSRC_OVRFC_Msk      (0x1000000UL)  /*!< OVRFC (Bitfield-Mask: 0x01)                           */
29252  #define R_SPI_B0_SPSRC_MODFC_Pos      (26UL)         /*!< MODFC (Bit 26)                                        */
29253  #define R_SPI_B0_SPSRC_MODFC_Msk      (0x4000000UL)  /*!< MODFC (Bitfield-Mask: 0x01)                           */
29254  #define R_SPI_B0_SPSRC_PERFC_Pos      (27UL)         /*!< PERFC (Bit 27)                                        */
29255  #define R_SPI_B0_SPSRC_PERFC_Msk      (0x8000000UL)  /*!< PERFC (Bitfield-Mask: 0x01)                           */
29256  #define R_SPI_B0_SPSRC_UDRFC_Pos      (28UL)         /*!< UDRFC (Bit 28)                                        */
29257  #define R_SPI_B0_SPSRC_UDRFC_Msk      (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01)                           */
29258  #define R_SPI_B0_SPSRC_SPTEFC_Pos     (29UL)         /*!< SPTEFC (Bit 29)                                       */
29259  #define R_SPI_B0_SPSRC_SPTEFC_Msk     (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
29260  #define R_SPI_B0_SPSRC_CENDFC_Pos     (30UL)         /*!< CENDFC (Bit 30)                                       */
29261  #define R_SPI_B0_SPSRC_CENDFC_Msk     (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01)                          */
29262  #define R_SPI_B0_SPSRC_SPRFC_Pos      (31UL)         /*!< SPRFC (Bit 31)                                        */
29263  #define R_SPI_B0_SPSRC_SPRFC_Msk      (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01)                           */
29264 /* =========================================================  SPFCR  ========================================================= */
29265  #define R_SPI_B0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
29266  #define R_SPI_B0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */
29267 
29268 /* =========================================================================================================================== */
29269 /* ================                                          R_XSPI                                           ================ */
29270 /* =========================================================================================================================== */
29271 
29272 /* ========================================================  WRAPCFG  ======================================================== */
29273  #define R_XSPI_WRAPCFG_CKSFTCS0_Pos      (0UL)          /*!< CKSFTCS0 (Bit 0)                                      */
29274  #define R_XSPI_WRAPCFG_CKSFTCS0_Msk      (0x1fUL)       /*!< CKSFTCS0 (Bitfield-Mask: 0x1f)                        */
29275  #define R_XSPI_WRAPCFG_DSSFTCS0_Pos      (8UL)          /*!< DSSFTCS0 (Bit 8)                                      */
29276  #define R_XSPI_WRAPCFG_DSSFTCS0_Msk      (0x1f00UL)     /*!< DSSFTCS0 (Bitfield-Mask: 0x1f)                        */
29277  #define R_XSPI_WRAPCFG_CKSFTCS1_Pos      (16UL)         /*!< CKSFTCS1 (Bit 16)                                     */
29278  #define R_XSPI_WRAPCFG_CKSFTCS1_Msk      (0x1f0000UL)   /*!< CKSFTCS1 (Bitfield-Mask: 0x1f)                        */
29279  #define R_XSPI_WRAPCFG_DSSFTCS1_Pos      (24UL)         /*!< DSSFTCS1 (Bit 24)                                     */
29280  #define R_XSPI_WRAPCFG_DSSFTCS1_Msk      (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f)                        */
29281 /* ========================================================  COMCFG  ========================================================= */
29282  #define R_XSPI_COMCFG_ARBMD_Pos          (0UL)          /*!< ARBMD (Bit 0)                                         */
29283  #define R_XSPI_COMCFG_ARBMD_Msk          (0x3UL)        /*!< ARBMD (Bitfield-Mask: 0x03)                           */
29284  #define R_XSPI_COMCFG_ECSINTOUTEN_Pos    (4UL)          /*!< ECSINTOUTEN (Bit 4)                                   */
29285  #define R_XSPI_COMCFG_ECSINTOUTEN_Msk    (0x30UL)       /*!< ECSINTOUTEN (Bitfield-Mask: 0x03)                     */
29286  #define R_XSPI_COMCFG_OEASTEX_Pos        (16UL)         /*!< OEASTEX (Bit 16)                                      */
29287  #define R_XSPI_COMCFG_OEASTEX_Msk        (0x10000UL)    /*!< OEASTEX (Bitfield-Mask: 0x01)                         */
29288  #define R_XSPI_COMCFG_OENEGEX_Pos        (17UL)         /*!< OENEGEX (Bit 17)                                      */
29289  #define R_XSPI_COMCFG_OENEGEX_Msk        (0x20000UL)    /*!< OENEGEX (Bitfield-Mask: 0x01)                         */
29290 /* ========================================================  BMCFGCH  ======================================================== */
29291  #define R_XSPI_BMCFGCH_WRMD_Pos          (0UL)          /*!< WRMD (Bit 0)                                          */
29292  #define R_XSPI_BMCFGCH_WRMD_Msk          (0x1UL)        /*!< WRMD (Bitfield-Mask: 0x01)                            */
29293  #define R_XSPI_BMCFGCH_MWRCOMB_Pos       (7UL)          /*!< MWRCOMB (Bit 7)                                       */
29294  #define R_XSPI_BMCFGCH_MWRCOMB_Msk       (0x80UL)       /*!< MWRCOMB (Bitfield-Mask: 0x01)                         */
29295  #define R_XSPI_BMCFGCH_MWRSIZE_Pos       (8UL)          /*!< MWRSIZE (Bit 8)                                       */
29296  #define R_XSPI_BMCFGCH_MWRSIZE_Msk       (0xff00UL)     /*!< MWRSIZE (Bitfield-Mask: 0xff)                         */
29297  #define R_XSPI_BMCFGCH_PREEN_Pos         (16UL)         /*!< PREEN (Bit 16)                                        */
29298  #define R_XSPI_BMCFGCH_PREEN_Msk         (0x10000UL)    /*!< PREEN (Bitfield-Mask: 0x01)                           */
29299  #define R_XSPI_BMCFGCH_CMBTIM_Pos        (24UL)         /*!< CMBTIM (Bit 24)                                       */
29300  #define R_XSPI_BMCFGCH_CMBTIM_Msk        (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff)                          */
29301 /* =======================================================  LIOCFGCS  ======================================================== */
29302  #define R_XSPI_LIOCFGCS_PRTMD_Pos        (0UL)          /*!< PRTMD (Bit 0)                                         */
29303  #define R_XSPI_LIOCFGCS_PRTMD_Msk        (0x3ffUL)      /*!< PRTMD (Bitfield-Mask: 0x3ff)                          */
29304  #define R_XSPI_LIOCFGCS_LATEMD_Pos       (10UL)         /*!< LATEMD (Bit 10)                                       */
29305  #define R_XSPI_LIOCFGCS_LATEMD_Msk       (0x400UL)      /*!< LATEMD (Bitfield-Mask: 0x01)                          */
29306  #define R_XSPI_LIOCFGCS_WRMSKMD_Pos      (11UL)         /*!< WRMSKMD (Bit 11)                                      */
29307  #define R_XSPI_LIOCFGCS_WRMSKMD_Msk      (0x800UL)      /*!< WRMSKMD (Bitfield-Mask: 0x01)                         */
29308  #define R_XSPI_LIOCFGCS_CSMIN_Pos        (16UL)         /*!< CSMIN (Bit 16)                                        */
29309  #define R_XSPI_LIOCFGCS_CSMIN_Msk        (0xf0000UL)    /*!< CSMIN (Bitfield-Mask: 0x0f)                           */
29310  #define R_XSPI_LIOCFGCS_CSASTEX_Pos      (20UL)         /*!< CSASTEX (Bit 20)                                      */
29311  #define R_XSPI_LIOCFGCS_CSASTEX_Msk      (0x100000UL)   /*!< CSASTEX (Bitfield-Mask: 0x01)                         */
29312  #define R_XSPI_LIOCFGCS_CSNEGEX_Pos      (21UL)         /*!< CSNEGEX (Bit 21)                                      */
29313  #define R_XSPI_LIOCFGCS_CSNEGEX_Msk      (0x200000UL)   /*!< CSNEGEX (Bitfield-Mask: 0x01)                         */
29314  #define R_XSPI_LIOCFGCS_SDRDRV_Pos       (22UL)         /*!< SDRDRV (Bit 22)                                       */
29315  #define R_XSPI_LIOCFGCS_SDRDRV_Msk       (0x400000UL)   /*!< SDRDRV (Bitfield-Mask: 0x01)                          */
29316  #define R_XSPI_LIOCFGCS_SDRSMPMD_Pos     (23UL)         /*!< SDRSMPMD (Bit 23)                                     */
29317  #define R_XSPI_LIOCFGCS_SDRSMPMD_Msk     (0x800000UL)   /*!< SDRSMPMD (Bitfield-Mask: 0x01)                        */
29318  #define R_XSPI_LIOCFGCS_SDRSMPSFT_Pos    (24UL)         /*!< SDRSMPSFT (Bit 24)                                    */
29319  #define R_XSPI_LIOCFGCS_SDRSMPSFT_Msk    (0xf000000UL)  /*!< SDRSMPSFT (Bitfield-Mask: 0x0f)                       */
29320  #define R_XSPI_LIOCFGCS_DDRSMPEX_Pos     (28UL)         /*!< DDRSMPEX (Bit 28)                                     */
29321  #define R_XSPI_LIOCFGCS_DDRSMPEX_Msk     (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f)                        */
29322 /* ========================================================  ABMCFG  ========================================================= */
29323  #define R_XSPI_ABMCFG_ODRMD_Pos          (0UL)          /*!< ODRMD (Bit 0)                                         */
29324  #define R_XSPI_ABMCFG_ODRMD_Msk          (0x3UL)        /*!< ODRMD (Bitfield-Mask: 0x03)                           */
29325  #define R_XSPI_ABMCFG_CHSEL_Pos          (16UL)         /*!< CHSEL (Bit 16)                                        */
29326  #define R_XSPI_ABMCFG_CHSEL_Msk          (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff)                         */
29327 /* ========================================================  BMCTL0  ========================================================= */
29328  #define R_XSPI_BMCTL0_CH0CS0ACC_Pos      (0UL)          /*!< CH0CS0ACC (Bit 0)                                     */
29329  #define R_XSPI_BMCTL0_CH0CS0ACC_Msk      (0x3UL)        /*!< CH0CS0ACC (Bitfield-Mask: 0x03)                       */
29330  #define R_XSPI_BMCTL0_CH0CS1ACC_Pos      (2UL)          /*!< CH0CS1ACC (Bit 2)                                     */
29331  #define R_XSPI_BMCTL0_CH0CS1ACC_Msk      (0xcUL)        /*!< CH0CS1ACC (Bitfield-Mask: 0x03)                       */
29332  #define R_XSPI_BMCTL0_CH1CS0ACC_Pos      (4UL)          /*!< CH1CS0ACC (Bit 4)                                     */
29333  #define R_XSPI_BMCTL0_CH1CS0ACC_Msk      (0x30UL)       /*!< CH1CS0ACC (Bitfield-Mask: 0x03)                       */
29334  #define R_XSPI_BMCTL0_CH1CS1ACC_Pos      (6UL)          /*!< CH1CS1ACC (Bit 6)                                     */
29335  #define R_XSPI_BMCTL0_CH1CS1ACC_Msk      (0xc0UL)       /*!< CH1CS1ACC (Bitfield-Mask: 0x03)                       */
29336 /* ========================================================  BMCTL1  ========================================================= */
29337  #define R_XSPI_BMCTL1_MWRPUSHCH_Pos      (8UL)          /*!< MWRPUSHCH (Bit 8)                                     */
29338  #define R_XSPI_BMCTL1_MWRPUSHCH_Msk      (0x100UL)      /*!< MWRPUSHCH (Bitfield-Mask: 0x01)                       */
29339  #define R_XSPI_BMCTL1_PBUFCLRCH_Pos      (10UL)         /*!< PBUFCLRCH (Bit 10)                                    */
29340  #define R_XSPI_BMCTL1_PBUFCLRCH_Msk      (0x400UL)      /*!< PBUFCLRCH (Bitfield-Mask: 0x01)                       */
29341 /* ========================================================  CMCTLCH  ======================================================== */
29342  #define R_XSPI_CMCTLCH_XIPENCODE_Pos     (0UL)          /*!< XIPENCODE (Bit 0)                                     */
29343  #define R_XSPI_CMCTLCH_XIPENCODE_Msk     (0xffUL)       /*!< XIPENCODE (Bitfield-Mask: 0xff)                       */
29344  #define R_XSPI_CMCTLCH_XIPEXCODE_Pos     (8UL)          /*!< XIPEXCODE (Bit 8)                                     */
29345  #define R_XSPI_CMCTLCH_XIPEXCODE_Msk     (0xff00UL)     /*!< XIPEXCODE (Bitfield-Mask: 0xff)                       */
29346  #define R_XSPI_CMCTLCH_XIPEN_Pos         (16UL)         /*!< XIPEN (Bit 16)                                        */
29347  #define R_XSPI_CMCTLCH_XIPEN_Msk         (0x10000UL)    /*!< XIPEN (Bitfield-Mask: 0x01)                           */
29348 /* ========================================================  CDCTL0  ========================================================= */
29349  #define R_XSPI_CDCTL0_TRREQ_Pos          (0UL)          /*!< TRREQ (Bit 0)                                         */
29350  #define R_XSPI_CDCTL0_TRREQ_Msk          (0x1UL)        /*!< TRREQ (Bitfield-Mask: 0x01)                           */
29351  #define R_XSPI_CDCTL0_PERMD_Pos          (1UL)          /*!< PERMD (Bit 1)                                         */
29352  #define R_XSPI_CDCTL0_PERMD_Msk          (0x2UL)        /*!< PERMD (Bitfield-Mask: 0x01)                           */
29353  #define R_XSPI_CDCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
29354  #define R_XSPI_CDCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
29355  #define R_XSPI_CDCTL0_TRNUM_Pos          (4UL)          /*!< TRNUM (Bit 4)                                         */
29356  #define R_XSPI_CDCTL0_TRNUM_Msk          (0x30UL)       /*!< TRNUM (Bitfield-Mask: 0x03)                           */
29357  #define R_XSPI_CDCTL0_PERITV_Pos         (16UL)         /*!< PERITV (Bit 16)                                       */
29358  #define R_XSPI_CDCTL0_PERITV_Msk         (0x1f0000UL)   /*!< PERITV (Bitfield-Mask: 0x1f)                          */
29359  #define R_XSPI_CDCTL0_PERREP_Pos         (24UL)         /*!< PERREP (Bit 24)                                       */
29360  #define R_XSPI_CDCTL0_PERREP_Msk         (0xf000000UL)  /*!< PERREP (Bitfield-Mask: 0x0f)                          */
29361 /* ========================================================  CDCTL1  ========================================================= */
29362  #define R_XSPI_CDCTL1_PEREXP_Pos         (0UL)          /*!< PEREXP (Bit 0)                                        */
29363  #define R_XSPI_CDCTL1_PEREXP_Msk         (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff)                    */
29364 /* ========================================================  CDCTL2  ========================================================= */
29365  #define R_XSPI_CDCTL2_PERMSK_Pos         (0UL)          /*!< PERMSK (Bit 0)                                        */
29366  #define R_XSPI_CDCTL2_PERMSK_Msk         (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff)                    */
29367 /* ========================================================  LPCTL0  ========================================================= */
29368  #define R_XSPI_LPCTL0_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
29369  #define R_XSPI_LPCTL0_PATREQ_Msk         (0x1UL)        /*!< PATREQ (Bitfield-Mask: 0x01)                          */
29370  #define R_XSPI_LPCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
29371  #define R_XSPI_LPCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
29372  #define R_XSPI_LPCTL0_XDPIN_Pos          (4UL)          /*!< XDPIN (Bit 4)                                         */
29373  #define R_XSPI_LPCTL0_XDPIN_Msk          (0x30UL)       /*!< XDPIN (Bitfield-Mask: 0x03)                           */
29374  #define R_XSPI_LPCTL0_XD1LEN_Pos         (16UL)         /*!< XD1LEN (Bit 16)                                       */
29375  #define R_XSPI_LPCTL0_XD1LEN_Msk         (0x1f0000UL)   /*!< XD1LEN (Bitfield-Mask: 0x1f)                          */
29376  #define R_XSPI_LPCTL0_XD1VAL_Pos         (23UL)         /*!< XD1VAL (Bit 23)                                       */
29377  #define R_XSPI_LPCTL0_XD1VAL_Msk         (0x800000UL)   /*!< XD1VAL (Bitfield-Mask: 0x01)                          */
29378  #define R_XSPI_LPCTL0_XD2LEN_Pos         (24UL)         /*!< XD2LEN (Bit 24)                                       */
29379  #define R_XSPI_LPCTL0_XD2LEN_Msk         (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f)                          */
29380  #define R_XSPI_LPCTL0_XD2VAL_Pos         (31UL)         /*!< XD2VAL (Bit 31)                                       */
29381  #define R_XSPI_LPCTL0_XD2VAL_Msk         (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01)                          */
29382 /* ========================================================  LPCTL1  ========================================================= */
29383  #define R_XSPI_LPCTL1_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
29384  #define R_XSPI_LPCTL1_PATREQ_Msk         (0x3UL)        /*!< PATREQ (Bitfield-Mask: 0x03)                          */
29385  #define R_XSPI_LPCTL1_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
29386  #define R_XSPI_LPCTL1_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
29387  #define R_XSPI_LPCTL1_RSTREP_Pos         (4UL)          /*!< RSTREP (Bit 4)                                        */
29388  #define R_XSPI_LPCTL1_RSTREP_Msk         (0x30UL)       /*!< RSTREP (Bitfield-Mask: 0x03)                          */
29389  #define R_XSPI_LPCTL1_RSTWID_Pos         (8UL)          /*!< RSTWID (Bit 8)                                        */
29390  #define R_XSPI_LPCTL1_RSTWID_Msk         (0x700UL)      /*!< RSTWID (Bitfield-Mask: 0x07)                          */
29391  #define R_XSPI_LPCTL1_RSTSU_Pos          (12UL)         /*!< RSTSU (Bit 12)                                        */
29392  #define R_XSPI_LPCTL1_RSTSU_Msk          (0x7000UL)     /*!< RSTSU (Bitfield-Mask: 0x07)                           */
29393 /* ========================================================  LIOCTL  ========================================================= */
29394  #define R_XSPI_LIOCTL_WPCS_Pos           (0UL)          /*!< WPCS (Bit 0)                                          */
29395  #define R_XSPI_LIOCTL_WPCS_Msk           (0x1UL)        /*!< WPCS (Bitfield-Mask: 0x01)                            */
29396  #define R_XSPI_LIOCTL_RSTCS_Pos          (16UL)         /*!< RSTCS (Bit 16)                                        */
29397  #define R_XSPI_LIOCTL_RSTCS_Msk          (0x10000UL)    /*!< RSTCS (Bitfield-Mask: 0x01)                           */
29398 /* ========================================================  VERSTT  ========================================================= */
29399  #define R_XSPI_VERSTT_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
29400  #define R_XSPI_VERSTT_VER_Msk            (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff)                       */
29401 /* ========================================================  COMSTT  ========================================================= */
29402  #define R_XSPI_COMSTT_MEMACCCH_Pos       (0UL)          /*!< MEMACCCH (Bit 0)                                      */
29403  #define R_XSPI_COMSTT_MEMACCCH_Msk       (0x1UL)        /*!< MEMACCCH (Bitfield-Mask: 0x01)                        */
29404  #define R_XSPI_COMSTT_PBUFNECH_Pos       (4UL)          /*!< PBUFNECH (Bit 4)                                      */
29405  #define R_XSPI_COMSTT_PBUFNECH_Msk       (0x10UL)       /*!< PBUFNECH (Bitfield-Mask: 0x01)                        */
29406  #define R_XSPI_COMSTT_WRBUFNECH_Pos      (6UL)          /*!< WRBUFNECH (Bit 6)                                     */
29407  #define R_XSPI_COMSTT_WRBUFNECH_Msk      (0x40UL)       /*!< WRBUFNECH (Bitfield-Mask: 0x01)                       */
29408  #define R_XSPI_COMSTT_ECSCS_Pos          (16UL)         /*!< ECSCS (Bit 16)                                        */
29409  #define R_XSPI_COMSTT_ECSCS_Msk          (0x10000UL)    /*!< ECSCS (Bitfield-Mask: 0x01)                           */
29410  #define R_XSPI_COMSTT_INTCS_Pos          (17UL)         /*!< INTCS (Bit 17)                                        */
29411  #define R_XSPI_COMSTT_INTCS_Msk          (0x20000UL)    /*!< INTCS (Bitfield-Mask: 0x01)                           */
29412  #define R_XSPI_COMSTT_RSTOCS_Pos         (18UL)         /*!< RSTOCS (Bit 18)                                       */
29413  #define R_XSPI_COMSTT_RSTOCS_Msk         (0x40000UL)    /*!< RSTOCS (Bitfield-Mask: 0x01)                          */
29414 /* ========================================================  CASTTCS  ======================================================== */
29415  #define R_XSPI_CASTTCS_CASUC_Pos         (0UL)          /*!< CASUC (Bit 0)                                         */
29416  #define R_XSPI_CASTTCS_CASUC_Msk         (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff)                     */
29417 /* =========================================================  INTS  ========================================================== */
29418  #define R_XSPI_INTS_CMDCMP_Pos           (0UL)          /*!< CMDCMP (Bit 0)                                        */
29419  #define R_XSPI_INTS_CMDCMP_Msk           (0x1UL)        /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
29420  #define R_XSPI_INTS_PATCMP_Pos           (1UL)          /*!< PATCMP (Bit 1)                                        */
29421  #define R_XSPI_INTS_PATCMP_Msk           (0x2UL)        /*!< PATCMP (Bitfield-Mask: 0x01)                          */
29422  #define R_XSPI_INTS_INICMP_Pos           (2UL)          /*!< INICMP (Bit 2)                                        */
29423  #define R_XSPI_INTS_INICMP_Msk           (0x4UL)        /*!< INICMP (Bitfield-Mask: 0x01)                          */
29424  #define R_XSPI_INTS_PERTO_Pos            (3UL)          /*!< PERTO (Bit 3)                                         */
29425  #define R_XSPI_INTS_PERTO_Msk            (0x8UL)        /*!< PERTO (Bitfield-Mask: 0x01)                           */
29426  #define R_XSPI_INTS_DSTOCS_Pos           (4UL)          /*!< DSTOCS (Bit 4)                                        */
29427  #define R_XSPI_INTS_DSTOCS_Msk           (0x10UL)       /*!< DSTOCS (Bitfield-Mask: 0x01)                          */
29428  #define R_XSPI_INTS_ECSCS_Pos            (8UL)          /*!< ECSCS (Bit 8)                                         */
29429  #define R_XSPI_INTS_ECSCS_Msk            (0x100UL)      /*!< ECSCS (Bitfield-Mask: 0x01)                           */
29430  #define R_XSPI_INTS_INTCS_Pos            (12UL)         /*!< INTCS (Bit 12)                                        */
29431  #define R_XSPI_INTS_INTCS_Msk            (0x1000UL)     /*!< INTCS (Bitfield-Mask: 0x01)                           */
29432  #define R_XSPI_INTS_BRGOFCH_Pos          (16UL)         /*!< BRGOFCH (Bit 16)                                      */
29433  #define R_XSPI_INTS_BRGOFCH_Msk          (0x10000UL)    /*!< BRGOFCH (Bitfield-Mask: 0x01)                         */
29434  #define R_XSPI_INTS_BRGUFCH_Pos          (18UL)         /*!< BRGUFCH (Bit 18)                                      */
29435  #define R_XSPI_INTS_BRGUFCH_Msk          (0x40000UL)    /*!< BRGUFCH (Bitfield-Mask: 0x01)                         */
29436  #define R_XSPI_INTS_BUSERRCH_Pos         (20UL)         /*!< BUSERRCH (Bit 20)                                     */
29437  #define R_XSPI_INTS_BUSERRCH_Msk         (0x100000UL)   /*!< BUSERRCH (Bitfield-Mask: 0x01)                        */
29438  #define R_XSPI_INTS_CAFAILCS_Pos         (28UL)         /*!< CAFAILCS (Bit 28)                                     */
29439  #define R_XSPI_INTS_CAFAILCS_Msk         (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01)                        */
29440  #define R_XSPI_INTS_CASUCCS_Pos          (30UL)         /*!< CASUCCS (Bit 30)                                      */
29441  #define R_XSPI_INTS_CASUCCS_Msk          (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01)                         */
29442 /* =========================================================  INTC  ========================================================== */
29443  #define R_XSPI_INTC_CMDCMPC_Pos          (0UL)          /*!< CMDCMPC (Bit 0)                                       */
29444  #define R_XSPI_INTC_CMDCMPC_Msk          (0x1UL)        /*!< CMDCMPC (Bitfield-Mask: 0x01)                         */
29445  #define R_XSPI_INTC_PATCMPC_Pos          (1UL)          /*!< PATCMPC (Bit 1)                                       */
29446  #define R_XSPI_INTC_PATCMPC_Msk          (0x2UL)        /*!< PATCMPC (Bitfield-Mask: 0x01)                         */
29447  #define R_XSPI_INTC_INICMPC_Pos          (2UL)          /*!< INICMPC (Bit 2)                                       */
29448  #define R_XSPI_INTC_INICMPC_Msk          (0x4UL)        /*!< INICMPC (Bitfield-Mask: 0x01)                         */
29449  #define R_XSPI_INTC_PERTOC_Pos           (3UL)          /*!< PERTOC (Bit 3)                                        */
29450  #define R_XSPI_INTC_PERTOC_Msk           (0x8UL)        /*!< PERTOC (Bitfield-Mask: 0x01)                          */
29451  #define R_XSPI_INTC_DSTOCSC_Pos          (4UL)          /*!< DSTOCSC (Bit 4)                                       */
29452  #define R_XSPI_INTC_DSTOCSC_Msk          (0x10UL)       /*!< DSTOCSC (Bitfield-Mask: 0x01)                         */
29453  #define R_XSPI_INTC_ECSCSC_Pos           (8UL)          /*!< ECSCSC (Bit 8)                                        */
29454  #define R_XSPI_INTC_ECSCSC_Msk           (0x100UL)      /*!< ECSCSC (Bitfield-Mask: 0x01)                          */
29455  #define R_XSPI_INTC_INTCSC_Pos           (12UL)         /*!< INTCSC (Bit 12)                                       */
29456  #define R_XSPI_INTC_INTCSC_Msk           (0x1000UL)     /*!< INTCSC (Bitfield-Mask: 0x01)                          */
29457  #define R_XSPI_INTC_BRGOFCHC_Pos         (16UL)         /*!< BRGOFCHC (Bit 16)                                     */
29458  #define R_XSPI_INTC_BRGOFCHC_Msk         (0x10000UL)    /*!< BRGOFCHC (Bitfield-Mask: 0x01)                        */
29459  #define R_XSPI_INTC_BRGUFCHC_Pos         (18UL)         /*!< BRGUFCHC (Bit 18)                                     */
29460  #define R_XSPI_INTC_BRGUFCHC_Msk         (0x40000UL)    /*!< BRGUFCHC (Bitfield-Mask: 0x01)                        */
29461  #define R_XSPI_INTC_BUSERRCHC_Pos        (20UL)         /*!< BUSERRCHC (Bit 20)                                    */
29462  #define R_XSPI_INTC_BUSERRCHC_Msk        (0x100000UL)   /*!< BUSERRCHC (Bitfield-Mask: 0x01)                       */
29463  #define R_XSPI_INTC_CAFAILCSC_Pos        (28UL)         /*!< CAFAILCSC (Bit 28)                                    */
29464  #define R_XSPI_INTC_CAFAILCSC_Msk        (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01)                       */
29465  #define R_XSPI_INTC_CASUCCSC_Pos         (30UL)         /*!< CASUCCSC (Bit 30)                                     */
29466  #define R_XSPI_INTC_CASUCCSC_Msk         (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01)                        */
29467 /* =========================================================  INTE  ========================================================== */
29468  #define R_XSPI_INTE_CMDCMPE_Pos          (0UL)          /*!< CMDCMPE (Bit 0)                                       */
29469  #define R_XSPI_INTE_CMDCMPE_Msk          (0x1UL)        /*!< CMDCMPE (Bitfield-Mask: 0x01)                         */
29470  #define R_XSPI_INTE_PATCMPE_Pos          (1UL)          /*!< PATCMPE (Bit 1)                                       */
29471  #define R_XSPI_INTE_PATCMPE_Msk          (0x2UL)        /*!< PATCMPE (Bitfield-Mask: 0x01)                         */
29472  #define R_XSPI_INTE_INICMPE_Pos          (2UL)          /*!< INICMPE (Bit 2)                                       */
29473  #define R_XSPI_INTE_INICMPE_Msk          (0x4UL)        /*!< INICMPE (Bitfield-Mask: 0x01)                         */
29474  #define R_XSPI_INTE_PERTOE_Pos           (3UL)          /*!< PERTOE (Bit 3)                                        */
29475  #define R_XSPI_INTE_PERTOE_Msk           (0x8UL)        /*!< PERTOE (Bitfield-Mask: 0x01)                          */
29476  #define R_XSPI_INTE_DSTOCSE_Pos          (4UL)          /*!< DSTOCSE (Bit 4)                                       */
29477  #define R_XSPI_INTE_DSTOCSE_Msk          (0x10UL)       /*!< DSTOCSE (Bitfield-Mask: 0x01)                         */
29478  #define R_XSPI_INTE_ECSCSE_Pos           (8UL)          /*!< ECSCSE (Bit 8)                                        */
29479  #define R_XSPI_INTE_ECSCSE_Msk           (0x100UL)      /*!< ECSCSE (Bitfield-Mask: 0x01)                          */
29480  #define R_XSPI_INTE_INTCSE_Pos           (12UL)         /*!< INTCSE (Bit 12)                                       */
29481  #define R_XSPI_INTE_INTCSE_Msk           (0x1000UL)     /*!< INTCSE (Bitfield-Mask: 0x01)                          */
29482  #define R_XSPI_INTE_BRGOFCHE_Pos         (16UL)         /*!< BRGOFCHE (Bit 16)                                     */
29483  #define R_XSPI_INTE_BRGOFCHE_Msk         (0x10000UL)    /*!< BRGOFCHE (Bitfield-Mask: 0x01)                        */
29484  #define R_XSPI_INTE_BRGUFCHE_Pos         (18UL)         /*!< BRGUFCHE (Bit 18)                                     */
29485  #define R_XSPI_INTE_BRGUFCHE_Msk         (0x40000UL)    /*!< BRGUFCHE (Bitfield-Mask: 0x01)                        */
29486  #define R_XSPI_INTE_BUSERRCHE_Pos        (20UL)         /*!< BUSERRCHE (Bit 20)                                    */
29487  #define R_XSPI_INTE_BUSERRCHE_Msk        (0x100000UL)   /*!< BUSERRCHE (Bitfield-Mask: 0x01)                       */
29488  #define R_XSPI_INTE_CAFAILCSE_Pos        (28UL)         /*!< CAFAILCSE (Bit 28)                                    */
29489  #define R_XSPI_INTE_CAFAILCSE_Msk        (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01)                       */
29490  #define R_XSPI_INTE_CASUCCSE_Pos         (30UL)         /*!< CASUCCSE (Bit 30)                                     */
29491  #define R_XSPI_INTE_CASUCCSE_Msk         (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01)                        */
29492 
29493 /* =========================================================================================================================== */
29494 /* ================                                          R_ULPT0                                          ================ */
29495 /* =========================================================================================================================== */
29496 
29497 /* ========================================================  ULPTCNT  ======================================================== */
29498  #define R_ULPT0_ULPTCNT_ULPTCNT_Pos     (0UL)          /*!< ULPTCNT (Bit 0)                                       */
29499  #define R_ULPT0_ULPTCNT_ULPTCNT_Msk     (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff)                   */
29500 /* ========================================================  ULPTCMA  ======================================================== */
29501  #define R_ULPT0_ULPTCMA_ULPTCMA_Pos     (0UL)          /*!< ULPTCMA (Bit 0)                                       */
29502  #define R_ULPT0_ULPTCMA_ULPTCMA_Msk     (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff)                   */
29503 /* ========================================================  ULPTCMB  ======================================================== */
29504  #define R_ULPT0_ULPTCMB_ULPTCMB_Pos     (0UL)          /*!< ULPTCMB (Bit 0)                                       */
29505  #define R_ULPT0_ULPTCMB_ULPTCMB_Msk     (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff)                   */
29506 /* ========================================================  ULPTCR  ========================================================= */
29507  #define R_ULPT0_ULPTCR_TSTART_Pos       (0UL)          /*!< TSTART (Bit 0)                                        */
29508  #define R_ULPT0_ULPTCR_TSTART_Msk       (0x1UL)        /*!< TSTART (Bitfield-Mask: 0x01)                          */
29509  #define R_ULPT0_ULPTCR_TCSTF_Pos        (1UL)          /*!< TCSTF (Bit 1)                                         */
29510  #define R_ULPT0_ULPTCR_TCSTF_Msk        (0x2UL)        /*!< TCSTF (Bitfield-Mask: 0x01)                           */
29511  #define R_ULPT0_ULPTCR_TSTOP_Pos        (2UL)          /*!< TSTOP (Bit 2)                                         */
29512  #define R_ULPT0_ULPTCR_TSTOP_Msk        (0x4UL)        /*!< TSTOP (Bitfield-Mask: 0x01)                           */
29513  #define R_ULPT0_ULPTCR_TUNDF_Pos        (5UL)          /*!< TUNDF (Bit 5)                                         */
29514  #define R_ULPT0_ULPTCR_TUNDF_Msk        (0x20UL)       /*!< TUNDF (Bitfield-Mask: 0x01)                           */
29515  #define R_ULPT0_ULPTCR_TCMAF_Pos        (6UL)          /*!< TCMAF (Bit 6)                                         */
29516  #define R_ULPT0_ULPTCR_TCMAF_Msk        (0x40UL)       /*!< TCMAF (Bitfield-Mask: 0x01)                           */
29517  #define R_ULPT0_ULPTCR_TCMBF_Pos        (7UL)          /*!< TCMBF (Bit 7)                                         */
29518  #define R_ULPT0_ULPTCR_TCMBF_Msk        (0x80UL)       /*!< TCMBF (Bitfield-Mask: 0x01)                           */
29519 /* ========================================================  ULPTMR1  ======================================================== */
29520  #define R_ULPT0_ULPTMR1_TMOD1_Pos       (1UL)          /*!< TMOD1 (Bit 1)                                         */
29521  #define R_ULPT0_ULPTMR1_TMOD1_Msk       (0x2UL)        /*!< TMOD1 (Bitfield-Mask: 0x01)                           */
29522  #define R_ULPT0_ULPTMR1_TEDGPL_Pos      (3UL)          /*!< TEDGPL (Bit 3)                                        */
29523  #define R_ULPT0_ULPTMR1_TEDGPL_Msk      (0x8UL)        /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
29524  #define R_ULPT0_ULPTMR1_TCK1_Pos        (5UL)          /*!< TCK1 (Bit 5)                                          */
29525  #define R_ULPT0_ULPTMR1_TCK1_Msk        (0x20UL)       /*!< TCK1 (Bitfield-Mask: 0x01)                            */
29526 /* ========================================================  ULPTMR2  ======================================================== */
29527  #define R_ULPT0_ULPTMR2_CKS_Pos         (0UL)          /*!< CKS (Bit 0)                                           */
29528  #define R_ULPT0_ULPTMR2_CKS_Msk         (0x7UL)        /*!< CKS (Bitfield-Mask: 0x07)                             */
29529  #define R_ULPT0_ULPTMR2_LPM_Pos         (7UL)          /*!< LPM (Bit 7)                                           */
29530  #define R_ULPT0_ULPTMR2_LPM_Msk         (0x80UL)       /*!< LPM (Bitfield-Mask: 0x01)                             */
29531 /* ========================================================  ULPTMR3  ======================================================== */
29532  #define R_ULPT0_ULPTMR3_TCNTCTL_Pos     (0UL)          /*!< TCNTCTL (Bit 0)                                       */
29533  #define R_ULPT0_ULPTMR3_TCNTCTL_Msk     (0x1UL)        /*!< TCNTCTL (Bitfield-Mask: 0x01)                         */
29534  #define R_ULPT0_ULPTMR3_TEVPOL_Pos      (1UL)          /*!< TEVPOL (Bit 1)                                        */
29535  #define R_ULPT0_ULPTMR3_TEVPOL_Msk      (0x2UL)        /*!< TEVPOL (Bitfield-Mask: 0x01)                          */
29536  #define R_ULPT0_ULPTMR3_TOPOL_Pos       (2UL)          /*!< TOPOL (Bit 2)                                         */
29537  #define R_ULPT0_ULPTMR3_TOPOL_Msk       (0x4UL)        /*!< TOPOL (Bitfield-Mask: 0x01)                           */
29538  #define R_ULPT0_ULPTMR3_TEECTL_Pos      (4UL)          /*!< TEECTL (Bit 4)                                        */
29539  #define R_ULPT0_ULPTMR3_TEECTL_Msk      (0x30UL)       /*!< TEECTL (Bitfield-Mask: 0x03)                          */
29540  #define R_ULPT0_ULPTMR3_TEEPOL_Pos      (6UL)          /*!< TEEPOL (Bit 6)                                        */
29541  #define R_ULPT0_ULPTMR3_TEEPOL_Msk      (0xc0UL)       /*!< TEEPOL (Bitfield-Mask: 0x03)                          */
29542 /* ========================================================  ULPTIOC  ======================================================== */
29543  #define R_ULPT0_ULPTIOC_TOE_Pos         (2UL)          /*!< TOE (Bit 2)                                           */
29544  #define R_ULPT0_ULPTIOC_TOE_Msk         (0x4UL)        /*!< TOE (Bitfield-Mask: 0x01)                             */
29545  #define R_ULPT0_ULPTIOC_TIPF_Pos        (4UL)          /*!< TIPF (Bit 4)                                          */
29546  #define R_ULPT0_ULPTIOC_TIPF_Msk        (0x30UL)       /*!< TIPF (Bitfield-Mask: 0x03)                            */
29547  #define R_ULPT0_ULPTIOC_TIOGT0_Pos      (6UL)          /*!< TIOGT0 (Bit 6)                                        */
29548  #define R_ULPT0_ULPTIOC_TIOGT0_Msk      (0x40UL)       /*!< TIOGT0 (Bitfield-Mask: 0x01)                          */
29549 /* ========================================================  ULPTISR  ======================================================== */
29550  #define R_ULPT0_ULPTISR_RCCPSEL2_Pos    (2UL)          /*!< RCCPSEL2 (Bit 2)                                      */
29551  #define R_ULPT0_ULPTISR_RCCPSEL2_Msk    (0x4UL)        /*!< RCCPSEL2 (Bitfield-Mask: 0x01)                        */
29552 /* =======================================================  ULPTCMSR  ======================================================== */
29553  #define R_ULPT0_ULPTCMSR_TCMEA_Pos      (0UL)          /*!< TCMEA (Bit 0)                                         */
29554  #define R_ULPT0_ULPTCMSR_TCMEA_Msk      (0x1UL)        /*!< TCMEA (Bitfield-Mask: 0x01)                           */
29555  #define R_ULPT0_ULPTCMSR_TOEA_Pos       (1UL)          /*!< TOEA (Bit 1)                                          */
29556  #define R_ULPT0_ULPTCMSR_TOEA_Msk       (0x2UL)        /*!< TOEA (Bitfield-Mask: 0x01)                            */
29557  #define R_ULPT0_ULPTCMSR_TOPOLA_Pos     (2UL)          /*!< TOPOLA (Bit 2)                                        */
29558  #define R_ULPT0_ULPTCMSR_TOPOLA_Msk     (0x4UL)        /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
29559  #define R_ULPT0_ULPTCMSR_TCMEB_Pos      (4UL)          /*!< TCMEB (Bit 4)                                         */
29560  #define R_ULPT0_ULPTCMSR_TCMEB_Msk      (0x10UL)       /*!< TCMEB (Bitfield-Mask: 0x01)                           */
29561  #define R_ULPT0_ULPTCMSR_TOEB_Pos       (5UL)          /*!< TOEB (Bit 5)                                          */
29562  #define R_ULPT0_ULPTCMSR_TOEB_Msk       (0x20UL)       /*!< TOEB (Bitfield-Mask: 0x01)                            */
29563  #define R_ULPT0_ULPTCMSR_TOPOLB_Pos     (6UL)          /*!< TOPOLB (Bit 6)                                        */
29564  #define R_ULPT0_ULPTCMSR_TOPOLB_Msk     (0x40UL)       /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
29565 
29566 /* =========================================================================================================================== */
29567 /* ================                                        R_DEBUG_OCD                                        ================ */
29568 /* =========================================================================================================================== */
29569 
29570 /* =======================================================  FSBLSTATM  ======================================================= */
29571  #define R_DEBUG_OCD_FSBLSTATM_CS_Pos    (0UL)   /*!< CS (Bit 0)                                            */
29572  #define R_DEBUG_OCD_FSBLSTATM_CS_Msk    (0x1UL) /*!< CS (Bitfield-Mask: 0x01)                              */
29573  #define R_DEBUG_OCD_FSBLSTATM_RS_Pos    (1UL)   /*!< RS (Bit 1)                                            */
29574  #define R_DEBUG_OCD_FSBLSTATM_RS_Msk    (0x2UL) /*!< RS (Bitfield-Mask: 0x01)                              */
29575 
29576 /* =========================================================================================================================== */
29577 /* ================                                          R_AGTX0                                          ================ */
29578 /* =========================================================================================================================== */
29579 
29580 /* =========================================================================================================================== */
29581 /* ================                                          R_FLAD                                           ================ */
29582 /* =========================================================================================================================== */
29583 
29584 /* ========================================================  FCKMHZ  ========================================================= */
29585  #define R_FLAD_FCKMHZ_FCKMHZ_Pos    (0UL)    /*!< FCKMHZ (Bit 0)                                        */
29586  #define R_FLAD_FCKMHZ_FCKMHZ_Msk    (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff)                          */
29587 
29588 /* =========================================================================================================================== */
29589 /* ================                                      R_OFS_DATAFLASH                                      ================ */
29590 /* =========================================================================================================================== */
29591 
29592 /* =======================================================  FSBLCTRL0  ======================================================= */
29593  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos        (0UL)     /*!< FSBLEN (Bit 0)                                        */
29594  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Msk        (0x7UL)   /*!< FSBLEN (Bitfield-Mask: 0x07)                          */
29595  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos    (3UL)     /*!< FSBLSKIPSW (Bit 3)                                    */
29596  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Msk    (0x38UL)  /*!< FSBLSKIPSW (Bitfield-Mask: 0x07)                      */
29597  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos    (6UL)     /*!< FSBLSKIPDS (Bit 6)                                    */
29598  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Msk    (0x1c0UL) /*!< FSBLSKIPDS (Bitfield-Mask: 0x07)                      */
29599  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos       (9UL)     /*!< FSBLCLK (Bit 9)                                       */
29600  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Msk       (0xe00UL) /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
29601 /* =======================================================  FSBLCTRL1  ======================================================= */
29602  #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos      (0UL)     /*!< FSBLEXMD (Bit 0)                                      */
29603  #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Msk      (0x3UL)   /*!< FSBLEXMD (Bitfield-Mask: 0x03)                        */
29604 /* =======================================================  FSBLCTRL2  ======================================================= */
29605  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos        (0UL)     /*!< PORTPN (Bit 0)                                        */
29606  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Msk        (0xfUL)   /*!< PORTPN (Bitfield-Mask: 0x0f)                          */
29607  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos        (4UL)     /*!< PORTGN (Bit 4)                                        */
29608  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Msk        (0x1f0UL) /*!< PORTGN (Bitfield-Mask: 0x1f)                          */
29609 /* =========================================================  SACC0  ========================================================= */
29610 /* =========================================================  SACC1  ========================================================= */
29611 /* =========================================================  SAMR  ========================================================== */
29612 /* =======================================================  HOEMRTPK  ======================================================== */
29613 /* =========================================================  ARCLS  ========================================================= */
29614  #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos          (0UL)          /*!< ARCS_LK (Bit 0)                                       */
29615  #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Msk          (0x1UL)        /*!< ARCS_LK (Bitfield-Mask: 0x01)                         */
29616  #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos         (1UL)          /*!< ARCNS_LK (Bit 1)                                      */
29617  #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Msk         (0x1eUL)       /*!< ARCNS_LK (Bitfield-Mask: 0x0f)                        */
29618  #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos         (5UL)          /*!< ARCBL_LK (Bit 5)                                      */
29619  #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Msk         (0x20UL)       /*!< ARCBL_LK (Bitfield-Mask: 0x01)                        */
29620 /* =========================================================  ARCCS  ========================================================= */
29621  #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Pos        (0UL)          /*!< CNF_ARCNS (Bit 0)                                     */
29622  #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Msk        (0x3UL)        /*!< CNF_ARCNS (Bitfield-Mask: 0x03)                       */
29623 /* ========================================================  ARC_SEC  ======================================================== */
29624  #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Pos        (0UL)          /*!< ARC_SEC (Bit 0)                                       */
29625  #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Msk        (0xffffffffUL) /*!< ARC_SEC (Bitfield-Mask: 0xffffffff)                   */
29626 /* =======================================================  ARC_NSEC  ======================================================== */
29627  #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Pos      (0UL)          /*!< ARC_NSEC (Bit 0)                                      */
29628  #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Msk      (0xffffffffUL) /*!< ARC_NSEC (Bitfield-Mask: 0xffffffff)                  */
29629 /* =======================================================  ARC_OEMBL  ======================================================= */
29630  #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Pos    (0UL)          /*!< ARC_OEMBL (Bit 0)                                     */
29631  #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Msk    (0xffffffffUL) /*!< ARC_OEMBL (Bitfield-Mask: 0xffffffff)                 */
29632 
29633 /** @} */ /* End of group PosMask_peripherals */
29634 
29635  #ifdef __cplusplus
29636 }
29637  #endif
29638 
29639 #endif                                 /* R7FA8T1AH_H */
29640 
29641 /** @} */ /* End of group R7FA8T1AH */
29642 
29643 /** @} */ /* End of group Renesas */
29644