1 /*
2  * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * @file     ./out/R7FA4L1BD.h
7  * @brief    CMSIS HeaderFile
8  * @version  1.10.03
9  */
10 
11 /** @addtogroup Renesas Electronics Corporation
12  * @{
13  */
14 
15 /** @addtogroup R7FA4L1BD
16  * @{
17  */
18 
19 #ifndef R7FA4L1BD_H
20  #define R7FA4L1BD_H
21 
22  #ifdef __cplusplus
23 extern "C" {
24  #endif
25 
26 /** @addtogroup Configuration_of_CMSIS
27  * @{
28  */
29 
30 /* =========================================================================================================================== */
31 /* ================                                Interrupt Number Definition                                ================ */
32 /* =========================================================================================================================== */
33 
34 /* =========================================================================================================================== */
35 /* ================                           Processor and Core Peripheral Section                           ================ */
36 /* =========================================================================================================================== */
37 
38 /* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
39  #define __CM33_REV                0x0004U /*!< CM33 Core Revision                                                        */
40  #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
41  #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
42  #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
43  #define __MPU_PRESENT             1       /*!< MPU present                                                               */
44  #define __FPU_PRESENT             1       /*!< FPU present                                                               */
45  #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
46  #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
47  #define __SAUREGION_PRESENT       0       /*!< SAU region present                                                        */
48 
49 /** @} */ /* End of group Configuration_of_CMSIS */
50 
51  #include "core_cm33.h"                    /*!< ARM Cortex-M33 processor and core peripherals                             */
52  #include "system.h"                       /*!< R7FA4L1BD System                                                          */
53 
54  #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
55   #define __IM     __I
56  #endif
57  #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
58   #define __OM     __O
59  #endif
60  #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
61   #define __IOM    __IO
62  #endif
63 
64 /* ========================================  Start of section using anonymous unions  ======================================== */
65  #if defined(__CC_ARM)
66   #pragma push
67   #pragma anon_unions
68  #elif defined(__ICCARM__)
69   #pragma language=extended
70  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
71   #pragma clang diagnostic push
72   #pragma clang diagnostic ignored "-Wc11-extensions"
73   #pragma clang diagnostic ignored "-Wreserved-id-macro"
74   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
75   #pragma clang diagnostic ignored "-Wnested-anon-types"
76  #elif defined(__GNUC__)
77 
78 /* anonymous unions are enabled by default */
79  #elif defined(__TMS470__)
80 
81 /* anonymous unions are enabled by default */
82  #elif defined(__TASKING__)
83   #pragma warning 586
84  #elif defined(__CSMC__)
85 
86 /* anonymous unions are enabled by default */
87  #else
88   #warning Not supported compiler type
89  #endif
90 
91 /* =========================================================================================================================== */
92 /* ================                              Device Specific Cluster Section                              ================ */
93 /* =========================================================================================================================== */
94 
95 /** @addtogroup Device_Peripheral_clusters
96  * @{
97  */
98 
99 /**
100  * @brief R_BUS_CSa [CSa] (CS Registers)
101  */
102 typedef struct
103 {
104     __IM uint16_t RESERVED;
105 
106     union
107     {
108         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
109 
110         struct
111         {
112             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
113             uint16_t             : 2;
114             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
115             uint16_t             : 4;
116             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
117             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
118             uint16_t             : 5;
119             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
120         } MOD_b;
121     };
122 
123     union
124     {
125         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
126 
127         struct
128         {
129             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
130             uint32_t                : 5;
131             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
132             uint32_t                : 5;
133             __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
134             uint32_t                : 3;
135             __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
136             uint32_t                : 3;
137         } WCR1_b;
138     };
139 
140     union
141     {
142         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
143 
144         struct
145         {
146             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
147             uint32_t              : 1;
148             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
149             uint32_t              : 1;
150             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
151             uint32_t              : 1;
152             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
153             uint32_t              : 2;
154             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
155             uint32_t              : 1;
156             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
157             uint32_t              : 1;
158             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
159             uint32_t              : 1;
160             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
161             uint32_t              : 1;
162         } WCR2_b;
163     };
164     __IM uint32_t RESERVED1;
165 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
166 
167 /**
168  * @brief R_BUS_CSb [CSb] (CS Registers)
169  */
170 typedef struct
171 {
172     __IM uint16_t RESERVED;
173 
174     union
175     {
176         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
177 
178         struct
179         {
180             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
181             uint16_t             : 3;
182             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
183             uint16_t             : 2;
184             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
185             uint16_t             : 3;
186             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
187             uint16_t             : 3;
188         } CR_b;
189     };
190     __IM uint16_t RESERVED1[3];
191 
192     union
193     {
194         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
195 
196         struct
197         {
198             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
199             uint16_t            : 4;
200             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
201             uint16_t            : 4;
202         } REC_b;
203     };
204     __IM uint16_t RESERVED2[2];
205 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
206 
207 /**
208  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
209  */
210 typedef struct
211 {
212     union
213     {
214         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
215 
216         struct
217         {
218             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
219             uint8_t             : 3;
220             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
221             uint8_t             : 2;
222         } SDCCR_b;
223     };
224 
225     union
226     {
227         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
228 
229         struct
230         {
231             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
232             uint8_t             : 7;
233         } SDCMOD_b;
234     };
235 
236     union
237     {
238         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
239 
240         struct
241         {
242             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
243             uint8_t          : 7;
244         } SDAMOD_b;
245     };
246     __IM uint8_t  RESERVED;
247     __IM uint32_t RESERVED1[3];
248 
249     union
250     {
251         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
252 
253         struct
254         {
255             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
256             uint8_t            : 7;
257         } SDSELF_b;
258     };
259     __IM uint8_t  RESERVED2;
260     __IM uint16_t RESERVED3;
261 
262     union
263     {
264         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
265 
266         struct
267         {
268             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
269             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
270                                         *   Setting. ( REFW+1 Cycles )                                                */
271         } SDRFCR_b;
272     };
273 
274     union
275     {
276         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
277 
278         struct
279         {
280             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
281             uint8_t            : 7;
282         } SDRFEN_b;
283     };
284     __IM uint8_t  RESERVED4;
285     __IM uint32_t RESERVED5[2];
286 
287     union
288     {
289         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
290 
291         struct
292         {
293             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
294             uint8_t             : 7;
295         } SDICR_b;
296     };
297     __IM uint8_t  RESERVED6;
298     __IM uint16_t RESERVED7;
299 
300     union
301     {
302         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
303 
304         struct
305         {
306             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
307             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
308             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
309                                         *   )                                                                         */
310             uint16_t : 5;
311         } SDIR_b;
312     };
313     __IM uint16_t RESERVED8;
314     __IM uint32_t RESERVED9[6];
315 
316     union
317     {
318         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
319 
320         struct
321         {
322             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
323             uint8_t           : 6;
324         } SDADR_b;
325     };
326     __IM uint8_t  RESERVED10;
327     __IM uint16_t RESERVED11;
328 
329     union
330     {
331         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
332 
333         struct
334         {
335             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
336             uint32_t           : 5;
337             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
338             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
339             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
340             uint32_t           : 2;
341             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
342             uint32_t           : 13;
343         } SDTR_b;
344     };
345 
346     union
347     {
348         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
349 
350         struct
351         {
352             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
353             uint16_t          : 1;
354         } SDMOD_b;
355     };
356     __IM uint16_t RESERVED12;
357     __IM uint32_t RESERVED13;
358 
359     union
360     {
361         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
362 
363         struct
364         {
365             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
366             uint8_t            : 2;
367             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
368             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
369             uint8_t            : 3;
370         } SDSR_b;
371     };
372     __IM uint8_t  RESERVED14;
373     __IM uint16_t RESERVED15;
374 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
375 
376 /**
377  * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
378  */
379 typedef struct
380 {
381     union
382     {
383         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
384 
385         struct
386         {
387             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
388         } ADD_b;
389     };
390 
391     union
392     {
393         union
394         {
395             __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */
396 
397             struct
398             {
399                 __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
400                 uint8_t              : 6;
401                 __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
402             } STAT_b;
403         };
404 
405         union
406         {
407             __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */
408 
409             struct
410             {
411                 __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
412                 uint8_t             : 7;
413             } RW_b;
414         };
415     };
416     __IM uint8_t  RESERVED;
417     __IM uint16_t RESERVED1;
418     __IM uint32_t RESERVED2[2];
419 } R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */
420 
421 /**
422  * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
423  */
424 typedef struct
425 {
426     union
427     {
428         __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */
429 
430         struct
431         {
432             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
433         } ADD_b;
434     };
435 
436     union
437     {
438         __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */
439 
440         struct
441         {
442             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
443             uint8_t              : 7;
444         } RW_b;
445     };
446     __IM uint8_t  RESERVED;
447     __IM uint16_t RESERVED1;
448     __IM uint32_t RESERVED2[2];
449 } R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */
450 
451 /**
452  * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
453  */
454 typedef struct
455 {
456     union
457     {
458         __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */
459 
460         struct
461         {
462             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
463             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
464             uint8_t                : 1;
465             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
466             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
467             __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
468             uint8_t                : 2;
469         } STAT_b;
470     };
471     __IM uint8_t  RESERVED;
472     __IM uint16_t RESERVED1;
473     __IM uint32_t RESERVED2;
474 
475     union
476     {
477         union
478         {
479             __IOM uint32_t IRQEN;      /*!< (@ 0x00000008) BUS Error IRQ Enable                                       */
480 
481             struct
482             {
483                 __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when
484                                         *   a bus error occurs                                                        */
485                 uint32_t : 31;
486             } IRQEN_b;
487         };
488 
489         union
490         {
491             __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */
492 
493             struct
494             {
495                 __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
496                 __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
497                 uint8_t                : 1;
498                 __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
499                 __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
500                 __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
501                 uint8_t                : 2;
502             } CLR_b;
503         };
504     };
505     __IM uint32_t RESERVED3;
506 } R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */
507 
508 /**
509  * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
510  */
511 typedef struct
512 {
513     __IM uint8_t RESERVED[36];
514 
515     union
516     {
517         __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */
518 
519         struct
520         {
521             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
522             uint8_t                : 7;
523         } STAT_b;
524     };
525     __IM uint8_t RESERVED1[7];
526 
527     union
528     {
529         __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */
530 
531         struct
532         {
533             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
534             uint8_t                : 7;
535         } CLR_b;
536     };
537 } R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */
538 
539 /**
540  * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
541  */
542 typedef struct
543 {
544     __IM uint32_t RESERVED[2];
545 
546     union
547     {
548         __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */
549 
550         struct
551         {
552             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
553             uint32_t            : 31;
554         } MRE0BI_b;
555     };
556     __IM uint32_t RESERVED1;
557 
558     union
559     {
560         __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */
561 
562         struct
563         {
564             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
565             uint32_t            : 31;
566         } FLBI_b;
567     };
568     __IM uint32_t RESERVED2[3];
569 
570     union
571     {
572         __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
573 
574         struct
575         {
576             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
577             uint32_t            : 31;
578         } S0BI_b;
579     };
580     __IM uint32_t RESERVED3;
581 
582     union
583     {
584         __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */
585 
586         struct
587         {
588             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
589             uint32_t            : 31;
590         } S1BI_b;
591     };
592     __IM uint32_t RESERVED4;
593 
594     union
595     {
596         __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */
597 
598         struct
599         {
600             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
601             uint32_t            : 31;
602         } S2BI_b;
603     };
604     __IM uint32_t RESERVED5;
605 
606     union
607     {
608         __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */
609 
610         struct
611         {
612             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
613             uint32_t            : 31;
614         } S3BI_b;
615     };
616     __IM uint32_t RESERVED6[3];
617 
618     union
619     {
620         __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */
621 
622         struct
623         {
624             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
625             uint32_t            : 31;
626         } STBYSBI_b;
627     };
628     __IM uint32_t RESERVED7;
629 
630     union
631     {
632         union
633         {
634             __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
635 
636             struct
637             {
638                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
639                 uint32_t            : 31;
640             } ECBI_b;
641         };
642 
643         union
644         {
645             __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
646 
647             struct
648             {
649                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
650                 uint32_t            : 31;
651             } SPI0BI_b;
652         };
653     };
654     __IM uint32_t RESERVED8;
655 
656     union
657     {
658         union
659         {
660             __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
661 
662             struct
663             {
664                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
665                 uint32_t            : 31;
666             } EOBI_b;
667         };
668 
669         union
670         {
671             __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
672 
673             struct
674             {
675                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
676                 uint32_t            : 31;
677             } SPI1BI_b;
678         };
679     };
680     __IM uint32_t RESERVED9;
681 
682     union
683     {
684         __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */
685 
686         struct
687         {
688             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
689             uint32_t            : 31;
690         } PBBI_b;
691     };
692     __IM uint32_t RESERVED10;
693 
694     union
695     {
696         union
697         {
698             __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
699 
700             struct
701             {
702                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
703                 uint32_t            : 31;
704             } PABI_b;
705         };
706 
707         union
708         {
709             __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
710 
711             struct
712             {
713                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
714                 uint32_t            : 31;
715             } CPU0SAHBI_b;
716         };
717     };
718     __IM uint32_t RESERVED11;
719 
720     union
721     {
722         __IOM uint32_t PIBI;           /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
723 
724         struct
725         {
726             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
727             uint32_t            : 31;
728         } PIBI_b;
729     };
730     __IM uint32_t RESERVED12;
731 
732     union
733     {
734         __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */
735 
736         struct
737         {
738             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
739             uint32_t            : 31;
740         } PSBI_b;
741     };
742 } R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */
743 
744 /**
745  * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
746  */
747 typedef struct
748 {
749     union
750     {
751         union
752         {
753             __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
754 
755             struct
756             {
757                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
758                 uint32_t            : 30;
759             } FHBI_b;
760         };
761 
762         union
763         {
764             __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
765 
766             struct
767             {
768                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
769                 uint32_t            : 30;
770             } MRC0BI_b;
771         };
772     };
773     __IM uint32_t RESERVED[5];
774 
775     union
776     {
777         __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */
778 
779         struct
780         {
781             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
782             uint32_t            : 30;
783         } S0BI_b;
784     };
785     __IM uint32_t RESERVED1;
786 
787     union
788     {
789         __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
790 
791         struct
792         {
793             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
794             uint32_t            : 30;
795         } S1BI_b;
796     };
797 } R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */
798 
799 /**
800  * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
801  */
802 typedef struct
803 {
804     union
805     {
806         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */
807 
808         struct
809         {
810             __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
811         } ADD_b;
812     };
813 
814     union
815     {
816         __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
817                                          *                  Write.                                                     */
818 
819         struct
820         {
821             __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
822                                          *   Status.                                                                   */
823             uint8_t : 7;
824         } RW_b;
825     };
826     __IM uint8_t  RESERVED;
827     __IM uint16_t RESERVED1;
828     __IM uint32_t RESERVED2[2];
829 } R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */
830 
831 /**
832  * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
833  */
834 typedef struct
835 {
836     union
837     {
838         __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */
839 
840         struct
841         {
842             __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
843             __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
844             __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
845             uint16_t                : 13;
846         } BUSOAD_b;
847     };
848     __IM uint16_t RESERVED;
849 
850     union
851     {
852         __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */
853 
854         struct
855         {
856             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
857             uint16_t               : 7;
858             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
859         } BUSOADPT_b;
860     };
861     __IM uint16_t RESERVED1[5];
862 
863     union
864     {
865         __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
866                                         *                  Register.                                                  */
867 
868         struct
869         {
870             __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
871             uint16_t           : 7;
872             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
873         } MSAOAD_b;
874     };
875     __IM uint16_t RESERVED2;
876 
877     union
878     {
879         __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */
880 
881         struct
882         {
883             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
884             uint16_t               : 7;
885             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
886         } MSAPT_b;
887     };
888 } R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */
889 
890 /**
891  * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
892  */
893 typedef struct
894 {
895     union
896     {
897         __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */
898 
899         struct
900         {
901             __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
902             __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
903             __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
904             __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
905             __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
906             __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
907             __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
908             __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
909             __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
910             __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
911             __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
912             __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
913             __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
914             __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
915             __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
916             __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
917             __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
918             __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
919             __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
920             __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
921             __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
922             __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
923             __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
924             __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
925             __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
926             __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
927             __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
928             __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
929             __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
930             __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
931             __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
932             __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
933         } STAT_b;
934     };
935     __IM uint32_t RESERVED;
936 
937     union
938     {
939         __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */
940 
941         struct
942         {
943             __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
944             __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
945             __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
946             __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
947             __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
948             __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
949             __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
950             __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
951             __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
952             __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
953             __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
954             __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
955             __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
956             __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
957             __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
958             __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
959             __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
960             __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
961             __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
962             __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
963             __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
964             __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
965             __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
966             __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
967             __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
968             __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
969             __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
970             __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
971             __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
972             __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
973             __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
974             __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
975         } CLR_b;
976     };
977 } R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */
978 
979 /**
980  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
981  */
982 typedef struct
983 {
984     union
985     {
986         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
987 
988         struct
989         {
990             uint16_t             : 15;
991             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
992         } CNT_b;
993     };
994     __IM uint16_t RESERVED;
995 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
996 
997 /**
998  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
999  */
1000 typedef struct
1001 {
1002     union
1003     {
1004         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
1005 
1006         struct
1007         {
1008             __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
1009             uint16_t              : 2;
1010             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
1011             uint16_t              : 10;
1012         } CNT_b;
1013     };
1014     __IM uint16_t RESERVED;
1015 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
1016 
1017 /**
1018  * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
1019  */
1020 typedef struct
1021 {
1022     union
1023     {
1024         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
1025 
1026         struct
1027         {
1028             __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
1029             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
1030             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
1031             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
1032         } NCFG_b;
1033     };
1034 
1035     union
1036     {
1037         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
1038 
1039         struct
1040         {
1041             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
1042             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
1043             __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
1044             uint32_t               : 4;
1045             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
1046             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
1047             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
1048             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
1049             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
1050             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
1051             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
1052             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
1053             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
1054             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
1055             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
1056             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
1057                                          *   enable                                                                    */
1058             uint32_t            : 1;
1059             __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
1060             __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
1061             __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
1062             __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
1063             uint32_t            : 3;
1064             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
1065             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
1066         } CTR_b;
1067     };
1068 
1069     union
1070     {
1071         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
1072 
1073         struct
1074         {
1075             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
1076             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
1077             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
1078             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
1079             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
1080             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
1081             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
1082             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
1083             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
1084             uint32_t               : 7;
1085             __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
1086             __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
1087         } STS_b;
1088     };
1089 
1090     union
1091     {
1092         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
1093 
1094         struct
1095         {
1096             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
1097             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
1098             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
1099             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
1100             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
1101             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
1102             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
1103             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
1104             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
1105             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
1106             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
1107             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
1108             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
1109             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
1110             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
1111             uint32_t             : 1;
1112             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
1113             uint32_t             : 1;
1114         } ERFL_b;
1115     };
1116 } R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
1117 
1118 /**
1119  * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
1120  */
1121 typedef struct
1122 {
1123     union
1124     {
1125         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
1126 
1127         struct
1128         {
1129             __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
1130             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
1131             uint32_t              : 3;
1132             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
1133             uint32_t              : 4;
1134             __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
1135             uint32_t              : 4;
1136         } DCFG_b;
1137     };
1138 
1139     union
1140     {
1141         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
1142 
1143         struct
1144         {
1145             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
1146             uint32_t              : 5;
1147             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
1148             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
1149             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
1150             uint32_t              : 5;
1151             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
1152             uint32_t              : 4;
1153             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
1154             __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
1155             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
1156             uint32_t              : 1;
1157         } FDCFG_b;
1158     };
1159 
1160     union
1161     {
1162         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
1163 
1164         struct
1165         {
1166             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
1167             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
1168             uint32_t              : 30;
1169         } FDCTR_b;
1170     };
1171 
1172     union
1173     {
1174         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
1175 
1176         struct
1177         {
1178             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
1179             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
1180             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
1181             uint32_t             : 5;
1182             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
1183             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
1184             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
1185         } FDSTS_b;
1186     };
1187 
1188     union
1189     {
1190         __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
1191 
1192         struct
1193         {
1194             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
1195             uint32_t             : 3;
1196             __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
1197             uint32_t             : 4;
1198         } FDCRC_b;
1199     };
1200     __IM uint32_t RESERVED[3];
1201 } R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
1202 
1203 /**
1204  * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
1205  */
1206 typedef struct
1207 {
1208     union
1209     {
1210         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
1211 
1212         struct
1213         {
1214             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
1215             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
1216             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
1217             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
1218         } ID_b;
1219     };
1220 
1221     union
1222     {
1223         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
1224 
1225         struct
1226         {
1227             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
1228             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
1229             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
1230             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
1231         } M_b;
1232     };
1233 
1234     union
1235     {
1236         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
1237 
1238         struct
1239         {
1240             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
1241             uint32_t                : 3;
1242             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
1243             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
1244                                           *   Pointer                                                                   */
1245             uint32_t               : 2;
1246             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
1247             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
1248         } P0_b;
1249     };
1250 
1251     union
1252     {
1253         __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
1254 
1255         struct
1256         {
1257             __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
1258             uint32_t               : 23;
1259         } P1_b;
1260     };
1261 } R_CANFD_CFDGAFL_Type;                 /*!< Size = 16 (0x10)                                                          */
1262 
1263 /**
1264  * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
1265  */
1266 typedef struct
1267 {
1268     union
1269     {
1270         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
1271 
1272         struct
1273         {
1274             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
1275             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
1276             uint32_t           : 6;
1277             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
1278         } ACC0_b;
1279     };
1280 
1281     union
1282     {
1283         __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
1284 
1285         struct
1286         {
1287             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
1288             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
1289             uint32_t           : 14;
1290         } ACC1_b;
1291     };
1292 } R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
1293 
1294 /**
1295  * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
1296  */
1297 typedef struct
1298 {
1299     union
1300     {
1301         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
1302 
1303         struct
1304         {
1305             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
1306             uint32_t            : 1;
1307             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
1308             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
1309         } ID_b;
1310     };
1311 
1312     union
1313     {
1314         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
1315 
1316         struct
1317         {
1318             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
1319             uint32_t            : 12;
1320             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
1321         } PTR_b;
1322     };
1323 
1324     union
1325     {
1326         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
1327 
1328         struct
1329         {
1330             __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1331             __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1332             __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1333             uint32_t            : 5;
1334             __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
1335             uint32_t            : 6;
1336             __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
1337         } FDSTS_b;
1338     };
1339 
1340     union
1341     {
1342         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
1343 
1344         struct
1345         {
1346             __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
1347         } DF_b[64];
1348     };
1349 } R_CANFD_CFDRF_Type;                  /*!< Size = 76 (0x4c)                                                          */
1350 
1351 /**
1352  * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
1353  */
1354 typedef struct
1355 {
1356     union
1357     {
1358         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
1359 
1360         struct
1361         {
1362             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
1363             __IOM uint32_t THLEN : 1;  /*!< [29..29] THL Entry enable                                                 */
1364             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
1365             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
1366         } ID_b;
1367     };
1368 
1369     union
1370     {
1371         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
1372 
1373         struct
1374         {
1375             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
1376             uint32_t             : 12;
1377             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
1378         } PTR_b;
1379     };
1380 
1381     union
1382     {
1383         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
1384 
1385         struct
1386         {
1387             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1388             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1389             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1390             uint32_t             : 5;
1391             __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
1392             uint32_t             : 6;
1393             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
1394         } FDSTS_b;
1395     };
1396 
1397     union
1398     {
1399         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
1400 
1401         struct
1402         {
1403             __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
1404         } DF_b[64];
1405     };
1406 } R_CANFD_CFDCF_Type;                  /*!< Size = 76 (0x4c)                                                          */
1407 
1408 /**
1409  * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
1410  */
1411 typedef struct
1412 {
1413     union
1414     {
1415         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
1416 
1417         struct
1418         {
1419             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
1420             __IOM uint32_t THLEN : 1;  /*!< [29..29] Tx History List Entry                                            */
1421             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
1422             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
1423         } ID_b;
1424     };
1425 
1426     union
1427     {
1428         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
1429 
1430         struct
1431         {
1432             __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
1433             uint32_t             : 12;
1434             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
1435         } PTR_b;
1436     };
1437 
1438     union
1439     {
1440         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
1441 
1442         struct
1443         {
1444             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1445             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1446             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1447             uint32_t             : 5;
1448             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
1449             uint32_t             : 6;
1450             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
1451         } FDCTR_b;
1452     };
1453 
1454     union
1455     {
1456         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
1457 
1458         struct
1459         {
1460             __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
1461         } DF_b[64];
1462     };
1463 } R_CANFD_CFDTM_Type;                  /*!< Size = 76 (0x4c)                                                          */
1464 
1465 /**
1466  * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
1467  */
1468 typedef struct
1469 {
1470     union
1471     {
1472         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
1473 
1474         struct
1475         {
1476             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
1477             uint32_t            : 1;
1478             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
1479             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
1480         } ID_b;
1481     };
1482 
1483     union
1484     {
1485         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
1486 
1487         struct
1488         {
1489             __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
1490             uint32_t            : 12;
1491             __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
1492         } PTR_b;
1493     };
1494 
1495     union
1496     {
1497         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
1498 
1499         struct
1500         {
1501             __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1502             __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1503             __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1504             uint32_t            : 5;
1505             __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
1506             uint32_t            : 6;
1507             __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
1508         } FDSTS_b;
1509     };
1510 
1511     union
1512     {
1513         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
1514 
1515         struct
1516         {
1517             __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
1518         } DF_b[64];
1519     };
1520 } R_CANFD_CFDRM_RM_Type;               /*!< Size = 76 (0x4c)                                                          */
1521 
1522 /**
1523  * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
1524  */
1525 typedef struct
1526 {
1527     __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
1528     __IM uint32_t               RESERVED[104];
1529 } R_CANFD_CFDRM_Type;                  /*!< Size = 1024 (0x400)                                                       */
1530 
1531 /**
1532  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1533  */
1534 typedef struct
1535 {
1536     union
1537     {
1538         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1539 
1540         struct
1541         {
1542             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1543             uint8_t          : 5;
1544             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1545             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1546         } BY_b;
1547     };
1548     __IM uint8_t RESERVED;
1549 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1550 
1551 /**
1552  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
1553  */
1554 typedef struct
1555 {
1556     union
1557     {
1558         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1559 
1560         struct
1561         {
1562             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1563             uint16_t           : 7;
1564         } HA_b;
1565     };
1566     __IM uint16_t RESERVED;
1567 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1568 
1569 /**
1570  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
1571  */
1572 typedef struct
1573 {
1574     union
1575     {
1576         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
1577 
1578         struct
1579         {
1580             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
1581                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
1582         } L_b;
1583     };
1584 
1585     union
1586     {
1587         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
1588 
1589         struct
1590         {
1591             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
1592             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
1593             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
1594             uint8_t            : 5;
1595         } U_b;
1596     };
1597 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
1598 
1599 /**
1600  * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control)
1601  */
1602 typedef struct
1603 {
1604     union
1605     {
1606         __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */
1607 
1608         struct
1609         {
1610             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
1611             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
1612             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
1613             __IOM uint16_t PP     : 1; /*!< [3..3] Privilege protection                                               */
1614             uint16_t              : 12;
1615         } AC_b;
1616     };
1617     __IM uint16_t RESERVED;
1618 
1619     union
1620     {
1621         __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */
1622 
1623         struct
1624         {
1625             __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
1626                                         *   NOTE: Some low-order bits are fixed to 0.                                 */
1627         } S_b;
1628     };
1629 
1630     union
1631     {
1632         __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */
1633 
1634         struct
1635         {
1636             __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
1637                                         *   end, for use in region determination. NOTE: Some low-order
1638                                         *   bits are fixed to 1.                                                      */
1639         } E_b;
1640     };
1641     __IM uint32_t RESERVED1;
1642 } R_MPU_MMPU_GROUP_REGION_Type;        /*!< Size = 16 (0x10)                                                          */
1643 
1644 /**
1645  * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers)
1646  */
1647 typedef struct
1648 {
1649     union
1650     {
1651         __IOM uint16_t EN;             /*!< (@ 0x00000000) MMPU enable register                                       */
1652 
1653         struct
1654         {
1655             __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable                                      */
1656             uint16_t              : 7;
1657             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1658                                         *   stored.                                                                   */
1659         } EN_b;
1660     };
1661     __IM uint16_t RESERVED;
1662 
1663     union
1664     {
1665         __IOM uint16_t ENPT;            /*!< (@ 0x00000004) MMPU enable protect register                               */
1666 
1667         struct
1668         {
1669             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN                                          */
1670             uint16_t               : 7;
1671             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1672                                          *   stored.                                                                   */
1673         } ENPT_b;
1674     };
1675     __IM uint16_t RESERVED1;
1676 
1677     union
1678     {
1679         __IOM uint16_t RPT;             /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure                   */
1680 
1681         struct
1682         {
1683             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
1684             uint16_t               : 7;
1685             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1686                                          *   stored.                                                                   */
1687         } RPT_b;
1688     };
1689     __IM uint16_t RESERVED2;
1690 
1691     union
1692     {
1693         __IOM uint16_t RPT_SEC;         /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only)           */
1694 
1695         struct
1696         {
1697             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
1698             uint16_t               : 7;
1699             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1700                                          *   stored.                                                                   */
1701         } RPT_SEC_b;
1702     };
1703     __IM uint16_t RESERVED3;
1704     __IM uint32_t RESERVED4[60];
1705     __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control                                     */
1706     __IM uint32_t RESERVED5[32];
1707 } R_MPU_MMPU_GROUP_Type;                          /*!< Size = 512 (0x200)                                                        */
1708 
1709 /**
1710  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
1711  */
1712 typedef struct
1713 {
1714     union
1715     {
1716         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
1717                                         *                  Register                                                   */
1718 
1719         struct
1720         {
1721             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
1722             uint16_t           : 7;
1723             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
1724                                         *   stored.                                                                   */
1725         } OAD_b;
1726     };
1727     __IM uint16_t RESERVED;
1728 
1729     union
1730     {
1731         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
1732 
1733         struct
1734         {
1735             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
1736             uint16_t              : 7;
1737             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
1738             uint16_t              : 7;
1739         } CTL_b;
1740     };
1741 
1742     union
1743     {
1744         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
1745 
1746         struct
1747         {
1748             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
1749             uint16_t               : 7;
1750             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1751                                          *   stored.                                                                   */
1752         } PT_b;
1753     };
1754 
1755     union
1756     {
1757         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
1758 
1759         struct
1760         {
1761             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
1762                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
1763                                            *   The low-order 2 bits are fixed to 0.                                      */
1764         } SA_b;
1765     };
1766 
1767     union
1768     {
1769         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
1770 
1771         struct
1772         {
1773             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
1774                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
1775                                            *   The low-order 2 bits are fixed to 1.                                      */
1776         } EA_b;
1777     };
1778 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
1779 
1780 /**
1781  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
1782  */
1783 typedef struct
1784 {
1785     union
1786     {
1787         union
1788         {
1789             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
1790 
1791             struct
1792             {
1793                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1794                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1795                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1796                 uint32_t             : 1;
1797                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1798                 __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1799                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1800                 uint32_t             : 3;
1801                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1802                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
1803                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1804                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1805                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
1806                 uint32_t             : 7;
1807                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
1808                                            *   function. For individual pin functions, see the MPC table                 */
1809                 uint32_t : 3;
1810             } PmnPFS_b;
1811         };
1812 
1813         struct
1814         {
1815             union
1816             {
1817                 struct
1818                 {
1819                     __IM uint16_t RESERVED;
1820 
1821                     union
1822                     {
1823                         __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
1824 
1825                         struct
1826                         {
1827                             __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1828                             __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1829                             __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1830                             uint16_t             : 1;
1831                             __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1832                             __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1833                             __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1834                             uint16_t             : 3;
1835                             __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1836                             __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
1837                             __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1838                             __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1839                         } PmnPFS_HA_b;
1840                     };
1841                 };
1842 
1843                 struct
1844                 {
1845                     __IM uint16_t RESERVED1;
1846                     __IM uint8_t  RESERVED2;
1847 
1848                     union
1849                     {
1850                         __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
1851 
1852                         struct
1853                         {
1854                             __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1855                             __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1856                             __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1857                             uint8_t             : 1;
1858                             __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1859                             __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1860                             __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1861                             uint8_t             : 1;
1862                         } PmnPFS_BY_b;
1863                     };
1864                 };
1865             };
1866         };
1867     };
1868 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
1869 
1870 /**
1871  * @brief R_PFS_PORT [PORT] (Port [0..14])
1872  */
1873 typedef struct
1874 {
1875     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
1876 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
1877 
1878 /**
1879  * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
1880  */
1881 typedef struct
1882 {
1883     __IM uint8_t RESERVED[389];
1884 
1885     union
1886     {
1887         __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
1888 
1889         struct
1890         {
1891             __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
1892             uint8_t             : 7;
1893         } VL1SEL_b;
1894     };
1895 } R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
1896 
1897 /**
1898  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
1899  */
1900 typedef struct
1901 {
1902     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
1903 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
1904 
1905 /**
1906  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
1907  */
1908 typedef struct
1909 {
1910     union
1911     {
1912         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
1913 
1914         struct
1915         {
1916             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
1917             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
1918             uint8_t            : 1;
1919             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
1920             uint8_t            : 1;
1921             __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
1922         } RTCCR_b;
1923     };
1924     __IM uint8_t RESERVED;
1925 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
1926 
1927 /**
1928  * @brief R_RTC_CP [CP] (Capture registers)
1929  */
1930 typedef struct
1931 {
1932     __IM uint8_t RESERVED[2];
1933 
1934     union
1935     {
1936         union
1937         {
1938             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
1939 
1940             struct
1941             {
1942                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
1943                                          *   seconds                                                                   */
1944                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
1945                                          *   seconds                                                                   */
1946                 uint8_t : 1;
1947             } RSEC_b;
1948         };
1949 
1950         union
1951         {
1952             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
1953 
1954             struct
1955             {
1956                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
1957                                            *   value when a time capture event is detected.                              */
1958             } BCNT0_b;
1959         };
1960     };
1961     __IM uint8_t RESERVED1;
1962 
1963     union
1964     {
1965         union
1966         {
1967             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
1968 
1969             struct
1970             {
1971                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
1972                                          *   minutes                                                                   */
1973                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
1974                                          *   minutes                                                                   */
1975                 uint8_t : 1;
1976             } RMIN_b;
1977         };
1978 
1979         union
1980         {
1981             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
1982 
1983             struct
1984             {
1985                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
1986                                            *   value when a time capture event is detected.                              */
1987             } BCNT1_b;
1988         };
1989     };
1990     __IM uint8_t RESERVED2;
1991 
1992     union
1993     {
1994         union
1995         {
1996             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
1997 
1998             struct
1999             {
2000                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
2001                                         *   minutes                                                                   */
2002                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
2003                                         *   minutes                                                                   */
2004                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
2005                 uint8_t         : 1;
2006             } RHR_b;
2007         };
2008 
2009         union
2010         {
2011             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
2012 
2013             struct
2014             {
2015                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
2016                                            *   value when a time capture event is detected.                              */
2017             } BCNT2_b;
2018         };
2019     };
2020     __IM uint8_t RESERVED3[3];
2021 
2022     union
2023     {
2024         union
2025         {
2026             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
2027 
2028             struct
2029             {
2030                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
2031                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
2032                 uint8_t             : 2;
2033             } RDAY_b;
2034         };
2035 
2036         union
2037         {
2038             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
2039 
2040             struct
2041             {
2042                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
2043                                            *   value when a time capture event is detected.                              */
2044             } BCNT3_b;
2045         };
2046     };
2047     __IM uint8_t RESERVED4;
2048 
2049     union
2050     {
2051         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
2052 
2053         struct
2054         {
2055             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
2056             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
2057                                         *   months                                                                    */
2058             uint8_t : 3;
2059         } RMON_b;
2060     };
2061     __IM uint8_t RESERVED5[3];
2062 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
2063 
2064 /**
2065  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2066  */
2067 typedef struct
2068 {
2069     union
2070     {
2071         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
2072 
2073         struct
2074         {
2075             uint16_t             : 8;
2076             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
2077             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
2078             uint16_t             : 6;
2079         } E_b;
2080     };
2081 
2082     union
2083     {
2084         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
2085 
2086         struct
2087         {
2088             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
2089         } N_b;
2090     };
2091 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2092 
2093 /**
2094  * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
2095  */
2096 typedef struct
2097 {
2098     union
2099     {
2100         __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
2101 
2102         struct
2103         {
2104             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
2105             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
2106             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
2107             uint8_t              : 1;
2108             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
2109             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
2110             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
2111             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
2112         } AGTCR_b;
2113     };
2114 
2115     union
2116     {
2117         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
2118 
2119         struct
2120         {
2121             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
2122             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
2123             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
2124             uint8_t              : 1;
2125         } AGTMR1_b;
2126     };
2127 
2128     union
2129     {
2130         __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
2131 
2132         struct
2133         {
2134             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
2135                                         *   ratio                                                                     */
2136             uint8_t           : 4;
2137             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
2138         } AGTMR2_b;
2139     };
2140 
2141     union
2142     {
2143         __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
2144 
2145         struct
2146         {
2147             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2148             uint8_t            : 2;
2149             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2150             uint8_t            : 3;
2151         } AGTIOSEL_ALT_b;
2152     };
2153 
2154     union
2155     {
2156         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
2157 
2158         struct
2159         {
2160             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
2161                                         *   mode.                                                                     */
2162             uint8_t             : 1;
2163             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
2164             uint8_t             : 1;
2165             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
2166             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
2167         } AGTIOC_b;
2168     };
2169 
2170     union
2171     {
2172         __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
2173 
2174         struct
2175         {
2176             uint8_t            : 2;
2177             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
2178             uint8_t            : 5;
2179         } AGTISR_b;
2180     };
2181 
2182     union
2183     {
2184         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
2185 
2186         struct
2187         {
2188             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
2189             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
2190             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
2191             uint8_t              : 1;
2192             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
2193             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
2194             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
2195             uint8_t              : 1;
2196         } AGTCMSR_b;
2197     };
2198 
2199     union
2200     {
2201         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
2202 
2203         struct
2204         {
2205             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2206             uint8_t            : 2;
2207             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2208             uint8_t            : 3;
2209         } AGTIOSEL_b;
2210     };
2211 } R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
2212 
2213 /**
2214  * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
2215  */
2216 typedef struct
2217 {
2218     union
2219     {
2220         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
2221 
2222         struct
2223         {
2224             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
2225                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2226                                         *   counter is forcibly stopped and set to FFFFH.                             */
2227         } AGT_b;
2228     };
2229 
2230     union
2231     {
2232         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
2233 
2234         struct
2235         {
2236             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
2237                                          *   written to the TSTOP bit in the AGTCRn register, set to
2238                                          *   FFFFH                                                                     */
2239         } AGTCMA_b;
2240     };
2241 
2242     union
2243     {
2244         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
2245 
2246         struct
2247         {
2248             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
2249                                          *   written to the TSTOP bit in the AGTCR register, set to
2250                                          *   FFFFH                                                                     */
2251         } AGTCMB_b;
2252     };
2253     __IM uint16_t                 RESERVED;
2254     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
2255 } R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
2256 
2257 /**
2258  * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
2259  */
2260 typedef struct
2261 {
2262     union
2263     {
2264         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
2265 
2266         struct
2267         {
2268             __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
2269                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2270                                         *   counter is forcibly stopped and set to FFFFH.                             */
2271         } AGT_b;
2272     };
2273 
2274     union
2275     {
2276         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
2277 
2278         struct
2279         {
2280             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
2281                                          *   written to the TSTOP bit in the AGTCRn register, set to
2282                                          *   FFFFH                                                                     */
2283         } AGTCMA_b;
2284     };
2285 
2286     union
2287     {
2288         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
2289 
2290         struct
2291         {
2292             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
2293                                          *   written to the TSTOP bit in the AGTCR register, set to
2294                                          *   FFFFH                                                                     */
2295         } AGTCMB_b;
2296     };
2297     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
2298 } R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
2299 
2300 /** @} */ /* End of group Device_Peripheral_clusters */
2301 
2302 /* =========================================================================================================================== */
2303 /* ================                            Device Specific Peripheral Section                             ================ */
2304 /* =========================================================================================================================== */
2305 
2306 /** @addtogroup Device_Peripheral_peripherals
2307  * @{
2308  */
2309 
2310 /* =========================================================================================================================== */
2311 /* ================                                         R_ACMPLP                                          ================ */
2312 /* =========================================================================================================================== */
2313 
2314 /**
2315  * @brief Low-Power Analog Comparator (R_ACMPLP)
2316  */
2317 
2318 typedef struct                         /*!< (@ 0x400F4000) R_ACMPLP Structure                                         */
2319 {
2320     union
2321     {
2322         __IOM uint8_t COMPMDR;         /*!< (@ 0x00000000) ACMPLP Mode Setting Register                               */
2323 
2324         struct
2325         {
2326             __IOM uint8_t C0ENB : 1;   /*!< [0..0] ACMPLP0 Operation Enable                                           */
2327             __IOM uint8_t C0WDE : 1;   /*!< [1..1] ACMPLP0 Window Function Mode Enable                                */
2328             __IOM uint8_t C0VRF : 1;   /*!< [2..2] ACMPLP0 Reference Voltage Selection                                */
2329             __IM uint8_t  C0MON : 1;   /*!< [3..3] ACMPLP0 Monitor Flag                                               */
2330             __IOM uint8_t C1ENB : 1;   /*!< [4..4] ACMPLP1 Operation Enable                                           */
2331             __IOM uint8_t C1WDE : 1;   /*!< [5..5] ACMPLP1 Window Function Mode Enable                                */
2332             __IOM uint8_t C1VRF : 1;   /*!< [6..6] ACMPLP1 Reference Voltage Selection                                */
2333             __IM uint8_t  C1MON : 1;   /*!< [7..7] ACMPLP1 Monitor Flag                                               */
2334         } COMPMDR_b;
2335     };
2336 
2337     union
2338     {
2339         __IOM uint8_t COMPFIR;         /*!< (@ 0x00000001) ACMPLP Filter Control Register                             */
2340 
2341         struct
2342         {
2343             __IOM uint8_t C0FCK : 2;   /*!< [1..0] ACMPLP0 Filter Select                                              */
2344             __IOM uint8_t C0EPO : 1;   /*!< [2..2] ACMPLP0 Edge Polarity Switching                                    */
2345             __IOM uint8_t C0EDG : 1;   /*!< [3..3] ACMPLP0 Edge Detection Selection                                   */
2346             __IOM uint8_t C1FCK : 2;   /*!< [5..4] ACMPLP1 Filter Select                                              */
2347             __IOM uint8_t C1EPO : 1;   /*!< [6..6] ACMPLP1 Edge Polarity Switching                                    */
2348             __IOM uint8_t C1EDG : 1;   /*!< [7..7] ACMPLP1 Edge Detection Selection                                   */
2349         } COMPFIR_b;
2350     };
2351 
2352     union
2353     {
2354         __IOM uint8_t COMPOCR;         /*!< (@ 0x00000002) ACMPLP Output Control Register                             */
2355 
2356         struct
2357         {
2358             uint8_t             : 1;
2359             __IOM uint8_t C0OE  : 1;   /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable                                    */
2360             __IOM uint8_t C0OP  : 1;   /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection                            */
2361             uint8_t             : 2;
2362             __IOM uint8_t C1OE  : 1;   /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable                                    */
2363             __IOM uint8_t C1OP  : 1;   /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection                            */
2364             __IOM uint8_t SPDMD : 1;   /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection                                    */
2365         } COMPOCR_b;
2366     };
2367     __IM uint8_t RESERVED;
2368 
2369     union
2370     {
2371         __IOM uint8_t COMPSEL0;        /*!< (@ 0x00000004) Comparator Input Select Register                           */
2372 
2373         struct
2374         {
2375             __IOM uint8_t IVCMP0 : 3;  /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection                                   */
2376             uint8_t              : 1;
2377             __IOM uint8_t IVCMP1 : 3;  /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection                                   */
2378             uint8_t              : 1;
2379         } COMPSEL0_b;
2380     };
2381 
2382     union
2383     {
2384         __IOM uint8_t COMPSEL1;        /*!< (@ 0x00000005) Comparator Reference voltage Select Register               */
2385 
2386         struct
2387         {
2388             __IOM uint8_t IVREF0 : 3;  /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection                       */
2389             uint8_t              : 1;
2390             __IOM uint8_t IVREF1 : 3;  /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection                        */
2391             __IOM uint8_t C1VRF2 : 1;  /*!< [7..7] ACMPLP1 Reference Voltage Selection                                */
2392         } COMPSEL1_b;
2393     };
2394 } R_ACMPLP_Type;                       /*!< Size = 6 (0x6)                                                            */
2395 
2396 /* =========================================================================================================================== */
2397 /* ================                                          R_ADC0                                           ================ */
2398 /* =========================================================================================================================== */
2399 
2400 /**
2401  * @brief A/D Converter (R_ADC0)
2402  */
2403 
2404 typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure                                           */
2405 {
2406     union
2407     {
2408         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
2409 
2410         struct
2411         {
2412             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
2413                                         *   input channel for double triggered operation. The setting
2414                                         *   is only effective while double trigger mode is selected.                  */
2415             uint16_t              : 1;
2416             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
2417             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
2418             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
2419             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
2420             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
2421             uint16_t              : 1;
2422             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
2423             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
2424             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
2425         } ADCSR_b;
2426     };
2427 
2428     union
2429     {
2430         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
2431 
2432         struct
2433         {
2434             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
2435                                         *   '1' while scanning.                                                       */
2436             uint8_t              : 6;
2437             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
2438         } ADREF_b;
2439     };
2440 
2441     union
2442     {
2443         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
2444 
2445         struct
2446         {
2447             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
2448             uint8_t             : 7;
2449         } ADEXREF_b;
2450     };
2451 
2452     union
2453     {
2454         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
2455 
2456         struct
2457         {
2458             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
2459             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
2460             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
2461             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
2462             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
2463             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
2464             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
2465             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
2466             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
2467             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
2468             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
2469             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
2470             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
2471             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
2472             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
2473             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
2474         } ADANSA_b[2];
2475     };
2476 
2477     union
2478     {
2479         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
2480                                         *                  Select Register                                            */
2481 
2482         struct
2483         {
2484             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
2485             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
2486             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
2487             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
2488             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
2489             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
2490             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
2491             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
2492             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
2493             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
2494             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
2495             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
2496             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
2497             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
2498             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
2499             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
2500         } ADADS_b[2];
2501     };
2502 
2503     union
2504     {
2505         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
2506                                         *                  Register                                                   */
2507 
2508         struct
2509         {
2510             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
2511                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
2512                                         *   average mode is selected by setting the ADADC.AVEE bit
2513                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
2514                                         *   = 010b)                                                                   */
2515             uint8_t            : 4;
2516             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
2517                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
2518                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
2519                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
2520                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
2521                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
2522                                         *   bit to 1, do not set the addition count to three times
2523                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
2524         } ADADC_b;
2525     };
2526     __IM uint8_t RESERVED;
2527 
2528     union
2529     {
2530         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
2531 
2532         struct
2533         {
2534             uint16_t               : 1;
2535             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
2536             uint16_t               : 1;
2537             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
2538             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
2539             uint16_t               : 2;
2540             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
2541             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
2542             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
2543             uint16_t               : 2;
2544             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
2545             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
2546         } ADCER_b;
2547     };
2548 
2549     union
2550     {
2551         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
2552 
2553         struct
2554         {
2555             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
2556                                         *   the A/D conversion start trigger for group B in group scan
2557                                         *   mode.                                                                     */
2558             uint16_t            : 2;
2559             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
2560                                         *   start trigger in single scan mode and continuous mode.
2561                                         *   In group scan mode, the A/D conversion start trigger for
2562                                         *   group A is selected.                                                      */
2563             uint16_t : 2;
2564         } ADSTRGR_b;
2565     };
2566 
2567     union
2568     {
2569         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
2570 
2571         struct
2572         {
2573             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
2574                                         *   Mode Select                                                               */
2575             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
2576                                         *   Mode Select                                                               */
2577             uint16_t            : 6;
2578             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
2579             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
2580             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
2581                                         *   Group B in group scan mode.                                               */
2582             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
2583                                         *   Group B in group scan mode.                                               */
2584             uint16_t             : 2;
2585             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
2586             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
2587         } ADEXICR_b;
2588     };
2589 
2590     union
2591     {
2592         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
2593 
2594         struct
2595         {
2596             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
2597             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
2598             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
2599             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
2600             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
2601             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
2602             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
2603             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
2604             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
2605             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
2606             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
2607             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
2608             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
2609             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
2610             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
2611             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
2612         } ADANSB_b[2];
2613     };
2614 
2615     union
2616     {
2617         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
2618 
2619         struct
2620         {
2621             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2622                                          *   result of A/D conversion in response to the second trigger
2623                                          *   in double trigger mode.                                                   */
2624         } ADDBLDR_b;
2625     };
2626 
2627     union
2628     {
2629         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
2630 
2631         struct
2632         {
2633             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2634                                         *   A/D conversion result of temperature sensor output.                       */
2635         } ADTSDR_b;
2636     };
2637 
2638     union
2639     {
2640         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
2641 
2642         struct
2643         {
2644             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2645                                         *   A/D result of internal reference voltage.                                 */
2646         } ADOCDR_b;
2647     };
2648 
2649     union
2650     {
2651         union
2652         {
2653             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
2654 
2655             struct
2656             {
2657                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified). The format for
2658                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2659                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
2660             } ADRD_RIGHT_b;
2661         };
2662 
2663         union
2664         {
2665             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
2666 
2667             struct
2668             {
2669                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
2670                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (left-justified). The format for
2671                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2672             } ADRD_LEFT_b;
2673         };
2674     };
2675 
2676     union
2677     {
2678         __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
2679 
2680         struct
2681         {
2682             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
2683                                         *   storing the result of A/D conversion.                                     */
2684         } ADDR_b[29];
2685     };
2686     __IM uint16_t RESERVED1;
2687     __IM uint32_t RESERVED2;
2688     __IM uint16_t RESERVED3;
2689 
2690     union
2691     {
2692         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
2693 
2694         struct
2695         {
2696             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
2697         } ADAMPOFF_b;
2698     };
2699 
2700     union
2701     {
2702         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
2703 
2704         struct
2705         {
2706             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
2707             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
2708             uint8_t            : 6;
2709         } ADTSTPR_b;
2710     };
2711 
2712     union
2713     {
2714         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
2715 
2716         struct
2717         {
2718             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
2719             uint16_t              : 3;
2720             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
2721             uint16_t              : 2;
2722             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
2723         } ADDDACER_b;
2724     };
2725 
2726     union
2727     {
2728         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
2729 
2730         struct
2731         {
2732             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
2733                                         *   Setting Set the sampling time (4 to 255 states)                           */
2734             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
2735             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
2736             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
2737             uint16_t              : 5;
2738         } ADSHCR_b;
2739     };
2740 
2741     union
2742     {
2743         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
2744 
2745         struct
2746         {
2747             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
2748                                         *   only for channel.                                                         */
2749             uint16_t             : 1;
2750             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
2751             uint16_t             : 2;
2752             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
2753                                         *   for adjustment to hardening of process.                                   */
2754             uint16_t              : 1;
2755             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
2756                                         *   power save bit for A/D hard macro to hardening of process.                */
2757             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
2758                                         *   bit for A/D hard macro to hardening of process.                           */
2759             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
2760                                         *   bit for A/D hard macro to hardening of process.                           */
2761         } ADEXTSTR_b;
2762     };
2763 
2764     union
2765     {
2766         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
2767 
2768         struct
2769         {
2770             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
2771             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
2772                                            *   amplifier test.Refreshing the pressure switch that opens
2773                                            *   for the DAC output voltage charge period when the amplifier
2774                                            *   of the S&H circuit is tested only for the channel is set.                 */
2775             uint16_t            : 1;
2776             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
2777                                            *   bit.                                                                      */
2778             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
2779                                            *   bit                                                                       */
2780             uint16_t                 : 1;
2781             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
2782                                            *   module Details are described to the bit explanation.                      */
2783             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
2784                                            *   bit explanation.                                                          */
2785         } ADTSTRA_b;
2786     };
2787 
2788     union
2789     {
2790         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
2791 
2792         struct
2793         {
2794             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
2795                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
2796             uint16_t : 1;
2797         } ADTSTRB_b;
2798     };
2799 
2800     union
2801     {
2802         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
2803 
2804         struct
2805         {
2806             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
2807                                          *   analog module.                                                            */
2808             uint16_t               : 4;
2809             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
2810             uint16_t               : 3;
2811         } ADTSTRC_b;
2812     };
2813 
2814     union
2815     {
2816         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
2817 
2818         struct
2819         {
2820             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
2821                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
2822             uint16_t : 15;
2823         } ADTSTRD_b;
2824     };
2825 
2826     union
2827     {
2828         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
2829 
2830         struct
2831         {
2832             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
2833             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
2834             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
2835             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
2836             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
2837             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
2838             uint16_t              : 10;
2839         } ADSWTSTR0_b;
2840     };
2841 
2842     union
2843     {
2844         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
2845 
2846         struct
2847         {
2848             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
2849             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
2850             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
2851             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
2852             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
2853             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
2854             uint16_t              : 10;
2855         } ADSWTSTR1_b;
2856     };
2857 
2858     union
2859     {
2860         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
2861 
2862         struct
2863         {
2864             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
2865                                           *   (ANEX0 switch)                                                            */
2866             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
2867                                           *   (ANEX1 switch).                                                           */
2868             uint16_t                : 2;
2869             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
2870             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
2871             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
2872             uint16_t                : 1;
2873             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
2874             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
2875             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
2876             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
2877             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
2878             uint16_t                : 3;
2879         } ADSWTSTR2_b;
2880     };
2881     __IM uint16_t RESERVED4;
2882 
2883     union
2884     {
2885         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
2886 
2887         struct
2888         {
2889             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
2890             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
2891             uint8_t              : 3;
2892         } ADDISCR_b;
2893     };
2894 
2895     union
2896     {
2897         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
2898 
2899         struct
2900         {
2901             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
2902                                         *   the pressure switch in A/D analog module is set.                          */
2903             uint8_t               : 1;
2904             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
2905             uint8_t               : 1;
2906         } ADSWCR_b;
2907     };
2908 
2909     union
2910     {
2911         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
2912 
2913         struct
2914         {
2915             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
2916                                         *   Select                                                                    */
2917             uint8_t : 7;
2918         } ADSHMSR_b;
2919     };
2920 
2921     union
2922     {
2923         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
2924 
2925         struct
2926         {
2927             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
2928             uint8_t            : 6;
2929         } ADICR_b;
2930     };
2931 
2932     union
2933     {
2934         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
2935 
2936         struct
2937         {
2938             uint8_t             : 1;
2939             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
2940             uint8_t             : 6;
2941         } ADACSR_b;
2942     };
2943     __IM uint8_t RESERVED5;
2944 
2945     union
2946     {
2947         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
2948 
2949         struct
2950         {
2951             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
2952                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
2953                                          *   set to 01b (group scan mode). If the bits are set to any
2954                                          *   other values, proper operation is not guaranteed.                         */
2955             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
2956                                          *   when PGS = 0.)                                                            */
2957             uint16_t               : 6;
2958             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
2959             uint16_t               : 6;
2960             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
2961                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
2962                                          *   has been set to 1, single scan is performed continuously
2963                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
2964         } ADGSPCR_b;
2965     };
2966 
2967     union
2968     {
2969         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
2970                                         *                  Scan)                                                      */
2971 
2972         struct
2973         {
2974             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
2975             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
2976         } ADGSCS_b;
2977     };
2978 
2979     union
2980     {
2981         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
2982 
2983         struct
2984         {
2985             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
2986                                           *   the result of A/D conversion in response to the respective
2987                                           *   triggers during extended operation in double trigger mode.                */
2988         } ADDBLDRA_b;
2989     };
2990 
2991     union
2992     {
2993         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
2994 
2995         struct
2996         {
2997             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
2998                                           *   the result of A/D conversion in response to the respective
2999                                           *   triggers during extended operation in double trigger mode.                */
3000         } ADDBLDRB_b;
3001     };
3002 
3003     union
3004     {
3005         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
3006 
3007         struct
3008         {
3009             uint8_t             : 7;
3010             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
3011         } ADSER_b;
3012     };
3013     __IM uint8_t RESERVED6;
3014 
3015     union
3016     {
3017         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
3018                                         *                  Control Register                                           */
3019 
3020         struct
3021         {
3022             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
3023             uint8_t             : 2;
3024             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
3025             uint8_t             : 2;
3026             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
3027         } ADHVREFCNT_b;
3028     };
3029     __IM uint8_t RESERVED7;
3030 
3031     union
3032     {
3033         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
3034                                         *                  Register                                                   */
3035 
3036         struct
3037         {
3038             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
3039                                         *   result.This bit is valid when both window A operation and
3040                                         *   window B operation are enabled.                                           */
3041             uint8_t              : 3;
3042             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
3043             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
3044             uint8_t              : 2;
3045         } ADWINMON_b;
3046     };
3047     __IM uint8_t  RESERVED8;
3048     __IM uint16_t RESERVED9;
3049 
3050     union
3051     {
3052         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
3053 
3054         struct
3055         {
3056             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
3057                                         *   are valid when both window A and window B are enabled (CMPAE
3058                                         *   = 1 and CMPBE = 1).                                                       */
3059             uint16_t              : 7;
3060             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
3061             uint16_t              : 1;
3062             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
3063             uint16_t              : 1;
3064             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
3065             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
3066             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
3067         } ADCMPCR_b;
3068     };
3069 
3070     union
3071     {
3072         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
3073                                         *                  Select Register                                            */
3074 
3075         struct
3076         {
3077             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
3078             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
3079             uint8_t              : 6;
3080         } ADCMPANSER_b;
3081     };
3082 
3083     union
3084     {
3085         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
3086                                         *                  Comparison Condition Setting Register                      */
3087 
3088         struct
3089         {
3090             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
3091                                         *   Condition Select                                                          */
3092             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
3093                                         *   Select                                                                    */
3094             uint8_t : 6;
3095         } ADCMPLER_b;
3096     };
3097 
3098     union
3099     {
3100         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
3101                                           *                  Register                                                   */
3102 
3103         struct
3104         {
3105             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
3106             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
3107             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
3108             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
3109             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
3110             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
3111             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
3112             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
3113             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
3114             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
3115             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
3116             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
3117             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
3118             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
3119             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
3120             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
3121         } ADCMPANSR_b[2];
3122     };
3123 
3124     union
3125     {
3126         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
3127                                            *                  Setting Register                                           */
3128 
3129         struct
3130         {
3131             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
3132             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
3133             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
3134             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
3135             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
3136             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
3137             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
3138             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
3139             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
3140             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
3141             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
3142             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
3143             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
3144             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
3145             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
3146             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
3147         } ADCMPLR_b[2];
3148     };
3149 
3150     union
3151     {
3152         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
3153                                            *                  Setting Register                                           */
3154 
3155         struct
3156         {
3157             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
3158                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
3159                                            *   level of window A.                                                        */
3160         } ADCMPDR0_b;
3161     };
3162 
3163     union
3164     {
3165         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
3166                                            *                  Setting Register                                           */
3167 
3168         struct
3169         {
3170             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
3171                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
3172                                            *   level of window A..                                                       */
3173         } ADCMPDR1_b;
3174     };
3175 
3176     union
3177     {
3178         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
3179                                             *                  Register                                                   */
3180 
3181         struct
3182         {
3183             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
3184             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
3185             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
3186             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
3187             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
3188             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
3189             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
3190             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
3191             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
3192             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
3193             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
3194             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
3195             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
3196             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
3197             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
3198             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
3199         } ADCMPSR_b[2];
3200     };
3201 
3202     union
3203     {
3204         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
3205                                          *                  Channel Status Register                                    */
3206 
3207         struct
3208         {
3209             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
3210                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3211                                          *   this bit indicates the temperature sensor output comparison
3212                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3213                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3214                                          *   time.                                                                     */
3215             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
3216                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3217                                          *   this bit indicates the temperature sensor output comparison
3218                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3219                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3220                                          *   time.                                                                     */
3221             uint8_t : 6;
3222         } ADCMPSER_b;
3223     };
3224     __IM uint8_t RESERVED10;
3225 
3226     union
3227     {
3228         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
3229                                         *                  Register                                                   */
3230 
3231         struct
3232         {
3233             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
3234                                         *   compares it on the condition of compare window B is selected.             */
3235             uint8_t             : 1;
3236             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
3237         } ADCMPBNSR_b;
3238     };
3239     __IM uint8_t RESERVED11;
3240 
3241     union
3242     {
3243         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
3244                                            *                  Setting Register                                           */
3245 
3246         struct
3247         {
3248             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
3249                                            *   used to set the lower level of the window B.                              */
3250         } ADWINLLB_b;
3251     };
3252 
3253     union
3254     {
3255         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
3256                                            *                  Setting Register                                           */
3257 
3258         struct
3259         {
3260             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
3261                                            *   used to set the higher level of the window B.                             */
3262         } ADWINULB_b;
3263     };
3264 
3265     union
3266     {
3267         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
3268 
3269         struct
3270         {
3271             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
3272                                         *   the comparative result of CH (AN000-AN027, temperature
3273                                         *   sensor, and internal reference voltage) made the object
3274                                         *   of window B relation condition.                                           */
3275             uint8_t : 7;
3276         } ADCMPBSR_b;
3277     };
3278     __IM uint8_t  RESERVED12;
3279     __IM uint16_t RESERVED13;
3280 
3281     union
3282     {
3283         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
3284 
3285         struct
3286         {
3287             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3288                                         *   registers that sequentially store all A/D converted values.
3289                                         *   The automatic clear function is not applied to these registers.           */
3290         } ADBUF0_b;
3291     };
3292 
3293     union
3294     {
3295         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
3296 
3297         struct
3298         {
3299             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3300                                         *   registers that sequentially store all A/D converted values.
3301                                         *   The automatic clear function is not applied to these registers.           */
3302         } ADBUF1_b;
3303     };
3304 
3305     union
3306     {
3307         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
3308 
3309         struct
3310         {
3311             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3312                                         *   registers that sequentially store all A/D converted values.
3313                                         *   The automatic clear function is not applied to these registers.           */
3314         } ADBUF2_b;
3315     };
3316 
3317     union
3318     {
3319         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
3320 
3321         struct
3322         {
3323             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3324                                         *   registers that sequentially store all A/D converted values.
3325                                         *   The automatic clear function is not applied to these registers.           */
3326         } ADBUF3_b;
3327     };
3328 
3329     union
3330     {
3331         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
3332 
3333         struct
3334         {
3335             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3336                                         *   registers that sequentially store all A/D converted values.
3337                                         *   The automatic clear function is not applied to these registers.           */
3338         } ADBUF4_b;
3339     };
3340 
3341     union
3342     {
3343         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
3344 
3345         struct
3346         {
3347             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3348                                         *   registers that sequentially store all A/D converted values.
3349                                         *   The automatic clear function is not applied to these registers.           */
3350         } ADBUF5_b;
3351     };
3352 
3353     union
3354     {
3355         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
3356 
3357         struct
3358         {
3359             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3360                                         *   registers that sequentially store all A/D converted values.
3361                                         *   The automatic clear function is not applied to these registers.           */
3362         } ADBUF6_b;
3363     };
3364 
3365     union
3366     {
3367         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
3368 
3369         struct
3370         {
3371             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3372                                         *   registers that sequentially store all A/D converted values.
3373                                         *   The automatic clear function is not applied to these registers.           */
3374         } ADBUF7_b;
3375     };
3376 
3377     union
3378     {
3379         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
3380 
3381         struct
3382         {
3383             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3384                                         *   registers that sequentially store all A/D converted values.
3385                                         *   The automatic clear function is not applied to these registers.           */
3386         } ADBUF8_b;
3387     };
3388 
3389     union
3390     {
3391         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
3392 
3393         struct
3394         {
3395             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3396                                         *   registers that sequentially store all A/D converted values.
3397                                         *   The automatic clear function is not applied to these registers.           */
3398         } ADBUF9_b;
3399     };
3400 
3401     union
3402     {
3403         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
3404 
3405         struct
3406         {
3407             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3408                                         *   registers that sequentially store all A/D converted values.
3409                                         *   The automatic clear function is not applied to these registers.           */
3410         } ADBUF10_b;
3411     };
3412 
3413     union
3414     {
3415         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
3416 
3417         struct
3418         {
3419             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3420                                         *   registers that sequentially store all A/D converted values.
3421                                         *   The automatic clear function is not applied to these registers.           */
3422         } ADBUF11_b;
3423     };
3424 
3425     union
3426     {
3427         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
3428 
3429         struct
3430         {
3431             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3432                                         *   registers that sequentially store all A/D converted values.
3433                                         *   The automatic clear function is not applied to these registers.           */
3434         } ADBUF12_b;
3435     };
3436 
3437     union
3438     {
3439         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
3440 
3441         struct
3442         {
3443             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3444                                         *   registers that sequentially store all A/D converted values.
3445                                         *   The automatic clear function is not applied to these registers.           */
3446         } ADBUF13_b;
3447     };
3448 
3449     union
3450     {
3451         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
3452 
3453         struct
3454         {
3455             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3456                                         *   registers that sequentially store all A/D converted values.
3457                                         *   The automatic clear function is not applied to these registers.           */
3458         } ADBUF14_b;
3459     };
3460 
3461     union
3462     {
3463         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
3464 
3465         struct
3466         {
3467             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3468                                         *   registers that sequentially store all A/D converted values.
3469                                         *   The automatic clear function is not applied to these registers.           */
3470         } ADBUF15_b;
3471     };
3472 
3473     union
3474     {
3475         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
3476 
3477         struct
3478         {
3479             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
3480             uint8_t             : 7;
3481         } ADBUFEN_b;
3482     };
3483     __IM uint8_t RESERVED14;
3484 
3485     union
3486     {
3487         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
3488 
3489         struct
3490         {
3491             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
3492                                         *   data buffer to which the next A/D converted data is transferred.          */
3493             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
3494             uint8_t             : 3;
3495         } ADBUFPTR_b;
3496     };
3497     __IM uint8_t  RESERVED15;
3498     __IM uint32_t RESERVED16[2];
3499     __IM uint8_t  RESERVED17;
3500 
3501     union
3502     {
3503         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
3504 
3505         struct
3506         {
3507             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
3508         } ADSSTRL_b;
3509     };
3510 
3511     union
3512     {
3513         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
3514 
3515         struct
3516         {
3517             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
3518         } ADSSTRT_b;
3519     };
3520 
3521     union
3522     {
3523         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
3524 
3525         struct
3526         {
3527             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
3528         } ADSSTRO_b;
3529     };
3530 
3531     union
3532     {
3533         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
3534 
3535         struct
3536         {
3537             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
3538         } ADSSTR_b[16];
3539     };
3540 
3541     union
3542     {
3543         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
3544 
3545         struct
3546         {
3547             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
3548             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
3549             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
3550             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
3551             uint16_t             : 12;
3552         } ADANIM_b;
3553     };
3554 
3555     union
3556     {
3557         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
3558 
3559         struct
3560         {
3561             uint8_t              : 6;
3562             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
3563             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
3564         } ADCALEXE_b;
3565     };
3566     __IM uint8_t RESERVED18;
3567 
3568     union
3569     {
3570         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
3571                                           *                  Register                                                   */
3572 
3573         struct
3574         {
3575             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
3576             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
3577             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
3578             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
3579             uint8_t                 : 2;
3580             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
3581         } VREFAMPCNT_b;
3582     };
3583     __IM uint8_t  RESERVED19;
3584     __IM uint16_t RESERVED20;
3585 
3586     union
3587     {
3588         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
3589 
3590         struct
3591         {
3592             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
3593         } ADRD_b;
3594     };
3595 
3596     union
3597     {
3598         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
3599 
3600         struct
3601         {
3602             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
3603             uint8_t             : 6;
3604         } ADRST_b;
3605     };
3606     __IM uint8_t  RESERVED21;
3607     __IM uint32_t RESERVED22[41];
3608 
3609     union
3610     {
3611         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
3612 
3613         struct
3614         {
3615             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
3616             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
3617             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
3618             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
3619             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
3620             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
3621             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
3622             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
3623             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
3624             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
3625             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
3626             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
3627             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
3628             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
3629             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
3630             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
3631         } ADPGACR_b;
3632     };
3633 
3634     union
3635     {
3636         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
3637                                           *                  Register 0                                                 */
3638 
3639         struct
3640         {
3641             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
3642                                           *   b) when the shingle end is input and each PGA P000 is set.
3643                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
3644                                           *   sets the gain magnification when the differential motion
3645                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
3646             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
3647                                           *   b) when the shingle end is input and each PGA P001 is set.
3648                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
3649                                           *   sets the gain magnification when the differential motion
3650                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
3651             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
3652                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
3653                                           *   each PGA P002 is set. When the differential motion is input,
3654                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
3655                                           *   the differential motion is input by the combination with
3656                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
3657             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
3658                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
3659                                           *   each PGA P003 is set. When the differential motion is input,
3660                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
3661                                           *   the differential motion is input by the combination with
3662                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
3663         } ADPGAGS0_b;
3664     };
3665     __IM uint32_t RESERVED23[3];
3666 
3667     union
3668     {
3669         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
3670                                          *                  Input Control Register                                     */
3671 
3672         struct
3673         {
3674             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
3675                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
3676             uint16_t               : 1;
3677             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
3678             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
3679                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
3680             uint16_t               : 1;
3681             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
3682             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
3683                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
3684             uint16_t               : 1;
3685             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
3686             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
3687                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
3688             uint16_t               : 1;
3689             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
3690         } ADPGADCR0_b;
3691     };
3692     __IM uint16_t RESERVED24;
3693 
3694     union
3695     {
3696         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
3697                                         *                  Input Bias Select Register 0                               */
3698 
3699         struct
3700         {
3701             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
3702                                         *   SelectNOTE: This bit selects the input bias voltage value
3703                                         *   when differential inputs are used.                                        */
3704             uint8_t : 7;
3705         } ADPGADBS0_b;
3706     };
3707 
3708     union
3709     {
3710         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
3711                                         *                  Input Bias Select Register 1                               */
3712 
3713         struct
3714         {
3715             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
3716                                         *   This bit selects the input bias voltage value when differential
3717                                         *   inputs are used.                                                          */
3718             uint8_t : 7;
3719         } ADPGADBS1_b;
3720     };
3721     __IM uint16_t RESERVED25;
3722     __IM uint32_t RESERVED26[10];
3723 
3724     union
3725     {
3726         __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
3727 
3728         struct
3729         {
3730             __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
3731             uint32_t              : 13;
3732             __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
3733             uint32_t              : 12;
3734         } ADREFMON_b;
3735     };
3736 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
3737 
3738 /* =========================================================================================================================== */
3739 /* ================                                          R_PSCU                                           ================ */
3740 /* =========================================================================================================================== */
3741 
3742 /**
3743  * @brief Peripheral Security Control Unit (R_PSCU)
3744  */
3745 
3746 typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure                                           */
3747 {
3748     __IM uint32_t RESERVED;
3749 
3750     union
3751     {
3752         __IOM uint32_t PSARB;           /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
3753 
3754         struct
3755         {
3756             __IOM uint32_t PSARB0  : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution              */
3757             __IOM uint32_t PSARB1  : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution               */
3758             __IOM uint32_t PSARB2  : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution               */
3759             __IOM uint32_t PSARB3  : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution                */
3760             __IOM uint32_t PSARB4  : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution                */
3761             __IOM uint32_t PSARB5  : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution               */
3762             __IM uint32_t  PSARB6  : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution               */
3763             __IOM uint32_t PSARB7  : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution               */
3764             __IOM uint32_t PSARB8  : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution               */
3765             __IOM uint32_t PSARB9  : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution               */
3766             uint32_t               : 1;
3767             __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution           */
3768             __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution           */
3769             uint32_t               : 2;
3770             __IM uint32_t PSARB15  : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
3771                                          *   bit security attribution                                                  */
3772             __IM uint32_t  PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution            */
3773             __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution            */
3774             __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution           */
3775             __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution           */
3776             uint32_t               : 2;
3777             __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution            */
3778             __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution            */
3779             __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution            */
3780             __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution            */
3781             __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution            */
3782             __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution            */
3783             __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution            */
3784             __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution            */
3785             __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution            */
3786             __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution            */
3787         } PSARB_b;
3788     };
3789 
3790     union
3791     {
3792         __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
3793 
3794         struct
3795         {
3796             __IOM uint32_t PSARC0  : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution                */
3797             __IOM uint32_t PSARC1  : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution                */
3798             uint32_t               : 1;
3799             __IOM uint32_t PSARC3  : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution               */
3800             __IOM uint32_t PSARC4  : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution              */
3801             uint32_t               : 3;
3802             __IOM uint32_t PSARC8  : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution              */
3803             uint32_t               : 3;
3804             __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution           */
3805             __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution             */
3806             uint32_t               : 6;
3807             __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution             */
3808             uint32_t               : 6;
3809             __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution          */
3810             uint32_t               : 3;
3811             __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution            */
3812         } PSARC_b;
3813     };
3814 
3815     union
3816     {
3817         __IOM uint32_t PSARD;           /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
3818 
3819         struct
3820         {
3821             __IOM uint32_t PSARD0  : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution               */
3822             __IOM uint32_t PSARD1  : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution               */
3823             __IOM uint32_t PSARD2  : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution               */
3824             __IOM uint32_t PSARD3  : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution               */
3825             uint32_t               : 7;
3826             __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution            */
3827             __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution            */
3828             __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution            */
3829             __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution            */
3830             __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution            */
3831             __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution            */
3832             uint32_t               : 2;
3833             __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution          */
3834             __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution          */
3835             uint32_t               : 1;
3836             __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution             */
3837             uint32_t               : 2;
3838             __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution         */
3839             __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution         */
3840             __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution         */
3841             __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution         */
3842             __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution          */
3843             uint32_t               : 2;
3844         } PSARD_b;
3845     };
3846 
3847     union
3848     {
3849         __IOM uint32_t PSARE;           /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
3850 
3851         struct
3852         {
3853             __IOM uint32_t PSARE0  : 1; /*!< [0..0] WDT security attribution                                           */
3854             __IOM uint32_t PSARE1  : 1; /*!< [1..1] IWDT security attribution                                          */
3855             __IOM uint32_t PSARE2  : 1; /*!< [2..2] RTC security attribution                                           */
3856             uint32_t               : 11;
3857             __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
3858             __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
3859             uint32_t               : 6;
3860             __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
3861             __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
3862             __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
3863             __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
3864             __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
3865             __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
3866             __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
3867             __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
3868             __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
3869             __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
3870         } PSARE_b;
3871     };
3872 
3873     union
3874     {
3875         __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
3876 
3877         struct
3878         {
3879             __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
3880             __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
3881             __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
3882             __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
3883             __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution                     */
3884             uint32_t              : 27;
3885         } MSSAR_b;
3886     };
3887 
3888     union
3889     {
3890         __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
3891                                         *                  A                                                          */
3892 
3893         struct
3894         {
3895             uint32_t            : 15;
3896             __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
3897             uint32_t            : 8;
3898         } CFSAMONA_b;
3899     };
3900 
3901     union
3902     {
3903         __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
3904                                         *                  B                                                          */
3905 
3906         struct
3907         {
3908             uint32_t            : 10;
3909             __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
3910             uint32_t            : 8;
3911         } CFSAMONB_b;
3912     };
3913 
3914     union
3915     {
3916         __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
3917 
3918         struct
3919         {
3920             uint32_t           : 10;
3921             __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
3922             uint32_t           : 16;
3923         } DFSAMON_b;
3924     };
3925 
3926     union
3927     {
3928         __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
3929 
3930         struct
3931         {
3932             uint32_t           : 13;
3933             __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
3934             uint32_t           : 11;
3935         } SSAMONA_b;
3936     };
3937 
3938     union
3939     {
3940         __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
3941 
3942         struct
3943         {
3944             uint32_t           : 10;
3945             __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
3946             uint32_t           : 11;
3947         } SSAMONB_b;
3948     };
3949 
3950     union
3951     {
3952         __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
3953 
3954         struct
3955         {
3956             __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
3957             uint32_t             : 28;
3958         } DLMMON_b;
3959     };
3960 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
3961 
3962 /* =========================================================================================================================== */
3963 /* ================                                           R_BUS                                           ================ */
3964 /* =========================================================================================================================== */
3965 
3966 /**
3967  * @brief Bus Interface (R_BUS)
3968  */
3969 
3970 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
3971 {
3972     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
3973     __IM uint32_t        RESERVED[480];
3974     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
3975 
3976     union
3977     {
3978         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
3979 
3980         struct
3981         {
3982             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
3983             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
3984             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
3985             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
3986             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
3987             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
3988             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
3989             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
3990             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
3991             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
3992             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3993             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3994             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3995             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3996             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3997             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3998         } CSRECEN_b;
3999     };
4000     __IM uint16_t          RESERVED1;
4001     __IM uint32_t          RESERVED2[223];
4002     __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
4003     __IM uint32_t          RESERVED3[235];
4004 
4005     union
4006     {
4007         __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
4008         __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
4009     };
4010     __IM uint32_t RESERVED4[58];
4011 
4012     union
4013     {
4014         union
4015         {
4016             __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */
4017 
4018             struct
4019             {
4020                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
4021                 uint32_t            : 31;
4022             } BUSMABT_b;
4023         };
4024         __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
4025     };
4026     __IM uint32_t RESERVED5[46];
4027 
4028     union
4029     {
4030         __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
4031         __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
4032     };
4033     __IM uint32_t RESERVED6[33];
4034 
4035     union
4036     {
4037         __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */
4038 
4039         struct
4040         {
4041             __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
4042             uint32_t                : 2;
4043             __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
4044             uint32_t                : 12;
4045             __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
4046             uint32_t                : 15;
4047         } BUSDIVBYP_b;
4048     };
4049     __IM uint32_t RESERVED7[63];
4050 
4051     union
4052     {
4053         __IOM uint16_t BUSTHRPUT;      /*!< (@ 0x00001400) Graphic Bus Throughput Control Register                    */
4054 
4055         struct
4056         {
4057             __IOM uint16_t DIS : 1;    /*!< [0..0] Bandwidth Control Function                                         */
4058             uint16_t           : 15;
4059         } BUSTHRPUT_b;
4060     };
4061     __IM uint16_t            RESERVED8;
4062     __IM uint32_t            RESERVED9[255];
4063     __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
4064     __IM uint32_t            RESERVED10[16];
4065 
4066     union
4067     {
4068         __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
4069         __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
4070                                               *                  and Read/Write Status registers.                           */
4071     };
4072     __IM uint32_t RESERVED11[28];
4073 
4074     union
4075     {
4076         __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
4077         __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
4078     };
4079     __IM uint32_t           RESERVED12[16];
4080     __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
4081     __IM uint32_t           RESERVED13[5];
4082     __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
4083 } R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */
4084 
4085 /* =========================================================================================================================== */
4086 /* ================                                           R_CAC                                           ================ */
4087 /* =========================================================================================================================== */
4088 
4089 /**
4090  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
4091  */
4092 
4093 typedef struct                         /*!< (@ 0x40083600) R_CAC Structure                                            */
4094 {
4095     union
4096     {
4097         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
4098 
4099         struct
4100         {
4101             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
4102             uint8_t            : 7;
4103         } CACR0_b;
4104     };
4105 
4106     union
4107     {
4108         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
4109 
4110         struct
4111         {
4112             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
4113             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
4114             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
4115             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
4116         } CACR1_b;
4117     };
4118 
4119     union
4120     {
4121         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
4122 
4123         struct
4124         {
4125             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
4126             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
4127             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
4128                                         *   Select                                                                    */
4129             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
4130         } CACR2_b;
4131     };
4132 
4133     union
4134     {
4135         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
4136 
4137         struct
4138         {
4139             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
4140             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
4141             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
4142             uint8_t              : 1;
4143             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
4144             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
4145             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
4146             uint8_t              : 1;
4147         } CAICR_b;
4148     };
4149 
4150     union
4151     {
4152         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
4153 
4154         struct
4155         {
4156             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
4157             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
4158             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
4159             uint8_t            : 5;
4160         } CASTR_b;
4161     };
4162     __IM uint8_t RESERVED;
4163 
4164     union
4165     {
4166         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
4167 
4168         struct
4169         {
4170             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
4171                                          *   the upper-limit value of the frequency.                                   */
4172         } CAULVR_b;
4173     };
4174 
4175     union
4176     {
4177         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
4178 
4179         struct
4180         {
4181             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
4182                                          *   the lower-limit value of the frequency.                                   */
4183         } CALLVR_b;
4184     };
4185 
4186     union
4187     {
4188         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
4189 
4190         struct
4191         {
4192             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
4193                                          *   the counter value at the time a valid reference signal
4194                                          *   edge is input                                                             */
4195         } CACNTBR_b;
4196     };
4197 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
4198 
4199 /* =========================================================================================================================== */
4200 /* ================                                         R_CANFD0                                          ================ */
4201 /* =========================================================================================================================== */
4202 
4203 /**
4204  * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
4205  */
4206 
4207 typedef struct                         /*!< (@ 0x400B0000) R_CANFD0 Structure                                         */
4208 {
4209     __IOM R_CANFD_CFDC_Type CFDC[1];   /*!< (@ 0x00000000) Channel Control/Status                                     */
4210     __IM uint32_t           RESERVED;
4211 
4212     union
4213     {
4214         __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */
4215 
4216         struct
4217         {
4218             __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
4219             __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
4220             __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
4221             __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
4222             __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
4223             __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
4224             uint32_t             : 2;
4225             __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
4226             __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
4227             uint32_t             : 3;
4228             __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
4229         } CFDGCFG_b;
4230     };
4231 
4232     union
4233     {
4234         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */
4235 
4236         struct
4237         {
4238             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
4239             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
4240             uint32_t               : 5;
4241             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
4242             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
4243             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
4244             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
4245             uint32_t               : 4;
4246             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
4247             uint32_t               : 15;
4248         } CFDGCTR_b;
4249     };
4250 
4251     union
4252     {
4253         __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */
4254 
4255         struct
4256         {
4257             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
4258             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
4259             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
4260             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
4261             uint32_t               : 28;
4262         } CFDGSTS_b;
4263     };
4264 
4265     union
4266     {
4267         __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */
4268 
4269         struct
4270         {
4271             __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
4272             __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
4273             __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
4274             __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
4275             uint32_t             : 12;
4276             __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
4277             uint32_t             : 15;
4278         } CFDGERFL_b;
4279     };
4280 
4281     union
4282     {
4283         __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */
4284 
4285         struct
4286         {
4287             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
4288             uint32_t         : 16;
4289         } CFDGTSC_b;
4290     };
4291 
4292     union
4293     {
4294         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */
4295 
4296         struct
4297         {
4298             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
4299             uint32_t              : 4;
4300             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
4301             uint32_t              : 23;
4302         } CFDGAFLECTR_b;
4303     };
4304 
4305     union
4306     {
4307         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
4308                                         *                  0                                                          */
4309 
4310         struct
4311         {
4312             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
4313             uint32_t            : 7;
4314             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
4315             uint32_t            : 7;
4316         } CFDGAFLCFG0_b;
4317     };
4318 
4319     union
4320     {
4321         __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */
4322 
4323         struct
4324         {
4325             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
4326             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
4327             uint32_t             : 21;
4328         } CFDRMNB_b;
4329     };
4330 
4331     union
4332     {
4333         __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */
4334 
4335         struct
4336         {
4337             __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
4338         } CFDRMND0_b;
4339     };
4340 
4341     union
4342     {
4343         __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
4344                                         *                  Register                                                   */
4345 
4346         struct
4347         {
4348             __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
4349         } CFDRMIEC_b;
4350     };
4351 
4352     union
4353     {
4354         __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */
4355 
4356         struct
4357         {
4358             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
4359             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
4360             uint32_t              : 2;
4361             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
4362             uint32_t              : 1;
4363             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
4364             uint32_t              : 1;
4365             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
4366             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
4367             uint32_t              : 16;
4368         } CFDRFCC_b[2];
4369     };
4370 
4371     union
4372     {
4373         __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */
4374 
4375         struct
4376         {
4377             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
4378             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
4379             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
4380             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
4381             uint32_t             : 4;
4382             __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
4383             uint32_t             : 16;
4384         } CFDRFSTS_b[2];
4385     };
4386 
4387     union
4388     {
4389         __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */
4390 
4391         struct
4392         {
4393             __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
4394             uint32_t           : 24;
4395         } CFDRFPCTR_b[2];
4396     };
4397 
4398     union
4399     {
4400         __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */
4401 
4402         struct
4403         {
4404             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
4405             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
4406             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
4407             uint32_t              : 1;
4408             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
4409             uint32_t              : 1;
4410             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
4411             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
4412             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
4413             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
4414             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
4415             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
4416             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
4417             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
4418         } CFDCFCC_b[1];
4419     };
4420 
4421     union
4422     {
4423         __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */
4424 
4425         struct
4426         {
4427             __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
4428             __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
4429             __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
4430             __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
4431             __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
4432             uint32_t              : 3;
4433             __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
4434             uint32_t              : 16;
4435         } CFDCFSTS_b[1];
4436     };
4437 
4438     union
4439     {
4440         __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */
4441 
4442         struct
4443         {
4444             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
4445             uint32_t           : 24;
4446         } CFDCFPCTR_b[1];
4447     };
4448 
4449     union
4450     {
4451         __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */
4452 
4453         struct
4454         {
4455             __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
4456             uint32_t             : 6;
4457             __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
4458             uint32_t             : 23;
4459         } CFDFESTS_b;
4460     };
4461 
4462     union
4463     {
4464         __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */
4465 
4466         struct
4467         {
4468             __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
4469             uint32_t             : 6;
4470             __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
4471             uint32_t             : 23;
4472         } CFDFFSTS_b;
4473     };
4474 
4475     union
4476     {
4477         __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */
4478 
4479         struct
4480         {
4481             __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
4482             uint32_t             : 6;
4483             __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
4484             uint32_t             : 23;
4485         } CFDFMSTS_b;
4486     };
4487 
4488     union
4489     {
4490         __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */
4491 
4492         struct
4493         {
4494             __IM uint32_t RFXIF : 2;   /*!< [1..0] RX FIFO[x] Interrupt Flag Status                                   */
4495             uint32_t            : 30;
4496         } CFDRFISTS_b;
4497     };
4498 
4499     union
4500     {
4501         __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */
4502 
4503         struct
4504         {
4505             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
4506             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
4507             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
4508             uint8_t             : 5;
4509         } CFDTMC_b[4];
4510     };
4511 
4512     union
4513     {
4514         __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */
4515 
4516         struct
4517         {
4518             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
4519             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
4520             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
4521             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
4522             uint8_t              : 3;
4523         } CFDTMSTS_b[4];
4524     };
4525 
4526     union
4527     {
4528         __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
4529                                             *                  Register                                                   */
4530 
4531         struct
4532         {
4533             __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
4534             uint32_t                  : 28;
4535         } CFDTMTRSTS_b[1];
4536     };
4537 
4538     union
4539     {
4540         __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
4541                                              *                  Status Register                                            */
4542 
4543         struct
4544         {
4545             __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
4546             uint32_t                   : 28;
4547         } CFDTMTARSTS_b[1];
4548     };
4549 
4550     union
4551     {
4552         __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
4553                                             *                  Register                                                   */
4554 
4555         struct
4556         {
4557             __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
4558             uint32_t                  : 28;
4559         } CFDTMTCSTS_b[1];
4560     };
4561 
4562     union
4563     {
4564         __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */
4565 
4566         struct
4567         {
4568             __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
4569             uint32_t                  : 28;
4570         } CFDTMTASTS_b[1];
4571     };
4572 
4573     union
4574     {
4575         __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
4576                                         *                  Register                                                   */
4577 
4578         struct
4579         {
4580             __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
4581             uint32_t             : 28;
4582         } CFDTMIEC_b[1];
4583     };
4584 
4585     union
4586     {
4587         __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */
4588 
4589         struct
4590         {
4591             __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
4592             uint32_t               : 4;
4593             __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4594             uint32_t               : 1;
4595             __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4596             __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
4597             uint32_t               : 22;
4598         } CFDTXQCC0_b[1];
4599     };
4600 
4601     union
4602     {
4603         __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */
4604 
4605         struct
4606         {
4607             __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
4608             __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
4609             __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4610             uint32_t               : 5;
4611             __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
4612             uint32_t               : 18;
4613         } CFDTXQSTS0_b[1];
4614     };
4615 
4616     union
4617     {
4618         __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */
4619 
4620         struct
4621         {
4622             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4623             uint32_t            : 24;
4624         } CFDTXQPCTR0_b[1];
4625     };
4626 
4627     union
4628     {
4629         __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */
4630 
4631         struct
4632         {
4633             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
4634             uint32_t              : 7;
4635             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
4636             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
4637             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
4638             uint32_t              : 21;
4639         } CFDTHLCC_b[1];
4640     };
4641 
4642     union
4643     {
4644         __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */
4645 
4646         struct
4647         {
4648             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
4649             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
4650             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
4651             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
4652             uint32_t              : 4;
4653             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
4654             uint32_t              : 18;
4655         } CFDTHLSTS_b[1];
4656     };
4657 
4658     union
4659     {
4660         __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */
4661 
4662         struct
4663         {
4664             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
4665             uint32_t            : 24;
4666         } CFDTHLPCTR_b[1];
4667     };
4668 
4669     union
4670     {
4671         __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */
4672 
4673         struct
4674         {
4675             __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
4676             __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
4677             __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
4678             __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
4679             __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
4680             uint32_t             : 27;
4681         } CFDGTINTSTS0_b;
4682     };
4683 
4684     union
4685     {
4686         __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */
4687 
4688         struct
4689         {
4690             uint32_t             : 16;
4691             __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
4692             uint32_t             : 6;
4693         } CFDGTSTCFG_b;
4694     };
4695 
4696     union
4697     {
4698         __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */
4699 
4700         struct
4701         {
4702             uint32_t            : 2;
4703             __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
4704             uint32_t            : 29;
4705         } CFDGTSTCTR_b;
4706     };
4707 
4708     union
4709     {
4710         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */
4711 
4712         struct
4713         {
4714             __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
4715             uint32_t              : 7;
4716             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
4717             uint32_t              : 22;
4718         } CFDGFDCFG_b;
4719     };
4720     __IM uint32_t RESERVED1;
4721 
4722     union
4723     {
4724         __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */
4725 
4726         struct
4727         {
4728             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
4729             uint32_t           : 16;
4730         } CFDGLOCKK_b;
4731     };
4732     __IM uint32_t RESERVED2;
4733 
4734     union
4735     {
4736         __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */
4737 
4738         struct
4739         {
4740             __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
4741             uint32_t           : 27;
4742         } CFDGAFLIGNENT_b;
4743     };
4744 
4745     union
4746     {
4747         __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */
4748 
4749         struct
4750         {
4751             __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
4752             uint32_t            : 7;
4753             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
4754             uint32_t            : 16;
4755         } CFDGAFLIGNCTR_b;
4756     };
4757 
4758     union
4759     {
4760         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */
4761 
4762         struct
4763         {
4764             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
4765             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
4766             uint32_t               : 6;
4767             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
4768             uint32_t               : 23;
4769         } CFDCDTCT_b;
4770     };
4771 
4772     union
4773     {
4774         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */
4775 
4776         struct
4777         {
4778             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
4779             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
4780             uint32_t                : 6;
4781             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
4782                                           *   0                                                                         */
4783             uint32_t : 23;
4784         } CFDCDTSTS_b;
4785     };
4786     __IM uint32_t RESERVED3[2];
4787 
4788     union
4789     {
4790         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */
4791 
4792         struct
4793         {
4794             __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
4795             uint32_t            : 7;
4796             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
4797             uint32_t            : 16;
4798         } CFDGRSTC_b;
4799     };
4800     __IM uint32_t              RESERVED4[9];
4801     __IOM R_CANFD_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
4802     __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
4803     __IM uint32_t              RESERVED5[24];
4804 
4805     union
4806     {
4807         __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00000280) RAM Test Page Access Registers                             */
4808 
4809         struct
4810         {
4811             __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
4812         } CFDRPGACC_b[64];
4813     };
4814     __IM uint32_t             RESERVED6[104];
4815     __IOM R_CANFD_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
4816     __IOM R_CANFD_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
4817     __IOM R_CANFD_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
4818     __IM uint32_t             RESERVED7[3];
4819     __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
4820     __IM uint32_t             RESERVED8[118];
4821     __IOM R_CANFD_CFDRM_Type  CFDRM[4];  /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
4822 } R_CANFD_Type;                          /*!< Size = 6432 (0x1920)                                                      */
4823 
4824 /* =========================================================================================================================== */
4825 /* ================                                           R_CRC                                           ================ */
4826 /* =========================================================================================================================== */
4827 
4828 /**
4829  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
4830  */
4831 
4832 typedef struct                         /*!< (@ 0x40108000) R_CRC Structure                                            */
4833 {
4834     union
4835     {
4836         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
4837 
4838         struct
4839         {
4840             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
4841             uint8_t              : 3;
4842             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
4843             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
4844         } CRCCR0_b;
4845     };
4846 
4847     union
4848     {
4849         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
4850 
4851         struct
4852         {
4853             uint8_t              : 6;
4854             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
4855             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
4856         } CRCCR1_b;
4857     };
4858     __IM uint16_t RESERVED;
4859 
4860     union
4861     {
4862         union
4863         {
4864             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
4865 
4866             struct
4867             {
4868                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
4869             } CRCDIR_b;
4870         };
4871 
4872         union
4873         {
4874             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
4875 
4876             struct
4877             {
4878                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
4879                                               *   )                                                                         */
4880             } CRCDIR_BY_b;
4881         };
4882     };
4883 
4884     union
4885     {
4886         union
4887         {
4888             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
4889 
4890             struct
4891             {
4892                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
4893             } CRCDOR_b;
4894         };
4895 
4896         union
4897         {
4898             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
4899 
4900             struct
4901             {
4902                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
4903                                                 *   )                                                                         */
4904             } CRCDOR_HA_b;
4905         };
4906 
4907         union
4908         {
4909             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
4910 
4911             struct
4912             {
4913                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
4914             } CRCDOR_BY_b;
4915         };
4916     };
4917 
4918     union
4919     {
4920         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
4921 
4922         struct
4923         {
4924             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
4925             uint16_t             : 2;
4926         } CRCSAR_b;
4927     };
4928     __IM uint16_t RESERVED1;
4929 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
4930 
4931 /* =========================================================================================================================== */
4932 /* ================                                          R_CTSU2                                          ================ */
4933 /* =========================================================================================================================== */
4934 
4935 /**
4936  * @brief Capacitive Touch Sensing Unit (R_CTSU2)
4937  */
4938 
4939 typedef struct                         /*!< (@ 0x400D0000) R_CTSU2 Structure                                          */
4940 {
4941     union
4942     {
4943         union
4944         {
4945             __IOM uint32_t CTSUCRA;        /*!< (@ 0x00000000) CTSU Control Register A                                    */
4946 
4947             struct
4948             {
4949                 __IOM uint32_t STRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
4950                 __IOM uint32_t CAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
4951                 __IOM uint32_t SNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
4952                 __IOM uint32_t CFCON  : 1; /*!< [3..3] CTSU CFC Power on Control                                          */
4953                 __OM uint32_t  INIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
4954                 __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control                                         */
4955                 __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection                           */
4956                 __IOM uint32_t PON    : 1; /*!< [8..8] CTSU Power On Control                                              */
4957                 __IOM uint32_t CSW    : 1; /*!< [9..9] TSCAP Pin Enable                                                   */
4958                 __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting                         */
4959                 __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment                                    */
4960                 __IOM uint32_t CLK    : 2; /*!< [13..12] CTSU Operating Clock Select                                      */
4961                 __IOM uint32_t MD0    : 1; /*!< [14..14] CTSU Measurement Mode Select 0                                   */
4962                 __IOM uint32_t MD1    : 1; /*!< [15..15] CTSU Measurement Mode Select 1                                   */
4963                 __IOM uint32_t MD2    : 1; /*!< [16..16] CTSU Measurement Mode Select 2                                   */
4964                 __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment                                    */
4965                 __IOM uint32_t LOAD   : 2; /*!< [19..18] CTSU Load Control During Measurement                             */
4966                 __IOM uint32_t POSEL  : 2; /*!< [21..20] CTSU Non-measured Channel Output Select                          */
4967                 __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select                                   */
4968                 __IOM uint32_t PCSEL  : 1; /*!< [23..23] CTSU Boost Circuit Clock Select                                  */
4969                 __IOM uint32_t STCLK  : 6; /*!< [29..24] CTSU STCLK Select                                                */
4970                 __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select                             */
4971                 __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select                         */
4972             } CTSUCRA_b;
4973         };
4974 
4975         struct
4976         {
4977             union
4978             {
4979                 __IOM uint16_t CTSUCRAL;   /*!< (@ 0x00000000) CTSU Control Register A                                    */
4980 
4981                 struct
4982                 {
4983                     __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A                                    */
4984                     __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A                                    */
4985                 };
4986             };
4987 
4988             union
4989             {
4990                 __IOM uint16_t CTSUCRAH;   /*!< (@ 0x00000002) CTSU Control Register A                                    */
4991 
4992                 struct
4993                 {
4994                     __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A                                    */
4995                     __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A                                    */
4996                 };
4997             };
4998         };
4999     };
5000 
5001     union
5002     {
5003         union
5004         {
5005             __IOM uint32_t CTSUCRB;         /*!< (@ 0x00000004) CTSU Control Register B                                    */
5006 
5007             struct
5008             {
5009                 __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control                             */
5010                 __IOM uint32_t PRMODE  : 2; /*!< [5..4] Phase Control Period                                               */
5011                 __IOM uint32_t SOFF    : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable                         */
5012                 __IOM uint32_t PROFF   : 1; /*!< [7..7] Drive Pulse Phase Control                                          */
5013                 __IOM uint32_t SST     : 8; /*!< [15..8] Wait Time Sensor Stabilization                                    */
5014                 uint32_t               : 8;
5015                 __IOM uint32_t SSMOD   : 3; /*!< [26..24] Spread Spectrum Modulation Frequency                             */
5016                 uint32_t               : 1;
5017                 __IOM uint32_t SSCNT   : 2; /*!< [29..28] Adjusting the SUCLK frequency                                    */
5018                 uint32_t               : 2;
5019             } CTSUCRB_b;
5020         };
5021 
5022         struct
5023         {
5024             union
5025             {
5026                 __IOM uint16_t CTSUCRBL;     /*!< (@ 0x00000004) CTSU Control Register B                                    */
5027 
5028                 struct
5029                 {
5030                     __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B                                    */
5031                     __IOM uint8_t CTSUSST;   /*!< (@ 0x00000005) CTSU Control Register B                                    */
5032                 };
5033             };
5034 
5035             union
5036             {
5037                 __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B                                    */
5038 
5039                 struct
5040                 {
5041                     __IM uint8_t  RESERVED;
5042                     __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B                                    */
5043                 };
5044             };
5045         };
5046     };
5047 
5048     union
5049     {
5050         union
5051         {
5052             __IOM uint32_t CTSUMCH;      /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
5053 
5054             struct
5055             {
5056                 __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0                                         */
5057                 uint32_t            : 2;
5058                 __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1                                        */
5059                 uint32_t            : 2;
5060                 __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control                                */
5061                 __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control                                */
5062                 __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control                                */
5063                 __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control                                */
5064                 uint32_t            : 12;
5065             } CTSUMCH_b;
5066         };
5067 
5068         struct
5069         {
5070             union
5071             {
5072                 __IOM uint16_t CTSUMCHL;    /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
5073 
5074                 struct
5075                 {
5076                     __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
5077                     __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register                          */
5078                 };
5079             };
5080 
5081             union
5082             {
5083                 __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
5084                 __IOM uint8_t  CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
5085             };
5086         };
5087     };
5088 
5089     union
5090     {
5091         union
5092         {
5093             __IOM uint32_t CTSUCHACA;      /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
5094 
5095             struct
5096             {
5097                 __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A                                      */
5098                 __IOM uint32_t CHAC01 : 1; /*!< [1..1] CTSU Channel Enable Control A                                      */
5099                 __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A                                      */
5100                 __IOM uint32_t CHAC03 : 1; /*!< [3..3] CTSU Channel Enable Control A                                      */
5101                 __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A                                      */
5102                 __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A                                      */
5103                 __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A                                      */
5104                 __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A                                      */
5105                 __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A                                      */
5106                 __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A                                      */
5107                 __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A                                    */
5108                 __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A                                    */
5109                 __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A                                    */
5110                 __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A                                    */
5111                 __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A                                    */
5112                 __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A                                    */
5113                 __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A                                    */
5114                 __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A                                    */
5115                 __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A                                    */
5116                 uint32_t              : 2;
5117                 __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A                                    */
5118                 __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A                                    */
5119                 __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A                                    */
5120                 __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A                                    */
5121                 __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A                                    */
5122                 __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A                                    */
5123                 __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A                                    */
5124                 __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A                                    */
5125                 __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A                                    */
5126                 __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A                                    */
5127                 __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A                                    */
5128             } CTSUCHACA_b;
5129         };
5130 
5131         struct
5132         {
5133             union
5134             {
5135                 __IOM uint16_t CTSUCHACAL;   /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
5136 
5137                 struct
5138                 {
5139                     __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
5140                     __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A                     */
5141                 };
5142             };
5143 
5144             union
5145             {
5146                 __IOM uint16_t CTSUCHACAH;   /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
5147 
5148                 struct
5149                 {
5150                     __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
5151                     __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A                     */
5152                 };
5153             };
5154         };
5155     };
5156 
5157     union
5158     {
5159         union
5160         {
5161             __IOM uint32_t CTSUCHACB;      /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
5162 
5163             struct
5164             {
5165                 __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B                                      */
5166                 __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B                                      */
5167                 __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B                                      */
5168                 __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B                                      */
5169                 uint32_t              : 28;
5170             } CTSUCHACB_b;
5171         };
5172         __IOM uint16_t CTSUCHACBL;         /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
5173         __IOM uint8_t  CTSUCHAC4;          /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
5174     };
5175 
5176     union
5177     {
5178         union
5179         {
5180             __IOM uint32_t CTSUCHTRCA;      /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
5181                                              *                  A                                                          */
5182 
5183             struct
5184             {
5185                 __IOM uint32_t CHTRC   : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A                            */
5186                 __IOM uint32_t CHTRC01 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control A                            */
5187                 __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A                            */
5188                 __IOM uint32_t CHTRC03 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control A                            */
5189                 __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A                            */
5190                 __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A                            */
5191                 __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A                            */
5192                 __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A                            */
5193                 __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A                            */
5194                 __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A                            */
5195                 __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A                          */
5196                 __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A                          */
5197                 __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A                          */
5198                 __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A                          */
5199                 __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A                          */
5200                 __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A                          */
5201                 __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A                          */
5202                 __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A                          */
5203                 __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A                          */
5204                 uint32_t               : 2;
5205                 __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A                          */
5206                 __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A                          */
5207                 __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A                          */
5208                 __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A                          */
5209                 __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A                          */
5210                 __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A                          */
5211                 __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A                          */
5212                 __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A                          */
5213                 __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A                          */
5214                 __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A                          */
5215                 __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A                          */
5216             } CTSUCHTRCA_b;
5217         };
5218 
5219         struct
5220         {
5221             union
5222             {
5223                 __IOM uint16_t CTSUCHTRCAL;   /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
5224                                                *                  A                                                          */
5225 
5226                 struct
5227                 {
5228                     __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
5229                                                *                  A                                                          */
5230                     __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register
5231                                                *                  A                                                          */
5232                 };
5233             };
5234 
5235             union
5236             {
5237                 __IOM uint16_t CTSUCHTRCAH;   /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
5238                                                *                  A                                                          */
5239 
5240                 struct
5241                 {
5242                     __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
5243                                                *                  A                                                          */
5244                     __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register
5245                                                *                  A                                                          */
5246                 };
5247             };
5248         };
5249     };
5250 
5251     union
5252     {
5253         union
5254         {
5255             __IOM uint32_t CTSUCHTRCB;      /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
5256                                              *                  B                                                          */
5257 
5258             struct
5259             {
5260                 __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B                            */
5261                 __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B                            */
5262                 __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B                            */
5263                 __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B                            */
5264                 uint32_t               : 28;
5265             } CTSUCHTRCB_b;
5266         };
5267         __IOM uint16_t CTSUCHTRCBL;         /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
5268                                              *                  B                                                          */
5269         __IOM uint8_t CTSUCHTRC4;           /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
5270                                              *                  B                                                          */
5271     };
5272 
5273     union
5274     {
5275         union
5276         {
5277             __IOM uint32_t CTSUSR;          /*!< (@ 0x0000001C) CTSU Status Register                                       */
5278 
5279             struct
5280             {
5281                 __IOM uint32_t MFC     : 2; /*!< [1..0] CTSU Multi-clock Counter                                           */
5282                 uint32_t               : 3;
5283                 __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset                                         */
5284                 __IM uint32_t ICOMP1   : 1; /*!< [6..6] CTSU Sense Current Error Monitor                                   */
5285                 __IM uint32_t ICOMP0   : 1; /*!< [7..7] TSCAP Voltage Error Monitor                                        */
5286                 __IM uint32_t STC      : 3; /*!< [10..8] CTSU Measurement Status Counter                                   */
5287                 uint32_t               : 1;
5288                 __IM uint32_t  DTSR    : 1; /*!< [12..12] CTSU Data Transfer Status Flag                                   */
5289                 __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag                                */
5290                 __IOM uint32_t SUOVF   : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag                                 */
5291                 __IM uint32_t  PS      : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag                              */
5292                 __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select                                     */
5293                 uint32_t               : 10;
5294             } CTSUSR_b;
5295         };
5296 
5297         struct
5298         {
5299             union
5300             {
5301                 __IOM uint16_t CTSUSRL;    /*!< (@ 0x0000001C) CTSU Status Register                                       */
5302 
5303                 struct
5304                 {
5305                     __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register                                       */
5306                     __IOM uint8_t CTSUST;  /*!< (@ 0x0000001D) CTSU Status Register                                       */
5307                 };
5308             };
5309 
5310             union
5311             {
5312                 __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register                                       */
5313                 __IOM uint8_t  CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register                                       */
5314             };
5315         };
5316     };
5317 
5318     union
5319     {
5320         union
5321         {
5322             __IOM uint32_t CTSUSO;         /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
5323 
5324             struct
5325             {
5326                 __IOM uint32_t SO    : 10; /*!< [9..0] CTSU Sensor Offset Adjustment                                      */
5327                 __IOM uint32_t SNUM  : 8;  /*!< [17..10] CTSU Measurement Count Setting                                   */
5328                 uint32_t             : 2;
5329                 __IOM uint32_t SSDIV : 4;  /*!< [23..20] Spread Spectrum Frequency                                        */
5330                 __IOM uint32_t SDPA  : 8;  /*!< [31..24] CTSU Base Clock Setting                                          */
5331             } CTSUSO_b;
5332         };
5333 
5334         struct
5335         {
5336             __IOM uint16_t CTSUSO0;    /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
5337             __IOM uint16_t CTSUSO1;    /*!< (@ 0x00000022) CTSU Sensor Offset Register                                */
5338         };
5339     };
5340 
5341     union
5342     {
5343         union
5344         {
5345             __IM uint32_t CTSUSCNT;         /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
5346 
5347             struct
5348             {
5349                 __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter                                               */
5350                 __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter                                               */
5351             } CTSUSCNT_b;
5352         };
5353         __IM uint16_t CTSUSC;               /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
5354     };
5355 
5356     union
5357     {
5358         union
5359         {
5360             __IOM uint32_t CTSUCALIB;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
5361 
5362             struct
5363             {
5364                 uint32_t                : 2;
5365                 __IOM uint32_t TSOD     : 1; /*!< [2..2] TS Pins Fixed Output                                               */
5366                 __IOM uint32_t DRV      : 1; /*!< [3..3] Power Supply Calibration Select                                    */
5367                 __IOM uint32_t CLKSEL   : 2; /*!< [5..4] Observation Clock Select                                           */
5368                 __IOM uint32_t SUCLKEN  : 1; /*!< [6..6] SUCLK Forced Oscillation Control                                   */
5369                 __IOM uint32_t TSOC     : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit                */
5370                 __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter                                */
5371                 __IOM uint32_t IOC      : 1; /*!< [9..9] TS Pin Fixed Output Value Set                                      */
5372                 __IOM uint32_t CFCRDMD  : 1; /*!< [10..10] CFC Counter Read Mode Select                                     */
5373                 __IOM uint32_t DCOFF    : 1; /*!< [11..11] Down Converter Control                                           */
5374                 __IOM uint32_t IOCSEL   : 1; /*!< [12..12] TS Pins Fixed Output Select                                      */
5375                 uint32_t                : 3;
5376                 __IOM uint32_t CFCSEL   : 6; /*!< [21..16] Observation CFC Clock Select                                     */
5377                 __IOM uint32_t CFCMODE  : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select                           */
5378                 uint32_t                : 1;
5379                 __IOM uint32_t DACMSEL  : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select             */
5380                 __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration                        */
5381                 __IOM uint32_t SUMSEL   : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration
5382                                               *   Select                                                                    */
5383                 __IOM uint32_t SUCARRY : 1;  /*!< [27..27] Current Control Oscillator Input Current Adjustment
5384                                               *   for SUCLK                                                                 */
5385                 __IOM uint32_t DACCLK : 1;   /*!< [28..28] Modulation Clock Select for Offset Current Circuits              */
5386                 __IOM uint32_t CCOCLK : 1;   /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator
5387                                               *   Input Current of SUCLK                                                    */
5388                 __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator
5389                                               *   for Measurement                                                           */
5390                 __IOM uint32_t TXREV : 1;    /*!< [31..31] Transmit Pin Inverted Output                                     */
5391             } CTSUCALIB_b;
5392         };
5393 
5394         struct
5395         {
5396             __IOM uint16_t CTSUDBGR0;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
5397             __IOM uint16_t CTSUDBGR1;  /*!< (@ 0x0000002A) CTSU Calibration Register                                  */
5398         };
5399     };
5400 
5401     union
5402     {
5403         union
5404         {
5405             __IOM uint32_t CTSUSUCLKA;       /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
5406 
5407             struct
5408             {
5409                 __IOM uint32_t SUADJ0   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
5410                 __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
5411                 __IOM uint32_t SUADJ1   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
5412                 __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
5413             } CTSUSUCLKA_b;
5414         };
5415 
5416         struct
5417         {
5418             __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
5419             __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A                  */
5420         };
5421     };
5422 
5423     union
5424     {
5425         union
5426         {
5427             __IOM uint32_t CTSUSUCLKB;       /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
5428 
5429             struct
5430             {
5431                 __IOM uint32_t SUADJ2   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
5432                 __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
5433                 __IOM uint32_t SUADJ3   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
5434                 __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
5435             } CTSUSUCLKB_b;
5436         };
5437 
5438         struct
5439         {
5440             __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
5441             __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B                  */
5442         };
5443     };
5444 
5445     union
5446     {
5447         union
5448         {
5449             __IM uint32_t CTSUCFCCNT;      /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
5450 
5451             struct
5452             {
5453                 __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter                                                  */
5454                 uint32_t             : 16;
5455             } CTSUCFCCNT_b;
5456         };
5457         __IM uint16_t CTSUCFCCNTL;         /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
5458     };
5459     __IM uint32_t RESERVED1[2];
5460 
5461     union
5462     {
5463         union
5464         {
5465             __IOM uint32_t CTSUOPT;          /*!< (@ 0x00000040) CTSU Option Setting Register                               */
5466 
5467             struct
5468             {
5469                 __IOM uint32_t CCOCFEN  : 1; /*!< [0..0] CCO Characteristics Correction Function Enable                     */
5470                 __IOM uint32_t MCACEFN  : 1; /*!< [1..1] Multi-clock Correction Function Enable                             */
5471                 __IOM uint32_t MAJIRIMD : 1; /*!< [2..2] Majority Mode                                                      */
5472                 uint32_t                : 1;
5473                 __IOM uint32_t DTCLESS  : 1; /*!< [4..4] Data Transfer Request Disable                                      */
5474                 __IOM uint32_t MTUCFEN  : 1; /*!< [5..5] 5 MTUCFEN Mutual Capacitance Calculation Enable                    */
5475                 uint32_t                : 2;
5476                 __IOM uint32_t AJFEN    : 1; /*!< [8..8] Automatic Judgment Function Enable                                 */
5477                 __IOM uint32_t AJINTC   : 1; /*!< [9..9] Automatic Judgment Interrupt Control                               */
5478                 uint32_t                : 6;
5479                 __IOM uint32_t SCACTB   : 4; /*!< [19..16] Sensor Counter Automatic Correction Table Number Setting         */
5480                 uint32_t                : 12;
5481             } CTSUOPT_b;
5482         };
5483 
5484         struct
5485         {
5486             union
5487             {
5488                 __IOM uint16_t CTSUOPTL; /*!< (@ 0x00000040) CTSU Option Setting Register                               */
5489 
5490                 struct
5491                 {
5492                     __IOM uint8_t AC;    /*!< (@ 0x00000040) CTSU Option Setting Register                               */
5493                     __IOM uint8_t AJ;    /*!< (@ 0x00000041) CTSU Option Setting Register                               */
5494                 };
5495             };
5496 
5497             union
5498             {
5499                 __IOM uint16_t CTSUOPTH; /*!< (@ 0x00000042) CTSU Option Setting Register                               */
5500                 __IOM uint8_t  ACTB;     /*!< (@ 0x00000042) CTSU Option Setting Register                               */
5501             };
5502         };
5503     };
5504 
5505     union
5506     {
5507         union
5508         {
5509             __IOM uint32_t CTSUSCNTACT;          /*!< (@ 0x00000044) CTSU Sensor Counter Automatic Correction Table
5510                                                   *                  Access Register                                            */
5511 
5512             struct
5513             {
5514                 __IOM uint32_t SCNTACCOEFF : 16; /*!< [15..0] Sensor Counter Correction Coefficient Setting                     */
5515                 __IOM uint32_t SCNTACCOUNT : 16; /*!< [31..16] Set the measurement value to be compared                         */
5516             } CTSUSCNTACT_b;
5517         };
5518 
5519         struct
5520         {
5521             __IOM uint16_t CTSUSCNTACTL; /*!< (@ 0x00000044) CTSU Option Setting Register                               */
5522             __IOM uint16_t CTSUSCNTACTH; /*!< (@ 0x00000046) CTSU Option Setting Register                               */
5523         };
5524     };
5525     __IM uint32_t RESERVED2;
5526 
5527     union
5528     {
5529         union
5530         {
5531             __IOM uint32_t CTSUMACT1;            /*!< (@ 0x0000004C) Multi-Clock Automatic Correction Table Access
5532                                                   *                  Register                                                   */
5533 
5534             struct
5535             {
5536                 __IOM uint32_t SO          : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock                      */
5537                 uint32_t                   : 6;
5538                 __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock                          */
5539             } CTSUMACT1_b;
5540         };
5541 
5542         struct
5543         {
5544             __IOM uint16_t CTSUMACT1L; /*!< (@ 0x0000004C) CTSU Option Setting Register                               */
5545             __IOM uint16_t CTSUMACT1H; /*!< (@ 0x0000004E) CTSU Option Setting Register                               */
5546         };
5547     };
5548 
5549     union
5550     {
5551         union
5552         {
5553             __IOM uint32_t CTSUMACT2;            /*!< (@ 0x00000050) Multi-Clock Automatic Correction Table Access
5554                                                   *                  Register                                                   */
5555 
5556             struct
5557             {
5558                 __IOM uint32_t SO          : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock                      */
5559                 uint32_t                   : 6;
5560                 __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock                          */
5561             } CTSUMACT2_b;
5562         };
5563 
5564         struct
5565         {
5566             __IOM uint16_t CTSUMACT2L; /*!< (@ 0x00000050) CTSU Option Setting Register                               */
5567             __IOM uint16_t CTSUMACT2H; /*!< (@ 0x00000052) CTSU Option Setting Register                               */
5568         };
5569     };
5570 
5571     union
5572     {
5573         union
5574         {
5575             __IOM uint32_t CTSUMACT3;            /*!< (@ 0x00000054) Multi-Clock Automatic Correction Table Access
5576                                                   *                  Register                                                   */
5577 
5578             struct
5579             {
5580                 __IOM uint32_t SO          : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock                      */
5581                 uint32_t                   : 6;
5582                 __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock                          */
5583             } CTSUMACT3_b;
5584         };
5585 
5586         struct
5587         {
5588             __IOM uint16_t CTSUMACT3L; /*!< (@ 0x00000054) CTSU Option Setting Register                               */
5589             __IOM uint16_t CTSUMACT3H; /*!< (@ 0x00000056) CTSU Option Setting Register                               */
5590         };
5591     };
5592 
5593     union
5594     {
5595         union
5596         {
5597             __IOM uint32_t CTSUAJCR;       /*!< (@ 0x00000058) CTSU Automatic Judgment Control Registe                    */
5598 
5599             struct
5600             {
5601                 __IOM uint32_t TLOT   : 8; /*!< [7..0] Non-Touch Judgment Criterion Setting                               */
5602                 __IOM uint32_t THOT   : 8; /*!< [15..8] Touch Judgment Criterion Setting                                  */
5603                 __IOM uint32_t BLINI  : 1; /*!< [16..16] Baseline Initialization                                          */
5604                 uint32_t              : 3;
5605                 __IOM uint32_t JC     : 2; /*!< [21..20] Judgment Condition Setting                                       */
5606                 uint32_t              : 2;
5607                 __IOM uint32_t AJMMAT : 4; /*!< [27..24] Measured Value Moving Average Number Setting                     */
5608                 __IOM uint32_t AJBMAT : 4; /*!< [31..28] Baseline Average Number Setting                                  */
5609             } CTSUAJCR_b;
5610         };
5611 
5612         struct
5613         {
5614             union
5615             {
5616                 __IOM uint16_t CTSUAJCRL; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register                   */
5617 
5618                 struct
5619                 {
5620                     __IOM uint8_t AJCR0;  /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register                   */
5621                     __IOM uint8_t AJCR1;  /*!< (@ 0x00000059) CTSU Automatic Judgment Control Register                   */
5622                 };
5623             };
5624 
5625             union
5626             {
5627                 __IOM uint16_t CTSUAJCRH; /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register                   */
5628 
5629                 struct
5630                 {
5631                     __IOM uint8_t AJCR2;  /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register                   */
5632                     __IOM uint8_t AJCR3;  /*!< (@ 0x0000005B) CTSU Automatic Judgment Control Register                   */
5633                 };
5634             };
5635         };
5636     };
5637 
5638     union
5639     {
5640         union
5641         {
5642             __IOM uint32_t CTSUAJTHR;      /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register                   */
5643 
5644             struct
5645             {
5646                 __IOM uint32_t AJTHL : 16; /*!< [15..0] Lower Threshold Setting                                           */
5647                 __IOM uint32_t AJTHH : 16; /*!< [31..16] Upper Threshold Setting                                          */
5648             } CTSUAJTHR_b;
5649         };
5650 
5651         struct
5652         {
5653             __IOM uint16_t CTSUAJTHRL; /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register                   */
5654             __IOM uint16_t CTSUAJTHRH; /*!< (@ 0x0000005E) CTSU Automatic Judgment Control Register                   */
5655         };
5656     };
5657 
5658     union
5659     {
5660         union
5661         {
5662             __IOM uint32_t CTSUAJMMAR;       /*!< (@ 0x00000060) CTSU Threshold Register                                    */
5663 
5664             struct
5665             {
5666                 __IOM uint32_t AJMMATI : 4;  /*!< [3..0] Moving Average Count                                               */
5667                 uint32_t               : 1;
5668                 __IOM uint32_t AJMMR   : 27; /*!< [31..5] Moving Average Result                                             */
5669             } CTSUAJMMAR_b;
5670         };
5671 
5672         struct
5673         {
5674             __IOM uint16_t CTSUAJMMARL; /*!< (@ 0x00000060) CTSU Threshold Register                                    */
5675             __IOM uint16_t CTSUAJMMARH; /*!< (@ 0x00000062) CTSU Threshold Register                                    */
5676         };
5677     };
5678 
5679     union
5680     {
5681         union
5682         {
5683             __IOM uint32_t CTSUAJBLACT;      /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register         */
5684 
5685             struct
5686             {
5687                 __IOM uint32_t AJBLACT : 32; /*!< [31..0] Automatic determination baseline average calculation
5688                                               *   bits                                                                      */
5689             } CTSUAJBLACT_b;
5690         };
5691 
5692         struct
5693         {
5694             __IOM uint16_t CTSUAJBLACTL; /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register         */
5695             __IOM uint16_t CTSUAJBLACTH; /*!< (@ 0x00000066) CTSU Baseline Average Intermediate Result Register         */
5696         };
5697     };
5698 
5699     union
5700     {
5701         union
5702         {
5703             __IOM uint32_t CTSUAJBLAR;      /*!< (@ 0x00000068) CTSU Baseline Average Result Register                      */
5704 
5705             struct
5706             {
5707                 __IOM uint32_t AJBLAC : 16; /*!< [15..0] Baseline Average Count                                            */
5708                 __IOM uint32_t AJBLAR : 16; /*!< [31..16] Baseline Average Result                                          */
5709             } CTSUAJBLAR_b;
5710         };
5711 
5712         struct
5713         {
5714             __IOM uint16_t CTSUAJBLARL; /*!< (@ 0x00000068) CTSU Baseline Average Result Register                      */
5715             __IOM uint16_t CTSUAJBLARH; /*!< (@ 0x0000006A) CTSU Baseline Average Result Register                      */
5716         };
5717     };
5718 
5719     union
5720     {
5721         union
5722         {
5723             __IOM uint32_t CTSUAJRR;      /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register                    */
5724 
5725             struct
5726             {
5727                 __IOM uint32_t TJR0 : 1;  /*!< [0..0] The judgment result when using SUCLK0 is stored.                   */
5728                 __IOM uint32_t TJR1 : 1;  /*!< [1..1] The judgment result when using SUCLK1 is stored.                   */
5729                 __IOM uint32_t TJR2 : 1;  /*!< [2..2] The judgment result when using SUCLK2 is stored.                   */
5730                 __IOM uint32_t TJR3 : 1;  /*!< [3..3] The judgment result when using SUCLK3 is stored.                   */
5731                 __IOM uint32_t FJR  : 1;  /*!< [4..4] The final judgment result on multi-clock measurement
5732                                            *   is stored.                                                                */
5733                 uint32_t             : 3;
5734                 __IOM uint32_t SJCCR : 8; /*!< [15..8] Remaining Number of Consecutive Detections                        */
5735                 uint32_t             : 16;
5736             } CTSUAJRR_b;
5737         };
5738         __IOM uint16_t CTSUAJRRL;         /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register                    */
5739 
5740         struct
5741         {
5742             __IOM uint8_t CTSUAJRR0;      /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register                    */
5743             __IOM uint8_t CTSUAJRR1;      /*!< (@ 0x0000006D) CTSU Automatic Judgment Result Register                    */
5744         };
5745     };
5746 } R_CTSU2_Type;                           /*!< Size = 112 (0x70)                                                         */
5747 
5748 /* =========================================================================================================================== */
5749 /* ================                                           R_DAC                                           ================ */
5750 /* =========================================================================================================================== */
5751 
5752 /**
5753  * @brief D/A Converter (R_DAC)
5754  */
5755 
5756 typedef struct                         /*!< (@ 0x40171000) R_DAC Structure                                            */
5757 {
5758     union
5759     {
5760         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
5761 
5762         struct
5763         {
5764             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
5765                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
5766                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
5767                                         *   format.                                                                   */
5768         } DADR_b[2];
5769     };
5770 
5771     union
5772     {
5773         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
5774 
5775         struct
5776         {
5777             uint8_t             : 5;
5778             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
5779             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
5780             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
5781         } DACR_b;
5782     };
5783 
5784     union
5785     {
5786         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
5787 
5788         struct
5789         {
5790             uint8_t             : 7;
5791             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
5792         } DADPR_b;
5793     };
5794 
5795     union
5796     {
5797         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
5798 
5799         struct
5800         {
5801             uint8_t              : 7;
5802             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
5803         } DAADSCR_b;
5804     };
5805 
5806     union
5807     {
5808         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
5809 
5810         struct
5811         {
5812             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
5813             uint8_t           : 5;
5814         } DAVREFCR_b;
5815     };
5816 
5817     union
5818     {
5819         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
5820 
5821         struct
5822         {
5823             uint8_t              : 6;
5824             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
5825             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
5826         } DAAMPCR_b;
5827     };
5828 
5829     union
5830     {
5831         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
5832 
5833         struct
5834         {
5835             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
5836             uint8_t              : 7;
5837         } DAPC_b;
5838     };
5839     __IM uint16_t RESERVED[9];
5840 
5841     union
5842     {
5843         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
5844 
5845         struct
5846         {
5847             uint8_t              : 6;
5848             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
5849                                         *   to wait for stabilization of the output amplifier of D/A
5850                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
5851                                         *   but the conversion result D/A is not output from channel
5852                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
5853                                         *   stops, and the D/A conversion result of channel 0 is output
5854                                         *   through the output amplifier.                                             */
5855             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
5856                                         *   to wait for stabilization of the output amplifier of D/A
5857                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
5858                                         *   but the conversion result D/A is not output from channel
5859                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
5860                                         *   stops, and the D/A conversion result of channel 1 is output
5861                                         *   through the output amplifier.                                             */
5862         } DAASWCR_b;
5863     };
5864     __IM uint8_t  RESERVED1;
5865     __IM uint16_t RESERVED2[2129];
5866 
5867     union
5868     {
5869         __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
5870 
5871         struct
5872         {
5873             __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
5874                                          *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
5875                                          *   select unit 0 as the target synchronous unit for the MCU.
5876                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5877                                          *   conversions, select the target unit in this register in
5878                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5879                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5880                                          *   is set to 0.                                                              */
5881             __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
5882                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
5883                                          *   select unit 1 as the target synchronous unit for the MCU.
5884                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5885                                          *   conversions, select the target unit in this register in
5886                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5887                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5888                                          *   is set to 0.                                                              */
5889             uint8_t : 6;
5890         } DAADUSR_b;
5891     };
5892     __IM uint8_t  RESERVED3;
5893     __IM uint16_t RESERVED4;
5894 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
5895 
5896 /* =========================================================================================================================== */
5897 /* ================                                          R_DEBUG                                          ================ */
5898 /* =========================================================================================================================== */
5899 
5900 /**
5901  * @brief Debug Function (R_DEBUG)
5902  */
5903 
5904 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
5905 {
5906     union
5907     {
5908         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
5909 
5910         struct
5911         {
5912             uint32_t                   : 28;
5913             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
5914             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
5915             uint32_t                   : 2;
5916         } DBGSTR_b;
5917     };
5918     __IM uint32_t RESERVED[3];
5919 
5920     union
5921     {
5922         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
5923 
5924         struct
5925         {
5926             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
5927             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
5928             uint32_t                     : 12;
5929             __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
5930             __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
5931             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
5932             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
5933             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
5934             uint32_t                     : 5;
5935             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
5936             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
5937             uint32_t                     : 5;
5938             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
5939         } DBGSTOPCR_b;
5940     };
5941     __IM uint32_t RESERVED1[123];
5942 
5943     union
5944     {
5945         __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */
5946 
5947         struct
5948         {
5949             __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
5950             __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
5951             uint32_t              : 6;
5952             __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
5953             uint32_t              : 21;
5954         } FSBLSTAT_b;
5955     };
5956 } R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */
5957 
5958 /* =========================================================================================================================== */
5959 /* ================                                           R_DMA                                           ================ */
5960 /* =========================================================================================================================== */
5961 
5962 /**
5963  * @brief DMA Controller Common (R_DMA)
5964  */
5965 
5966 typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
5967 {
5968     union
5969     {
5970         __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
5971 
5972         struct
5973         {
5974             __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
5975             uint8_t            : 7;
5976         } DMAST_b;
5977     };
5978     __IM uint8_t  RESERVED;
5979     __IM uint16_t RESERVED1;
5980     __IM uint32_t RESERVED2[3];
5981 
5982     union
5983     {
5984         __IOM uint8_t DMCTL;           /*!< (@ 0x00000010) DMAC Control Register                                      */
5985 
5986         struct
5987         {
5988             __IOM uint8_t PR   : 1;    /*!< [0..0] Priority Control Select                                            */
5989             uint8_t            : 3;
5990             __IOM uint8_t ERCH : 1;    /*!< [4..4] Clear Channel Select                                               */
5991             uint8_t            : 3;
5992         } DMCTL_b;
5993     };
5994     __IM uint8_t  RESERVED3;
5995     __IM uint16_t RESERVED4;
5996     __IM uint32_t RESERVED5[11];
5997 
5998     union
5999     {
6000         __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
6001 
6002         struct
6003         {
6004             __IM uint32_t DMECH    : 4; /*!< [3..0] DMAC Error channel                                                 */
6005             uint32_t               : 4;
6006             __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
6007             uint32_t               : 7;
6008             __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
6009             uint32_t               : 15;
6010         } DMECHR_b;
6011     };
6012     __IM uint32_t RESERVED6[15];
6013 
6014     union
6015     {
6016         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
6017 
6018         struct
6019         {
6020             __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
6021             uint32_t            : 7;
6022             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
6023                                         *   IR flag is prohibited.                                                    */
6024             uint32_t : 15;
6025         } DELSR_b[8];
6026     };
6027 } R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
6028 
6029 /* =========================================================================================================================== */
6030 /* ================                                          R_DMAC0                                          ================ */
6031 /* =========================================================================================================================== */
6032 
6033 /**
6034  * @brief DMA Controller (R_DMAC0)
6035  */
6036 
6037 typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
6038 {
6039     union
6040     {
6041         __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
6042 
6043         struct
6044         {
6045             __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
6046         } DMSAR_b;
6047     };
6048 
6049     union
6050     {
6051         __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
6052 
6053         struct
6054         {
6055             __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
6056         } DMDAR_b;
6057     };
6058 
6059     union
6060     {
6061         __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
6062 
6063         struct
6064         {
6065             __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
6066             __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
6067             uint32_t              : 6;
6068         } DMCRA_b;
6069     };
6070 
6071     union
6072     {
6073         __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
6074 
6075         struct
6076         {
6077             __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
6078                                          *   transfer counter.                                                         */
6079             __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
6080                                          *   repeat transfer operations.                                               */
6081         } DMCRB_b;
6082     };
6083 
6084     union
6085     {
6086         __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
6087 
6088         struct
6089         {
6090             __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
6091             uint16_t            : 6;
6092             __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
6093             __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
6094             uint16_t            : 1;
6095             __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
6096             __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
6097         } DMTMD_b;
6098     };
6099     __IM uint8_t RESERVED;
6100 
6101     union
6102     {
6103         __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
6104 
6105         struct
6106         {
6107             __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
6108                                         *   Enable                                                                    */
6109             __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
6110                                         *   Enable                                                                    */
6111             __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
6112             __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
6113             __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
6114             uint8_t             : 3;
6115         } DMINT_b;
6116     };
6117 
6118     union
6119     {
6120         __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
6121 
6122         struct
6123         {
6124             __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
6125                                         *   extended repeat area on the destination address. For details
6126                                         *   on the settings.                                                          */
6127             __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
6128             __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
6129             __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
6130                                         *   repeat area on the source address. For details on the settings.           */
6131             __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
6132             __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
6133         } DMAMD_b;
6134     };
6135     __IM uint16_t RESERVED1;
6136 
6137     union
6138     {
6139         __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
6140 
6141         struct
6142         {
6143             __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
6144                                         *   as the address update mode for transfer source or destination.            */
6145         } DMOFR_b;
6146     };
6147 
6148     union
6149     {
6150         __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
6151 
6152         struct
6153         {
6154             __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
6155             uint8_t           : 7;
6156         } DMCNT_b;
6157     };
6158 
6159     union
6160     {
6161         __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
6162 
6163         struct
6164         {
6165             __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
6166             uint8_t             : 3;
6167             __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
6168             uint8_t             : 3;
6169         } DMREQ_b;
6170     };
6171 
6172     union
6173     {
6174         __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
6175 
6176         struct
6177         {
6178             __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
6179             uint8_t            : 3;
6180             __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
6181             uint8_t            : 2;
6182             __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
6183         } DMSTS_b;
6184     };
6185     __IM uint8_t   RESERVED2;
6186     __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
6187     __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
6188 
6189     union
6190     {
6191         __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
6192 
6193         struct
6194         {
6195             __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
6196                                          *   mode                                                                      */
6197             __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
6198                                          *   mode                                                                      */
6199         } DMSBS_b;
6200     };
6201 
6202     union
6203     {
6204         __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
6205 
6206         struct
6207         {
6208             __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
6209                                          *   mode                                                                      */
6210             __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
6211                                          *   mode                                                                      */
6212         } DMDBS_b;
6213     };
6214 
6215     union
6216     {
6217         __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
6218 
6219         struct
6220         {
6221             __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
6222             uint8_t           : 7;
6223         } DMBWR_b;
6224     };
6225     __IM uint8_t  RESERVED3;
6226     __IM uint16_t RESERVED4;
6227 } R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
6228 
6229 /* =========================================================================================================================== */
6230 /* ================                                           R_DTC                                           ================ */
6231 /* =========================================================================================================================== */
6232 
6233 /**
6234  * @brief Data Transfer Controller (R_DTC)
6235  */
6236 
6237 typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
6238 {
6239     union
6240     {
6241         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
6242 
6243         struct
6244         {
6245             uint8_t           : 4;
6246             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
6247             uint8_t           : 3;
6248         } DTCCR_b;
6249     };
6250     __IM uint8_t  RESERVED;
6251     __IM uint16_t RESERVED1;
6252 
6253     union
6254     {
6255         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
6256 
6257         struct
6258         {
6259             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.                                          */
6260         } DTCVBR_b;
6261     };
6262 
6263     union
6264     {
6265         __IOM uint8_t DTCADMOD;        /*!< (@ 0x00000008) DTC Address Mode Register                                  */
6266 
6267         struct
6268         {
6269             __IOM uint8_t SHORT : 1;   /*!< [0..0] Short-Address Mode Set                                             */
6270             uint8_t             : 7;
6271         } DTCADMOD_b;
6272     };
6273     __IM uint8_t  RESERVED2;
6274     __IM uint16_t RESERVED3;
6275 
6276     union
6277     {
6278         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
6279 
6280         struct
6281         {
6282             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
6283             uint8_t             : 7;
6284         } DTCST_b;
6285     };
6286     __IM uint8_t RESERVED4;
6287 
6288     union
6289     {
6290         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
6291 
6292         struct
6293         {
6294             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
6295                                         *   the vector number for the activating source when DTC transfer
6296                                         *   is in progress.The value is only valid if DTC transfer
6297                                         *   is in progress (the value of the ACT flag is 1)                           */
6298             uint16_t          : 7;
6299             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
6300         } DTCSTS_b;
6301     };
6302 
6303     union
6304     {
6305         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
6306 
6307         struct
6308         {
6309             uint8_t           : 4;
6310             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
6311             uint8_t           : 3;
6312         } DTCCR_SEC_b;
6313     };
6314     __IM uint8_t  RESERVED5;
6315     __IM uint16_t RESERVED6;
6316 
6317     union
6318     {
6319         __IOM uint32_t DTCVBR_SEC;      /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
6320 
6321         struct
6322         {
6323             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.                                          */
6324         } DTCVBR_SEC_b;
6325     };
6326 
6327     union
6328     {
6329         __IOM uint32_t DTCDISP;          /*!< (@ 0x00000018) DTC Address Displacement Register                          */
6330 
6331         struct
6332         {
6333             __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement                                          */
6334         } DTCDISP_b;
6335     };
6336     __IM uint32_t RESERVED7;
6337 
6338     union
6339     {
6340         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
6341 
6342         struct
6343         {
6344             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
6345             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
6346             uint32_t              : 7;
6347             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
6348             uint32_t              : 15;
6349         } DTEVR_b;
6350     };
6351 
6352     union
6353     {
6354         __IOM uint32_t DTCIBR;         /*!< (@ 0x00000024) DTC Index Table Base Register                              */
6355 
6356         struct
6357         {
6358             uint32_t              : 10;
6359             __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address                                     */
6360         } DTCIBR_b;
6361     };
6362 
6363     union
6364     {
6365         __IOM uint8_t DTCOR;           /*!< (@ 0x00000028) DTC Operation Register                                     */
6366 
6367         struct
6368         {
6369             __IOM uint8_t SQTFRL : 1;  /*!< [0..0] Sequence Transfer Stop                                             */
6370             uint8_t              : 7;
6371         } DTCOR_b;
6372     };
6373     __IM uint8_t  RESERVED8;
6374     __IM uint16_t RESERVED9;
6375 
6376     union
6377     {
6378         __IOM uint16_t DTCSQE;         /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register                      */
6379 
6380         struct
6381         {
6382             __IOM uint16_t VECN   : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified                      */
6383             uint16_t              : 7;
6384             __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable                                     */
6385         } DTCSQE_b;
6386     };
6387     __IM uint16_t RESERVED10;
6388 } R_DTC_Type;                          /*!< Size = 48 (0x30)                                                          */
6389 
6390 /* =========================================================================================================================== */
6391 /* ================                                           R_ELC                                           ================ */
6392 /* =========================================================================================================================== */
6393 
6394 /**
6395  * @brief Event Link Controller (R_ELC)
6396  */
6397 
6398 typedef struct                         /*!< (@ 0x40082000) R_ELC Structure                                            */
6399 {
6400     union
6401     {
6402         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
6403 
6404         struct
6405         {
6406             uint8_t             : 7;
6407             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
6408         } ELCR_b;
6409     };
6410     __IM uint8_t            RESERVED;
6411     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
6412     __IM uint16_t           RESERVED1[5];
6413     __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
6414     __IM uint16_t           RESERVED2[4];
6415 
6416     union
6417     {
6418         __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
6419                                          *                  A                                                          */
6420 
6421         struct
6422         {
6423             __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
6424             __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
6425                                          *   Attribution                                                               */
6426             __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
6427                                          *   Attribution                                                               */
6428             uint16_t : 13;
6429         } ELCSARA_b;
6430     };
6431     __IM uint16_t RESERVED3;
6432 
6433     union
6434     {
6435         __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
6436                                         *                  B                                                          */
6437 
6438         struct
6439         {
6440             __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
6441             __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
6442             __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
6443             __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
6444             __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
6445             __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
6446             __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
6447             __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
6448             __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
6449             __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
6450             __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
6451             __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
6452             __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
6453             __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
6454             __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
6455             __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
6456         } ELCSARB_b;
6457     };
6458     __IM uint16_t RESERVED4;
6459 
6460     union
6461     {
6462         __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
6463                                         *                  C                                                          */
6464 
6465         struct
6466         {
6467             __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
6468             __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
6469             __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
6470             uint16_t              : 13;
6471         } ELCSARC_b;
6472     };
6473 } R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
6474 
6475 /* =========================================================================================================================== */
6476 /* ================                                       R_FACI_HP_CMD                                       ================ */
6477 /* =========================================================================================================================== */
6478 
6479 /**
6480  * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
6481  */
6482 
6483 typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
6484 {
6485     union
6486     {
6487         __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
6488         __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
6489     };
6490 } R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
6491 
6492 /* =========================================================================================================================== */
6493 /* ================                                         R_FACI_HP                                         ================ */
6494 /* =========================================================================================================================== */
6495 
6496 /**
6497  * @brief Flash Application Command Interface (R_FACI_HP)
6498  */
6499 
6500 typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
6501 {
6502     __IM uint32_t RESERVED[4];
6503 
6504     union
6505     {
6506         __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
6507 
6508         struct
6509         {
6510             uint8_t             : 3;
6511             __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
6512             __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
6513             uint8_t             : 2;
6514             __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
6515         } FASTAT_b;
6516     };
6517     __IM uint8_t  RESERVED1;
6518     __IM uint16_t RESERVED2;
6519 
6520     union
6521     {
6522         __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
6523 
6524         struct
6525         {
6526             uint8_t               : 3;
6527             __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
6528             __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
6529             uint8_t               : 2;
6530             __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
6531         } FAEINT_b;
6532     };
6533     __IM uint8_t  RESERVED3;
6534     __IM uint16_t RESERVED4;
6535 
6536     union
6537     {
6538         __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
6539 
6540         struct
6541         {
6542             __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
6543             uint8_t              : 7;
6544         } FRDYIE_b;
6545     };
6546     __IM uint8_t  RESERVED5;
6547     __IM uint16_t RESERVED6;
6548     __IM uint32_t RESERVED7[5];
6549 
6550     union
6551     {
6552         __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
6553 
6554         struct
6555         {
6556             __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
6557                                         *   These bits can be written when FRDY bit of FSTATR register
6558                                         *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
6559         } FSADDR_b;
6560     };
6561 
6562     union
6563     {
6564         __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
6565 
6566         struct
6567         {
6568             __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
6569                                         *   end address of target area in 'Blank Check' command. These
6570                                         *   bits can be written when FRDY bit of FSTATR register is
6571                                         *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
6572         } FEADDR_b;
6573     };
6574     __IM uint32_t RESERVED8[3];
6575 
6576     union
6577     {
6578         __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
6579 
6580         struct
6581         {
6582             __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
6583                                         *   is only possible when the FRDY bit in the FSTATR register
6584                                         *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
6585                                         *   to this bit is only possible when 16 bits are written and
6586                                         *   the value written to the KEY bits is D9h.Written values
6587                                         *   are not retained by these bits (always read as 0x00).Only
6588                                         *   secure access can write to this register. Both secure access
6589                                         *   and non-secure read access are allowed. Non-secure writeaccess
6590                                         *   is denied, but TrustZo                                                    */
6591             uint16_t          : 7;
6592             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6593         } FMEPROT_b;
6594     };
6595     __IM uint16_t RESERVED9;
6596 
6597     union
6598     {
6599         __IOM uint8_t FCNTSELR;        /*!< (@ 0x00000048) Flash Counter Select Register                              */
6600 
6601         struct
6602         {
6603             __IOM uint8_t CNTSEL : 3;  /*!< [2..0] Counter Select                                                     */
6604             uint8_t              : 5;
6605         } FCNTSELR_b;
6606     };
6607     __IM uint8_t  RESERVED10;
6608     __IM uint16_t RESERVED11;
6609 
6610     union
6611     {
6612         __IM uint32_t FCNTDATAR0;       /*!< (@ 0x0000004C) Flash Counter Data Register 0                              */
6613 
6614         struct
6615         {
6616             __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data                                                 */
6617         } FCNTDATAR0_b;
6618     };
6619 
6620     union
6621     {
6622         __IM uint32_t FCNTDATAR1;       /*!< (@ 0x00000050) Flash Counter Data Register 1                              */
6623 
6624         struct
6625         {
6626             __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data                                                 */
6627         } FCNTDATAR1_b;
6628     };
6629     __IM uint32_t RESERVED12[9];
6630 
6631     union
6632     {
6633         __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
6634 
6635         struct
6636         {
6637             __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
6638                                         *   written when the FRDY bit in the FSTATR register is 1.
6639                                         *   Writing to this bit is ignored when the FRDY bit is 0.Writing
6640                                         *   to this bit is only possible when 16 bits are written and
6641                                         *   the value written to the KEY[7:0] bits is 0x78.Written
6642                                         *   values are not retained by these bits (always read as 0x00).              */
6643             uint16_t          : 7;
6644             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6645         } FBPROT0_b;
6646     };
6647     __IM uint16_t RESERVED13;
6648 
6649     union
6650     {
6651         __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
6652 
6653         struct
6654         {
6655             __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
6656                                         *   is only possible when the FRDY bit in the FSTATR register
6657                                         *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
6658                                         *   to this bit is only possible when 16 bits are written and
6659                                         *   the value written to the KEY[7:0] bits is 0xB1.Written
6660                                         *   values are not retained by these bits (always read as 0x00).              */
6661             uint16_t          : 7;
6662             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6663         } FBPROT1_b;
6664     };
6665     __IM uint16_t RESERVED14;
6666 
6667     union
6668     {
6669         __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
6670 
6671         struct
6672         {
6673             uint32_t                 : 6;
6674             __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
6675             uint32_t                 : 1;
6676             __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
6677             __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
6678             __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
6679             __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
6680             __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
6681             __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
6682             __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
6683             __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
6684             uint32_t                 : 4;
6685             __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
6686             __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
6687             __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
6688             __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
6689             uint32_t                 : 8;
6690         } FSTATR_b;
6691     };
6692 
6693     union
6694     {
6695         __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
6696 
6697         struct
6698         {
6699             __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
6700                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
6701                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
6702                                          *   only when this register is accessed in 16-bit size and
6703                                          *   H'AA is written to KEY bits                                               */
6704             uint16_t               : 6;
6705             __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
6706                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
6707                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
6708                                          *   only when this register is accessed in 16-bit size and
6709                                          *   H'AA is written to KEY bits.                                              */
6710             __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
6711         } FENTRYR_b;
6712     };
6713     __IM uint16_t RESERVED15;
6714     __IM uint32_t RESERVED16;
6715 
6716     union
6717     {
6718         __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
6719 
6720         struct
6721         {
6722             __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
6723                                         *   bit of FSTATR register is '1'. Writing to this bit in FRDY
6724                                         *   = '0' is ignored. Writing to these bits is enabled only
6725                                         *   when this register is accessed in 16-bit size and H'2D
6726                                         *   is written to KEY bits.                                                   */
6727             uint16_t          : 7;
6728             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6729         } FSUINITR_b;
6730     };
6731     __IM uint16_t RESERVED17;
6732     __IM uint32_t RESERVED18[4];
6733 
6734     union
6735     {
6736         __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
6737 
6738         struct
6739         {
6740             __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
6741             __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
6742         } FCMDR_b;
6743     };
6744     __IM uint16_t RESERVED19;
6745     __IM uint32_t RESERVED20[11];
6746 
6747     union
6748     {
6749         __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
6750 
6751         struct
6752         {
6753             __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
6754             uint8_t             : 7;
6755         } FBCCNT_b;
6756     };
6757     __IM uint8_t  RESERVED21;
6758     __IM uint16_t RESERVED22;
6759 
6760     union
6761     {
6762         __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
6763 
6764         struct
6765         {
6766             __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
6767             uint8_t           : 7;
6768         } FBCSTAT_b;
6769     };
6770     __IM uint8_t  RESERVED23;
6771     __IM uint16_t RESERVED24;
6772 
6773     union
6774     {
6775         union
6776         {
6777             __IM uint32_t FPSADDR;        /*!< (@ 0x000000D8) Programmed Area Start Address                              */
6778 
6779             struct
6780             {
6781                 __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
6782                                            *   of the first programmed data which is found in 'Blank Check'
6783                                            *   command execution.                                                        */
6784                 uint32_t : 13;
6785             } FPSADDR_b;
6786         };
6787 
6788         union
6789         {
6790             __IOM uint32_t FBCADDR;       /*!< (@ 0x000000D8) Flash Blank Check Address Register                         */
6791 
6792             struct
6793             {
6794                 __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address
6795                                            *   or the last blank checked address which is found in 'Blank
6796                                            *   Check' command execution.                                                 */
6797                 uint32_t : 8;
6798             } FBCADDR_b;
6799         };
6800     };
6801 
6802     union
6803     {
6804         __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
6805 
6806         struct
6807         {
6808             __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
6809                                         *   indicate the start sector address for setting the access
6810                                         *   window that is located in the configuration area.                         */
6811             uint32_t           : 4;
6812             __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
6813                                         *   Flag and Temporary Boot Swap Control and 'Config Clear'
6814                                         *   command execution                                                         */
6815             __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
6816                                         *   indicate the end sector address for setting the access
6817                                         *   window that is located in the configuration area.                         */
6818             uint32_t            : 4;
6819             __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
6820         } FAWMON_b;
6821     };
6822 
6823     union
6824     {
6825         __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
6826 
6827         struct
6828         {
6829             __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
6830             uint16_t               : 15;
6831         } FCPSR_b;
6832     };
6833     __IM uint16_t RESERVED25;
6834 
6835     union
6836     {
6837         __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
6838 
6839         struct
6840         {
6841             __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
6842                                         *   can be written when FRDY bit in FSTATR register is '1'.
6843                                         *   Writing to this bit in FRDY = '0' is ignored. Writing to
6844                                         *   these bits is enabled only when this register is accessed
6845                                         *   in 16-bit size and H'1E is written to KEY bits.                           */
6846             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6847         } FPCKAR_b;
6848     };
6849     __IM uint16_t RESERVED26;
6850 
6851     union
6852     {
6853         __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
6854 
6855         struct
6856         {
6857             __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
6858                                         *   bit in FSTATR register is '1'. Writing to this bit in FRDY
6859                                         *   = '0' is ignored. Writing to these bits is enabled only
6860                                         *   when this register is accessed in 16-bit size and H'66
6861                                         *   is written to KEY bits.                                                   */
6862             uint16_t          : 6;
6863             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
6864         } FSUACR_b;
6865     };
6866     __IM uint16_t RESERVED27;
6867 } R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
6868 
6869 /* =========================================================================================================================== */
6870 /* ================                                         R_FACI_LP                                         ================ */
6871 /* =========================================================================================================================== */
6872 
6873 /**
6874  * @brief Flash Application Command Interface (R_FACI_LP)
6875  */
6876 
6877 typedef struct                         /*!< (@ 0x407EC000) R_FACI_LP Structure                                        */
6878 {
6879     __IM uint32_t RESERVED[36];
6880     __IOM uint8_t DFLCTL;              /*!< (@ 0x00000090) Flash P/E Mode Control Register                            */
6881     __IM uint8_t  RESERVED1;
6882     __IM uint16_t RESERVED2;
6883     __IM uint32_t RESERVED3[27];
6884 
6885     union
6886     {
6887         __IOM uint8_t FPMCR;           /*!< (@ 0x00000100) Flash P/E Mode Control Register                            */
6888 
6889         struct
6890         {
6891             uint8_t            : 1;
6892             __IOM uint8_t FMS0 : 1;    /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode
6893                                         *   011: Discharge mode 1 111: Discharge mode 2 101: Code Flash
6894                                         *   P/E mode 010: Data flash P/E mode Others: Setting prohibited.             */
6895             uint8_t             : 1;
6896             __IOM uint8_t RPDIS : 1;   /*!< [3..3] Code Flash P/E Disable                                             */
6897             __IOM uint8_t FMS1  : 1;   /*!< [4..4] The bit to make data flash a programming modeRefer to
6898                                         *   the description of the FMS0 bit.                                          */
6899             uint8_t            : 1;
6900             __IOM uint8_t VLPE : 1;    /*!< [6..6] Low-Voltage P/E Mode Enable                                        */
6901             __IOM uint8_t FMS2 : 1;    /*!< [7..7] Flash Operating Mode Select 2.Refer to the description
6902                                         *   of the FMS0 bit.                                                          */
6903         } FPMCR_b;
6904     };
6905     __IM uint8_t  RESERVED4;
6906     __IM uint16_t RESERVED5;
6907 
6908     union
6909     {
6910         __IOM uint8_t FASR;            /*!< (@ 0x00000104) Flash Area Select Register                                 */
6911 
6912         struct
6913         {
6914             __IOM uint8_t EXS : 1;     /*!< [0..0] Extra area select                                                  */
6915             uint8_t           : 7;
6916         } FASR_b;
6917     };
6918     __IM uint8_t  RESERVED6;
6919     __IM uint16_t RESERVED7;
6920 
6921     union
6922     {
6923         __IOM uint16_t FSARL;             /*!< (@ 0x00000108) Flash Processing Start Address Register L                  */
6924 
6925         struct
6926         {
6927             __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address                                                     */
6928         } FSARL_b;
6929     };
6930     __IM uint16_t RESERVED8;
6931     __IM uint32_t RESERVED9;
6932 
6933     union
6934     {
6935         __IOM uint16_t FSARH;             /*!< (@ 0x00000110) Flash Processing Start Address Register H                  */
6936 
6937         struct
6938         {
6939             __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address                                                      */
6940             uint16_t                 : 4;
6941             __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address                                                     */
6942         } FSARH_b;
6943     };
6944     __IM uint16_t RESERVED10;
6945 
6946     union
6947     {
6948         __IOM uint8_t FCR;             /*!< (@ 0x00000114) Flash Control Register                                     */
6949 
6950         struct
6951         {
6952             __IOM uint8_t CMD  : 4;    /*!< [3..0] Software Command Setting                                           */
6953             __IOM uint8_t DRC  : 1;    /*!< [4..4] Data Read Completion                                               */
6954             uint8_t            : 1;
6955             __IOM uint8_t STOP : 1;    /*!< [6..6] Forced Processing Stop                                             */
6956             __IOM uint8_t OPST : 1;    /*!< [7..7] Processing Start                                                   */
6957         } FCR_b;
6958     };
6959     __IM uint8_t  RESERVED11;
6960     __IM uint16_t RESERVED12;
6961 
6962     union
6963     {
6964         __IOM uint16_t FEARL;             /*!< (@ 0x00000118) Flash Processing End Address Register L                    */
6965 
6966         struct
6967         {
6968             __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address                                                       */
6969         } FEARL_b;
6970     };
6971     __IM uint16_t RESERVED13;
6972     __IM uint32_t RESERVED14;
6973 
6974     union
6975     {
6976         __IOM uint32_t FEARH;             /*!< (@ 0x00000120) Flash Processing End Address Register H                    */
6977 
6978         struct
6979         {
6980             __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address                                                        */
6981             uint32_t                 : 4;
6982             __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address                                                       */
6983             uint32_t                 : 16;
6984         } FEARH_b;
6985     };
6986 
6987     union
6988     {
6989         __IOM uint32_t FRESETR;        /*!< (@ 0x00000124) Flash Reset Register                                       */
6990 
6991         struct
6992         {
6993             __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers                                    */
6994             uint32_t              : 31;
6995         } FRESETR_b;
6996     };
6997 
6998     union
6999     {
7000         __IM uint32_t FSTATR00;         /*!< (@ 0x00000128) Flash Status Register00                                    */
7001 
7002         struct
7003         {
7004             __IM uint32_t ERERR0   : 1; /*!< [0..0] Erase Error Flag0                                                  */
7005             __IM uint32_t PRGERR0  : 1; /*!< [1..1] Program Error Flag0                                                */
7006             __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
7007             __IM uint32_t BCERR0   : 1; /*!< [3..3] Blank Check Error Flag0                                            */
7008             __IM uint32_t ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
7009             __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
7010             uint32_t               : 26;
7011         } FSTATR00_b;
7012     };
7013 
7014     union
7015     {
7016         __IM uint32_t FSTATR1;         /*!< (@ 0x0000012C) Flash Status Register1                                     */
7017 
7018         struct
7019         {
7020             uint32_t            : 1;
7021             __IM uint32_t DRRDY : 1;   /*!< [1..1] Data read request                                                  */
7022             uint32_t            : 4;
7023             __IM uint32_t FRDY  : 1;   /*!< [6..6] End status signal of a sequencer                                   */
7024             __IM uint32_t EXRDY : 1;   /*!< [7..7] End status signal of a Extra programming sequencer                 */
7025             uint32_t            : 24;
7026         } FSTATR1_b;
7027     };
7028 
7029     union
7030     {
7031         __IOM uint32_t FWBL0;          /*!< (@ 0x00000130) Flash Write Buffer Register L0                             */
7032 
7033         struct
7034         {
7035             __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
7036             uint32_t             : 16;
7037         } FWBL0_b;
7038     };
7039     __IM uint32_t RESERVED15;
7040 
7041     union
7042     {
7043         __IOM uint32_t FWBH0;          /*!< (@ 0x00000138) Flash Write Buffer Register H0                             */
7044 
7045         struct
7046         {
7047             __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
7048             uint32_t             : 16;
7049         } FWBH0_b;
7050     };
7051 
7052     union
7053     {
7054         __IM uint32_t FSTATR01;        /*!< (@ 0x0000013C) Flash Status Register01                                    */
7055 
7056         struct
7057         {
7058             __IM uint32_t ERERR1  : 1; /*!< [0..0] Erase Error Flag1                                                  */
7059             __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1                                                */
7060             uint32_t              : 1;
7061             __IM uint32_t BCERR1  : 1; /*!< [3..3] Blank Check Error Flag1                                            */
7062             uint32_t              : 28;
7063         } FSTATR01_b;
7064     };
7065 
7066     union
7067     {
7068         __IOM uint32_t FWBL1;               /*!< (@ 0x00000140) Flash Write Buffer Register L1                             */
7069 
7070         struct
7071         {
7072             __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command                               */
7073             uint32_t                  : 16;
7074         } FWBL1_b;
7075     };
7076 
7077     union
7078     {
7079         __IOM uint32_t FWBH1;               /*!< (@ 0x00000144) Flash Write Buffer Register H1                             */
7080 
7081         struct
7082         {
7083             __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command                               */
7084             uint32_t                  : 16;
7085         } FWBH1_b;
7086     };
7087 
7088     union
7089     {
7090         __IM uint32_t FRBL1;               /*!< (@ 0x00000148) Flash Read Buffer Register L1                              */
7091 
7092         struct
7093         {
7094             __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command                         */
7095             uint32_t                 : 16;
7096         } FRBL1_b;
7097     };
7098 
7099     union
7100     {
7101         __IM uint32_t FRBH1;               /*!< (@ 0x0000014C) Flash Read Buffer Register H1                              */
7102 
7103         struct
7104         {
7105             __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command                         */
7106             uint32_t                 : 16;
7107         } FRBH1_b;
7108     };
7109     __IM uint32_t RESERVED16[12];
7110 
7111     union
7112     {
7113         __OM uint32_t FPR;             /*!< (@ 0x00000180) Protection Unlock Register                                 */
7114 
7115         struct
7116         {
7117             __OM uint32_t FPR : 8;     /*!< [7..0] Protection Unlock Register                                         */
7118             uint32_t          : 24;
7119         } FPR_b;
7120     };
7121 
7122     union
7123     {
7124         __IM uint32_t FPSR;            /*!< (@ 0x00000184) Protection Unlock Status Register                          */
7125 
7126         struct
7127         {
7128             __IM uint32_t PERR : 1;    /*!< [0..0] Protect Error Flag                                                 */
7129             uint32_t           : 31;
7130         } FPSR_b;
7131     };
7132 
7133     union
7134     {
7135         __IM uint32_t FRBL0;           /*!< (@ 0x00000188) Flash Read Buffer Register L0                              */
7136 
7137         struct
7138         {
7139             __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
7140             uint32_t            : 16;
7141         } FRBL0_b;
7142     };
7143     __IM uint32_t RESERVED17;
7144 
7145     union
7146     {
7147         __IM uint32_t FRBH0;           /*!< (@ 0x00000190) Flash Read Buffer Register H0                              */
7148 
7149         struct
7150         {
7151             __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
7152             uint32_t            : 16;
7153         } FRBH0_b;
7154     };
7155     __IM uint32_t RESERVED18[11];
7156 
7157     union
7158     {
7159         __IM uint32_t FSCMR;           /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register                    */
7160 
7161         struct
7162         {
7163             uint32_t            : 8;
7164             __IM uint32_t SASMF : 1;   /*!< [8..8] Start-up Area Setting Monitor Flag                                 */
7165             uint32_t            : 5;
7166             __IM uint32_t FSPR  : 1;   /*!< [14..14] Access Window Protection Flag                                    */
7167             uint32_t            : 17;
7168         } FSCMR_b;
7169     };
7170     __IM uint32_t RESERVED19;
7171 
7172     union
7173     {
7174         __IM uint32_t FAWSMR;          /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register         */
7175 
7176         struct
7177         {
7178             __IM uint32_t FAWS : 12;   /*!< [11..0] Flash Access Window Start Address                                 */
7179             uint32_t           : 20;
7180         } FAWSMR_b;
7181     };
7182     __IM uint32_t RESERVED20;
7183 
7184     union
7185     {
7186         __IM uint32_t FAWEMR;          /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register           */
7187 
7188         struct
7189         {
7190             __IM uint32_t FAWE : 12;   /*!< [11..0] Flash Access Window End Address                                   */
7191             uint32_t           : 20;
7192         } FAWEMR_b;
7193     };
7194     __IM uint32_t RESERVED21;
7195 
7196     union
7197     {
7198         __IOM uint32_t FISR;           /*!< (@ 0x000001D8) Flash Initial Setting Register                             */
7199 
7200         struct
7201         {
7202             __IOM uint32_t PCKA : 6;   /*!< [5..0] Peripheral Clock Notification                                      */
7203             __IOM uint32_t SAS  : 2;   /*!< [7..6] Temporary boot swap mode                                           */
7204             uint32_t            : 24;
7205         } FISR_b;
7206     };
7207 
7208     union
7209     {
7210         __IOM uint32_t FEXCR;          /*!< (@ 0x000001DC) Flash Extra Area Control Register                          */
7211 
7212         struct
7213         {
7214             __IOM uint32_t CMD  : 3;   /*!< [2..0] Processing Start)                                                  */
7215             uint32_t            : 4;
7216             __IOM uint32_t OPST : 1;   /*!< [7..7] Software Command Setting                                           */
7217             uint32_t            : 24;
7218         } FEXCR_b;
7219     };
7220 
7221     union
7222     {
7223         __IM uint32_t FEAML;           /*!< (@ 0x000001E0) Flash Error Address Monitor Register L                     */
7224 
7225         struct
7226         {
7227             __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
7228             uint32_t           : 16;
7229         } FEAML_b;
7230     };
7231     __IM uint32_t RESERVED22;
7232 
7233     union
7234     {
7235         __IM uint32_t FEAMH;           /*!< (@ 0x000001E8) Flash Error Address Monitor Register H                     */
7236 
7237         struct
7238         {
7239             __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
7240             uint32_t           : 16;
7241         } FEAMH_b;
7242     };
7243     __IM uint32_t RESERVED23;
7244 
7245     union
7246     {
7247         __IM uint32_t FSTATR2;           /*!< (@ 0x000001F0) Flash Status Register2                                     */
7248 
7249         struct
7250         {
7251             __IM uint32_t  ERERR    : 1; /*!< [0..0] Erase Error Flag                                                   */
7252             __IM uint32_t  PRGERR1  : 1; /*!< [1..1] Program Error Flag                                                 */
7253             __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
7254             __IM uint32_t  BCERR    : 1; /*!< [3..3] Blank Check Error Flag                                             */
7255             __IM uint32_t  ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
7256             __IM uint32_t  EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
7257             uint32_t                : 26;
7258         } FSTATR2_b;
7259     };
7260     __IM uint32_t RESERVED24[3];
7261 
7262     union
7263     {
7264         __IOM uint8_t HIOTRM;          /*!< (@ 0x00000200) High-speed On-chip Oscillator Trimming Register            */
7265 
7266         struct
7267         {
7268             __IOM uint8_t HIOTRM : 6;  /*!< [5..0] HOCO User Trimming                                                 */
7269             uint8_t              : 2;
7270         } HIOTRM_b;
7271     };
7272     __IM uint8_t  RESERVED25;
7273     __IM uint16_t RESERVED26;
7274     __IM uint32_t RESERVED27;
7275     __IM uint16_t RESERVED28;
7276 
7277     union
7278     {
7279         __IOM uint8_t FLMODE;          /*!< (@ 0x0000020A) Flash Operating Mode Control Register                      */
7280 
7281         struct
7282         {
7283             uint8_t            : 6;
7284             __IOM uint8_t MODE : 2;    /*!< [7..6] Operating Mode Select                                              */
7285         } FLMODE_b;
7286     };
7287 
7288     union
7289     {
7290         __IOM uint8_t FLMWRP;          /*!< (@ 0x0000020B) Flash Operating Mode Protect Register                      */
7291 
7292         struct
7293         {
7294             __IOM uint8_t FLMWEN : 1;  /*!< [0..0] Control of Flash Operation Mode Select Register                    */
7295             uint8_t              : 7;
7296         } FLMWRP_b;
7297     };
7298     __IM uint32_t RESERVED29[89];
7299 
7300     union
7301     {
7302         __IOM uint32_t FCTLFR;          /*!< (@ 0x00000370) Flash Control Flag Register                                */
7303 
7304         struct
7305         {
7306             __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting                                                  */
7307             uint32_t               : 29;
7308         } FCTLFR_b;
7309     };
7310     __IM uint32_t  RESERVED30[3855];
7311     __IOM uint16_t FENTRYR_MF4;        /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4                      */
7312     __IOM uint16_t FENTRYR;            /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register                              */
7313     __IM uint32_t  RESERVED31[3];
7314     __IOM uint8_t  FLWAITR;            /*!< (@ 0x00003FC0) Flash Wait Cycle Register                                  */
7315     __IM uint8_t   RESERVED32;
7316     __IM uint16_t  RESERVED33;
7317 
7318     union
7319     {
7320         __IOM uint8_t FLDWAITR;         /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash          */
7321 
7322         struct
7323         {
7324             __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash                            */
7325             uint8_t                : 7;
7326         } FLDWAITR_b;
7327     };
7328     __IM uint8_t  RESERVED34;
7329     __IM uint16_t RESERVED35;
7330     __IOM uint8_t PFBER;               /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register                            */
7331     __IM uint8_t  RESERVED36;
7332     __IM uint16_t RESERVED37;
7333     __IM uint32_t RESERVED38;
7334 
7335     union
7336     {
7337         __IOM uint16_t FBKPGCR;        /*!< (@ 0x00003FD0) Flash Bank Program Control Register                        */
7338 
7339         struct
7340         {
7341             __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable                                    */
7342             uint16_t              : 7;
7343             __OM uint16_t FEKEY   : 8; /*!< [15..8] Key Code                                                          */
7344         } FBKPGCR_b;
7345     };
7346     __IM uint16_t RESERVED39;
7347 
7348     union
7349     {
7350         __IOM uint16_t FBKSWCR;          /*!< (@ 0x00003FD4) Flash Bank Swap Control Register                           */
7351 
7352         struct
7353         {
7354             __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable                                            */
7355             uint16_t                : 7;
7356             __OM uint16_t FEKEY     : 8; /*!< [15..8] Key Code                                                          */
7357         } FBKSWCR_b;
7358     };
7359     __IM uint16_t RESERVED40;
7360 } R_FACI_LP_Type;                        /*!< Size = 16344 (0x3fd8)                                                     */
7361 
7362 /* =========================================================================================================================== */
7363 /* ================                                        R_CTSUTRIM                                         ================ */
7364 /* =========================================================================================================================== */
7365 
7366 /**
7367  * @brief CTSU Trimming Registers (R_CTSUTRIM)
7368  */
7369 
7370 typedef struct                         /*!< (@ 0x407EC000) R_CTSUTRIM Structure                                       */
7371 {
7372     __IM uint32_t RESERVED[233];
7373 
7374     union
7375     {
7376         __IOM uint32_t CTSUTRIMA;         /*!< (@ 0x000003A4) CTSU Trimming Register A                                   */
7377 
7378         struct
7379         {
7380             __IOM uint32_t RTRIM     : 8; /*!< [7..0] CTSU Reference Resistance Adjustment                               */
7381             __IOM uint32_t DACTRIM   : 8; /*!< [15..8] Linearity Adjustment of Offset Current                            */
7382             __IOM uint32_t SUADJD    : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
7383             __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
7384                                            *   (120k)                                                                    */
7385         } CTSUTRIMA_b;
7386     };
7387 
7388     union
7389     {
7390         __IOM uint32_t CTSUTRIMB;        /*!< (@ 0x000003A8) CTSU Trimming Register B                                   */
7391 
7392         struct
7393         {
7394             __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance
7395                                           *   (7.5k)                                                                    */
7396             __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance
7397                                           *   (15k)                                                                     */
7398             __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance
7399                                           *   (30k)                                                                     */
7400             __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
7401                                           *   (60k)                                                                     */
7402         } CTSUTRIMB_b;
7403     };
7404 } R_CTSUTRIM_Type;                       /*!< Size = 940 (0x3ac)                                                        */
7405 
7406 /* =========================================================================================================================== */
7407 /* ================                                         R_FCACHE                                          ================ */
7408 /* =========================================================================================================================== */
7409 
7410 /**
7411  * @brief Flash Memory Cache (R_FCACHE)
7412  */
7413 
7414 typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
7415 {
7416     __IM uint16_t RESERVED[128];
7417 
7418     union
7419     {
7420         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
7421 
7422         struct
7423         {
7424             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
7425             uint16_t                : 15;
7426         } FCACHEE_b;
7427     };
7428     __IM uint16_t RESERVED1;
7429 
7430     union
7431     {
7432         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
7433 
7434         struct
7435         {
7436             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
7437             uint16_t                : 15;
7438         } FCACHEIV_b;
7439     };
7440     __IM uint16_t RESERVED2[11];
7441 
7442     union
7443     {
7444         __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
7445 
7446         struct
7447         {
7448             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
7449             uint8_t            : 5;
7450         } FLWT_b;
7451     };
7452     __IM uint8_t  RESERVED3;
7453     __IM uint16_t RESERVED4[17];
7454 
7455     union
7456     {
7457         __IOM uint16_t FSAR;               /*!< (@ 0x00000140) Flash Security Attribution Register                        */
7458 
7459         struct
7460         {
7461             __IOM uint16_t FLWTSA     : 1; /*!< [0..0] FLWT Security Attribution                                          */
7462             __IOM uint16_t PFBERSA    : 1; /*!< [1..1] PFBERSA Security Attribution                                       */
7463             uint16_t                  : 6;
7464             __IOM uint16_t FCKMHZSA   : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
7465             __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution                          */
7466             __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution                      */
7467             uint16_t                  : 4;
7468             __IOM uint16_t DFLCTLSA   : 1; /*!< [15..15] DFLCTL Security Attribution                                      */
7469         } FSAR_b;
7470     };
7471 } R_FCACHE_Type;                           /*!< Size = 322 (0x142)                                                        */
7472 
7473 /* =========================================================================================================================== */
7474 /* ================                                          R_GPT0                                           ================ */
7475 /* =========================================================================================================================== */
7476 
7477 /**
7478  * @brief General PWM Timer (R_GPT0)
7479  */
7480 
7481 typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure                                           */
7482 {
7483     union
7484     {
7485         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
7486 
7487         struct
7488         {
7489             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
7490             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
7491             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
7492             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
7493             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
7494             uint32_t             : 3;
7495             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
7496             uint32_t             : 16;
7497         } GTWP_b;
7498     };
7499 
7500     union
7501     {
7502         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
7503 
7504         struct
7505         {
7506             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
7507                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7508                                          *   means counter running.                                                    */
7509             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
7510                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7511                                          *   means counter running.                                                    */
7512             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
7513                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7514                                          *   means counter running.                                                    */
7515             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
7516                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7517                                          *   means counter running.                                                    */
7518             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
7519                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7520                                          *   means counter running.                                                    */
7521             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
7522                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7523                                          *   means counter running.                                                    */
7524             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
7525                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7526                                          *   means counter running.                                                    */
7527             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
7528                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7529                                          *   means counter running.                                                    */
7530             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
7531                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7532                                          *   means counter running.                                                    */
7533             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
7534                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7535                                          *   means counter running.                                                    */
7536             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
7537                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7538                                          *   means counter running.                                                    */
7539             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
7540                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7541                                          *   means counter running.                                                    */
7542             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
7543                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7544                                          *   means counter running.                                                    */
7545             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
7546                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7547                                          *   means counter running.                                                    */
7548             __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
7549                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7550                                          *   means counter running.                                                    */
7551             __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
7552                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7553                                          *   means counter running.                                                    */
7554             __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
7555                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7556                                          *   means counter running.                                                    */
7557             __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
7558                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7559                                          *   means counter running.                                                    */
7560             __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
7561                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7562                                          *   means counter running.                                                    */
7563             __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
7564                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7565                                          *   means counter running.                                                    */
7566             __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
7567                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7568                                          *   means counter running.                                                    */
7569             __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
7570                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7571                                          *   means counter running.                                                    */
7572             __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
7573                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7574                                          *   means counter running.                                                    */
7575             __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
7576                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7577                                          *   means counter running.                                                    */
7578             __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
7579                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7580                                          *   means counter running.                                                    */
7581             __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
7582                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7583                                          *   means counter running.                                                    */
7584             __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
7585                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7586                                          *   means counter running.                                                    */
7587             __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
7588                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7589                                          *   means counter running.                                                    */
7590             __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
7591                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7592                                          *   means counter running.                                                    */
7593             __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
7594                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7595                                          *   means counter running.                                                    */
7596             __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
7597                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7598                                          *   means counter running.                                                    */
7599             __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
7600                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7601                                          *   means counter running.                                                    */
7602         } GTSTR_b;
7603     };
7604 
7605     union
7606     {
7607         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
7608 
7609         struct
7610         {
7611             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
7612                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7613                                          *   1 means counter stop.                                                     */
7614             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
7615                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7616                                          *   1 means counter stop.                                                     */
7617             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
7618                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7619                                          *   1 means counter stop.                                                     */
7620             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
7621                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7622                                          *   1 means counter stop.                                                     */
7623             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
7624                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7625                                          *   1 means counter stop.                                                     */
7626             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
7627                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7628                                          *   1 means counter stop.                                                     */
7629             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
7630                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7631                                          *   1 means counter stop.                                                     */
7632             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
7633                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7634                                          *   1 means counter stop.                                                     */
7635             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
7636                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7637                                          *   1 means counter stop.                                                     */
7638             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
7639                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7640                                          *   1 means counter stop.                                                     */
7641             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
7642                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7643                                          *   1 means counter stop.                                                     */
7644             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
7645                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7646                                          *   1 means counter stop.                                                     */
7647             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
7648                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7649                                          *   1 means counter stop.                                                     */
7650             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
7651                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7652                                          *   1 means counter stop.                                                     */
7653             __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
7654                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7655                                          *   1 means counter stop.                                                     */
7656             __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
7657                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7658                                          *   1 means counter stop.                                                     */
7659             __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
7660                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7661                                          *   1 means counter stop.                                                     */
7662             __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
7663                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7664                                          *   1 means counter stop.                                                     */
7665             __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
7666                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7667                                          *   1 means counter stop.                                                     */
7668             __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
7669                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7670                                          *   1 means counter stop.                                                     */
7671             __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
7672                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7673                                          *   1 means counter stop.                                                     */
7674             __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
7675                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7676                                          *   1 means counter stop.                                                     */
7677             __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
7678                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7679                                          *   1 means counter stop.                                                     */
7680             __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
7681                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7682                                          *   1 means counter stop.                                                     */
7683             __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
7684                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7685                                          *   1 means counter stop.                                                     */
7686             __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
7687                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7688                                          *   1 means counter stop.                                                     */
7689             __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
7690                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7691                                          *   1 means counter stop.                                                     */
7692             __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
7693                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7694                                          *   1 means counter stop.                                                     */
7695             __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
7696                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7697                                          *   1 means counter stop.                                                     */
7698             __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
7699                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7700                                          *   1 means counter stop.                                                     */
7701             __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
7702                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7703                                          *   1 means counter stop.                                                     */
7704             __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
7705                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7706                                          *   1 means counter stop.                                                     */
7707         } GTSTP_b;
7708     };
7709 
7710     union
7711     {
7712         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
7713 
7714         struct
7715         {
7716             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
7717             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
7718             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
7719             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
7720             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
7721             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
7722             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
7723             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
7724             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
7725             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
7726             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
7727             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
7728             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
7729             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
7730             __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
7731             __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
7732             __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
7733             __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
7734             __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
7735             __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
7736             __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
7737             __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
7738             __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
7739             __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
7740             __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
7741             __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
7742             __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
7743             __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
7744             __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
7745             __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
7746             __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
7747             __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
7748         } GTCLR_b;
7749     };
7750 
7751     union
7752     {
7753         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
7754 
7755         struct
7756         {
7757             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
7758             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
7759             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
7760             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
7761             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
7762             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
7763             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
7764             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
7765             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7766                                           *   Counter Start Enable                                                      */
7767             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7768                                           *   Counter Start Enable                                                      */
7769             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7770                                           *   Counter Start Enable                                                      */
7771             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7772                                           *   Counter Start Enable                                                      */
7773             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7774                                           *   Counter Start Enable                                                      */
7775             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7776                                           *   Counter Start Enable                                                      */
7777             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7778                                           *   Counter Start Enable                                                      */
7779             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7780                                           *   Counter Start Enable                                                      */
7781             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
7782             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
7783             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
7784             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
7785             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
7786             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
7787             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
7788             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
7789             uint32_t              : 7;
7790             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
7791         } GTSSR_b;
7792     };
7793 
7794     union
7795     {
7796         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
7797 
7798         struct
7799         {
7800             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7801             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
7802             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7803             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
7804             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7805             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
7806             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7807             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
7808             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7809                                           *   Counter Stop Enable                                                       */
7810             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7811                                           *   Counter Stop Enable                                                       */
7812             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7813                                           *   Counter Stop Enable                                                       */
7814             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7815                                           *   Counter Stop Enable                                                       */
7816             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7817                                           *   Counter Stop Enable                                                       */
7818             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7819                                           *   Counter Stop Enable                                                       */
7820             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7821                                           *   Counter Stop Enable                                                       */
7822             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7823                                           *   Counter Stop Enable                                                       */
7824             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
7825             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
7826             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
7827             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
7828             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
7829             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
7830             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
7831             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
7832             uint32_t              : 7;
7833             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
7834         } GTPSR_b;
7835     };
7836 
7837     union
7838     {
7839         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
7840 
7841         struct
7842         {
7843             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
7844             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
7845             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
7846             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
7847             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
7848             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
7849             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
7850             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
7851             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7852                                           *   Counter Clear Enable                                                      */
7853             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7854                                           *   Counter Clear Enable                                                      */
7855             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7856                                           *   Counter Clear Enable                                                      */
7857             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7858                                           *   Counter Clear Enable                                                      */
7859             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7860                                           *   Counter Clear Enable                                                      */
7861             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7862                                           *   Counter Clear Enable                                                      */
7863             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7864                                           *   Counter Clear Enable                                                      */
7865             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7866                                           *   Counter Clear Enable                                                      */
7867             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
7868             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
7869             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
7870             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
7871             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
7872             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
7873             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
7874             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
7875             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
7876                                           *   Source Counter Clear Enable.                                              */
7877             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
7878                                           *   Enable (This bit is only available in GPT324 to GPT329.
7879                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
7880                                           *   should be 0.)                                                             */
7881             uint32_t            : 3;
7882             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
7883         } GTCSR_b;
7884     };
7885 
7886     union
7887     {
7888         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
7889 
7890         struct
7891         {
7892             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7893             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7894             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7895             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7896             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7897             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7898             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7899             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7900             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7901                                           *   Counter Count Up Enable                                                   */
7902             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7903                                           *   Counter Count Up Enable                                                   */
7904             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7905                                           *   Counter Count Up Enable                                                   */
7906             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7907                                           *   Counter Count Up Enable                                                   */
7908             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7909                                           *   Counter Count Up Enable                                                   */
7910             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7911                                           *   Counter Count Up Enable                                                   */
7912             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7913                                           *   Counter Count Up Enable                                                   */
7914             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7915                                           *   Counter Count Up Enable                                                   */
7916             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
7917             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
7918             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
7919             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
7920             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
7921             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
7922             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
7923             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
7924             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
7925             uint32_t              : 4;
7926         } GTUPSR_b;
7927     };
7928 
7929     union
7930     {
7931         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
7932 
7933         struct
7934         {
7935             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7936             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7937             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7938             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7939             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7940             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7941             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7942             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7943             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7944                                           *   Counter Count Down Enable                                                 */
7945             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7946                                           *   Counter Count Down Enable                                                 */
7947             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7948                                           *   Counter Count Down Enable                                                 */
7949             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7950                                           *   Counter Count Down Enable                                                 */
7951             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7952                                           *   Counter Count Down Enable                                                 */
7953             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7954                                           *   Counter Count Down Enable                                                 */
7955             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7956                                           *   Counter Count Down Enable                                                 */
7957             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7958                                           *   Counter Count Down Enable                                                 */
7959             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
7960             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
7961             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
7962             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
7963             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
7964             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
7965             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
7966             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
7967             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
7968             uint32_t              : 4;
7969         } GTDNSR_b;
7970     };
7971 
7972     union
7973     {
7974         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
7975                                           *                  Register A                                                 */
7976 
7977         struct
7978         {
7979             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7980             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
7981                                           *   Enable                                                                    */
7982             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7983             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
7984                                           *   Enable                                                                    */
7985             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7986             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
7987                                           *   Enable                                                                    */
7988             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7989             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
7990                                           *   Enable                                                                    */
7991             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7992                                           *   GTCCRA Input Capture Enable                                               */
7993             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7994                                           *   GTCCRA Input Capture Enable                                               */
7995             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7996                                           *   GTCCRA Input Capture Enable                                               */
7997             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7998                                           *   GTCCRA Input Capture Enable                                               */
7999             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
8000                                           *   GTCCRA Input Capture Enable                                               */
8001             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
8002                                           *   GTCCRA Input Capture Enable                                               */
8003             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
8004                                           *   GTCCRA Input Capture Enable                                               */
8005             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
8006                                           *   GTCCRA Input Capture Enable                                               */
8007             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8008             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8009             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8010             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8011             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8012             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8013             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8014             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
8015             __IOM uint32_t ASOC   : 1;   /*!< [24..24] Other channel Source GTCCRA Input Capture Enable                 */
8016             uint32_t              : 7;
8017         } GTICASR_b;
8018     };
8019 
8020     union
8021     {
8022         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
8023                                           *                  Register B                                                 */
8024 
8025         struct
8026         {
8027             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8028             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
8029                                           *   Enable                                                                    */
8030             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8031             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
8032                                           *   Enable                                                                    */
8033             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8034             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
8035                                           *   Enable                                                                    */
8036             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8037             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
8038                                           *   Enable                                                                    */
8039             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
8040                                           *   GTCCRB Input Capture Enable                                               */
8041             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
8042                                           *   GTCCRB Input Capture Enable                                               */
8043             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
8044                                           *   GTCCRB Input Capture Enable                                               */
8045             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
8046                                           *   GTCCRB Input Capture Enable                                               */
8047             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
8048                                           *   GTCCRB Input Capture Enable                                               */
8049             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
8050                                           *   GTCCRB Input Capture Enable                                               */
8051             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
8052                                           *   GTCCRB Input Capture Enable                                               */
8053             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
8054                                           *   GTCCRB Input Capture Enable                                               */
8055             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8056             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8057             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8058             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8059             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8060             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8061             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8062             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8063             __IOM uint32_t BSOC   : 1;   /*!< [24..24] Other channel Source GTCCRB Input Capture Enable                 */
8064             uint32_t              : 7;
8065         } GTICBSR_b;
8066     };
8067 
8068     union
8069     {
8070         __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
8071 
8072         struct
8073         {
8074             __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
8075             uint32_t               : 3;
8076             __IOM uint32_t AINV    : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control                 */
8077             __IOM uint32_t BINV    : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control                 */
8078             uint32_t               : 2;
8079             __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
8080             __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
8081             __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
8082             __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
8083             uint32_t               : 2;
8084             __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
8085             __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
8086             uint32_t               : 3;
8087             __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
8088             __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
8089             uint32_t               : 3;
8090         } GTCR_b;
8091     };
8092 
8093     union
8094     {
8095         __IOM uint32_t GTUDDTYC;        /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
8096                                          *                  Register                                                   */
8097 
8098         struct
8099         {
8100             __IOM uint32_t UD     : 1;  /*!< [0..0] Count Direction Setting                                            */
8101             __IOM uint32_t UDF    : 1;  /*!< [1..1] Forcible Count Direction Setting                                   */
8102             uint32_t              : 14;
8103             __IOM uint32_t OADTY  : 2;  /*!< [17..16] GTIOCA Output Duty Setting                                       */
8104             __IOM uint32_t OADTYF : 1;  /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
8105             __IOM uint32_t OADTYR : 1;  /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
8106                                          *   percent Duty Setting                                                      */
8107             uint32_t              : 4;
8108             __IOM uint32_t OBDTY  : 2;  /*!< [25..24] GTIOCB Output Duty Setting                                       */
8109             __IOM uint32_t OBDTYF : 1;  /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
8110             __IOM uint32_t OBDTYR : 1;  /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
8111                                          *   percent Duty Setting                                                      */
8112             __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection
8113                                          *   timing setting                                                            */
8114             uint32_t : 3;
8115         } GTUDDTYC_b;
8116     };
8117 
8118     union
8119     {
8120         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
8121 
8122         struct
8123         {
8124             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
8125             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
8126                                         *   Clear Disable.(This bit is only available in GPT324 to
8127                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
8128                                         *   write value should be 0.)                                                 */
8129             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
8130             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
8131             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
8132             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
8133             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
8134                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
8135                                         *   GPT323, this bit is read as 0. The write value should be
8136                                         *   0.)                                                                       */
8137             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
8138             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
8139             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
8140             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
8141             uint32_t              : 1;
8142             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
8143             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
8144             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
8145             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
8146             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
8147                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
8148                                         *   GPT323, this bit is read as 0. The write value should be
8149                                         *   0.)                                                                       */
8150             uint32_t             : 1;
8151             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
8152             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
8153         } GTIOR_b;
8154     };
8155 
8156     union
8157     {
8158         __IOM uint32_t GTINTAD;          /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
8159 
8160         struct
8161         {
8162             __IOM uint32_t GTINTA : 1;   /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt
8163                                           *   Enable                                                                    */
8164             __IOM uint32_t GTINTB : 1;   /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt
8165                                           *   Enable                                                                    */
8166             __IOM uint32_t GTINTC : 1;   /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt
8167                                           *   Enable                                                                    */
8168             __IOM uint32_t GTINTD : 1;   /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt
8169                                           *   Enable                                                                    */
8170             __IOM uint32_t GTINTE : 1;   /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt
8171                                           *   Enable                                                                    */
8172             __IOM uint32_t GTINTF : 1;   /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt
8173                                           *   Enable                                                                    */
8174             __IOM uint32_t GTINTPR : 2;  /*!< [7..6] GTPR Register Compare Match Interrupt Enable                       */
8175             __IOM uint32_t SCFA    : 1;  /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
8176                                           *   Clear Enable                                                              */
8177             __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
8178                                           *   Clear Enable                                                              */
8179             __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
8180                                           *   Synchronous Clear Enable                                                  */
8181             __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
8182                                           *   Synchronous Clear Enable                                                  */
8183             __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
8184                                           *   Synchronous Clear Enable                                                  */
8185             __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
8186                                           *   Synchronous Clear Enable                                                  */
8187             __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
8188             __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
8189             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
8190                                           *   Start Request Enable                                                      */
8191             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
8192                                           *   Conversion Start Request Enable                                           */
8193             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
8194                                           *   Start Request Enable                                                      */
8195             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
8196                                           *   Conversion Start Request Enable                                           */
8197             uint32_t               : 4;
8198             __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
8199             uint32_t               : 2;
8200             __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
8201             __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
8202             __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
8203             __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
8204         } GTINTAD_b;
8205     };
8206 
8207     union
8208     {
8209         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
8210 
8211         struct
8212         {
8213             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
8214             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
8215             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
8216             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
8217             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
8218             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
8219             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
8220             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
8221             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
8222                                          *   for counting the number of times a timer interrupt has
8223                                          *   been skipped.)                                                            */
8224             uint32_t               : 4;
8225             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
8226             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
8227                                          *   Request Interrupt Enable                                                  */
8228             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
8229                                          *   Start Request Flag                                                        */
8230             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
8231                                          *   Request Flag                                                              */
8232             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
8233                                          *   Start Request Flag                                                        */
8234             uint32_t             : 4;
8235             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
8236             uint32_t             : 3;
8237             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
8238             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
8239             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
8240             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
8241         } GTST_b;
8242     };
8243 
8244     union
8245     {
8246         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
8247 
8248         struct
8249         {
8250             __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
8251             __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
8252             __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
8253             __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
8254             uint32_t               : 4;
8255             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
8256             uint32_t               : 1;
8257             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
8258             uint32_t               : 5;
8259             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
8260             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
8261             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
8262             __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
8263                                          *   is read as 0.                                                             */
8264             uint32_t             : 1;
8265             __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
8266                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
8267                                          *   at an underflow (in down-counting) or overflow (in up-counting)
8268                                          *   is performed.                                                             */
8269             __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
8270             uint32_t             : 1;
8271             __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
8272                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
8273                                          *   at an underflow (in down-counting) or overflow (in up-counting)
8274                                          *   is performed.                                                             */
8275             __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
8276             uint32_t             : 1;
8277         } GTBER_b;
8278     };
8279 
8280     union
8281     {
8282         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
8283                                         *                  Start Request Skipping Setting Register                    */
8284 
8285         struct
8286         {
8287             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
8288             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
8289             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
8290             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
8291             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
8292             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
8293             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
8294             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
8295             uint32_t             : 1;
8296             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
8297             uint32_t             : 1;
8298             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
8299             uint32_t             : 17;
8300         } GTITC_b;
8301     };
8302 
8303     union
8304     {
8305         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
8306 
8307         struct
8308         {
8309             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
8310         } GTCNT_b;
8311     };
8312 
8313     union
8314     {
8315         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
8316 
8317         struct
8318         {
8319             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
8320         } GTCCR_b[6];
8321     };
8322 
8323     union
8324     {
8325         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
8326 
8327         struct
8328         {
8329             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
8330         } GTPR_b;
8331     };
8332 
8333     union
8334     {
8335         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
8336 
8337         struct
8338         {
8339             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
8340         } GTPBR_b;
8341     };
8342 
8343     union
8344     {
8345         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
8346                                          *                  Register                                                   */
8347 
8348         struct
8349         {
8350             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
8351         } GTPDBR_b;
8352     };
8353 
8354     union
8355     {
8356         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
8357 
8358         struct
8359         {
8360             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
8361         } GTADTRA_b;
8362     };
8363 
8364     union
8365     {
8366         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
8367                                            *                  A                                                          */
8368 
8369         struct
8370         {
8371             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
8372         } GTADTBRA_b;
8373     };
8374 
8375     union
8376     {
8377         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
8378                                             *                  Register A                                                 */
8379 
8380         struct
8381         {
8382             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
8383                                             *   A                                                                         */
8384         } GTADTDBRA_b;
8385     };
8386 
8387     union
8388     {
8389         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
8390 
8391         struct
8392         {
8393             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
8394         } GTADTRB_b;
8395     };
8396 
8397     union
8398     {
8399         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
8400                                            *                  B                                                          */
8401 
8402         struct
8403         {
8404             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
8405         } GTADTBRB_b;
8406     };
8407 
8408     union
8409     {
8410         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
8411                                             *                  Register B                                                 */
8412 
8413         struct
8414         {
8415             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
8416                                             *   B                                                                         */
8417         } GTADTDBRB_b;
8418     };
8419 
8420     union
8421     {
8422         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
8423 
8424         struct
8425         {
8426             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
8427             uint32_t             : 3;
8428             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
8429             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
8430             uint32_t             : 2;
8431             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
8432             uint32_t             : 23;
8433         } GTDTCR_b;
8434     };
8435 
8436     union
8437     {
8438         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
8439 
8440         struct
8441         {
8442             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
8443         } GTDVU_b;
8444     };
8445 
8446     union
8447     {
8448         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
8449 
8450         struct
8451         {
8452             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
8453         } GTDVD_b;
8454     };
8455 
8456     union
8457     {
8458         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
8459 
8460         struct
8461         {
8462             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
8463         } GTDBU_b;
8464     };
8465 
8466     union
8467     {
8468         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
8469 
8470         struct
8471         {
8472             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
8473         } GTDBD_b;
8474     };
8475 
8476     union
8477     {
8478         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
8479                                         *                  Status Register                                            */
8480 
8481         struct
8482         {
8483             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
8484             uint32_t          : 30;
8485         } GTSOS_b;
8486     };
8487 
8488     union
8489     {
8490         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
8491                                         *                  Temporary Release Register                                 */
8492 
8493         struct
8494         {
8495             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
8496             uint32_t            : 31;
8497         } GTSOTR_b;
8498     };
8499 
8500     union
8501     {
8502         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
8503                                          *                  Signal Monitoring Register                                 */
8504 
8505         struct
8506         {
8507             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
8508             uint32_t               : 6;
8509             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
8510                                          *   Enabling                                                                  */
8511             uint32_t               : 7;
8512             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
8513             uint32_t               : 6;
8514             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
8515                                          *   Enabling                                                                  */
8516             uint32_t : 7;
8517         } GTADSMR_b;
8518     };
8519 
8520     union
8521     {
8522         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
8523                                            *                  Counter Control Register                                   */
8524 
8525         struct
8526         {
8527             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
8528             uint32_t               : 2;
8529             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
8530             uint32_t               : 4;
8531             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
8532             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
8533                                            *   select                                                                    */
8534             uint32_t                 : 2;
8535             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
8536             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
8537             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
8538         } GTEITC_b;
8539     };
8540 
8541     union
8542     {
8543         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
8544                                         *                  Setting Register 1                                         */
8545 
8546         struct
8547         {
8548             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
8549                                         *   Extended Skipping Function Select                                         */
8550             uint32_t             : 1;
8551             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
8552                                         *   Extended Skipping Function Select                                         */
8553             uint32_t             : 1;
8554             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
8555                                         *   Function Select                                                           */
8556             uint32_t             : 1;
8557             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
8558                                         *   Function Select                                                           */
8559             uint32_t             : 1;
8560             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
8561                                         *   Function Select                                                           */
8562             uint32_t             : 1;
8563             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
8564                                         *   Function Select                                                           */
8565             uint32_t             : 1;
8566             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
8567             uint32_t             : 1;
8568             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
8569             uint32_t             : 1;
8570         } GTEITLI1_b;
8571     };
8572 
8573     union
8574     {
8575         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
8576                                         *                  Setting Register 2                                         */
8577 
8578         struct
8579         {
8580             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
8581                                         *   Skipping Function Select                                                  */
8582             uint32_t              : 1;
8583             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
8584                                         *   Skipping Function Select                                                  */
8585             uint32_t : 25;
8586         } GTEITLI2_b;
8587     };
8588 
8589     union
8590     {
8591         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
8592                                          *                  Setting Register                                           */
8593 
8594         struct
8595         {
8596             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
8597                                          *   Select                                                                    */
8598             uint32_t              : 1;
8599             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
8600                                          *   Select                                                                    */
8601             uint32_t              : 1;
8602             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
8603                                          *   Select                                                                    */
8604             uint32_t               : 5;
8605             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
8606                                          *   Function Select                                                           */
8607             uint32_t               : 1;
8608             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
8609                                          *   Function Select                                                           */
8610             uint32_t               : 1;
8611             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
8612                                          *   Select                                                                    */
8613             uint32_t               : 1;
8614             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
8615                                          *   Select                                                                    */
8616             uint32_t : 1;
8617         } GTEITLB_b;
8618     };
8619 
8620     union
8621     {
8622         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
8623                                           *                  Function Setting Register                                  */
8624 
8625         struct
8626         {
8627             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
8628             uint32_t                : 1;
8629             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
8630             uint32_t                : 6;
8631             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
8632             uint32_t                : 1;
8633             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
8634             uint32_t                : 6;
8635         } GTICLF_b;
8636     };
8637 
8638     union
8639     {
8640         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
8641 
8642         struct
8643         {
8644             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
8645             uint32_t            : 7;
8646             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
8647             uint32_t            : 7;
8648             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
8649             uint32_t            : 4;
8650         } GTPC_b;
8651     };
8652 
8653     union
8654     {
8655         __IOM uint32_t GTADCMSC;            /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request
8656                                              *                  Compare Match Skipping Control Register                    */
8657 
8658         struct
8659         {
8660             __IOM uint32_t ADCMSC1 : 2;     /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter
8661                                              *   1 Count Source Select                                                     */
8662             uint32_t               : 2;
8663             __IOM uint32_t ADCMST1 : 4;     /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1
8664                                              *   Skipping Count Setting                                                    */
8665             __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping
8666                                              *   Counter 1 Initial Value                                                   */
8667             __IM uint32_t ADCMSCNT1 : 4;    /*!< [15..12] A/D Conversion Start Request Compare Match Skipping
8668                                              *   Counter 1                                                                 */
8669             __IOM uint32_t ADCMSC2 : 2;     /*!< [17..16] A/D Conversion Start Request Compare Match Skipping
8670                                              *   Counter 2 Count Source Select                                             */
8671             uint32_t               : 2;
8672             __IOM uint32_t ADCMST2 : 4;     /*!< [23..20] A/D Conversion Start Request Compare Match Skipping
8673                                              *   2 Skipping Count Setting                                                  */
8674             __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping
8675                                              *   Counter 2 Initial Value                                                   */
8676             __IM uint32_t ADCMSCNT2 : 4;    /*!< [31..28] A/D Conversion Start Request Compare Match Skipping
8677                                              *   Counter 2                                                                 */
8678         } GTADCMSC_b;
8679     };
8680 
8681     union
8682     {
8683         __IOM uint32_t GTADCMSS;        /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request
8684                                          *                  Compare Match Skipping Setting Register                    */
8685 
8686         struct
8687         {
8688             __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare
8689                                          *   Match Skipping Function Select                                            */
8690             uint32_t               : 1;
8691             __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare
8692                                          *   Match Skipping Function Select                                            */
8693             uint32_t               : 9;
8694             __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion
8695                                          *   Start Request Compare Match Skipping Function Select                      */
8696             uint32_t               : 1;
8697             __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion
8698                                          *   Start Request Compare Match Skipping Function Select                      */
8699             uint32_t : 9;
8700         } GTADCMSS_b;
8701     };
8702     __IM uint32_t RESERVED[2];
8703 
8704     union
8705     {
8706         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
8707                                          *                  Control Channel Select Register                            */
8708 
8709         struct
8710         {
8711             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
8712                                          *   Select                                                                    */
8713             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
8714                                          *   Select                                                                    */
8715             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
8716                                          *   Select                                                                    */
8717             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
8718                                          *   Select                                                                    */
8719             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
8720                                          *   Select                                                                    */
8721             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
8722                                          *   Select                                                                    */
8723             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
8724                                          *   Select                                                                    */
8725             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
8726                                          *   Select                                                                    */
8727             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
8728                                          *   Select                                                                    */
8729             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
8730                                          *   Select                                                                    */
8731             uint32_t : 22;
8732         } GTSECSR_b;
8733     };
8734 
8735     union
8736     {
8737         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
8738                                         *                  Control Register                                           */
8739 
8740         struct
8741         {
8742             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
8743             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
8744             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
8745             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
8746             uint32_t             : 4;
8747             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
8748             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
8749             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
8750             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
8751             uint32_t             : 4;
8752             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
8753             __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
8754             uint32_t             : 6;
8755             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
8756             __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
8757             uint32_t             : 6;
8758         } GTSECR_b;
8759     };
8760     __IM uint32_t RESERVED1[2];
8761 
8762     union
8763     {
8764         __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
8765 
8766         struct
8767         {
8768             __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
8769                                         *   Disable                                                                   */
8770             __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
8771                                         *   Disable                                                                   */
8772             __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
8773             __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
8774                                         *   Disable                                                                   */
8775             __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
8776                                         *   Disable                                                                   */
8777             __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
8778                                         *   Disable                                                                   */
8779             uint32_t             : 2;
8780             __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
8781                                         *   Enable                                                                    */
8782             __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
8783                                         *   Enable                                                                    */
8784             uint32_t              : 1;
8785             __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
8786                                         *   Enable                                                                    */
8787             __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
8788                                         *   Enable                                                                    */
8789             uint32_t             : 1;
8790             __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
8791                                         *   Disable                                                                   */
8792             __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
8793                                         *   Disable                                                                   */
8794             __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
8795                                         *   Disable                                                                   */
8796             __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
8797                                         *   Disable                                                                   */
8798             __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
8799                                         *   Disable                                                                   */
8800             __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
8801                                         *   Transfer Disable                                                          */
8802             uint32_t             : 2;
8803             __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
8804             __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
8805             __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
8806             __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
8807             uint32_t             : 2;
8808         } GTBER2_b;
8809     };
8810 
8811     union
8812     {
8813         __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
8814 
8815         struct
8816         {
8817             __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
8818             uint32_t              : 11;
8819             __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
8820             uint32_t              : 11;
8821         } GTOLBR_b;
8822     };
8823     __IM uint32_t RESERVED2;
8824 
8825     union
8826     {
8827         __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
8828                                         *                  Capture Control Register                                   */
8829 
8830         struct
8831         {
8832             __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
8833                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
8834             __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
8835                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
8836             __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
8837                                         *   Channel GTCCRA Input Capture Source Enable                                */
8838             __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
8839                                         *   Channel GTCCRA Input Capture Source Enable                                */
8840             __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
8841                                         *   Channel GTCCRA Input Capture Source Enable                                */
8842             __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
8843                                         *   Channel GTCCRA Input Capture Source Enable                                */
8844             __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
8845                                         *   Source Enable                                                             */
8846             __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
8847                                         *   Source Enable                                                             */
8848             __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
8849                                         *   Capture Source Enable                                                     */
8850             uint32_t              : 5;
8851             __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
8852             __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
8853                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
8854             __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
8855                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
8856             __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
8857                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8858             __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
8859                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8860             __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
8861                                         *   Other Channel GTCCRb Input Capture Source Enable                          */
8862             __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
8863                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8864             __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
8865                                         *   Source Enable                                                             */
8866             __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
8867                                         *   Capture Source Enable                                                     */
8868             __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
8869                                         *   Capture Source Enable                                                     */
8870             uint32_t              : 5;
8871             __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
8872         } GTICCR_b;
8873     };
8874 } R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
8875 
8876 /* =========================================================================================================================== */
8877 /* ================                                         R_GPT_OPS                                         ================ */
8878 /* =========================================================================================================================== */
8879 
8880 /**
8881  * @brief Output Phase Switching for GPT (R_GPT_OPS)
8882  */
8883 
8884 typedef struct                         /*!< (@ 0x40169A00) R_GPT_OPS Structure                                        */
8885 {
8886     union
8887     {
8888         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
8889 
8890         struct
8891         {
8892             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
8893                                         *   by the software settings.This bit setting is valid when
8894                                         *   the OPSCR.FB bit = 1.                                                     */
8895             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
8896                                         *   by the software settings.This bit setting is valid when
8897                                         *   the OPSCR.FB bit = 1.                                                     */
8898             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
8899                                         *   by the software settings.This bit setting is valid when
8900                                         *   the OPSCR.FB bit = 1.                                                     */
8901             uint32_t        : 1;
8902             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
8903                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8904                                         *   e settings (UF/VF/WF)                                                     */
8905             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
8906                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8907                                         *   e settings (UF/VF/WF)                                                     */
8908             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
8909                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8910                                         *   e settings (UF/VF/WF)                                                     */
8911             uint32_t          : 1;
8912             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
8913             uint32_t          : 7;
8914             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
8915                                         *   input phase from the software settings and external input.                */
8916             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
8917             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
8918             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
8919             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
8920             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
8921             uint32_t             : 2;
8922             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
8923             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
8924             uint32_t             : 2;
8925             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
8926             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
8927                                         *   sampling clock setting of the external input.                             */
8928         } OPSCR_b;
8929     };
8930 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
8931 
8932 /* =========================================================================================================================== */
8933 /* ================                                        R_GPT_POEG0                                        ================ */
8934 /* =========================================================================================================================== */
8935 
8936 /**
8937  * @brief Port Output Enable for GPT (R_GPT_POEG0)
8938  */
8939 
8940 typedef struct                         /*!< (@ 0x4008A000) R_GPT_POEG0 Structure                                      */
8941 {
8942     union
8943     {
8944         __IOM uint32_t POEGG;          /*!< (@ 0x00000000) POEG Group Setting Register                                */
8945 
8946         struct
8947         {
8948             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
8949             __IOM uint32_t IOCF  : 1;  /*!< [1..1] Real Time Overcurrent Detection Flag                               */
8950             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
8951             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
8952             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
8953                                         *   once after a reset.                                                       */
8954             __IOM uint32_t IOCE : 1;   /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
8955                                         *   only once after a reset.                                                  */
8956             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
8957                                         *   only once after a reset.                                                  */
8958             uint32_t             : 1;
8959             __IOM uint32_t CDRE0 : 1;  /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
8960                                         *   only once after a reset.                                                  */
8961             __IOM uint32_t CDRE1 : 1;  /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
8962                                         *   only once after a reset.                                                  */
8963             __IOM uint32_t CDRE2 : 1;  /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
8964                                         *   only once after a reset.                                                  */
8965             __IOM uint32_t CDRE3 : 1;  /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
8966                                         *   only once after a reset.                                                  */
8967             __IOM uint32_t CDRE4 : 1;  /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
8968                                         *   only once after a reset.                                                  */
8969             __IOM uint32_t CDRE5 : 1;  /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
8970                                         *   only once after a reset.                                                  */
8971             uint32_t            : 2;
8972             __IM uint32_t ST    : 1;   /*!< [16..16] GTETRG Input Status Flag                                         */
8973             uint32_t            : 11;
8974             __IOM uint32_t INV  : 1;   /*!< [28..28] GTETRG Input Reverse                                             */
8975             __IOM uint32_t NFEN : 1;   /*!< [29..29] Noise Filter Enable                                              */
8976             __IOM uint32_t NFCS : 2;   /*!< [31..30] Noise Filter Clock Select                                        */
8977         } POEGG_b;
8978     };
8979     __IM uint32_t RESERVED[15];
8980 
8981     union
8982     {
8983         __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
8984                                         *                  Register                                                   */
8985 
8986         struct
8987         {
8988             __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
8989             uint16_t             : 7;
8990             __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
8991         } GTONCWP_b;
8992     };
8993     __IM uint16_t RESERVED1;
8994 
8995     union
8996     {
8997         __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
8998                                         *                  Register                                                   */
8999 
9000         struct
9001         {
9002             __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
9003             uint16_t           : 3;
9004             __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
9005             __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
9006             uint16_t           : 7;
9007         } GTONCCR_b;
9008     };
9009     __IM uint16_t RESERVED2;
9010 } R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */
9011 
9012 /* =========================================================================================================================== */
9013 /* ================                                           R_ICU                                           ================ */
9014 /* =========================================================================================================================== */
9015 
9016 /**
9017  * @brief Interrupt Controller Unit (R_ICU)
9018  */
9019 
9020 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
9021 {
9022     union
9023     {
9024         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
9025 
9026         struct
9027         {
9028             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
9029             uint8_t               : 1;
9030             __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select                     */
9031             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
9032             uint8_t               : 1;
9033             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
9034         } IRQCR_b[16];
9035     };
9036     __IM uint32_t RESERVED[60];
9037 
9038     union
9039     {
9040         __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
9041 
9042         struct
9043         {
9044             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
9045             uint8_t                : 3;
9046             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
9047             uint8_t                : 1;
9048             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
9049         } NMICR_b;
9050     };
9051     __IM uint8_t  RESERVED1;
9052     __IM uint16_t RESERVED2;
9053     __IM uint32_t RESERVED3[7];
9054 
9055     union
9056     {
9057         __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
9058 
9059         struct
9060         {
9061             __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
9062             __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
9063             __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
9064             __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
9065             __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
9066             uint16_t               : 1;
9067             __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
9068             __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
9069             __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
9070             __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
9071             __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
9072             __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
9073             __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
9074             __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
9075             uint16_t               : 1;
9076             __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
9077         } NMIER_b;
9078     };
9079     __IM uint16_t RESERVED4;
9080     __IM uint32_t RESERVED5[3];
9081 
9082     union
9083     {
9084         __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
9085 
9086         struct
9087         {
9088             __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
9089             __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
9090             __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
9091             __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
9092             __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
9093             uint16_t               : 1;
9094             __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
9095             __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
9096             __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
9097             __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
9098             __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
9099             __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
9100             __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
9101             __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
9102             uint16_t               : 1;
9103             __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
9104         } NMICLR_b;
9105     };
9106     __IM uint16_t RESERVED6;
9107     __IM uint32_t RESERVED7[3];
9108 
9109     union
9110     {
9111         __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
9112 
9113         struct
9114         {
9115             __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
9116             __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
9117             __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
9118             __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
9119             __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
9120             uint16_t              : 1;
9121             __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
9122             __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
9123             __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
9124             __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
9125             __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
9126             __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
9127             __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
9128             __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
9129             uint16_t              : 1;
9130             __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
9131         } NMISR_b;
9132     };
9133     __IM uint16_t RESERVED8;
9134     __IM uint32_t RESERVED9[23];
9135 
9136     union
9137     {
9138         __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
9139 
9140         struct
9141         {
9142             __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
9143             __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
9144             __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
9145             __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
9146             __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
9147             __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
9148             __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
9149             __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
9150             __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
9151             __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
9152             __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
9153             __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
9154             __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
9155             __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
9156             __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
9157             __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
9158             __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
9159             __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
9160             __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
9161             __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
9162             __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
9163             uint32_t                    : 1;
9164             __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
9165             __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
9166             __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
9167             __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
9168             __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
9169             __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
9170             __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
9171             __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
9172                                               *   enable                                                                    */
9173             __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
9174                                               *   enable                                                                    */
9175             __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
9176         } WUPEN_b;
9177     };
9178 
9179     union
9180     {
9181         __IOM uint32_t WUPEN1;         /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
9182 
9183         struct
9184         {
9185             uint32_t                 : 7;
9186             __IOM uint32_t SOSCWUPEN : 1; /*!< [7..7] Sub Oscillation Stop Detection Interrupt Software Standby/Snooze
9187                                            *   Mode Returns Enable Bit                                                   */
9188             uint32_t                : 3;
9189             __IOM uint32_t I3CWUPEN : 1;  /*!< [11..11] I3C Wakeup Condition Detection Interrupt Software Standby/Snooze
9190                                            *   Mode Returns Enable Bit                                                   */
9191             uint32_t : 20;
9192         } WUPEN1_b;
9193     };
9194 
9195     union
9196     {
9197         __IOM uint32_t WUPEN2;                 /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2                        */
9198 
9199         struct
9200         {
9201             __IOM uint32_t INTUR0WUPEN : 1;    /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return
9202                                                 *   Enable                                                                    */
9203             __IOM uint32_t INTURE0WUPEN : 1;   /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode
9204                                                 *   Return Enable                                                             */
9205             __IOM uint32_t INTUR1WUPEN : 1;    /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return
9206                                                 *   Enable                                                                    */
9207             __IOM uint32_t INTURE1WUPEN : 1;   /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode
9208                                                 *   Return Enable                                                             */
9209             __IOM uint32_t EXLVDVBATWUPEN : 1; /*!< [4..4] LVD_EXLVDVBAT Interrupt Software Standby/Snooze Mode
9210                                                 *   Returns Enable Bit                                                        */
9211             __IOM uint32_t LVDVRTCWUPEN : 1;   /*!< [5..5] LVD_VRTC Interrupt Software Standby/Snooze Mode Returns
9212                                                 *   Enable Bit                                                                */
9213             __IOM uint32_t EXLVDWUPEN : 1;     /*!< [6..6] LVD_EXLVD Interrupt Software Standby/Snooze Mode Returns
9214                                                 *   Enable Bit                                                                */
9215             uint32_t : 25;
9216         } WUPEN2_b;
9217     };
9218     __IM uint32_t RESERVED10[5];
9219 
9220     union
9221     {
9222         __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
9223 
9224         struct
9225         {
9226             __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
9227                                          *   = 1)                                                                      */
9228             __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
9229                                          *   LPOPTEN bit = 1)                                                          */
9230             uint8_t : 6;
9231         } IELEN_b;
9232     };
9233     __IM uint8_t  RESERVED11;
9234     __IM uint16_t RESERVED12;
9235     __IM uint32_t RESERVED13[15];
9236 
9237     union
9238     {
9239         __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
9240 
9241         struct
9242         {
9243             __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
9244             uint16_t            : 7;
9245         } SELSR0_b;
9246     };
9247     __IM uint16_t RESERVED14;
9248     __IM uint32_t RESERVED15[31];
9249 
9250     union
9251     {
9252         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
9253 
9254         struct
9255         {
9256             __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
9257             uint32_t            : 7;
9258             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
9259                                         *   IR flag is prohibited.                                                    */
9260             uint32_t : 15;
9261         } DELSR_b[8];
9262     };
9263     __IM uint32_t RESERVED16[24];
9264 
9265     union
9266     {
9267         __IOM uint32_t IELSR[64];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..63]                    */
9268 
9269         struct
9270         {
9271             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
9272                                         *   signal to be linked .                                                     */
9273             uint32_t            : 7;
9274             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
9275             uint32_t            : 7;
9276             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
9277             uint32_t            : 7;
9278         } IELSR_b[64];
9279     };
9280 } R_ICU_Type;                          /*!< Size = 1024 (0x400)                                                       */
9281 
9282 /* =========================================================================================================================== */
9283 /* ================                                          R_IIC0                                           ================ */
9284 /* =========================================================================================================================== */
9285 
9286 /**
9287  * @brief I2C Bus Interface (R_IIC0)
9288  */
9289 
9290 typedef struct                         /*!< (@ 0x4009F000) R_IIC0 Structure                                           */
9291 {
9292     union
9293     {
9294         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
9295 
9296         struct
9297         {
9298             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
9299             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
9300             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
9301             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
9302             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
9303             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
9304             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
9305                                         *   is initiated using the IICRST bit for a bus hang-up occurred
9306                                         *   during communication with the master device in slave mode,
9307                                         *   the states may become different between the slave device
9308                                         *   and the master device (due to the difference in the bit
9309                                         *   counter information).                                                     */
9310             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
9311         } ICCR1_b;
9312     };
9313 
9314     union
9315     {
9316         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
9317 
9318         struct
9319         {
9320             uint8_t          : 1;
9321             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
9322                                         *   condition issuance request) when the BBSY flag is set to
9323                                         *   0 (bus free state).                                                       */
9324             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
9325                                         *   RS bit to 1 while issuing a stop condition.                               */
9326             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
9327                                         *   bit is not possible while the setting of the BBSY flag
9328                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
9329                                         *   while a restart condition is being issued.                                */
9330             uint8_t            : 1;
9331             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
9332             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
9333             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
9334         } ICCR2_b;
9335     };
9336 
9337     union
9338     {
9339         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
9340 
9341         struct
9342         {
9343             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
9344             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
9345             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
9346                                         *   / 2^CKS )                                                                 */
9347             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
9348         } ICMR1_b;
9349     };
9350 
9351     union
9352     {
9353         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
9354 
9355         struct
9356         {
9357             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
9358             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
9359             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
9360             uint8_t            : 1;
9361             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
9362             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
9363         } ICMR2_b;
9364     };
9365 
9366     union
9367     {
9368         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
9369 
9370         struct
9371         {
9372             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
9373             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
9374             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
9375             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
9376             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
9377             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
9378                                         *   be sure to read the ICDRR beforehand.                                     */
9379             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
9380         } ICMR3_b;
9381     };
9382 
9383     union
9384     {
9385         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
9386 
9387         struct
9388         {
9389             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
9390             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
9391             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
9392             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
9393             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
9394             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
9395             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
9396             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
9397         } ICFER_b;
9398     };
9399 
9400     union
9401     {
9402         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
9403 
9404         struct
9405         {
9406             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
9407             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
9408             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
9409             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
9410             uint8_t             : 1;
9411             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
9412             uint8_t             : 1;
9413             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
9414         } ICSER_b;
9415     };
9416 
9417     union
9418     {
9419         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
9420 
9421         struct
9422         {
9423             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
9424             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
9425             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
9426             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
9427             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
9428             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
9429             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
9430             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
9431         } ICIER_b;
9432     };
9433 
9434     union
9435     {
9436         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
9437 
9438         struct
9439         {
9440             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
9441             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
9442             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
9443             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
9444             uint8_t            : 1;
9445             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
9446             uint8_t            : 1;
9447             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
9448         } ICSR1_b;
9449     };
9450 
9451     union
9452     {
9453         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
9454 
9455         struct
9456         {
9457             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
9458             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
9459             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
9460             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
9461             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
9462             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
9463             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
9464             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
9465         } ICSR2_b;
9466     };
9467     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
9468 
9469     union
9470     {
9471         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
9472 
9473         struct
9474         {
9475             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
9476             uint8_t           : 3;
9477         } ICBRL_b;
9478     };
9479 
9480     union
9481     {
9482         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
9483 
9484         struct
9485         {
9486             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
9487             uint8_t           : 3;
9488         } ICBRH_b;
9489     };
9490 
9491     union
9492     {
9493         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
9494 
9495         struct
9496         {
9497             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
9498         } ICDRT_b;
9499     };
9500 
9501     union
9502     {
9503         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
9504 
9505         struct
9506         {
9507             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
9508         } ICDRR_b;
9509     };
9510     __IM uint8_t RESERVED[2];
9511 
9512     union
9513     {
9514         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
9515 
9516         struct
9517         {
9518             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
9519             uint8_t             : 3;
9520             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
9521             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
9522             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
9523             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
9524         } ICWUR_b;
9525     };
9526 
9527     union
9528     {
9529         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
9530 
9531         struct
9532         {
9533             __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
9534             __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
9535             __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
9536             uint8_t              : 5;
9537         } ICWUR2_b;
9538     };
9539 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
9540 
9541 /* =========================================================================================================================== */
9542 /* ================                                          R_IRDA                                           ================ */
9543 /* =========================================================================================================================== */
9544 
9545 /**
9546  * @brief IrDA Interface (R_IRDA)
9547  */
9548 
9549 typedef struct                         /*!< (@ 0x40118F00) R_IRDA Structure                                           */
9550 {
9551     union
9552     {
9553         __IOM uint8_t IRCR;            /*!< (@ 0x00000000) IrDA Control Register                                      */
9554 
9555         struct
9556         {
9557             uint8_t               : 2;
9558             __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching                                           */
9559             __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching                                           */
9560             uint8_t               : 3;
9561             __IOM uint8_t IRE     : 1; /*!< [7..7] IrDA Enable                                                        */
9562         } IRCR_b;
9563     };
9564 } R_IRDA_Type;                         /*!< Size = 1 (0x1)                                                            */
9565 
9566 /* =========================================================================================================================== */
9567 /* ================                                          R_IWDT                                           ================ */
9568 /* =========================================================================================================================== */
9569 
9570 /**
9571  * @brief Independent Watchdog Timer (R_IWDT)
9572  */
9573 
9574 typedef struct                         /*!< (@ 0x40083200) R_IWDT Structure                                           */
9575 {
9576     union
9577     {
9578         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
9579 
9580         struct
9581         {
9582             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
9583                                         *   0xFF to this register.                                                    */
9584         } IWDTRR_b;
9585     };
9586     __IM uint8_t RESERVED;
9587 
9588     union
9589     {
9590         __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
9591 
9592         struct
9593         {
9594             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
9595             uint16_t            : 2;
9596             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
9597             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
9598             uint16_t            : 2;
9599             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
9600             uint16_t            : 2;
9601         } IWDTCR_b;
9602     };
9603 
9604     union
9605     {
9606         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
9607 
9608         struct
9609         {
9610             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
9611             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
9612             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
9613         } IWDTSR_b;
9614     };
9615 
9616     union
9617     {
9618         __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
9619 
9620         struct
9621         {
9622             uint8_t               : 7;
9623             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
9624         } IWDTRCR_b;
9625     };
9626     __IM uint8_t RESERVED1;
9627 
9628     union
9629     {
9630         __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
9631 
9632         struct
9633         {
9634             uint8_t              : 7;
9635             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
9636         } IWDTCSTPR_b;
9637     };
9638     __IM uint8_t  RESERVED2;
9639     __IM uint16_t RESERVED3;
9640 } R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
9641 
9642 /* =========================================================================================================================== */
9643 /* ================                                          R_I3C0                                           ================ */
9644 /* =========================================================================================================================== */
9645 
9646 /**
9647  * @brief I3C Bus Interface (R_I3C0)
9648  */
9649 
9650 typedef struct                         /*!< (@ 0x4011F000) R_I3C0 Structure                                           */
9651 {
9652     union
9653     {
9654         __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
9655 
9656         struct
9657         {
9658             __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
9659             uint32_t             : 31;
9660         } PRTS_b;
9661     };
9662     __IM uint32_t RESERVED[3];
9663 
9664     union
9665     {
9666         __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
9667 
9668         struct
9669         {
9670             __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
9671             uint32_t            : 31;
9672         } CECTL_b;
9673     };
9674 
9675     union
9676     {
9677         __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
9678 
9679         struct
9680         {
9681             __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
9682             uint32_t                : 6;
9683             __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
9684             __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
9685             uint32_t                : 20;
9686             __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
9687             __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
9688             __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
9689         } BCTL_b;
9690     };
9691 
9692     union
9693     {
9694         __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
9695 
9696         struct
9697         {
9698             uint32_t              : 16;
9699             __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
9700             uint32_t              : 8;
9701             __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
9702         } MSDVAD_b;
9703     };
9704     __IM uint32_t RESERVED1;
9705 
9706     union
9707     {
9708         __IOM uint32_t RSTCTL;           /*!< (@ 0x00000020) Reset Control Register                                     */
9709 
9710         struct
9711         {
9712             __IOM uint32_t RI3CRST  : 1; /*!< [0..0] I3C Software Reset                                                 */
9713             __IOM uint32_t CMDQRST  : 1; /*!< [1..1] Command Queue Software Reset                                       */
9714             __IOM uint32_t RSPQRST  : 1; /*!< [2..2] Response Queue Software Reset                                      */
9715             __IOM uint32_t TDBRST   : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
9716             __IOM uint32_t RDBRST   : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
9717             __IOM uint32_t IBIQRST  : 1; /*!< [5..5] IBI Queue Software Reset                                           */
9718             __IOM uint32_t RSQRST   : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
9719             uint32_t                : 2;
9720             __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset                         */
9721             __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese                       */
9722             __IOM uint32_t HTDBRST  : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset                      */
9723             __IOM uint32_t HRDBRST  : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset                      */
9724             uint32_t                : 3;
9725             __IOM uint32_t INTLRST  : 1; /*!< [16..16] Internal Software Reset                                          */
9726             uint32_t                : 15;
9727         } RSTCTL_b;
9728     };
9729 
9730     union
9731     {
9732         __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
9733 
9734         struct
9735         {
9736             uint32_t              : 2;
9737             __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
9738             uint32_t              : 1;
9739             __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
9740             uint32_t              : 2;
9741             __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
9742             uint32_t              : 24;
9743         } PRSST_b;
9744     };
9745     __IM uint32_t RESERVED2[2];
9746 
9747     union
9748     {
9749         __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
9750 
9751         struct
9752         {
9753             uint32_t            : 10;
9754             __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
9755             uint32_t            : 21;
9756         } INST_b;
9757     };
9758 
9759     union
9760     {
9761         __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
9762 
9763         struct
9764         {
9765             uint32_t            : 10;
9766             __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
9767             uint32_t            : 21;
9768         } INSTE_b;
9769     };
9770 
9771     union
9772     {
9773         __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
9774 
9775         struct
9776         {
9777             uint32_t             : 10;
9778             __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
9779             uint32_t             : 21;
9780         } INIE_b;
9781     };
9782 
9783     union
9784     {
9785         __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
9786 
9787         struct
9788         {
9789             uint32_t            : 10;
9790             __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
9791             uint32_t            : 21;
9792         } INSTFC_b;
9793     };
9794     __IM uint32_t RESERVED3;
9795 
9796     union
9797     {
9798         __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
9799 
9800         struct
9801         {
9802             uint32_t          : 19;
9803             __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
9804             uint32_t          : 8;
9805         } DVCT_b;
9806     };
9807     __IM uint32_t RESERVED4[4];
9808 
9809     union
9810     {
9811         __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
9812 
9813         struct
9814         {
9815             __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
9816             __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
9817             uint32_t                : 1;
9818             __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
9819             uint32_t                : 28;
9820         } IBINCTL_b;
9821     };
9822     __IM uint32_t RESERVED5;
9823 
9824     union
9825     {
9826         __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
9827 
9828         struct
9829         {
9830             __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
9831             __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
9832             __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
9833             uint32_t              : 5;
9834             __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
9835             uint32_t              : 3;
9836             __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
9837             uint32_t              : 1;
9838             __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
9839             __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
9840             uint32_t              : 16;
9841         } BFCTL_b;
9842     };
9843 
9844     union
9845     {
9846         __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
9847 
9848         struct
9849         {
9850             __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
9851             uint32_t             : 4;
9852             __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
9853             __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
9854             uint32_t             : 8;
9855             __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
9856             __IOM uint32_t SVAEn : 3;  /*!< [18..16] Slave Address Enable                                             */
9857             uint32_t             : 13;
9858         } SVCTL_b;
9859     };
9860     __IM uint32_t RESERVED6[2];
9861 
9862     union
9863     {
9864         __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
9865 
9866         struct
9867         {
9868             __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
9869             uint32_t               : 29;
9870         } REFCKCTL_b;
9871     };
9872 
9873     union
9874     {
9875         __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
9876 
9877         struct
9878         {
9879             __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
9880             __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
9881             __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
9882             uint32_t              : 2;
9883             __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
9884             uint32_t              : 1;
9885             __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
9886         } STDBR_b;
9887     };
9888 
9889     union
9890     {
9891         __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
9892 
9893         struct
9894         {
9895             __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
9896             __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
9897             __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
9898             uint32_t             : 2;
9899             __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull                    */
9900             uint32_t             : 2;
9901         } EXTBR_b;
9902     };
9903 
9904     union
9905     {
9906         __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
9907 
9908         struct
9909         {
9910             __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
9911             uint32_t              : 23;
9912         } BFRECDT_b;
9913     };
9914 
9915     union
9916     {
9917         __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
9918 
9919         struct
9920         {
9921             __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
9922             uint32_t              : 23;
9923         } BAVLCDT_b;
9924     };
9925 
9926     union
9927     {
9928         __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
9929 
9930         struct
9931         {
9932             __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
9933             uint32_t              : 14;
9934         } BIDLCDT_b;
9935     };
9936 
9937     union
9938     {
9939         __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
9940 
9941         struct
9942         {
9943             __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
9944             __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
9945             __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
9946             uint32_t              : 1;
9947             __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
9948             uint32_t              : 3;
9949             __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
9950             uint32_t              : 4;
9951             __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
9952             uint32_t              : 16;
9953         } OUTCTL_b;
9954     };
9955 
9956     union
9957     {
9958         __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
9959 
9960         struct
9961         {
9962             __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
9963             __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
9964             uint32_t            : 27;
9965         } INCTL_b;
9966     };
9967 
9968     union
9969     {
9970         __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
9971 
9972         struct
9973         {
9974             __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
9975             uint32_t              : 2;
9976             __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
9977             __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
9978             __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
9979             uint32_t              : 24;
9980         } TMOCTL_b;
9981     };
9982     __IM uint32_t RESERVED7;
9983 
9984     union
9985     {
9986         __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
9987 
9988         struct
9989         {
9990             __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
9991             uint32_t               : 3;
9992             __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
9993             uint32_t               : 1;
9994             __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
9995             __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
9996             uint32_t               : 24;
9997         } WUCTL_b;
9998     };
9999     __IM uint32_t RESERVED8;
10000 
10001     union
10002     {
10003         __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
10004 
10005         struct
10006         {
10007             __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
10008             __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
10009             __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
10010             uint32_t              : 29;
10011         } ACKCTL_b;
10012     };
10013 
10014     union
10015     {
10016         __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
10017 
10018         struct
10019         {
10020             __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
10021             __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
10022             uint32_t              : 30;
10023         } SCSTRCTL_b;
10024     };
10025     __IM uint32_t RESERVED9[2];
10026 
10027     union
10028     {
10029         __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
10030 
10031         struct
10032         {
10033             __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
10034             uint32_t              : 12;
10035             __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
10036             __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
10037             __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
10038             __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
10039         } SCSTLCTL_b;
10040     };
10041     __IM uint32_t RESERVED10[3];
10042 
10043     union
10044     {
10045         __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
10046 
10047         struct
10048         {
10049             uint32_t             : 16;
10050             __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
10051         } SVTDLG0_b;
10052     };
10053     __IM uint32_t RESERVED11[23];
10054 
10055     union
10056     {
10057         __IOM uint32_t STCTL;          /*!< (@ 0x00000120) Synchronous Timing Control Register                        */
10058 
10059         struct
10060         {
10061             __IOM uint32_t STOE : 1;   /*!< [0..0] Synchronous Timing output Enable                                   */
10062             uint32_t            : 31;
10063         } STCTL_b;
10064     };
10065 
10066     union
10067     {
10068         __IOM uint32_t ATCTL;          /*!< (@ 0x00000124) Asynchronous Timing Control Register                       */
10069 
10070         struct
10071         {
10072             __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select                                 */
10073             __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow)              */
10074             __IOM uint32_t AMEOE  : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable                */
10075             uint32_t              : 5;
10076             __IOM uint32_t CDIV   : 8; /*!< [15..8] TCLK Counter Divide Setting                                       */
10077             uint32_t              : 16;
10078         } ATCTL_b;
10079     };
10080 
10081     union
10082     {
10083         __IOM uint32_t ATTRG;          /*!< (@ 0x00000128) Asynchronous Timing Trigger Register                       */
10084 
10085         struct
10086         {
10087             __OM uint32_t ATSTRG : 1;  /*!< [0..0] Asynchronous Timing Software Trigger                               */
10088             uint32_t             : 31;
10089         } ATTRG_b;
10090     };
10091 
10092     union
10093     {
10094         __IOM uint32_t ATCCNTE;        /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register       */
10095 
10096         struct
10097         {
10098             __IOM uint32_t ATCE : 1;   /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1,
10099                                         *   SC2.                                                                      */
10100             uint32_t : 31;
10101         } ATCCNTE_b;
10102     };
10103     __IM uint32_t RESERVED12[4];
10104 
10105     union
10106     {
10107         __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
10108 
10109         struct
10110         {
10111             __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
10112             __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
10113             __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
10114             uint32_t             : 29;
10115         } CNDCTL_b;
10116     };
10117     __IM uint32_t  RESERVED13[3];
10118     __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
10119     __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
10120     __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
10121     __IM uint32_t  RESERVED14[8];
10122     __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
10123     __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
10124 
10125     union
10126     {
10127         __OM uint32_t HCMDQP;          /*!< (@ 0x00000184) High Priority Command Queue Port Register                  */
10128 
10129         struct
10130         {
10131             __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port                                  */
10132         } HCMDQP_b;
10133     };
10134 
10135     union
10136     {
10137         __IM uint32_t HRSPQP;          /*!< (@ 0x00000188) High Priority Response Queue Port Register                 */
10138 
10139         struct
10140         {
10141             __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port                                 */
10142         } HRSPQP_b;
10143     };
10144 
10145     union
10146     {
10147         __IOM uint32_t HTDTBP;          /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register           */
10148 
10149         struct
10150         {
10151             __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port                           */
10152         } HTDTBP_b;
10153     };
10154 
10155     union
10156     {
10157         __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
10158 
10159         struct
10160         {
10161             __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
10162             __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
10163             __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
10164             __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
10165         } NQTHCTL_b;
10166     };
10167 
10168     union
10169     {
10170         __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
10171                                         *                  Register 0                                                 */
10172 
10173         struct
10174         {
10175             __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
10176             uint32_t              : 5;
10177             __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
10178             uint32_t              : 5;
10179             __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
10180             uint32_t              : 5;
10181             __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
10182             uint32_t              : 5;
10183         } NTBTHCTL0_b;
10184     };
10185     __IM uint32_t RESERVED15[10];
10186 
10187     union
10188     {
10189         __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
10190                                         *                  Register                                                   */
10191 
10192         struct
10193         {
10194             __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
10195             uint32_t             : 24;
10196         } NRQTHCTL_b;
10197     };
10198 
10199     union
10200     {
10201         __IOM uint32_t HQTHCTL;        /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register             */
10202 
10203         struct
10204         {
10205             __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold                              */
10206             __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold                            */
10207             uint32_t              : 16;
10208         } HQTHCTL_b;
10209     };
10210 
10211     union
10212     {
10213         __IOM uint32_t HTBTHCTL;       /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold
10214                                         *                  Control Register                                           */
10215 
10216         struct
10217         {
10218             __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold                             */
10219             uint32_t              : 5;
10220             __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold                            */
10221             uint32_t              : 5;
10222             __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold                                 */
10223             uint32_t              : 5;
10224             __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold                                 */
10225             uint32_t              : 5;
10226         } HTBTHCTL_b;
10227     };
10228     __IM uint32_t RESERVED16;
10229 
10230     union
10231     {
10232         __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
10233 
10234         struct
10235         {
10236             __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
10237             __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
10238             __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
10239             uint32_t               : 1;
10240             __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
10241             uint32_t               : 3;
10242             __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
10243             uint32_t               : 7;
10244             __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
10245             uint32_t               : 3;
10246             __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
10247             uint32_t               : 3;
10248             __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag                                 */
10249             uint32_t               : 7;
10250         } BST_b;
10251     };
10252 
10253     union
10254     {
10255         __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
10256 
10257         struct
10258         {
10259             __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
10260             __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
10261             __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
10262             uint32_t               : 1;
10263             __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
10264             uint32_t               : 3;
10265             __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
10266             uint32_t               : 7;
10267             __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
10268             uint32_t               : 3;
10269             __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
10270             uint32_t               : 3;
10271             __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable                               */
10272             uint32_t               : 7;
10273         } BSTE_b;
10274     };
10275 
10276     union
10277     {
10278         __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
10279 
10280         struct
10281         {
10282             __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
10283             __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
10284             __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
10285             uint32_t                : 1;
10286             __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
10287             uint32_t                : 3;
10288             __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
10289             uint32_t                : 7;
10290             __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
10291             uint32_t                : 3;
10292             __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
10293             uint32_t                : 3;
10294             __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable                     */
10295             uint32_t                : 7;
10296         } BIE_b;
10297     };
10298 
10299     union
10300     {
10301         __IOM uint32_t BSTFC;            /*!< (@ 0x000001DC) Bus Status Force Register                                  */
10302 
10303         struct
10304         {
10305             __OM uint32_t STCNDDFC  : 1; /*!< [0..0] START condition Detection Force                                    */
10306             __OM uint32_t SPCNDDFC  : 1; /*!< [1..1] STOP condition Detection Force                                     */
10307             __OM uint32_t HDREXDFC  : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
10308             uint32_t                : 1;
10309             __OM uint32_t NACKDFC   : 1; /*!< [4..4] NACK Detection Force                                               */
10310             uint32_t                : 3;
10311             __OM uint32_t TENDFC    : 1; /*!< [8..8] Transmit End Force                                                 */
10312             uint32_t                : 7;
10313             __OM uint32_t ALFC      : 1; /*!< [16..16] Arbitration Lost Force                                           */
10314             uint32_t                : 3;
10315             __OM uint32_t TODFC     : 1; /*!< [20..20] Timeout Detection Force                                          */
10316             uint32_t                : 3;
10317             __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force                                */
10318             uint32_t                : 7;
10319         } BSTFC_b;
10320     };
10321 
10322     union
10323     {
10324         __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
10325 
10326         struct
10327         {
10328             __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
10329             __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
10330             __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
10331             __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
10332             __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
10333             __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
10334             uint32_t               : 3;
10335             __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
10336             uint32_t               : 10;
10337             __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
10338             uint32_t               : 11;
10339         } NTST_b;
10340     };
10341 
10342     union
10343     {
10344         __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
10345 
10346         struct
10347         {
10348             __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
10349             __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
10350             __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
10351             __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
10352             __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
10353             __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
10354             uint32_t               : 3;
10355             __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
10356             uint32_t               : 10;
10357             __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
10358             uint32_t               : 11;
10359         } NTSTE_b;
10360     };
10361 
10362     union
10363     {
10364         __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
10365 
10366         struct
10367         {
10368             __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
10369             __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
10370             __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
10371             __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
10372             __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
10373             __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
10374             uint32_t                : 3;
10375             __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
10376             uint32_t                : 10;
10377             __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
10378             uint32_t                : 11;
10379         } NTIE_b;
10380     };
10381 
10382     union
10383     {
10384         __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
10385 
10386         struct
10387         {
10388             __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
10389             __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
10390             __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
10391             __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
10392             __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
10393             __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
10394             uint32_t               : 3;
10395             __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
10396             uint32_t               : 10;
10397             __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
10398             uint32_t               : 11;
10399         } NTSTFC_b;
10400     };
10401     __IM uint32_t RESERVED17[4];
10402 
10403     union
10404     {
10405         __IOM uint32_t HTST;           /*!< (@ 0x00000200) High Priority Transfer Status Register                     */
10406 
10407         struct
10408         {
10409             __IOM uint32_t TDBEF  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag                            */
10410             __IOM uint32_t RDBFF  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag                             */
10411             uint32_t              : 1;
10412             __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag                             */
10413             __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag                             */
10414             __IOM uint32_t TABTF  : 1; /*!< [5..5] High Priority Transfer Abort Flag                                  */
10415             uint32_t              : 3;
10416             __IOM uint32_t TEF    : 1; /*!< [9..9] High Priority Transfer Error Flag                                  */
10417             uint32_t              : 22;
10418         } HTST_b;
10419     };
10420 
10421     union
10422     {
10423         __IOM uint32_t HTSTE;          /*!< (@ 0x00000204) High Priority Transfer Status Enable Register              */
10424 
10425         struct
10426         {
10427             __IOM uint32_t TDBEE  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable                          */
10428             __IOM uint32_t RDBFE  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable                           */
10429             uint32_t              : 1;
10430             __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable                           */
10431             __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable                           */
10432             __IOM uint32_t TABTE  : 1; /*!< [5..5] High Priority Transfer Abort Enable                                */
10433             uint32_t              : 3;
10434             __IOM uint32_t TEE    : 1; /*!< [9..9] High Priority Transfer Error Enable                                */
10435             uint32_t              : 22;
10436         } HTSTE_b;
10437     };
10438 
10439     union
10440     {
10441         __IOM uint32_t HTIE;            /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register           */
10442 
10443         struct
10444         {
10445             __IOM uint32_t TDBEIE  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable                */
10446             __IOM uint32_t RDBFIE  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable                 */
10447             uint32_t               : 1;
10448             __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable                 */
10449             __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable                 */
10450             __IOM uint32_t TABTIE  : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable                      */
10451             uint32_t               : 3;
10452             __IOM uint32_t TEIE    : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable                      */
10453             uint32_t               : 22;
10454         } HTIE_b;
10455     };
10456 
10457     union
10458     {
10459         __IOM uint32_t HTSTFC;         /*!< (@ 0x0000020C) High Priority Transfer Status Force Register               */
10460 
10461         struct
10462         {
10463             __OM uint32_t TDBEFC  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force                           */
10464             __OM uint32_t RDBFFC  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force                            */
10465             uint32_t              : 1;
10466             __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force                            */
10467             __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force                            */
10468             __OM uint32_t TABTFC  : 1; /*!< [5..5] High Priority Transfer Abort Force                                 */
10469             uint32_t              : 3;
10470             __OM uint32_t TEFC    : 1; /*!< [9..9] High Priority Transfer Error Force                                 */
10471             uint32_t              : 22;
10472         } HTSTFC_b;
10473     };
10474 
10475     union
10476     {
10477         __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
10478 
10479         struct
10480         {
10481             __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
10482             __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
10483             __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
10484             uint32_t            : 29;
10485         } BCST_b;
10486     };
10487 
10488     union
10489     {
10490         __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
10491 
10492         struct
10493         {
10494             __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
10495             uint32_t             : 4;
10496             __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
10497             __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
10498             uint32_t             : 8;
10499             __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
10500             __IOM uint32_t SVAFn : 3;  /*!< [18..16] Slave Address Detection Flag                                     */
10501             uint32_t             : 13;
10502         } SVST_b;
10503     };
10504 
10505     union
10506     {
10507         __IM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Operating Status Register                     */
10508 
10509         struct
10510         {
10511             __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
10512             uint32_t              : 31;
10513         } WUST_b;
10514     };
10515 
10516     union
10517     {
10518         __IM uint32_t MRCCPT;          /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register                          */
10519 
10520         struct
10521         {
10522             __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture                                          */
10523         } MRCCPT_b;
10524     };
10525     __IM uint32_t RESERVED18;
10526 
10527     union
10528     {
10529         __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
10530 
10531         struct
10532         {
10533             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10534             uint32_t               : 5;
10535             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10536             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10537             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10538             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10539             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10540             uint32_t               : 5;
10541             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10542             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10543         } DATBAS0_b;
10544     };
10545     __IM uint32_t RESERVED19;
10546 
10547     union
10548     {
10549         __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
10550 
10551         struct
10552         {
10553             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10554             uint32_t               : 5;
10555             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10556             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10557             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10558             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10559             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10560             uint32_t               : 5;
10561             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10562             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10563         } DATBAS1_b;
10564     };
10565     __IM uint32_t RESERVED20;
10566 
10567     union
10568     {
10569         __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
10570 
10571         struct
10572         {
10573             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10574             uint32_t               : 5;
10575             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10576             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10577             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10578             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10579             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10580             uint32_t               : 5;
10581             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10582             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10583         } DATBAS2_b;
10584     };
10585     __IM uint32_t RESERVED21;
10586 
10587     union
10588     {
10589         __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
10590 
10591         struct
10592         {
10593             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10594             uint32_t               : 5;
10595             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10596             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10597             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10598             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10599             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10600             uint32_t               : 5;
10601             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10602             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10603         } DATBAS3_b;
10604     };
10605     __IM uint32_t RESERVED22;
10606 
10607     union
10608     {
10609         __IOM uint32_t DATBAS4;         /*!< (@ 0x00000244) Device Address Table Basic Register 4                      */
10610 
10611         struct
10612         {
10613             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10614             uint32_t               : 5;
10615             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10616             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10617             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10618             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10619             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10620             uint32_t               : 5;
10621             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10622             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10623         } DATBAS4_b;
10624     };
10625     __IM uint32_t RESERVED23;
10626 
10627     union
10628     {
10629         __IOM uint32_t DATBAS5;         /*!< (@ 0x0000024C) Device Address Table Basic Register 5                      */
10630 
10631         struct
10632         {
10633             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10634             uint32_t               : 5;
10635             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10636             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10637             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10638             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10639             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10640             uint32_t               : 5;
10641             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10642             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10643         } DATBAS5_b;
10644     };
10645     __IM uint32_t RESERVED24;
10646 
10647     union
10648     {
10649         __IOM uint32_t DATBAS6;         /*!< (@ 0x00000254) Device Address Table Basic Register 6                      */
10650 
10651         struct
10652         {
10653             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10654             uint32_t               : 5;
10655             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10656             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10657             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10658             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10659             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10660             uint32_t               : 5;
10661             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10662             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10663         } DATBAS6_b;
10664     };
10665     __IM uint32_t RESERVED25;
10666 
10667     union
10668     {
10669         __IOM uint32_t DATBAS7;         /*!< (@ 0x0000025C) Device Address Table Basic Register 7                      */
10670 
10671         struct
10672         {
10673             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10674             uint32_t               : 5;
10675             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10676             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10677             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10678             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10679             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10680             uint32_t               : 5;
10681             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10682             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10683         } DATBAS7_b;
10684     };
10685     __IM uint32_t RESERVED26[16];
10686 
10687     union
10688     {
10689         __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
10690 
10691         struct
10692         {
10693             __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
10694             uint32_t              : 9;
10695             __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
10696             uint32_t              : 5;
10697             __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
10698             __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
10699         } EXDATBAS_b;
10700     };
10701     __IM uint32_t RESERVED27[3];
10702 
10703     union
10704     {
10705         __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
10706 
10707         struct
10708         {
10709             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10710             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10711             uint32_t               : 1;
10712             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10713             uint32_t               : 3;
10714             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10715             uint32_t               : 9;
10716         } SDATBAS0_b;
10717     };
10718 
10719     union
10720     {
10721         __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
10722 
10723         struct
10724         {
10725             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10726             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10727             uint32_t               : 1;
10728             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10729             uint32_t               : 3;
10730             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10731             uint32_t               : 9;
10732         } SDATBAS1_b;
10733     };
10734 
10735     union
10736     {
10737         __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
10738 
10739         struct
10740         {
10741             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10742             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10743             uint32_t               : 1;
10744             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10745             uint32_t               : 3;
10746             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10747             uint32_t               : 9;
10748         } SDATBAS2_b;
10749     };
10750     __IM uint32_t RESERVED28[5];
10751 
10752     union
10753     {
10754         __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
10755 
10756         struct
10757         {
10758             uint32_t              : 8;
10759             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10760             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10761             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10762             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10763             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10764             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10765             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10766             uint32_t              : 16;
10767         } MSDCT0_b;
10768     };
10769 
10770     union
10771     {
10772         __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
10773 
10774         struct
10775         {
10776             uint32_t              : 8;
10777             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10778             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10779             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10780             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10781             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10782             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10783             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10784             uint32_t              : 16;
10785         } MSDCT1_b;
10786     };
10787 
10788     union
10789     {
10790         __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
10791 
10792         struct
10793         {
10794             uint32_t              : 8;
10795             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10796             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10797             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10798             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10799             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10800             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10801             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10802             uint32_t              : 16;
10803         } MSDCT2_b;
10804     };
10805 
10806     union
10807     {
10808         __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
10809 
10810         struct
10811         {
10812             uint32_t              : 8;
10813             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10814             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10815             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10816             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10817             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10818             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10819             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10820             uint32_t              : 16;
10821         } MSDCT3_b;
10822     };
10823 
10824     union
10825     {
10826         __IOM uint32_t MSDCT4;         /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4              */
10827 
10828         struct
10829         {
10830             uint32_t              : 8;
10831             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10832             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10833             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10834             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10835             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10836             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10837             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10838             uint32_t              : 16;
10839         } MSDCT4_b;
10840     };
10841 
10842     union
10843     {
10844         __IOM uint32_t MSDCT5;         /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5              */
10845 
10846         struct
10847         {
10848             uint32_t              : 8;
10849             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10850             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10851             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10852             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10853             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10854             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10855             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10856             uint32_t              : 16;
10857         } MSDCT5_b;
10858     };
10859 
10860     union
10861     {
10862         __IOM uint32_t MSDCT6;         /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6              */
10863 
10864         struct
10865         {
10866             uint32_t              : 8;
10867             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10868             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10869             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10870             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10871             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10872             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10873             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10874             uint32_t              : 16;
10875         } MSDCT6_b;
10876     };
10877 
10878     union
10879     {
10880         __IOM uint32_t MSDCT7;         /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7              */
10881 
10882         struct
10883         {
10884             uint32_t              : 8;
10885             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10886             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10887             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10888             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10889             __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10890             __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10891             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10892             uint32_t              : 16;
10893         } MSDCT7_b;
10894     };
10895     __IM uint32_t RESERVED29[12];
10896 
10897     union
10898     {
10899         __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
10900 
10901         struct
10902         {
10903             __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
10904             __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10905             __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10906             __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10907             __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10908             __IOM uint32_t TBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
10909             __IOM uint32_t TBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
10910             __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
10911             uint32_t              : 16;
10912         } SVDCT_b;
10913     };
10914     __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
10915                                         *                  ID Low Register                                            */
10916     __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
10917                                         *                  ID High Register                                           */
10918     __IM uint32_t RESERVED30;
10919 
10920     union
10921     {
10922         __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
10923 
10924         struct
10925         {
10926             uint32_t             : 16;
10927             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
10928             uint32_t             : 1;
10929             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
10930             uint32_t             : 2;
10931             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
10932             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
10933         } SVDVAD0_b;
10934     };
10935 
10936     union
10937     {
10938         __IM uint32_t SVDVAD1;         /*!< (@ 0x00000334) Slave Device Address Register 1                            */
10939 
10940         struct
10941         {
10942             uint32_t             : 16;
10943             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
10944             uint32_t             : 1;
10945             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
10946             uint32_t             : 2;
10947             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
10948             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
10949         } SVDVAD1_b;
10950     };
10951 
10952     union
10953     {
10954         __IM uint32_t SVDVAD2;         /*!< (@ 0x00000338) Slave Device Address Register 2                            */
10955 
10956         struct
10957         {
10958             uint32_t             : 16;
10959             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
10960             uint32_t             : 1;
10961             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
10962             uint32_t             : 2;
10963             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
10964             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
10965         } SVDVAD2_b;
10966     };
10967     __IM uint32_t RESERVED31[5];
10968 
10969     union
10970     {
10971         __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
10972 
10973         struct
10974         {
10975             __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
10976             __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
10977             uint32_t              : 1;
10978             __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
10979             uint32_t              : 28;
10980         } CSECMD_b;
10981     };
10982 
10983     union
10984     {
10985         __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
10986 
10987         struct
10988         {
10989             __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
10990             uint32_t             : 28;
10991         } CEACTST_b;
10992     };
10993 
10994     union
10995     {
10996         __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
10997 
10998         struct
10999         {
11000             __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
11001             uint32_t            : 16;
11002         } CMWLG_b;
11003     };
11004 
11005     union
11006     {
11007         __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
11008 
11009         struct
11010         {
11011             __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
11012             __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
11013             uint32_t              : 8;
11014         } CMRLG_b;
11015     };
11016 
11017     union
11018     {
11019         __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
11020 
11021         struct
11022         {
11023             __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
11024             uint32_t            : 24;
11025         } CETSTMD_b;
11026     };
11027 
11028     union
11029     {
11030         __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
11031 
11032         struct
11033         {
11034             __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
11035             uint32_t              : 1;
11036             __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
11037             __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
11038             __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
11039             uint32_t              : 16;
11040         } CGDVST_b;
11041     };
11042 
11043     union
11044     {
11045         __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
11046 
11047         struct
11048         {
11049             __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
11050             uint32_t             : 29;
11051         } CMDSPW_b;
11052     };
11053 
11054     union
11055     {
11056         __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
11057 
11058         struct
11059         {
11060             __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
11061             __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
11062             uint32_t              : 26;
11063         } CMDSPR_b;
11064     };
11065 
11066     union
11067     {
11068         __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
11069 
11070         struct
11071         {
11072             __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
11073             uint32_t              : 7;
11074             __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
11075         } CMDSPT_b;
11076     };
11077 
11078     union
11079     {
11080         __IOM uint32_t CETSM;            /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
11081                                           *                  Register                                                   */
11082 
11083         struct
11084         {
11085             __IOM uint32_t SPTSYN   : 1; /*!< [0..0] Supports Sync Mode                                                 */
11086             __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0                                               */
11087             __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1                                               */
11088             uint32_t                : 5;
11089             __IOM uint32_t FREQ     : 8; /*!< [15..8] Frequency Byte                                                    */
11090             __IOM uint32_t INAC     : 8; /*!< [23..16] Inaccuracy Byte                                                  */
11091             uint32_t                : 8;
11092         } CETSM_b;
11093     };
11094 
11095     union
11096     {
11097         __IOM uint32_t CETSS;          /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State)
11098                                         *                  Register                                                   */
11099 
11100         struct
11101         {
11102             __IOM uint32_t SYNE  : 1;  /*!< [0..0] Sync Mode Enabled                                                  */
11103             __IOM uint32_t ASYNE : 2;  /*!< [2..1] Async Mode Enabled                                                 */
11104             uint32_t             : 4;
11105             __IOM uint32_t ICOVF : 1;  /*!< [7..7] Internal Counter Overflow                                          */
11106             uint32_t             : 24;
11107         } CETSS_b;
11108     };
11109 
11110     union
11111     {
11112         __IOM uint32_t CGHDRCAP;       /*!< (@ 0x0000037C) CCC Get HDR Capability Register                            */
11113 
11114         struct
11115         {
11116             __IOM uint32_t DDREN : 1;  /*!< [0..0] HDR-DDR Operation Enable                                           */
11117             __IOM uint32_t TSPEN : 1;  /*!< [1..1] HDR-TSP Operation Enable                                           */
11118             __IOM uint32_t TSLEN : 1;  /*!< [2..2] HDR-TSL Operation Enable                                           */
11119             uint32_t             : 29;
11120         } CGHDRCAP_b;
11121     };
11122 
11123     union
11124     {
11125         __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
11126 
11127         struct
11128         {
11129             __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
11130             uint32_t             : 2;
11131             __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
11132             uint32_t             : 24;
11133         } BITCNT_b;
11134     };
11135     __IM uint32_t RESERVED32[4];
11136 
11137     union
11138     {
11139         __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
11140 
11141         struct
11142         {
11143             __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
11144             __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
11145             __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
11146             __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
11147             uint32_t              : 3;
11148         } NQSTLV_b;
11149     };
11150 
11151     union
11152     {
11153         __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0                 */
11154 
11155         struct
11156         {
11157             __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
11158             __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
11159             uint32_t             : 16;
11160         } NDBSTLV0_b;
11161     };
11162     __IM uint32_t RESERVED33[9];
11163 
11164     union
11165     {
11166         __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
11167 
11168         struct
11169         {
11170             __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
11171             uint32_t            : 24;
11172         } NRSQSTLV_b;
11173     };
11174 
11175     union
11176     {
11177         __IM uint32_t HQSTLV;          /*!< (@ 0x000003C4) High Priority Queue Status Level Register                  */
11178 
11179         struct
11180         {
11181             __IM uint32_t CMDQLV : 8;  /*!< [7..0] High Priority Command Queue Level                                  */
11182             __IM uint32_t RSPQLV : 8;  /*!< [15..8] High Priority Response Queue Level                                */
11183             uint32_t             : 16;
11184         } HQSTLV_b;
11185     };
11186 
11187     union
11188     {
11189         __IM uint32_t HDBSTLV;         /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register            */
11190 
11191         struct
11192         {
11193             __IM uint32_t TDBFLV : 8;  /*!< [7..0] High Priority Tx Data Buffer Free Level                            */
11194             __IM uint32_t RDBLV  : 8;  /*!< [15..8] High Priority Rx Data Buffer Level                                */
11195             uint32_t             : 16;
11196         } HDBSTLV_b;
11197     };
11198 
11199     union
11200     {
11201         __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
11202 
11203         struct
11204         {
11205             __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
11206             __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
11207             __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
11208             __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
11209             uint32_t            : 28;
11210         } PRSTDBG_b;
11211     };
11212 
11213     union
11214     {
11215         __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
11216 
11217         struct
11218         {
11219             __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
11220             uint32_t             : 24;
11221         } MSERRCNT_b;
11222     };
11223     __IM uint32_t RESERVED34[3];
11224 
11225     union
11226     {
11227         __IM uint32_t SC1CPT;          /*!< (@ 0x000003E0) SC1 Capture monitor Register                               */
11228 
11229         struct
11230         {
11231             __IM uint32_t SC1C : 16;   /*!< [15..0] SC1 Capture                                                       */
11232             uint32_t           : 16;
11233         } SC1CPT_b;
11234     };
11235 
11236     union
11237     {
11238         __IM uint32_t SC2CPT;          /*!< (@ 0x000003E4) SC2 Capture monitor Register                               */
11239 
11240         struct
11241         {
11242             __IM uint32_t SC2C : 16;   /*!< [15..0] SC2 Capture                                                       */
11243             uint32_t           : 16;
11244         } SC2CPT_b;
11245     };
11246 } R_I3C0_Type;                         /*!< Size = 1000 (0x3e8)                                                       */
11247 
11248 /* =========================================================================================================================== */
11249 /* ================                                        R_MPU_MMPU                                         ================ */
11250 /* =========================================================================================================================== */
11251 
11252 /**
11253  * @brief Bus Master MPU (R_MPU_MMPU)
11254  */
11255 
11256 typedef struct                         /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
11257 {
11258     union
11259     {
11260         __IOM uint16_t OAD;            /*!< (@ 0x00000000) MMPU Operation After Detection Register                    */
11261 
11262         struct
11263         {
11264             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
11265             uint16_t           : 7;
11266             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
11267                                         *   stored.                                                                   */
11268         } OAD_b;
11269     };
11270     __IM uint16_t RESERVED;
11271 
11272     union
11273     {
11274         __IOM uint16_t OADPT;           /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register            */
11275 
11276         struct
11277         {
11278             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
11279             uint16_t               : 7;
11280             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
11281                                          *   stored.                                                                   */
11282         } OADPT_b;
11283     };
11284     __IM uint16_t               RESERVED1;
11285     __IM uint32_t               RESERVED2[62];
11286     __IOM R_MPU_MMPU_GROUP_Type DMAC0;    /*!< (@ 0x00000100) DMAC0 MMPU Registers                                       */
11287     __IOM R_MPU_MMPU_GROUP_Type DMAC1;    /*!< (@ 0x00000300) DMAC1 MMPU Registers                                       */
11288     __IOM R_MPU_MMPU_GROUP_Type EDMAC;    /*!< (@ 0x00000500) EDMAC MMPU Registers                                       */
11289     __IOM R_MPU_MMPU_GROUP_Type GLCDC;    /*!< (@ 0x00000700) GLCDC MMPU Registers                                       */
11290     __IOM R_MPU_MMPU_GROUP_Type DRW;      /*!< (@ 0x00000900) DRW MMPU Registers                                         */
11291     __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers                                    */
11292     __IOM R_MPU_MMPU_GROUP_Type CEU;      /*!< (@ 0x00000D00) CEU MMPU Registers                                         */
11293 } R_MPU_MMPU_Type;                        /*!< Size = 3840 (0xf00)                                                       */
11294 
11295 /* =========================================================================================================================== */
11296 /* ================                                        R_MPU_SPMON                                        ================ */
11297 /* =========================================================================================================================== */
11298 
11299 /**
11300  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
11301  */
11302 
11303 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
11304 {
11305     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
11306 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
11307 
11308 /* =========================================================================================================================== */
11309 /* ================                                          R_MSTP                                           ================ */
11310 /* =========================================================================================================================== */
11311 
11312 /**
11313  * @brief System-Module Stop (R_MSTP)
11314  */
11315 
11316 typedef struct                          /*!< (@ 0x40084000) R_MSTP Structure                                           */
11317 {
11318     union
11319     {
11320         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
11321 
11322         struct
11323         {
11324             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
11325             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
11326             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
11327             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
11328             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
11329             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
11330             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
11331             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
11332             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
11333             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
11334             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
11335                                          *   usage.                                                                    */
11336             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
11337                                          *   usage.                                                                    */
11338             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
11339                                          *   usage.                                                                    */
11340             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
11341                                          *   usage.                                                                    */
11342             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
11343                                          *   usage.                                                                    */
11344             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
11345                                          *   usage.                                                                    */
11346             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
11347                                          *   usage.                                                                    */
11348             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
11349                                          *   usage.                                                                    */
11350             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
11351                                          *   usage.                                                                    */
11352             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
11353                                          *   usage.                                                                    */
11354             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
11355                                          *   usage.                                                                    */
11356             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
11357                                          *   usage.                                                                    */
11358             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
11359                                          *   usage.                                                                    */
11360             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
11361                                          *   usage.                                                                    */
11362             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
11363                                          *   usage.                                                                    */
11364             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
11365                                          *   usage.                                                                    */
11366             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
11367                                          *   usage.                                                                    */
11368             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
11369                                          *   usage.                                                                    */
11370             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
11371                                          *   usage.                                                                    */
11372             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
11373                                          *   usage.                                                                    */
11374             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
11375                                          *   usage.                                                                    */
11376             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
11377                                          *   usage.                                                                    */
11378         } MSTPCRA_b;
11379     };
11380 
11381     union
11382     {
11383         __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */
11384 
11385         struct
11386         {
11387             __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
11388             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
11389             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
11390             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
11391             __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
11392             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
11393             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
11394             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
11395             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
11396             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
11397             __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
11398                                          *   usage.                                                                    */
11399             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
11400                                          *   usage.                                                                    */
11401             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
11402                                          *   usage.                                                                    */
11403             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
11404                                          *   usage.                                                                    */
11405             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
11406                                          *   usage.                                                                    */
11407             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
11408                                          *   usage.                                                                    */
11409             __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
11410                                          *   usage.                                                                    */
11411             __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
11412                                          *   usage.                                                                    */
11413             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
11414                                          *   usage.                                                                    */
11415             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
11416                                          *   usage.                                                                    */
11417             __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
11418                                          *   usage.                                                                    */
11419             __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
11420                                          *   usage.                                                                    */
11421             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
11422                                          *   usage.                                                                    */
11423             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
11424                                          *   usage.                                                                    */
11425             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
11426                                          *   usage.                                                                    */
11427             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
11428                                          *   usage.                                                                    */
11429             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
11430                                          *   usage.                                                                    */
11431             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
11432                                          *   usage.                                                                    */
11433             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
11434                                          *   usage.                                                                    */
11435             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
11436                                          *   usage.                                                                    */
11437             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
11438                                          *   usage.                                                                    */
11439             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
11440                                          *   usage.                                                                    */
11441         } MSTPCRB_b;
11442     };
11443 
11444     union
11445     {
11446         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
11447 
11448         struct
11449         {
11450             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
11451             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
11452             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
11453             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
11454             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
11455             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
11456             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
11457             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
11458             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
11459             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
11460             __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
11461                                          *   usage.                                                                    */
11462             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
11463                                          *   usage.                                                                    */
11464             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
11465                                          *   usage.                                                                    */
11466             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
11467                                          *   usage.                                                                    */
11468             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
11469                                          *   usage.                                                                    */
11470             __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
11471                                          *   usage.                                                                    */
11472             __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
11473                                          *   usage.                                                                    */
11474             __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
11475                                          *   usage.                                                                    */
11476             __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
11477                                          *   usage.                                                                    */
11478             __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
11479                                          *   usage.                                                                    */
11480             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
11481                                          *   usage.                                                                    */
11482             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
11483                                          *   usage.                                                                    */
11484             __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
11485                                          *   usage.                                                                    */
11486             __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
11487                                          *   usage.                                                                    */
11488             __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
11489                                          *   usage.                                                                    */
11490             __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
11491                                          *   usage.                                                                    */
11492             __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
11493                                          *   usage.                                                                    */
11494             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
11495                                          *   usage.                                                                    */
11496             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
11497                                          *   usage.                                                                    */
11498             __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
11499                                          *   usage.                                                                    */
11500             __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
11501                                          *   usage.                                                                    */
11502             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
11503                                          *   usage.                                                                    */
11504         } MSTPCRC_b;
11505     };
11506 
11507     union
11508     {
11509         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
11510 
11511         struct
11512         {
11513             __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
11514             __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
11515             __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
11516             __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
11517             __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
11518             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
11519             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
11520             __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
11521             __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
11522             __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
11523             __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
11524                                          *   usage.                                                                    */
11525             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
11526                                          *   usage.                                                                    */
11527             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
11528                                          *   usage.                                                                    */
11529             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
11530                                          *   usage.                                                                    */
11531             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
11532                                          *   usage.                                                                    */
11533             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
11534                                          *   usage.                                                                    */
11535             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
11536                                          *   usage.                                                                    */
11537             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
11538                                          *   usage.                                                                    */
11539             __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
11540                                          *   usage.                                                                    */
11541             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
11542                                          *   usage.                                                                    */
11543             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
11544                                          *   usage.                                                                    */
11545             __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
11546                                          *   usage.                                                                    */
11547             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
11548                                          *   usage.                                                                    */
11549             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
11550                                          *   usage.                                                                    */
11551             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
11552                                          *   usage.                                                                    */
11553             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
11554                                          *   usage.                                                                    */
11555             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
11556                                          *   usage.                                                                    */
11557             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
11558                                          *   usage.                                                                    */
11559             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
11560                                          *   usage.                                                                    */
11561             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
11562                                          *   usage.                                                                    */
11563             __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
11564                                          *   usage.                                                                    */
11565             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
11566                                          *   usage.                                                                    */
11567         } MSTPCRD_b;
11568     };
11569 
11570     union
11571     {
11572         union
11573         {
11574             __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */
11575 
11576             struct
11577             {
11578                 __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
11579                 __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
11580                 __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
11581                 __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
11582                 __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
11583                 __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
11584                 __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
11585                 __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
11586                 __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
11587                 __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
11588                 __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
11589                                              *   usage.                                                                    */
11590                 __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
11591                                              *   usage.                                                                    */
11592                 __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
11593                                              *   usage.                                                                    */
11594                 __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
11595                                              *   usage.                                                                    */
11596                 __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
11597                                              *   usage.                                                                    */
11598                 __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
11599                                              *   usage.                                                                    */
11600                 __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
11601                                              *   usage.                                                                    */
11602                 __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
11603                                              *   usage.                                                                    */
11604                 __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
11605                                              *   usage.                                                                    */
11606                 __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
11607                                              *   usage.                                                                    */
11608                 __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
11609                                              *   usage.                                                                    */
11610                 __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
11611                                              *   usage.                                                                    */
11612                 __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
11613                                              *   usage.                                                                    */
11614                 __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
11615                                              *   usage.                                                                    */
11616                 __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
11617                                              *   usage.                                                                    */
11618                 __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
11619                                              *   usage.                                                                    */
11620                 __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
11621                                              *   usage.                                                                    */
11622                 __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
11623                                              *   usage.                                                                    */
11624                 __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
11625                                              *   usage.                                                                    */
11626                 __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
11627                                              *   usage.                                                                    */
11628                 __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
11629                                              *   usage.                                                                    */
11630                 __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
11631                                              *   usage.                                                                    */
11632             } MSTPCRE_b;
11633         };
11634 
11635         union
11636         {
11637             __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */
11638 
11639             struct
11640             {
11641                 __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
11642                 __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
11643                 __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
11644                 uint16_t                : 4;
11645                 __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
11646                 __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
11647             } LSMRWDIS_b;
11648         };
11649     };
11650 } R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */
11651 
11652 /* =========================================================================================================================== */
11653 /* ================                                          R_PORT0                                          ================ */
11654 /* =========================================================================================================================== */
11655 
11656 /**
11657  * @brief I/O Ports (R_PORT0)
11658  */
11659 
11660 typedef struct                         /*!< (@ 0x4001F000) R_PORT0 Structure                                          */
11661 {
11662     union
11663     {
11664         union
11665         {
11666             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
11667 
11668             struct
11669             {
11670                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
11671                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
11672             } PCNTR1_b;
11673         };
11674 
11675         struct
11676         {
11677             union
11678             {
11679                 __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
11680 
11681                 struct
11682                 {
11683                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
11684                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
11685                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
11686                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
11687                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
11688                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
11689                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
11690                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
11691                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
11692                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
11693                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
11694                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
11695                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
11696                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
11697                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
11698                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
11699                 } PODR_b;
11700             };
11701 
11702             union
11703             {
11704                 __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
11705 
11706                 struct
11707                 {
11708                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
11709                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
11710                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
11711                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
11712                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
11713                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
11714                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
11715                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
11716                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
11717                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
11718                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
11719                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
11720                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
11721                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
11722                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
11723                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
11724                 } PDR_b;
11725             };
11726         };
11727     };
11728 
11729     union
11730     {
11731         union
11732         {
11733             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
11734 
11735             struct
11736             {
11737                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
11738                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
11739             } PCNTR2_b;
11740         };
11741 
11742         struct
11743         {
11744             union
11745             {
11746                 __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
11747 
11748                 struct
11749                 {
11750                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
11751                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
11752                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
11753                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
11754                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
11755                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
11756                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
11757                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
11758                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
11759                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
11760                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
11761                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
11762                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
11763                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
11764                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
11765                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
11766                 } EIDR_b;
11767             };
11768 
11769             union
11770             {
11771                 __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
11772 
11773                 struct
11774                 {
11775                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
11776                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
11777                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
11778                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
11779                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
11780                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
11781                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
11782                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
11783                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
11784                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
11785                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
11786                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
11787                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
11788                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
11789                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
11790                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
11791                 } PIDR_b;
11792             };
11793         };
11794     };
11795 
11796     union
11797     {
11798         union
11799         {
11800             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
11801 
11802             struct
11803             {
11804                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
11805                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
11806             } PCNTR3_b;
11807         };
11808 
11809         struct
11810         {
11811             union
11812             {
11813                 __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
11814 
11815                 struct
11816                 {
11817                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
11818                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
11819                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
11820                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
11821                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
11822                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
11823                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
11824                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
11825                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
11826                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
11827                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
11828                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
11829                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
11830                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
11831                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
11832                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
11833                 } PORR_b;
11834             };
11835 
11836             union
11837             {
11838                 __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
11839 
11840                 struct
11841                 {
11842                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
11843                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
11844                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
11845                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
11846                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
11847                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
11848                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
11849                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
11850                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
11851                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
11852                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
11853                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
11854                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
11855                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
11856                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
11857                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
11858                 } POSR_b;
11859             };
11860         };
11861     };
11862 
11863     union
11864     {
11865         union
11866         {
11867             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
11868 
11869             struct
11870             {
11871                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
11872                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
11873             } PCNTR4_b;
11874         };
11875 
11876         struct
11877         {
11878             union
11879             {
11880                 __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
11881 
11882                 struct
11883                 {
11884                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
11885                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
11886                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
11887                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
11888                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
11889                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
11890                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
11891                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
11892                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
11893                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
11894                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
11895                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
11896                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
11897                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
11898                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
11899                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
11900                 } EORR_b;
11901             };
11902 
11903             union
11904             {
11905                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
11906 
11907                 struct
11908                 {
11909                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
11910                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
11911                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
11912                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
11913                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
11914                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
11915                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
11916                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
11917                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
11918                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
11919                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
11920                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
11921                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
11922                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
11923                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
11924                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
11925                 } EOSR_b;
11926             };
11927         };
11928     };
11929 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
11930 
11931 /* =========================================================================================================================== */
11932 /* ================                                           R_PFS                                           ================ */
11933 /* =========================================================================================================================== */
11934 
11935 /**
11936  * @brief I/O Ports-PFS (R_PFS)
11937  */
11938 
11939 typedef struct                           /*!< (@ 0x4001F800) R_PFS Structure                                            */
11940 {
11941     union
11942     {
11943         __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
11944         __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
11945     };
11946 } R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
11947 
11948 /* =========================================================================================================================== */
11949 /* ================                                          R_PMISC                                          ================ */
11950 /* =========================================================================================================================== */
11951 
11952 /**
11953  * @brief I/O Ports-MISC (R_PMISC)
11954  */
11955 
11956 typedef struct                         /*!< (@ 0x4001FD00) R_PMISC Structure                                          */
11957 {
11958     __IM uint16_t RESERVED;
11959     __IM uint8_t  RESERVED1;
11960 
11961     union
11962     {
11963         __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
11964 
11965         struct
11966         {
11967             uint8_t             : 6;
11968             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
11969             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
11970         } PWPR_b;
11971     };
11972     __IM uint8_t RESERVED2;
11973 
11974     union
11975     {
11976         __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
11977 
11978         struct
11979         {
11980             uint8_t             : 6;
11981             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
11982             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
11983         } PWPRS_b;
11984     };
11985     __IM uint16_t RESERVED3[3];
11986 
11987     union
11988     {
11989         __IOM uint8_t PRWCNTR;         /*!< (@ 0x0000000C) Port Read Wait Control Register                            */
11990 
11991         struct
11992         {
11993             __IOM uint8_t WAIT : 4;    /*!< [3..0] Wait Cycle Control                                                 */
11994             uint8_t            : 4;
11995         } PRWCNTR_b;
11996     };
11997     __IM uint8_t             RESERVED4;
11998     __IM uint16_t            RESERVED5;
11999     __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
12000     __IM uint16_t            RESERVED6[12];
12001 
12002     union
12003     {
12004         __IOM uint16_t PSAR;            /*!< (@ 0x00000040) PORT Security Attribution Register                         */
12005 
12006         struct
12007         {
12008             __IOM uint16_t PORTSA0 : 1; /*!< [0..0] PRWCNTR Security Attribution                                       */
12009             uint16_t               : 15;
12010         } PSAR_b;
12011     };
12012 } R_PMISC_Type;                         /*!< Size = 66 (0x42)                                                          */
12013 
12014 /* =========================================================================================================================== */
12015 /* ================                                          R_QSPI                                           ================ */
12016 /* =========================================================================================================================== */
12017 
12018 /**
12019  * @brief Quad Serial Peripheral Interface (R_QSPI)
12020  */
12021 
12022 typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
12023 {
12024     union
12025     {
12026         __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */
12027 
12028         struct
12029         {
12030             __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
12031             uint32_t              : 1;
12032             __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
12033             __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
12034             __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
12035                                         *   other than on byte boundaries                                             */
12036             __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
12037                                         *   input to CFGMD3.                                                          */
12038             __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
12039                                         *   the serial interface                                                      */
12040             __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
12041             __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
12042             uint32_t              : 3;
12043             __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
12044             uint32_t              : 16;
12045         } SFMSMD_b;
12046     };
12047 
12048     union
12049     {
12050         __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */
12051 
12052         struct
12053         {
12054             __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
12055             __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
12056             __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
12057             uint32_t              : 26;
12058         } SFMSSC_b;
12059     };
12060 
12061     union
12062     {
12063         __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */
12064 
12065         struct
12066         {
12067             __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
12068                                         *   to the irregularity.)NOTE: When PCLKA multiplied by an
12069                                         *   odd number is selected, the high-level width of the SCK
12070                                         *   signal is longer than the low-level width by 1 x PCLKA
12071                                         *   before duty ratio correction.                                             */
12072             __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
12073                                         *   SCK signal                                                                */
12074             uint32_t : 26;
12075         } SFMSKC_b;
12076     };
12077 
12078     union
12079     {
12080         __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */
12081 
12082         struct
12083         {
12084             __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
12085                                         *   (No combination other than the above is available.)                       */
12086             uint32_t            : 1;
12087             __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
12088             __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
12089             uint32_t            : 24;
12090         } SFMSST_b;
12091     };
12092 
12093     union
12094     {
12095         __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */
12096 
12097         struct
12098         {
12099             __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
12100                                         *   to and from this port is converted to a SPIbus cycle. This
12101                                         *   port is accessible in the direct communication mode (DCOM=1)
12102                                         *   only.Access to this port is ignored in the ROM access mode.               */
12103             uint32_t : 24;
12104         } SFMCOM_b;
12105     };
12106 
12107     union
12108     {
12109         __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */
12110 
12111         struct
12112         {
12113             __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
12114             uint32_t            : 31;
12115         } SFMCMD_b;
12116     };
12117 
12118     union
12119     {
12120         __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */
12121 
12122         struct
12123         {
12124             __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
12125             uint32_t             : 6;
12126             __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
12127                                         *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
12128                                         *   ignored.                                                                  */
12129             uint32_t : 24;
12130         } SFMCST_b;
12131     };
12132     __IM uint32_t RESERVED;
12133 
12134     union
12135     {
12136         __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */
12137 
12138         struct
12139         {
12140             __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
12141             uint32_t              : 24;
12142         } SFMSIC_b;
12143     };
12144 
12145     union
12146     {
12147         __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */
12148 
12149         struct
12150         {
12151             __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
12152             uint32_t              : 2;
12153             __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
12154                                         *   Interface address width is selected 4 bytes.                              */
12155             uint32_t : 27;
12156         } SFMSAC_b;
12157     };
12158 
12159     union
12160     {
12161         __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */
12162 
12163         struct
12164         {
12165             __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
12166                                         *   instructions                                                              */
12167             uint32_t              : 2;
12168             __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
12169             __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
12170             __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
12171             uint32_t              : 16;
12172         } SFMSDC_b;
12173     };
12174     __IM uint32_t RESERVED1;
12175 
12176     union
12177     {
12178         __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */
12179 
12180         struct
12181         {
12182             __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
12183                                         *   is required to be set by software separately.                             */
12184             uint32_t              : 2;
12185             __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
12186                                         *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
12187             uint32_t : 27;
12188         } SFMSPC_b;
12189     };
12190 
12191     union
12192     {
12193         __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */
12194 
12195         struct
12196         {
12197             uint32_t              : 2;
12198             __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
12199             uint32_t              : 29;
12200         } SFMPMD_b;
12201     };
12202     __IM uint32_t RESERVED2[499];
12203 
12204     union
12205     {
12206         __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */
12207 
12208         struct
12209         {
12210             uint32_t                : 26;
12211             __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
12212                                           *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
12213                                           *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
12214         } SFMCNT1_b;
12215     };
12216 } R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */
12217 
12218 /* =========================================================================================================================== */
12219 /* ================                                           R_RTC                                           ================ */
12220 /* =========================================================================================================================== */
12221 
12222 /**
12223  * @brief Realtime Clock (R_RTC)
12224  */
12225 
12226 typedef struct                         /*!< (@ 0x40083000) R_RTC Structure                                            */
12227 {
12228     union
12229     {
12230         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
12231 
12232         struct
12233         {
12234             __IM uint8_t F64HZ  : 1;   /*!< [0..0] 64Hz Flag                                                          */
12235             __IM uint8_t F32HZ  : 1;   /*!< [1..1] 32Hz Flag                                                          */
12236             __IM uint8_t F16HZ  : 1;   /*!< [2..2] 16Hz Flag                                                          */
12237             __IM uint8_t F8HZ   : 1;   /*!< [3..3] 8Hz Flag                                                           */
12238             __IM uint8_t F4HZ   : 1;   /*!< [4..4] 4Hz Flag                                                           */
12239             __IM uint8_t F2HZ   : 1;   /*!< [5..5] 2Hz Flag                                                           */
12240             __IM uint8_t F1HZ   : 1;   /*!< [6..6] 1Hz Flag                                                           */
12241             __IM uint8_t R64OVF : 1;   /*!< [7..7] This bit indicates the overflow of F1HZ only when using
12242                                         *   time error adjustment function inlow-consumption clock
12243                                         *   mode.                                                                     */
12244         } R64CNT_b;
12245     };
12246     __IM uint8_t RESERVED;
12247 
12248     union
12249     {
12250         union
12251         {
12252             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
12253 
12254             struct
12255             {
12256                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
12257                                           *   counter b7 to b0.                                                         */
12258             } BCNT0_b;
12259         };
12260 
12261         union
12262         {
12263             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
12264 
12265             struct
12266             {
12267                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
12268                                           *   a carry is generated, 1 is added to the tens place.                       */
12269                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
12270                 uint8_t             : 1;
12271             } RSECCNT_b;
12272         };
12273     };
12274     __IM uint8_t RESERVED1;
12275 
12276     union
12277     {
12278         union
12279         {
12280             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
12281 
12282             struct
12283             {
12284                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
12285                                           *   counter b15 to b8.                                                        */
12286             } BCNT1_b;
12287         };
12288 
12289         union
12290         {
12291             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
12292 
12293             struct
12294             {
12295                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
12296                                           *   a carry is generated, 1 is added to the tens place.                       */
12297                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
12298                 uint8_t             : 1;
12299             } RMINCNT_b;
12300         };
12301     };
12302     __IM uint8_t RESERVED2;
12303 
12304     union
12305     {
12306         union
12307         {
12308             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
12309 
12310             struct
12311             {
12312                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
12313                                           *   counter b23 to b16.                                                       */
12314             } BCNT2_b;
12315         };
12316 
12317         union
12318         {
12319             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
12320 
12321             struct
12322             {
12323                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
12324                                          *   carry is generated, 1 is added to the tens place.                         */
12325                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
12326                                          *   the ones place.                                                           */
12327                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
12328                 uint8_t          : 1;
12329             } RHRCNT_b;
12330         };
12331     };
12332     __IM uint8_t RESERVED3;
12333 
12334     union
12335     {
12336         union
12337         {
12338             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
12339 
12340             struct
12341             {
12342                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
12343                                           *   counter b31 to b24.                                                       */
12344             } BCNT3_b;
12345         };
12346 
12347         union
12348         {
12349             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
12350 
12351             struct
12352             {
12353                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
12354                 uint8_t            : 5;
12355             } RWKCNT_b;
12356         };
12357     };
12358     __IM uint8_t RESERVED4;
12359 
12360     union
12361     {
12362         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
12363 
12364         struct
12365         {
12366             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
12367                                         *   is generated, 1 is added to the tens place.                               */
12368             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
12369                                         *   ones place.                                                               */
12370             uint8_t : 2;
12371         } RDAYCNT_b;
12372     };
12373     __IM uint8_t RESERVED5;
12374 
12375     union
12376     {
12377         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
12378 
12379         struct
12380         {
12381             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
12382                                         *   a carry is generated, 1 is added to the tens place.                       */
12383             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
12384                                         *   the ones place.                                                           */
12385             uint8_t : 3;
12386         } RMONCNT_b;
12387     };
12388     __IM uint8_t RESERVED6;
12389 
12390     union
12391     {
12392         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
12393 
12394         struct
12395         {
12396             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
12397                                         *   carry is generated, 1 is added to the tens place.                         */
12398             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
12399                                         *   ones place. When a carry is generated in the tens place,
12400                                         *   1 is added to the hundreds place.                                         */
12401             uint16_t : 8;
12402         } RYRCNT_b;
12403     };
12404 
12405     union
12406     {
12407         union
12408         {
12409             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
12410 
12411             struct
12412             {
12413                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
12414                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
12415             } BCNT0AR_b;
12416         };
12417 
12418         union
12419         {
12420             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
12421 
12422             struct
12423             {
12424                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
12425                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
12426                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
12427             } RSECAR_b;
12428         };
12429     };
12430     __IM uint8_t RESERVED7;
12431 
12432     union
12433     {
12434         union
12435         {
12436             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
12437 
12438             struct
12439             {
12440                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
12441                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
12442             } BCNT1AR_b;
12443         };
12444 
12445         union
12446         {
12447             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
12448 
12449             struct
12450             {
12451                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
12452                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
12453                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
12454             } RMINAR_b;
12455         };
12456     };
12457     __IM uint8_t RESERVED8;
12458 
12459     union
12460     {
12461         union
12462         {
12463             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
12464 
12465             struct
12466             {
12467                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
12468                                             *   counter b23 to b16.                                                       */
12469             } BCNT2AR_b;
12470         };
12471 
12472         union
12473         {
12474             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
12475 
12476             struct
12477             {
12478                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
12479                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
12480                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
12481                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
12482             } RHRAR_b;
12483         };
12484     };
12485     __IM uint8_t RESERVED9;
12486 
12487     union
12488     {
12489         union
12490         {
12491             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
12492 
12493             struct
12494             {
12495                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
12496                                             *   counter b31 to b24.                                                       */
12497             } BCNT3AR_b;
12498         };
12499 
12500         union
12501         {
12502             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
12503 
12504             struct
12505             {
12506                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
12507                 uint8_t            : 4;
12508                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
12509             } RWKAR_b;
12510         };
12511     };
12512     __IM uint8_t RESERVED10;
12513 
12514     union
12515     {
12516         union
12517         {
12518             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
12519 
12520             struct
12521             {
12522                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
12523                                         *   for setting the alarm enable corresponding to 32-bit binary
12524                                         *   counter b7 to b0.                                                         */
12525             } BCNT0AER_b;
12526         };
12527 
12528         union
12529         {
12530             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
12531 
12532             struct
12533             {
12534                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
12535                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
12536                 uint8_t              : 1;
12537                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
12538             } RDAYAR_b;
12539         };
12540     };
12541     __IM uint8_t RESERVED11;
12542 
12543     union
12544     {
12545         union
12546         {
12547             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
12548 
12549             struct
12550             {
12551                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
12552                                         *   for setting the alarm enable corresponding to 32-bit binary
12553                                         *   counter b15 to b8.                                                        */
12554             } BCNT1AER_b;
12555         };
12556 
12557         union
12558         {
12559             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
12560 
12561             struct
12562             {
12563                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
12564                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
12565                 uint8_t             : 2;
12566                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
12567             } RMONAR_b;
12568         };
12569     };
12570     __IM uint8_t RESERVED12;
12571 
12572     union
12573     {
12574         union
12575         {
12576             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
12577 
12578             struct
12579             {
12580                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
12581                                          *   for setting the alarm enable corresponding to 32-bit binary
12582                                          *   counter b23 to b16.                                                       */
12583                 uint16_t : 8;
12584             } BCNT2AER_b;
12585         };
12586 
12587         union
12588         {
12589             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
12590 
12591             struct
12592             {
12593                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
12594                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
12595                 uint16_t            : 8;
12596             } RYRAR_b;
12597         };
12598     };
12599 
12600     union
12601     {
12602         union
12603         {
12604             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
12605 
12606             struct
12607             {
12608                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
12609                                         *   for setting the alarm enable corresponding to 32-bit binary
12610                                         *   counter b31 to b24.                                                       */
12611             } BCNT3AER_b;
12612         };
12613 
12614         union
12615         {
12616             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
12617 
12618             struct
12619             {
12620                 uint8_t           : 7;
12621                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
12622             } RYRAREN_b;
12623         };
12624     };
12625     __IM uint8_t  RESERVED13;
12626     __IM uint16_t RESERVED14;
12627 
12628     union
12629     {
12630         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
12631 
12632         struct
12633         {
12634             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
12635             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
12636             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
12637             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
12638             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
12639         } RCR1_b;
12640     };
12641     __IM uint8_t RESERVED15;
12642 
12643     union
12644     {
12645         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
12646 
12647         struct
12648         {
12649             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
12650             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
12651             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
12652             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
12653             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
12654                                         *   the setting of this bit is disabled.)                                     */
12655             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
12656                                         *   is selected, the setting of this bit is disabled.)                        */
12657             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
12658             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
12659         } RCR2_b;
12660     };
12661     __IM uint8_t  RESERVED16;
12662     __IM uint16_t RESERVED17;
12663 
12664     union
12665     {
12666         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
12667 
12668         struct
12669         {
12670             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
12671             uint8_t              : 6;
12672             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
12673         } RCR4_b;
12674     };
12675     __IM uint8_t RESERVED18;
12676 
12677     union
12678     {
12679         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
12680 
12681         struct
12682         {
12683             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
12684                                         *   clock from the LOCOclock, this bit sets the comparison
12685                                         *   value of the 128-Hz clock cycle.                                          */
12686             uint16_t : 15;
12687         } RFRH_b;
12688     };
12689 
12690     union
12691     {
12692         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
12693 
12694         struct
12695         {
12696             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
12697                                         *   clock from the main clock, this bit sets the comparison
12698                                         *   value of the 128-Hz clock cycle.                                          */
12699         } RFRL_b;
12700     };
12701 
12702     union
12703     {
12704         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
12705 
12706         struct
12707         {
12708             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
12709                                         *   from the prescaler.                                                       */
12710             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
12711         } RADJ_b;
12712     };
12713     __IM uint8_t RESERVED19;
12714 
12715     union
12716     {
12717         __IOM uint16_t RADJ2;          /*!< (@ 0x00000030) Time Error Adjustment Register 2                           */
12718 
12719         struct
12720         {
12721             uint16_t            : 5;
12722             __IOM uint16_t FADJ : 11;  /*!< [15..5] Fractional Adjust Value                                           */
12723         } RADJ2_b;
12724     };
12725     __IM uint16_t          RESERVED20[7];
12726     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
12727     __IM uint16_t          RESERVED21[5];
12728     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
12729 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
12730 
12731 /* =========================================================================================================================== */
12732 /* ================                                          R_SCI0                                           ================ */
12733 /* =========================================================================================================================== */
12734 
12735 /**
12736  * @brief Serial Communications Interface (R_SCI0)
12737  */
12738 
12739 typedef struct                         /*!< (@ 0x40118000) R_SCI0 Structure                                           */
12740 {
12741     union
12742     {
12743         union
12744         {
12745             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
12746 
12747             struct
12748             {
12749                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
12750                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
12751                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
12752                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
12753                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
12754                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
12755                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
12756             } SMR_b;
12757         };
12758 
12759         union
12760         {
12761             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
12762 
12763             struct
12764             {
12765                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
12766                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
12767                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
12768                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
12769                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
12770                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
12771             } SMR_SMCI_b;
12772         };
12773     };
12774 
12775     union
12776     {
12777         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
12778 
12779         struct
12780         {
12781             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
12782         } BRR_b;
12783     };
12784 
12785     union
12786     {
12787         union
12788         {
12789             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
12790 
12791             struct
12792             {
12793                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
12794                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
12795                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
12796                                          *   mode when SMR.MP = 1)                                                     */
12797                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
12798                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
12799                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
12800                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
12801             } SCR_b;
12802         };
12803 
12804         union
12805         {
12806             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
12807 
12808             struct
12809             {
12810                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
12811                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
12812                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
12813                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
12814                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
12815                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
12816                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
12817             } SCR_SMCI_b;
12818         };
12819     };
12820 
12821     union
12822     {
12823         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
12824 
12825         struct
12826         {
12827             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
12828         } TDR_b;
12829     };
12830 
12831     union
12832     {
12833         union
12834         {
12835             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
12836 
12837             struct
12838             {
12839                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
12840                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
12841                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12842                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12843                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
12844                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12845                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
12846                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
12847             } SSR_b;
12848         };
12849 
12850         union
12851         {
12852             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
12853 
12854             struct
12855             {
12856                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
12857                                          *   multi-processor) and FIFO selected)                                       */
12858                 uint8_t            : 1;
12859                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12860                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12861                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
12862                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12863                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
12864                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
12865             } SSR_FIFO_b;
12866         };
12867 
12868         union
12869         {
12870             __IOM uint8_t SSR_MANC;     /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF
12871                                          *                  = 0, and MMR.MANEN = 1)                                    */
12872 
12873             struct
12874             {
12875                 __IOM uint8_t MER  : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only               */
12876                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
12877                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12878                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12879                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
12880                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12881                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
12882                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
12883             } SSR_MANC_b;
12884         };
12885 
12886         union
12887         {
12888             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
12889 
12890             struct
12891             {
12892                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
12893                                          *   card interface mode.                                                      */
12894                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
12895                                          *   mode.                                                                     */
12896                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12897                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12898                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
12899                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12900                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
12901                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
12902             } SSR_SMCI_b;
12903         };
12904     };
12905 
12906     union
12907     {
12908         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
12909 
12910         struct
12911         {
12912             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
12913         } RDR_b;
12914     };
12915 
12916     union
12917     {
12918         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
12919 
12920         struct
12921         {
12922             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
12923             uint8_t            : 1;
12924             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
12925                                         *   operation is to be in simple I2C mode.                                    */
12926             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
12927                                         *   setting is invalid and a fixed data length of 8 bits is
12928                                         *   used in modes other than asynchronous mode.Set this bit
12929                                         *   to 1 if operation is to be in simple I2C mode.                            */
12930             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
12931             uint8_t            : 2;
12932             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
12933                                         *   in combination with the SMR.BCP[1:0] bits                                 */
12934         } SCMR_b;
12935     };
12936 
12937     union
12938     {
12939         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
12940 
12941         struct
12942         {
12943             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
12944                                         *   asynchronous mode).                                                       */
12945             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
12946                                         *   mode).                                                                    */
12947             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
12948             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
12949                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
12950             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
12951                                         *   mode)                                                                     */
12952             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
12953                                         *   be 0 without simple I2C mode and asynchronous mode.)In
12954                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
12955                                         *   for RXDn/TxDn input.                                                      */
12956             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
12957                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
12958             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
12959                                         *   in asynchronous mode)                                                     */
12960         } SEMR_b;
12961     };
12962 
12963     union
12964     {
12965         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
12966 
12967         struct
12968         {
12969             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
12970             uint8_t            : 5;
12971         } SNFR_b;
12972     };
12973 
12974     union
12975     {
12976         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
12977 
12978         struct
12979         {
12980             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
12981             uint8_t             : 2;
12982             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
12983                                         *   signal from the on-chip baud rate generator.                              */
12984         } SIMR1_b;
12985     };
12986 
12987     union
12988     {
12989         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
12990 
12991         struct
12992         {
12993             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
12994             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
12995             uint8_t               : 3;
12996             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
12997             uint8_t               : 2;
12998         } SIMR2_b;
12999     };
13000 
13001     union
13002     {
13003         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
13004 
13005         struct
13006         {
13007             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
13008             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
13009             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
13010             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
13011                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
13012             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
13013             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
13014         } SIMR3_b;
13015     };
13016 
13017     union
13018     {
13019         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
13020 
13021         struct
13022         {
13023             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
13024             uint8_t              : 7;
13025         } SISR_b;
13026     };
13027 
13028     union
13029     {
13030         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
13031 
13032         struct
13033         {
13034             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
13035             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
13036             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
13037             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
13038             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
13039             uint8_t              : 1;
13040             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
13041             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
13042         } SPMR_b;
13043     };
13044 
13045     union
13046     {
13047         union
13048         {
13049             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
13050 
13051             struct
13052             {
13053                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
13054             } TDRHL_b;
13055         };
13056 
13057         union
13058         {
13059             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
13060 
13061             struct
13062             {
13063                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
13064                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13065                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
13066                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
13067                 uint16_t : 6;
13068             } FTDRHL_b;
13069         };
13070 
13071         union
13072         {
13073             __IOM uint16_t TDRHL_MAN;     /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN
13074                                            *                  = 1)                                                       */
13075 
13076             struct
13077             {
13078                 __IOM uint16_t TDAT  : 9; /*!< [8..0] Serial transmit data                                               */
13079                 __IOM uint16_t MPBT  : 1; /*!< [9..9] Multi-processor Transfer Bit Flag                                  */
13080                 uint16_t             : 2;
13081                 __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit                                           */
13082                 uint16_t             : 3;
13083             } TDRHL_MAN_b;
13084         };
13085 
13086         struct
13087         {
13088             union
13089             {
13090                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
13091 
13092                 struct
13093                 {
13094                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
13095                                              *   mode(including multi-processor) or clock synchronous mode,
13096                                              *   and FIFO selected)                                                        */
13097                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
13098                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
13099                     uint8_t : 6;
13100                 } FTDRH_b;
13101             };
13102 
13103             union
13104             {
13105                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
13106 
13107                 struct
13108                 {
13109                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
13110                                              *   mode(including multi-processor) or clock synchronous mode,
13111                                              *   and FIFO selected)                                                        */
13112                 } FTDRL_b;
13113             };
13114         };
13115     };
13116 
13117     union
13118     {
13119         union
13120         {
13121             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
13122 
13123             struct
13124             {
13125                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
13126             } RDRHL_b;
13127         };
13128 
13129         union
13130         {
13131             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
13132 
13133             struct
13134             {
13135                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
13136                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13137                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
13138                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
13139                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
13140                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
13141                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
13142                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
13143                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
13144                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
13145                 uint16_t           : 1;
13146             } FRDRHL_b;
13147         };
13148 
13149         union
13150         {
13151             __IM uint16_t RDRHL_MAN;     /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN
13152                                           *                  = 1)                                                       */
13153 
13154             struct
13155             {
13156                 __IM uint16_t RDAT  : 9; /*!< [8..0] Serial Receive Data                                                */
13157                 __IM uint16_t MPB   : 1; /*!< [9..9] Multi-processor Bit                                                */
13158                 uint16_t            : 2;
13159                 __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit                                            */
13160                 uint16_t            : 3;
13161             } RDRHL_MAN_b;
13162         };
13163 
13164         struct
13165         {
13166             union
13167             {
13168                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
13169 
13170                 struct
13171                 {
13172                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
13173                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13174                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
13175                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
13176                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
13177                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
13178                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
13179                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
13180                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
13181                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
13182                     uint8_t           : 1;
13183                 } FRDRH_b;
13184             };
13185 
13186             union
13187             {
13188                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
13189 
13190                 struct
13191                 {
13192                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
13193                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
13194                                              *   When reading both of FRDRH register and FRDRL register,
13195                                              *   please read by an order of the FRDRH register and the FRDRL
13196                                              *   register.                                                                 */
13197                 } FRDRL_b;
13198             };
13199         };
13200     };
13201 
13202     union
13203     {
13204         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
13205 
13206         struct
13207         {
13208             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
13209         } MDDR_b;
13210     };
13211 
13212     union
13213     {
13214         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
13215 
13216         struct
13217         {
13218             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
13219             uint8_t             : 2;
13220             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
13221             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
13222             uint8_t             : 1;
13223             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
13224                                         *   multi-processor)                                                          */
13225             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
13226                                         *   mode(including multi-processor)                                           */
13227         } DCCR_b;
13228     };
13229 
13230     union
13231     {
13232         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
13233 
13234         struct
13235         {
13236             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
13237                                         *   multi-processor) or clock synchronous mode)                               */
13238             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
13239             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
13240             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
13241                                         *   reception data ready, the interrupt request is selected.)                 */
13242             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
13243                                         *   mode(including multi-processor) or clock synchronous mode)                */
13244             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
13245                                         *   mode(including multi-processor) or clock synchronous mode)                */
13246             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
13247                                         *   in asynchronous mode(including multi-processor) or clock
13248                                         *   synchronous mode)                                                         */
13249         } FCR_b;
13250     };
13251 
13252     union
13253     {
13254         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
13255 
13256         struct
13257         {
13258             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
13259                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
13260                                         *   mode(including multi-processor) or clock synchronous mode,
13261                                         *   while FCR.FM=1)                                                           */
13262             uint16_t        : 3;
13263             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
13264                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
13265                                         *   mode(including multi-processor) or clock synchronous mode,
13266                                         *   while FCR.FM=1)                                                           */
13267             uint16_t : 3;
13268         } FDR_b;
13269     };
13270 
13271     union
13272     {
13273         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
13274 
13275         struct
13276         {
13277             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
13278                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13279             uint16_t           : 1;
13280             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
13281                                         *   a framing error among the receive data stored in the receive
13282                                         *   FIFO data register (FRDRH and FRDRL).                                     */
13283             uint16_t           : 1;
13284             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
13285                                         *   a parity error among the receive data stored in the receive
13286                                         *   FIFO data register (FRDRH and FRDRL).                                     */
13287             uint16_t : 3;
13288         } LSR_b;
13289     };
13290 
13291     union
13292     {
13293         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
13294 
13295         struct
13296         {
13297             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
13298                                         *   wake-up function                                                          */
13299             uint16_t : 7;
13300         } CDR_b;
13301     };
13302 
13303     union
13304     {
13305         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
13306 
13307         struct
13308         {
13309             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
13310                                         *   is shown.)                                                                */
13311             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
13312                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
13313             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
13314                                         *   of SPB2DT is output to TxD terminal.)                                     */
13315             uint8_t            : 1;
13316             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
13317             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
13318             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
13319             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
13320         } SPTR_b;
13321     };
13322 
13323     union
13324     {
13325         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
13326 
13327         struct
13328         {
13329             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
13330             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
13331             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
13332             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
13333         } ACTR_b;
13334     };
13335     __IM uint16_t RESERVED;
13336 
13337     union
13338     {
13339         union
13340         {
13341             __IOM uint8_t ESMER;        /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
13342 
13343             struct
13344             {
13345                 __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable                                        */
13346                 uint8_t            : 7;
13347             } ESMER_b;
13348         };
13349 
13350         union
13351         {
13352             __IOM uint8_t MMR;            /*!< (@ 0x00000020) Manchester Mode Register                                   */
13353 
13354             struct
13355             {
13356                 __IOM uint8_t RMPOL  : 1; /*!< [0..0] Polarity of Received Manchester Code                               */
13357                 __IOM uint8_t TMPOL  : 1; /*!< [1..1] Polarity of Transmit Manchester Code                               */
13358                 __IOM uint8_t ERTEN  : 1; /*!< [2..2] Manchester Edge Retiming Enable                                    */
13359                 uint8_t              : 1;
13360                 __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting                                                 */
13361                 __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select                                                        */
13362                 __IOM uint8_t SBSEL  : 1; /*!< [6..6] Start Bit Select                                                   */
13363                 __IOM uint8_t MANEN  : 1; /*!< [7..7] Manchester Mode Enable                                             */
13364             } MMR_b;
13365         };
13366     };
13367 
13368     union
13369     {
13370         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
13371 
13372         struct
13373         {
13374             uint8_t             : 1;
13375             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
13376             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
13377             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
13378             uint8_t             : 4;
13379         } CR0_b;
13380     };
13381 
13382     union
13383     {
13384         union
13385         {
13386             __IOM uint8_t CR1;           /*!< (@ 0x00000022) Control Register 1                                         */
13387 
13388             struct
13389             {
13390                 __IOM uint8_t BFE   : 1; /*!< [0..0] Break Field Enable                                                 */
13391                 __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable                                   */
13392                 __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select                               */
13393                 __IOM uint8_t PIBE  : 1; /*!< [4..4] Priority Interrupt Bit Enable                                      */
13394                 __IOM uint8_t PIBS  : 3; /*!< [7..5] Priority Interrupt Bit Select                                      */
13395             } CR1_b;
13396         };
13397 
13398         union
13399         {
13400             __IOM uint8_t TMPR;          /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register               */
13401 
13402             struct
13403             {
13404                 __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length                                            */
13405                 __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern                                           */
13406                 uint8_t             : 2;
13407             } TMPR_b;
13408         };
13409     };
13410 
13411     union
13412     {
13413         union
13414         {
13415             __IOM uint8_t CR2;          /*!< (@ 0x00000023) Control Register 2                                         */
13416 
13417             struct
13418             {
13419                 __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
13420                 uint8_t            : 1;
13421                 __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select                               */
13422                 __IOM uint8_t RTS  : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
13423             } CR2_b;
13424         };
13425 
13426         union
13427         {
13428             __IOM uint8_t RMPR;          /*!< (@ 0x00000023) Receive Manchester Preface Setting Register                */
13429 
13430             struct
13431             {
13432                 __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length                                             */
13433                 __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern                                            */
13434                 uint8_t             : 2;
13435             } RMPR_b;
13436         };
13437     };
13438 
13439     union
13440     {
13441         union
13442         {
13443             __IOM uint8_t CR3;          /*!< (@ 0x00000024) Control Register 3                                         */
13444 
13445             struct
13446             {
13447                 __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start                                        */
13448                 uint8_t            : 7;
13449             } CR3_b;
13450         };
13451 
13452         union
13453         {
13454             __IOM uint8_t MESR;         /*!< (@ 0x00000024) Manchester Extended Error Status Register                  */
13455 
13456             struct
13457             {
13458                 __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag                                                 */
13459                 __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag                                                    */
13460                 __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag                                               */
13461                 uint8_t            : 5;
13462             } MESR_b;
13463         };
13464     };
13465 
13466     union
13467     {
13468         union
13469         {
13470             __IOM uint8_t PCR;            /*!< (@ 0x00000025) Port Control Register                                      */
13471 
13472             struct
13473             {
13474                 __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select                                       */
13475                 __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select                                       */
13476                 uint8_t              : 2;
13477                 __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
13478                 uint8_t              : 3;
13479             } PCR_b;
13480         };
13481 
13482         union
13483         {
13484             __IOM uint8_t MECR;           /*!< (@ 0x00000025) Manchester Extended Error Control Register                 */
13485 
13486             struct
13487             {
13488                 __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag                                                 */
13489                 __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable                                          */
13490                 __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable                                             */
13491                 uint8_t              : 5;
13492             } MECR_b;
13493         };
13494     };
13495 
13496     union
13497     {
13498         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
13499 
13500         struct
13501         {
13502             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
13503             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
13504             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
13505             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
13506             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
13507             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
13508             uint8_t              : 2;
13509         } ICR_b;
13510     };
13511 
13512     union
13513     {
13514         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
13515 
13516         struct
13517         {
13518             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
13519             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
13520             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
13521             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
13522             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
13523             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
13524             uint8_t            : 2;
13525         } STR_b;
13526     };
13527 
13528     union
13529     {
13530         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
13531 
13532         struct
13533         {
13534             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
13535             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
13536             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
13537             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
13538             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
13539             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
13540             uint8_t              : 2;
13541         } STCR_b;
13542     };
13543     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
13544 
13545     union
13546     {
13547         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
13548 
13549         struct
13550         {
13551             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
13552             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
13553             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
13554             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
13555             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
13556             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
13557             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
13558             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
13559         } CF0CR_b;
13560     };
13561     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
13562     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
13563     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
13564 
13565     union
13566     {
13567         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
13568 
13569         struct
13570         {
13571             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
13572             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
13573             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
13574             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
13575             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
13576             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
13577             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
13578             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
13579         } CF1CR_b;
13580     };
13581     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
13582 
13583     union
13584     {
13585         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
13586 
13587         struct
13588         {
13589             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
13590             uint8_t            : 7;
13591         } TCR_b;
13592     };
13593 
13594     union
13595     {
13596         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
13597 
13598         struct
13599         {
13600             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
13601             uint8_t            : 1;
13602             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
13603             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
13604             uint8_t            : 1;
13605         } TMR_b;
13606     };
13607     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
13608     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
13609     __IM uint16_t RESERVED1[4];
13610 
13611     union
13612     {
13613         __IOM uint8_t SCIMSKEN;        /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register                       */
13614 
13615         struct
13616         {
13617             __IOM uint8_t MSKEN : 1;   /*!< [0..0] SCI5 TXD Output Mask Enable                                        */
13618             uint8_t             : 7;
13619         } SCIMSKEN_b;
13620     };
13621     __IM uint8_t  RESERVED2;
13622     __IM uint16_t RESERVED3;
13623 } R_SCI0_Type;                         /*!< Size = 64 (0x40)                                                          */
13624 
13625 /* =========================================================================================================================== */
13626 /* ================                                          R_SLCDC                                          ================ */
13627 /* =========================================================================================================================== */
13628 
13629 /**
13630  * @brief Segment LCD Controller/Driver (R_SLCDC)
13631  */
13632 
13633 typedef struct                         /*!< (@ 0x400D4000) R_SLCDC Structure                                          */
13634 {
13635     union
13636     {
13637         __IOM uint8_t LCDM0;           /*!< (@ 0x00000000) LCD Mode Register 0                                        */
13638 
13639         struct
13640         {
13641             __IOM uint8_t LBAS  : 2;   /*!< [1..0] LCD Display Bias Method Select                                     */
13642             __IOM uint8_t LDTY  : 3;   /*!< [4..2] Time Slice of LCD Display Select                                   */
13643             __IOM uint8_t LWAVE : 1;   /*!< [5..5] LCD display waveform selection                                     */
13644             __IOM uint8_t MDSET : 2;   /*!< [7..6] LCD drive voltage generator selection                              */
13645         } LCDM0_b;
13646     };
13647 
13648     union
13649     {
13650         __IOM uint8_t LCDM1;           /*!< (@ 0x00000001) LCD Mode Register 1                                        */
13651 
13652         struct
13653         {
13654             __IOM uint8_t LCDVLM : 1;  /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control               */
13655             uint8_t              : 2;
13656             __IOM uint8_t LCDSEL : 1;  /*!< [3..3] Display data area control                                          */
13657             __IOM uint8_t BLON   : 1;  /*!< [4..4] Display data area control                                          */
13658             __IOM uint8_t VLCON  : 1;  /*!< [5..5] Voltage boost circuit or capacitor split circuit operation
13659                                         *   enable/disable                                                            */
13660             __IOM uint8_t SCOC  : 1;   /*!< [6..6] LCD Display Enable/Disable                                         */
13661             __IOM uint8_t LCDON : 1;   /*!< [7..7] LCD Display Enable/Disable                                         */
13662         } LCDM1_b;
13663     };
13664 
13665     union
13666     {
13667         __IOM uint8_t LCDC0;           /*!< (@ 0x00000002) LCD Clock Control Register 0                               */
13668 
13669         struct
13670         {
13671             __IOM uint8_t LCDC : 6;    /*!< [5..0] LCD clock (LCDCL)                                                  */
13672             uint8_t            : 2;
13673         } LCDC0_b;
13674     };
13675 
13676     union
13677     {
13678         __IOM uint8_t VLCD;            /*!< (@ 0x00000003) LCD Boost Level Control Register                           */
13679 
13680         struct
13681         {
13682             __IOM uint8_t VLCD   : 5;  /*!< [4..0] Reference Voltage(Contrast Adjustment) Select                      */
13683             uint8_t              : 2;
13684             __IOM uint8_t MDSET2 : 1;  /*!< [7..7] Reference Voltage Selection                                        */
13685         } VLCD_b;
13686     };
13687     __IM uint8_t RESERVED[252];
13688 
13689     union
13690     {
13691         __IOM uint8_t SEG[64];         /*!< (@ 0x00000100) LCD Display Data Array                                     */
13692 
13693         struct
13694         {
13695             __IOM uint8_t A : 4;       /*!< [3..0] A-Pattern Area                                                     */
13696             __IOM uint8_t B : 4;       /*!< [7..4] B-Pattern Area                                                     */
13697         } SEG_b[64];
13698     };
13699 } R_SLCDC_Type;                        /*!< Size = 320 (0x140)                                                        */
13700 
13701 /* =========================================================================================================================== */
13702 /* ================                                          R_SPI0                                           ================ */
13703 /* =========================================================================================================================== */
13704 
13705 /**
13706  * @brief Serial Peripheral Interface (R_SPI0)
13707  */
13708 
13709 typedef struct                         /*!< (@ 0x4011A000) R_SPI0 Structure                                           */
13710 {
13711     union
13712     {
13713         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
13714 
13715         struct
13716         {
13717             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
13718             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
13719             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
13720             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
13721             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
13722             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
13723             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
13724             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
13725         } SPCR_b;
13726     };
13727 
13728     union
13729     {
13730         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
13731 
13732         struct
13733         {
13734             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
13735             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
13736             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
13737             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
13738             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
13739             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
13740             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
13741             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
13742         } SSLP_b;
13743     };
13744 
13745     union
13746     {
13747         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
13748 
13749         struct
13750         {
13751             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
13752             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
13753             uint8_t             : 2;
13754             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
13755             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
13756             uint8_t             : 2;
13757         } SPPCR_b;
13758     };
13759 
13760     union
13761     {
13762         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
13763 
13764         struct
13765         {
13766             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
13767             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
13768             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
13769             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
13770             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
13771             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
13772             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
13773             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
13774         } SPSR_b;
13775     };
13776 
13777     union
13778     {
13779         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
13780         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
13781         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
13782     };
13783 
13784     union
13785     {
13786         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
13787 
13788         struct
13789         {
13790             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
13791                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
13792                                         *   changed in accordance with the sequence length that is
13793                                         *   set in these bits. The relationship among the setting of
13794                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
13795                                         *   referenced by the RSPI is shown above. However, the RSPI
13796                                         *   in slave mode always references SPCMD0.                                   */
13797             uint8_t : 5;
13798         } SPSCR_b;
13799     };
13800 
13801     union
13802     {
13803         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
13804 
13805         struct
13806         {
13807             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
13808             uint8_t            : 1;
13809             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
13810             uint8_t            : 1;
13811         } SPSSR_b;
13812     };
13813 
13814     union
13815     {
13816         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
13817 
13818         struct
13819         {
13820             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
13821         } SPBR_b;
13822     };
13823 
13824     union
13825     {
13826         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
13827 
13828         struct
13829         {
13830             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
13831             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
13832             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
13833             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
13834             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
13835             uint8_t              : 1;
13836         } SPDCR_b;
13837     };
13838 
13839     union
13840     {
13841         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
13842 
13843         struct
13844         {
13845             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
13846             uint8_t             : 5;
13847         } SPCKD_b;
13848     };
13849 
13850     union
13851     {
13852         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
13853 
13854         struct
13855         {
13856             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
13857             uint8_t             : 5;
13858         } SSLND_b;
13859     };
13860 
13861     union
13862     {
13863         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
13864 
13865         struct
13866         {
13867             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
13868             uint8_t             : 5;
13869         } SPND_b;
13870     };
13871 
13872     union
13873     {
13874         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
13875 
13876         struct
13877         {
13878             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
13879             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
13880             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
13881             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
13882             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
13883             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
13884         } SPCR2_b;
13885     };
13886 
13887     union
13888     {
13889         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
13890 
13891         struct
13892         {
13893             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
13894             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
13895             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
13896             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
13897             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
13898             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
13899             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
13900             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
13901             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
13902             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
13903         } SPCMD_b[8];
13904     };
13905 
13906     union
13907     {
13908         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
13909 
13910         struct
13911         {
13912             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
13913             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
13914             uint8_t            : 6;
13915         } SPDCR2_b;
13916     };
13917 
13918     union
13919     {
13920         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
13921 
13922         struct
13923         {
13924             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
13925             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
13926             uint8_t              : 2;
13927             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
13928             uint8_t              : 3;
13929         } SPCR3_b;
13930     };
13931     __IM uint16_t RESERVED;
13932     __IM uint32_t RESERVED1[6];
13933     __IM uint16_t RESERVED2;
13934 
13935     union
13936     {
13937         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
13938 
13939         struct
13940         {
13941             uint16_t              : 4;
13942             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
13943             uint16_t              : 3;
13944             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
13945             uint16_t              : 1;
13946             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
13947         } SPPR_b;
13948     };
13949 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
13950 
13951 /* =========================================================================================================================== */
13952 /* ================                                          R_SRAM                                           ================ */
13953 /* =========================================================================================================================== */
13954 
13955 /**
13956  * @brief SRAM (R_SRAM)
13957  */
13958 
13959 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
13960 {
13961     union
13962     {
13963         __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
13964 
13965         struct
13966         {
13967             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
13968             uint8_t           : 7;
13969         } PARIOAD_b;
13970     };
13971     __IM uint8_t RESERVED[3];
13972 
13973     union
13974     {
13975         __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
13976 
13977         struct
13978         {
13979             __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
13980             __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
13981         } SRAMPRCR_b;
13982     };
13983     __IM uint8_t  RESERVED1[3];
13984     __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
13985     __IM uint8_t  RESERVED2[3];
13986 
13987     union
13988     {
13989         __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
13990 
13991         struct
13992         {
13993             __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
13994             __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
13995         } SRAMPRCR2_b;
13996     };
13997     __IM uint8_t RESERVED3[179];
13998 
13999     union
14000     {
14001         __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
14002 
14003         struct
14004         {
14005             __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
14006             uint8_t              : 6;
14007         } ECCMODE_b;
14008     };
14009 
14010     union
14011     {
14012         __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
14013 
14014         struct
14015         {
14016             __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
14017             uint8_t               : 7;
14018         } ECC2STS_b;
14019     };
14020 
14021     union
14022     {
14023         __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
14024 
14025         struct
14026         {
14027             __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
14028             uint8_t               : 7;
14029         } ECC1STSEN_b;
14030     };
14031 
14032     union
14033     {
14034         __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
14035 
14036         struct
14037         {
14038             __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
14039             uint8_t               : 7;
14040         } ECC1STS_b;
14041     };
14042 
14043     union
14044     {
14045         __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
14046 
14047         struct
14048         {
14049             __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
14050             __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
14051         } ECCPRCR_b;
14052     };
14053     __IM uint8_t RESERVED4[11];
14054 
14055     union
14056     {
14057         __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
14058 
14059         struct
14060         {
14061             __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
14062             __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
14063         } ECCPRCR2_b;
14064     };
14065     __IM uint8_t RESERVED5[3];
14066 
14067     union
14068     {
14069         __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
14070 
14071         struct
14072         {
14073             __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
14074             uint8_t              : 7;
14075         } ECCETST_b;
14076     };
14077     __IM uint8_t RESERVED6[3];
14078 
14079     union
14080     {
14081         __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
14082 
14083         struct
14084         {
14085             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
14086             uint8_t           : 7;
14087         } ECCOAD_b;
14088     };
14089 } R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
14090 
14091 /* =========================================================================================================================== */
14092 /* ================                                          R_SSI0                                           ================ */
14093 /* =========================================================================================================================== */
14094 
14095 /**
14096  * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
14097  */
14098 
14099 typedef struct                         /*!< (@ 0x4009D000) R_SSI0 Structure                                           */
14100 {
14101     union
14102     {
14103         __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
14104 
14105         struct
14106         {
14107             __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
14108             __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
14109             uint32_t            : 1;
14110             __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
14111                                         *   of outputting serial data is rewritten to 0 but data transmission
14112                                         *   is not stopped. Write dummy data to the SSIFTDR not to
14113                                         *   generate a transmit underflow because the number of data
14114                                         *   in the transmit FIFO is decreasing.                                       */
14115             __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
14116             __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
14117             __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
14118             __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
14119             __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
14120             __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
14121             __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
14122             __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
14123                                         *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
14124                                         *   are prohibited.                                                           */
14125             uint32_t           : 1;
14126             __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
14127                                         *   bit clock frequency/2 fs.                                                 */
14128             __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
14129             __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
14130             uint32_t             : 1;
14131             __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
14132             __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
14133             __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
14134             __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
14135             __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
14136             __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
14137             uint32_t             : 1;
14138         } SSICR_b;
14139     };
14140 
14141     union
14142     {
14143         __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
14144 
14145         struct
14146         {
14147             __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
14148             __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
14149             __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
14150             __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
14151             __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
14152             uint32_t             : 18;
14153             __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
14154             __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
14155                                         *   Writable only to clear the flag. Confirm the value is 1
14156                                         *   and then write 0.                                                         */
14157             __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
14158                                         *   Writable only to clear the flag. Confirm the value is 1
14159                                         *   and then write 0.                                                         */
14160             __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
14161                                         *   Writable only to clear the flag. Confirm the value is 1
14162                                         *   and then write 0.                                                         */
14163             __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
14164                                         *   Writable only to clear the flag. Confirm the value is 1
14165                                         *   and then write 0.                                                         */
14166             uint32_t : 2;
14167         } SSISR_b;
14168     };
14169     __IM uint32_t RESERVED[2];
14170 
14171     union
14172     {
14173         __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
14174 
14175         struct
14176         {
14177             __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
14178             __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
14179             __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
14180                                         *   clearing either the RDF flag (see the description of the
14181                                         *   RDF bit for details) or RIE bit.                                          */
14182             __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
14183                                         *   clearing either the TDE flag (see the description of the
14184                                         *   TDE bit for details) or TIE bit.                                          */
14185             __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
14186             __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
14187                                         *   are the number of empty stages in SSIFTDR at which the
14188                                         *   TDE flag is set.                                                          */
14189             uint32_t              : 3;
14190             __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
14191             uint32_t              : 4;
14192             __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
14193             uint32_t              : 14;
14194             __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
14195         } SSIFCR_b;
14196     };
14197 
14198     union
14199     {
14200         __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
14201 
14202         struct
14203         {
14204             __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
14205                                         *   is a 32-byte FIFO register, the maximum number of data
14206                                         *   bytes that can be read from it while the RDF flag is 1
14207                                         *   is indicated in the RDC[3:0] flags. If reading data from
14208                                         *   the SSIFRDR register is continued after all the data is
14209                                         *   read, undefined values will be read.                                      */
14210             uint32_t          : 7;
14211             __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
14212                                         *   units stored in SSIFRDR)                                                  */
14213             uint32_t           : 2;
14214             __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
14215                                         *   is a 32-byte FIFO register, the maximum number of bytes
14216                                         *   that can be written to it while the TDE flag is 1 is 8
14217                                         *   - TDC[3:0]. If writing data to the SSIFTDR register is
14218                                         *   continued after all the data is written, writing will be
14219                                         *   invalid and an overflow occurs.                                           */
14220             uint32_t          : 7;
14221             __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
14222                                         *   data units stored in SSIFTDR)                                             */
14223             uint32_t : 2;
14224         } SSIFSR_b;
14225     };
14226 
14227     union
14228     {
14229         union
14230         {
14231             __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
14232 
14233             struct
14234             {
14235                 __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
14236                                              *   eight stages of 32-bit registers for storing data to be
14237                                              *   serially transmitted. NOTE: that when the SSIFTDR register
14238                                              *   is full of data (32 bytes), the next data cannot be written
14239                                              *   to it. If writing is attempted, it will be ignored and
14240                                              *   an overflow occurs.                                                       */
14241             } SSIFTDR_b;
14242         };
14243         __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
14244         __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
14245     };
14246 
14247     union
14248     {
14249         union
14250         {
14251             __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
14252 
14253             struct
14254             {
14255                 __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
14256                                              *   stages of 32-bit registers for storing serially received
14257                                              *   data.                                                                     */
14258             } SSIFRDR_b;
14259         };
14260         __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
14261         __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
14262     };
14263 
14264     union
14265     {
14266         __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
14267 
14268         struct
14269         {
14270             __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
14271             uint32_t               : 6;
14272             __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
14273             __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
14274                                          *   Idle Status                                                               */
14275             uint32_t : 22;
14276         } SSIOFR_b;
14277     };
14278 
14279     union
14280     {
14281         __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
14282 
14283         struct
14284         {
14285             __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
14286             uint32_t            : 3;
14287             __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
14288             uint32_t            : 19;
14289         } SSISCR_b;
14290     };
14291 } R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
14292 
14293 /* =========================================================================================================================== */
14294 /* ================                                         R_SYSTEM                                          ================ */
14295 /* =========================================================================================================================== */
14296 
14297 /**
14298  * @brief System Pins (R_SYSTEM)
14299  */
14300 
14301 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
14302 {
14303     __IM uint32_t RESERVED[3];
14304 
14305     union
14306     {
14307         __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
14308 
14309         struct
14310         {
14311             uint16_t            : 15;
14312             __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
14313         } SBYCR_b;
14314     };
14315     __IM uint16_t RESERVED1;
14316     __IM uint32_t RESERVED2[4];
14317 
14318     union
14319     {
14320         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
14321 
14322         struct
14323         {
14324             __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
14325             uint32_t            : 1;
14326             __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
14327             uint32_t            : 1;
14328             __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
14329             uint32_t            : 1;
14330             __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
14331             uint32_t            : 1;
14332             __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
14333             uint32_t            : 5;
14334             __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
14335             uint32_t            : 1;
14336             __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
14337             uint32_t            : 1;
14338         } SCKDIVCR_b;
14339     };
14340     __IM uint16_t RESERVED3;
14341 
14342     union
14343     {
14344         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
14345 
14346         struct
14347         {
14348             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
14349             uint8_t             : 5;
14350         } SCKSCR_b;
14351     };
14352     __IM uint8_t RESERVED4;
14353 
14354     union
14355     {
14356         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
14357 
14358         struct
14359         {
14360             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
14361             uint16_t                : 2;
14362             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
14363             uint16_t                : 3;
14364             __IOM uint16_t PLLMUL   : 5; /*!< [12..8] PLL Frequency Multiplication Factor Select [PLL Frequency
14365                                           *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
14366                                           *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
14367                                           *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
14368                                           *   111011: x30.0                                                             */
14369             uint16_t : 3;
14370         } PLLCCR_b;
14371     };
14372 
14373     union
14374     {
14375         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
14376 
14377         struct
14378         {
14379             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
14380             uint8_t              : 7;
14381         } PLLCR_b;
14382     };
14383     __IM uint8_t  RESERVED5;
14384     __IM uint32_t RESERVED6;
14385     __IM uint8_t  RESERVED7;
14386 
14387     union
14388     {
14389         __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
14390 
14391         struct
14392         {
14393             __IOM uint8_t MEMWAIT : 2; /*!< [1..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
14394                                         *   is prohibited when SCKDIVCR.ICK selects division by 1 and
14395                                         *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
14396                                         *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
14397             uint8_t : 6;
14398         } MEMWAIT_b;
14399     };
14400 
14401     union
14402     {
14403         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
14404 
14405         struct
14406         {
14407             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
14408             uint8_t             : 7;
14409         } MOSCCR_b;
14410     };
14411     __IM uint8_t  RESERVED8;
14412     __IM uint16_t RESERVED9;
14413 
14414     union
14415     {
14416         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
14417 
14418         struct
14419         {
14420             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
14421             uint8_t             : 7;
14422         } HOCOCR_b;
14423     };
14424     __IM uint8_t RESERVED10;
14425 
14426     union
14427     {
14428         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
14429 
14430         struct
14431         {
14432             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
14433             uint8_t             : 7;
14434         } MOCOCR_b;
14435     };
14436     __IM uint8_t  RESERVED11;
14437     __IM uint16_t RESERVED12;
14438 
14439     union
14440     {
14441         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
14442 
14443         struct
14444         {
14445             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
14446                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
14447                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
14448             uint8_t               : 2;
14449             __IM uint8_t MOSCSF   : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
14450             uint8_t               : 1;
14451             __IM uint8_t PLLSF    : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
14452             uint8_t               : 1;
14453             __IM uint8_t PLLRTCSF : 1; /*!< [7..7] PLL_RTC Clock Oscillation Stabilization Flag                       */
14454         } OSCSF_b;
14455     };
14456     __IM uint8_t RESERVED13;
14457 
14458     union
14459     {
14460         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
14461 
14462         struct
14463         {
14464             __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
14465             uint8_t              : 1;
14466             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
14467             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
14468         } CKOCR_b;
14469     };
14470     __IM uint8_t RESERVED14;
14471 
14472     union
14473     {
14474         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
14475 
14476         struct
14477         {
14478             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
14479             uint8_t              : 6;
14480             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
14481         } OSTDCR_b;
14482     };
14483 
14484     union
14485     {
14486         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
14487 
14488         struct
14489         {
14490             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
14491             uint8_t             : 7;
14492         } OSTDSR_b;
14493     };
14494 
14495     union
14496     {
14497         __IOM uint16_t SOSTDCR;           /*!< (@ 0x00000042) Sub-Clock Oscillation Stop Detection Control
14498                                            *                  Register                                                   */
14499 
14500         struct
14501         {
14502             __IOM uint16_t SOSDCCMP : 12; /*!< [11..0] Sub-Clock Oscillation Stop Detection Time                         */
14503             __IOM uint16_t SOSTDIE  : 1;  /*!< [12..12] Sub-Clock Oscillation Stop Detection Interrupt Enable            */
14504             __IM uint16_t  SOSTDF   : 1;  /*!< [13..13] Sub-Clock Oscillation Stop Detection Flag                        */
14505             __IM uint16_t  SOSDCF   : 1;  /*!< [14..14] Status of Sub-Clock Oscillation Stop Detector Operation          */
14506             __IM uint16_t  SOSDCE   : 1;  /*!< [15..15] Control of Sub-Clock Oscillation Stop Detector Operation         */
14507         } SOSTDCR_b;
14508     };
14509     __IM uint32_t RESERVED15;
14510     __IM uint16_t RESERVED16;
14511 
14512     union
14513     {
14514         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
14515 
14516         struct
14517         {
14518             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
14519             uint8_t               : 7;
14520         } PLL2CR_b;
14521     };
14522     __IM uint8_t  RESERVED17;
14523     __IM uint32_t RESERVED18;
14524 
14525     union
14526     {
14527         __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
14528 
14529         struct
14530         {
14531             __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
14532             uint8_t                 : 4;
14533             __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
14534         } SLCDSCKCR_b;
14535     };
14536     __IM uint8_t  RESERVED19;
14537     __IM uint16_t RESERVED20[2];
14538 
14539     union
14540     {
14541         __IOM uint8_t PLLRTCCR;          /*!< (@ 0x00000056) PLL_RTC Control Register                                   */
14542 
14543         struct
14544         {
14545             __IOM uint8_t PLLRTCSTP : 1; /*!< [0..0] PLL_RTC Stop Control                                               */
14546             uint8_t                 : 7;
14547         } PLLRTCCR_b;
14548     };
14549     __IM uint8_t  RESERVED21;
14550     __IM uint32_t RESERVED22[2];
14551     __IM uint8_t  RESERVED23;
14552 
14553     union
14554     {
14555         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
14556 
14557         struct
14558         {
14559             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
14560                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
14561                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
14562                                          +126 0111_1111 : +127These bits are added to original MOCO
14563                                          *   trimming bits                                                             */
14564         } MOCOUTCR_b;
14565     };
14566 
14567     union
14568     {
14569         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
14570 
14571         struct
14572         {
14573             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
14574                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
14575                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
14576                                          +126 0111_1111 : +127These bits are added to original HOCO
14577                                          *   trimming bits                                                             */
14578         } HOCOUTCR_b;
14579     };
14580     __IM uint8_t  RESERVED24;
14581     __IM uint32_t RESERVED25[2];
14582     __IM uint16_t RESERVED26;
14583 
14584     union
14585     {
14586         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
14587 
14588         struct
14589         {
14590             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
14591             uint8_t                  : 5;
14592         } CANFDCKDIVCR_b;
14593     };
14594     __IM uint8_t RESERVED27[2];
14595 
14596     union
14597     {
14598         __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
14599 
14600         struct
14601         {
14602             __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
14603             uint8_t                : 5;
14604         } I3CCKDIVCR_b;
14605     };
14606     __IM uint16_t RESERVED28;
14607 
14608     union
14609     {
14610         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
14611 
14612         struct
14613         {
14614             __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
14615             uint8_t                 : 3;
14616             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
14617             __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
14618         } USBCKCR_b;
14619     };
14620     __IM uint8_t RESERVED29;
14621 
14622     union
14623     {
14624         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
14625 
14626         struct
14627         {
14628             __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
14629             uint8_t                   : 3;
14630             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
14631             __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
14632         } CANFDCKCR_b;
14633     };
14634     __IM uint8_t RESERVED30[2];
14635 
14636     union
14637     {
14638         __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */
14639 
14640         struct
14641         {
14642             __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
14643             uint8_t                 : 3;
14644             __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
14645             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
14646         } I3CCKCR_b;
14647     };
14648     __IM uint16_t RESERVED31;
14649     __IM uint32_t RESERVED32[5];
14650     __IM uint16_t RESERVED33;
14651 
14652     union
14653     {
14654         __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
14655 
14656         struct
14657         {
14658             __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
14659                                          *   than in asynchronous mode.                                                */
14660             __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
14661             uint8_t                : 5;
14662             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
14663         } SNZCR_b;
14664     };
14665     __IM uint8_t RESERVED34;
14666 
14667     union
14668     {
14669         __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
14670 
14671         struct
14672         {
14673             __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
14674             __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
14675             __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
14676             __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
14677             __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
14678             uint8_t                 : 2;
14679             __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
14680                                           *   to 1 other than in asynchronous mode.                                     */
14681         } SNZEDCR_b;
14682     };
14683 
14684     union
14685     {
14686         __IOM uint8_t SNZEDCR1;        /*!< (@ 0x00000095) Snooze End Control Register 1                              */
14687 
14688         struct
14689         {
14690             uint8_t                 : 1;
14691             __IOM uint8_t CTSUNAJED : 1; /*!< [1..1] CTSU2SLa non-touch automatic judgment Snooze End Enable            */
14692             uint8_t                 : 6;
14693         } SNZEDCR1_b;
14694     };
14695     __IM uint16_t RESERVED35;
14696 
14697     union
14698     {
14699         __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
14700 
14701         struct
14702         {
14703             __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
14704             __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
14705             __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
14706             __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
14707             __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
14708             __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
14709             __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
14710             __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
14711             __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
14712             __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
14713             __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
14714             __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
14715             __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
14716             __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
14717             __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
14718             __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
14719             uint32_t                  : 7;
14720             __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
14721                                             *   request                                                                   */
14722             __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
14723             __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
14724             uint32_t                  : 2;
14725             __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
14726                                             *   request                                                                   */
14727             __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
14728                                             *   snooze request                                                            */
14729             __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
14730                                             *   snooze request                                                            */
14731             uint32_t : 1;
14732         } SNZREQCR_b;
14733     };
14734     __IM uint16_t RESERVED36;
14735     __IM uint8_t  RESERVED37;
14736 
14737     union
14738     {
14739         __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
14740 
14741         struct
14742         {
14743             __IOM uint8_t PSMC0 : 1;   /*!< [0..0] Power save memory control.                                         */
14744             __IOM uint8_t PSMC1 : 1;   /*!< [1..1] Power save memory control.                                         */
14745             __IOM uint8_t PSMC2 : 1;   /*!< [2..2] Power save memory control.                                         */
14746             __IOM uint8_t PSMC3 : 1;   /*!< [3..3] Power save memory control.                                         */
14747             __IOM uint8_t PSMC4 : 1;   /*!< [4..4] Power save memory control.                                         */
14748             __IOM uint8_t PSMC5 : 1;   /*!< [5..5] Power save memory control.                                         */
14749             uint8_t             : 2;
14750         } PSMCR_b;
14751     };
14752 
14753     union
14754     {
14755         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
14756 
14757         struct
14758         {
14759             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
14760             uint8_t              : 2;
14761             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
14762             uint8_t              : 3;
14763         } OPCCR_b;
14764     };
14765     __IM uint8_t RESERVED38;
14766 
14767     union
14768     {
14769         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
14770 
14771         struct
14772         {
14773             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
14774             uint8_t            : 4;
14775         } MOSCWTCR_b;
14776     };
14777     __IM uint8_t  RESERVED39;
14778     __IM uint32_t RESERVED40;
14779     __IM uint16_t RESERVED41;
14780 
14781     union
14782     {
14783         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
14784 
14785         struct
14786         {
14787             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
14788             uint8_t               : 3;
14789             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
14790             uint8_t               : 3;
14791         } SOPCCR_b;
14792     };
14793     __IM uint8_t RESERVED42;
14794 
14795     union
14796     {
14797         __IOM uint8_t LDOCR;           /*!< (@ 0x000000AC) LDO control register                                       */
14798 
14799         struct
14800         {
14801             __IOM uint8_t CHG0 : 1;    /*!< [0..0] Charge up 0                                                        */
14802             uint8_t            : 7;
14803         } LDOCR_b;
14804     };
14805     __IM uint8_t  RESERVED43;
14806     __IM uint16_t RESERVED44;
14807     __IM uint32_t RESERVED45[4];
14808 
14809     union
14810     {
14811         __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
14812 
14813         struct
14814         {
14815             __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
14816                                         *   only to clear the flag. Confirm the value is 1 and then
14817                                         *   write 0.                                                                  */
14818             __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
14819                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
14820             __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
14821                                         *   the flag. Confirm the value is 1 and then write 0.                        */
14822             uint16_t             : 5;
14823             __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
14824                                         *   to clear the flag. Confirm the value is 1 and then write
14825                                         *   0.                                                                        */
14826             __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
14827                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
14828             uint16_t              : 1;
14829             __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
14830                                         *   to clear the flag. Confirm the value is 1 and then write
14831                                         *   0.                                                                        */
14832             uint16_t             : 1;
14833             __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
14834             uint16_t             : 1;
14835             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
14836         } RSTSR1_b;
14837     };
14838     __IM uint16_t RESERVED46;
14839     __IM uint32_t RESERVED47[3];
14840 
14841     union
14842     {
14843         __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
14844 
14845         struct
14846         {
14847             __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
14848                                           *   (UCLK).                                                                   */
14849             uint8_t : 7;
14850         } USBCKCR_ALT_b;
14851     };
14852     __IM uint8_t  RESERVED48;
14853     __IM uint16_t RESERVED49;
14854     __IM uint32_t RESERVED50[3];
14855 
14856     union
14857     {
14858         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
14859 
14860         struct
14861         {
14862             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
14863             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
14864             uint8_t              : 5;
14865         } LVD1CR1_b;
14866     };
14867 
14868     union
14869     {
14870         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
14871 
14872         struct
14873         {
14874             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
14875                                         *   0 can be written to this bit. After writing 0 to this bit,
14876                                         *   it takes 2 system clock cycles for the bit to be read as
14877                                         *   0.                                                                        */
14878             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
14879             uint8_t          : 6;
14880         } LVD1SR_b;
14881     };
14882 
14883     union
14884     {
14885         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
14886 
14887         struct
14888         {
14889             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
14890             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
14891             uint8_t              : 5;
14892         } LVD2CR1_b;
14893     };
14894 
14895     union
14896     {
14897         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
14898 
14899         struct
14900         {
14901             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
14902                                         *   0 can be written to this bit. After writing 0 to this bit,
14903                                         *   it takes 2 system clock cycles for the bit to be read as
14904                                         *   0.                                                                        */
14905             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
14906             uint8_t          : 6;
14907         } LVD2SR_b;
14908     };
14909     __IM uint32_t RESERVED51[3];
14910 
14911     union
14912     {
14913         __IOM uint8_t SRMPSCR;         /*!< (@ 0x000000F0) SRAM Power State Control Register                          */
14914 
14915         struct
14916         {
14917             __IOM uint8_t SPSC0 : 1;   /*!< [0..0] SRAM Power State Control                                           */
14918             __IOM uint8_t SPSC1 : 1;   /*!< [1..1] SRAM Power State Control                                           */
14919             __IOM uint8_t SPSC2 : 1;   /*!< [2..2] SRAM Power State Control                                           */
14920             __IOM uint8_t SPSC3 : 1;   /*!< [3..3] SRAM Power State Control                                           */
14921             __IOM uint8_t SPSC4 : 1;   /*!< [4..4] SRAM Power State Control                                           */
14922             __IOM uint8_t SPSC5 : 1;   /*!< [5..5] SRAM Power State Control                                           */
14923             uint8_t             : 2;
14924         } SRMPSCR_b;
14925     };
14926     __IM uint8_t  RESERVED52;
14927     __IM uint16_t RESERVED53;
14928     __IM uint32_t RESERVED54[179];
14929 
14930     union
14931     {
14932         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
14933                                           *                  Register                                                   */
14934 
14935         struct
14936         {
14937             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
14938             uint32_t                : 1;
14939             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
14940             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
14941             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
14942             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
14943             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
14944             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
14945             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
14946             uint32_t                : 2;
14947             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
14948             uint32_t                : 4;
14949             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
14950             uint32_t                : 1;
14951             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
14952             uint32_t                : 1;
14953             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
14954             uint32_t                : 5;
14955             __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26                                      */
14956             __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27                                      */
14957             uint32_t                : 4;
14958         } CGFSAR_b;
14959     };
14960 
14961     union
14962     {
14963         __IOM uint32_t RSTSAR;          /*!< (@ 0x000003C4) Reset Security Attribution Register                        */
14964 
14965         struct
14966         {
14967             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
14968             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
14969             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
14970             uint32_t               : 29;
14971         } RSTSAR_b;
14972     };
14973 
14974     union
14975     {
14976         __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
14977 
14978         struct
14979         {
14980             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
14981             uint32_t               : 1;
14982             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
14983             uint32_t               : 1;
14984             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
14985             uint32_t               : 27;
14986         } LPMSAR_b;
14987     };
14988 
14989     union
14990     {
14991         __IOM uint32_t LVDSAR;           /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
14992 
14993         struct
14994         {
14995             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
14996             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
14997             uint32_t                : 6;
14998             __IOM uint32_t NONSEC8  : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
14999             __IOM uint32_t NONSEC9  : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
15000             __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10                                      */
15001             uint32_t                : 21;
15002         } LVDSAR_b;
15003     };
15004     __IM uint32_t RESERVED55[11];
15005     __IM uint16_t RESERVED56;
15006 
15007     union
15008     {
15009         __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
15010 
15011         struct
15012         {
15013             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
15014                                         *   generation circuit.                                                       */
15015             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
15016                                         *   modes, the low power consumption modes and the battery
15017                                         *   backup function.                                                          */
15018             uint16_t            : 1;
15019             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
15020             __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
15021             uint16_t            : 3;
15022             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
15023         } PRCR_b;
15024     };
15025     __IM uint32_t RESERVED57[3];
15026     __IM uint16_t RESERVED58;
15027 
15028     union
15029     {
15030         __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
15031 
15032         struct
15033         {
15034             uint8_t             : 7;
15035             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
15036         } SYOCDCR_b;
15037     };
15038     __IM uint8_t RESERVED59;
15039 
15040     union
15041     {
15042         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
15043 
15044         struct
15045         {
15046             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
15047                                         *   the flag. Confirm the value is 1 and then write 0.                        */
15048             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
15049                                         *   to clear the flag. Confirm the value is 1 and then write
15050                                         *   0.                                                                        */
15051             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
15052                                         *   to clear the flag. Confirm the value is 1 and then write
15053                                         *   0.                                                                        */
15054             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
15055                                         *   to clear the flag. Confirm the value is 1 and then write
15056                                         *   0.                                                                        */
15057             uint8_t : 4;
15058         } RSTSR0_b;
15059     };
15060 
15061     union
15062     {
15063         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
15064 
15065         struct
15066         {
15067             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
15068             uint8_t            : 7;
15069         } RSTSR2_b;
15070     };
15071     __IM uint8_t RESERVED60;
15072 
15073     union
15074     {
15075         __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
15076                                         *                  Register                                                   */
15077 
15078         struct
15079         {
15080             uint8_t              : 3;
15081             __IOM uint8_t MODRV1 : 1;  /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
15082             uint8_t              : 2;
15083             __IOM uint8_t MOSEL  : 1;  /*!< [6..6] Main Clock Oscillator Switching                                    */
15084             uint8_t              : 1;
15085         } MOMCR_b;
15086     };
15087     __IM uint16_t RESERVED61;
15088     __IM uint8_t  RESERVED62;
15089 
15090     union
15091     {
15092         union
15093         {
15094             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
15095 
15096             struct
15097             {
15098                 uint8_t             : 5;
15099                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
15100                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
15101                 uint8_t             : 1;
15102             } LVCMPCR_b;
15103         };
15104 
15105         union
15106         {
15107             __IOM uint8_t LVD1CMPCR;      /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
15108 
15109             struct
15110             {
15111                 __IOM uint8_t LVDLVL : 4; /*!< [3..0] Voltage Detection 1 Level Select (Standard voltage during
15112                                            *   drop in voltage)                                                          */
15113                 uint8_t            : 3;
15114                 __IOM uint8_t LVDE : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
15115             } LVD1CMPCR_b;
15116         };
15117     };
15118 
15119     union
15120     {
15121         __IOM uint8_t LVD2CMPCR;         /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
15122 
15123         struct
15124         {
15125             __IOM uint8_t LVDLVL : 3;    /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
15126                                           *   drop in voltage)                                                          */
15127             uint8_t                 : 3;
15128             __IOM uint8_t EXVCCINP2 : 1; /*!< [6..6] Voltage Detection 2 Comparison (Voltage external input
15129                                           *   select)                                                                   */
15130             __IOM uint8_t LVDE : 1;      /*!< [7..7] Voltage Detection 2 Enable                                         */
15131         } LVD2CMPCR_b;
15132     };
15133     __IM uint8_t RESERVED63;
15134 
15135     union
15136     {
15137         __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
15138 
15139         struct
15140         {
15141             __IOM uint8_t RIE  : 1;    /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
15142             uint8_t            : 1;
15143             __IOM uint8_t CMPE : 1;    /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
15144             uint8_t            : 3;
15145             __IOM uint8_t RI   : 1;    /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
15146             __IOM uint8_t RN   : 1;    /*!< [7..7] Voltage Monitor Reset Negate Select                                */
15147         } LVD1CR0_b;
15148     };
15149 
15150     union
15151     {
15152         __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
15153 
15154         struct
15155         {
15156             __IOM uint8_t RIE  : 1;    /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
15157             uint8_t            : 1;
15158             __IOM uint8_t CMPE : 1;    /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
15159             uint8_t            : 3;
15160             __IOM uint8_t RI   : 1;    /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
15161             __IOM uint8_t RN   : 1;    /*!< [7..7] Voltage Monitor Reset Negate Select                                */
15162         } LVD2CR0_b;
15163     };
15164     __IM uint32_t RESERVED64[25];
15165 
15166     union
15167     {
15168         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
15169 
15170         struct
15171         {
15172             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
15173             uint8_t             : 7;
15174         } SOSCCR_b;
15175     };
15176 
15177     union
15178     {
15179         __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
15180 
15181         struct
15182         {
15183             __IOM uint8_t SODRV  : 2;  /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
15184             uint8_t              : 2;
15185             __IOM uint8_t EXCLKS : 1;  /*!< [4..4] Sub Clock Oscillator Mode Function Switching                       */
15186             uint8_t              : 3;
15187         } SOMCR_b;
15188     };
15189 
15190     union
15191     {
15192         __IOM uint8_t SOMRG;           /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register                 */
15193 
15194         struct
15195         {
15196             __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching                        */
15197             uint8_t               : 6;
15198         } SOMRG_b;
15199     };
15200     __IM uint8_t  RESERVED65;
15201     __IM uint32_t RESERVED66[3];
15202 
15203     union
15204     {
15205         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
15206 
15207         struct
15208         {
15209             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
15210             uint8_t             : 7;
15211         } LOCOCR_b;
15212     };
15213     __IM uint8_t RESERVED67;
15214 
15215     union
15216     {
15217         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
15218 
15219         struct
15220         {
15221             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
15222                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
15223                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
15224                                          +126 0111_1111 : +127These bits are added to original LOCO
15225                                          *   trimming bits                                                             */
15226         } LOCOUTCR_b;
15227     };
15228     __IM uint8_t  RESERVED68;
15229     __IM uint32_t RESERVED69[11];
15230 
15231     union
15232     {
15233         __IOM uint8_t VBTLVDCR;        /*!< (@ 0x000004C0) EXLVDVBAT Circuit Control Register                         */
15234 
15235         struct
15236         {
15237             uint8_t            : 4;
15238             __IOM uint8_t LVDE : 1;    /*!< [4..4] EXLVDVBAT Pin Low Voltage Detect Enable                            */
15239             __IOM uint8_t LVL  : 3;    /*!< [7..5] EXLVDVBAT Pin Low Voltage Detect Level Select                      */
15240         } VBTLVDCR_b;
15241     };
15242 
15243     union
15244     {
15245         __IOM uint8_t VBTLVDSR;        /*!< (@ 0x000004C1) EXLVDVBAT Circuit Status Register                          */
15246 
15247         struct
15248         {
15249             uint8_t           : 1;
15250             __IOM uint8_t DET : 1;     /*!< [1..1] EXLVDVBAT Pin Low Voltage Detect Flag                              */
15251             uint8_t           : 3;
15252             __IM uint8_t MON  : 1;     /*!< [5..5] EXLVDVBAT Pin Low Voltage Monitor Flag                             */
15253             uint8_t           : 2;
15254         } VBTLVDSR_b;
15255     };
15256 
15257     union
15258     {
15259         __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004C2) EXLVDVBAT Comparator Control Register                      */
15260 
15261         struct
15262         {
15263             __IOM uint8_t CMPE : 1;    /*!< [0..0] EXLVDVBAT Pin Low Voltage Detect Circuit Output Enable             */
15264             uint8_t            : 7;
15265         } VBTCMPCR_b;
15266     };
15267 
15268     union
15269     {
15270         __IOM uint8_t VBTLVDICR;       /*!< (@ 0x000004C3) EXLVDVBAT Pin Low Voltage Detect Interrupt Control
15271                                         *                  Register                                                   */
15272 
15273         struct
15274         {
15275             __IOM uint8_t IE     : 1;  /*!< [0..0] EXLVDVBAT Pin Low Voltage Detect Interrupt Enable                  */
15276             uint8_t              : 3;
15277             __IOM uint8_t IDTSEL : 2;  /*!< [5..4] EXLVDVBAT Pin Low Voltage Detect Interrupt Generation
15278                                         *   Condition Select                                                          */
15279             uint8_t : 2;
15280         } VBTLVDICR_b;
15281     };
15282 
15283     union
15284     {
15285         __IOM uint8_t VRTLVDCR;        /*!< (@ 0x000004C4) LVDVRTC Circuit Control Register                           */
15286 
15287         struct
15288         {
15289             uint8_t            : 4;
15290             __IOM uint8_t LVDE : 1;    /*!< [4..4] VRTC Pin Low Voltage Detect Enable                                 */
15291             __IOM uint8_t LVL  : 3;    /*!< [7..5] VRTC Pin Low Voltage Detect Level Select                           */
15292         } VRTLVDCR_b;
15293     };
15294 
15295     union
15296     {
15297         __IOM uint8_t VRTSR;           /*!< (@ 0x000004C5) VRTC Status Register                                       */
15298 
15299         struct
15300         {
15301             __IOM uint8_t PORDET : 1;  /*!< [0..0] VRTC-domain Power-on Reset Detect Flag                             */
15302             __IOM uint8_t DET    : 1;  /*!< [1..1] VRTC Voltage Variation Detection Flag                              */
15303             uint8_t              : 2;
15304             __IM uint8_t VRTVLD  : 1;  /*!< [4..4] VRTC-domain Valid                                                  */
15305             __IM uint8_t MON     : 1;  /*!< [5..5] VRTC Signal Monitor Flag                                           */
15306             uint8_t              : 2;
15307         } VRTSR_b;
15308     };
15309 
15310     union
15311     {
15312         __IOM uint8_t VRTCMPCR;        /*!< (@ 0x000004C6) VRTC Comparator Control Register                           */
15313 
15314         struct
15315         {
15316             __IOM uint8_t CMPE : 1;    /*!< [0..0] VRTC Pin Low Voltage Detect Circuit Output Enable                  */
15317             uint8_t            : 7;
15318         } VRTCMPCR_b;
15319     };
15320 
15321     union
15322     {
15323         __IOM uint8_t VRTLVDICR;       /*!< (@ 0x000004C7) VRTC Pin Low Voltage Detect Interrupt Control
15324                                         *                  Register                                                   */
15325 
15326         struct
15327         {
15328             __IOM uint8_t IE     : 1;  /*!< [0..0] VRTC Pin Low Voltage Detect Interrupt Enable                       */
15329             uint8_t              : 3;
15330             __IOM uint8_t IDTSEL : 2;  /*!< [5..4] VRTC Pin Low Voltage Detect Interrupt Generation Condition
15331                                         *   Select                                                                    */
15332             uint8_t : 2;
15333         } VRTLVDICR_b;
15334     };
15335 
15336     union
15337     {
15338         __IOM uint8_t EXLVDCR;         /*!< (@ 0x000004C8) EXLVD Circuit Control Register                             */
15339 
15340         struct
15341         {
15342             uint8_t            : 4;
15343             __IOM uint8_t LVDE : 1;    /*!< [4..4] EXLVD Pin Low Voltage Detect Enable                                */
15344             uint8_t            : 3;
15345         } EXLVDCR_b;
15346     };
15347 
15348     union
15349     {
15350         __IOM uint8_t EXLVDSR;         /*!< (@ 0x000004C9) EXLVD Circuit Status Register                              */
15351 
15352         struct
15353         {
15354             uint8_t           : 1;
15355             __IOM uint8_t DET : 1;     /*!< [1..1] EXLVD pin Low Voltage Detect Flag                                  */
15356             uint8_t           : 3;
15357             __IM uint8_t MON  : 1;     /*!< [5..5] EXLVD pin Low Voltage Monitor Flag                                 */
15358             uint8_t           : 2;
15359         } EXLVDSR_b;
15360     };
15361 
15362     union
15363     {
15364         __IOM uint8_t EXLVDCMPCR;      /*!< (@ 0x000004CA) EXLVD Comparator Control Register                          */
15365 
15366         struct
15367         {
15368             __IOM uint8_t CMPE : 1;    /*!< [0..0] EXLVD Pin Low Voltage Detect Circuit Output Enable                 */
15369             uint8_t            : 7;
15370         } EXLVDCMPCR_b;
15371     };
15372 
15373     union
15374     {
15375         __IOM uint8_t EXLVDICR;        /*!< (@ 0x000004CB) EXLVD Pin Low Voltage Detect Interrupt Control
15376                                         *                  Register                                                   */
15377 
15378         struct
15379         {
15380             __IOM uint8_t IE     : 1;  /*!< [0..0] EXLVD Pin Low Voltage Detect Interrupt Enable                      */
15381             uint8_t              : 3;
15382             __IOM uint8_t IDTSEL : 2;  /*!< [5..4] EXLVD Pin Low Voltage Detect Interrupt Generation Condition
15383                                         *   Select                                                                    */
15384             uint8_t : 2;
15385         } EXLVDICR_b;
15386     };
15387 } R_SYSTEM_Type;                       /*!< Size = 1228 (0x4cc)                                                       */
15388 
15389 /* =========================================================================================================================== */
15390 /* ================                                           R_TSN                                           ================ */
15391 /* =========================================================================================================================== */
15392 
15393 /**
15394  * @brief Temperature Sensor (R_TSN)
15395  */
15396 
15397 typedef struct                         /*!< (@ 0x407EC000) R_TSN Structure                                            */
15398 {
15399     __IM uint16_t RESERVED[276];
15400 
15401     union
15402     {
15403         __IM uint16_t TSCDR;           /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register               */
15404 
15405         struct
15406         {
15407             union
15408             {
15409                 __IM uint8_t TSCDRL;         /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register
15410                                               *                  L                                                          */
15411 
15412                 struct
15413                 {
15414                     __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */
15415                 } TSCDRL_b;
15416             };
15417 
15418             union
15419             {
15420                 __IM uint8_t TSCDRH;         /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register
15421                                               *                  H                                                          */
15422 
15423                 struct
15424                 {
15425                     __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the
15426                                               *   convertedvalue.                                                           */
15427                 } TSCDRH_b;
15428             };
15429         };
15430     };
15431     __IM uint16_t TSCDRR;              /*!< (@ 0x0000022A) Temperature Sensor Calibration Data Register
15432                                         *                  (Room Temperature)                                         */
15433 } R_TSN_Type;                          /*!< Size = 556 (0x22c)                                                        */
15434 
15435 /* =========================================================================================================================== */
15436 /* ================                                         R_USB_FS0                                         ================ */
15437 /* =========================================================================================================================== */
15438 
15439 /**
15440  * @brief USB 2.0 Module (R_USB_FS0)
15441  */
15442 
15443 typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
15444 {
15445     union
15446     {
15447         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
15448 
15449         struct
15450         {
15451             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
15452             uint16_t             : 2;
15453             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
15454             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
15455             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
15456             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
15457             uint16_t             : 1;
15458             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
15459             uint16_t             : 1;
15460             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
15461             uint16_t             : 5;
15462         } SYSCFG_b;
15463     };
15464 
15465     union
15466     {
15467         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
15468 
15469         struct
15470         {
15471             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
15472                                         *   access cycles)                                                            */
15473             uint16_t : 12;
15474         } BUSWAIT_b;
15475     };
15476 
15477     union
15478     {
15479         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
15480 
15481         struct
15482         {
15483             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
15484             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
15485             uint16_t            : 2;
15486             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
15487                                         *   Selected.                                                                 */
15488             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
15489             uint16_t             : 7;
15490             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
15491                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
15492                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
15493                                         *   pin.                                                                      */
15494         } SYSSTS0_b;
15495     };
15496 
15497     union
15498     {
15499         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
15500 
15501         struct
15502         {
15503             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
15504             uint16_t              : 15;
15505         } PLLSTA_b;
15506     };
15507 
15508     union
15509     {
15510         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
15511 
15512         struct
15513         {
15514             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
15515             uint16_t               : 1;
15516             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
15517             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
15518             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
15519             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
15520             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
15521             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
15522             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
15523             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
15524                                          *   used when switching from device B to device A while in
15525                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
15526                                          *   control keeps the suspended state until the HNP processing
15527                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
15528                                          *   set.                                                                      */
15529             uint16_t : 4;
15530         } DVSTCTR0_b;
15531     };
15532     __IM uint16_t RESERVED;
15533 
15534     union
15535     {
15536         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
15537 
15538         struct
15539         {
15540             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
15541             uint16_t            : 12;
15542         } TESTMODE_b;
15543     };
15544     __IM uint16_t RESERVED1;
15545     __IM uint32_t RESERVED2;
15546 
15547     union
15548     {
15549         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
15550 
15551         struct
15552         {
15553             union
15554             {
15555                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
15556                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
15557             };
15558 
15559             union
15560             {
15561                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
15562 
15563                 struct
15564                 {
15565                     __IM uint8_t  RESERVED3;
15566                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
15567                 };
15568             };
15569         };
15570     };
15571 
15572     union
15573     {
15574         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
15575 
15576         struct
15577         {
15578             union
15579             {
15580                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
15581                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
15582             };
15583 
15584             union
15585             {
15586                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
15587 
15588                 struct
15589                 {
15590                     __IM uint8_t  RESERVED4;
15591                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
15592                 };
15593             };
15594         };
15595     };
15596 
15597     union
15598     {
15599         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
15600 
15601         struct
15602         {
15603             union
15604             {
15605                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
15606                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
15607             };
15608 
15609             union
15610             {
15611                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
15612 
15613                 struct
15614                 {
15615                     __IM uint8_t  RESERVED5;
15616                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
15617                 };
15618             };
15619         };
15620     };
15621 
15622     union
15623     {
15624         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
15625 
15626         struct
15627         {
15628             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
15629             uint16_t               : 1;
15630             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
15631             uint16_t               : 2;
15632             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
15633             uint16_t               : 1;
15634             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
15635             uint16_t               : 2;
15636             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
15637             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
15638         } CFIFOSEL_b;
15639     };
15640 
15641     union
15642     {
15643         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
15644 
15645         struct
15646         {
15647             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
15648                                         *   data.                                                                     */
15649             uint16_t            : 1;
15650             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
15651             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
15652             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
15653         } CFIFOCTR_b;
15654     };
15655     __IM uint32_t RESERVED6;
15656 
15657     union
15658     {
15659         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
15660 
15661         struct
15662         {
15663             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
15664             uint16_t               : 4;
15665             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
15666             uint16_t               : 1;
15667             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
15668             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
15669             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
15670                                          *   Pipe Data is Read                                                         */
15671             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
15672             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
15673         } D0FIFOSEL_b;
15674     };
15675 
15676     union
15677     {
15678         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
15679 
15680         struct
15681         {
15682             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
15683                                         *   data.                                                                     */
15684             uint16_t            : 1;
15685             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
15686             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
15687             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
15688         } D0FIFOCTR_b;
15689     };
15690 
15691     union
15692     {
15693         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
15694 
15695         struct
15696         {
15697             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
15698             uint16_t               : 4;
15699             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
15700             uint16_t               : 1;
15701             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
15702             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
15703             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
15704                                          *   Pipe Data is Read                                                         */
15705             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
15706             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
15707         } D1FIFOSEL_b;
15708     };
15709 
15710     union
15711     {
15712         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
15713 
15714         struct
15715         {
15716             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
15717                                         *   data.                                                                     */
15718             uint16_t            : 1;
15719             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
15720             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
15721             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
15722         } D1FIFOCTR_b;
15723     };
15724 
15725     union
15726     {
15727         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
15728 
15729         struct
15730         {
15731             uint16_t             : 8;
15732             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
15733             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
15734             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
15735             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
15736             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
15737             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
15738             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
15739             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
15740         } INTENB0_b;
15741     };
15742 
15743     union
15744     {
15745         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
15746 
15747         struct
15748         {
15749             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
15750             uint16_t                  : 3;
15751             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
15752             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
15753             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
15754             uint16_t                  : 4;
15755             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
15756             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
15757             uint16_t                  : 1;
15758             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
15759             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
15760         } INTENB1_b;
15761     };
15762     __IM uint16_t RESERVED7;
15763 
15764     union
15765     {
15766         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
15767 
15768         struct
15769         {
15770             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
15771             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
15772             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
15773             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
15774             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
15775             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
15776             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
15777             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
15778             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
15779             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
15780             uint16_t                  : 6;
15781         } BRDYENB_b;
15782     };
15783 
15784     union
15785     {
15786         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
15787 
15788         struct
15789         {
15790             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
15791             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
15792             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
15793             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
15794             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
15795             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
15796             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
15797             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
15798             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
15799             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
15800             uint16_t                  : 6;
15801         } NRDYENB_b;
15802     };
15803 
15804     union
15805     {
15806         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
15807 
15808         struct
15809         {
15810             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
15811             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
15812             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
15813             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
15814             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
15815             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
15816             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
15817             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
15818             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
15819             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
15820             uint16_t                  : 6;
15821         } BEMPENB_b;
15822     };
15823 
15824     union
15825     {
15826         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
15827 
15828         struct
15829         {
15830             uint16_t                : 4;
15831             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
15832             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
15833             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
15834             uint16_t                : 1;
15835             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
15836             uint16_t                : 7;
15837         } SOFCFG_b;
15838     };
15839 
15840     union
15841     {
15842         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
15843 
15844         struct
15845         {
15846             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
15847             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
15848             uint16_t                : 1;
15849             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
15850             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
15851             uint16_t                : 2;
15852             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
15853             uint16_t                : 1;
15854             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
15855             uint16_t                : 3;
15856             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
15857         } PHYSET_b;
15858     };
15859 
15860     union
15861     {
15862         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
15863 
15864         struct
15865         {
15866             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
15867             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
15868             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
15869             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
15870             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
15871             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
15872             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
15873             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
15874             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
15875             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
15876             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
15877             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
15878         } INTSTS0_b;
15879     };
15880 
15881     union
15882     {
15883         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
15884 
15885         struct
15886         {
15887             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
15888             uint16_t                 : 3;
15889             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
15890             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
15891             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
15892             uint16_t                 : 1;
15893             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
15894             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
15895             uint16_t                 : 1;
15896             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
15897             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
15898             uint16_t                 : 1;
15899             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
15900             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
15901         } INTSTS1_b;
15902     };
15903     __IM uint16_t RESERVED8;
15904 
15905     union
15906     {
15907         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
15908 
15909         struct
15910         {
15911             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
15912             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
15913             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
15914             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
15915             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
15916             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
15917             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
15918             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
15919             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
15920             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
15921             uint16_t                 : 6;
15922         } BRDYSTS_b;
15923     };
15924 
15925     union
15926     {
15927         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
15928 
15929         struct
15930         {
15931             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
15932             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
15933             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
15934             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
15935             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
15936             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
15937             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
15938             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
15939             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
15940             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
15941             uint16_t                 : 6;
15942         } NRDYSTS_b;
15943     };
15944 
15945     union
15946     {
15947         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
15948 
15949         struct
15950         {
15951             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
15952             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
15953             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
15954             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
15955             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
15956             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
15957             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
15958             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
15959             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
15960             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
15961             uint16_t                 : 6;
15962         } BEMPSTS_b;
15963     };
15964 
15965     union
15966     {
15967         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
15968 
15969         struct
15970         {
15971             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
15972             uint16_t            : 3;
15973             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
15974             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
15975         } FRMNUM_b;
15976     };
15977 
15978     union
15979     {
15980         __IOM uint16_t DVCHGR;         /*!< (@ 0x0000004E) Device State Change Register                               */
15981 
15982         struct
15983         {
15984             uint16_t             : 15;
15985             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
15986         } DVCHGR_b;
15987     };
15988 
15989     union
15990     {
15991         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
15992 
15993         struct
15994         {
15995             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
15996                                            *   the USB address assigned by the host when the USBHS processed
15997                                            *   the SET_ADDRESS request successfully.                                     */
15998             uint16_t                 : 1;
15999             __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery                                                   */
16000             uint16_t                 : 4;
16001         } USBADDR_b;
16002     };
16003     __IM uint16_t RESERVED9;
16004 
16005     union
16006     {
16007         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
16008 
16009         struct
16010         {
16011             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
16012                                                *   value.                                                                    */
16013             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
16014         } USBREQ_b;
16015     };
16016 
16017     union
16018     {
16019         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
16020 
16021         struct
16022         {
16023             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
16024         } USBVAL_b;
16025     };
16026 
16027     union
16028     {
16029         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
16030 
16031         struct
16032         {
16033             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
16034         } USBINDX_b;
16035     };
16036 
16037     union
16038     {
16039         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
16040 
16041         struct
16042         {
16043             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
16044         } USBLENG_b;
16045     };
16046 
16047     union
16048     {
16049         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
16050 
16051         struct
16052         {
16053             uint16_t              : 4;
16054             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
16055             uint16_t              : 2;
16056             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
16057             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
16058             uint16_t              : 7;
16059         } DCPCFG_b;
16060     };
16061 
16062     union
16063     {
16064         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
16065 
16066         struct
16067         {
16068             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
16069                                         *   of data (maximum packet size) in payloads for the DCP.                    */
16070             uint16_t              : 5;
16071             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
16072         } DCPMAXP_b;
16073     };
16074 
16075     union
16076     {
16077         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
16078 
16079         struct
16080         {
16081             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
16082             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
16083             uint16_t                : 2;
16084             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
16085             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
16086             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
16087             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
16088             uint16_t                : 2;
16089             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
16090             uint16_t                : 2;
16091             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
16092             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
16093         } DCPCTR_b;
16094     };
16095     __IM uint16_t RESERVED10;
16096 
16097     union
16098     {
16099         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
16100 
16101         struct
16102         {
16103             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
16104             uint16_t               : 12;
16105         } PIPESEL_b;
16106     };
16107     __IM uint16_t RESERVED11;
16108 
16109     union
16110     {
16111         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
16112 
16113         struct
16114         {
16115             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
16116                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
16117             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
16118             uint16_t              : 2;
16119             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
16120             uint16_t              : 1;
16121             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
16122             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
16123             uint16_t              : 3;
16124             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
16125         } PIPECFG_b;
16126     };
16127     __IM uint16_t RESERVED12;
16128 
16129     union
16130     {
16131         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
16132 
16133         struct
16134         {
16135             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
16136                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
16137                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
16138                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
16139                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
16140             uint16_t              : 3;
16141             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
16142         } PIPEMAXP_b;
16143     };
16144 
16145     union
16146     {
16147         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
16148 
16149         struct
16150         {
16151             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
16152                                         *   error detection timing for the selected pipe in terms of
16153                                         *   frames, which is expressed as nth power of 2.                             */
16154             uint16_t            : 9;
16155             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
16156             uint16_t            : 3;
16157         } PIPEPERI_b;
16158     };
16159 
16160     union
16161     {
16162         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
16163 
16164         struct
16165         {
16166             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
16167             uint16_t              : 3;
16168             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
16169             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
16170             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
16171             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
16172             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
16173             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
16174             uint16_t              : 1;
16175             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
16176                                         *   Split Transaction of the relevant pipe                                    */
16177             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
16178                                         *   the CSSTS bit of the relevant pipe                                        */
16179             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
16180             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
16181         } PIPE_CTR_b[9];
16182     };
16183     __IM uint16_t                RESERVED13;
16184     __IM uint32_t                RESERVED14[3];
16185     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
16186     __IM uint32_t                RESERVED15[3];
16187 
16188     union
16189     {
16190         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
16191 
16192         struct
16193         {
16194             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
16195             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
16196             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
16197             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
16198             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
16199             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
16200             uint16_t                  : 1;
16201             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
16202             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
16203             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
16204             uint16_t                  : 6;
16205         } USBBCCTRL0_b;
16206     };
16207     __IM uint16_t RESERVED16;
16208     __IM uint32_t RESERVED17[4];
16209 
16210     union
16211     {
16212         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
16213 
16214         struct
16215         {
16216             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
16217             uint16_t               : 15;
16218         } UCKSEL_b;
16219     };
16220     __IM uint16_t RESERVED18;
16221     __IM uint32_t RESERVED19;
16222 
16223     union
16224     {
16225         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
16226 
16227         struct
16228         {
16229             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
16230             uint16_t               : 6;
16231             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
16232             uint16_t               : 8;
16233         } USBMC_b;
16234     };
16235     __IM uint16_t RESERVED20;
16236 
16237     union
16238     {
16239         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
16240 
16241         struct
16242         {
16243             uint16_t               : 6;
16244             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
16245             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
16246             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
16247             uint16_t               : 1;
16248         } DEVADD_b[10];
16249     };
16250     __IM uint32_t RESERVED21[3];
16251 
16252     union
16253     {
16254         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
16255 
16256         struct
16257         {
16258             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
16259             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
16260             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
16261             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
16262             uint32_t               : 28;
16263         } PHYSLEW_b;
16264     };
16265     __IM uint32_t RESERVED22[3];
16266 
16267     union
16268     {
16269         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
16270 
16271         struct
16272         {
16273             uint16_t             : 7;
16274             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
16275             uint16_t             : 8;
16276         } LPCTRL_b;
16277     };
16278 
16279     union
16280     {
16281         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
16282 
16283         struct
16284         {
16285             uint16_t                : 14;
16286             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
16287             uint16_t                : 1;
16288         } LPSTS_b;
16289     };
16290     __IM uint32_t RESERVED23[15];
16291 
16292     union
16293     {
16294         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
16295 
16296         struct
16297         {
16298             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
16299             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
16300             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
16301             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
16302             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
16303             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
16304             uint16_t                : 2;
16305             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
16306             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
16307             uint16_t                : 6;
16308         } BCCTRL_b;
16309     };
16310     __IM uint16_t RESERVED24;
16311 
16312     union
16313     {
16314         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
16315 
16316         struct
16317         {
16318             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
16319             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
16320             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
16321                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
16322             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
16323                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
16324             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
16325                                           *   value used for L1NEGOMD.The format is the same as the HIRD
16326                                           *   field in HL1CTRL.                                                         */
16327             uint16_t               : 2;
16328             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
16329             uint16_t               : 1;
16330         } PL1CTRL1_b;
16331     };
16332 
16333     union
16334     {
16335         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
16336 
16337         struct
16338         {
16339             uint16_t               : 8;
16340             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
16341             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
16342             uint16_t               : 3;
16343         } PL1CTRL2_b;
16344     };
16345 
16346     union
16347     {
16348         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
16349 
16350         struct
16351         {
16352             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
16353             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
16354             uint16_t                : 13;
16355         } HL1CTRL1_b;
16356     };
16357 
16358     union
16359     {
16360         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
16361 
16362         struct
16363         {
16364             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
16365                                         *   be set in the ADDR field of LPM token.                                    */
16366             uint16_t             : 4;
16367             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
16368             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
16369                                         *   value to be set in the RWE field of LPM token.                            */
16370             uint16_t            : 2;
16371             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
16372                                         *   period at the time of L1 Resume.                                          */
16373         } HL1CTRL2_b;
16374     };
16375     __IM uint32_t RESERVED25[5];
16376 
16377     union
16378     {
16379         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
16380                                         *                  Register                                                   */
16381 
16382         struct
16383         {
16384             uint32_t              : 20;
16385             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
16386                                          *   HS side of USB port.                                                      */
16387             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
16388                                          *   HS side of USB port.                                                      */
16389             uint32_t               : 1;
16390             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
16391                                          *   of USB port.                                                              */
16392             uint32_t : 8;
16393         } DPUSR0R_b;
16394     };
16395 
16396     union
16397     {
16398         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
16399 
16400         struct
16401         {
16402             uint32_t                : 4;
16403             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
16404             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
16405             uint32_t                : 1;
16406             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
16407             uint32_t                : 12;
16408             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
16409             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
16410             uint32_t                : 1;
16411             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
16412             uint32_t                : 8;
16413         } DPUSR1R_b;
16414     };
16415 
16416     union
16417     {
16418         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
16419 
16420         struct
16421         {
16422             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
16423             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
16424             uint16_t            : 2;
16425             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
16426                                         *   port.                                                                     */
16427             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
16428                                         *   port.                                                                     */
16429             uint16_t              : 2;
16430             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
16431             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
16432             uint16_t              : 6;
16433         } DPUSR2R_b;
16434     };
16435 
16436     union
16437     {
16438         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
16439 
16440         struct
16441         {
16442             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
16443             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
16444             uint16_t                : 14;
16445         } DPUSRCR_b;
16446     };
16447     __IM uint32_t RESERVED26[165];
16448 
16449     union
16450     {
16451         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
16452                                          *                  Monitor Register                                           */
16453 
16454         struct
16455         {
16456             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
16457             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
16458             uint32_t               : 1;
16459             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
16460             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
16461             uint32_t               : 11;
16462             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
16463             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
16464             uint32_t               : 2;
16465             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
16466                                          *   of the USB.                                                               */
16467             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
16468                                          *   of the USB.                                                               */
16469             uint32_t              : 1;
16470             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
16471                                          *   USB.                                                                      */
16472             uint32_t : 8;
16473         } DPUSR0R_FS_b;
16474     };
16475 
16476     union
16477     {
16478         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
16479                                            *                  Register                                                   */
16480 
16481         struct
16482         {
16483             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
16484             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
16485             uint32_t                 : 2;
16486             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
16487             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
16488             uint32_t                 : 1;
16489             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
16490             uint32_t                 : 8;
16491             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
16492             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
16493             uint32_t                 : 2;
16494             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
16495             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
16496             uint32_t                 : 1;
16497             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
16498             uint32_t                 : 8;
16499         } DPUSR1R_FS_b;
16500     };
16501 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
16502 
16503 /* =========================================================================================================================== */
16504 /* ================                                         R_UARTA0                                          ================ */
16505 /* =========================================================================================================================== */
16506 
16507 /**
16508  * @brief Serial Interface UARTA (R_UARTA0)
16509  */
16510 
16511 typedef struct                         /*!< (@ 0x40097000) R_UARTA0 Structure                                         */
16512 {
16513     __IOM uint8_t TXBAn;               /*!< (@ 0x00000000) Transmit Buffer Register 0                                 */
16514     __IM uint8_t  RXBAn;               /*!< (@ 0x00000001) Receive Buffer Register 0                                  */
16515 
16516     union
16517     {
16518         __IOM uint8_t ASIMAn0;         /*!< (@ 0x00000002) Operation Mode Setting Register 00                         */
16519 
16520         struct
16521         {
16522             __IOM uint8_t ISRMA : 1;   /*!< [0..0] Receive Interrupt Mode Select                                      */
16523             __IOM uint8_t ISSMA : 1;   /*!< [1..1] Transmit Interrupt Mode Select                                     */
16524             uint8_t             : 3;
16525             __IOM uint8_t RXEA  : 1;   /*!< [5..5] Reception Enable                                                   */
16526             __IOM uint8_t TXEA  : 1;   /*!< [6..6] Transmission Enable                                                */
16527             __IOM uint8_t EN    : 1;   /*!< [7..7] UART Operation Enable                                              */
16528         } ASIMAn0_b;
16529     };
16530 
16531     union
16532     {
16533         __IOM uint8_t ASIMAn1;         /*!< (@ 0x00000003) Operation Mode Setting Register 01                         */
16534 
16535         struct
16536         {
16537             __IOM uint8_t ALV : 1;     /*!< [0..0] Transmission and Reception Level Setting                           */
16538             __IOM uint8_t DIR : 1;     /*!< [1..1] Transmission and Reception Order Setting                           */
16539             __IOM uint8_t SL  : 1;     /*!< [2..2] Transmission Stop Bit Length Setting                               */
16540             __IOM uint8_t CL  : 2;     /*!< [4..3] Transmission and Reception Character Length Setting                */
16541             __IOM uint8_t PS  : 2;     /*!< [6..5] Transmission and Reception Parity Bit Setting                      */
16542             uint8_t           : 1;
16543         } ASIMAn1_b;
16544     };
16545     __IOM uint8_t BRGCAn;              /*!< (@ 0x00000004) Baud Rate Generator Control Register 0                     */
16546 
16547     union
16548     {
16549         __IM uint8_t ASISAn;           /*!< (@ 0x00000005) Status Register 0                                          */
16550 
16551         struct
16552         {
16553             __IM uint8_t OVEA  : 1;    /*!< [0..0] Overrun Error Flag                                                 */
16554             __IM uint8_t FEA   : 1;    /*!< [1..1] Framing Error Flag                                                 */
16555             __IM uint8_t PEA   : 1;    /*!< [2..2] Parity Error Flag                                                  */
16556             uint8_t            : 1;
16557             __IM uint8_t TXSFA : 1;    /*!< [4..4] Transmit Shift Register Data Flag                                  */
16558             __IM uint8_t TXBFA : 1;    /*!< [5..5] Transmit Buffer Data Flag                                          */
16559             uint8_t            : 2;
16560         } ASISAn_b;
16561     };
16562 
16563     union
16564     {
16565         __IOM uint8_t ASCTAn;          /*!< (@ 0x00000006) Status Clear Trigger Register 0                            */
16566 
16567         struct
16568         {
16569             __IOM uint8_t OVECTA : 1;  /*!< [0..0] Overrun Error Flag Clear Trigger                                   */
16570             __IOM uint8_t FECTA  : 1;  /*!< [1..1] Framing Error Flag Clear Trigger                                   */
16571             __IOM uint8_t PECTA  : 1;  /*!< [2..2] Parity Error Flag Clear Trigger                                    */
16572             uint8_t              : 5;
16573         } ASCTAn_b;
16574     };
16575 } R_UARTA0_Type;                       /*!< Size = 7 (0x7)                                                            */
16576 
16577 /* =========================================================================================================================== */
16578 /* ================                                        R_UARTA_CK                                         ================ */
16579 /* =========================================================================================================================== */
16580 
16581 /**
16582  * @brief Serial Interface UARTA Clock (R_UARTA_CK)
16583  */
16584 
16585 typedef struct                         /*!< (@ 0x40097010) R_UARTA_CK Structure                                       */
16586 {
16587     union
16588     {
16589         __IOM uint8_t UTAnCK[2];       /*!< (@ 0x00000000) UARTA Clock Select Register                                */
16590 
16591         struct
16592         {
16593             __IOM uint8_t CK  : 4;     /*!< [3..0] UARTAn Operation Clock Select (fUTAn)                              */
16594             __IOM uint8_t SEL : 2;     /*!< [5..4] fSEL Clock Select                                                  */
16595             uint8_t           : 1;
16596             __IOM uint8_t EN  : 1;     /*!< [7..7] UARTAn clock output function enable                                */
16597         } UTAnCK_b[2];
16598     };
16599 } R_UARTA_CK_Type;                     /*!< Size = 2 (0x2)                                                            */
16600 
16601 /* =========================================================================================================================== */
16602 /* ================                                           R_WDT                                           ================ */
16603 /* =========================================================================================================================== */
16604 
16605 /**
16606  * @brief Watchdog Timer (R_WDT)
16607  */
16608 
16609 typedef struct                         /*!< (@ 0x40083400) R_WDT Structure                                            */
16610 {
16611     union
16612     {
16613         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
16614 
16615         struct
16616         {
16617             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
16618                                         *   of the WDT.                                                               */
16619         } WDTRR_b;
16620     };
16621     __IM uint8_t RESERVED;
16622 
16623     union
16624     {
16625         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
16626 
16627         struct
16628         {
16629             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
16630             uint16_t            : 2;
16631             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
16632             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
16633             uint16_t            : 2;
16634             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
16635             uint16_t            : 2;
16636         } WDTCR_b;
16637     };
16638 
16639     union
16640     {
16641         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
16642 
16643         struct
16644         {
16645             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
16646             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
16647             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
16648         } WDTSR_b;
16649     };
16650 
16651     union
16652     {
16653         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
16654 
16655         struct
16656         {
16657             uint8_t               : 7;
16658             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
16659         } WDTRCR_b;
16660     };
16661     __IM uint8_t RESERVED1;
16662 
16663     union
16664     {
16665         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
16666 
16667         struct
16668         {
16669             uint8_t              : 7;
16670             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
16671         } WDTCSTPR_b;
16672     };
16673     __IM uint8_t  RESERVED2;
16674     __IM uint16_t RESERVED3;
16675 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
16676 
16677 /* =========================================================================================================================== */
16678 /* ================                                           R_TZF                                           ================ */
16679 /* =========================================================================================================================== */
16680 
16681 /**
16682  * @brief TrustZone Filter (R_TZF)
16683  */
16684 
16685 typedef struct                         /*!< (@ 0x40000E00) R_TZF Structure                                            */
16686 {
16687     union
16688     {
16689         __IOM uint16_t TZFOAD;         /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register        */
16690 
16691         struct
16692         {
16693             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
16694             uint16_t           : 7;
16695             __OM uint16_t KEY  : 8;    /*!< [15..8] KeyCode                                                           */
16696         } TZFOAD_b;
16697     };
16698     __IM uint16_t RESERVED;
16699 
16700     union
16701     {
16702         __IOM uint16_t TZFPT;           /*!< (@ 0x00000004) TrustZone Filter Protect Register                          */
16703 
16704         struct
16705         {
16706             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
16707             uint16_t               : 7;
16708             __OM uint16_t KEY      : 8; /*!< [15..8] KeyCode                                                           */
16709         } TZFPT_b;
16710     };
16711 } R_TZF_Type;                           /*!< Size = 6 (0x6)                                                            */
16712 
16713 /* =========================================================================================================================== */
16714 /* ================                                          R_CACHE                                          ================ */
16715 /* =========================================================================================================================== */
16716 
16717 /**
16718  * @brief R_CACHE (R_CACHE)
16719  */
16720 
16721 typedef struct                         /*!< (@ 0x40007000) R_CACHE Structure                                          */
16722 {
16723     union
16724     {
16725         __IOM uint32_t CCACTL;         /*!< (@ 0x00000000) C-Cache Control Register                                   */
16726 
16727         struct
16728         {
16729             __IOM uint32_t ENC : 1;    /*!< [0..0] C-Cache Enable                                                     */
16730             uint32_t           : 31;
16731         } CCACTL_b;
16732     };
16733 
16734     union
16735     {
16736         __IOM uint32_t CCAFCT;         /*!< (@ 0x00000004) C-Cache Flush Control Register                             */
16737 
16738         struct
16739         {
16740             __IOM uint32_t FC : 1;     /*!< [0..0] C-Cache Flush                                                      */
16741             uint32_t          : 31;
16742         } CCAFCT_b;
16743     };
16744 
16745     union
16746     {
16747         __IOM uint32_t CCALCF;         /*!< (@ 0x00000008) C-Cache Line Configuration Register                        */
16748 
16749         struct
16750         {
16751             __IOM uint32_t CC : 2;     /*!< [1..0] C-Cache Line Size                                                  */
16752             uint32_t          : 30;
16753         } CCALCF_b;
16754     };
16755     __IM uint32_t RESERVED[13];
16756 
16757     union
16758     {
16759         __IOM uint32_t SCACTL;         /*!< (@ 0x00000040) S-Cache Control Register                                   */
16760 
16761         struct
16762         {
16763             __IOM uint32_t ENS : 1;    /*!< [0..0] S-Cache Enable                                                     */
16764             uint32_t           : 31;
16765         } SCACTL_b;
16766     };
16767 
16768     union
16769     {
16770         __IOM uint32_t SCAFCT;         /*!< (@ 0x00000044) S-Cache Flush Control Register                             */
16771 
16772         struct
16773         {
16774             __IOM uint32_t FS : 1;     /*!< [0..0] S-Cache Flush                                                      */
16775             uint32_t          : 31;
16776         } SCAFCT_b;
16777     };
16778 
16779     union
16780     {
16781         __IOM uint32_t SCALCF;         /*!< (@ 0x00000048) S-Cache Line Configuration Register                        */
16782 
16783         struct
16784         {
16785             __IOM uint32_t CS : 2;     /*!< [1..0] S-Cache Line Size                                                  */
16786             uint32_t          : 30;
16787         } SCALCF_b;
16788     };
16789     __IM uint32_t RESERVED1[109];
16790 
16791     union
16792     {
16793         __IOM uint32_t CAPOAD;         /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
16794                                         *                  Register                                                   */
16795 
16796         struct
16797         {
16798             __IOM uint32_t OAD : 1;    /*!< [0..0] Operation after Detection                                          */
16799             uint32_t           : 31;
16800         } CAPOAD_b;
16801     };
16802 
16803     union
16804     {
16805         __IOM uint32_t CAPRCR;         /*!< (@ 0x00000204) Cache Protection Register                                  */
16806 
16807         struct
16808         {
16809             __IOM uint32_t PRCR : 1;   /*!< [0..0] Register Write Control                                             */
16810             __IOM uint32_t KW   : 7;   /*!< [7..1] Write key code                                                     */
16811             uint32_t            : 24;
16812         } CAPRCR_b;
16813     };
16814 } R_CACHE_Type;                        /*!< Size = 520 (0x208)                                                        */
16815 
16816 /* =========================================================================================================================== */
16817 /* ================                                          R_CPSCU                                          ================ */
16818 /* =========================================================================================================================== */
16819 
16820 /**
16821  * @brief CPU System Security Control Unit (R_CPSCU)
16822  */
16823 
16824 typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
16825 {
16826     union
16827     {
16828         __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
16829 
16830         struct
16831         {
16832             __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
16833             __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
16834             __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
16835             uint32_t                : 29;
16836         } CSAR_b;
16837     };
16838     __IM uint32_t RESERVED[3];
16839 
16840     union
16841     {
16842         __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
16843 
16844         struct
16845         {
16846             __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
16847             __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
16848                                          *   2                                                                         */
16849             __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
16850             uint32_t               : 29;
16851         } SRAMSAR_b;
16852     };
16853 
16854     union
16855     {
16856         __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
16857 
16858         struct
16859         {
16860             __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
16861             uint32_t               : 28;
16862         } STBRAMSAR_b;
16863     };
16864     __IM uint32_t RESERVED1[6];
16865 
16866     union
16867     {
16868         __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
16869 
16870         struct
16871         {
16872             __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
16873             uint32_t               : 31;
16874         } DTCSAR_b;
16875     };
16876 
16877     union
16878     {
16879         __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
16880 
16881         struct
16882         {
16883             __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
16884             uint32_t               : 31;
16885         } DMACSAR_b;
16886     };
16887     __IM uint32_t RESERVED2[2];
16888 
16889     union
16890     {
16891         __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
16892 
16893         struct
16894         {
16895             __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
16896             uint32_t                : 16;
16897         } ICUSARA_b;
16898     };
16899 
16900     union
16901     {
16902         __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
16903 
16904         struct
16905         {
16906             __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
16907             uint32_t             : 31;
16908         } ICUSARB_b;
16909     };
16910 
16911     union
16912     {
16913         __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
16914 
16915         struct
16916         {
16917             __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
16918             uint32_t               : 24;
16919         } ICUSARC_b;
16920     };
16921 
16922     union
16923     {
16924         __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
16925 
16926         struct
16927         {
16928             __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
16929             uint32_t                : 31;
16930         } ICUSARD_b;
16931     };
16932 
16933     union
16934     {
16935         __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
16936 
16937         struct
16938         {
16939             uint32_t                    : 16;
16940             __IOM uint32_t SAIWDTWUP    : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
16941             uint32_t                    : 1;
16942             __IOM uint32_t SALVD1WUP    : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
16943             __IOM uint32_t SALVD2WUP    : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
16944             __IOM uint32_t SAVBATTWUP   : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
16945             uint32_t                    : 2;
16946             __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23                 */
16947             __IOM uint32_t SARTCALMWUP  : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
16948             __IOM uint32_t SARTCPRDWUP  : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
16949             uint32_t                    : 1;
16950             __IOM uint32_t SAUSBFS0WUP  : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
16951             __IOM uint32_t SAAGT1UDWUP  : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
16952             __IOM uint32_t SAAGT1CAWUP  : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
16953             __IOM uint32_t SAAGT1CBWUP  : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
16954             __IOM uint32_t SAIIC0WUP    : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
16955         } ICUSARE_b;
16956     };
16957 
16958     union
16959     {
16960         __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
16961 
16962         struct
16963         {
16964             __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
16965             __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
16966             __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
16967             __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
16968             uint32_t                    : 3;
16969             __IOM uint32_t SASOSCWUP    : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7                    */
16970             __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
16971             __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
16972             __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
16973             __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
16974             __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
16975             __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
16976             __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
16977             uint32_t                    : 17;
16978         } ICUSARF_b;
16979     };
16980 
16981     union
16982     {
16983         __IOM uint32_t ICUSARM;                /*!< (@ 0x00000058) ICU Security Attribution Register M                        */
16984 
16985         struct
16986         {
16987             __IOM uint32_t SAINTUR0WUP    : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0                    */
16988             __IOM uint32_t SAINTURE0WUP   : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1                    */
16989             __IOM uint32_t SAINTUR1WUP    : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2                    */
16990             __IOM uint32_t SAINTURE1WUP   : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3                    */
16991             __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4                    */
16992             __IOM uint32_t SALVDVRTCWUP   : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5                    */
16993             __IOM uint32_t SAEXLVDWUP     : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6                    */
16994             uint32_t                      : 25;
16995         } ICUSARM_b;
16996     };
16997     __IM uint32_t RESERVED3[5];
16998 
16999     union
17000     {
17001         __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
17002 
17003         struct
17004         {
17005             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
17006         } ICUSARG_b;
17007     };
17008 
17009     union
17010     {
17011         __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
17012 
17013         struct
17014         {
17015             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
17016         } ICUSARH_b;
17017     };
17018 
17019     union
17020     {
17021         __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
17022 
17023         struct
17024         {
17025             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
17026         } ICUSARI_b;
17027     };
17028     __IM uint32_t RESERVED4[33];
17029 
17030     union
17031     {
17032         __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
17033 
17034         struct
17035         {
17036             __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
17037             uint32_t              : 31;
17038         } BUSSARA_b;
17039     };
17040 
17041     union
17042     {
17043         __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
17044 
17045         struct
17046         {
17047             __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
17048             uint32_t              : 31;
17049         } BUSSARB_b;
17050     };
17051     __IM uint32_t RESERVED5[2];
17052 
17053     union
17054     {
17055         __IOM uint32_t BUSSARC;        /*!< (@ 0x00000110) Bus Security Attribution Register C                        */
17056 
17057         struct
17058         {
17059             __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0                                        */
17060             uint32_t              : 31;
17061         } BUSSARC_b;
17062     };
17063 
17064     union
17065     {
17066         __IOM uint32_t BUSPARC;        /*!< (@ 0x00000114) Bus Privileged Attribution Register C                      */
17067 
17068         struct
17069         {
17070             __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution                      */
17071             uint32_t              : 31;
17072         } BUSPARC_b;
17073     };
17074     __IM uint32_t RESERVED6[6];
17075 
17076     union
17077     {
17078         __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
17079                                           *                  Register A                                                 */
17080 
17081         struct
17082         {
17083             __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
17084             uint32_t                : 24;
17085         } MMPUSARA_b;
17086     };
17087 
17088     union
17089     {
17090         __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
17091                                           *                  Register B                                                 */
17092 
17093         struct
17094         {
17095             __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
17096             uint32_t                : 31;
17097         } MMPUSARB_b;
17098     };
17099     __IM uint32_t RESERVED7[18];
17100 
17101     union
17102     {
17103         union
17104         {
17105             __IOM uint32_t TZFSAR;         /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register             */
17106 
17107             struct
17108             {
17109                 __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter              */
17110                 uint32_t              : 31;
17111             } TZFSAR_b;
17112         };
17113 
17114         union
17115         {
17116             __IOM uint32_t DEBUGSAR;       /*!< (@ 0x00000180) Debug Security Attribution Register                        */
17117 
17118             struct
17119             {
17120                 __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0                             */
17121                 uint32_t              : 31;
17122             } DEBUGSAR_b;
17123         };
17124     };
17125     __IM uint32_t RESERVED8[7];
17126 
17127     union
17128     {
17129         __IOM uint32_t DMACCHSAR;          /*!< (@ 0x000001A0) DMA channel Security Attribution Register                  */
17130 
17131         struct
17132         {
17133             __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
17134                                             *   channel                                                                   */
17135             uint32_t : 24;
17136         } DMACCHSAR_b;
17137     };
17138     __IM uint32_t RESERVED9[3];
17139 
17140     union
17141     {
17142         __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
17143 
17144         struct
17145         {
17146             __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
17147             uint32_t               : 31;
17148         } CPUDSAR_b;
17149     };
17150     __IM uint32_t RESERVED10[147];
17151 
17152     union
17153     {
17154         __IOM uint32_t SRAMSABAR0;     /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register
17155                                         *                  0                                                          */
17156 
17157         struct
17158         {
17159             uint32_t                 : 13;
17160             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
17161                                            *   address of non-secure region).                                            */
17162             uint32_t : 11;
17163         } SRAMSABAR0_b;
17164     };
17165 
17166     union
17167     {
17168         __IOM uint32_t SRAMSABAR1;     /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register
17169                                         *                  1                                                          */
17170 
17171         struct
17172         {
17173             uint32_t                 : 13;
17174             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
17175                                            *   address of non-secure region).                                            */
17176             uint32_t : 11;
17177         } SRAMSABAR1_b;
17178     };
17179     __IM uint32_t RESERVED11[126];
17180 
17181     union
17182     {
17183         __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */
17184 
17185         struct
17186         {
17187             __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
17188                                         *   and ELCSRn                                                                */
17189             uint32_t : 31;
17190         } TEVTRCR_b;
17191     };
17192 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
17193 
17194 /* =========================================================================================================================== */
17195 /* ================                                          R_DOC_B                                          ================ */
17196 /* =========================================================================================================================== */
17197 
17198 /**
17199  * @brief Data Operation Circuit (R_DOC_B)
17200  */
17201 
17202 typedef struct                         /*!< (@ 0x40109000) R_DOC_B Structure                                          */
17203 {
17204     union
17205     {
17206         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
17207 
17208         struct
17209         {
17210             __IOM uint8_t OMS   : 2;   /*!< [1..0] Operating Mode Select                                              */
17211             uint8_t             : 1;
17212             __IOM uint8_t DOBW  : 1;   /*!< [3..3] Data Operation Bit Width Select                                    */
17213             __IOM uint8_t DCSEL : 3;   /*!< [6..4] Detection Condition Select                                         */
17214             uint8_t             : 1;
17215         } DOCR_b;
17216     };
17217     __IM uint8_t  RESERVED;
17218     __IM uint16_t RESERVED1;
17219 
17220     union
17221     {
17222         __IOM uint8_t DOSR;            /*!< (@ 0x00000004) DOC Flag Status Register                                   */
17223 
17224         struct
17225         {
17226             __IM uint8_t DOPCF : 1;    /*!< [0..0] Data Operation Circuit Flag                                        */
17227             uint8_t            : 7;
17228         } DOSR_b;
17229     };
17230     __IM uint8_t  RESERVED2;
17231     __IM uint16_t RESERVED3;
17232 
17233     union
17234     {
17235         __IOM uint8_t DOSCR;           /*!< (@ 0x00000008) DOC Flag Status Clear Register                             */
17236 
17237         struct
17238         {
17239             __OM uint8_t DOPCFCL : 1;  /*!< [0..0] DOPCF Clear                                                        */
17240             uint8_t              : 7;
17241         } DOSCR_b;
17242     };
17243     __IM uint8_t   RESERVED4;
17244     __IM uint16_t  RESERVED5;
17245     __IOM uint32_t DODIR;              /*!< (@ 0x0000000C) DOC Data Input Register                                    */
17246     __IOM uint32_t DODSR0;             /*!< (@ 0x00000010) DOC Data Setting Register 0                                */
17247     __IOM uint32_t DODSR1;             /*!< (@ 0x00000014) DOC Data Setting Register 1                                */
17248 } R_DOC_B_Type;                        /*!< Size = 24 (0x18)                                                          */
17249 
17250 /* =========================================================================================================================== */
17251 /* ================                                          R_AGTX0                                          ================ */
17252 /* =========================================================================================================================== */
17253 
17254 /**
17255  * @brief Asynchronous General Purpose Timer (R_AGTX0)
17256  */
17257 
17258 typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
17259 {
17260     union
17261     {
17262         __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
17263         __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
17264     };
17265 } R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
17266 
17267 /** @} */ /* End of group Device_Peripheral_peripherals */
17268 
17269 /* =========================================================================================================================== */
17270 /* ================                          Device Specific Peripheral Address Map                           ================ */
17271 /* =========================================================================================================================== */
17272 
17273 /** @addtogroup Device_Peripheral_peripheralAddr
17274  * @{
17275  */
17276 
17277  #define R_ACMPLP_BASE         0x400F4000UL
17278  #define R_ADC0_BASE           0x40170000UL
17279  #define R_ADC1_BASE           0x40170200UL
17280  #define R_PSCU_BASE           0x400E0000UL
17281  #define R_BUS_BASE            0x40003000UL
17282  #define R_CAC_BASE            0x40083600UL
17283  #define R_CANFD_BASE          0x400B0000UL
17284  #define R_CANFD1_BASE         0x400B2000UL
17285  #define R_CRC_BASE            0x40108000UL
17286  #define R_CTSU2_BASE          0x400D0000UL
17287  #define R_DAC_BASE            0x40171000UL
17288  #define R_DEBUG_BASE          0x4001B000UL
17289  #define R_DMA_BASE            0x40005200UL
17290  #define R_DMAC0_BASE          0x40005000UL
17291  #define R_DMAC1_BASE          0x40005040UL
17292  #define R_DMAC2_BASE          0x40005080UL
17293  #define R_DMAC3_BASE          0x400050C0UL
17294  #define R_DMAC4_BASE          0x40005100UL
17295  #define R_DMAC5_BASE          0x40005140UL
17296  #define R_DMAC6_BASE          0x40005180UL
17297  #define R_DMAC7_BASE          0x400051C0UL
17298  #define R_DTC_BASE            0x40005400UL
17299  #define R_ELC_BASE            0x40082000UL
17300  #define R_FACI_HP_CMD_BASE    0x407E0000UL
17301  #define R_FACI_HP_BASE        0x407FE000UL
17302  #define R_FACI_LP_BASE        0x407EC000UL
17303  #define R_CTSUTRIM_BASE       0x407EC000UL
17304  #define R_FCACHE_BASE         0x4001C000UL
17305  #define R_GPT0_BASE           0x40169000UL
17306  #define R_GPT1_BASE           0x40169100UL
17307  #define R_GPT2_BASE           0x40169200UL
17308  #define R_GPT3_BASE           0x40169300UL
17309  #define R_GPT4_BASE           0x40169400UL
17310  #define R_GPT5_BASE           0x40169500UL
17311  #define R_GPT6_BASE           0x40169600UL
17312  #define R_GPT7_BASE           0x40169700UL
17313  #define R_GPT8_BASE           0x40169800UL
17314  #define R_GPT9_BASE           0x40169900UL
17315  #define R_GPT10_BASE          0x40169A00UL
17316  #define R_GPT11_BASE          0x40169B00UL
17317  #define R_GPT12_BASE          0x40169C00UL
17318  #define R_GPT13_BASE          0x40169D00UL
17319  #define R_GPT_OPS_BASE        0x40169A00UL
17320  #define R_GPT_POEG0_BASE      0x4008A000UL
17321  #define R_GPT_POEG1_BASE      0x4008A100UL
17322  #define R_GPT_POEG2_BASE      0x4008A200UL
17323  #define R_GPT_POEG3_BASE      0x4008A300UL
17324  #define R_ICU_BASE            0x40006000UL
17325  #define R_IIC0_BASE           0x4009F000UL
17326  #define R_IIC1_BASE           0x4009F100UL
17327  #define R_IIC2_BASE           0x4009F200UL
17328  #define R_IRDA_BASE           0x40118F00UL
17329  #define R_IWDT_BASE           0x40083200UL
17330  #define R_I3C0_BASE           0x4011F000UL
17331  #define R_I3C1_BASE           0x4011F400UL
17332  #define R_MPU_MMPU_BASE       0x40000000UL
17333  #define R_MPU_SPMON_BASE      0x40000D00UL
17334  #define R_MSTP_BASE           0x40084000UL
17335  #define R_PORT0_BASE          0x4001F000UL
17336  #define R_PORT1_BASE          0x4001F020UL
17337  #define R_PORT2_BASE          0x4001F040UL
17338  #define R_PORT3_BASE          0x4001F060UL
17339  #define R_PORT4_BASE          0x4001F080UL
17340  #define R_PORT5_BASE          0x4001F0A0UL
17341  #define R_PORT6_BASE          0x4001F0C0UL
17342  #define R_PORT7_BASE          0x4001F0E0UL
17343  #define R_PORT8_BASE          0x4001F100UL
17344  #define R_PORT9_BASE          0x40080120UL
17345  #define R_PORT10_BASE         0x40080140UL
17346  #define R_PORT11_BASE         0x40080160UL
17347  #define R_PORT12_BASE         0x40080180UL
17348  #define R_PORT13_BASE         0x400801A0UL
17349  #define R_PORT14_BASE         0x400801C0UL
17350  #define R_PFS_BASE            0x4001F800UL
17351  #define R_PMISC_BASE          0x4001FD00UL
17352  #define R_QSPI_BASE           0x64000000UL
17353  #define R_RTC_BASE            0x40083000UL
17354  #define R_SCI0_BASE           0x40118000UL
17355  #define R_SCI1_BASE           0x40118100UL
17356  #define R_SCI2_BASE           0x40118200UL
17357  #define R_SCI3_BASE           0x40118300UL
17358  #define R_SCI4_BASE           0x40118400UL
17359  #define R_SCI5_BASE           0x40118500UL
17360  #define R_SCI6_BASE           0x40118600UL
17361  #define R_SCI7_BASE           0x40118700UL
17362  #define R_SCI8_BASE           0x40118800UL
17363  #define R_SCI9_BASE           0x40118900UL
17364  #define R_SLCDC_BASE          0x400D4000UL
17365  #define R_SPI0_BASE           0x4011A000UL
17366  #define R_SPI1_BASE           0x4011A100UL
17367  #define R_SPI2_BASE           0x40072200UL
17368  #define R_SRAM_BASE           0x40002000UL
17369  #define R_SSI0_BASE           0x4009D000UL
17370  #define R_SSI1_BASE           0x4009D100UL
17371  #define R_SYSTEM_BASE         0x4001E000UL
17372  #define R_TSN_BASE            0x407EC000UL
17373  #define R_USB_FS0_BASE        0x40090000UL
17374  #define R_UARTA0_BASE         0x40097000UL
17375  #define R_UARTA1_BASE         0x40097008UL
17376  #define R_UARTA_CK_BASE       0x40097010UL
17377  #define R_WDT_BASE            0x40083400UL
17378  #define R_TZF_BASE            0x40000E00UL
17379  #define R_CACHE_BASE          0x40007000UL
17380  #define R_CPSCU_BASE          0x40008000UL
17381  #define R_DOC_B_BASE          0x40109000UL
17382  #define R_AGTX0_BASE          0x400E8000UL
17383  #define R_AGTX1_BASE          0x400E8100UL
17384  #define R_AGTX2_BASE          0x400E8200UL
17385  #define R_AGTX3_BASE          0x400E8300UL
17386  #define R_AGTX4_BASE          0x400E8400UL
17387  #define R_AGTX5_BASE          0x400E8500UL
17388  #define R_AGTX6_BASE          0x400E8600UL
17389  #define R_AGTX7_BASE          0x400E8700UL
17390  #define R_AGTX8_BASE          0x400E8800UL
17391  #define R_AGTX9_BASE          0x400E8900UL
17392  #define R_WDT1_BASE           0x40044300UL
17393 
17394 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
17395 
17396 /* =========================================================================================================================== */
17397 /* ================                                  Peripheral declaration                                   ================ */
17398 /* =========================================================================================================================== */
17399 
17400 /** @addtogroup Device_Peripheral_declaration
17401  * @{
17402  */
17403 
17404  #define R_ACMPLP         ((R_ACMPLP_Type *) R_ACMPLP_BASE)
17405  #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
17406  #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
17407  #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)
17408 
17409 /* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
17410  #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
17411  #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
17412  #define R_CANFD0         ((R_CANFD_Type *) R_CANFD_BASE)
17413  #define R_CANFD1         ((R_CANFD_Type *) R_CANFD1_BASE)
17414  #define R_CRC            ((R_CRC_Type *) R_CRC_BASE)
17415  #define R_CTSU           ((R_CTSU2_Type *) R_CTSU2_BASE)
17416  #define R_DAC            ((R_DAC_Type *) R_DAC_BASE)
17417  #define R_DEBUG          ((R_DEBUG_Type *) R_DEBUG_BASE)
17418  #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
17419  #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
17420  #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
17421  #define R_DMAC2          ((R_DMAC0_Type *) R_DMAC2_BASE)
17422  #define R_DMAC3          ((R_DMAC0_Type *) R_DMAC3_BASE)
17423  #define R_DMAC4          ((R_DMAC0_Type *) R_DMAC4_BASE)
17424  #define R_DMAC5          ((R_DMAC0_Type *) R_DMAC5_BASE)
17425  #define R_DMAC6          ((R_DMAC0_Type *) R_DMAC6_BASE)
17426  #define R_DMAC7          ((R_DMAC0_Type *) R_DMAC7_BASE)
17427  #define R_DTC            ((R_DTC_Type *) R_DTC_BASE)
17428  #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
17429  #define R_FACI_HP_CMD    ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
17430  #define R_FACI_HP        ((R_FACI_HP_Type *) R_FACI_HP_BASE)
17431  #define R_FACI_LP        ((R_FACI_LP_Type *) R_FACI_LP_BASE)
17432  #define R_CTSUTRIM       ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE)
17433  #define R_FCACHE         ((R_FCACHE_Type *) R_FCACHE_BASE)
17434  #define R_GPT0           ((R_GPT0_Type *) R_GPT0_BASE)
17435  #define R_GPT1           ((R_GPT0_Type *) R_GPT1_BASE)
17436  #define R_GPT2           ((R_GPT0_Type *) R_GPT2_BASE)
17437  #define R_GPT3           ((R_GPT0_Type *) R_GPT3_BASE)
17438  #define R_GPT4           ((R_GPT0_Type *) R_GPT4_BASE)
17439  #define R_GPT5           ((R_GPT0_Type *) R_GPT5_BASE)
17440  #define R_GPT6           ((R_GPT0_Type *) R_GPT6_BASE)
17441  #define R_GPT7           ((R_GPT0_Type *) R_GPT7_BASE)
17442  #define R_GPT8           ((R_GPT0_Type *) R_GPT8_BASE)
17443  #define R_GPT9           ((R_GPT0_Type *) R_GPT9_BASE)
17444  #define R_GPT10          ((R_GPT0_Type *) R_GPT10_BASE)
17445  #define R_GPT11          ((R_GPT0_Type *) R_GPT11_BASE)
17446  #define R_GPT12          ((R_GPT0_Type *) R_GPT12_BASE)
17447  #define R_GPT13          ((R_GPT0_Type *) R_GPT13_BASE)
17448  #define R_GPT_OPS        ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
17449  #define R_GPT_POEG0      ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
17450  #define R_GPT_POEG1      ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
17451  #define R_GPT_POEG2      ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
17452  #define R_GPT_POEG3      ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
17453  #define R_ICU            ((R_ICU_Type *) R_ICU_BASE)
17454  #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
17455  #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
17456  #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
17457  #define R_IRDA           ((R_IRDA_Type *) R_IRDA_BASE)
17458  #define R_IWDT           ((R_IWDT_Type *) R_IWDT_BASE)
17459  #define R_I3C0           ((R_I3C0_Type *) R_I3C0_BASE)
17460  #define R_I3C1           ((R_I3C0_Type *) R_I3C1_BASE)
17461  #define R_MPU_MMPU       ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
17462  #define R_MPU_SPMON      ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
17463  #define R_MSTP           ((R_MSTP_Type *) R_MSTP_BASE)
17464  #define R_PORT0          ((R_PORT0_Type *) R_PORT0_BASE)
17465  #define R_PORT1          ((R_PORT0_Type *) R_PORT1_BASE)
17466  #define R_PORT2          ((R_PORT0_Type *) R_PORT2_BASE)
17467  #define R_PORT3          ((R_PORT0_Type *) R_PORT3_BASE)
17468  #define R_PORT4          ((R_PORT0_Type *) R_PORT4_BASE)
17469  #define R_PORT5          ((R_PORT0_Type *) R_PORT5_BASE)
17470  #define R_PORT6          ((R_PORT0_Type *) R_PORT6_BASE)
17471  #define R_PORT7          ((R_PORT0_Type *) R_PORT7_BASE)
17472  #define R_PORT8          ((R_PORT0_Type *) R_PORT8_BASE)
17473  #define R_PORT9          ((R_PORT0_Type *) R_PORT9_BASE)
17474  #define R_PORT10         ((R_PORT0_Type *) R_PORT10_BASE)
17475  #define R_PORT11         ((R_PORT0_Type *) R_PORT11_BASE)
17476  #define R_PORT12         ((R_PORT0_Type *) R_PORT12_BASE)
17477  #define R_PORT13         ((R_PORT0_Type *) R_PORT13_BASE)
17478  #define R_PORT14         ((R_PORT0_Type *) R_PORT14_BASE)
17479  #define R_PFS            ((R_PFS_Type *) R_PFS_BASE)
17480  #define R_PMISC          ((R_PMISC_Type *) R_PMISC_BASE)
17481  #define R_QSPI           ((R_QSPI_Type *) R_QSPI_BASE)
17482  #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
17483  #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
17484  #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
17485  #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
17486  #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
17487  #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
17488  #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
17489  #define R_SCI6           ((R_SCI0_Type *) R_SCI6_BASE)
17490  #define R_SCI7           ((R_SCI0_Type *) R_SCI7_BASE)
17491  #define R_SCI8           ((R_SCI0_Type *) R_SCI8_BASE)
17492  #define R_SCI9           ((R_SCI0_Type *) R_SCI9_BASE)
17493  #define R_SLCDC          ((R_SLCDC_Type *) R_SLCDC_BASE)
17494  #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
17495  #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
17496  #define R_SPI2           ((R_SPI0_Type *) R_SPI2_BASE)
17497  #define R_SRAM           ((R_SRAM_Type *) R_SRAM_BASE)
17498  #define R_SSI0           ((R_SSI0_Type *) R_SSI0_BASE)
17499  #define R_SSI1           ((R_SSI0_Type *) R_SSI1_BASE)
17500  #define R_SYSTEM         ((R_SYSTEM_Type *) R_SYSTEM_BASE)
17501  #define R_TSN            ((R_TSN_Type *) R_TSN_BASE)
17502  #define R_USB_FS0        ((R_USB_FS0_Type *) R_USB_FS0_BASE)
17503  #define R_UARTA0         ((R_UARTA0_Type *) R_UARTA0_BASE)
17504  #define R_UARTA1         ((R_UARTA0_Type *) R_UARTA1_BASE)
17505  #define R_UARTA_CK       ((R_UARTA_CK_Type *) R_UARTA_CK_BASE)
17506  #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
17507  #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
17508  #define R_CACHE          ((R_CACHE_Type *) R_CACHE_BASE)
17509  #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
17510  #define R_DOC_B          ((R_DOC_B_Type *) R_DOC_B_BASE)
17511  #define R_AGTW0          ((R_AGTX0_Type *) R_AGTX0_BASE)
17512  #define R_AGTW1          ((R_AGTX0_Type *) R_AGTX1_BASE)
17513  #define R_AGTW2          ((R_AGTX0_Type *) R_AGTX2_BASE)
17514  #define R_AGTW3          ((R_AGTX0_Type *) R_AGTX3_BASE)
17515  #define R_AGTW4          ((R_AGTX0_Type *) R_AGTX4_BASE)
17516  #define R_AGTW5          ((R_AGTX0_Type *) R_AGTX5_BASE)
17517  #define R_AGTW6          ((R_AGTX0_Type *) R_AGTX6_BASE)
17518  #define R_AGTW7          ((R_AGTX0_Type *) R_AGTX7_BASE)
17519  #define R_AGTW8          ((R_AGTX0_Type *) R_AGTX8_BASE)
17520  #define R_AGTW9          ((R_AGTX0_Type *) R_AGTX9_BASE)
17521  #define R_WDT1           ((R_WDT_Type *) R_WDT1_BASE)
17522 
17523 /** @} */ /* End of group Device_Peripheral_declaration */
17524 
17525 /* =========================================  End of section using anonymous unions  ========================================= */
17526  #if defined(__CC_ARM)
17527   #pragma pop
17528  #elif defined(__ICCARM__)
17529 
17530 /* leave anonymous unions enabled */
17531  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
17532   #pragma clang diagnostic pop
17533  #elif defined(__GNUC__)
17534 
17535 /* anonymous unions are enabled by default */
17536  #elif defined(__TMS470__)
17537 
17538 /* anonymous unions are enabled by default */
17539  #elif defined(__TASKING__)
17540   #pragma warning restore
17541  #elif defined(__CSMC__)
17542 
17543 /* anonymous unions are enabled by default */
17544  #endif
17545 
17546 /* =========================================================================================================================== */
17547 /* ================                                 Pos/Mask Cluster Section                                  ================ */
17548 /* =========================================================================================================================== */
17549 
17550 /** @addtogroup PosMask_clusters
17551  * @{
17552  */
17553 
17554 /* =========================================================================================================================== */
17555 /* ================                                            CSa                                            ================ */
17556 /* =========================================================================================================================== */
17557 
17558 /* ==========================================================  MOD  ========================================================== */
17559  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
17560  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
17561  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
17562  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
17563  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
17564  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
17565  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
17566  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
17567  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
17568  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
17569 /* =========================================================  WCR1  ========================================================== */
17570  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
17571  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
17572  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
17573  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
17574  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
17575  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
17576  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
17577  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
17578 /* =========================================================  WCR2  ========================================================== */
17579  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
17580  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
17581  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
17582  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
17583  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
17584  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
17585  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
17586  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
17587  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
17588  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
17589  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
17590  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
17591  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
17592  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
17593  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
17594  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
17595 
17596 /* =========================================================================================================================== */
17597 /* ================                                            CSb                                            ================ */
17598 /* =========================================================================================================================== */
17599 
17600 /* ==========================================================  CR  =========================================================== */
17601  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
17602  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
17603  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
17604  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
17605  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
17606  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
17607  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
17608  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
17609 /* ==========================================================  REC  ========================================================== */
17610  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
17611  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
17612  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
17613  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
17614 
17615 /* =========================================================================================================================== */
17616 /* ================                                           SDRAM                                           ================ */
17617 /* =========================================================================================================================== */
17618 
17619 /* =========================================================  SDCCR  ========================================================= */
17620  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
17621  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
17622  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
17623  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
17624 /* ========================================================  SDCMOD  ========================================================= */
17625  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
17626  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
17627 /* ========================================================  SDAMOD  ========================================================= */
17628  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
17629  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
17630 /* ========================================================  SDSELF  ========================================================= */
17631  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
17632  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
17633 /* ========================================================  SDRFCR  ========================================================= */
17634  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
17635  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
17636  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
17637  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
17638 /* ========================================================  SDRFEN  ========================================================= */
17639  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
17640  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
17641 /* =========================================================  SDICR  ========================================================= */
17642  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
17643  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
17644 /* =========================================================  SDIR  ========================================================== */
17645  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
17646  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
17647  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
17648  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
17649  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
17650  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
17651 /* =========================================================  SDADR  ========================================================= */
17652  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
17653  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
17654 /* =========================================================  SDTR  ========================================================== */
17655  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
17656  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
17657  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
17658  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
17659  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
17660  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
17661  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
17662  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
17663  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
17664  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
17665 /* =========================================================  SDMOD  ========================================================= */
17666  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
17667  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
17668 /* =========================================================  SDSR  ========================================================== */
17669  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
17670  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
17671  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
17672  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
17673  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
17674  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
17675 
17676 /* =========================================================================================================================== */
17677 /* ================                                          BUSERRa                                          ================ */
17678 /* =========================================================================================================================== */
17679 
17680 /* ==========================================================  ADD  ========================================================== */
17681  #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
17682  #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
17683 /* =========================================================  STAT  ========================================================== */
17684  #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
17685  #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
17686  #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
17687  #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
17688 /* ==========================================================  RW  =========================================================== */
17689  #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
17690  #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
17691 
17692 /* =========================================================================================================================== */
17693 /* ================                                          BTZFERR                                          ================ */
17694 /* =========================================================================================================================== */
17695 
17696 /* ==========================================================  ADD  ========================================================== */
17697  #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
17698  #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
17699 /* ==========================================================  RW  =========================================================== */
17700  #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
17701  #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
17702 
17703 /* =========================================================================================================================== */
17704 /* ================                                          BUSERRb                                          ================ */
17705 /* =========================================================================================================================== */
17706 
17707 /* =========================================================  STAT  ========================================================== */
17708  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
17709  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
17710  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
17711  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
17712  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
17713  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
17714  #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
17715  #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
17716  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
17717  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
17718 /* ==========================================================  CLR  ========================================================== */
17719  #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
17720  #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
17721  #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
17722  #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
17723  #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
17724  #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
17725  #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
17726  #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
17727  #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
17728  #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
17729 /* =========================================================  IRQEN  ========================================================= */
17730  #define R_BUS_BUSERRb_IRQEN_EN_Pos          (0UL)    /*!< EN (Bit 0)                                            */
17731  #define R_BUS_BUSERRb_IRQEN_EN_Msk          (0x1UL)  /*!< EN (Bitfield-Mask: 0x01)                              */
17732 
17733 /* =========================================================================================================================== */
17734 /* ================                                        DMACDTCERR                                         ================ */
17735 /* =========================================================================================================================== */
17736 
17737 /* =========================================================  STAT  ========================================================== */
17738  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
17739  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
17740 /* ==========================================================  CLR  ========================================================== */
17741  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
17742  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
17743 
17744 /* =========================================================================================================================== */
17745 /* ================                                         BUSSABT0                                          ================ */
17746 /* =========================================================================================================================== */
17747 
17748 /* =========================================================  FLBI  ========================================================== */
17749  #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17750  #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17751 /* ========================================================  MRE0BI  ========================================================= */
17752  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
17753  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17754 /* =========================================================  S0BI  ========================================================== */
17755  #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17756  #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17757 /* =========================================================  S1BI  ========================================================== */
17758  #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17759  #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17760 /* =========================================================  S2BI  ========================================================== */
17761  #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17762  #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17763 /* =========================================================  S3BI  ========================================================== */
17764  #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17765  #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17766 /* ========================================================  STBYSBI  ======================================================== */
17767  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
17768  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17769 /* =========================================================  ECBI  ========================================================== */
17770  #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17771  #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17772 /* =========================================================  EOBI  ========================================================== */
17773  #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17774  #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17775 /* ========================================================  SPI0BI  ========================================================= */
17776  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
17777  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17778 /* ========================================================  SPI1BI  ========================================================= */
17779  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
17780  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17781 /* =========================================================  PBBI  ========================================================== */
17782  #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17783  #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17784 /* =========================================================  PABI  ========================================================== */
17785  #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17786  #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17787 /* =========================================================  PIBI  ========================================================== */
17788  #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17789  #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17790 /* =========================================================  PSBI  ========================================================== */
17791  #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
17792  #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17793 /* =======================================================  CPU0SAHBI  ======================================================= */
17794  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
17795  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
17796 
17797 /* =========================================================================================================================== */
17798 /* ================                                         BUSSABT1                                          ================ */
17799 /* =========================================================================================================================== */
17800 
17801 /* =========================================================  FHBI  ========================================================== */
17802  #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
17803  #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
17804 /* ========================================================  MRC0BI  ========================================================= */
17805  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
17806  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
17807 /* =========================================================  S0BI  ========================================================== */
17808  #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
17809  #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
17810 /* =========================================================  S1BI  ========================================================== */
17811  #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
17812  #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
17813 
17814 /* =========================================================================================================================== */
17815 /* ================                                          BMSAERR                                          ================ */
17816 /* =========================================================================================================================== */
17817 
17818 /* ==========================================================  ADD  ========================================================== */
17819  #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
17820  #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
17821 /* ==========================================================  RW  =========================================================== */
17822  #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
17823  #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */
17824 
17825 /* =========================================================================================================================== */
17826 /* ================                                            OAD                                            ================ */
17827 /* =========================================================================================================================== */
17828 
17829 /* ========================================================  BUSOAD  ========================================================= */
17830  #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
17831  #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
17832  #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
17833  #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
17834  #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
17835  #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
17836 /* =======================================================  BUSOADPT  ======================================================== */
17837  #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
17838  #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
17839  #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
17840  #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
17841 /* ========================================================  MSAOAD  ========================================================= */
17842  #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
17843  #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
17844  #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
17845  #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
17846 /* =========================================================  MSAPT  ========================================================= */
17847  #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
17848  #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
17849  #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
17850  #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
17851 
17852 /* =========================================================================================================================== */
17853 /* ================                                          MBWERR                                           ================ */
17854 /* =========================================================================================================================== */
17855 
17856 /* =========================================================  STAT  ========================================================== */
17857  #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
17858  #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
17859 /* ==========================================================  CLR  ========================================================== */
17860  #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
17861  #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
17862 
17863 /* =========================================================================================================================== */
17864 /* ================                                           BUSM                                            ================ */
17865 /* =========================================================================================================================== */
17866 
17867 /* ==========================================================  CNT  ========================================================== */
17868  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
17869  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
17870 
17871 /* =========================================================================================================================== */
17872 /* ================                                           BUSS                                            ================ */
17873 /* =========================================================================================================================== */
17874 
17875 /* ==========================================================  CNT  ========================================================== */
17876  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
17877  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
17878  #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
17879  #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */
17880 
17881 /* =========================================================================================================================== */
17882 /* ================                                           CFDC                                            ================ */
17883 /* =========================================================================================================================== */
17884 
17885 /* =========================================================  NCFG  ========================================================== */
17886  #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
17887  #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
17888  #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
17889  #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
17890  #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
17891  #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
17892  #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
17893  #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
17894 /* ==========================================================  CTR  ========================================================== */
17895  #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
17896  #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
17897  #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
17898  #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
17899  #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
17900  #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
17901  #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
17902  #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
17903  #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
17904  #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
17905  #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
17906  #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
17907  #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
17908  #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
17909  #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
17910  #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
17911  #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
17912  #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
17913  #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
17914  #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
17915  #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
17916  #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
17917  #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
17918  #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
17919  #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
17920  #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
17921  #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
17922  #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
17923  #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
17924  #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
17925  #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
17926  #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
17927  #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
17928  #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
17929  #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
17930  #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
17931  #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
17932  #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
17933  #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
17934  #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
17935  #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
17936  #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
17937 /* ==========================================================  STS  ========================================================== */
17938  #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
17939  #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
17940  #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
17941  #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
17942  #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
17943  #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
17944  #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
17945  #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
17946  #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
17947  #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
17948  #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
17949  #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
17950  #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
17951  #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
17952  #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
17953  #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
17954  #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
17955  #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
17956  #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
17957  #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
17958  #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
17959  #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
17960 /* =========================================================  ERFL  ========================================================== */
17961  #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
17962  #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
17963  #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
17964  #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
17965  #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
17966  #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
17967  #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
17968  #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
17969  #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
17970  #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
17971  #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
17972  #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
17973  #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
17974  #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
17975  #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
17976  #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
17977  #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
17978  #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
17979  #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
17980  #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
17981  #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
17982  #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
17983  #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
17984  #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
17985  #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
17986  #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
17987  #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
17988  #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
17989  #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
17990  #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
17991  #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
17992  #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
17993 
17994 /* =========================================================================================================================== */
17995 /* ================                                           CFDC2                                           ================ */
17996 /* =========================================================================================================================== */
17997 
17998 /* =========================================================  DCFG  ========================================================== */
17999  #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
18000  #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
18001  #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
18002  #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
18003  #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
18004  #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
18005  #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
18006  #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
18007 /* =========================================================  FDCFG  ========================================================= */
18008  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
18009  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
18010  #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
18011  #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
18012  #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
18013  #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
18014  #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
18015  #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
18016  #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
18017  #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
18018  #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
18019  #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
18020  #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
18021  #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
18022  #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
18023  #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
18024 /* =========================================================  FDCTR  ========================================================= */
18025  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
18026  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
18027  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
18028  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
18029 /* =========================================================  FDSTS  ========================================================= */
18030  #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
18031  #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
18032  #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
18033  #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
18034  #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
18035  #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
18036  #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
18037  #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
18038  #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
18039  #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
18040  #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
18041  #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
18042 /* =========================================================  FDCRC  ========================================================= */
18043  #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
18044  #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
18045  #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
18046  #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
18047 
18048 /* =========================================================================================================================== */
18049 /* ================                                          CFDGAFL                                          ================ */
18050 /* =========================================================================================================================== */
18051 
18052 /* ==========================================================  ID  =========================================================== */
18053  #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
18054  #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
18055  #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
18056  #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
18057  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
18058  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
18059  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
18060  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
18061 /* ===========================================================  M  =========================================================== */
18062  #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
18063  #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
18064  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
18065  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
18066  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
18067  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
18068  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
18069  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
18070 /* ==========================================================  P0  =========================================================== */
18071  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
18072  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
18073  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
18074  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
18075  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
18076  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
18077  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
18078  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
18079  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
18080  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
18081 /* ==========================================================  P1  =========================================================== */
18082  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
18083  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */
18084 
18085 /* =========================================================================================================================== */
18086 /* ================                                          CFDTHL                                           ================ */
18087 /* =========================================================================================================================== */
18088 
18089 /* =========================================================  ACC0  ========================================================== */
18090  #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
18091  #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
18092  #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
18093  #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
18094  #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
18095  #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
18096 /* =========================================================  ACC1  ========================================================== */
18097  #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
18098  #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
18099  #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
18100  #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
18101 
18102 /* =========================================================================================================================== */
18103 /* ================                                           CFDRF                                           ================ */
18104 /* =========================================================================================================================== */
18105 
18106 /* ==========================================================  ID  =========================================================== */
18107  #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
18108  #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
18109  #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
18110  #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
18111  #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
18112  #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
18113 /* ==========================================================  PTR  ========================================================== */
18114  #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
18115  #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
18116  #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
18117  #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
18118 /* =========================================================  FDSTS  ========================================================= */
18119  #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
18120  #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
18121  #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
18122  #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
18123  #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
18124  #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
18125  #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
18126  #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
18127  #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
18128  #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
18129 /* ==========================================================  DF  =========================================================== */
18130  #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
18131  #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
18132 
18133 /* =========================================================================================================================== */
18134 /* ================                                           CFDCF                                           ================ */
18135 /* =========================================================================================================================== */
18136 
18137 /* ==========================================================  ID  =========================================================== */
18138  #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
18139  #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
18140  #define R_CANFD_CFDCF_ID_THLEN_Pos       (29UL)         /*!< THLEN (Bit 29)                                        */
18141  #define R_CANFD_CFDCF_ID_THLEN_Msk       (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
18142  #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
18143  #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
18144  #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
18145  #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
18146 /* ==========================================================  PTR  ========================================================== */
18147  #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
18148  #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
18149  #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
18150  #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
18151 /* =========================================================  FDSTS  ========================================================= */
18152  #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
18153  #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
18154  #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
18155  #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
18156  #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
18157  #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
18158  #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
18159  #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
18160  #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
18161  #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
18162 /* ==========================================================  DF  =========================================================== */
18163  #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
18164  #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
18165 
18166 /* =========================================================================================================================== */
18167 /* ================                                           CFDTM                                           ================ */
18168 /* =========================================================================================================================== */
18169 
18170 /* ==========================================================  ID  =========================================================== */
18171  #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
18172  #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
18173  #define R_CANFD_CFDTM_ID_THLEN_Pos       (29UL)         /*!< THLEN (Bit 29)                                        */
18174  #define R_CANFD_CFDTM_ID_THLEN_Msk       (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
18175  #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
18176  #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
18177  #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
18178  #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
18179 /* ==========================================================  PTR  ========================================================== */
18180  #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
18181  #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
18182  #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
18183  #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
18184 /* =========================================================  FDCTR  ========================================================= */
18185  #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
18186  #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
18187  #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
18188  #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
18189  #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
18190  #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
18191  #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
18192  #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
18193  #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
18194  #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
18195 /* ==========================================================  DF  =========================================================== */
18196  #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
18197  #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
18198 
18199 /* =========================================================================================================================== */
18200 /* ================                                            RM                                             ================ */
18201 /* =========================================================================================================================== */
18202 
18203 /* ==========================================================  ID  =========================================================== */
18204  #define R_CANFD_CFDRM_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
18205  #define R_CANFD_CFDRM_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
18206  #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
18207  #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
18208  #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
18209  #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
18210 /* ==========================================================  PTR  ========================================================== */
18211  #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
18212  #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
18213  #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
18214  #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
18215 /* =========================================================  FDSTS  ========================================================= */
18216  #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
18217  #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
18218  #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
18219  #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
18220  #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
18221  #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
18222  #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
18223  #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
18224  #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
18225  #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
18226 /* ==========================================================  DF  =========================================================== */
18227  #define R_CANFD_CFDRM_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
18228  #define R_CANFD_CFDRM_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
18229 
18230 /* =========================================================================================================================== */
18231 /* ================                                           CFDRM                                           ================ */
18232 /* =========================================================================================================================== */
18233 
18234 /* =========================================================================================================================== */
18235 /* ================                                          ELSEGR                                           ================ */
18236 /* =========================================================================================================================== */
18237 
18238 /* ==========================================================  BY  =========================================================== */
18239  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
18240  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
18241  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
18242  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
18243  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
18244  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
18245 
18246 /* =========================================================================================================================== */
18247 /* ================                                           ELSR                                            ================ */
18248 /* =========================================================================================================================== */
18249 
18250 /* ==========================================================  HA  =========================================================== */
18251  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
18252  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
18253 
18254 /* =========================================================================================================================== */
18255 /* ================                                            SAR                                            ================ */
18256 /* =========================================================================================================================== */
18257 
18258 /* ===========================================================  L  =========================================================== */
18259  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
18260  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
18261 /* ===========================================================  U  =========================================================== */
18262  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
18263  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
18264  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
18265  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
18266  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
18267  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
18268 
18269 /* =========================================================================================================================== */
18270 /* ================                                          REGION                                           ================ */
18271 /* =========================================================================================================================== */
18272 
18273 /* ==========================================================  AC  =========================================================== */
18274  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos        (3UL)          /*!< PP (Bit 3)                                            */
18275  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk        (0x8UL)        /*!< PP (Bitfield-Mask: 0x01)                              */
18276  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
18277  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
18278  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
18279  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
18280  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
18281  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
18282 /* ===========================================================  S  =========================================================== */
18283  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
18284  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
18285 /* ===========================================================  E  =========================================================== */
18286  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
18287  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */
18288 
18289 /* =========================================================================================================================== */
18290 /* ================                                           GROUP                                           ================ */
18291 /* =========================================================================================================================== */
18292 
18293 /* ==========================================================  EN  =========================================================== */
18294  #define R_MPU_MMPU_GROUP_EN_KEY_Pos             (8UL)      /*!< KEY (Bit 8)                                           */
18295  #define R_MPU_MMPU_GROUP_EN_KEY_Msk             (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
18296  #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos          (0UL)      /*!< ENABLE (Bit 0)                                        */
18297  #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk          (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
18298 /* =========================================================  ENPT  ========================================================== */
18299  #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
18300  #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
18301  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
18302  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
18303 /* ==========================================================  RPT  ========================================================== */
18304  #define R_MPU_MMPU_GROUP_RPT_KEY_Pos            (8UL)      /*!< KEY (Bit 8)                                           */
18305  #define R_MPU_MMPU_GROUP_RPT_KEY_Msk            (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
18306  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos        (0UL)      /*!< PROTECT (Bit 0)                                       */
18307  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk        (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
18308 /* ========================================================  RPT_SEC  ======================================================== */
18309  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
18310  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
18311  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
18312  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
18313 
18314 /* =========================================================================================================================== */
18315 /* ================                                            SP                                             ================ */
18316 /* =========================================================================================================================== */
18317 
18318 /* ==========================================================  OAD  ========================================================== */
18319  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
18320  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
18321  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
18322  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
18323 /* ==========================================================  CTL  ========================================================== */
18324  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
18325  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
18326  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
18327  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
18328 /* ==========================================================  PT  =========================================================== */
18329  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
18330  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
18331  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
18332  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
18333 /* ==========================================================  SA  =========================================================== */
18334  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
18335  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
18336 /* ==========================================================  EA  =========================================================== */
18337  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
18338  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
18339 
18340 /* =========================================================================================================================== */
18341 /* ================                                            PIN                                            ================ */
18342 /* =========================================================================================================================== */
18343 
18344 /* =======================================================  PmnPFS_BY  ======================================================= */
18345  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
18346  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
18347  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
18348  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
18349  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
18350  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
18351  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
18352  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
18353  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
18354  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
18355  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
18356  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
18357 /* =======================================================  PmnPFS_HA  ======================================================= */
18358  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
18359  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
18360  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
18361  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
18362  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
18363  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
18364  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
18365  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
18366  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
18367  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
18368  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
18369  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
18370  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
18371  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
18372  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
18373  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
18374  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
18375  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
18376  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
18377  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
18378 /* ========================================================  PmnPFS  ========================================================= */
18379  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
18380  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
18381  #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
18382  #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
18383  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
18384  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
18385  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
18386  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
18387  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
18388  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
18389  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
18390  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
18391  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
18392  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
18393  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
18394  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
18395  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
18396  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
18397  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
18398  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
18399  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
18400  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
18401  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
18402  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
18403 
18404 /* =========================================================================================================================== */
18405 /* ================                                           PORT                                            ================ */
18406 /* =========================================================================================================================== */
18407 
18408 /* =========================================================================================================================== */
18409 /* ================                                           VLSEL                                           ================ */
18410 /* =========================================================================================================================== */
18411 
18412 /* ========================================================  VL1SEL  ========================================================= */
18413  #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
18414  #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
18415 
18416 /* =========================================================================================================================== */
18417 /* ================                                           PMSAR                                           ================ */
18418 /* =========================================================================================================================== */
18419 
18420 /* =========================================================  PMSAR  ========================================================= */
18421 
18422 /* =========================================================================================================================== */
18423 /* ================                                           RTCCR                                           ================ */
18424 /* =========================================================================================================================== */
18425 
18426 /* =========================================================  RTCCR  ========================================================= */
18427  #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
18428  #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
18429  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
18430  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
18431  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
18432  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
18433  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
18434  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
18435 
18436 /* =========================================================================================================================== */
18437 /* ================                                            CP                                             ================ */
18438 /* =========================================================================================================================== */
18439 
18440 /* =========================================================  RSEC  ========================================================== */
18441  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
18442  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
18443  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
18444  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
18445 /* =========================================================  BCNT0  ========================================================= */
18446  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
18447  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
18448 /* =========================================================  RMIN  ========================================================== */
18449  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
18450  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
18451  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
18452  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
18453 /* =========================================================  BCNT1  ========================================================= */
18454  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
18455  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
18456 /* ==========================================================  RHR  ========================================================== */
18457  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
18458  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
18459  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
18460  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
18461  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
18462  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
18463 /* =========================================================  BCNT2  ========================================================= */
18464  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
18465  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
18466 /* =========================================================  RDAY  ========================================================== */
18467  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
18468  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
18469  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
18470  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
18471 /* =========================================================  BCNT3  ========================================================= */
18472  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
18473  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
18474 /* =========================================================  RMON  ========================================================== */
18475  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
18476  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
18477  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
18478  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
18479 
18480 /* =========================================================================================================================== */
18481 /* ================                                          PIPE_TR                                          ================ */
18482 /* =========================================================================================================================== */
18483 
18484 /* ===========================================================  E  =========================================================== */
18485  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
18486  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
18487  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
18488  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
18489 /* ===========================================================  N  =========================================================== */
18490  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
18491  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
18492 
18493 /* =========================================================================================================================== */
18494 /* ================                                           CTRL                                            ================ */
18495 /* =========================================================================================================================== */
18496 
18497 /* =========================================================  AGTCR  ========================================================= */
18498  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
18499  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
18500  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
18501  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
18502  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
18503  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
18504  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
18505  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
18506  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
18507  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
18508  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
18509  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
18510  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
18511  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
18512 /* ========================================================  AGTMR1  ========================================================= */
18513  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
18514  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
18515  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
18516  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
18517  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
18518  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
18519 /* ========================================================  AGTMR2  ========================================================= */
18520  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
18521  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
18522  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
18523  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
18524 /* =====================================================  AGTIOSEL_ALT  ====================================================== */
18525  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
18526  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
18527  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
18528  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
18529 /* ========================================================  AGTIOC  ========================================================= */
18530  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
18531  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
18532  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
18533  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
18534  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
18535  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
18536  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
18537  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
18538 /* ========================================================  AGTISR  ========================================================= */
18539  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
18540  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
18541 /* ========================================================  AGTCMSR  ======================================================== */
18542  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
18543  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
18544  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
18545  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
18546  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
18547  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
18548  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
18549  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
18550  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
18551  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
18552  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
18553  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
18554 /* =======================================================  AGTIOSEL  ======================================================== */
18555  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
18556  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
18557  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
18558  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
18559 
18560 /* =========================================================================================================================== */
18561 /* ================                                           AGT16                                           ================ */
18562 /* =========================================================================================================================== */
18563 
18564 /* ==========================================================  AGT  ========================================================== */
18565  #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
18566  #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
18567 /* ========================================================  AGTCMA  ========================================================= */
18568  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
18569  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
18570 /* ========================================================  AGTCMB  ========================================================= */
18571  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
18572  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
18573 
18574 /* =========================================================================================================================== */
18575 /* ================                                           AGT32                                           ================ */
18576 /* =========================================================================================================================== */
18577 
18578 /* ==========================================================  AGT  ========================================================== */
18579  #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
18580  #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
18581 /* ========================================================  AGTCMA  ========================================================= */
18582  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
18583  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
18584 /* ========================================================  AGTCMB  ========================================================= */
18585  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
18586  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
18587 
18588 /** @} */ /* End of group PosMask_clusters */
18589 
18590 /* =========================================================================================================================== */
18591 /* ================                                Pos/Mask Peripheral Section                                ================ */
18592 /* =========================================================================================================================== */
18593 
18594 /** @addtogroup PosMask_peripherals
18595  * @{
18596  */
18597 
18598 /* =========================================================================================================================== */
18599 /* ================                                         R_ACMPLP                                          ================ */
18600 /* =========================================================================================================================== */
18601 
18602 /* ========================================================  COMPMDR  ======================================================== */
18603  #define R_ACMPLP_COMPMDR_C1MON_Pos      (7UL)    /*!< C1MON (Bit 7)                                         */
18604  #define R_ACMPLP_COMPMDR_C1MON_Msk      (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01)                           */
18605  #define R_ACMPLP_COMPMDR_C1VRF_Pos      (6UL)    /*!< C1VRF (Bit 6)                                         */
18606  #define R_ACMPLP_COMPMDR_C1VRF_Msk      (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01)                           */
18607  #define R_ACMPLP_COMPMDR_C1WDE_Pos      (5UL)    /*!< C1WDE (Bit 5)                                         */
18608  #define R_ACMPLP_COMPMDR_C1WDE_Msk      (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01)                           */
18609  #define R_ACMPLP_COMPMDR_C1ENB_Pos      (4UL)    /*!< C1ENB (Bit 4)                                         */
18610  #define R_ACMPLP_COMPMDR_C1ENB_Msk      (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01)                           */
18611  #define R_ACMPLP_COMPMDR_C0MON_Pos      (3UL)    /*!< C0MON (Bit 3)                                         */
18612  #define R_ACMPLP_COMPMDR_C0MON_Msk      (0x8UL)  /*!< C0MON (Bitfield-Mask: 0x01)                           */
18613  #define R_ACMPLP_COMPMDR_C0WDE_Pos      (1UL)    /*!< C0WDE (Bit 1)                                         */
18614  #define R_ACMPLP_COMPMDR_C0WDE_Msk      (0x2UL)  /*!< C0WDE (Bitfield-Mask: 0x01)                           */
18615  #define R_ACMPLP_COMPMDR_C0VRF_Pos      (2UL)    /*!< C0VRF (Bit 2)                                         */
18616  #define R_ACMPLP_COMPMDR_C0VRF_Msk      (0x4UL)  /*!< C0VRF (Bitfield-Mask: 0x01)                           */
18617  #define R_ACMPLP_COMPMDR_C0ENB_Pos      (0UL)    /*!< C0ENB (Bit 0)                                         */
18618  #define R_ACMPLP_COMPMDR_C0ENB_Msk      (0x1UL)  /*!< C0ENB (Bitfield-Mask: 0x01)                           */
18619 /* ========================================================  COMPFIR  ======================================================== */
18620  #define R_ACMPLP_COMPFIR_C1EDG_Pos      (7UL)    /*!< C1EDG (Bit 7)                                         */
18621  #define R_ACMPLP_COMPFIR_C1EDG_Msk      (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01)                           */
18622  #define R_ACMPLP_COMPFIR_C1EPO_Pos      (6UL)    /*!< C1EPO (Bit 6)                                         */
18623  #define R_ACMPLP_COMPFIR_C1EPO_Msk      (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01)                           */
18624  #define R_ACMPLP_COMPFIR_C1FCK_Pos      (4UL)    /*!< C1FCK (Bit 4)                                         */
18625  #define R_ACMPLP_COMPFIR_C1FCK_Msk      (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03)                           */
18626  #define R_ACMPLP_COMPFIR_C0EDG_Pos      (3UL)    /*!< C0EDG (Bit 3)                                         */
18627  #define R_ACMPLP_COMPFIR_C0EDG_Msk      (0x8UL)  /*!< C0EDG (Bitfield-Mask: 0x01)                           */
18628  #define R_ACMPLP_COMPFIR_C0EPO_Pos      (2UL)    /*!< C0EPO (Bit 2)                                         */
18629  #define R_ACMPLP_COMPFIR_C0EPO_Msk      (0x4UL)  /*!< C0EPO (Bitfield-Mask: 0x01)                           */
18630  #define R_ACMPLP_COMPFIR_C0FCK_Pos      (0UL)    /*!< C0FCK (Bit 0)                                         */
18631  #define R_ACMPLP_COMPFIR_C0FCK_Msk      (0x3UL)  /*!< C0FCK (Bitfield-Mask: 0x03)                           */
18632 /* ========================================================  COMPOCR  ======================================================== */
18633  #define R_ACMPLP_COMPOCR_SPDMD_Pos      (7UL)    /*!< SPDMD (Bit 7)                                         */
18634  #define R_ACMPLP_COMPOCR_SPDMD_Msk      (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01)                           */
18635  #define R_ACMPLP_COMPOCR_C1OP_Pos       (6UL)    /*!< C1OP (Bit 6)                                          */
18636  #define R_ACMPLP_COMPOCR_C1OP_Msk       (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01)                            */
18637  #define R_ACMPLP_COMPOCR_C1OE_Pos       (5UL)    /*!< C1OE (Bit 5)                                          */
18638  #define R_ACMPLP_COMPOCR_C1OE_Msk       (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01)                            */
18639  #define R_ACMPLP_COMPOCR_C0OP_Pos       (2UL)    /*!< C0OP (Bit 2)                                          */
18640  #define R_ACMPLP_COMPOCR_C0OP_Msk       (0x4UL)  /*!< C0OP (Bitfield-Mask: 0x01)                            */
18641  #define R_ACMPLP_COMPOCR_C0OE_Pos       (1UL)    /*!< C0OE (Bit 1)                                          */
18642  #define R_ACMPLP_COMPOCR_C0OE_Msk       (0x2UL)  /*!< C0OE (Bitfield-Mask: 0x01)                            */
18643 /* =======================================================  COMPSEL0  ======================================================== */
18644  #define R_ACMPLP_COMPSEL0_IVCMP1_Pos    (4UL)    /*!< IVCMP1 (Bit 4)                                        */
18645  #define R_ACMPLP_COMPSEL0_IVCMP1_Msk    (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07)                          */
18646  #define R_ACMPLP_COMPSEL0_IVCMP0_Pos    (0UL)    /*!< IVCMP0 (Bit 0)                                        */
18647  #define R_ACMPLP_COMPSEL0_IVCMP0_Msk    (0x7UL)  /*!< IVCMP0 (Bitfield-Mask: 0x07)                          */
18648 /* =======================================================  COMPSEL1  ======================================================== */
18649  #define R_ACMPLP_COMPSEL1_C1VRF2_Pos    (7UL)    /*!< C1VRF2 (Bit 7)                                        */
18650  #define R_ACMPLP_COMPSEL1_C1VRF2_Msk    (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01)                          */
18651  #define R_ACMPLP_COMPSEL1_IVREF1_Pos    (4UL)    /*!< IVREF1 (Bit 4)                                        */
18652  #define R_ACMPLP_COMPSEL1_IVREF1_Msk    (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07)                          */
18653  #define R_ACMPLP_COMPSEL1_IVREF0_Pos    (0UL)    /*!< IVREF0 (Bit 0)                                        */
18654  #define R_ACMPLP_COMPSEL1_IVREF0_Msk    (0x7UL)  /*!< IVREF0 (Bitfield-Mask: 0x07)                          */
18655 
18656 /* =========================================================================================================================== */
18657 /* ================                                          R_ADC0                                           ================ */
18658 /* =========================================================================================================================== */
18659 
18660 /* =========================================================  ADCSR  ========================================================= */
18661  #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
18662  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
18663  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
18664  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
18665  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
18666  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
18667  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
18668  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
18669  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
18670  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
18671  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
18672  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
18673  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
18674  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
18675  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
18676  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
18677  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
18678  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
18679 /* ========================================================  ADANSA  ========================================================= */
18680  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
18681  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
18682 /* =========================================================  ADADS  ========================================================= */
18683  #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
18684  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
18685 /* =========================================================  ADADC  ========================================================= */
18686  #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
18687  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
18688  #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
18689  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
18690 /* =========================================================  ADCER  ========================================================= */
18691  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
18692  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
18693  #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
18694  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
18695  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
18696  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
18697  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
18698  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
18699  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
18700  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
18701  #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
18702  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
18703  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
18704  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
18705  #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
18706  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
18707 /* ========================================================  ADSTRGR  ======================================================== */
18708  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
18709  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
18710  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
18711  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
18712 /* ========================================================  ADEXICR  ======================================================== */
18713  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
18714  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
18715  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
18716  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
18717  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
18718  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
18719  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
18720  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
18721  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
18722  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
18723  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
18724  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
18725  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
18726  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
18727  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
18728  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
18729 /* ========================================================  ADANSB  ========================================================= */
18730  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
18731  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
18732 /* ========================================================  ADDBLDR  ======================================================== */
18733  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
18734  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
18735 /* ========================================================  ADTSDR  ========================================================= */
18736  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
18737  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
18738 /* ========================================================  ADOCDR  ========================================================= */
18739  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
18740  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
18741 /* ======================================================  ADRD_RIGHT  ======================================================= */
18742  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
18743  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
18744  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
18745  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
18746 /* =======================================================  ADRD_LEFT  ======================================================= */
18747  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
18748  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
18749  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
18750  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
18751 /* =========================================================  ADDR  ========================================================== */
18752  #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
18753  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
18754 /* ========================================================  ADSHCR  ========================================================= */
18755  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
18756  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
18757  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
18758  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
18759  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
18760  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
18761  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
18762  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
18763 /* ========================================================  ADDISCR  ======================================================== */
18764  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
18765  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
18766  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
18767  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
18768 /* ========================================================  ADSHMSR  ======================================================== */
18769  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
18770  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
18771 /* ========================================================  ADACSR  ========================================================= */
18772  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
18773  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
18774 /* ========================================================  ADGSPCR  ======================================================== */
18775  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
18776  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
18777  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
18778  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
18779  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
18780  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
18781  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
18782  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
18783 /* =========================================================  ADICR  ========================================================= */
18784  #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
18785  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
18786 /* =======================================================  ADDBLDRA  ======================================================== */
18787  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
18788  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
18789 /* =======================================================  ADDBLDRB  ======================================================== */
18790  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
18791  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
18792 /* ======================================================  ADHVREFCNT  ======================================================= */
18793  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
18794  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
18795  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
18796  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
18797  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
18798  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
18799 /* =======================================================  ADWINMON  ======================================================== */
18800  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
18801  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
18802  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
18803  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
18804  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
18805  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
18806 /* ========================================================  ADCMPCR  ======================================================== */
18807  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
18808  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
18809  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
18810  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
18811  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
18812  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
18813  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
18814  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
18815  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
18816  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
18817  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
18818  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
18819 /* ======================================================  ADCMPANSER  ======================================================= */
18820  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
18821  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
18822  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
18823  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
18824 /* =======================================================  ADCMPLER  ======================================================== */
18825  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
18826  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
18827  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
18828  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
18829 /* =======================================================  ADCMPANSR  ======================================================= */
18830  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
18831  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
18832 /* ========================================================  ADCMPLR  ======================================================== */
18833  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
18834  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
18835 /* =======================================================  ADCMPDR0  ======================================================== */
18836  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
18837  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
18838 /* =======================================================  ADCMPDR1  ======================================================== */
18839  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
18840  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
18841 /* ========================================================  ADCMPSR  ======================================================== */
18842  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
18843  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
18844 /* =======================================================  ADCMPSER  ======================================================== */
18845  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
18846  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
18847  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
18848  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
18849 /* =======================================================  ADCMPBNSR  ======================================================= */
18850  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
18851  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
18852  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
18853  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
18854 /* =======================================================  ADWINLLB  ======================================================== */
18855  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
18856  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
18857 /* =======================================================  ADWINULB  ======================================================== */
18858  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
18859  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
18860 /* =======================================================  ADCMPBSR  ======================================================== */
18861  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
18862  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
18863 /* ========================================================  ADSSTRL  ======================================================== */
18864  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
18865  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
18866 /* ========================================================  ADSSTRT  ======================================================== */
18867  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
18868  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
18869 /* ========================================================  ADSSTRO  ======================================================== */
18870  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
18871  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
18872 /* ========================================================  ADSSTR  ========================================================= */
18873  #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
18874  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
18875 /* ========================================================  ADPGACR  ======================================================== */
18876  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
18877  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
18878  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
18879  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
18880  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
18881  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
18882  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
18883  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
18884  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
18885  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
18886  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
18887  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
18888  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
18889  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
18890  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
18891  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
18892  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
18893  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
18894  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
18895  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
18896  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
18897  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
18898  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
18899  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
18900  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
18901  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
18902  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
18903  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
18904  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
18905  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
18906  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
18907  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
18908 /* =========================================================  ADRD  ========================================================== */
18909  #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
18910  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
18911 /* =========================================================  ADRST  ========================================================= */
18912  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
18913  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
18914 /* ======================================================  VREFAMPCNT  ======================================================= */
18915  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
18916  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
18917  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
18918  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
18919  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
18920  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
18921  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
18922  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
18923  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
18924  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
18925 /* =======================================================  ADCALEXE  ======================================================== */
18926  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
18927  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
18928  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
18929  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
18930 /* ========================================================  ADANIM  ========================================================= */
18931  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
18932  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
18933 /* =======================================================  ADPGAGS0  ======================================================== */
18934  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
18935  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
18936  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
18937  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
18938  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
18939  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
18940  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
18941  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
18942 /* =======================================================  ADPGADCR0  ======================================================= */
18943  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
18944  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
18945  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
18946  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
18947  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
18948  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
18949  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
18950  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
18951  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
18952  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
18953  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
18954  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
18955  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
18956  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
18957  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
18958  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
18959 /* =========================================================  ADREF  ========================================================= */
18960  #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
18961  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
18962  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
18963  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
18964 /* ========================================================  ADEXREF  ======================================================== */
18965  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
18966  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
18967 /* =======================================================  ADAMPOFF  ======================================================== */
18968  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
18969  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
18970 /* ========================================================  ADTSTPR  ======================================================== */
18971  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
18972  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
18973  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
18974  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
18975 /* =======================================================  ADDDACER  ======================================================== */
18976  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
18977  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
18978  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
18979  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
18980  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
18981  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
18982 /* =======================================================  ADEXTSTR  ======================================================== */
18983  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
18984  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
18985  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
18986  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
18987  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
18988  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
18989  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
18990  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
18991  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
18992  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
18993  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
18994  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
18995 /* ========================================================  ADTSTRA  ======================================================== */
18996  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
18997  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
18998  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
18999  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
19000  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
19001  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
19002  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
19003  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
19004  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
19005  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
19006  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
19007  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
19008 /* ========================================================  ADTSTRB  ======================================================== */
19009  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
19010  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
19011 /* ========================================================  ADTSTRC  ======================================================== */
19012  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
19013  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
19014  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
19015  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
19016 /* ========================================================  ADTSTRD  ======================================================== */
19017  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
19018  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
19019 /* =======================================================  ADSWTSTR0  ======================================================= */
19020  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
19021  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
19022  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
19023  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
19024  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
19025  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
19026  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
19027  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
19028  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
19029  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
19030  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
19031  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
19032 /* =======================================================  ADSWTSTR1  ======================================================= */
19033  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
19034  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
19035  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
19036  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
19037  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
19038  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
19039  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
19040  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
19041  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
19042  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
19043  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
19044  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
19045 /* =======================================================  ADSWTSTR2  ======================================================= */
19046  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
19047  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
19048  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
19049  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
19050  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
19051  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
19052  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
19053  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
19054  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
19055  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
19056  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
19057  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
19058  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
19059  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
19060  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
19061  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
19062  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
19063  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
19064  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
19065  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
19066 /* ========================================================  ADSWCR  ========================================================= */
19067  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
19068  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
19069  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
19070  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
19071 /* ========================================================  ADGSCS  ========================================================= */
19072  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
19073  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
19074  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
19075  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
19076 /* =========================================================  ADSER  ========================================================= */
19077  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
19078  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
19079 /* ========================================================  ADBUF0  ========================================================= */
19080  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19081  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19082 /* ========================================================  ADBUF1  ========================================================= */
19083  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19084  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19085 /* ========================================================  ADBUF2  ========================================================= */
19086  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19087  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19088 /* ========================================================  ADBUF3  ========================================================= */
19089  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19090  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19091 /* ========================================================  ADBUF4  ========================================================= */
19092  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19093  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19094 /* ========================================================  ADBUF5  ========================================================= */
19095  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19096  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19097 /* ========================================================  ADBUF6  ========================================================= */
19098  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19099  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19100 /* ========================================================  ADBUF7  ========================================================= */
19101  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19102  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19103 /* ========================================================  ADBUF8  ========================================================= */
19104  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19105  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19106 /* ========================================================  ADBUF9  ========================================================= */
19107  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
19108  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19109 /* ========================================================  ADBUF10  ======================================================== */
19110  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
19111  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19112 /* ========================================================  ADBUF11  ======================================================== */
19113  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
19114  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19115 /* ========================================================  ADBUF12  ======================================================== */
19116  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
19117  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19118 /* ========================================================  ADBUF13  ======================================================== */
19119  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
19120  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19121 /* ========================================================  ADBUF14  ======================================================== */
19122  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
19123  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19124 /* ========================================================  ADBUF15  ======================================================== */
19125  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
19126  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
19127 /* ========================================================  ADBUFEN  ======================================================== */
19128  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
19129  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
19130 /* =======================================================  ADBUFPTR  ======================================================== */
19131  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
19132  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
19133  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
19134  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
19135 /* =======================================================  ADPGADBS0  ======================================================= */
19136  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
19137  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
19138 /* =======================================================  ADPGADBS1  ======================================================= */
19139  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
19140  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
19141 /* =======================================================  ADREFMON  ======================================================== */
19142  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
19143  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
19144  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
19145  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
19146 
19147 /* =========================================================================================================================== */
19148 /* ================                                          R_PSCU                                           ================ */
19149 /* =========================================================================================================================== */
19150 
19151 /* =========================================================  PSARB  ========================================================= */
19152  #define R_PSCU_PSARB_PSARB0_Pos     (0UL)          /*!< PSARB0 (Bit 0)                                        */
19153  #define R_PSCU_PSARB_PSARB0_Msk     (0x1UL)        /*!< PSARB0 (Bitfield-Mask: 0x01)                          */
19154  #define R_PSCU_PSARB_PSARB1_Pos     (1UL)          /*!< PSARB1 (Bit 1)                                        */
19155  #define R_PSCU_PSARB_PSARB1_Msk     (0x2UL)        /*!< PSARB1 (Bitfield-Mask: 0x01)                          */
19156  #define R_PSCU_PSARB_PSARB2_Pos     (2UL)          /*!< PSARB2 (Bit 2)                                        */
19157  #define R_PSCU_PSARB_PSARB2_Msk     (0x4UL)        /*!< PSARB2 (Bitfield-Mask: 0x01)                          */
19158  #define R_PSCU_PSARB_PSARB3_Pos     (3UL)          /*!< PSARB3 (Bit 3)                                        */
19159  #define R_PSCU_PSARB_PSARB3_Msk     (0x8UL)        /*!< PSARB3 (Bitfield-Mask: 0x01)                          */
19160  #define R_PSCU_PSARB_PSARB4_Pos     (4UL)          /*!< PSARB4 (Bit 4)                                        */
19161  #define R_PSCU_PSARB_PSARB4_Msk     (0x10UL)       /*!< PSARB4 (Bitfield-Mask: 0x01)                          */
19162  #define R_PSCU_PSARB_PSARB5_Pos     (5UL)          /*!< PSARB5 (Bit 5)                                        */
19163  #define R_PSCU_PSARB_PSARB5_Msk     (0x20UL)       /*!< PSARB5 (Bitfield-Mask: 0x01)                          */
19164  #define R_PSCU_PSARB_PSARB6_Pos     (6UL)          /*!< PSARB6 (Bit 6)                                        */
19165  #define R_PSCU_PSARB_PSARB6_Msk     (0x40UL)       /*!< PSARB6 (Bitfield-Mask: 0x01)                          */
19166  #define R_PSCU_PSARB_PSARB7_Pos     (7UL)          /*!< PSARB7 (Bit 7)                                        */
19167  #define R_PSCU_PSARB_PSARB7_Msk     (0x80UL)       /*!< PSARB7 (Bitfield-Mask: 0x01)                          */
19168  #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
19169  #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
19170  #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
19171  #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
19172  #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
19173  #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
19174  #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
19175  #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
19176  #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
19177  #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
19178  #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
19179  #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
19180  #define R_PSCU_PSARB_PSARB17_Pos    (17UL)         /*!< PSARB17 (Bit 17)                                      */
19181  #define R_PSCU_PSARB_PSARB17_Msk    (0x20000UL)    /*!< PSARB17 (Bitfield-Mask: 0x01)                         */
19182  #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
19183  #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
19184  #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
19185  #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
19186  #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
19187  #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
19188  #define R_PSCU_PSARB_PSARB23_Pos    (23UL)         /*!< PSARB23 (Bit 23)                                      */
19189  #define R_PSCU_PSARB_PSARB23_Msk    (0x800000UL)   /*!< PSARB23 (Bitfield-Mask: 0x01)                         */
19190  #define R_PSCU_PSARB_PSARB24_Pos    (24UL)         /*!< PSARB24 (Bit 24)                                      */
19191  #define R_PSCU_PSARB_PSARB24_Msk    (0x1000000UL)  /*!< PSARB24 (Bitfield-Mask: 0x01)                         */
19192  #define R_PSCU_PSARB_PSARB25_Pos    (25UL)         /*!< PSARB25 (Bit 25)                                      */
19193  #define R_PSCU_PSARB_PSARB25_Msk    (0x2000000UL)  /*!< PSARB25 (Bitfield-Mask: 0x01)                         */
19194  #define R_PSCU_PSARB_PSARB26_Pos    (26UL)         /*!< PSARB26 (Bit 26)                                      */
19195  #define R_PSCU_PSARB_PSARB26_Msk    (0x4000000UL)  /*!< PSARB26 (Bitfield-Mask: 0x01)                         */
19196  #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
19197  #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
19198  #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
19199  #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
19200  #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
19201  #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
19202  #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
19203  #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
19204  #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
19205  #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
19206 /* =========================================================  PSARC  ========================================================= */
19207  #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
19208  #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
19209  #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
19210  #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
19211  #define R_PSCU_PSARC_PSARC3_Pos     (3UL)          /*!< PSARC3 (Bit 3)                                        */
19212  #define R_PSCU_PSARC_PSARC3_Msk     (0x8UL)        /*!< PSARC3 (Bitfield-Mask: 0x01)                          */
19213  #define R_PSCU_PSARC_PSARC4_Pos     (4UL)          /*!< PSARC4 (Bit 4)                                        */
19214  #define R_PSCU_PSARC_PSARC4_Msk     (0x10UL)       /*!< PSARC4 (Bitfield-Mask: 0x01)                          */
19215  #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
19216  #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
19217  #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
19218  #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
19219  #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
19220  #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
19221  #define R_PSCU_PSARC_PSARC20_Pos    (20UL)         /*!< PSARC20 (Bit 20)                                      */
19222  #define R_PSCU_PSARC_PSARC20_Msk    (0x100000UL)   /*!< PSARC20 (Bitfield-Mask: 0x01)                         */
19223  #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
19224  #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
19225  #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
19226  #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
19227 /* =========================================================  PSARD  ========================================================= */
19228  #define R_PSCU_PSARD_PSARD0_Pos     (0UL)          /*!< PSARD0 (Bit 0)                                        */
19229  #define R_PSCU_PSARD_PSARD0_Msk     (0x1UL)        /*!< PSARD0 (Bitfield-Mask: 0x01)                          */
19230  #define R_PSCU_PSARD_PSARD1_Pos     (1UL)          /*!< PSARD1 (Bit 1)                                        */
19231  #define R_PSCU_PSARD_PSARD1_Msk     (0x2UL)        /*!< PSARD1 (Bitfield-Mask: 0x01)                          */
19232  #define R_PSCU_PSARD_PSARD2_Pos     (2UL)          /*!< PSARD2 (Bit 2)                                        */
19233  #define R_PSCU_PSARD_PSARD2_Msk     (0x4UL)        /*!< PSARD2 (Bitfield-Mask: 0x01)                          */
19234  #define R_PSCU_PSARD_PSARD3_Pos     (3UL)          /*!< PSARD3 (Bit 3)                                        */
19235  #define R_PSCU_PSARD_PSARD3_Msk     (0x8UL)        /*!< PSARD3 (Bitfield-Mask: 0x01)                          */
19236  #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
19237  #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
19238  #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
19239  #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
19240  #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
19241  #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
19242  #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
19243  #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
19244  #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
19245  #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
19246  #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
19247  #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
19248  #define R_PSCU_PSARD_PSARD19_Pos    (19UL)         /*!< PSARD19 (Bit 19)                                      */
19249  #define R_PSCU_PSARD_PSARD19_Msk    (0x80000UL)    /*!< PSARD19 (Bitfield-Mask: 0x01)                         */
19250  #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
19251  #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
19252  #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
19253  #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
19254  #define R_PSCU_PSARD_PSARD25_Pos    (25UL)         /*!< PSARD25 (Bit 25)                                      */
19255  #define R_PSCU_PSARD_PSARD25_Msk    (0x2000000UL)  /*!< PSARD25 (Bitfield-Mask: 0x01)                         */
19256  #define R_PSCU_PSARD_PSARD26_Pos    (26UL)         /*!< PSARD26 (Bit 26)                                      */
19257  #define R_PSCU_PSARD_PSARD26_Msk    (0x4000000UL)  /*!< PSARD26 (Bitfield-Mask: 0x01)                         */
19258  #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
19259  #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
19260  #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
19261  #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
19262  #define R_PSCU_PSARD_PSARD29_Pos    (29UL)         /*!< PSARD29 (Bit 29)                                      */
19263  #define R_PSCU_PSARD_PSARD29_Msk    (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01)                         */
19264 /* =========================================================  PSARE  ========================================================= */
19265  #define R_PSCU_PSARE_PSARE0_Pos     (0UL)          /*!< PSARE0 (Bit 0)                                        */
19266  #define R_PSCU_PSARE_PSARE0_Msk     (0x1UL)        /*!< PSARE0 (Bitfield-Mask: 0x01)                          */
19267  #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
19268  #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
19269  #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
19270  #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
19271  #define R_PSCU_PSARE_PSARE14_Pos    (14UL)         /*!< PSARE14 (Bit 14)                                      */
19272  #define R_PSCU_PSARE_PSARE14_Msk    (0x4000UL)     /*!< PSARE14 (Bitfield-Mask: 0x01)                         */
19273  #define R_PSCU_PSARE_PSARE15_Pos    (15UL)         /*!< PSARE15 (Bit 15)                                      */
19274  #define R_PSCU_PSARE_PSARE15_Msk    (0x8000UL)     /*!< PSARE15 (Bitfield-Mask: 0x01)                         */
19275  #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
19276  #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
19277  #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
19278  #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
19279  #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
19280  #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
19281  #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
19282  #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
19283  #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
19284  #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
19285  #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
19286  #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
19287  #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
19288  #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
19289  #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
19290  #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
19291  #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
19292  #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
19293  #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
19294  #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
19295 /* =========================================================  MSSAR  ========================================================= */
19296  #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
19297  #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
19298  #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
19299  #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
19300  #define R_PSCU_MSSAR_MSSAR2_Pos     (2UL)          /*!< MSSAR2 (Bit 2)                                        */
19301  #define R_PSCU_MSSAR_MSSAR2_Msk     (0x4UL)        /*!< MSSAR2 (Bitfield-Mask: 0x01)                          */
19302  #define R_PSCU_MSSAR_MSSAR3_Pos     (3UL)          /*!< MSSAR3 (Bit 3)                                        */
19303  #define R_PSCU_MSSAR_MSSAR3_Msk     (0x8UL)        /*!< MSSAR3 (Bitfield-Mask: 0x01)                          */
19304  #define R_PSCU_MSSAR_MSSAR4_Pos     (4UL)          /*!< MSSAR4 (Bit 4)                                        */
19305  #define R_PSCU_MSSAR_MSSAR4_Msk     (0x10UL)       /*!< MSSAR4 (Bitfield-Mask: 0x01)                          */
19306 /* =======================================================  CFSAMONA  ======================================================== */
19307  #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
19308  #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
19309 /* =======================================================  CFSAMONB  ======================================================== */
19310  #define R_PSCU_CFSAMONB_CFS1_Pos    (10UL)         /*!< CFS1 (Bit 10)                                         */
19311  #define R_PSCU_CFSAMONB_CFS1_Msk    (0xfffc00UL)   /*!< CFS1 (Bitfield-Mask: 0x3fff)                          */
19312 /* ========================================================  DFSAMON  ======================================================== */
19313  #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
19314  #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
19315 /* ========================================================  SSAMONA  ======================================================== */
19316  #define R_PSCU_SSAMONA_SS2_Pos      (13UL)         /*!< SS2 (Bit 13)                                          */
19317  #define R_PSCU_SSAMONA_SS2_Msk      (0x1fe000UL)   /*!< SS2 (Bitfield-Mask: 0xff)                             */
19318 /* ========================================================  SSAMONB  ======================================================== */
19319  #define R_PSCU_SSAMONB_SS1_Pos      (10UL)         /*!< SS1 (Bit 10)                                          */
19320  #define R_PSCU_SSAMONB_SS1_Msk      (0x1ffc00UL)   /*!< SS1 (Bitfield-Mask: 0x7ff)                            */
19321 /* ========================================================  DLMMON  ========================================================= */
19322  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
19323  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
19324 
19325 /* =========================================================================================================================== */
19326 /* ================                                           R_BUS                                           ================ */
19327 /* =========================================================================================================================== */
19328 
19329 /* ========================================================  CSRECEN  ======================================================== */
19330  #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
19331  #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
19332  #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
19333  #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
19334 /* ========================================================  BUSMABT  ======================================================== */
19335  #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
19336  #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
19337 /* =======================================================  BUSDIVBYP  ======================================================= */
19338  #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
19339  #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
19340  #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
19341  #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
19342  #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
19343  #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
19344 /* =======================================================  BUSTHRPUT  ======================================================= */
19345  #define R_BUS_BUSTHRPUT_DIS_Pos         (0UL)       /*!< DIS (Bit 0)                                           */
19346  #define R_BUS_BUSTHRPUT_DIS_Msk         (0x1UL)     /*!< DIS (Bitfield-Mask: 0x01)                             */
19347 
19348 /* =========================================================================================================================== */
19349 /* ================                                           R_CAC                                           ================ */
19350 /* =========================================================================================================================== */
19351 
19352 /* =========================================================  CACR0  ========================================================= */
19353  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
19354  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
19355 /* =========================================================  CACR1  ========================================================= */
19356  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
19357  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
19358  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
19359  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
19360  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
19361  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
19362  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
19363  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
19364 /* =========================================================  CACR2  ========================================================= */
19365  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
19366  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
19367  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
19368  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
19369  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
19370  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
19371  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
19372  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
19373 /* =========================================================  CAICR  ========================================================= */
19374  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
19375  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
19376  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
19377  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
19378  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
19379  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
19380  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
19381  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
19382  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
19383  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
19384  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
19385  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
19386 /* =========================================================  CASTR  ========================================================= */
19387  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
19388  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
19389  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
19390  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
19391  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
19392  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
19393 /* ========================================================  CAULVR  ========================================================= */
19394  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
19395  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
19396 /* ========================================================  CALLVR  ========================================================= */
19397  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
19398  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
19399 /* ========================================================  CACNTBR  ======================================================== */
19400  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
19401  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
19402 
19403 /* =========================================================================================================================== */
19404 /* ================                                         R_CANFD0                                          ================ */
19405 /* =========================================================================================================================== */
19406 
19407 /* ========================================================  CFDGCFG  ======================================================== */
19408  #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
19409  #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
19410  #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
19411  #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
19412  #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
19413  #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
19414  #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
19415  #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
19416  #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
19417  #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
19418  #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
19419  #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
19420  #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
19421  #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
19422  #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
19423  #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
19424  #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
19425  #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
19426 /* ========================================================  CFDGCTR  ======================================================== */
19427  #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
19428  #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
19429  #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
19430  #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
19431  #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
19432  #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
19433  #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
19434  #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
19435  #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
19436  #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
19437  #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
19438  #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
19439  #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
19440  #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
19441 /* ========================================================  CFDGSTS  ======================================================== */
19442  #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
19443  #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
19444  #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
19445  #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
19446  #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
19447  #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
19448  #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
19449  #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
19450 /* =======================================================  CFDGERFL  ======================================================== */
19451  #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
19452  #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
19453  #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
19454  #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
19455  #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
19456  #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
19457  #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
19458  #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
19459  #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
19460  #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
19461 /* ========================================================  CFDGTSC  ======================================================== */
19462  #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
19463  #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
19464 /* ======================================================  CFDGAFLECTR  ====================================================== */
19465  #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
19466  #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
19467  #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
19468  #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
19469 /* ======================================================  CFDGAFLCFG0  ====================================================== */
19470  #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
19471  #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
19472  #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
19473  #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
19474 /* ========================================================  CFDRMNB  ======================================================== */
19475  #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
19476  #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
19477  #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
19478  #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
19479 /* =======================================================  CFDRMND0  ======================================================== */
19480  #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
19481  #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
19482 /* =======================================================  CFDRMIEC  ======================================================== */
19483  #define R_CANFD_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
19484  #define R_CANFD_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
19485 /* ========================================================  CFDRFCC  ======================================================== */
19486  #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
19487  #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
19488  #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
19489  #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
19490  #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
19491  #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
19492  #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
19493  #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
19494  #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
19495  #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
19496  #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
19497  #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
19498 /* =======================================================  CFDRFSTS  ======================================================== */
19499  #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
19500  #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
19501  #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
19502  #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
19503  #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
19504  #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
19505  #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
19506  #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
19507  #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
19508  #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
19509 /* =======================================================  CFDRFPCTR  ======================================================= */
19510  #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
19511  #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
19512 /* ========================================================  CFDCFCC  ======================================================== */
19513  #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
19514  #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
19515  #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
19516  #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
19517  #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
19518  #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
19519  #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
19520  #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
19521  #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
19522  #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
19523  #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
19524  #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
19525  #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
19526  #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
19527  #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
19528  #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
19529  #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
19530  #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
19531  #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
19532  #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
19533  #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
19534  #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
19535  #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
19536  #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
19537 /* =======================================================  CFDCFSTS  ======================================================== */
19538  #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
19539  #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
19540  #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
19541  #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
19542  #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
19543  #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
19544  #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
19545  #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
19546  #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
19547  #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
19548  #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
19549  #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
19550 /* =======================================================  CFDCFPCTR  ======================================================= */
19551  #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
19552  #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
19553 /* =======================================================  CFDFESTS  ======================================================== */
19554  #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
19555  #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
19556  #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
19557  #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
19558 /* =======================================================  CFDFFSTS  ======================================================== */
19559  #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
19560  #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
19561  #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
19562  #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
19563 /* =======================================================  CFDFMSTS  ======================================================== */
19564  #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
19565  #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
19566  #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
19567  #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
19568 /* =======================================================  CFDRFISTS  ======================================================= */
19569  #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
19570  #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0x3UL)        /*!< RFXIF (Bitfield-Mask: 0x03)                           */
19571 /* ========================================================  CFDTMC  ========================================================= */
19572  #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
19573  #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
19574  #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
19575  #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
19576  #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
19577  #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
19578 /* =======================================================  CFDTMSTS  ======================================================== */
19579  #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
19580  #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
19581  #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
19582  #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
19583  #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
19584  #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
19585  #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
19586  #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
19587 /* ======================================================  CFDTMTRSTS  ======================================================= */
19588  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
19589  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
19590 /* ======================================================  CFDTMTARSTS  ====================================================== */
19591  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
19592  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
19593 /* ======================================================  CFDTMTCSTS  ======================================================= */
19594  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
19595  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
19596 /* ======================================================  CFDTMTASTS  ======================================================= */
19597  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
19598  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
19599 /* =======================================================  CFDTMIEC  ======================================================== */
19600  #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
19601  #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
19602 /* =======================================================  CFDTXQCC0  ======================================================= */
19603  #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
19604  #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
19605  #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
19606  #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
19607  #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
19608  #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
19609  #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
19610  #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
19611 /* ======================================================  CFDTXQSTS0  ======================================================= */
19612  #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
19613  #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
19614  #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
19615  #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
19616  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
19617  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
19618  #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
19619  #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
19620 /* ======================================================  CFDTXQPCTR0  ====================================================== */
19621  #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
19622  #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
19623 /* =======================================================  CFDTHLCC  ======================================================== */
19624  #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
19625  #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
19626  #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
19627  #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
19628  #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
19629  #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
19630  #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
19631  #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
19632 /* =======================================================  CFDTHLSTS  ======================================================= */
19633  #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
19634  #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
19635  #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
19636  #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
19637  #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
19638  #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
19639  #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
19640  #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
19641  #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
19642  #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
19643 /* ======================================================  CFDTHLPCTR  ======================================================= */
19644  #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
19645  #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
19646 /* =====================================================  CFDGTINTSTS0  ====================================================== */
19647  #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
19648  #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
19649  #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
19650  #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
19651  #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
19652  #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
19653  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
19654  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
19655  #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
19656  #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
19657 /* ======================================================  CFDGTSTCFG  ======================================================= */
19658  #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
19659  #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
19660 /* ======================================================  CFDGTSTCTR  ======================================================= */
19661  #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
19662  #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
19663 /* =======================================================  CFDGFDCFG  ======================================================= */
19664  #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
19665  #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
19666  #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
19667  #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
19668 /* =======================================================  CFDGLOCKK  ======================================================= */
19669  #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
19670  #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
19671 /* =====================================================  CFDGAFLIGNENT  ===================================================== */
19672  #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
19673  #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
19674 /* =====================================================  CFDGAFLIGNCTR  ===================================================== */
19675  #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
19676  #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
19677  #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
19678  #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
19679 /* =======================================================  CFDCDTCT  ======================================================== */
19680  #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
19681  #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
19682  #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
19683  #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
19684  #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
19685  #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
19686 /* =======================================================  CFDCDTSTS  ======================================================= */
19687  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
19688  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
19689  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
19690  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
19691  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
19692  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
19693 /* =======================================================  CFDGRSTC  ======================================================== */
19694  #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
19695  #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
19696  #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
19697  #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
19698 /* =======================================================  CFDRPGACC  ======================================================= */
19699  #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
19700  #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
19701 
19702 /* =========================================================================================================================== */
19703 /* ================                                           R_CRC                                           ================ */
19704 /* =========================================================================================================================== */
19705 
19706 /* ========================================================  CRCCR0  ========================================================= */
19707  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
19708  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
19709  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
19710  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
19711  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
19712  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
19713 /* ========================================================  CRCCR1  ========================================================= */
19714  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
19715  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
19716  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
19717  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
19718 /* ========================================================  CRCDIR  ========================================================= */
19719  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
19720  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
19721 /* =======================================================  CRCDIR_BY  ======================================================= */
19722  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
19723  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
19724 /* ========================================================  CRCDOR  ========================================================= */
19725  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
19726  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
19727 /* =======================================================  CRCDOR_HA  ======================================================= */
19728  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
19729  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
19730 /* =======================================================  CRCDOR_BY  ======================================================= */
19731  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
19732  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
19733 /* ========================================================  CRCSAR  ========================================================= */
19734  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
19735  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
19736 
19737 /* =========================================================================================================================== */
19738 /* ================                                          R_CTSU2                                          ================ */
19739 /* =========================================================================================================================== */
19740 
19741 /* ========================================================  CTSUCRA  ======================================================== */
19742  #define R_CTSU2_CTSUCRA_STRT_Pos      (0UL)          /*!< STRT (Bit 0)                                          */
19743  #define R_CTSU2_CTSUCRA_STRT_Msk      (0x1UL)        /*!< STRT (Bitfield-Mask: 0x01)                            */
19744  #define R_CTSU2_CTSUCRA_CAP_Pos       (1UL)          /*!< CAP (Bit 1)                                           */
19745  #define R_CTSU2_CTSUCRA_CAP_Msk       (0x2UL)        /*!< CAP (Bitfield-Mask: 0x01)                             */
19746  #define R_CTSU2_CTSUCRA_SNZ_Pos       (2UL)          /*!< SNZ (Bit 2)                                           */
19747  #define R_CTSU2_CTSUCRA_SNZ_Msk       (0x4UL)        /*!< SNZ (Bitfield-Mask: 0x01)                             */
19748  #define R_CTSU2_CTSUCRA_CFCON_Pos     (3UL)          /*!< CFCON (Bit 3)                                         */
19749  #define R_CTSU2_CTSUCRA_CFCON_Msk     (0x8UL)        /*!< CFCON (Bitfield-Mask: 0x01)                           */
19750  #define R_CTSU2_CTSUCRA_INIT_Pos      (4UL)          /*!< INIT (Bit 4)                                          */
19751  #define R_CTSU2_CTSUCRA_INIT_Msk      (0x10UL)       /*!< INIT (Bitfield-Mask: 0x01)                            */
19752  #define R_CTSU2_CTSUCRA_PUMPON_Pos    (5UL)          /*!< PUMPON (Bit 5)                                        */
19753  #define R_CTSU2_CTSUCRA_PUMPON_Msk    (0x20UL)       /*!< PUMPON (Bitfield-Mask: 0x01)                          */
19754  #define R_CTSU2_CTSUCRA_TXVSEL_Pos    (6UL)          /*!< TXVSEL (Bit 6)                                        */
19755  #define R_CTSU2_CTSUCRA_TXVSEL_Msk    (0xc0UL)       /*!< TXVSEL (Bitfield-Mask: 0x03)                          */
19756  #define R_CTSU2_CTSUCRA_PON_Pos       (8UL)          /*!< PON (Bit 8)                                           */
19757  #define R_CTSU2_CTSUCRA_PON_Msk       (0x100UL)      /*!< PON (Bitfield-Mask: 0x01)                             */
19758  #define R_CTSU2_CTSUCRA_CSW_Pos       (9UL)          /*!< CSW (Bit 9)                                           */
19759  #define R_CTSU2_CTSUCRA_CSW_Msk       (0x200UL)      /*!< CSW (Bitfield-Mask: 0x01)                             */
19760  #define R_CTSU2_CTSUCRA_ATUNE0_Pos    (10UL)         /*!< ATUNE0 (Bit 10)                                       */
19761  #define R_CTSU2_CTSUCRA_ATUNE0_Msk    (0x400UL)      /*!< ATUNE0 (Bitfield-Mask: 0x01)                          */
19762  #define R_CTSU2_CTSUCRA_ATUNE1_Pos    (11UL)         /*!< ATUNE1 (Bit 11)                                       */
19763  #define R_CTSU2_CTSUCRA_ATUNE1_Msk    (0x800UL)      /*!< ATUNE1 (Bitfield-Mask: 0x01)                          */
19764  #define R_CTSU2_CTSUCRA_CLK_Pos       (12UL)         /*!< CLK (Bit 12)                                          */
19765  #define R_CTSU2_CTSUCRA_CLK_Msk       (0x3000UL)     /*!< CLK (Bitfield-Mask: 0x03)                             */
19766  #define R_CTSU2_CTSUCRA_MD0_Pos       (14UL)         /*!< MD0 (Bit 14)                                          */
19767  #define R_CTSU2_CTSUCRA_MD0_Msk       (0x4000UL)     /*!< MD0 (Bitfield-Mask: 0x01)                             */
19768  #define R_CTSU2_CTSUCRA_MD1_Pos       (15UL)         /*!< MD1 (Bit 15)                                          */
19769  #define R_CTSU2_CTSUCRA_MD1_Msk       (0x8000UL)     /*!< MD1 (Bitfield-Mask: 0x01)                             */
19770  #define R_CTSU2_CTSUCRA_MD2_Pos       (16UL)         /*!< MD2 (Bit 16)                                          */
19771  #define R_CTSU2_CTSUCRA_MD2_Msk       (0x10000UL)    /*!< MD2 (Bitfield-Mask: 0x01)                             */
19772  #define R_CTSU2_CTSUCRA_ATUNE2_Pos    (17UL)         /*!< ATUNE2 (Bit 17)                                       */
19773  #define R_CTSU2_CTSUCRA_ATUNE2_Msk    (0x20000UL)    /*!< ATUNE2 (Bitfield-Mask: 0x01)                          */
19774  #define R_CTSU2_CTSUCRA_LOAD_Pos      (18UL)         /*!< LOAD (Bit 18)                                         */
19775  #define R_CTSU2_CTSUCRA_LOAD_Msk      (0xc0000UL)    /*!< LOAD (Bitfield-Mask: 0x03)                            */
19776  #define R_CTSU2_CTSUCRA_POSEL_Pos     (20UL)         /*!< POSEL (Bit 20)                                        */
19777  #define R_CTSU2_CTSUCRA_POSEL_Msk     (0x300000UL)   /*!< POSEL (Bitfield-Mask: 0x03)                           */
19778  #define R_CTSU2_CTSUCRA_SDPSEL_Pos    (22UL)         /*!< SDPSEL (Bit 22)                                       */
19779  #define R_CTSU2_CTSUCRA_SDPSEL_Msk    (0x400000UL)   /*!< SDPSEL (Bitfield-Mask: 0x01)                          */
19780  #define R_CTSU2_CTSUCRA_PCSEL_Pos     (23UL)         /*!< PCSEL (Bit 23)                                        */
19781  #define R_CTSU2_CTSUCRA_PCSEL_Msk     (0x800000UL)   /*!< PCSEL (Bitfield-Mask: 0x01)                           */
19782  #define R_CTSU2_CTSUCRA_STCLK_Pos     (24UL)         /*!< STCLK (Bit 24)                                        */
19783  #define R_CTSU2_CTSUCRA_STCLK_Msk     (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f)                           */
19784  #define R_CTSU2_CTSUCRA_DCMODE_Pos    (30UL)         /*!< DCMODE (Bit 30)                                       */
19785  #define R_CTSU2_CTSUCRA_DCMODE_Msk    (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01)                          */
19786  #define R_CTSU2_CTSUCRA_DCBACK_Pos    (31UL)         /*!< DCBACK (Bit 31)                                       */
19787  #define R_CTSU2_CTSUCRA_DCBACK_Msk    (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01)                          */
19788 /* =======================================================  CTSUCRAL  ======================================================== */
19789 /* ========================================================  CTSUCR0  ======================================================== */
19790 /* ========================================================  CTSUCR1  ======================================================== */
19791 /* =======================================================  CTSUCRAH  ======================================================== */
19792 /* ========================================================  CTSUCR2  ======================================================== */
19793 /* ========================================================  CTSUCR3  ======================================================== */
19794 /* ========================================================  CTSUCRB  ======================================================== */
19795  #define R_CTSU2_CTSUCRB_PRRATIO_Pos    (0UL)          /*!< PRRATIO (Bit 0)                                       */
19796  #define R_CTSU2_CTSUCRB_PRRATIO_Msk    (0xfUL)        /*!< PRRATIO (Bitfield-Mask: 0x0f)                         */
19797  #define R_CTSU2_CTSUCRB_PRMODE_Pos     (4UL)          /*!< PRMODE (Bit 4)                                        */
19798  #define R_CTSU2_CTSUCRB_PRMODE_Msk     (0x30UL)       /*!< PRMODE (Bitfield-Mask: 0x03)                          */
19799  #define R_CTSU2_CTSUCRB_SOFF_Pos       (6UL)          /*!< SOFF (Bit 6)                                          */
19800  #define R_CTSU2_CTSUCRB_SOFF_Msk       (0x40UL)       /*!< SOFF (Bitfield-Mask: 0x01)                            */
19801  #define R_CTSU2_CTSUCRB_PROFF_Pos      (7UL)          /*!< PROFF (Bit 7)                                         */
19802  #define R_CTSU2_CTSUCRB_PROFF_Msk      (0x80UL)       /*!< PROFF (Bitfield-Mask: 0x01)                           */
19803  #define R_CTSU2_CTSUCRB_SST_Pos        (8UL)          /*!< SST (Bit 8)                                           */
19804  #define R_CTSU2_CTSUCRB_SST_Msk        (0xff00UL)     /*!< SST (Bitfield-Mask: 0xff)                             */
19805  #define R_CTSU2_CTSUCRB_SSMOD_Pos      (24UL)         /*!< SSMOD (Bit 24)                                        */
19806  #define R_CTSU2_CTSUCRB_SSMOD_Msk      (0x7000000UL)  /*!< SSMOD (Bitfield-Mask: 0x07)                           */
19807  #define R_CTSU2_CTSUCRB_SSCNT_Pos      (28UL)         /*!< SSCNT (Bit 28)                                        */
19808  #define R_CTSU2_CTSUCRB_SSCNT_Msk      (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03)                           */
19809 /* =======================================================  CTSUCRBL  ======================================================== */
19810 /* =======================================================  CTSUSDPRS  ======================================================= */
19811 /* ========================================================  CTSUSST  ======================================================== */
19812 /* =======================================================  CTSUCRBH  ======================================================== */
19813 /* =======================================================  CTSUDCLKC  ======================================================= */
19814 /* ========================================================  CTSUMCH  ======================================================== */
19815  #define R_CTSU2_CTSUMCH_MCH0_Pos    (0UL)       /*!< MCH0 (Bit 0)                                          */
19816  #define R_CTSU2_CTSUMCH_MCH0_Msk    (0x3fUL)    /*!< MCH0 (Bitfield-Mask: 0x3f)                            */
19817  #define R_CTSU2_CTSUMCH_MCH1_Pos    (8UL)       /*!< MCH1 (Bit 8)                                          */
19818  #define R_CTSU2_CTSUMCH_MCH1_Msk    (0x3f00UL)  /*!< MCH1 (Bitfield-Mask: 0x3f)                            */
19819  #define R_CTSU2_CTSUMCH_MCA0_Pos    (16UL)      /*!< MCA0 (Bit 16)                                         */
19820  #define R_CTSU2_CTSUMCH_MCA0_Msk    (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01)                            */
19821  #define R_CTSU2_CTSUMCH_MCA1_Pos    (17UL)      /*!< MCA1 (Bit 17)                                         */
19822  #define R_CTSU2_CTSUMCH_MCA1_Msk    (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01)                            */
19823  #define R_CTSU2_CTSUMCH_MCA2_Pos    (18UL)      /*!< MCA2 (Bit 18)                                         */
19824  #define R_CTSU2_CTSUMCH_MCA2_Msk    (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01)                            */
19825  #define R_CTSU2_CTSUMCH_MCA3_Pos    (19UL)      /*!< MCA3 (Bit 19)                                         */
19826  #define R_CTSU2_CTSUMCH_MCA3_Msk    (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01)                            */
19827 /* =======================================================  CTSUMCHL  ======================================================== */
19828 /* =======================================================  CTSUMCH0  ======================================================== */
19829 /* =======================================================  CTSUMCH1  ======================================================== */
19830 /* =======================================================  CTSUMCHH  ======================================================== */
19831 /* =======================================================  CTSUMFAF  ======================================================== */
19832 /* =======================================================  CTSUCHACA  ======================================================= */
19833  #define R_CTSU2_CTSUCHACA_CHAC00_Pos    (0UL)          /*!< CHAC00 (Bit 0)                                        */
19834  #define R_CTSU2_CTSUCHACA_CHAC00_Msk    (0x1UL)        /*!< CHAC00 (Bitfield-Mask: 0x01)                          */
19835  #define R_CTSU2_CTSUCHACA_CHAC01_Pos    (1UL)          /*!< CHAC01 (Bit 1)                                        */
19836  #define R_CTSU2_CTSUCHACA_CHAC01_Msk    (0x2UL)        /*!< CHAC01 (Bitfield-Mask: 0x01)                          */
19837  #define R_CTSU2_CTSUCHACA_CHAC02_Pos    (2UL)          /*!< CHAC02 (Bit 2)                                        */
19838  #define R_CTSU2_CTSUCHACA_CHAC02_Msk    (0x4UL)        /*!< CHAC02 (Bitfield-Mask: 0x01)                          */
19839  #define R_CTSU2_CTSUCHACA_CHAC03_Pos    (3UL)          /*!< CHAC03 (Bit 3)                                        */
19840  #define R_CTSU2_CTSUCHACA_CHAC03_Msk    (0x8UL)        /*!< CHAC03 (Bitfield-Mask: 0x01)                          */
19841  #define R_CTSU2_CTSUCHACA_CHAC04_Pos    (4UL)          /*!< CHAC04 (Bit 4)                                        */
19842  #define R_CTSU2_CTSUCHACA_CHAC04_Msk    (0x10UL)       /*!< CHAC04 (Bitfield-Mask: 0x01)                          */
19843  #define R_CTSU2_CTSUCHACA_CHAC05_Pos    (5UL)          /*!< CHAC05 (Bit 5)                                        */
19844  #define R_CTSU2_CTSUCHACA_CHAC05_Msk    (0x20UL)       /*!< CHAC05 (Bitfield-Mask: 0x01)                          */
19845  #define R_CTSU2_CTSUCHACA_CHAC06_Pos    (6UL)          /*!< CHAC06 (Bit 6)                                        */
19846  #define R_CTSU2_CTSUCHACA_CHAC06_Msk    (0x40UL)       /*!< CHAC06 (Bitfield-Mask: 0x01)                          */
19847  #define R_CTSU2_CTSUCHACA_CHAC07_Pos    (7UL)          /*!< CHAC07 (Bit 7)                                        */
19848  #define R_CTSU2_CTSUCHACA_CHAC07_Msk    (0x80UL)       /*!< CHAC07 (Bitfield-Mask: 0x01)                          */
19849  #define R_CTSU2_CTSUCHACA_CHAC08_Pos    (8UL)          /*!< CHAC08 (Bit 8)                                        */
19850  #define R_CTSU2_CTSUCHACA_CHAC08_Msk    (0x100UL)      /*!< CHAC08 (Bitfield-Mask: 0x01)                          */
19851  #define R_CTSU2_CTSUCHACA_CHAC09_Pos    (9UL)          /*!< CHAC09 (Bit 9)                                        */
19852  #define R_CTSU2_CTSUCHACA_CHAC09_Msk    (0x200UL)      /*!< CHAC09 (Bitfield-Mask: 0x01)                          */
19853  #define R_CTSU2_CTSUCHACA_CHAC10_Pos    (10UL)         /*!< CHAC10 (Bit 10)                                       */
19854  #define R_CTSU2_CTSUCHACA_CHAC10_Msk    (0x400UL)      /*!< CHAC10 (Bitfield-Mask: 0x01)                          */
19855  #define R_CTSU2_CTSUCHACA_CHAC11_Pos    (11UL)         /*!< CHAC11 (Bit 11)                                       */
19856  #define R_CTSU2_CTSUCHACA_CHAC11_Msk    (0x800UL)      /*!< CHAC11 (Bitfield-Mask: 0x01)                          */
19857  #define R_CTSU2_CTSUCHACA_CHAC12_Pos    (12UL)         /*!< CHAC12 (Bit 12)                                       */
19858  #define R_CTSU2_CTSUCHACA_CHAC12_Msk    (0x1000UL)     /*!< CHAC12 (Bitfield-Mask: 0x01)                          */
19859  #define R_CTSU2_CTSUCHACA_CHAC13_Pos    (13UL)         /*!< CHAC13 (Bit 13)                                       */
19860  #define R_CTSU2_CTSUCHACA_CHAC13_Msk    (0x2000UL)     /*!< CHAC13 (Bitfield-Mask: 0x01)                          */
19861  #define R_CTSU2_CTSUCHACA_CHAC14_Pos    (14UL)         /*!< CHAC14 (Bit 14)                                       */
19862  #define R_CTSU2_CTSUCHACA_CHAC14_Msk    (0x4000UL)     /*!< CHAC14 (Bitfield-Mask: 0x01)                          */
19863  #define R_CTSU2_CTSUCHACA_CHAC15_Pos    (15UL)         /*!< CHAC15 (Bit 15)                                       */
19864  #define R_CTSU2_CTSUCHACA_CHAC15_Msk    (0x8000UL)     /*!< CHAC15 (Bitfield-Mask: 0x01)                          */
19865  #define R_CTSU2_CTSUCHACA_CHAC16_Pos    (16UL)         /*!< CHAC16 (Bit 16)                                       */
19866  #define R_CTSU2_CTSUCHACA_CHAC16_Msk    (0x10000UL)    /*!< CHAC16 (Bitfield-Mask: 0x01)                          */
19867  #define R_CTSU2_CTSUCHACA_CHAC17_Pos    (17UL)         /*!< CHAC17 (Bit 17)                                       */
19868  #define R_CTSU2_CTSUCHACA_CHAC17_Msk    (0x20000UL)    /*!< CHAC17 (Bitfield-Mask: 0x01)                          */
19869  #define R_CTSU2_CTSUCHACA_CHAC18_Pos    (18UL)         /*!< CHAC18 (Bit 18)                                       */
19870  #define R_CTSU2_CTSUCHACA_CHAC18_Msk    (0x40000UL)    /*!< CHAC18 (Bitfield-Mask: 0x01)                          */
19871  #define R_CTSU2_CTSUCHACA_CHAC21_Pos    (21UL)         /*!< CHAC21 (Bit 21)                                       */
19872  #define R_CTSU2_CTSUCHACA_CHAC21_Msk    (0x200000UL)   /*!< CHAC21 (Bitfield-Mask: 0x01)                          */
19873  #define R_CTSU2_CTSUCHACA_CHAC22_Pos    (22UL)         /*!< CHAC22 (Bit 22)                                       */
19874  #define R_CTSU2_CTSUCHACA_CHAC22_Msk    (0x400000UL)   /*!< CHAC22 (Bitfield-Mask: 0x01)                          */
19875  #define R_CTSU2_CTSUCHACA_CHAC23_Pos    (23UL)         /*!< CHAC23 (Bit 23)                                       */
19876  #define R_CTSU2_CTSUCHACA_CHAC23_Msk    (0x800000UL)   /*!< CHAC23 (Bitfield-Mask: 0x01)                          */
19877  #define R_CTSU2_CTSUCHACA_CHAC24_Pos    (24UL)         /*!< CHAC24 (Bit 24)                                       */
19878  #define R_CTSU2_CTSUCHACA_CHAC24_Msk    (0x1000000UL)  /*!< CHAC24 (Bitfield-Mask: 0x01)                          */
19879  #define R_CTSU2_CTSUCHACA_CHAC25_Pos    (25UL)         /*!< CHAC25 (Bit 25)                                       */
19880  #define R_CTSU2_CTSUCHACA_CHAC25_Msk    (0x2000000UL)  /*!< CHAC25 (Bitfield-Mask: 0x01)                          */
19881  #define R_CTSU2_CTSUCHACA_CHAC26_Pos    (26UL)         /*!< CHAC26 (Bit 26)                                       */
19882  #define R_CTSU2_CTSUCHACA_CHAC26_Msk    (0x4000000UL)  /*!< CHAC26 (Bitfield-Mask: 0x01)                          */
19883  #define R_CTSU2_CTSUCHACA_CHAC27_Pos    (27UL)         /*!< CHAC27 (Bit 27)                                       */
19884  #define R_CTSU2_CTSUCHACA_CHAC27_Msk    (0x8000000UL)  /*!< CHAC27 (Bitfield-Mask: 0x01)                          */
19885  #define R_CTSU2_CTSUCHACA_CHAC28_Pos    (28UL)         /*!< CHAC28 (Bit 28)                                       */
19886  #define R_CTSU2_CTSUCHACA_CHAC28_Msk    (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01)                          */
19887  #define R_CTSU2_CTSUCHACA_CHAC29_Pos    (29UL)         /*!< CHAC29 (Bit 29)                                       */
19888  #define R_CTSU2_CTSUCHACA_CHAC29_Msk    (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01)                          */
19889  #define R_CTSU2_CTSUCHACA_CHAC30_Pos    (30UL)         /*!< CHAC30 (Bit 30)                                       */
19890  #define R_CTSU2_CTSUCHACA_CHAC30_Msk    (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01)                          */
19891  #define R_CTSU2_CTSUCHACA_CHAC31_Pos    (31UL)         /*!< CHAC31 (Bit 31)                                       */
19892  #define R_CTSU2_CTSUCHACA_CHAC31_Msk    (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01)                          */
19893 /* ======================================================  CTSUCHACAL  ======================================================= */
19894 /* =======================================================  CTSUCHAC0  ======================================================= */
19895 /* =======================================================  CTSUCHAC1  ======================================================= */
19896 /* ======================================================  CTSUCHACAH  ======================================================= */
19897 /* =======================================================  CTSUCHAC2  ======================================================= */
19898 /* =======================================================  CTSUCHAC3  ======================================================= */
19899 /* =======================================================  CTSUCHACB  ======================================================= */
19900  #define R_CTSU2_CTSUCHACB_CHAC32_Pos      (0UL)          /*!< CHAC32 (Bit 0)                                        */
19901  #define R_CTSU2_CTSUCHACB_CHAC32_Msk      (0x1UL)        /*!< CHAC32 (Bitfield-Mask: 0x01)                          */
19902  #define R_CTSU2_CTSUCHACB_CHAC33_Pos      (1UL)          /*!< CHAC33 (Bit 1)                                        */
19903  #define R_CTSU2_CTSUCHACB_CHAC33_Msk      (0x2UL)        /*!< CHAC33 (Bitfield-Mask: 0x01)                          */
19904  #define R_CTSU2_CTSUCHACB_CHAC34_Pos      (2UL)          /*!< CHAC34 (Bit 2)                                        */
19905  #define R_CTSU2_CTSUCHACB_CHAC34_Msk      (0x4UL)        /*!< CHAC34 (Bitfield-Mask: 0x01)                          */
19906  #define R_CTSU2_CTSUCHACB_CHAC35_Pos      (3UL)          /*!< CHAC35 (Bit 3)                                        */
19907  #define R_CTSU2_CTSUCHACB_CHAC35_Msk      (0x8UL)        /*!< CHAC35 (Bitfield-Mask: 0x01)                          */
19908 /* ======================================================  CTSUCHACBL  ======================================================= */
19909 /* =======================================================  CTSUCHAC4  ======================================================= */
19910 /* ======================================================  CTSUCHTRCA  ======================================================= */
19911  #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos      (0UL)          /*!< CHTRC (Bit 0)                                         */
19912  #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk      (0x1UL)        /*!< CHTRC (Bitfield-Mask: 0x01)                           */
19913  #define R_CTSU2_CTSUCHTRCA_CHTRC01_Pos    (1UL)          /*!< CHTRC01 (Bit 1)                                       */
19914  #define R_CTSU2_CTSUCHTRCA_CHTRC01_Msk    (0x2UL)        /*!< CHTRC01 (Bitfield-Mask: 0x01)                         */
19915  #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos    (2UL)          /*!< CHTRC02 (Bit 2)                                       */
19916  #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk    (0x4UL)        /*!< CHTRC02 (Bitfield-Mask: 0x01)                         */
19917  #define R_CTSU2_CTSUCHTRCA_CHTRC03_Pos    (3UL)          /*!< CHTRC03 (Bit 3)                                       */
19918  #define R_CTSU2_CTSUCHTRCA_CHTRC03_Msk    (0x8UL)        /*!< CHTRC03 (Bitfield-Mask: 0x01)                         */
19919  #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos    (4UL)          /*!< CHTRC04 (Bit 4)                                       */
19920  #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk    (0x10UL)       /*!< CHTRC04 (Bitfield-Mask: 0x01)                         */
19921  #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos    (5UL)          /*!< CHTRC05 (Bit 5)                                       */
19922  #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk    (0x20UL)       /*!< CHTRC05 (Bitfield-Mask: 0x01)                         */
19923  #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos    (6UL)          /*!< CHTRC06 (Bit 6)                                       */
19924  #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk    (0x40UL)       /*!< CHTRC06 (Bitfield-Mask: 0x01)                         */
19925  #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos    (7UL)          /*!< CHTRC07 (Bit 7)                                       */
19926  #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk    (0x80UL)       /*!< CHTRC07 (Bitfield-Mask: 0x01)                         */
19927  #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos    (8UL)          /*!< CHTRC08 (Bit 8)                                       */
19928  #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk    (0x100UL)      /*!< CHTRC08 (Bitfield-Mask: 0x01)                         */
19929  #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos    (9UL)          /*!< CHTRC09 (Bit 9)                                       */
19930  #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk    (0x200UL)      /*!< CHTRC09 (Bitfield-Mask: 0x01)                         */
19931  #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos    (10UL)         /*!< CHTRC10 (Bit 10)                                      */
19932  #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk    (0x400UL)      /*!< CHTRC10 (Bitfield-Mask: 0x01)                         */
19933  #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos    (11UL)         /*!< CHTRC11 (Bit 11)                                      */
19934  #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk    (0x800UL)      /*!< CHTRC11 (Bitfield-Mask: 0x01)                         */
19935  #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos    (12UL)         /*!< CHTRC12 (Bit 12)                                      */
19936  #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk    (0x1000UL)     /*!< CHTRC12 (Bitfield-Mask: 0x01)                         */
19937  #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos    (13UL)         /*!< CHTRC13 (Bit 13)                                      */
19938  #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk    (0x2000UL)     /*!< CHTRC13 (Bitfield-Mask: 0x01)                         */
19939  #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos    (14UL)         /*!< CHTRC14 (Bit 14)                                      */
19940  #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk    (0x4000UL)     /*!< CHTRC14 (Bitfield-Mask: 0x01)                         */
19941  #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos    (15UL)         /*!< CHTRC15 (Bit 15)                                      */
19942  #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk    (0x8000UL)     /*!< CHTRC15 (Bitfield-Mask: 0x01)                         */
19943  #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos    (16UL)         /*!< CHTRC16 (Bit 16)                                      */
19944  #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk    (0x10000UL)    /*!< CHTRC16 (Bitfield-Mask: 0x01)                         */
19945  #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos    (17UL)         /*!< CHTRC17 (Bit 17)                                      */
19946  #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk    (0x20000UL)    /*!< CHTRC17 (Bitfield-Mask: 0x01)                         */
19947  #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos    (18UL)         /*!< CHTRC18 (Bit 18)                                      */
19948  #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk    (0x40000UL)    /*!< CHTRC18 (Bitfield-Mask: 0x01)                         */
19949  #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos    (21UL)         /*!< CHTRC21 (Bit 21)                                      */
19950  #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk    (0x200000UL)   /*!< CHTRC21 (Bitfield-Mask: 0x01)                         */
19951  #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos    (22UL)         /*!< CHTRC22 (Bit 22)                                      */
19952  #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk    (0x400000UL)   /*!< CHTRC22 (Bitfield-Mask: 0x01)                         */
19953  #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos    (23UL)         /*!< CHTRC23 (Bit 23)                                      */
19954  #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk    (0x800000UL)   /*!< CHTRC23 (Bitfield-Mask: 0x01)                         */
19955  #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos    (24UL)         /*!< CHTRC24 (Bit 24)                                      */
19956  #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk    (0x1000000UL)  /*!< CHTRC24 (Bitfield-Mask: 0x01)                         */
19957  #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos    (25UL)         /*!< CHTRC25 (Bit 25)                                      */
19958  #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk    (0x2000000UL)  /*!< CHTRC25 (Bitfield-Mask: 0x01)                         */
19959  #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos    (26UL)         /*!< CHTRC26 (Bit 26)                                      */
19960  #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk    (0x4000000UL)  /*!< CHTRC26 (Bitfield-Mask: 0x01)                         */
19961  #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos    (27UL)         /*!< CHTRC27 (Bit 27)                                      */
19962  #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk    (0x8000000UL)  /*!< CHTRC27 (Bitfield-Mask: 0x01)                         */
19963  #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos    (28UL)         /*!< CHTRC28 (Bit 28)                                      */
19964  #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk    (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01)                         */
19965  #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos    (29UL)         /*!< CHTRC29 (Bit 29)                                      */
19966  #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk    (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01)                         */
19967  #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos    (30UL)         /*!< CHTRC30 (Bit 30)                                      */
19968  #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk    (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01)                         */
19969  #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos    (31UL)         /*!< CHTRC31 (Bit 31)                                      */
19970  #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk    (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01)                         */
19971 /* ======================================================  CTSUCHTRCAL  ====================================================== */
19972 /* ======================================================  CTSUCHTRC0  ======================================================= */
19973 /* ======================================================  CTSUCHTRC1  ======================================================= */
19974 /* ======================================================  CTSUCHTRCAH  ====================================================== */
19975 /* ======================================================  CTSUCHTRC2  ======================================================= */
19976 /* ======================================================  CTSUCHTRC3  ======================================================= */
19977 /* ======================================================  CTSUCHTRCB  ======================================================= */
19978  #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos    (0UL)        /*!< CHTRC32 (Bit 0)                                       */
19979  #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk    (0x1UL)      /*!< CHTRC32 (Bitfield-Mask: 0x01)                         */
19980  #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos    (1UL)        /*!< CHTRC33 (Bit 1)                                       */
19981  #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk    (0x2UL)      /*!< CHTRC33 (Bitfield-Mask: 0x01)                         */
19982  #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos    (2UL)        /*!< CHTRC34 (Bit 2)                                       */
19983  #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk    (0x4UL)      /*!< CHTRC34 (Bitfield-Mask: 0x01)                         */
19984  #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos    (3UL)        /*!< CHTRC35 (Bit 3)                                       */
19985  #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk    (0x8UL)      /*!< CHTRC35 (Bitfield-Mask: 0x01)                         */
19986 /* ======================================================  CTSUCHTRCBL  ====================================================== */
19987 /* ======================================================  CTSUCHTRC4  ======================================================= */
19988 /* ========================================================  CTSUSR  ========================================================= */
19989  #define R_CTSU2_CTSUSR_MFC_Pos            (0UL)        /*!< MFC (Bit 0)                                           */
19990  #define R_CTSU2_CTSUSR_MFC_Msk            (0x3UL)      /*!< MFC (Bitfield-Mask: 0x03)                             */
19991  #define R_CTSU2_CTSUSR_ICOMPRST_Pos       (5UL)        /*!< ICOMPRST (Bit 5)                                      */
19992  #define R_CTSU2_CTSUSR_ICOMPRST_Msk       (0x20UL)     /*!< ICOMPRST (Bitfield-Mask: 0x01)                        */
19993  #define R_CTSU2_CTSUSR_ICOMP1_Pos         (6UL)        /*!< ICOMP1 (Bit 6)                                        */
19994  #define R_CTSU2_CTSUSR_ICOMP1_Msk         (0x40UL)     /*!< ICOMP1 (Bitfield-Mask: 0x01)                          */
19995  #define R_CTSU2_CTSUSR_ICOMP0_Pos         (7UL)        /*!< ICOMP0 (Bit 7)                                        */
19996  #define R_CTSU2_CTSUSR_ICOMP0_Msk         (0x80UL)     /*!< ICOMP0 (Bitfield-Mask: 0x01)                          */
19997  #define R_CTSU2_CTSUSR_STC_Pos            (8UL)        /*!< STC (Bit 8)                                           */
19998  #define R_CTSU2_CTSUSR_STC_Msk            (0x700UL)    /*!< STC (Bitfield-Mask: 0x07)                             */
19999  #define R_CTSU2_CTSUSR_DTSR_Pos           (12UL)       /*!< DTSR (Bit 12)                                         */
20000  #define R_CTSU2_CTSUSR_DTSR_Msk           (0x1000UL)   /*!< DTSR (Bitfield-Mask: 0x01)                            */
20001  #define R_CTSU2_CTSUSR_SENSOVF_Pos        (13UL)       /*!< SENSOVF (Bit 13)                                      */
20002  #define R_CTSU2_CTSUSR_SENSOVF_Msk        (0x2000UL)   /*!< SENSOVF (Bitfield-Mask: 0x01)                         */
20003  #define R_CTSU2_CTSUSR_SUOVF_Pos          (14UL)       /*!< SUOVF (Bit 14)                                        */
20004  #define R_CTSU2_CTSUSR_SUOVF_Msk          (0x4000UL)   /*!< SUOVF (Bitfield-Mask: 0x01)                           */
20005  #define R_CTSU2_CTSUSR_PS_Pos             (15UL)       /*!< PS (Bit 15)                                           */
20006  #define R_CTSU2_CTSUSR_PS_Msk             (0x8000UL)   /*!< PS (Bitfield-Mask: 0x01)                              */
20007  #define R_CTSU2_CTSUSR_CFCRDCH_Pos        (16UL)       /*!< CFCRDCH (Bit 16)                                      */
20008  #define R_CTSU2_CTSUSR_CFCRDCH_Msk        (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f)                         */
20009 /* ========================================================  CTSUSRL  ======================================================== */
20010 /* ========================================================  CTSUSR0  ======================================================== */
20011 /* ========================================================  CTSUST  ========================================================= */
20012 /* ========================================================  CTSUSRH  ======================================================== */
20013 /* ========================================================  CTSUSR2  ======================================================== */
20014 /* ========================================================  CTSUSO  ========================================================= */
20015  #define R_CTSU2_CTSUSO_SO_Pos              (0UL)          /*!< SO (Bit 0)                                            */
20016  #define R_CTSU2_CTSUSO_SO_Msk              (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
20017  #define R_CTSU2_CTSUSO_SNUM_Pos            (10UL)         /*!< SNUM (Bit 10)                                         */
20018  #define R_CTSU2_CTSUSO_SNUM_Msk            (0x3fc00UL)    /*!< SNUM (Bitfield-Mask: 0xff)                            */
20019  #define R_CTSU2_CTSUSO_SSDIV_Pos           (20UL)         /*!< SSDIV (Bit 20)                                        */
20020  #define R_CTSU2_CTSUSO_SSDIV_Msk           (0xf00000UL)   /*!< SSDIV (Bitfield-Mask: 0x0f)                           */
20021  #define R_CTSU2_CTSUSO_SDPA_Pos            (24UL)         /*!< SDPA (Bit 24)                                         */
20022  #define R_CTSU2_CTSUSO_SDPA_Msk            (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff)                            */
20023 /* ========================================================  CTSUSO0  ======================================================== */
20024 /* ========================================================  CTSUSO1  ======================================================== */
20025 /* =======================================================  CTSUSCNT  ======================================================== */
20026  #define R_CTSU2_CTSUSCNT_SENSCNT_Pos       (0UL)          /*!< SENSCNT (Bit 0)                                       */
20027  #define R_CTSU2_CTSUSCNT_SENSCNT_Msk       (0xffffUL)     /*!< SENSCNT (Bitfield-Mask: 0xffff)                       */
20028  #define R_CTSU2_CTSUSCNT_SUCKCNT_Pos       (16UL)         /*!< SUCKCNT (Bit 16)                                      */
20029  #define R_CTSU2_CTSUSCNT_SUCKCNT_Msk       (0xffff0000UL) /*!< SUCKCNT (Bitfield-Mask: 0xffff)                       */
20030 /* ========================================================  CTSUSC  ========================================================= */
20031 /* =======================================================  CTSUCALIB  ======================================================= */
20032  #define R_CTSU2_CTSUCALIB_TSOD_Pos         (2UL)          /*!< TSOD (Bit 2)                                          */
20033  #define R_CTSU2_CTSUCALIB_TSOD_Msk         (0x4UL)        /*!< TSOD (Bitfield-Mask: 0x01)                            */
20034  #define R_CTSU2_CTSUCALIB_DRV_Pos          (3UL)          /*!< DRV (Bit 3)                                           */
20035  #define R_CTSU2_CTSUCALIB_DRV_Msk          (0x8UL)        /*!< DRV (Bitfield-Mask: 0x01)                             */
20036  #define R_CTSU2_CTSUCALIB_CLKSEL_Pos       (4UL)          /*!< CLKSEL (Bit 4)                                        */
20037  #define R_CTSU2_CTSUCALIB_CLKSEL_Msk       (0x30UL)       /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
20038  #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos      (6UL)          /*!< SUCLKEN (Bit 6)                                       */
20039  #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk      (0x40UL)       /*!< SUCLKEN (Bitfield-Mask: 0x01)                         */
20040  #define R_CTSU2_CTSUCALIB_TSOC_Pos         (7UL)          /*!< TSOC (Bit 7)                                          */
20041  #define R_CTSU2_CTSUCALIB_TSOC_Msk         (0x80UL)       /*!< TSOC (Bitfield-Mask: 0x01)                            */
20042  #define R_CTSU2_CTSUCALIB_CNTRDSEL_Pos     (8UL)          /*!< CNTRDSEL (Bit 8)                                      */
20043  #define R_CTSU2_CTSUCALIB_CNTRDSEL_Msk     (0x100UL)      /*!< CNTRDSEL (Bitfield-Mask: 0x01)                        */
20044  #define R_CTSU2_CTSUCALIB_IOC_Pos          (9UL)          /*!< IOC (Bit 9)                                           */
20045  #define R_CTSU2_CTSUCALIB_IOC_Msk          (0x200UL)      /*!< IOC (Bitfield-Mask: 0x01)                             */
20046  #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos      (10UL)         /*!< CFCRDMD (Bit 10)                                      */
20047  #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk      (0x400UL)      /*!< CFCRDMD (Bitfield-Mask: 0x01)                         */
20048  #define R_CTSU2_CTSUCALIB_DCOFF_Pos        (11UL)         /*!< DCOFF (Bit 11)                                        */
20049  #define R_CTSU2_CTSUCALIB_DCOFF_Msk        (0x800UL)      /*!< DCOFF (Bitfield-Mask: 0x01)                           */
20050  #define R_CTSU2_CTSUCALIB_IOCSEL_Pos       (12UL)         /*!< IOCSEL (Bit 12)                                       */
20051  #define R_CTSU2_CTSUCALIB_IOCSEL_Msk       (0x1000UL)     /*!< IOCSEL (Bitfield-Mask: 0x01)                          */
20052  #define R_CTSU2_CTSUCALIB_CFCSEL_Pos       (16UL)         /*!< CFCSEL (Bit 16)                                       */
20053  #define R_CTSU2_CTSUCALIB_CFCSEL_Msk       (0x3f0000UL)   /*!< CFCSEL (Bitfield-Mask: 0x3f)                          */
20054  #define R_CTSU2_CTSUCALIB_CFCMODE_Pos      (22UL)         /*!< CFCMODE (Bit 22)                                      */
20055  #define R_CTSU2_CTSUCALIB_CFCMODE_Msk      (0x400000UL)   /*!< CFCMODE (Bitfield-Mask: 0x01)                         */
20056  #define R_CTSU2_CTSUCALIB_DACMSEL_Pos      (24UL)         /*!< DACMSEL (Bit 24)                                      */
20057  #define R_CTSU2_CTSUCALIB_DACMSEL_Msk      (0x1000000UL)  /*!< DACMSEL (Bitfield-Mask: 0x01)                         */
20058  #define R_CTSU2_CTSUCALIB_DACCARRY_Pos     (25UL)         /*!< DACCARRY (Bit 25)                                     */
20059  #define R_CTSU2_CTSUCALIB_DACCARRY_Msk     (0x2000000UL)  /*!< DACCARRY (Bitfield-Mask: 0x01)                        */
20060  #define R_CTSU2_CTSUCALIB_SUMSEL_Pos       (26UL)         /*!< SUMSEL (Bit 26)                                       */
20061  #define R_CTSU2_CTSUCALIB_SUMSEL_Msk       (0x4000000UL)  /*!< SUMSEL (Bitfield-Mask: 0x01)                          */
20062  #define R_CTSU2_CTSUCALIB_SUCARRY_Pos      (27UL)         /*!< SUCARRY (Bit 27)                                      */
20063  #define R_CTSU2_CTSUCALIB_SUCARRY_Msk      (0x8000000UL)  /*!< SUCARRY (Bitfield-Mask: 0x01)                         */
20064  #define R_CTSU2_CTSUCALIB_DACCLK_Pos       (28UL)         /*!< DACCLK (Bit 28)                                       */
20065  #define R_CTSU2_CTSUCALIB_DACCLK_Msk       (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01)                          */
20066  #define R_CTSU2_CTSUCALIB_CCOCLK_Pos       (29UL)         /*!< CCOCLK (Bit 29)                                       */
20067  #define R_CTSU2_CTSUCALIB_CCOCLK_Msk       (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01)                          */
20068  #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos     (30UL)         /*!< CCOCALIB (Bit 30)                                     */
20069  #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk     (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01)                        */
20070  #define R_CTSU2_CTSUCALIB_TXREV_Pos        (31UL)         /*!< TXREV (Bit 31)                                        */
20071  #define R_CTSU2_CTSUCALIB_TXREV_Msk        (0x80000000UL) /*!< TXREV (Bitfield-Mask: 0x01)                           */
20072 /* =======================================================  CTSUDBGR0  ======================================================= */
20073 /* =======================================================  CTSUDBGR1  ======================================================= */
20074 /* ======================================================  CTSUSUCLKA  ======================================================= */
20075  #define R_CTSU2_CTSUSUCLKA_SUADJ0_Pos      (0UL)          /*!< SUADJ0 (Bit 0)                                        */
20076  #define R_CTSU2_CTSUSUCLKA_SUADJ0_Msk      (0xffUL)       /*!< SUADJ0 (Bitfield-Mask: 0xff)                          */
20077  #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Pos    (8UL)          /*!< SUMULTI0 (Bit 8)                                      */
20078  #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Msk    (0xff00UL)     /*!< SUMULTI0 (Bitfield-Mask: 0xff)                        */
20079  #define R_CTSU2_CTSUSUCLKA_SUADJ1_Pos      (16UL)         /*!< SUADJ1 (Bit 16)                                       */
20080  #define R_CTSU2_CTSUSUCLKA_SUADJ1_Msk      (0xff0000UL)   /*!< SUADJ1 (Bitfield-Mask: 0xff)                          */
20081  #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Pos    (24UL)         /*!< SUMULTI1 (Bit 24)                                     */
20082  #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Msk    (0xff000000UL) /*!< SUMULTI1 (Bitfield-Mask: 0xff)                        */
20083 /* ======================================================  CTSUSUCLK0  ======================================================= */
20084 /* ======================================================  CTSUSUCLK1  ======================================================= */
20085 /* ======================================================  CTSUSUCLKB  ======================================================= */
20086  #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos      (0UL)          /*!< SUADJ2 (Bit 0)                                        */
20087  #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk      (0xffUL)       /*!< SUADJ2 (Bitfield-Mask: 0xff)                          */
20088  #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos    (8UL)          /*!< SUMULTI2 (Bit 8)                                      */
20089  #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk    (0xff00UL)     /*!< SUMULTI2 (Bitfield-Mask: 0xff)                        */
20090  #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos      (16UL)         /*!< SUADJ3 (Bit 16)                                       */
20091  #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk      (0xff0000UL)   /*!< SUADJ3 (Bitfield-Mask: 0xff)                          */
20092  #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos    (24UL)         /*!< SUMULTI3 (Bit 24)                                     */
20093  #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk    (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff)                        */
20094 /* ======================================================  CTSUSUCLK2  ======================================================= */
20095 /* ======================================================  CTSUSUCLK3  ======================================================= */
20096 /* ======================================================  CTSUCFCCNT  ======================================================= */
20097  #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos      (0UL)          /*!< CFCCNT (Bit 0)                                        */
20098  #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk      (0xffffUL)     /*!< CFCCNT (Bitfield-Mask: 0xffff)                        */
20099 /* ======================================================  CTSUCFCCNTL  ====================================================== */
20100 /* ========================================================  CTSUOPT  ======================================================== */
20101  #define R_CTSU2_CTSUOPT_CCOCFEN_Pos        (0UL)          /*!< CCOCFEN (Bit 0)                                       */
20102  #define R_CTSU2_CTSUOPT_CCOCFEN_Msk        (0x1UL)        /*!< CCOCFEN (Bitfield-Mask: 0x01)                         */
20103  #define R_CTSU2_CTSUOPT_MCACEFN_Pos        (1UL)          /*!< MCACEFN (Bit 1)                                       */
20104  #define R_CTSU2_CTSUOPT_MCACEFN_Msk        (0x2UL)        /*!< MCACEFN (Bitfield-Mask: 0x01)                         */
20105  #define R_CTSU2_CTSUOPT_MAJIRIMD_Pos       (2UL)          /*!< MAJIRIMD (Bit 2)                                      */
20106  #define R_CTSU2_CTSUOPT_MAJIRIMD_Msk       (0x4UL)        /*!< MAJIRIMD (Bitfield-Mask: 0x01)                        */
20107  #define R_CTSU2_CTSUOPT_DTCLESS_Pos        (4UL)          /*!< DTCLESS (Bit 4)                                       */
20108  #define R_CTSU2_CTSUOPT_DTCLESS_Msk        (0x10UL)       /*!< DTCLESS (Bitfield-Mask: 0x01)                         */
20109  #define R_CTSU2_CTSUOPT_MTUCFEN_Pos        (5UL)          /*!< MTUCFEN (Bit 5)                                       */
20110  #define R_CTSU2_CTSUOPT_MTUCFEN_Msk        (0x20UL)       /*!< MTUCFEN (Bitfield-Mask: 0x01)                         */
20111  #define R_CTSU2_CTSUOPT_AJFEN_Pos          (8UL)          /*!< AJFEN (Bit 8)                                         */
20112  #define R_CTSU2_CTSUOPT_AJFEN_Msk          (0x100UL)      /*!< AJFEN (Bitfield-Mask: 0x01)                           */
20113  #define R_CTSU2_CTSUOPT_AJINTC_Pos         (9UL)          /*!< AJINTC (Bit 9)                                        */
20114  #define R_CTSU2_CTSUOPT_AJINTC_Msk         (0x200UL)      /*!< AJINTC (Bitfield-Mask: 0x01)                          */
20115  #define R_CTSU2_CTSUOPT_SCACTB_Pos         (16UL)         /*!< SCACTB (Bit 16)                                       */
20116  #define R_CTSU2_CTSUOPT_SCACTB_Msk         (0xf0000UL)    /*!< SCACTB (Bitfield-Mask: 0x0f)                          */
20117 /* =======================================================  CTSUOPTL  ======================================================== */
20118 /* ==========================================================  AC  =========================================================== */
20119 /* ==========================================================  AJ  =========================================================== */
20120 /* =======================================================  CTSUOPTH  ======================================================== */
20121 /* =========================================================  ACTB  ========================================================== */
20122 /* ======================================================  CTSUSCNTACT  ====================================================== */
20123  #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Pos    (0UL)          /*!< SCNTACCOEFF (Bit 0)                                   */
20124  #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Msk    (0xffffUL)     /*!< SCNTACCOEFF (Bitfield-Mask: 0xffff)                   */
20125  #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Pos    (16UL)         /*!< SCNTACCOUNT (Bit 16)                                  */
20126  #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Msk    (0xffff0000UL) /*!< SCNTACCOUNT (Bitfield-Mask: 0xffff)                   */
20127 /* =====================================================  CTSUSCNTACTL  ====================================================== */
20128 /* =====================================================  CTSUSCNTACTH  ====================================================== */
20129 /* =======================================================  CTSUMACT1  ======================================================= */
20130  #define R_CTSU2_CTSUMACT1_SO_Pos               (0UL)          /*!< SO (Bit 0)                                            */
20131  #define R_CTSU2_CTSUMACT1_SO_Msk               (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
20132  #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Pos      (16UL)         /*!< OFFSETCOEFF (Bit 16)                                  */
20133  #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Msk      (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff)                   */
20134 /* ======================================================  CTSUMACT1L  ======================================================= */
20135 /* ======================================================  CTSUMACT1H  ======================================================= */
20136 /* =======================================================  CTSUMACT2  ======================================================= */
20137  #define R_CTSU2_CTSUMACT2_SO_Pos               (0UL)          /*!< SO (Bit 0)                                            */
20138  #define R_CTSU2_CTSUMACT2_SO_Msk               (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
20139  #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Pos      (16UL)         /*!< OFFSETCOEFF (Bit 16)                                  */
20140  #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Msk      (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff)                   */
20141 /* ======================================================  CTSUMACT2L  ======================================================= */
20142 /* ======================================================  CTSUMACT2H  ======================================================= */
20143 /* =======================================================  CTSUMACT3  ======================================================= */
20144  #define R_CTSU2_CTSUMACT3_SO_Pos               (0UL)          /*!< SO (Bit 0)                                            */
20145  #define R_CTSU2_CTSUMACT3_SO_Msk               (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
20146  #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Pos      (16UL)         /*!< OFFSETCOEFF (Bit 16)                                  */
20147  #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Msk      (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff)                   */
20148 /* ======================================================  CTSUMACT3L  ======================================================= */
20149 /* ======================================================  CTSUMACT3H  ======================================================= */
20150 /* =======================================================  CTSUAJCR  ======================================================== */
20151  #define R_CTSU2_CTSUAJCR_TLOT_Pos              (0UL)          /*!< TLOT (Bit 0)                                          */
20152  #define R_CTSU2_CTSUAJCR_TLOT_Msk              (0xffUL)       /*!< TLOT (Bitfield-Mask: 0xff)                            */
20153  #define R_CTSU2_CTSUAJCR_THOT_Pos              (8UL)          /*!< THOT (Bit 8)                                          */
20154  #define R_CTSU2_CTSUAJCR_THOT_Msk              (0xff00UL)     /*!< THOT (Bitfield-Mask: 0xff)                            */
20155  #define R_CTSU2_CTSUAJCR_BLINI_Pos             (16UL)         /*!< BLINI (Bit 16)                                        */
20156  #define R_CTSU2_CTSUAJCR_BLINI_Msk             (0x10000UL)    /*!< BLINI (Bitfield-Mask: 0x01)                           */
20157  #define R_CTSU2_CTSUAJCR_JC_Pos                (20UL)         /*!< JC (Bit 20)                                           */
20158  #define R_CTSU2_CTSUAJCR_JC_Msk                (0x300000UL)   /*!< JC (Bitfield-Mask: 0x03)                              */
20159  #define R_CTSU2_CTSUAJCR_AJMMAT_Pos            (24UL)         /*!< AJMMAT (Bit 24)                                       */
20160  #define R_CTSU2_CTSUAJCR_AJMMAT_Msk            (0xf000000UL)  /*!< AJMMAT (Bitfield-Mask: 0x0f)                          */
20161  #define R_CTSU2_CTSUAJCR_AJBMAT_Pos            (28UL)         /*!< AJBMAT (Bit 28)                                       */
20162  #define R_CTSU2_CTSUAJCR_AJBMAT_Msk            (0xf0000000UL) /*!< AJBMAT (Bitfield-Mask: 0x0f)                          */
20163 /* =======================================================  CTSUAJCRL  ======================================================= */
20164 /* =========================================================  AJCR0  ========================================================= */
20165 /* =========================================================  AJCR1  ========================================================= */
20166 /* =======================================================  CTSUAJCRH  ======================================================= */
20167 /* =========================================================  AJCR2  ========================================================= */
20168 /* =========================================================  AJCR3  ========================================================= */
20169 /* =======================================================  CTSUAJTHR  ======================================================= */
20170  #define R_CTSU2_CTSUAJTHR_AJTHL_Pos        (0UL)          /*!< AJTHL (Bit 0)                                         */
20171  #define R_CTSU2_CTSUAJTHR_AJTHL_Msk        (0xffffUL)     /*!< AJTHL (Bitfield-Mask: 0xffff)                         */
20172  #define R_CTSU2_CTSUAJTHR_AJTHH_Pos        (16UL)         /*!< AJTHH (Bit 16)                                        */
20173  #define R_CTSU2_CTSUAJTHR_AJTHH_Msk        (0xffff0000UL) /*!< AJTHH (Bitfield-Mask: 0xffff)                         */
20174 /* ======================================================  CTSUAJTHRL  ======================================================= */
20175 /* ======================================================  CTSUAJTHRH  ======================================================= */
20176 /* ======================================================  CTSUAJMMAR  ======================================================= */
20177  #define R_CTSU2_CTSUAJMMAR_AJMMATI_Pos     (0UL)          /*!< AJMMATI (Bit 0)                                       */
20178  #define R_CTSU2_CTSUAJMMAR_AJMMATI_Msk     (0xfUL)        /*!< AJMMATI (Bitfield-Mask: 0x0f)                         */
20179  #define R_CTSU2_CTSUAJMMAR_AJMMR_Pos       (5UL)          /*!< AJMMR (Bit 5)                                         */
20180  #define R_CTSU2_CTSUAJMMAR_AJMMR_Msk       (0xffffffe0UL) /*!< AJMMR (Bitfield-Mask: 0x7ffffff)                      */
20181 /* ======================================================  CTSUAJMMARL  ====================================================== */
20182 /* ======================================================  CTSUAJMMARH  ====================================================== */
20183 /* ======================================================  CTSUAJBLACT  ====================================================== */
20184  #define R_CTSU2_CTSUAJBLACT_AJBLACT_Pos    (0UL)          /*!< AJBLACT (Bit 0)                                       */
20185  #define R_CTSU2_CTSUAJBLACT_AJBLACT_Msk    (0xffffffffUL) /*!< AJBLACT (Bitfield-Mask: 0xffffffff)                   */
20186 /* =====================================================  CTSUAJBLACTL  ====================================================== */
20187 /* =====================================================  CTSUAJBLACTH  ====================================================== */
20188 /* ======================================================  CTSUAJBLAR  ======================================================= */
20189  #define R_CTSU2_CTSUAJBLAR_AJBLAC_Pos      (0UL)          /*!< AJBLAC (Bit 0)                                        */
20190  #define R_CTSU2_CTSUAJBLAR_AJBLAC_Msk      (0xffffUL)     /*!< AJBLAC (Bitfield-Mask: 0xffff)                        */
20191  #define R_CTSU2_CTSUAJBLAR_AJBLAR_Pos      (16UL)         /*!< AJBLAR (Bit 16)                                       */
20192  #define R_CTSU2_CTSUAJBLAR_AJBLAR_Msk      (0xffff0000UL) /*!< AJBLAR (Bitfield-Mask: 0xffff)                        */
20193 /* ======================================================  CTSUAJBLARL  ====================================================== */
20194 /* ======================================================  CTSUAJBLARH  ====================================================== */
20195 /* =======================================================  CTSUAJRR  ======================================================== */
20196  #define R_CTSU2_CTSUAJRR_TJR0_Pos          (0UL)          /*!< TJR0 (Bit 0)                                          */
20197  #define R_CTSU2_CTSUAJRR_TJR0_Msk          (0x1UL)        /*!< TJR0 (Bitfield-Mask: 0x01)                            */
20198  #define R_CTSU2_CTSUAJRR_TJR1_Pos          (1UL)          /*!< TJR1 (Bit 1)                                          */
20199  #define R_CTSU2_CTSUAJRR_TJR1_Msk          (0x2UL)        /*!< TJR1 (Bitfield-Mask: 0x01)                            */
20200  #define R_CTSU2_CTSUAJRR_TJR2_Pos          (2UL)          /*!< TJR2 (Bit 2)                                          */
20201  #define R_CTSU2_CTSUAJRR_TJR2_Msk          (0x4UL)        /*!< TJR2 (Bitfield-Mask: 0x01)                            */
20202  #define R_CTSU2_CTSUAJRR_TJR3_Pos          (3UL)          /*!< TJR3 (Bit 3)                                          */
20203  #define R_CTSU2_CTSUAJRR_TJR3_Msk          (0x8UL)        /*!< TJR3 (Bitfield-Mask: 0x01)                            */
20204  #define R_CTSU2_CTSUAJRR_FJR_Pos           (4UL)          /*!< FJR (Bit 4)                                           */
20205  #define R_CTSU2_CTSUAJRR_FJR_Msk           (0x10UL)       /*!< FJR (Bitfield-Mask: 0x01)                             */
20206  #define R_CTSU2_CTSUAJRR_SJCCR_Pos         (8UL)          /*!< SJCCR (Bit 8)                                         */
20207  #define R_CTSU2_CTSUAJRR_SJCCR_Msk         (0xff00UL)     /*!< SJCCR (Bitfield-Mask: 0xff)                           */
20208 /* =======================================================  CTSUAJRRL  ======================================================= */
20209 /* =======================================================  CTSUAJRR0  ======================================================= */
20210 /* =======================================================  CTSUAJRR1  ======================================================= */
20211 
20212 /* =========================================================================================================================== */
20213 /* ================                                           R_DAC                                           ================ */
20214 /* =========================================================================================================================== */
20215 
20216 /* =========================================================  DACR  ========================================================== */
20217  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
20218  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
20219  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
20220  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
20221 /* =========================================================  DADR  ========================================================== */
20222  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
20223  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
20224 /* =========================================================  DADPR  ========================================================= */
20225  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
20226  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
20227 /* ========================================================  DAADSCR  ======================================================== */
20228  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
20229  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
20230 /* =======================================================  DAVREFCR  ======================================================== */
20231  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
20232  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
20233 /* =========================================================  DAPC  ========================================================== */
20234  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
20235  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
20236 /* ========================================================  DAAMPCR  ======================================================== */
20237  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
20238  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
20239 /* ========================================================  DAASWCR  ======================================================== */
20240  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
20241  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
20242  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
20243  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
20244 /* ========================================================  DAADUSR  ======================================================== */
20245  #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
20246  #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
20247  #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
20248  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
20249 
20250 /* =========================================================================================================================== */
20251 /* ================                                          R_DEBUG                                          ================ */
20252 /* =========================================================================================================================== */
20253 
20254 /* ========================================================  DBGSTR  ========================================================= */
20255  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
20256  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
20257  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
20258  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
20259 /* =======================================================  DBGSTOPCR  ======================================================= */
20260  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
20261  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
20262  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
20263  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
20264  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
20265  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
20266  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
20267  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
20268  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
20269  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
20270  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
20271  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
20272  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
20273  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
20274  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
20275  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
20276 /* =======================================================  FSBLSTAT  ======================================================== */
20277  #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
20278  #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
20279  #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
20280  #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
20281  #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
20282  #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
20283 
20284 /* =========================================================================================================================== */
20285 /* ================                                           R_DMA                                           ================ */
20286 /* =========================================================================================================================== */
20287 
20288 /* =========================================================  DMAST  ========================================================= */
20289  #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
20290  #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
20291 /* =========================================================  DMCTL  ========================================================= */
20292  #define R_DMA_DMCTL_PR_Pos           (0UL)       /*!< PR (Bit 0)                                            */
20293  #define R_DMA_DMCTL_PR_Msk           (0x1UL)     /*!< PR (Bitfield-Mask: 0x01)                              */
20294  #define R_DMA_DMCTL_ERCH_Pos         (4UL)       /*!< ERCH (Bit 4)                                          */
20295  #define R_DMA_DMCTL_ERCH_Msk         (0x10UL)    /*!< ERCH (Bitfield-Mask: 0x01)                            */
20296 /* ========================================================  DMECHR  ========================================================= */
20297  #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
20298  #define R_DMA_DMECHR_DMECH_Msk       (0xfUL)     /*!< DMECH (Bitfield-Mask: 0x0f)                           */
20299  #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
20300  #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
20301  #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
20302  #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
20303 /* =========================================================  DELSR  ========================================================= */
20304  #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
20305  #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
20306  #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
20307  #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
20308 
20309 /* =========================================================================================================================== */
20310 /* ================                                          R_DMAC0                                          ================ */
20311 /* =========================================================================================================================== */
20312 
20313 /* =========================================================  DMSAR  ========================================================= */
20314  #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
20315  #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
20316 /* =========================================================  DMDAR  ========================================================= */
20317  #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
20318  #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
20319 /* =========================================================  DMCRA  ========================================================= */
20320  #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
20321  #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
20322  #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
20323  #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
20324 /* =========================================================  DMCRB  ========================================================= */
20325  #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
20326  #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
20327  #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
20328  #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
20329 /* =========================================================  DMTMD  ========================================================= */
20330  #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
20331  #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
20332  #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
20333  #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
20334  #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
20335  #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
20336  #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
20337  #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
20338  #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
20339  #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
20340 /* =========================================================  DMINT  ========================================================= */
20341  #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
20342  #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
20343  #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
20344  #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
20345  #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
20346  #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
20347  #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
20348  #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
20349  #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
20350  #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
20351 /* =========================================================  DMAMD  ========================================================= */
20352  #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
20353  #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
20354  #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
20355  #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
20356  #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
20357  #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
20358  #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
20359  #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
20360  #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
20361  #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
20362  #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
20363  #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
20364 /* =========================================================  DMOFR  ========================================================= */
20365  #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
20366  #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
20367 /* =========================================================  DMCNT  ========================================================= */
20368  #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
20369  #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
20370 /* =========================================================  DMREQ  ========================================================= */
20371  #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
20372  #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
20373  #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
20374  #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
20375 /* =========================================================  DMSTS  ========================================================= */
20376  #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
20377  #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
20378  #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
20379  #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
20380  #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
20381  #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
20382 /* =========================================================  DMSRR  ========================================================= */
20383 /* =========================================================  DMDRR  ========================================================= */
20384 /* =========================================================  DMSBS  ========================================================= */
20385  #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
20386  #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
20387  #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
20388  #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
20389 /* =========================================================  DMDBS  ========================================================= */
20390  #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
20391  #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
20392  #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
20393  #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
20394 /* =========================================================  DMBWR  ========================================================= */
20395  #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
20396  #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
20397 
20398 /* =========================================================================================================================== */
20399 /* ================                                           R_DTC                                           ================ */
20400 /* =========================================================================================================================== */
20401 
20402 /* =========================================================  DTCCR  ========================================================= */
20403  #define R_DTC_DTCCR_RRS_Pos            (4UL)          /*!< RRS (Bit 4)                                           */
20404  #define R_DTC_DTCCR_RRS_Msk            (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
20405 /* ========================================================  DTCVBR  ========================================================= */
20406  #define R_DTC_DTCVBR_DTCVBR_Pos        (0UL)          /*!< DTCVBR (Bit 0)                                        */
20407  #define R_DTC_DTCVBR_DTCVBR_Msk        (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
20408 /* =======================================================  DTCADMOD  ======================================================== */
20409  #define R_DTC_DTCADMOD_SHORT_Pos       (0UL)          /*!< SHORT (Bit 0)                                         */
20410  #define R_DTC_DTCADMOD_SHORT_Msk       (0x1UL)        /*!< SHORT (Bitfield-Mask: 0x01)                           */
20411 /* =========================================================  DTCST  ========================================================= */
20412  #define R_DTC_DTCST_DTCST_Pos          (0UL)          /*!< DTCST (Bit 0)                                         */
20413  #define R_DTC_DTCST_DTCST_Msk          (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
20414 /* ========================================================  DTCSTS  ========================================================= */
20415  #define R_DTC_DTCSTS_VECN_Pos          (0UL)          /*!< VECN (Bit 0)                                          */
20416  #define R_DTC_DTCSTS_VECN_Msk          (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
20417  #define R_DTC_DTCSTS_ACT_Pos           (15UL)         /*!< ACT (Bit 15)                                          */
20418  #define R_DTC_DTCSTS_ACT_Msk           (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
20419 /* =======================================================  DTCCR_SEC  ======================================================= */
20420  #define R_DTC_DTCCR_SEC_RRS_Pos        (4UL)          /*!< RRS (Bit 4)                                           */
20421  #define R_DTC_DTCCR_SEC_RRS_Msk        (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
20422 /* ======================================================  DTCVBR_SEC  ======================================================= */
20423  #define R_DTC_DTCVBR_SEC_DTCVBR_Pos    (0UL)          /*!< DTCVBR (Bit 0)                                        */
20424  #define R_DTC_DTCVBR_SEC_DTCVBR_Msk    (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
20425 /* ========================================================  DTCDISP  ======================================================== */
20426  #define R_DTC_DTCDISP_DTCDISP_Pos      (0UL)          /*!< DTCDISP (Bit 0)                                       */
20427  #define R_DTC_DTCDISP_DTCDISP_Msk      (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff)                   */
20428 /* =========================================================  DTEVR  ========================================================= */
20429  #define R_DTC_DTEVR_DTEV_Pos           (0UL)          /*!< DTEV (Bit 0)                                          */
20430  #define R_DTC_DTEVR_DTEV_Msk           (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
20431  #define R_DTC_DTEVR_DTEVSAM_Pos        (8UL)          /*!< DTEVSAM (Bit 8)                                       */
20432  #define R_DTC_DTEVR_DTEVSAM_Msk        (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
20433  #define R_DTC_DTEVR_DTESTA_Pos         (16UL)         /*!< DTESTA (Bit 16)                                       */
20434  #define R_DTC_DTEVR_DTESTA_Msk         (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
20435 /* ========================================================  DTCIBR  ========================================================= */
20436  #define R_DTC_DTCIBR_DTCIBR_Pos        (10UL)         /*!< DTCIBR (Bit 10)                                       */
20437  #define R_DTC_DTCIBR_DTCIBR_Msk        (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff)                      */
20438 /* =========================================================  DTCOR  ========================================================= */
20439  #define R_DTC_DTCOR_SQTFRL_Pos         (0UL)          /*!< SQTFRL (Bit 0)                                        */
20440  #define R_DTC_DTCOR_SQTFRL_Msk         (0x1UL)        /*!< SQTFRL (Bitfield-Mask: 0x01)                          */
20441 /* ========================================================  DTCSQE  ========================================================= */
20442  #define R_DTC_DTCSQE_VECN_Pos          (0UL)          /*!< VECN (Bit 0)                                          */
20443  #define R_DTC_DTCSQE_VECN_Msk          (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
20444  #define R_DTC_DTCSQE_ESPSEL_Pos        (15UL)         /*!< ESPSEL (Bit 15)                                       */
20445  #define R_DTC_DTCSQE_ESPSEL_Msk        (0x8000UL)     /*!< ESPSEL (Bitfield-Mask: 0x01)                          */
20446 
20447 /* =========================================================================================================================== */
20448 /* ================                                           R_ELC                                           ================ */
20449 /* =========================================================================================================================== */
20450 
20451 /* =========================================================  ELCR  ========================================================== */
20452  #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
20453  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
20454 /* ========================================================  ELCSARA  ======================================================== */
20455  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
20456  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
20457  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
20458  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
20459  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
20460  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
20461 /* ========================================================  ELCSARB  ======================================================== */
20462  #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
20463  #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
20464  #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
20465  #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
20466  #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
20467  #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
20468  #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
20469  #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
20470  #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
20471  #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
20472  #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
20473  #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
20474  #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
20475  #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
20476  #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
20477  #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
20478  #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
20479  #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
20480  #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
20481  #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
20482  #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
20483  #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
20484  #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
20485  #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
20486  #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
20487  #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
20488  #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
20489  #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
20490  #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
20491  #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
20492  #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
20493  #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
20494 /* ========================================================  ELCSARC  ======================================================== */
20495  #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
20496  #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
20497  #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
20498  #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
20499  #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
20500  #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
20501 
20502 /* =========================================================================================================================== */
20503 /* ================                                       R_FACI_HP_CMD                                       ================ */
20504 /* =========================================================================================================================== */
20505 
20506 /* ======================================================  FACI_CMD16  ======================================================= */
20507 /* =======================================================  FACI_CMD8  ======================================================= */
20508 
20509 /* =========================================================================================================================== */
20510 /* ================                                         R_FACI_HP                                         ================ */
20511 /* =========================================================================================================================== */
20512 
20513 /* ========================================================  FASTAT  ========================================================= */
20514  #define R_FACI_HP_FASTAT_CFAE_Pos           (7UL)          /*!< CFAE (Bit 7)                                          */
20515  #define R_FACI_HP_FASTAT_CFAE_Msk           (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
20516  #define R_FACI_HP_FASTAT_CMDLK_Pos          (4UL)          /*!< CMDLK (Bit 4)                                         */
20517  #define R_FACI_HP_FASTAT_CMDLK_Msk          (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
20518  #define R_FACI_HP_FASTAT_DFAE_Pos           (3UL)          /*!< DFAE (Bit 3)                                          */
20519  #define R_FACI_HP_FASTAT_DFAE_Msk           (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
20520 /* ========================================================  FAEINT  ========================================================= */
20521  #define R_FACI_HP_FAEINT_CFAEIE_Pos         (7UL)          /*!< CFAEIE (Bit 7)                                        */
20522  #define R_FACI_HP_FAEINT_CFAEIE_Msk         (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
20523  #define R_FACI_HP_FAEINT_CMDLKIE_Pos        (4UL)          /*!< CMDLKIE (Bit 4)                                       */
20524  #define R_FACI_HP_FAEINT_CMDLKIE_Msk        (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
20525  #define R_FACI_HP_FAEINT_DFAEIE_Pos         (3UL)          /*!< DFAEIE (Bit 3)                                        */
20526  #define R_FACI_HP_FAEINT_DFAEIE_Msk         (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
20527 /* ========================================================  FRDYIE  ========================================================= */
20528  #define R_FACI_HP_FRDYIE_FRDYIE_Pos         (0UL)          /*!< FRDYIE (Bit 0)                                        */
20529  #define R_FACI_HP_FRDYIE_FRDYIE_Msk         (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
20530 /* ========================================================  FSADDR  ========================================================= */
20531  #define R_FACI_HP_FSADDR_FSA_Pos            (0UL)          /*!< FSA (Bit 0)                                           */
20532  #define R_FACI_HP_FSADDR_FSA_Msk            (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
20533 /* ========================================================  FEADDR  ========================================================= */
20534  #define R_FACI_HP_FEADDR_FEA_Pos            (0UL)          /*!< FEA (Bit 0)                                           */
20535  #define R_FACI_HP_FEADDR_FEA_Msk            (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
20536 /* ========================================================  FMEPROT  ======================================================== */
20537  #define R_FACI_HP_FMEPROT_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
20538  #define R_FACI_HP_FMEPROT_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20539  #define R_FACI_HP_FMEPROT_CEPROT_Pos        (0UL)          /*!< CEPROT (Bit 0)                                        */
20540  #define R_FACI_HP_FMEPROT_CEPROT_Msk        (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
20541 /* ========================================================  FBPROT0  ======================================================== */
20542  #define R_FACI_HP_FBPROT0_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
20543  #define R_FACI_HP_FBPROT0_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20544  #define R_FACI_HP_FBPROT0_BPCN0_Pos         (0UL)          /*!< BPCN0 (Bit 0)                                         */
20545  #define R_FACI_HP_FBPROT0_BPCN0_Msk         (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
20546 /* ========================================================  FBPROT1  ======================================================== */
20547  #define R_FACI_HP_FBPROT1_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
20548  #define R_FACI_HP_FBPROT1_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20549  #define R_FACI_HP_FBPROT1_BPCN1_Pos         (0UL)          /*!< BPCN1 (Bit 0)                                         */
20550  #define R_FACI_HP_FBPROT1_BPCN1_Msk         (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
20551 /* ========================================================  FSTATR  ========================================================= */
20552  #define R_FACI_HP_FSTATR_ILGCOMERR_Pos      (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
20553  #define R_FACI_HP_FSTATR_ILGCOMERR_Msk      (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
20554  #define R_FACI_HP_FSTATR_FESETERR_Pos       (22UL)         /*!< FESETERR (Bit 22)                                     */
20555  #define R_FACI_HP_FSTATR_FESETERR_Msk       (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
20556  #define R_FACI_HP_FSTATR_SECERR_Pos         (21UL)         /*!< SECERR (Bit 21)                                       */
20557  #define R_FACI_HP_FSTATR_SECERR_Msk         (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
20558  #define R_FACI_HP_FSTATR_OTERR_Pos          (20UL)         /*!< OTERR (Bit 20)                                        */
20559  #define R_FACI_HP_FSTATR_OTERR_Msk          (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
20560  #define R_FACI_HP_FSTATR_FRDY_Pos           (15UL)         /*!< FRDY (Bit 15)                                         */
20561  #define R_FACI_HP_FSTATR_FRDY_Msk           (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
20562  #define R_FACI_HP_FSTATR_ILGLERR_Pos        (14UL)         /*!< ILGLERR (Bit 14)                                      */
20563  #define R_FACI_HP_FSTATR_ILGLERR_Msk        (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
20564  #define R_FACI_HP_FSTATR_ERSERR_Pos         (13UL)         /*!< ERSERR (Bit 13)                                       */
20565  #define R_FACI_HP_FSTATR_ERSERR_Msk         (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
20566  #define R_FACI_HP_FSTATR_PRGERR_Pos         (12UL)         /*!< PRGERR (Bit 12)                                       */
20567  #define R_FACI_HP_FSTATR_PRGERR_Msk         (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
20568  #define R_FACI_HP_FSTATR_SUSRDY_Pos         (11UL)         /*!< SUSRDY (Bit 11)                                       */
20569  #define R_FACI_HP_FSTATR_SUSRDY_Msk         (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
20570  #define R_FACI_HP_FSTATR_DBFULL_Pos         (10UL)         /*!< DBFULL (Bit 10)                                       */
20571  #define R_FACI_HP_FSTATR_DBFULL_Msk         (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
20572  #define R_FACI_HP_FSTATR_ERSSPD_Pos         (9UL)          /*!< ERSSPD (Bit 9)                                        */
20573  #define R_FACI_HP_FSTATR_ERSSPD_Msk         (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
20574  #define R_FACI_HP_FSTATR_PRGSPD_Pos         (8UL)          /*!< PRGSPD (Bit 8)                                        */
20575  #define R_FACI_HP_FSTATR_PRGSPD_Msk         (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
20576  #define R_FACI_HP_FSTATR_FLWEERR_Pos        (6UL)          /*!< FLWEERR (Bit 6)                                       */
20577  #define R_FACI_HP_FSTATR_FLWEERR_Msk        (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
20578 /* ========================================================  FENTRYR  ======================================================== */
20579  #define R_FACI_HP_FENTRYR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
20580  #define R_FACI_HP_FENTRYR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20581  #define R_FACI_HP_FENTRYR_FENTRYD_Pos       (7UL)          /*!< FENTRYD (Bit 7)                                       */
20582  #define R_FACI_HP_FENTRYR_FENTRYD_Msk       (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
20583  #define R_FACI_HP_FENTRYR_FENTRYC_Pos       (0UL)          /*!< FENTRYC (Bit 0)                                       */
20584  #define R_FACI_HP_FENTRYR_FENTRYC_Msk       (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
20585 /* =======================================================  FSUINITR  ======================================================== */
20586  #define R_FACI_HP_FSUINITR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
20587  #define R_FACI_HP_FSUINITR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20588  #define R_FACI_HP_FSUINITR_SUINIT_Pos       (0UL)          /*!< SUINIT (Bit 0)                                        */
20589  #define R_FACI_HP_FSUINITR_SUINIT_Msk       (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
20590 /* =========================================================  FCMDR  ========================================================= */
20591  #define R_FACI_HP_FCMDR_CMDR_Pos            (8UL)          /*!< CMDR (Bit 8)                                          */
20592  #define R_FACI_HP_FCMDR_CMDR_Msk            (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
20593  #define R_FACI_HP_FCMDR_PCMDR_Pos           (0UL)          /*!< PCMDR (Bit 0)                                         */
20594  #define R_FACI_HP_FCMDR_PCMDR_Msk           (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
20595 /* ========================================================  FBCCNT  ========================================================= */
20596  #define R_FACI_HP_FBCCNT_BCDIR_Pos          (0UL)          /*!< BCDIR (Bit 0)                                         */
20597  #define R_FACI_HP_FBCCNT_BCDIR_Msk          (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
20598 /* ========================================================  FBCSTAT  ======================================================== */
20599  #define R_FACI_HP_FBCSTAT_BCST_Pos          (0UL)          /*!< BCST (Bit 0)                                          */
20600  #define R_FACI_HP_FBCSTAT_BCST_Msk          (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
20601 /* ========================================================  FPSADDR  ======================================================== */
20602  #define R_FACI_HP_FPSADDR_PSADR_Pos         (0UL)          /*!< PSADR (Bit 0)                                         */
20603  #define R_FACI_HP_FPSADDR_PSADR_Msk         (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
20604 /* ========================================================  FBCADDR  ======================================================== */
20605  #define R_FACI_HP_FBCADDR_BCADR_Pos         (0UL)          /*!< BCADR (Bit 0)                                         */
20606  #define R_FACI_HP_FBCADDR_BCADR_Msk         (0xffffffUL)   /*!< BCADR (Bitfield-Mask: 0xffffff)                       */
20607 /* ========================================================  FAWMON  ========================================================= */
20608  #define R_FACI_HP_FAWMON_BTFLG_Pos          (31UL)         /*!< BTFLG (Bit 31)                                        */
20609  #define R_FACI_HP_FAWMON_BTFLG_Msk          (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
20610  #define R_FACI_HP_FAWMON_FAWE_Pos           (16UL)         /*!< FAWE (Bit 16)                                         */
20611  #define R_FACI_HP_FAWMON_FAWE_Msk           (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
20612  #define R_FACI_HP_FAWMON_FSPR_Pos           (15UL)         /*!< FSPR (Bit 15)                                         */
20613  #define R_FACI_HP_FAWMON_FSPR_Msk           (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
20614  #define R_FACI_HP_FAWMON_FAWS_Pos           (0UL)          /*!< FAWS (Bit 0)                                          */
20615  #define R_FACI_HP_FAWMON_FAWS_Msk           (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
20616 /* =========================================================  FCPSR  ========================================================= */
20617  #define R_FACI_HP_FCPSR_ESUSPMD_Pos         (0UL)          /*!< ESUSPMD (Bit 0)                                       */
20618  #define R_FACI_HP_FCPSR_ESUSPMD_Msk         (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
20619 /* ========================================================  FPCKAR  ========================================================= */
20620  #define R_FACI_HP_FPCKAR_KEY_Pos            (8UL)          /*!< KEY (Bit 8)                                           */
20621  #define R_FACI_HP_FPCKAR_KEY_Msk            (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20622  #define R_FACI_HP_FPCKAR_PCKA_Pos           (0UL)          /*!< PCKA (Bit 0)                                          */
20623  #define R_FACI_HP_FPCKAR_PCKA_Msk           (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
20624 /* ========================================================  FSUACR  ========================================================= */
20625  #define R_FACI_HP_FSUACR_KEY_Pos            (8UL)          /*!< KEY (Bit 8)                                           */
20626  #define R_FACI_HP_FSUACR_KEY_Msk            (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20627  #define R_FACI_HP_FSUACR_SAS_Pos            (0UL)          /*!< SAS (Bit 0)                                           */
20628  #define R_FACI_HP_FSUACR_SAS_Msk            (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
20629 /* =======================================================  FCNTSELR  ======================================================== */
20630  #define R_FACI_HP_FCNTSELR_CNTSEL_Pos       (0UL)          /*!< CNTSEL (Bit 0)                                        */
20631  #define R_FACI_HP_FCNTSELR_CNTSEL_Msk       (0x7UL)        /*!< CNTSEL (Bitfield-Mask: 0x07)                          */
20632 /* ======================================================  FCNTDATAR0  ======================================================= */
20633  #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos    (0UL)          /*!< CNTRDAT (Bit 0)                                       */
20634  #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk    (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff)                   */
20635 /* ======================================================  FCNTDATAR1  ======================================================= */
20636  #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos    (0UL)          /*!< CNTRDAT (Bit 0)                                       */
20637  #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk    (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff)                   */
20638 
20639 /* =========================================================================================================================== */
20640 /* ================                                         R_FACI_LP                                         ================ */
20641 /* =========================================================================================================================== */
20642 
20643 /* ========================================================  DFLCTL  ========================================================= */
20644 /* =========================================================  FPMCR  ========================================================= */
20645  #define R_FACI_LP_FPMCR_FMS2_Pos           (7UL)      /*!< FMS2 (Bit 7)                                          */
20646  #define R_FACI_LP_FPMCR_FMS2_Msk           (0x80UL)   /*!< FMS2 (Bitfield-Mask: 0x01)                            */
20647  #define R_FACI_LP_FPMCR_VLPE_Pos           (6UL)      /*!< VLPE (Bit 6)                                          */
20648  #define R_FACI_LP_FPMCR_VLPE_Msk           (0x40UL)   /*!< VLPE (Bitfield-Mask: 0x01)                            */
20649  #define R_FACI_LP_FPMCR_FMS1_Pos           (4UL)      /*!< FMS1 (Bit 4)                                          */
20650  #define R_FACI_LP_FPMCR_FMS1_Msk           (0x10UL)   /*!< FMS1 (Bitfield-Mask: 0x01)                            */
20651  #define R_FACI_LP_FPMCR_RPDIS_Pos          (3UL)      /*!< RPDIS (Bit 3)                                         */
20652  #define R_FACI_LP_FPMCR_RPDIS_Msk          (0x8UL)    /*!< RPDIS (Bitfield-Mask: 0x01)                           */
20653  #define R_FACI_LP_FPMCR_FMS0_Pos           (1UL)      /*!< FMS0 (Bit 1)                                          */
20654  #define R_FACI_LP_FPMCR_FMS0_Msk           (0x2UL)    /*!< FMS0 (Bitfield-Mask: 0x01)                            */
20655 /* =========================================================  FASR  ========================================================== */
20656  #define R_FACI_LP_FASR_EXS_Pos             (0UL)      /*!< EXS (Bit 0)                                           */
20657  #define R_FACI_LP_FASR_EXS_Msk             (0x1UL)    /*!< EXS (Bitfield-Mask: 0x01)                             */
20658 /* =========================================================  FSARL  ========================================================= */
20659  #define R_FACI_LP_FSARL_FSAR15_0_Pos       (0UL)      /*!< FSAR15_0 (Bit 0)                                      */
20660  #define R_FACI_LP_FSARL_FSAR15_0_Msk       (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff)                      */
20661 /* =========================================================  FSARH  ========================================================= */
20662  #define R_FACI_LP_FSARH_FSAR31_25_Pos      (9UL)      /*!< FSAR31_25 (Bit 9)                                     */
20663  #define R_FACI_LP_FSARH_FSAR31_25_Msk      (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f)                       */
20664  #define R_FACI_LP_FSARH_FSAR20_16_Pos      (0UL)      /*!< FSAR20_16 (Bit 0)                                     */
20665  #define R_FACI_LP_FSARH_FSAR20_16_Msk      (0x1fUL)   /*!< FSAR20_16 (Bitfield-Mask: 0x1f)                       */
20666 /* ==========================================================  FCR  ========================================================== */
20667  #define R_FACI_LP_FCR_OPST_Pos             (7UL)      /*!< OPST (Bit 7)                                          */
20668  #define R_FACI_LP_FCR_OPST_Msk             (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
20669  #define R_FACI_LP_FCR_STOP_Pos             (6UL)      /*!< STOP (Bit 6)                                          */
20670  #define R_FACI_LP_FCR_STOP_Msk             (0x40UL)   /*!< STOP (Bitfield-Mask: 0x01)                            */
20671  #define R_FACI_LP_FCR_DRC_Pos              (4UL)      /*!< DRC (Bit 4)                                           */
20672  #define R_FACI_LP_FCR_DRC_Msk              (0x10UL)   /*!< DRC (Bitfield-Mask: 0x01)                             */
20673  #define R_FACI_LP_FCR_CMD_Pos              (0UL)      /*!< CMD (Bit 0)                                           */
20674  #define R_FACI_LP_FCR_CMD_Msk              (0xfUL)    /*!< CMD (Bitfield-Mask: 0x0f)                             */
20675 /* =========================================================  FEARL  ========================================================= */
20676  #define R_FACI_LP_FEARL_FEAR15_0_Pos       (0UL)      /*!< FEAR15_0 (Bit 0)                                      */
20677  #define R_FACI_LP_FEARL_FEAR15_0_Msk       (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff)                      */
20678 /* =========================================================  FEARH  ========================================================= */
20679  #define R_FACI_LP_FEARH_FEAR31_25_Pos      (9UL)      /*!< FEAR31_25 (Bit 9)                                     */
20680  #define R_FACI_LP_FEARH_FEAR31_25_Msk      (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f)                       */
20681  #define R_FACI_LP_FEARH_FEAR20_16_Pos      (0UL)      /*!< FEAR20_16 (Bit 0)                                     */
20682  #define R_FACI_LP_FEARH_FEAR20_16_Msk      (0x1fUL)   /*!< FEAR20_16 (Bitfield-Mask: 0x1f)                       */
20683 /* ========================================================  FRESETR  ======================================================== */
20684  #define R_FACI_LP_FRESETR_FRESET_Pos       (0UL)      /*!< FRESET (Bit 0)                                        */
20685  #define R_FACI_LP_FRESETR_FRESET_Msk       (0x1UL)    /*!< FRESET (Bitfield-Mask: 0x01)                          */
20686 /* =======================================================  FSTATR00  ======================================================== */
20687  #define R_FACI_LP_FSTATR00_EILGLERR_Pos    (5UL)      /*!< EILGLERR (Bit 5)                                      */
20688  #define R_FACI_LP_FSTATR00_EILGLERR_Msk    (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
20689  #define R_FACI_LP_FSTATR00_ILGLERR_Pos     (4UL)      /*!< ILGLERR (Bit 4)                                       */
20690  #define R_FACI_LP_FSTATR00_ILGLERR_Msk     (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
20691  #define R_FACI_LP_FSTATR00_BCERR0_Pos      (3UL)      /*!< BCERR0 (Bit 3)                                        */
20692  #define R_FACI_LP_FSTATR00_BCERR0_Msk      (0x8UL)    /*!< BCERR0 (Bitfield-Mask: 0x01)                          */
20693  #define R_FACI_LP_FSTATR00_PRGERR01_Pos    (2UL)      /*!< PRGERR01 (Bit 2)                                      */
20694  #define R_FACI_LP_FSTATR00_PRGERR01_Msk    (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
20695  #define R_FACI_LP_FSTATR00_PRGERR0_Pos     (1UL)      /*!< PRGERR0 (Bit 1)                                       */
20696  #define R_FACI_LP_FSTATR00_PRGERR0_Msk     (0x2UL)    /*!< PRGERR0 (Bitfield-Mask: 0x01)                         */
20697  #define R_FACI_LP_FSTATR00_ERERR0_Pos      (0UL)      /*!< ERERR0 (Bit 0)                                        */
20698  #define R_FACI_LP_FSTATR00_ERERR0_Msk      (0x1UL)    /*!< ERERR0 (Bitfield-Mask: 0x01)                          */
20699 /* ========================================================  FSTATR1  ======================================================== */
20700  #define R_FACI_LP_FSTATR1_EXRDY_Pos        (7UL)      /*!< EXRDY (Bit 7)                                         */
20701  #define R_FACI_LP_FSTATR1_EXRDY_Msk        (0x80UL)   /*!< EXRDY (Bitfield-Mask: 0x01)                           */
20702  #define R_FACI_LP_FSTATR1_FRDY_Pos         (6UL)      /*!< FRDY (Bit 6)                                          */
20703  #define R_FACI_LP_FSTATR1_FRDY_Msk         (0x40UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
20704  #define R_FACI_LP_FSTATR1_DRRDY_Pos        (1UL)      /*!< DRRDY (Bit 1)                                         */
20705  #define R_FACI_LP_FSTATR1_DRRDY_Msk        (0x2UL)    /*!< DRRDY (Bitfield-Mask: 0x01)                           */
20706 /* =========================================================  FWBL0  ========================================================= */
20707  #define R_FACI_LP_FWBL0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
20708  #define R_FACI_LP_FWBL0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
20709 /* =========================================================  FWBH0  ========================================================= */
20710  #define R_FACI_LP_FWBH0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
20711  #define R_FACI_LP_FWBH0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
20712 /* =======================================================  FSTATR01  ======================================================== */
20713  #define R_FACI_LP_FSTATR01_BCERR1_Pos      (3UL)      /*!< BCERR1 (Bit 3)                                        */
20714  #define R_FACI_LP_FSTATR01_BCERR1_Msk      (0x8UL)    /*!< BCERR1 (Bitfield-Mask: 0x01)                          */
20715  #define R_FACI_LP_FSTATR01_PRGERR1_Pos     (1UL)      /*!< PRGERR1 (Bit 1)                                       */
20716  #define R_FACI_LP_FSTATR01_PRGERR1_Msk     (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
20717  #define R_FACI_LP_FSTATR01_ERERR1_Pos      (0UL)      /*!< ERERR1 (Bit 0)                                        */
20718  #define R_FACI_LP_FSTATR01_ERERR1_Msk      (0x1UL)    /*!< ERERR1 (Bitfield-Mask: 0x01)                          */
20719 /* =========================================================  FWBL1  ========================================================= */
20720  #define R_FACI_LP_FWBL1_WDATA47_32_Pos     (0UL)      /*!< WDATA47_32 (Bit 0)                                    */
20721  #define R_FACI_LP_FWBL1_WDATA47_32_Msk     (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff)                    */
20722 /* =========================================================  FWBH1  ========================================================= */
20723  #define R_FACI_LP_FWBH1_WDATA63_48_Pos     (0UL)      /*!< WDATA63_48 (Bit 0)                                    */
20724  #define R_FACI_LP_FWBH1_WDATA63_48_Msk     (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff)                    */
20725 /* =========================================================  FRBL1  ========================================================= */
20726  #define R_FACI_LP_FRBL1_RDATA47_32_Pos     (0UL)      /*!< RDATA47_32 (Bit 0)                                    */
20727  #define R_FACI_LP_FRBL1_RDATA47_32_Msk     (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff)                    */
20728 /* =========================================================  FRBH1  ========================================================= */
20729  #define R_FACI_LP_FRBH1_RDATA63_48_Pos     (0UL)      /*!< RDATA63_48 (Bit 0)                                    */
20730  #define R_FACI_LP_FRBH1_RDATA63_48_Msk     (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff)                    */
20731 /* ==========================================================  FPR  ========================================================== */
20732  #define R_FACI_LP_FPR_FPR_Pos              (0UL)      /*!< FPR (Bit 0)                                           */
20733  #define R_FACI_LP_FPR_FPR_Msk              (0xffUL)   /*!< FPR (Bitfield-Mask: 0xff)                             */
20734 /* =========================================================  FPSR  ========================================================== */
20735  #define R_FACI_LP_FPSR_PERR_Pos            (0UL)      /*!< PERR (Bit 0)                                          */
20736  #define R_FACI_LP_FPSR_PERR_Msk            (0x1UL)    /*!< PERR (Bitfield-Mask: 0x01)                            */
20737 /* =========================================================  FRBL0  ========================================================= */
20738  #define R_FACI_LP_FRBL0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
20739  #define R_FACI_LP_FRBL0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
20740 /* =========================================================  FRBH0  ========================================================= */
20741  #define R_FACI_LP_FRBH0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
20742  #define R_FACI_LP_FRBH0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
20743 /* =========================================================  FSCMR  ========================================================= */
20744  #define R_FACI_LP_FSCMR_FSPR_Pos           (14UL)     /*!< FSPR (Bit 14)                                         */
20745  #define R_FACI_LP_FSCMR_FSPR_Msk           (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01)                            */
20746  #define R_FACI_LP_FSCMR_SASMF_Pos          (8UL)      /*!< SASMF (Bit 8)                                         */
20747  #define R_FACI_LP_FSCMR_SASMF_Msk          (0x100UL)  /*!< SASMF (Bitfield-Mask: 0x01)                           */
20748 /* ========================================================  FAWSMR  ========================================================= */
20749  #define R_FACI_LP_FAWSMR_FAWS_Pos          (0UL)      /*!< FAWS (Bit 0)                                          */
20750  #define R_FACI_LP_FAWSMR_FAWS_Msk          (0xfffUL)  /*!< FAWS (Bitfield-Mask: 0xfff)                           */
20751 /* ========================================================  FAWEMR  ========================================================= */
20752  #define R_FACI_LP_FAWEMR_FAWE_Pos          (0UL)      /*!< FAWE (Bit 0)                                          */
20753  #define R_FACI_LP_FAWEMR_FAWE_Msk          (0xfffUL)  /*!< FAWE (Bitfield-Mask: 0xfff)                           */
20754 /* =========================================================  FISR  ========================================================== */
20755  #define R_FACI_LP_FISR_SAS_Pos             (6UL)      /*!< SAS (Bit 6)                                           */
20756  #define R_FACI_LP_FISR_SAS_Msk             (0xc0UL)   /*!< SAS (Bitfield-Mask: 0x03)                             */
20757  #define R_FACI_LP_FISR_PCKA_Pos            (0UL)      /*!< PCKA (Bit 0)                                          */
20758  #define R_FACI_LP_FISR_PCKA_Msk            (0x3fUL)   /*!< PCKA (Bitfield-Mask: 0x3f)                            */
20759 /* =========================================================  FEXCR  ========================================================= */
20760  #define R_FACI_LP_FEXCR_OPST_Pos           (7UL)      /*!< OPST (Bit 7)                                          */
20761  #define R_FACI_LP_FEXCR_OPST_Msk           (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
20762  #define R_FACI_LP_FEXCR_CMD_Pos            (0UL)      /*!< CMD (Bit 0)                                           */
20763  #define R_FACI_LP_FEXCR_CMD_Msk            (0x7UL)    /*!< CMD (Bitfield-Mask: 0x07)                             */
20764 /* =========================================================  FEAML  ========================================================= */
20765  #define R_FACI_LP_FEAML_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
20766  #define R_FACI_LP_FEAML_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
20767 /* =========================================================  FEAMH  ========================================================= */
20768  #define R_FACI_LP_FEAMH_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
20769  #define R_FACI_LP_FEAMH_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
20770 /* ========================================================  FSTATR2  ======================================================== */
20771  #define R_FACI_LP_FSTATR2_EILGLERR_Pos     (5UL)      /*!< EILGLERR (Bit 5)                                      */
20772  #define R_FACI_LP_FSTATR2_EILGLERR_Msk     (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
20773  #define R_FACI_LP_FSTATR2_ILGLERR_Pos      (4UL)      /*!< ILGLERR (Bit 4)                                       */
20774  #define R_FACI_LP_FSTATR2_ILGLERR_Msk      (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
20775  #define R_FACI_LP_FSTATR2_BCERR_Pos        (3UL)      /*!< BCERR (Bit 3)                                         */
20776  #define R_FACI_LP_FSTATR2_BCERR_Msk        (0x8UL)    /*!< BCERR (Bitfield-Mask: 0x01)                           */
20777  #define R_FACI_LP_FSTATR2_PRGERR01_Pos     (2UL)      /*!< PRGERR01 (Bit 2)                                      */
20778  #define R_FACI_LP_FSTATR2_PRGERR01_Msk     (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
20779  #define R_FACI_LP_FSTATR2_PRGERR1_Pos      (1UL)      /*!< PRGERR1 (Bit 1)                                       */
20780  #define R_FACI_LP_FSTATR2_PRGERR1_Msk      (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
20781  #define R_FACI_LP_FSTATR2_ERERR_Pos        (0UL)      /*!< ERERR (Bit 0)                                         */
20782  #define R_FACI_LP_FSTATR2_ERERR_Msk        (0x1UL)    /*!< ERERR (Bitfield-Mask: 0x01)                           */
20783 /* ========================================================  FCTLFR  ========================================================= */
20784  #define R_FACI_LP_FCTLFR_BANKSWP_Pos       (0UL)      /*!< BANKSWP (Bit 0)                                       */
20785  #define R_FACI_LP_FCTLFR_BANKSWP_Msk       (0x7UL)    /*!< BANKSWP (Bitfield-Mask: 0x07)                         */
20786 /* ======================================================  FENTRYR_MF4  ====================================================== */
20787 /* ========================================================  FENTRYR  ======================================================== */
20788 /* ========================================================  FLWAITR  ======================================================== */
20789 /* =======================================================  FLDWAITR  ======================================================== */
20790  #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos    (0UL)      /*!< FLDWAIT1 (Bit 0)                                      */
20791  #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk    (0x1UL)    /*!< FLDWAIT1 (Bitfield-Mask: 0x01)                        */
20792 /* =========================================================  PFBER  ========================================================= */
20793 /* ========================================================  FBKPGCR  ======================================================== */
20794  #define R_FACI_LP_FBKPGCR_BKPGEN_Pos       (0UL)      /*!< BKPGEN (Bit 0)                                        */
20795  #define R_FACI_LP_FBKPGCR_BKPGEN_Msk       (0x1UL)    /*!< BKPGEN (Bitfield-Mask: 0x01)                          */
20796  #define R_FACI_LP_FBKPGCR_FEKEY_Pos        (8UL)      /*!< FEKEY (Bit 8)                                         */
20797  #define R_FACI_LP_FBKPGCR_FEKEY_Msk        (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff)                           */
20798 /* ========================================================  FBKSWCR  ======================================================== */
20799  #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos     (0UL)      /*!< BKSWUPEN (Bit 0)                                      */
20800  #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk     (0x1UL)    /*!< BKSWUPEN (Bitfield-Mask: 0x01)                        */
20801  #define R_FACI_LP_FBKSWCR_FEKEY_Pos        (8UL)      /*!< FEKEY (Bit 8)                                         */
20802  #define R_FACI_LP_FBKSWCR_FEKEY_Msk        (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff)                           */
20803 /* ========================================================  HIOTRM  ========================================================= */
20804  #define R_FACI_LP_HIOTRM_HIOTRM_Pos        (0UL)      /*!< HIOTRM (Bit 0)                                        */
20805  #define R_FACI_LP_HIOTRM_HIOTRM_Msk        (0x3fUL)   /*!< HIOTRM (Bitfield-Mask: 0x3f)                          */
20806 /* ========================================================  FLMODE  ========================================================= */
20807  #define R_FACI_LP_FLMODE_MODE_Pos          (6UL)      /*!< MODE (Bit 6)                                          */
20808  #define R_FACI_LP_FLMODE_MODE_Msk          (0xc0UL)   /*!< MODE (Bitfield-Mask: 0x03)                            */
20809 /* ========================================================  FLMWRP  ========================================================= */
20810  #define R_FACI_LP_FLMWRP_FLMWEN_Pos        (0UL)      /*!< FLMWEN (Bit 0)                                        */
20811  #define R_FACI_LP_FLMWRP_FLMWEN_Msk        (0x1UL)    /*!< FLMWEN (Bitfield-Mask: 0x01)                          */
20812 
20813 /* =========================================================================================================================== */
20814 /* ================                                        R_CTSUTRIM                                         ================ */
20815 /* =========================================================================================================================== */
20816 
20817 /* =======================================================  CTSUTRIMA  ======================================================= */
20818  #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Pos    (24UL)         /*!< SUADJTRIM (Bit 24)                                    */
20819  #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Msk    (0xff000000UL) /*!< SUADJTRIM (Bitfield-Mask: 0xff)                       */
20820  #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Pos       (16UL)         /*!< SUADJD (Bit 16)                                       */
20821  #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Msk       (0xff0000UL)   /*!< SUADJD (Bitfield-Mask: 0xff)                          */
20822  #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Pos      (8UL)          /*!< DACTRIM (Bit 8)                                       */
20823  #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Msk      (0xff00UL)     /*!< DACTRIM (Bitfield-Mask: 0xff)                         */
20824  #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Pos        (0UL)          /*!< RTRIM (Bit 0)                                         */
20825  #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Msk        (0xffUL)       /*!< RTRIM (Bitfield-Mask: 0xff)                           */
20826 /* =======================================================  CTSUTRIMB  ======================================================= */
20827  #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Pos     (24UL)         /*!< TRESULT3 (Bit 24)                                     */
20828  #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Msk     (0xff000000UL) /*!< TRESULT3 (Bitfield-Mask: 0xff)                        */
20829  #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Pos     (16UL)         /*!< TRESULT2 (Bit 16)                                     */
20830  #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Msk     (0xff0000UL)   /*!< TRESULT2 (Bitfield-Mask: 0xff)                        */
20831  #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Pos     (8UL)          /*!< TRESULT1 (Bit 8)                                      */
20832  #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Msk     (0xff00UL)     /*!< TRESULT1 (Bitfield-Mask: 0xff)                        */
20833  #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Pos     (0UL)          /*!< TRESULT0 (Bit 0)                                      */
20834  #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Msk     (0xffUL)       /*!< TRESULT0 (Bitfield-Mask: 0xff)                        */
20835 
20836 /* =========================================================================================================================== */
20837 /* ================                                         R_FCACHE                                          ================ */
20838 /* =========================================================================================================================== */
20839 
20840 /* ========================================================  FCACHEE  ======================================================== */
20841  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)      /*!< FCACHEEN (Bit 0)                                      */
20842  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)    /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
20843 /* =======================================================  FCACHEIV  ======================================================== */
20844  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)      /*!< FCACHEIV (Bit 0)                                      */
20845  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)    /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
20846 /* =========================================================  FLWT  ========================================================== */
20847  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)      /*!< FLWT (Bit 0)                                          */
20848  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)    /*!< FLWT (Bitfield-Mask: 0x07)                            */
20849 /* =========================================================  FSAR  ========================================================== */
20850  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)      /*!< FLWTSA (Bit 0)                                        */
20851  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)    /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
20852  #define R_FCACHE_FSAR_PFBERSA_Pos         (1UL)      /*!< PFBERSA (Bit 1)                                       */
20853  #define R_FCACHE_FSAR_PFBERSA_Msk         (0x2UL)    /*!< PFBERSA (Bitfield-Mask: 0x01)                         */
20854  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)      /*!< FCKMHZSA (Bit 8)                                      */
20855  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL)  /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
20856  #define R_FCACHE_FSAR_FACICOMISA_Pos      (9UL)      /*!< FACICOMISA (Bit 9)                                    */
20857  #define R_FCACHE_FSAR_FACICOMISA_Msk      (0x200UL)  /*!< FACICOMISA (Bitfield-Mask: 0x01)                      */
20858  #define R_FCACHE_FSAR_FACICOMRSA_Pos      (10UL)     /*!< FACICOMRSA (Bit 10)                                   */
20859  #define R_FCACHE_FSAR_FACICOMRSA_Msk      (0x400UL)  /*!< FACICOMRSA (Bitfield-Mask: 0x01)                      */
20860  #define R_FCACHE_FSAR_DFLCTLSA_Pos        (15UL)     /*!< DFLCTLSA (Bit 15)                                     */
20861  #define R_FCACHE_FSAR_DFLCTLSA_Msk        (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01)                        */
20862 
20863 /* =========================================================================================================================== */
20864 /* ================                                          R_GPT0                                           ================ */
20865 /* =========================================================================================================================== */
20866 
20867 /* =========================================================  GTWP  ========================================================== */
20868  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
20869  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
20870  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
20871  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
20872  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
20873  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
20874  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
20875  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
20876  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
20877  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
20878  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
20879  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
20880 /* =========================================================  GTSTR  ========================================================= */
20881  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
20882  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
20883 /* =========================================================  GTSTP  ========================================================= */
20884  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
20885  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
20886 /* =========================================================  GTCLR  ========================================================= */
20887  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
20888  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
20889 /* =========================================================  GTSSR  ========================================================= */
20890  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
20891  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
20892  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
20893  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
20894  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
20895  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
20896  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
20897  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
20898  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
20899  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
20900  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
20901  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
20902  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
20903  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
20904  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
20905  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
20906  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
20907  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
20908  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
20909  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
20910  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
20911  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
20912  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
20913  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
20914 /* =========================================================  GTPSR  ========================================================= */
20915  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
20916  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
20917  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
20918  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
20919  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
20920  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
20921  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
20922  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
20923  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
20924  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
20925  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
20926  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
20927  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
20928  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
20929  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
20930  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
20931  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
20932  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
20933  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
20934  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
20935  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
20936  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
20937  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
20938  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
20939 /* =========================================================  GTCSR  ========================================================= */
20940  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
20941  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
20942  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
20943  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
20944  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
20945  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
20946  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
20947  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
20948  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
20949  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
20950  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
20951  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
20952  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
20953  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
20954  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
20955  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
20956  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
20957  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
20958  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
20959  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
20960  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
20961  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
20962  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
20963  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
20964  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
20965  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
20966  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
20967  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
20968 /* ========================================================  GTUPSR  ========================================================= */
20969  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
20970  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
20971  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
20972  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
20973  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
20974  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
20975  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
20976  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
20977  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
20978  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
20979  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
20980  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
20981  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
20982  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
20983  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
20984  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
20985  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
20986  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
20987  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
20988  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
20989  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
20990  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
20991  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
20992  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
20993 /* ========================================================  GTDNSR  ========================================================= */
20994  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
20995  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
20996  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
20997  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
20998  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
20999  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
21000  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
21001  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
21002  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
21003  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
21004  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
21005  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
21006  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
21007  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
21008  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
21009  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
21010  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
21011  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
21012  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
21013  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
21014  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
21015  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
21016  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
21017  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
21018 /* ========================================================  GTICASR  ======================================================== */
21019  #define R_GPT0_GTICASR_ASOC_Pos           (24UL)         /*!< ASOC (Bit 24)                                         */
21020  #define R_GPT0_GTICASR_ASOC_Msk           (0x1000000UL)  /*!< ASOC (Bitfield-Mask: 0x01)                            */
21021  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
21022  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
21023  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
21024  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
21025  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
21026  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
21027  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
21028  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
21029  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
21030  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
21031  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
21032  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
21033  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
21034  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
21035  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
21036  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
21037  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
21038  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
21039  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
21040  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
21041  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
21042  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
21043 /* ========================================================  GTICBSR  ======================================================== */
21044  #define R_GPT0_GTICBSR_BSOC_Pos           (24UL)         /*!< BSOC (Bit 24)                                         */
21045  #define R_GPT0_GTICBSR_BSOC_Msk           (0x1000000UL)  /*!< BSOC (Bitfield-Mask: 0x01)                            */
21046  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
21047  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
21048  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
21049  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
21050  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
21051  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
21052  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
21053  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
21054  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
21055  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
21056  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
21057  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
21058  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
21059  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
21060  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
21061  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
21062  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
21063  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
21064  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
21065  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
21066  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
21067  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
21068 /* =========================================================  GTCR  ========================================================== */
21069  #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
21070  #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
21071  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
21072  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
21073  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
21074  #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
21075  #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
21076  #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
21077  #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
21078  #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
21079  #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
21080  #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
21081  #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
21082  #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
21083  #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
21084  #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
21085  #define R_GPT0_GTCR_BINV_Pos              (5UL)          /*!< BINV (Bit 5)                                          */
21086  #define R_GPT0_GTCR_BINV_Msk              (0x20UL)       /*!< BINV (Bitfield-Mask: 0x01)                            */
21087  #define R_GPT0_GTCR_AINV_Pos              (4UL)          /*!< AINV (Bit 4)                                          */
21088  #define R_GPT0_GTCR_AINV_Msk              (0x10UL)       /*!< AINV (Bitfield-Mask: 0x01)                            */
21089  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
21090  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
21091 /* =======================================================  GTUDDTYC  ======================================================== */
21092  #define R_GPT0_GTUDDTYC_OABDTYT_Pos       (28UL)         /*!< OABDTYT (Bit 28)                                      */
21093  #define R_GPT0_GTUDDTYC_OABDTYT_Msk       (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01)                         */
21094  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
21095  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
21096  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
21097  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
21098  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
21099  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
21100  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
21101  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
21102  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
21103  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
21104  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
21105  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
21106  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
21107  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
21108  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
21109  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
21110 /* =========================================================  GTIOR  ========================================================= */
21111  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
21112  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
21113  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
21114  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
21115  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
21116  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
21117  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
21118  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
21119  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
21120  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
21121  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
21122  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
21123  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
21124  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
21125  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
21126  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
21127  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
21128  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
21129  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
21130  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
21131  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
21132  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
21133  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
21134  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
21135  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
21136  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
21137  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
21138  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
21139  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
21140  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
21141  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
21142  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
21143  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
21144  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
21145  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
21146  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
21147 /* ========================================================  GTINTAD  ======================================================== */
21148  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
21149  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
21150  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
21151  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
21152  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
21153  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
21154  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
21155  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
21156  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
21157  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
21158  #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
21159  #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
21160  #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
21161  #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
21162  #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
21163  #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
21164  #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
21165  #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
21166  #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
21167  #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
21168  #define R_GPT0_GTINTAD_GTINTPR_Pos        (6UL)          /*!< GTINTPR (Bit 6)                                       */
21169  #define R_GPT0_GTINTAD_GTINTPR_Msk        (0xc0UL)       /*!< GTINTPR (Bitfield-Mask: 0x03)                         */
21170  #define R_GPT0_GTINTAD_GTINT_Pos          (0UL)          /*!< GTINT (Bit 0)                                         */
21171  #define R_GPT0_GTINTAD_GTINT_Msk          (0x1UL)        /*!< GTINT (Bitfield-Mask: 0x01)                           */
21172 /* =========================================================  GTST  ========================================================== */
21173  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
21174  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
21175  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
21176  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
21177  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
21178  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
21179  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
21180  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
21181  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
21182  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
21183  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
21184  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
21185  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
21186  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
21187  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
21188  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
21189  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
21190  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
21191  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
21192  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
21193  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
21194  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
21195  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
21196  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
21197  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
21198  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
21199  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
21200  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
21201  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
21202  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
21203  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
21204  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
21205  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
21206  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
21207  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
21208  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
21209  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
21210  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
21211 /* =========================================================  GTBER  ========================================================= */
21212  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
21213  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
21214  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
21215  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
21216  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
21217  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
21218  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
21219  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
21220  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
21221  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
21222  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
21223  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
21224  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
21225  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
21226  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
21227  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
21228  #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
21229  #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
21230  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
21231  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
21232  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
21233  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
21234  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
21235  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
21236  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
21237  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
21238 /* =========================================================  GTITC  ========================================================= */
21239  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
21240  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
21241  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
21242  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
21243  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
21244  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
21245  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
21246  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
21247  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
21248  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
21249  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
21250  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
21251  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
21252  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
21253  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
21254  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
21255  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
21256  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
21257  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
21258  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
21259 /* =========================================================  GTCNT  ========================================================= */
21260  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
21261  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
21262 /* =========================================================  GTCCR  ========================================================= */
21263  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
21264  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
21265 /* =========================================================  GTPR  ========================================================== */
21266  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
21267  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
21268 /* =========================================================  GTPBR  ========================================================= */
21269  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
21270  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
21271 /* ========================================================  GTPDBR  ========================================================= */
21272  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
21273  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
21274 /* ========================================================  GTADTRA  ======================================================== */
21275  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
21276  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
21277 /* ========================================================  GTADTRB  ======================================================== */
21278  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
21279  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
21280 /* =======================================================  GTADTBRA  ======================================================== */
21281  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
21282  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
21283 /* =======================================================  GTADTBRB  ======================================================== */
21284  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
21285  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
21286 /* =======================================================  GTADTDBRA  ======================================================= */
21287  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
21288  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
21289 /* =======================================================  GTADTDBRB  ======================================================= */
21290  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
21291  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
21292 /* ========================================================  GTDTCR  ========================================================= */
21293  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
21294  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
21295  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
21296  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
21297  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
21298  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
21299  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
21300  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
21301 /* =========================================================  GTDVU  ========================================================= */
21302  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
21303  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
21304 /* =========================================================  GTDVD  ========================================================= */
21305  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
21306  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
21307 /* =========================================================  GTDBU  ========================================================= */
21308  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
21309  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
21310 /* =========================================================  GTDBD  ========================================================= */
21311  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
21312  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
21313 /* =========================================================  GTSOS  ========================================================= */
21314  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
21315  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
21316 /* ========================================================  GTSOTR  ========================================================= */
21317  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
21318  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
21319 /* ========================================================  GTADSMR  ======================================================== */
21320  #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
21321  #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
21322  #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
21323  #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
21324  #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
21325  #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
21326  #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
21327  #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
21328 /* ========================================================  GTEITC  ========================================================= */
21329  #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
21330  #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
21331  #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
21332  #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
21333  #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
21334  #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
21335  #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
21336  #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
21337  #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
21338  #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
21339  #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
21340  #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
21341  #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
21342  #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
21343 /* =======================================================  GTEITLI1  ======================================================== */
21344  #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
21345  #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
21346  #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
21347  #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
21348  #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
21349  #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
21350  #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
21351  #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
21352  #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
21353  #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
21354  #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
21355  #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
21356  #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
21357  #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
21358  #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
21359  #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
21360 /* =======================================================  GTEITLI2  ======================================================== */
21361  #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
21362  #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
21363  #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
21364  #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
21365 /* ========================================================  GTEITLB  ======================================================== */
21366  #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
21367  #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
21368  #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
21369  #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
21370  #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
21371  #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
21372  #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
21373  #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
21374  #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
21375  #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
21376  #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
21377  #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
21378  #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
21379  #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
21380 /* ========================================================  GTICLF  ========================================================= */
21381  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
21382  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
21383  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
21384  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
21385  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
21386  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
21387  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
21388  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
21389 /* =========================================================  GTPC  ========================================================== */
21390  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
21391  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
21392  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
21393  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
21394  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
21395  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
21396 /* =======================================================  GTADCMSC  ======================================================== */
21397  #define R_GPT0_GTADCMSC_ADCMSCNT_Pos      (12UL)         /*!< ADCMSCNT (Bit 12)                                     */
21398  #define R_GPT0_GTADCMSC_ADCMSCNT_Msk      (0xf000UL)     /*!< ADCMSCNT (Bitfield-Mask: 0x0f)                        */
21399  #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos    (8UL)          /*!< ADCMSCNTIV (Bit 8)                                    */
21400  #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk    (0xf00UL)      /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f)                      */
21401  #define R_GPT0_GTADCMSC_ADCMST_Pos        (4UL)          /*!< ADCMST (Bit 4)                                        */
21402  #define R_GPT0_GTADCMSC_ADCMST_Msk        (0xf0UL)       /*!< ADCMST (Bitfield-Mask: 0x0f)                          */
21403  #define R_GPT0_GTADCMSC_ADCMSC_Pos        (0UL)          /*!< ADCMSC (Bit 0)                                        */
21404  #define R_GPT0_GTADCMSC_ADCMSC_Msk        (0x3UL)        /*!< ADCMSC (Bitfield-Mask: 0x03)                          */
21405 /* =======================================================  GTADCMSS  ======================================================== */
21406  #define R_GPT0_GTADCMSS_ADCMSAL_Pos       (0UL)          /*!< ADCMSAL (Bit 0)                                       */
21407  #define R_GPT0_GTADCMSS_ADCMSAL_Msk       (0x7UL)        /*!< ADCMSAL (Bitfield-Mask: 0x07)                         */
21408  #define R_GPT0_GTADCMSS_ADCMSBL_Pos       (4UL)          /*!< ADCMSBL (Bit 4)                                       */
21409  #define R_GPT0_GTADCMSS_ADCMSBL_Msk       (0x70UL)       /*!< ADCMSBL (Bitfield-Mask: 0x07)                         */
21410  #define R_GPT0_GTADCMSS_ADCMBSA_Pos       (16UL)         /*!< ADCMBSA (Bit 16)                                      */
21411  #define R_GPT0_GTADCMSS_ADCMBSA_Msk       (0x70000UL)    /*!< ADCMBSA (Bitfield-Mask: 0x07)                         */
21412  #define R_GPT0_GTADCMSS_ADCMBSB_Pos       (20UL)         /*!< ADCMBSB (Bit 20)                                      */
21413  #define R_GPT0_GTADCMSS_ADCMBSB_Msk       (0x700000UL)   /*!< ADCMBSB (Bitfield-Mask: 0x07)                         */
21414 /* ========================================================  GTSECSR  ======================================================== */
21415  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
21416  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
21417  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
21418  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
21419  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
21420  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
21421  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
21422  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
21423  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
21424  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
21425  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
21426  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
21427  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
21428  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
21429  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
21430  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
21431  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
21432  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
21433  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
21434  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
21435 /* ========================================================  GTSECR  ========================================================= */
21436  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
21437  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
21438  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
21439  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
21440  #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
21441  #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
21442  #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
21443  #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
21444  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
21445  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
21446  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
21447  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
21448  #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
21449  #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
21450  #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
21451  #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
21452  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
21453  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
21454  #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
21455  #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
21456  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
21457  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
21458  #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
21459  #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
21460 /* ========================================================  GTBER2  ========================================================= */
21461  #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
21462  #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
21463  #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
21464  #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
21465  #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
21466  #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
21467  #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
21468  #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
21469  #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
21470  #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
21471  #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
21472  #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
21473  #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
21474  #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
21475  #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
21476  #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
21477  #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
21478  #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
21479  #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
21480  #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
21481  #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
21482  #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
21483  #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
21484  #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
21485  #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
21486  #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
21487  #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
21488  #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
21489  #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
21490  #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
21491  #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
21492  #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
21493  #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
21494  #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
21495  #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
21496  #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
21497  #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
21498  #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
21499  #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
21500  #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
21501 /* ========================================================  GTOLBR  ========================================================= */
21502  #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
21503  #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
21504  #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
21505  #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
21506 /* ========================================================  GTICCR  ========================================================= */
21507  #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
21508  #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
21509  #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
21510  #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
21511  #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
21512  #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
21513  #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
21514  #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
21515  #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
21516  #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
21517  #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
21518  #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
21519  #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
21520  #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
21521  #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
21522  #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
21523  #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
21524  #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
21525  #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
21526  #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
21527  #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
21528  #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
21529  #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
21530  #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
21531  #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
21532  #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
21533  #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
21534  #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
21535  #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
21536  #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
21537  #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
21538  #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
21539  #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
21540  #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
21541  #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
21542  #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
21543  #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
21544  #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
21545  #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
21546  #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
21547 
21548 /* =========================================================================================================================== */
21549 /* ================                                         R_GPT_OPS                                         ================ */
21550 /* =========================================================================================================================== */
21551 
21552 /* =========================================================  OPSCR  ========================================================= */
21553  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
21554  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
21555  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
21556  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
21557  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
21558  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
21559  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
21560  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
21561  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
21562  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
21563  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
21564  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
21565  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
21566  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
21567  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
21568  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
21569  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
21570  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
21571  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
21572  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
21573  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
21574  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
21575  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
21576  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
21577  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
21578  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
21579  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
21580  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
21581  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
21582  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
21583  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
21584  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
21585  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
21586  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
21587 
21588 /* =========================================================================================================================== */
21589 /* ================                                        R_GPT_POEG0                                        ================ */
21590 /* =========================================================================================================================== */
21591 
21592 /* =========================================================  POEGG  ========================================================= */
21593  #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
21594  #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
21595  #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
21596  #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
21597  #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
21598  #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
21599  #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
21600  #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
21601  #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
21602  #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
21603  #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
21604  #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
21605  #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
21606  #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
21607  #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
21608  #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
21609  #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
21610  #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
21611  #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
21612  #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
21613  #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
21614  #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
21615  #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
21616  #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
21617 /* ========================================================  GTONCWP  ======================================================== */
21618  #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
21619  #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
21620  #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
21621  #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
21622 /* ========================================================  GTONCCR  ======================================================== */
21623  #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
21624  #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
21625  #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
21626  #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
21627  #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
21628  #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */
21629 
21630 /* =========================================================================================================================== */
21631 /* ================                                           R_ICU                                           ================ */
21632 /* =========================================================================================================================== */
21633 
21634 /* =========================================================  IRQCR  ========================================================= */
21635  #define R_ICU_IRQCR_FLTEN_Pos              (7UL)          /*!< FLTEN (Bit 7)                                         */
21636  #define R_ICU_IRQCR_FLTEN_Msk              (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
21637  #define R_ICU_IRQCR_FCLKSEL_Pos            (4UL)          /*!< FCLKSEL (Bit 4)                                       */
21638  #define R_ICU_IRQCR_FCLKSEL_Msk            (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
21639  #define R_ICU_IRQCR_LOCOSEL_Pos            (3UL)          /*!< LOCOSEL (Bit 3)                                       */
21640  #define R_ICU_IRQCR_LOCOSEL_Msk            (0x8UL)        /*!< LOCOSEL (Bitfield-Mask: 0x01)                         */
21641  #define R_ICU_IRQCR_IRQMD_Pos              (0UL)          /*!< IRQMD (Bit 0)                                         */
21642  #define R_ICU_IRQCR_IRQMD_Msk              (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
21643 /* =========================================================  NMISR  ========================================================= */
21644  #define R_ICU_NMISR_SPEST_Pos              (12UL)         /*!< SPEST (Bit 12)                                        */
21645  #define R_ICU_NMISR_SPEST_Msk              (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
21646  #define R_ICU_NMISR_BUSMST_Pos             (11UL)         /*!< BUSMST (Bit 11)                                       */
21647  #define R_ICU_NMISR_BUSMST_Msk             (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
21648  #define R_ICU_NMISR_BUSSST_Pos             (10UL)         /*!< BUSSST (Bit 10)                                       */
21649  #define R_ICU_NMISR_BUSSST_Msk             (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
21650  #define R_ICU_NMISR_RECCST_Pos             (9UL)          /*!< RECCST (Bit 9)                                        */
21651  #define R_ICU_NMISR_RECCST_Msk             (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
21652  #define R_ICU_NMISR_RPEST_Pos              (8UL)          /*!< RPEST (Bit 8)                                         */
21653  #define R_ICU_NMISR_RPEST_Msk              (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
21654  #define R_ICU_NMISR_NMIST_Pos              (7UL)          /*!< NMIST (Bit 7)                                         */
21655  #define R_ICU_NMISR_NMIST_Msk              (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
21656  #define R_ICU_NMISR_OSTST_Pos              (6UL)          /*!< OSTST (Bit 6)                                         */
21657  #define R_ICU_NMISR_OSTST_Msk              (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
21658  #define R_ICU_NMISR_VBATTST_Pos            (4UL)          /*!< VBATTST (Bit 4)                                       */
21659  #define R_ICU_NMISR_VBATTST_Msk            (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
21660  #define R_ICU_NMISR_LVD2ST_Pos             (3UL)          /*!< LVD2ST (Bit 3)                                        */
21661  #define R_ICU_NMISR_LVD2ST_Msk             (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
21662  #define R_ICU_NMISR_LVD1ST_Pos             (2UL)          /*!< LVD1ST (Bit 2)                                        */
21663  #define R_ICU_NMISR_LVD1ST_Msk             (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
21664  #define R_ICU_NMISR_WDTST_Pos              (1UL)          /*!< WDTST (Bit 1)                                         */
21665  #define R_ICU_NMISR_WDTST_Msk              (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
21666  #define R_ICU_NMISR_IWDTST_Pos             (0UL)          /*!< IWDTST (Bit 0)                                        */
21667  #define R_ICU_NMISR_IWDTST_Msk             (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
21668  #define R_ICU_NMISR_TZFST_Pos              (13UL)         /*!< TZFST (Bit 13)                                        */
21669  #define R_ICU_NMISR_TZFST_Msk              (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
21670  #define R_ICU_NMISR_CPEST_Pos              (15UL)         /*!< CPEST (Bit 15)                                        */
21671  #define R_ICU_NMISR_CPEST_Msk              (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
21672 /* =========================================================  NMIER  ========================================================= */
21673  #define R_ICU_NMIER_SPEEN_Pos              (12UL)         /*!< SPEEN (Bit 12)                                        */
21674  #define R_ICU_NMIER_SPEEN_Msk              (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
21675  #define R_ICU_NMIER_BUSMEN_Pos             (11UL)         /*!< BUSMEN (Bit 11)                                       */
21676  #define R_ICU_NMIER_BUSMEN_Msk             (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
21677  #define R_ICU_NMIER_BUSSEN_Pos             (10UL)         /*!< BUSSEN (Bit 10)                                       */
21678  #define R_ICU_NMIER_BUSSEN_Msk             (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
21679  #define R_ICU_NMIER_RECCEN_Pos             (9UL)          /*!< RECCEN (Bit 9)                                        */
21680  #define R_ICU_NMIER_RECCEN_Msk             (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
21681  #define R_ICU_NMIER_RPEEN_Pos              (8UL)          /*!< RPEEN (Bit 8)                                         */
21682  #define R_ICU_NMIER_RPEEN_Msk              (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
21683  #define R_ICU_NMIER_NMIEN_Pos              (7UL)          /*!< NMIEN (Bit 7)                                         */
21684  #define R_ICU_NMIER_NMIEN_Msk              (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
21685  #define R_ICU_NMIER_OSTEN_Pos              (6UL)          /*!< OSTEN (Bit 6)                                         */
21686  #define R_ICU_NMIER_OSTEN_Msk              (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
21687  #define R_ICU_NMIER_VBATTEN_Pos            (4UL)          /*!< VBATTEN (Bit 4)                                       */
21688  #define R_ICU_NMIER_VBATTEN_Msk            (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
21689  #define R_ICU_NMIER_LVD2EN_Pos             (3UL)          /*!< LVD2EN (Bit 3)                                        */
21690  #define R_ICU_NMIER_LVD2EN_Msk             (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
21691  #define R_ICU_NMIER_LVD1EN_Pos             (2UL)          /*!< LVD1EN (Bit 2)                                        */
21692  #define R_ICU_NMIER_LVD1EN_Msk             (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
21693  #define R_ICU_NMIER_WDTEN_Pos              (1UL)          /*!< WDTEN (Bit 1)                                         */
21694  #define R_ICU_NMIER_WDTEN_Msk              (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
21695  #define R_ICU_NMIER_IWDTEN_Pos             (0UL)          /*!< IWDTEN (Bit 0)                                        */
21696  #define R_ICU_NMIER_IWDTEN_Msk             (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
21697  #define R_ICU_NMIER_TZFEN_Pos              (13UL)         /*!< TZFEN (Bit 13)                                        */
21698  #define R_ICU_NMIER_TZFEN_Msk              (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
21699  #define R_ICU_NMIER_CPEEN_Pos              (15UL)         /*!< CPEEN (Bit 15)                                        */
21700  #define R_ICU_NMIER_CPEEN_Msk              (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
21701 /* ========================================================  NMICLR  ========================================================= */
21702  #define R_ICU_NMICLR_SPECLR_Pos            (12UL)         /*!< SPECLR (Bit 12)                                       */
21703  #define R_ICU_NMICLR_SPECLR_Msk            (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
21704  #define R_ICU_NMICLR_BUSMCLR_Pos           (11UL)         /*!< BUSMCLR (Bit 11)                                      */
21705  #define R_ICU_NMICLR_BUSMCLR_Msk           (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
21706  #define R_ICU_NMICLR_BUSSCLR_Pos           (10UL)         /*!< BUSSCLR (Bit 10)                                      */
21707  #define R_ICU_NMICLR_BUSSCLR_Msk           (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
21708  #define R_ICU_NMICLR_RECCCLR_Pos           (9UL)          /*!< RECCCLR (Bit 9)                                       */
21709  #define R_ICU_NMICLR_RECCCLR_Msk           (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
21710  #define R_ICU_NMICLR_RPECLR_Pos            (8UL)          /*!< RPECLR (Bit 8)                                        */
21711  #define R_ICU_NMICLR_RPECLR_Msk            (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
21712  #define R_ICU_NMICLR_NMICLR_Pos            (7UL)          /*!< NMICLR (Bit 7)                                        */
21713  #define R_ICU_NMICLR_NMICLR_Msk            (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
21714  #define R_ICU_NMICLR_OSTCLR_Pos            (6UL)          /*!< OSTCLR (Bit 6)                                        */
21715  #define R_ICU_NMICLR_OSTCLR_Msk            (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
21716  #define R_ICU_NMICLR_VBATTCLR_Pos          (4UL)          /*!< VBATTCLR (Bit 4)                                      */
21717  #define R_ICU_NMICLR_VBATTCLR_Msk          (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
21718  #define R_ICU_NMICLR_LVD2CLR_Pos           (3UL)          /*!< LVD2CLR (Bit 3)                                       */
21719  #define R_ICU_NMICLR_LVD2CLR_Msk           (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
21720  #define R_ICU_NMICLR_LVD1CLR_Pos           (2UL)          /*!< LVD1CLR (Bit 2)                                       */
21721  #define R_ICU_NMICLR_LVD1CLR_Msk           (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
21722  #define R_ICU_NMICLR_WDTCLR_Pos            (1UL)          /*!< WDTCLR (Bit 1)                                        */
21723  #define R_ICU_NMICLR_WDTCLR_Msk            (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
21724  #define R_ICU_NMICLR_IWDTCLR_Pos           (0UL)          /*!< IWDTCLR (Bit 0)                                       */
21725  #define R_ICU_NMICLR_IWDTCLR_Msk           (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
21726  #define R_ICU_NMICLR_TZFCLR_Pos            (13UL)         /*!< TZFCLR (Bit 13)                                       */
21727  #define R_ICU_NMICLR_TZFCLR_Msk            (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
21728  #define R_ICU_NMICLR_CPECLR_Pos            (15UL)         /*!< CPECLR (Bit 15)                                       */
21729  #define R_ICU_NMICLR_CPECLR_Msk            (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
21730 /* =========================================================  NMICR  ========================================================= */
21731  #define R_ICU_NMICR_NFLTEN_Pos             (7UL)          /*!< NFLTEN (Bit 7)                                        */
21732  #define R_ICU_NMICR_NFLTEN_Msk             (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
21733  #define R_ICU_NMICR_NFCLKSEL_Pos           (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
21734  #define R_ICU_NMICR_NFCLKSEL_Msk           (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
21735  #define R_ICU_NMICR_NMIMD_Pos              (0UL)          /*!< NMIMD (Bit 0)                                         */
21736  #define R_ICU_NMICR_NMIMD_Msk              (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
21737 /* =========================================================  IELSR  ========================================================= */
21738  #define R_ICU_IELSR_DTCE_Pos               (24UL)         /*!< DTCE (Bit 24)                                         */
21739  #define R_ICU_IELSR_DTCE_Msk               (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
21740  #define R_ICU_IELSR_IR_Pos                 (16UL)         /*!< IR (Bit 16)                                           */
21741  #define R_ICU_IELSR_IR_Msk                 (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
21742  #define R_ICU_IELSR_IELS_Pos               (0UL)          /*!< IELS (Bit 0)                                          */
21743  #define R_ICU_IELSR_IELS_Msk               (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
21744 /* =========================================================  DELSR  ========================================================= */
21745  #define R_ICU_DELSR_IR_Pos                 (16UL)         /*!< IR (Bit 16)                                           */
21746  #define R_ICU_DELSR_IR_Msk                 (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
21747  #define R_ICU_DELSR_DELS_Pos               (0UL)          /*!< DELS (Bit 0)                                          */
21748  #define R_ICU_DELSR_DELS_Msk               (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
21749 /* ========================================================  SELSR0  ========================================================= */
21750  #define R_ICU_SELSR0_SELS_Pos              (0UL)          /*!< SELS (Bit 0)                                          */
21751  #define R_ICU_SELSR0_SELS_Msk              (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
21752 /* =========================================================  WUPEN  ========================================================= */
21753  #define R_ICU_WUPEN_IIC0WUPEN_Pos          (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
21754  #define R_ICU_WUPEN_IIC0WUPEN_Msk          (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
21755  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos        (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
21756  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk        (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
21757  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos        (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
21758  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk        (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
21759  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos        (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
21760  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk        (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
21761  #define R_ICU_WUPEN_USBFSWUPEN_Pos         (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
21762  #define R_ICU_WUPEN_USBFSWUPEN_Msk         (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
21763  #define R_ICU_WUPEN_USBHSWUPEN_Pos         (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
21764  #define R_ICU_WUPEN_USBHSWUPEN_Msk         (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
21765  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos        (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
21766  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk        (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
21767  #define R_ICU_WUPEN_RTCALMWUPEN_Pos        (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
21768  #define R_ICU_WUPEN_RTCALMWUPEN_Msk        (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
21769  #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos       (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
21770  #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk       (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
21771  #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos       (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
21772  #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk       (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
21773  #define R_ICU_WUPEN_VBATTWUPEN_Pos         (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
21774  #define R_ICU_WUPEN_VBATTWUPEN_Msk         (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
21775  #define R_ICU_WUPEN_LVD2WUPEN_Pos          (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
21776  #define R_ICU_WUPEN_LVD2WUPEN_Msk          (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
21777  #define R_ICU_WUPEN_LVD1WUPEN_Pos          (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
21778  #define R_ICU_WUPEN_LVD1WUPEN_Msk          (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
21779  #define R_ICU_WUPEN_KEYWUPEN_Pos           (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
21780  #define R_ICU_WUPEN_KEYWUPEN_Msk           (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
21781  #define R_ICU_WUPEN_IWDTWUPEN_Pos          (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
21782  #define R_ICU_WUPEN_IWDTWUPEN_Msk          (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
21783  #define R_ICU_WUPEN_IRQWUPEN_Pos           (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
21784  #define R_ICU_WUPEN_IRQWUPEN_Msk           (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
21785 /* ========================================================  WUPEN1  ========================================================= */
21786  #define R_ICU_WUPEN1_SOSCWUPEN_Pos         (7UL)          /*!< SOSCWUPEN (Bit 7)                                     */
21787  #define R_ICU_WUPEN1_SOSCWUPEN_Msk         (0x80UL)       /*!< SOSCWUPEN (Bitfield-Mask: 0x01)                       */
21788  #define R_ICU_WUPEN1_I3CWUPEN_Pos          (11UL)         /*!< I3CWUPEN (Bit 11)                                     */
21789  #define R_ICU_WUPEN1_I3CWUPEN_Msk          (0x800UL)      /*!< I3CWUPEN (Bitfield-Mask: 0x01)                        */
21790 /* ========================================================  WUPEN2  ========================================================= */
21791  #define R_ICU_WUPEN2_INTUR0WUPEN_Pos       (0UL)          /*!< INTUR0WUPEN (Bit 0)                                   */
21792  #define R_ICU_WUPEN2_INTUR0WUPEN_Msk       (0x1UL)        /*!< INTUR0WUPEN (Bitfield-Mask: 0x01)                     */
21793  #define R_ICU_WUPEN2_INTURE0WUPEN_Pos      (1UL)          /*!< INTURE0WUPEN (Bit 1)                                  */
21794  #define R_ICU_WUPEN2_INTURE0WUPEN_Msk      (0x2UL)        /*!< INTURE0WUPEN (Bitfield-Mask: 0x01)                    */
21795  #define R_ICU_WUPEN2_INTUR1WUPEN_Pos       (2UL)          /*!< INTUR1WUPEN (Bit 2)                                   */
21796  #define R_ICU_WUPEN2_INTUR1WUPEN_Msk       (0x4UL)        /*!< INTUR1WUPEN (Bitfield-Mask: 0x01)                     */
21797  #define R_ICU_WUPEN2_INTURE1WUPEN_Pos      (3UL)          /*!< INTURE1WUPEN (Bit 3)                                  */
21798  #define R_ICU_WUPEN2_INTURE1WUPEN_Msk      (0x8UL)        /*!< INTURE1WUPEN (Bitfield-Mask: 0x01)                    */
21799  #define R_ICU_WUPEN2_EXLVDVBATWUPEN_Pos    (4UL)          /*!< EXLVDVBATWUPEN (Bit 4)                                */
21800  #define R_ICU_WUPEN2_EXLVDVBATWUPEN_Msk    (0x10UL)       /*!< EXLVDVBATWUPEN (Bitfield-Mask: 0x01)                  */
21801  #define R_ICU_WUPEN2_LVDVRTCWUPEN_Pos      (5UL)          /*!< LVDVRTCWUPEN (Bit 5)                                  */
21802  #define R_ICU_WUPEN2_LVDVRTCWUPEN_Msk      (0x20UL)       /*!< LVDVRTCWUPEN (Bitfield-Mask: 0x01)                    */
21803  #define R_ICU_WUPEN2_EXLVDWUPEN_Pos        (6UL)          /*!< EXLVDWUPEN (Bit 6)                                    */
21804  #define R_ICU_WUPEN2_EXLVDWUPEN_Msk        (0x40UL)       /*!< EXLVDWUPEN (Bitfield-Mask: 0x01)                      */
21805 /* =========================================================  IELEN  ========================================================= */
21806  #define R_ICU_IELEN_IELEN_Pos              (1UL)          /*!< IELEN (Bit 1)                                         */
21807  #define R_ICU_IELEN_IELEN_Msk              (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
21808  #define R_ICU_IELEN_RTCINTEN_Pos           (0UL)          /*!< RTCINTEN (Bit 0)                                      */
21809  #define R_ICU_IELEN_RTCINTEN_Msk           (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
21810 
21811 /* =========================================================================================================================== */
21812 /* ================                                          R_IIC0                                           ================ */
21813 /* =========================================================================================================================== */
21814 
21815 /* =========================================================  ICCR1  ========================================================= */
21816  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
21817  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
21818  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
21819  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
21820  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
21821  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
21822  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
21823  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
21824  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
21825  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
21826  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
21827  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
21828  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
21829  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
21830  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
21831  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
21832 /* =========================================================  ICCR2  ========================================================= */
21833  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
21834  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
21835  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
21836  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
21837  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
21838  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
21839  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
21840  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
21841  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
21842  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
21843  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
21844  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
21845 /* =========================================================  ICMR1  ========================================================= */
21846  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
21847  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
21848  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
21849  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
21850  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
21851  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
21852  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
21853  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
21854 /* =========================================================  ICMR2  ========================================================= */
21855  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
21856  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
21857  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
21858  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
21859  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
21860  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
21861  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
21862  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
21863  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
21864  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
21865 /* =========================================================  ICMR3  ========================================================= */
21866  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
21867  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
21868  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
21869  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
21870  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
21871  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
21872  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
21873  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
21874  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
21875  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
21876  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
21877  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
21878  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
21879  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
21880 /* =========================================================  ICFER  ========================================================= */
21881  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
21882  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
21883  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
21884  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
21885  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
21886  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
21887  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
21888  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
21889  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
21890  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
21891  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
21892  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
21893  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
21894  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
21895  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
21896  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
21897 /* =========================================================  ICSER  ========================================================= */
21898  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
21899  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
21900  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
21901  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
21902  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
21903  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
21904  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
21905  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
21906  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
21907  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
21908  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
21909  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
21910 /* =========================================================  ICIER  ========================================================= */
21911  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
21912  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
21913  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
21914  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
21915  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
21916  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
21917  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
21918  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
21919  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
21920  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
21921  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
21922  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
21923  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
21924  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
21925  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
21926  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
21927 /* =========================================================  ICSR1  ========================================================= */
21928  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
21929  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
21930  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
21931  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
21932  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
21933  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
21934  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
21935  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
21936  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
21937  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
21938  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
21939  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
21940 /* =========================================================  ICSR2  ========================================================= */
21941  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
21942  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
21943  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
21944  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
21945  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
21946  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
21947  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
21948  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
21949  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
21950  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
21951  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
21952  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
21953  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
21954  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
21955  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
21956  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
21957 /* =========================================================  ICBRL  ========================================================= */
21958  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
21959  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
21960 /* =========================================================  ICBRH  ========================================================= */
21961  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
21962  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
21963 /* =========================================================  ICDRT  ========================================================= */
21964  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
21965  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
21966 /* =========================================================  ICDRR  ========================================================= */
21967  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
21968  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
21969 /* =========================================================  ICWUR  ========================================================= */
21970  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
21971  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
21972  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
21973  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
21974  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
21975  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
21976  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
21977  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
21978  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
21979  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
21980 /* ========================================================  ICWUR2  ========================================================= */
21981  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
21982  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
21983  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
21984  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
21985  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
21986  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
21987 
21988 /* =========================================================================================================================== */
21989 /* ================                                          R_IRDA                                           ================ */
21990 /* =========================================================================================================================== */
21991 
21992 /* =========================================================  IRCR  ========================================================== */
21993  #define R_IRDA_IRCR_IRE_Pos        (7UL)    /*!< IRE (Bit 7)                                           */
21994  #define R_IRDA_IRCR_IRE_Msk        (0x80UL) /*!< IRE (Bitfield-Mask: 0x01)                             */
21995  #define R_IRDA_IRCR_IRTXINV_Pos    (3UL)    /*!< IRTXINV (Bit 3)                                       */
21996  #define R_IRDA_IRCR_IRTXINV_Msk    (0x8UL)  /*!< IRTXINV (Bitfield-Mask: 0x01)                         */
21997  #define R_IRDA_IRCR_IRRXINV_Pos    (2UL)    /*!< IRRXINV (Bit 2)                                       */
21998  #define R_IRDA_IRCR_IRRXINV_Msk    (0x4UL)  /*!< IRRXINV (Bitfield-Mask: 0x01)                         */
21999 
22000 /* =========================================================================================================================== */
22001 /* ================                                          R_IWDT                                           ================ */
22002 /* =========================================================================================================================== */
22003 
22004 /* ========================================================  IWDTRR  ========================================================= */
22005  #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
22006  #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
22007 /* ========================================================  IWDTCR  ========================================================= */
22008  #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
22009  #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
22010  #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
22011  #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
22012  #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
22013  #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
22014  #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
22015  #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
22016 /* ========================================================  IWDTSR  ========================================================= */
22017  #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
22018  #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
22019  #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
22020  #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
22021  #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
22022  #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
22023 /* ========================================================  IWDTRCR  ======================================================== */
22024  #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
22025  #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
22026 /* =======================================================  IWDTCSTPR  ======================================================= */
22027  #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
22028  #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
22029 
22030 /* =========================================================================================================================== */
22031 /* ================                                          R_I3C0                                           ================ */
22032 /* =========================================================================================================================== */
22033 
22034 /* =========================================================  PRTS  ========================================================== */
22035  #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
22036  #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
22037 /* =========================================================  CECTL  ========================================================= */
22038  #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
22039  #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
22040 /* =========================================================  BCTL  ========================================================== */
22041  #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
22042  #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
22043  #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
22044  #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
22045  #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
22046  #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
22047  #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
22048  #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
22049  #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
22050  #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
22051  #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
22052  #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
22053 /* ========================================================  MSDVAD  ========================================================= */
22054  #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
22055  #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
22056  #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
22057  #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
22058 /* ========================================================  RSTCTL  ========================================================= */
22059  #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
22060  #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
22061  #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
22062  #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
22063  #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
22064  #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
22065  #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
22066  #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
22067  #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
22068  #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
22069  #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
22070  #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
22071  #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
22072  #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
22073  #define R_I3C0_RSTCTL_HCMDQRST_Pos     (9UL)          /*!< HCMDQRST (Bit 9)                                      */
22074  #define R_I3C0_RSTCTL_HCMDQRST_Msk     (0x200UL)      /*!< HCMDQRST (Bitfield-Mask: 0x01)                        */
22075  #define R_I3C0_RSTCTL_HRSPQRST_Pos     (10UL)         /*!< HRSPQRST (Bit 10)                                     */
22076  #define R_I3C0_RSTCTL_HRSPQRST_Msk     (0x400UL)      /*!< HRSPQRST (Bitfield-Mask: 0x01)                        */
22077  #define R_I3C0_RSTCTL_HTDBRST_Pos      (11UL)         /*!< HTDBRST (Bit 11)                                      */
22078  #define R_I3C0_RSTCTL_HTDBRST_Msk      (0x800UL)      /*!< HTDBRST (Bitfield-Mask: 0x01)                         */
22079  #define R_I3C0_RSTCTL_HRDBRST_Pos      (12UL)         /*!< HRDBRST (Bit 12)                                      */
22080  #define R_I3C0_RSTCTL_HRDBRST_Msk      (0x1000UL)     /*!< HRDBRST (Bitfield-Mask: 0x01)                         */
22081  #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
22082  #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
22083 /* =========================================================  PRSST  ========================================================= */
22084  #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
22085  #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
22086  #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
22087  #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
22088  #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
22089  #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
22090 /* =========================================================  INST  ========================================================== */
22091  #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
22092  #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
22093 /* =========================================================  INSTE  ========================================================= */
22094  #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
22095  #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
22096 /* =========================================================  INIE  ========================================================== */
22097  #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
22098  #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
22099 /* ========================================================  INSTFC  ========================================================= */
22100  #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
22101  #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
22102 /* =========================================================  DVCT  ========================================================== */
22103  #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
22104  #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
22105 /* ========================================================  IBINCTL  ======================================================== */
22106  #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
22107  #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
22108  #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
22109  #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
22110  #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
22111  #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
22112 /* =========================================================  BFCTL  ========================================================= */
22113  #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
22114  #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
22115  #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
22116  #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
22117  #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
22118  #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
22119  #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
22120  #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
22121  #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
22122  #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
22123  #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
22124  #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
22125  #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
22126  #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
22127 /* =========================================================  SVCTL  ========================================================= */
22128  #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
22129  #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
22130  #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
22131  #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
22132  #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
22133  #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
22134  #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
22135  #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
22136  #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
22137  #define R_I3C0_SVCTL_SVAEn_Msk         (0x70000UL)    /*!< SVAEn (Bitfield-Mask: 0x07)                           */
22138 /* =======================================================  REFCKCTL  ======================================================== */
22139  #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
22140  #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
22141 /* =========================================================  STDBR  ========================================================= */
22142  #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
22143  #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
22144  #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
22145  #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
22146  #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
22147  #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
22148  #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
22149  #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
22150  #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
22151  #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
22152 /* =========================================================  EXTBR  ========================================================= */
22153  #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
22154  #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
22155  #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
22156  #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
22157  #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
22158  #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
22159  #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
22160  #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
22161 /* ========================================================  BFRECDT  ======================================================== */
22162  #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
22163  #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
22164 /* ========================================================  BAVLCDT  ======================================================== */
22165  #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
22166  #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
22167 /* ========================================================  BIDLCDT  ======================================================== */
22168  #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
22169  #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
22170 /* ========================================================  OUTCTL  ========================================================= */
22171  #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
22172  #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
22173  #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
22174  #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
22175  #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
22176  #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
22177  #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
22178  #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
22179  #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
22180  #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
22181  #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
22182  #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
22183 /* =========================================================  INCTL  ========================================================= */
22184  #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
22185  #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
22186  #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
22187  #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
22188 /* ========================================================  TMOCTL  ========================================================= */
22189  #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
22190  #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
22191  #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
22192  #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
22193  #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
22194  #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
22195  #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
22196  #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
22197 /* =========================================================  WUCTL  ========================================================= */
22198  #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
22199  #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
22200  #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
22201  #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
22202  #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
22203  #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
22204  #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
22205  #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
22206 /* ========================================================  ACKCTL  ========================================================= */
22207  #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
22208  #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
22209  #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
22210  #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
22211  #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
22212  #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
22213 /* =======================================================  SCSTRCTL  ======================================================== */
22214  #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
22215  #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
22216  #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
22217  #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
22218 /* =======================================================  SCSTLCTL  ======================================================== */
22219  #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
22220  #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
22221  #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
22222  #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
22223  #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
22224  #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
22225  #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
22226  #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
22227  #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
22228  #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
22229 /* ========================================================  SVTDLG0  ======================================================== */
22230  #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
22231  #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
22232 /* =========================================================  STCTL  ========================================================= */
22233  #define R_I3C0_STCTL_STOE_Pos          (0UL)          /*!< STOE (Bit 0)                                          */
22234  #define R_I3C0_STCTL_STOE_Msk          (0x1UL)        /*!< STOE (Bitfield-Mask: 0x01)                            */
22235 /* =========================================================  ATCTL  ========================================================= */
22236  #define R_I3C0_ATCTL_ATTRGS_Pos        (0UL)          /*!< ATTRGS (Bit 0)                                        */
22237  #define R_I3C0_ATCTL_ATTRGS_Msk        (0x1UL)        /*!< ATTRGS (Bitfield-Mask: 0x01)                          */
22238  #define R_I3C0_ATCTL_MREFOE_Pos        (1UL)          /*!< MREFOE (Bit 1)                                        */
22239  #define R_I3C0_ATCTL_MREFOE_Msk        (0x2UL)        /*!< MREFOE (Bitfield-Mask: 0x01)                          */
22240  #define R_I3C0_ATCTL_AMEOE_Pos         (2UL)          /*!< AMEOE (Bit 2)                                         */
22241  #define R_I3C0_ATCTL_AMEOE_Msk         (0x4UL)        /*!< AMEOE (Bitfield-Mask: 0x01)                           */
22242  #define R_I3C0_ATCTL_CDIV_Pos          (8UL)          /*!< CDIV (Bit 8)                                          */
22243  #define R_I3C0_ATCTL_CDIV_Msk          (0xff00UL)     /*!< CDIV (Bitfield-Mask: 0xff)                            */
22244 /* =========================================================  ATTRG  ========================================================= */
22245  #define R_I3C0_ATTRG_ATSTRG_Pos        (0UL)          /*!< ATSTRG (Bit 0)                                        */
22246  #define R_I3C0_ATTRG_ATSTRG_Msk        (0x1UL)        /*!< ATSTRG (Bitfield-Mask: 0x01)                          */
22247 /* ========================================================  ATCCNTE  ======================================================== */
22248  #define R_I3C0_ATCCNTE_ATCE_Pos        (0UL)          /*!< ATCE (Bit 0)                                          */
22249  #define R_I3C0_ATCCNTE_ATCE_Msk        (0x1UL)        /*!< ATCE (Bitfield-Mask: 0x01)                            */
22250 /* ========================================================  CNDCTL  ========================================================= */
22251  #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
22252  #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
22253  #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
22254  #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
22255  #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
22256  #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
22257 /* ========================================================  NCMDQP  ========================================================= */
22258 /* ========================================================  NRSPQP  ========================================================= */
22259 /* ========================================================  NTDTBP0  ======================================================== */
22260 /* ========================================================  NIBIQP  ========================================================= */
22261 /* =========================================================  NRSQP  ========================================================= */
22262 /* ========================================================  HCMDQP  ========================================================= */
22263  #define R_I3C0_HCMDQP_HCMDQP_Pos       (0UL)          /*!< HCMDQP (Bit 0)                                        */
22264  #define R_I3C0_HCMDQP_HCMDQP_Msk       (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff)                    */
22265 /* ========================================================  HRSPQP  ========================================================= */
22266  #define R_I3C0_HRSPQP_HRSPQP_Pos       (0UL)          /*!< HRSPQP (Bit 0)                                        */
22267  #define R_I3C0_HRSPQP_HRSPQP_Msk       (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff)                    */
22268 /* ========================================================  HTDTBP  ========================================================= */
22269  #define R_I3C0_HTDTBP_HTDTBP_Pos       (0UL)          /*!< HTDTBP (Bit 0)                                        */
22270  #define R_I3C0_HTDTBP_HTDTBP_Msk       (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff)                    */
22271 /* ========================================================  NQTHCTL  ======================================================== */
22272  #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
22273  #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
22274  #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
22275  #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
22276  #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
22277  #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
22278  #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
22279  #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
22280 /* =======================================================  NTBTHCTL0  ======================================================= */
22281  #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
22282  #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
22283  #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
22284  #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
22285  #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
22286  #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
22287  #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
22288  #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
22289 /* =======================================================  NRQTHCTL  ======================================================== */
22290  #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
22291  #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
22292 /* ========================================================  HQTHCTL  ======================================================== */
22293  #define R_I3C0_HQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
22294  #define R_I3C0_HQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
22295  #define R_I3C0_HQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
22296  #define R_I3C0_HQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
22297 /* =======================================================  HTBTHCTL  ======================================================== */
22298  #define R_I3C0_HTBTHCTL_TXDBTH_Pos     (0UL)          /*!< TXDBTH (Bit 0)                                        */
22299  #define R_I3C0_HTBTHCTL_TXDBTH_Msk     (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
22300  #define R_I3C0_HTBTHCTL_RXDBTH_Pos     (8UL)          /*!< RXDBTH (Bit 8)                                        */
22301  #define R_I3C0_HTBTHCTL_RXDBTH_Msk     (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
22302  #define R_I3C0_HTBTHCTL_TXSTTH_Pos     (16UL)         /*!< TXSTTH (Bit 16)                                       */
22303  #define R_I3C0_HTBTHCTL_TXSTTH_Msk     (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
22304  #define R_I3C0_HTBTHCTL_RXSTTH_Pos     (24UL)         /*!< RXSTTH (Bit 24)                                       */
22305  #define R_I3C0_HTBTHCTL_RXSTTH_Msk     (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
22306 /* ==========================================================  BST  ========================================================== */
22307  #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
22308  #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
22309  #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
22310  #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
22311  #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
22312  #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
22313  #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
22314  #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
22315  #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
22316  #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
22317  #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
22318  #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
22319  #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
22320  #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
22321  #define R_I3C0_BST_WUCNDDF_Pos         (24UL)         /*!< WUCNDDF (Bit 24)                                      */
22322  #define R_I3C0_BST_WUCNDDF_Msk         (0x1000000UL)  /*!< WUCNDDF (Bitfield-Mask: 0x01)                         */
22323 /* =========================================================  BSTE  ========================================================== */
22324  #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
22325  #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
22326  #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
22327  #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
22328  #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
22329  #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
22330  #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
22331  #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
22332  #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
22333  #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
22334  #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
22335  #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
22336  #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
22337  #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
22338  #define R_I3C0_BSTE_WUCNDDE_Pos        (24UL)         /*!< WUCNDDE (Bit 24)                                      */
22339  #define R_I3C0_BSTE_WUCNDDE_Msk        (0x1000000UL)  /*!< WUCNDDE (Bitfield-Mask: 0x01)                         */
22340 /* ==========================================================  BIE  ========================================================== */
22341  #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
22342  #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
22343  #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
22344  #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
22345  #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
22346  #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
22347  #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
22348  #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
22349  #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
22350  #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
22351  #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
22352  #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
22353  #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
22354  #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
22355  #define R_I3C0_BIE_WUCNDDIE_Pos        (24UL)         /*!< WUCNDDIE (Bit 24)                                     */
22356  #define R_I3C0_BIE_WUCNDDIE_Msk        (0x1000000UL)  /*!< WUCNDDIE (Bitfield-Mask: 0x01)                        */
22357 /* =========================================================  BSTFC  ========================================================= */
22358  #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
22359  #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
22360  #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
22361  #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
22362  #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
22363  #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
22364  #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
22365  #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
22366  #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
22367  #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
22368  #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
22369  #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
22370  #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
22371  #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
22372  #define R_I3C0_BSTFC_WUCNDDFC_Pos      (24UL)         /*!< WUCNDDFC (Bit 24)                                     */
22373  #define R_I3C0_BSTFC_WUCNDDFC_Msk      (0x1000000UL)  /*!< WUCNDDFC (Bitfield-Mask: 0x01)                        */
22374 /* =========================================================  NTST  ========================================================== */
22375  #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
22376  #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
22377  #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
22378  #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
22379  #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
22380  #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
22381  #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
22382  #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
22383  #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
22384  #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
22385  #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
22386  #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
22387  #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
22388  #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
22389  #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
22390  #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
22391 /* =========================================================  NTSTE  ========================================================= */
22392  #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
22393  #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
22394  #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
22395  #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
22396  #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
22397  #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
22398  #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
22399  #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
22400  #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
22401  #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
22402  #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
22403  #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
22404  #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
22405  #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
22406  #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
22407  #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
22408 /* =========================================================  NTIE  ========================================================== */
22409  #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
22410  #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
22411  #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
22412  #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
22413  #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
22414  #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
22415  #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
22416  #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
22417  #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
22418  #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
22419  #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
22420  #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
22421  #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
22422  #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
22423  #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
22424  #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
22425 /* ========================================================  NTSTFC  ========================================================= */
22426  #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
22427  #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
22428  #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
22429  #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
22430  #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
22431  #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
22432  #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
22433  #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
22434  #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
22435  #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
22436  #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
22437  #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
22438  #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
22439  #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
22440  #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
22441  #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
22442 /* =========================================================  HTST  ========================================================== */
22443  #define R_I3C0_HTST_TDBEF_Pos          (0UL)          /*!< TDBEF (Bit 0)                                         */
22444  #define R_I3C0_HTST_TDBEF_Msk          (0x1UL)        /*!< TDBEF (Bitfield-Mask: 0x01)                           */
22445  #define R_I3C0_HTST_RDBFF_Pos          (1UL)          /*!< RDBFF (Bit 1)                                         */
22446  #define R_I3C0_HTST_RDBFF_Msk          (0x2UL)        /*!< RDBFF (Bitfield-Mask: 0x01)                           */
22447  #define R_I3C0_HTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
22448  #define R_I3C0_HTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
22449  #define R_I3C0_HTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
22450  #define R_I3C0_HTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
22451  #define R_I3C0_HTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
22452  #define R_I3C0_HTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
22453  #define R_I3C0_HTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
22454  #define R_I3C0_HTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
22455 /* =========================================================  HTSTE  ========================================================= */
22456  #define R_I3C0_HTSTE_TDBEE_Pos         (0UL)          /*!< TDBEE (Bit 0)                                         */
22457  #define R_I3C0_HTSTE_TDBEE_Msk         (0x1UL)        /*!< TDBEE (Bitfield-Mask: 0x01)                           */
22458  #define R_I3C0_HTSTE_RDBFE_Pos         (1UL)          /*!< RDBFE (Bit 1)                                         */
22459  #define R_I3C0_HTSTE_RDBFE_Msk         (0x2UL)        /*!< RDBFE (Bitfield-Mask: 0x01)                           */
22460  #define R_I3C0_HTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
22461  #define R_I3C0_HTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
22462  #define R_I3C0_HTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
22463  #define R_I3C0_HTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
22464  #define R_I3C0_HTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
22465  #define R_I3C0_HTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
22466  #define R_I3C0_HTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
22467  #define R_I3C0_HTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
22468 /* =========================================================  HTIE  ========================================================== */
22469  #define R_I3C0_HTIE_TDBEIE_Pos         (0UL)          /*!< TDBEIE (Bit 0)                                        */
22470  #define R_I3C0_HTIE_TDBEIE_Msk         (0x1UL)        /*!< TDBEIE (Bitfield-Mask: 0x01)                          */
22471  #define R_I3C0_HTIE_RDBFIE_Pos         (1UL)          /*!< RDBFIE (Bit 1)                                        */
22472  #define R_I3C0_HTIE_RDBFIE_Msk         (0x2UL)        /*!< RDBFIE (Bitfield-Mask: 0x01)                          */
22473  #define R_I3C0_HTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
22474  #define R_I3C0_HTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
22475  #define R_I3C0_HTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
22476  #define R_I3C0_HTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
22477  #define R_I3C0_HTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
22478  #define R_I3C0_HTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
22479  #define R_I3C0_HTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
22480  #define R_I3C0_HTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
22481 /* ========================================================  HTSTFC  ========================================================= */
22482  #define R_I3C0_HTSTFC_TDBEFC_Pos       (0UL)          /*!< TDBEFC (Bit 0)                                        */
22483  #define R_I3C0_HTSTFC_TDBEFC_Msk       (0x1UL)        /*!< TDBEFC (Bitfield-Mask: 0x01)                          */
22484  #define R_I3C0_HTSTFC_RDBFFC_Pos       (1UL)          /*!< RDBFFC (Bit 1)                                        */
22485  #define R_I3C0_HTSTFC_RDBFFC_Msk       (0x2UL)        /*!< RDBFFC (Bitfield-Mask: 0x01)                          */
22486  #define R_I3C0_HTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
22487  #define R_I3C0_HTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
22488  #define R_I3C0_HTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
22489  #define R_I3C0_HTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
22490  #define R_I3C0_HTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
22491  #define R_I3C0_HTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
22492  #define R_I3C0_HTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
22493  #define R_I3C0_HTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
22494 /* =========================================================  BCST  ========================================================== */
22495  #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
22496  #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
22497  #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
22498  #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
22499  #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
22500  #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
22501 /* =========================================================  SVST  ========================================================== */
22502  #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
22503  #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
22504  #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
22505  #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
22506  #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
22507  #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
22508  #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
22509  #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
22510  #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
22511  #define R_I3C0_SVST_SVAFn_Msk          (0x70000UL)    /*!< SVAFn (Bitfield-Mask: 0x07)                           */
22512 /* =========================================================  WUST  ========================================================== */
22513  #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
22514  #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
22515 /* ========================================================  MRCCPT  ========================================================= */
22516  #define R_I3C0_MRCCPT_MRCCPT_Pos       (0UL)          /*!< MRCCPT (Bit 0)                                        */
22517  #define R_I3C0_MRCCPT_MRCCPT_Msk       (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff)                    */
22518 /* ========================================================  DATBAS0  ======================================================== */
22519  #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22520  #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22521  #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22522  #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22523  #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22524  #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22525  #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22526  #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22527  #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22528  #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22529  #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22530  #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22531  #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22532  #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22533  #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22534  #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22535 /* ========================================================  DATBAS1  ======================================================== */
22536  #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22537  #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22538  #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22539  #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22540  #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22541  #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22542  #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22543  #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22544  #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22545  #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22546  #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22547  #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22548  #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22549  #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22550  #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22551  #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22552 /* ========================================================  DATBAS2  ======================================================== */
22553  #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22554  #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22555  #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22556  #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22557  #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22558  #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22559  #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22560  #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22561  #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22562  #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22563  #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22564  #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22565  #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22566  #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22567  #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22568  #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22569 /* ========================================================  DATBAS3  ======================================================== */
22570  #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22571  #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22572  #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22573  #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22574  #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22575  #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22576  #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22577  #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22578  #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22579  #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22580  #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22581  #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22582  #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22583  #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22584  #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22585  #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22586 /* ========================================================  DATBAS4  ======================================================== */
22587  #define R_I3C0_DATBAS4_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22588  #define R_I3C0_DATBAS4_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22589  #define R_I3C0_DATBAS4_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22590  #define R_I3C0_DATBAS4_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22591  #define R_I3C0_DATBAS4_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22592  #define R_I3C0_DATBAS4_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22593  #define R_I3C0_DATBAS4_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22594  #define R_I3C0_DATBAS4_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22595  #define R_I3C0_DATBAS4_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22596  #define R_I3C0_DATBAS4_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22597  #define R_I3C0_DATBAS4_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22598  #define R_I3C0_DATBAS4_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22599  #define R_I3C0_DATBAS4_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22600  #define R_I3C0_DATBAS4_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22601  #define R_I3C0_DATBAS4_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22602  #define R_I3C0_DATBAS4_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22603 /* ========================================================  DATBAS5  ======================================================== */
22604  #define R_I3C0_DATBAS5_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22605  #define R_I3C0_DATBAS5_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22606  #define R_I3C0_DATBAS5_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22607  #define R_I3C0_DATBAS5_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22608  #define R_I3C0_DATBAS5_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22609  #define R_I3C0_DATBAS5_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22610  #define R_I3C0_DATBAS5_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22611  #define R_I3C0_DATBAS5_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22612  #define R_I3C0_DATBAS5_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22613  #define R_I3C0_DATBAS5_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22614  #define R_I3C0_DATBAS5_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22615  #define R_I3C0_DATBAS5_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22616  #define R_I3C0_DATBAS5_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22617  #define R_I3C0_DATBAS5_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22618  #define R_I3C0_DATBAS5_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22619  #define R_I3C0_DATBAS5_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22620 /* ========================================================  DATBAS6  ======================================================== */
22621  #define R_I3C0_DATBAS6_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22622  #define R_I3C0_DATBAS6_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22623  #define R_I3C0_DATBAS6_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22624  #define R_I3C0_DATBAS6_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22625  #define R_I3C0_DATBAS6_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22626  #define R_I3C0_DATBAS6_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22627  #define R_I3C0_DATBAS6_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22628  #define R_I3C0_DATBAS6_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22629  #define R_I3C0_DATBAS6_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22630  #define R_I3C0_DATBAS6_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22631  #define R_I3C0_DATBAS6_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22632  #define R_I3C0_DATBAS6_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22633  #define R_I3C0_DATBAS6_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22634  #define R_I3C0_DATBAS6_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22635  #define R_I3C0_DATBAS6_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22636  #define R_I3C0_DATBAS6_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22637 /* ========================================================  DATBAS7  ======================================================== */
22638  #define R_I3C0_DATBAS7_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
22639  #define R_I3C0_DATBAS7_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
22640  #define R_I3C0_DATBAS7_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
22641  #define R_I3C0_DATBAS7_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
22642  #define R_I3C0_DATBAS7_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
22643  #define R_I3C0_DATBAS7_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
22644  #define R_I3C0_DATBAS7_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
22645  #define R_I3C0_DATBAS7_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
22646  #define R_I3C0_DATBAS7_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
22647  #define R_I3C0_DATBAS7_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
22648  #define R_I3C0_DATBAS7_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
22649  #define R_I3C0_DATBAS7_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
22650  #define R_I3C0_DATBAS7_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
22651  #define R_I3C0_DATBAS7_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
22652  #define R_I3C0_DATBAS7_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
22653  #define R_I3C0_DATBAS7_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
22654 /* =======================================================  EXDATBAS  ======================================================== */
22655  #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
22656  #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
22657  #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
22658  #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
22659  #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
22660  #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
22661  #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
22662  #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
22663 /* =======================================================  SDATBAS0  ======================================================== */
22664  #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
22665  #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
22666  #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
22667  #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
22668  #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
22669  #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
22670  #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
22671  #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
22672 /* =======================================================  SDATBAS1  ======================================================== */
22673  #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
22674  #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
22675  #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
22676  #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
22677  #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
22678  #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
22679  #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
22680  #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
22681 /* =======================================================  SDATBAS2  ======================================================== */
22682  #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
22683  #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
22684  #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
22685  #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
22686  #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
22687  #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
22688  #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
22689  #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
22690 /* ========================================================  MSDCT0  ========================================================= */
22691  #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22692  #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22693  #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22694  #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22695  #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22696  #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22697  #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22698  #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22699  #define R_I3C0_MSDCT0_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22700  #define R_I3C0_MSDCT0_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22701  #define R_I3C0_MSDCT0_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22702  #define R_I3C0_MSDCT0_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22703  #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22704  #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22705 /* ========================================================  MSDCT1  ========================================================= */
22706  #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22707  #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22708  #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22709  #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22710  #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22711  #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22712  #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22713  #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22714  #define R_I3C0_MSDCT1_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22715  #define R_I3C0_MSDCT1_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22716  #define R_I3C0_MSDCT1_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22717  #define R_I3C0_MSDCT1_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22718  #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22719  #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22720 /* ========================================================  MSDCT2  ========================================================= */
22721  #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22722  #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22723  #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22724  #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22725  #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22726  #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22727  #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22728  #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22729  #define R_I3C0_MSDCT2_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22730  #define R_I3C0_MSDCT2_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22731  #define R_I3C0_MSDCT2_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22732  #define R_I3C0_MSDCT2_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22733  #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22734  #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22735 /* ========================================================  MSDCT3  ========================================================= */
22736  #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22737  #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22738  #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22739  #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22740  #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22741  #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22742  #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22743  #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22744  #define R_I3C0_MSDCT3_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22745  #define R_I3C0_MSDCT3_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22746  #define R_I3C0_MSDCT3_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22747  #define R_I3C0_MSDCT3_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22748  #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22749  #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22750 /* ========================================================  MSDCT4  ========================================================= */
22751  #define R_I3C0_MSDCT4_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22752  #define R_I3C0_MSDCT4_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22753  #define R_I3C0_MSDCT4_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22754  #define R_I3C0_MSDCT4_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22755  #define R_I3C0_MSDCT4_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22756  #define R_I3C0_MSDCT4_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22757  #define R_I3C0_MSDCT4_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22758  #define R_I3C0_MSDCT4_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22759  #define R_I3C0_MSDCT4_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22760  #define R_I3C0_MSDCT4_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22761  #define R_I3C0_MSDCT4_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22762  #define R_I3C0_MSDCT4_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22763  #define R_I3C0_MSDCT4_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22764  #define R_I3C0_MSDCT4_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22765 /* ========================================================  MSDCT5  ========================================================= */
22766  #define R_I3C0_MSDCT5_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22767  #define R_I3C0_MSDCT5_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22768  #define R_I3C0_MSDCT5_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22769  #define R_I3C0_MSDCT5_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22770  #define R_I3C0_MSDCT5_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22771  #define R_I3C0_MSDCT5_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22772  #define R_I3C0_MSDCT5_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22773  #define R_I3C0_MSDCT5_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22774  #define R_I3C0_MSDCT5_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22775  #define R_I3C0_MSDCT5_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22776  #define R_I3C0_MSDCT5_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22777  #define R_I3C0_MSDCT5_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22778  #define R_I3C0_MSDCT5_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22779  #define R_I3C0_MSDCT5_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22780 /* ========================================================  MSDCT6  ========================================================= */
22781  #define R_I3C0_MSDCT6_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22782  #define R_I3C0_MSDCT6_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22783  #define R_I3C0_MSDCT6_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22784  #define R_I3C0_MSDCT6_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22785  #define R_I3C0_MSDCT6_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22786  #define R_I3C0_MSDCT6_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22787  #define R_I3C0_MSDCT6_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22788  #define R_I3C0_MSDCT6_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22789  #define R_I3C0_MSDCT6_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22790  #define R_I3C0_MSDCT6_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22791  #define R_I3C0_MSDCT6_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22792  #define R_I3C0_MSDCT6_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22793  #define R_I3C0_MSDCT6_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22794  #define R_I3C0_MSDCT6_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22795 /* ========================================================  MSDCT7  ========================================================= */
22796  #define R_I3C0_MSDCT7_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
22797  #define R_I3C0_MSDCT7_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
22798  #define R_I3C0_MSDCT7_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
22799  #define R_I3C0_MSDCT7_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
22800  #define R_I3C0_MSDCT7_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
22801  #define R_I3C0_MSDCT7_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
22802  #define R_I3C0_MSDCT7_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
22803  #define R_I3C0_MSDCT7_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
22804  #define R_I3C0_MSDCT7_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
22805  #define R_I3C0_MSDCT7_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
22806  #define R_I3C0_MSDCT7_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
22807  #define R_I3C0_MSDCT7_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
22808  #define R_I3C0_MSDCT7_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
22809  #define R_I3C0_MSDCT7_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
22810 /* =========================================================  SVDCT  ========================================================= */
22811  #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
22812  #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
22813  #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
22814  #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
22815  #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
22816  #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
22817  #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
22818  #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
22819  #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
22820  #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
22821  #define R_I3C0_SVDCT_TBCR4_Pos         (12UL)         /*!< TBCR4 (Bit 12)                                        */
22822  #define R_I3C0_SVDCT_TBCR4_Msk         (0x1000UL)     /*!< TBCR4 (Bitfield-Mask: 0x01)                           */
22823  #define R_I3C0_SVDCT_TBCR5_Pos         (13UL)         /*!< TBCR5 (Bit 13)                                        */
22824  #define R_I3C0_SVDCT_TBCR5_Msk         (0x2000UL)     /*!< TBCR5 (Bitfield-Mask: 0x01)                           */
22825  #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
22826  #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
22827 /* =======================================================  SDCTPIDL  ======================================================== */
22828 /* =======================================================  SDCTPIDH  ======================================================== */
22829 /* ========================================================  SVDVAD0  ======================================================== */
22830  #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
22831  #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
22832  #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
22833  #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
22834  #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
22835  #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
22836  #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
22837  #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
22838 /* ========================================================  SVDVAD1  ======================================================== */
22839  #define R_I3C0_SVDVAD1_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
22840  #define R_I3C0_SVDVAD1_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
22841  #define R_I3C0_SVDVAD1_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
22842  #define R_I3C0_SVDVAD1_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
22843  #define R_I3C0_SVDVAD1_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
22844  #define R_I3C0_SVDVAD1_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
22845  #define R_I3C0_SVDVAD1_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
22846  #define R_I3C0_SVDVAD1_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
22847 /* ========================================================  SVDVAD2  ======================================================== */
22848  #define R_I3C0_SVDVAD2_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
22849  #define R_I3C0_SVDVAD2_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
22850  #define R_I3C0_SVDVAD2_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
22851  #define R_I3C0_SVDVAD2_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
22852  #define R_I3C0_SVDVAD2_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
22853  #define R_I3C0_SVDVAD2_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
22854  #define R_I3C0_SVDVAD2_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
22855  #define R_I3C0_SVDVAD2_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
22856 /* ========================================================  CSECMD  ========================================================= */
22857  #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
22858  #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
22859  #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
22860  #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
22861  #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
22862  #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
22863 /* ========================================================  CEACTST  ======================================================== */
22864  #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
22865  #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
22866 /* =========================================================  CMWLG  ========================================================= */
22867  #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
22868  #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
22869 /* =========================================================  CMRLG  ========================================================= */
22870  #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
22871  #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
22872  #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
22873  #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
22874 /* ========================================================  CETSTMD  ======================================================== */
22875  #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
22876  #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
22877 /* ========================================================  CGDVST  ========================================================= */
22878  #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
22879  #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
22880  #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
22881  #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
22882  #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
22883  #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
22884  #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
22885  #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
22886 /* ========================================================  CMDSPW  ========================================================= */
22887  #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
22888  #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
22889 /* ========================================================  CMDSPR  ========================================================= */
22890  #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
22891  #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
22892  #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
22893  #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
22894 /* ========================================================  CMDSPT  ========================================================= */
22895  #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
22896  #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
22897  #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
22898  #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
22899 /* =========================================================  CETSM  ========================================================= */
22900  #define R_I3C0_CETSM_SPTSYN_Pos        (0UL)          /*!< SPTSYN (Bit 0)                                        */
22901  #define R_I3C0_CETSM_SPTSYN_Msk        (0x1UL)        /*!< SPTSYN (Bitfield-Mask: 0x01)                          */
22902  #define R_I3C0_CETSM_SPTASYN0_Pos      (1UL)          /*!< SPTASYN0 (Bit 1)                                      */
22903  #define R_I3C0_CETSM_SPTASYN0_Msk      (0x2UL)        /*!< SPTASYN0 (Bitfield-Mask: 0x01)                        */
22904  #define R_I3C0_CETSM_SPTASYN1_Pos      (2UL)          /*!< SPTASYN1 (Bit 2)                                      */
22905  #define R_I3C0_CETSM_SPTASYN1_Msk      (0x4UL)        /*!< SPTASYN1 (Bitfield-Mask: 0x01)                        */
22906  #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
22907  #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
22908  #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
22909  #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
22910 /* =========================================================  CETSS  ========================================================= */
22911  #define R_I3C0_CETSS_SYNE_Pos          (0UL)          /*!< SYNE (Bit 0)                                          */
22912  #define R_I3C0_CETSS_SYNE_Msk          (0x1UL)        /*!< SYNE (Bitfield-Mask: 0x01)                            */
22913  #define R_I3C0_CETSS_ASYNE_Pos         (1UL)          /*!< ASYNE (Bit 1)                                         */
22914  #define R_I3C0_CETSS_ASYNE_Msk         (0x6UL)        /*!< ASYNE (Bitfield-Mask: 0x03)                           */
22915  #define R_I3C0_CETSS_ICOVF_Pos         (7UL)          /*!< ICOVF (Bit 7)                                         */
22916  #define R_I3C0_CETSS_ICOVF_Msk         (0x80UL)       /*!< ICOVF (Bitfield-Mask: 0x01)                           */
22917 /* =======================================================  CGHDRCAP  ======================================================== */
22918  #define R_I3C0_CGHDRCAP_DDREN_Pos      (0UL)          /*!< DDREN (Bit 0)                                         */
22919  #define R_I3C0_CGHDRCAP_DDREN_Msk      (0x1UL)        /*!< DDREN (Bitfield-Mask: 0x01)                           */
22920  #define R_I3C0_CGHDRCAP_TSPEN_Pos      (1UL)          /*!< TSPEN (Bit 1)                                         */
22921  #define R_I3C0_CGHDRCAP_TSPEN_Msk      (0x2UL)        /*!< TSPEN (Bitfield-Mask: 0x01)                           */
22922  #define R_I3C0_CGHDRCAP_TSLEN_Pos      (2UL)          /*!< TSLEN (Bit 2)                                         */
22923  #define R_I3C0_CGHDRCAP_TSLEN_Msk      (0x4UL)        /*!< TSLEN (Bitfield-Mask: 0x01)                           */
22924 /* ========================================================  BITCNT  ========================================================= */
22925  #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
22926  #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
22927  #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
22928  #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
22929 /* ========================================================  NQSTLV  ========================================================= */
22930  #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
22931  #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
22932  #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
22933  #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
22934  #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
22935  #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
22936  #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
22937  #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
22938 /* =======================================================  NDBSTLV0  ======================================================== */
22939  #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
22940  #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
22941  #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
22942  #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
22943 /* =======================================================  NRSQSTLV  ======================================================== */
22944  #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
22945  #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
22946 /* ========================================================  HQSTLV  ========================================================= */
22947  #define R_I3C0_HQSTLV_CMDQLV_Pos       (0UL)          /*!< CMDQLV (Bit 0)                                        */
22948  #define R_I3C0_HQSTLV_CMDQLV_Msk       (0xffUL)       /*!< CMDQLV (Bitfield-Mask: 0xff)                          */
22949  #define R_I3C0_HQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
22950  #define R_I3C0_HQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
22951 /* ========================================================  HDBSTLV  ======================================================== */
22952  #define R_I3C0_HDBSTLV_TDBFLV_Pos      (0UL)          /*!< TDBFLV (Bit 0)                                        */
22953  #define R_I3C0_HDBSTLV_TDBFLV_Msk      (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
22954  #define R_I3C0_HDBSTLV_RDBLV_Pos       (8UL)          /*!< RDBLV (Bit 8)                                         */
22955  #define R_I3C0_HDBSTLV_RDBLV_Msk       (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
22956 /* ========================================================  PRSTDBG  ======================================================== */
22957  #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
22958  #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
22959  #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
22960  #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
22961  #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
22962  #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
22963  #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
22964  #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
22965 /* =======================================================  MSERRCNT  ======================================================== */
22966  #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
22967  #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
22968 /* ========================================================  SC1CPT  ========================================================= */
22969  #define R_I3C0_SC1CPT_SC1C_Pos         (0UL)          /*!< SC1C (Bit 0)                                          */
22970  #define R_I3C0_SC1CPT_SC1C_Msk         (0xffffUL)     /*!< SC1C (Bitfield-Mask: 0xffff)                          */
22971 /* ========================================================  SC2CPT  ========================================================= */
22972  #define R_I3C0_SC2CPT_SC2C_Pos         (0UL)          /*!< SC2C (Bit 0)                                          */
22973  #define R_I3C0_SC2CPT_SC2C_Msk         (0xffffUL)     /*!< SC2C (Bitfield-Mask: 0xffff)                          */
22974 
22975 /* =========================================================================================================================== */
22976 /* ================                                        R_MPU_MMPU                                         ================ */
22977 /* =========================================================================================================================== */
22978 
22979 /* ==========================================================  OAD  ========================================================== */
22980  #define R_MPU_MMPU_OAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
22981  #define R_MPU_MMPU_OAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
22982  #define R_MPU_MMPU_OAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
22983  #define R_MPU_MMPU_OAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
22984 /* =========================================================  OADPT  ========================================================= */
22985  #define R_MPU_MMPU_OADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
22986  #define R_MPU_MMPU_OADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
22987  #define R_MPU_MMPU_OADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
22988  #define R_MPU_MMPU_OADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
22989 
22990 /* =========================================================================================================================== */
22991 /* ================                                        R_MPU_SPMON                                        ================ */
22992 /* =========================================================================================================================== */
22993 
22994 /* =========================================================================================================================== */
22995 /* ================                                          R_MSTP                                           ================ */
22996 /* =========================================================================================================================== */
22997 
22998 /* ========================================================  MSTPCRA  ======================================================== */
22999  #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
23000  #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
23001 /* ========================================================  MSTPCRB  ======================================================== */
23002  #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
23003  #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
23004 /* ========================================================  MSTPCRC  ======================================================== */
23005  #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
23006  #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
23007 /* ========================================================  MSTPCRD  ======================================================== */
23008  #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
23009  #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
23010 /* ========================================================  MSTPCRE  ======================================================== */
23011  #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
23012  #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
23013 /* =======================================================  LSMRWDIS  ======================================================== */
23014  #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
23015  #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
23016  #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
23017  #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
23018  #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
23019  #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
23020  #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
23021  #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
23022  #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
23023  #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
23024 
23025 /* =========================================================================================================================== */
23026 /* ================                                          R_PORT0                                          ================ */
23027 /* =========================================================================================================================== */
23028 
23029 /* ========================================================  PCNTR1  ========================================================= */
23030  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
23031  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
23032  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
23033  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
23034 /* =========================================================  PODR  ========================================================== */
23035  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
23036  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
23037 /* ==========================================================  PDR  ========================================================== */
23038  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
23039  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
23040 /* ========================================================  PCNTR2  ========================================================= */
23041  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
23042  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
23043  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
23044  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
23045 /* =========================================================  EIDR  ========================================================== */
23046  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
23047  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
23048 /* =========================================================  PIDR  ========================================================== */
23049  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
23050  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
23051 /* ========================================================  PCNTR3  ========================================================= */
23052  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
23053  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
23054  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
23055  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
23056 /* =========================================================  PORR  ========================================================== */
23057  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
23058  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
23059 /* =========================================================  POSR  ========================================================== */
23060  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
23061  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
23062 /* ========================================================  PCNTR4  ========================================================= */
23063  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
23064  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
23065  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
23066  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
23067 /* =========================================================  EORR  ========================================================== */
23068  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
23069  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
23070 /* =========================================================  EOSR  ========================================================== */
23071  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
23072  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
23073 
23074 /* =========================================================================================================================== */
23075 /* ================                                           R_PFS                                           ================ */
23076 /* =========================================================================================================================== */
23077 
23078 /* =========================================================================================================================== */
23079 /* ================                                          R_PMISC                                          ================ */
23080 /* =========================================================================================================================== */
23081 
23082 /* =========================================================  PWPR  ========================================================== */
23083  #define R_PMISC_PWPR_PFSWE_Pos      (6UL)    /*!< PFSWE (Bit 6)                                         */
23084  #define R_PMISC_PWPR_PFSWE_Msk      (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
23085  #define R_PMISC_PWPR_B0WI_Pos       (7UL)    /*!< B0WI (Bit 7)                                          */
23086  #define R_PMISC_PWPR_B0WI_Msk       (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
23087 /* =========================================================  PWPRS  ========================================================= */
23088  #define R_PMISC_PWPRS_PFSWE_Pos     (6UL)    /*!< PFSWE (Bit 6)                                         */
23089  #define R_PMISC_PWPRS_PFSWE_Msk     (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
23090  #define R_PMISC_PWPRS_B0WI_Pos      (7UL)    /*!< B0WI (Bit 7)                                          */
23091  #define R_PMISC_PWPRS_B0WI_Msk      (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
23092 /* ========================================================  PRWCNTR  ======================================================== */
23093  #define R_PMISC_PRWCNTR_WAIT_Pos    (0UL)    /*!< WAIT (Bit 0)                                          */
23094  #define R_PMISC_PRWCNTR_WAIT_Msk    (0xfUL)  /*!< WAIT (Bitfield-Mask: 0x0f)                            */
23095 /* =========================================================  PSAR  ========================================================== */
23096  #define R_PMISC_PSAR_PORTSA0_Pos    (0UL)    /*!< PORTSA0 (Bit 0)                                       */
23097  #define R_PMISC_PSAR_PORTSA0_Msk    (0x1UL)  /*!< PORTSA0 (Bitfield-Mask: 0x01)                         */
23098 
23099 /* =========================================================================================================================== */
23100 /* ================                                          R_QSPI                                           ================ */
23101 /* =========================================================================================================================== */
23102 
23103 /* ========================================================  SFMSMD  ========================================================= */
23104  #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
23105  #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
23106  #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
23107  #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
23108  #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
23109  #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
23110  #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
23111  #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
23112  #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
23113  #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
23114  #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
23115  #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
23116  #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
23117  #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
23118  #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
23119  #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
23120  #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
23121  #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
23122 /* ========================================================  SFMSSC  ========================================================= */
23123  #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
23124  #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
23125  #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
23126  #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
23127  #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
23128  #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
23129 /* ========================================================  SFMSKC  ========================================================= */
23130  #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
23131  #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
23132  #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
23133  #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
23134 /* ========================================================  SFMSST  ========================================================= */
23135  #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
23136  #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
23137  #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
23138  #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
23139  #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
23140  #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
23141 /* ========================================================  SFMCOM  ========================================================= */
23142  #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
23143  #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
23144 /* ========================================================  SFMCMD  ========================================================= */
23145  #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
23146  #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
23147 /* ========================================================  SFMCST  ========================================================= */
23148  #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
23149  #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
23150  #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
23151  #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
23152 /* ========================================================  SFMSIC  ========================================================= */
23153  #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
23154  #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
23155 /* ========================================================  SFMSAC  ========================================================= */
23156  #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
23157  #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
23158  #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
23159  #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
23160 /* ========================================================  SFMSDC  ========================================================= */
23161  #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
23162  #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
23163  #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
23164  #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
23165  #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
23166  #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
23167  #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
23168  #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
23169 /* ========================================================  SFMSPC  ========================================================= */
23170  #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
23171  #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
23172  #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
23173  #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
23174 /* ========================================================  SFMPMD  ========================================================= */
23175  #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
23176  #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
23177 /* ========================================================  SFMCNT1  ======================================================== */
23178  #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
23179  #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */
23180 
23181 /* =========================================================================================================================== */
23182 /* ================                                           R_RTC                                           ================ */
23183 /* =========================================================================================================================== */
23184 
23185 /* ========================================================  R64CNT  ========================================================= */
23186  #define R_RTC_R64CNT_R64OVF_Pos      (7UL)      /*!< R64OVF (Bit 7)                                        */
23187  #define R_RTC_R64CNT_R64OVF_Msk      (0x80UL)   /*!< R64OVF (Bitfield-Mask: 0x01)                          */
23188  #define R_RTC_R64CNT_FHZ_Pos         (0UL)      /*!< FHZ (Bit 0)                                           */
23189  #define R_RTC_R64CNT_FHZ_Msk         (0x1UL)    /*!< FHZ (Bitfield-Mask: 0x01)                             */
23190 /* =========================================================  BCNT0  ========================================================= */
23191  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
23192  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
23193 /* ========================================================  RSECCNT  ======================================================== */
23194  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
23195  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
23196  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
23197  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
23198 /* =========================================================  BCNT1  ========================================================= */
23199  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
23200  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
23201 /* ========================================================  RMINCNT  ======================================================== */
23202  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
23203  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
23204  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
23205  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
23206 /* =========================================================  BCNT2  ========================================================= */
23207  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
23208  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
23209 /* ========================================================  RHRCNT  ========================================================= */
23210  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
23211  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
23212  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
23213  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
23214  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
23215  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
23216 /* =========================================================  BCNT3  ========================================================= */
23217  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
23218  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
23219 /* ========================================================  RWKCNT  ========================================================= */
23220  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
23221  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
23222 /* ========================================================  RDAYCNT  ======================================================== */
23223  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
23224  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
23225  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
23226  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
23227 /* ========================================================  RMONCNT  ======================================================== */
23228  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
23229  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
23230  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
23231  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
23232 /* ========================================================  RYRCNT  ========================================================= */
23233  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
23234  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
23235  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
23236  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
23237 /* ========================================================  BCNT0AR  ======================================================== */
23238  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
23239  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
23240 /* ========================================================  RSECAR  ========================================================= */
23241  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
23242  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23243  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
23244  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
23245  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
23246  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
23247 /* ========================================================  BCNT1AR  ======================================================== */
23248  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
23249  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
23250 /* ========================================================  RMINAR  ========================================================= */
23251  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
23252  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23253  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
23254  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
23255  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
23256  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
23257 /* ========================================================  BCNT2AR  ======================================================== */
23258  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
23259  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
23260 /* =========================================================  RHRAR  ========================================================= */
23261  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
23262  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23263  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
23264  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
23265  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
23266  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
23267  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
23268  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
23269 /* ========================================================  BCNT3AR  ======================================================== */
23270  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
23271  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
23272 /* =========================================================  RWKAR  ========================================================= */
23273  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
23274  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23275  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
23276  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
23277 /* =======================================================  BCNT0AER  ======================================================== */
23278  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
23279  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
23280 /* ========================================================  RDAYAR  ========================================================= */
23281  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
23282  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23283  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
23284  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
23285  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
23286  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
23287 /* =======================================================  BCNT1AER  ======================================================== */
23288  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
23289  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
23290 /* ========================================================  RMONAR  ========================================================= */
23291  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
23292  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23293  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
23294  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
23295  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
23296  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
23297 /* =======================================================  BCNT2AER  ======================================================== */
23298  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
23299  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
23300 /* =========================================================  RYRAR  ========================================================= */
23301  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
23302  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
23303  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
23304  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
23305 /* =======================================================  BCNT3AER  ======================================================== */
23306  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
23307  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
23308 /* ========================================================  RYRAREN  ======================================================== */
23309  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
23310  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
23311 /* =========================================================  RCR1  ========================================================== */
23312  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
23313  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
23314  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
23315  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
23316  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
23317  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
23318  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
23319  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
23320  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
23321  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
23322 /* =========================================================  RCR2  ========================================================== */
23323  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
23324  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
23325  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
23326  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
23327  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
23328  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
23329  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
23330  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
23331  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
23332  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
23333  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
23334  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
23335  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
23336  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
23337  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
23338  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
23339 /* =========================================================  RCR4  ========================================================== */
23340  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
23341  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
23342  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
23343  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
23344 /* =========================================================  RFRH  ========================================================== */
23345  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
23346  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
23347 /* =========================================================  RFRL  ========================================================== */
23348  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
23349  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
23350 /* =========================================================  RADJ  ========================================================== */
23351  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
23352  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
23353  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
23354  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
23355 /* =========================================================  RADJ2  ========================================================= */
23356  #define R_RTC_RADJ2_FADJ_Pos         (5UL)      /*!< FADJ (Bit 5)                                          */
23357  #define R_RTC_RADJ2_FADJ_Msk         (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff)                           */
23358 
23359 /* =========================================================================================================================== */
23360 /* ================                                          R_SCI0                                           ================ */
23361 /* =========================================================================================================================== */
23362 
23363 /* ==========================================================  SMR  ========================================================== */
23364  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
23365  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
23366  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
23367  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
23368  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
23369  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
23370  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
23371  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
23372  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
23373  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
23374  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
23375  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
23376  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
23377  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
23378 /* =======================================================  SMR_SMCI  ======================================================== */
23379  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
23380  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
23381  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
23382  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
23383  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
23384  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
23385  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
23386  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
23387  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
23388  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
23389  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
23390  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
23391 /* ==========================================================  BRR  ========================================================== */
23392  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
23393  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
23394 /* ==========================================================  SCR  ========================================================== */
23395  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
23396  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
23397  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
23398  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
23399  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
23400  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
23401  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
23402  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
23403  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
23404  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
23405  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
23406  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
23407  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
23408  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
23409 /* =======================================================  SCR_SMCI  ======================================================== */
23410  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
23411  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
23412  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
23413  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
23414  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
23415  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
23416  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
23417  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
23418  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
23419  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
23420  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
23421  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
23422  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
23423  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
23424 /* ==========================================================  TDR  ========================================================== */
23425  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
23426  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
23427 /* ==========================================================  SSR  ========================================================== */
23428  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
23429  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
23430  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
23431  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
23432  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
23433  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
23434  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
23435  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
23436  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
23437  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
23438  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
23439  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
23440  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
23441  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
23442  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
23443  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
23444 /* =======================================================  SSR_FIFO  ======================================================== */
23445  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
23446  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
23447  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
23448  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
23449  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
23450  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
23451  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
23452  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
23453  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
23454  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
23455  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
23456  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
23457  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
23458  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
23459 /* =======================================================  SSR_MANC  ======================================================== */
23460  #define R_SCI0_SSR_MANC_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
23461  #define R_SCI0_SSR_MANC_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
23462  #define R_SCI0_SSR_MANC_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
23463  #define R_SCI0_SSR_MANC_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
23464  #define R_SCI0_SSR_MANC_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
23465  #define R_SCI0_SSR_MANC_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
23466  #define R_SCI0_SSR_MANC_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
23467  #define R_SCI0_SSR_MANC_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
23468  #define R_SCI0_SSR_MANC_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
23469  #define R_SCI0_SSR_MANC_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
23470  #define R_SCI0_SSR_MANC_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
23471  #define R_SCI0_SSR_MANC_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
23472  #define R_SCI0_SSR_MANC_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
23473  #define R_SCI0_SSR_MANC_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
23474  #define R_SCI0_SSR_MANC_MER_Pos        (0UL)      /*!< MER (Bit 0)                                           */
23475  #define R_SCI0_SSR_MANC_MER_Msk        (0x1UL)    /*!< MER (Bitfield-Mask: 0x01)                             */
23476 /* =======================================================  SSR_SMCI  ======================================================== */
23477  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
23478  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
23479  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
23480  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
23481  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
23482  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
23483  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
23484  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
23485  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
23486  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
23487  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
23488  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
23489  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
23490  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
23491  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
23492  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
23493 /* ==========================================================  RDR  ========================================================== */
23494  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
23495  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
23496 /* =========================================================  SCMR  ========================================================== */
23497  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
23498  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
23499  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
23500  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
23501  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
23502  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
23503  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
23504  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
23505  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
23506  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
23507 /* =========================================================  SEMR  ========================================================== */
23508  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
23509  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
23510  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
23511  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
23512  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
23513  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
23514  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
23515  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
23516  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
23517  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
23518  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
23519  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
23520  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
23521  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
23522  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
23523  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
23524 /* =========================================================  SNFR  ========================================================== */
23525  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
23526  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
23527 /* =========================================================  SIMR1  ========================================================= */
23528  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
23529  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
23530  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
23531  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
23532 /* =========================================================  SIMR2  ========================================================= */
23533  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
23534  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
23535  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
23536  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
23537  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
23538  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
23539 /* =========================================================  SIMR3  ========================================================= */
23540  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
23541  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
23542  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
23543  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
23544  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
23545  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
23546  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
23547  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
23548  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
23549  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
23550  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
23551  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
23552 /* =========================================================  SISR  ========================================================== */
23553  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
23554  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
23555 /* =========================================================  SPMR  ========================================================== */
23556  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
23557  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
23558  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
23559  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
23560  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
23561  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
23562  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
23563  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
23564  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
23565  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
23566  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
23567  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
23568  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
23569  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
23570 /* =========================================================  TDRHL  ========================================================= */
23571  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
23572  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
23573 /* ========================================================  FTDRHL  ========================================================= */
23574  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
23575  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
23576  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
23577  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
23578 /* =========================================================  FTDRH  ========================================================= */
23579  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
23580  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
23581  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
23582  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
23583 /* =========================================================  FTDRL  ========================================================= */
23584  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
23585  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
23586 /* =========================================================  RDRHL  ========================================================= */
23587  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
23588  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
23589 /* ========================================================  FRDRHL  ========================================================= */
23590  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
23591  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
23592  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
23593  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
23594  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
23595  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
23596  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
23597  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
23598  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
23599  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
23600  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
23601  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
23602  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
23603  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
23604 /* =======================================================  TDRHL_MAN  ======================================================= */
23605  #define R_SCI0_TDRHL_MAN_TDAT_Pos      (0UL)      /*!< TDAT (Bit 0)                                          */
23606  #define R_SCI0_TDRHL_MAN_TDAT_Msk      (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
23607  #define R_SCI0_TDRHL_MAN_MPBT_Pos      (9UL)      /*!< MPBT (Bit 9)                                          */
23608  #define R_SCI0_TDRHL_MAN_MPBT_Msk      (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
23609  #define R_SCI0_TDRHL_MAN_TSYNC_Pos     (12UL)     /*!< TSYNC (Bit 12)                                        */
23610  #define R_SCI0_TDRHL_MAN_TSYNC_Msk     (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01)                           */
23611 /* =======================================================  RDRHL_MAN  ======================================================= */
23612  #define R_SCI0_RDRHL_MAN_RDAT_Pos      (0UL)      /*!< RDAT (Bit 0)                                          */
23613  #define R_SCI0_RDRHL_MAN_RDAT_Msk      (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
23614  #define R_SCI0_RDRHL_MAN_MPB_Pos       (9UL)      /*!< MPB (Bit 9)                                           */
23615  #define R_SCI0_RDRHL_MAN_MPB_Msk       (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
23616  #define R_SCI0_RDRHL_MAN_RSYNC_Pos     (12UL)     /*!< RSYNC (Bit 12)                                        */
23617  #define R_SCI0_RDRHL_MAN_RSYNC_Msk     (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01)                           */
23618 /* =========================================================  FRDRH  ========================================================= */
23619  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
23620  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
23621  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
23622  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
23623  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
23624  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
23625  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
23626  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
23627  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
23628  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
23629  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
23630  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
23631  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
23632  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
23633 /* =========================================================  FRDRL  ========================================================= */
23634  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
23635  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
23636 /* =========================================================  MDDR  ========================================================== */
23637  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
23638  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
23639 /* =========================================================  DCCR  ========================================================== */
23640  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
23641  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
23642  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
23643  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
23644  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
23645  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
23646  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
23647  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
23648  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
23649  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
23650 /* ==========================================================  FCR  ========================================================== */
23651  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
23652  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
23653  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
23654  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
23655  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
23656  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
23657  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
23658  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
23659  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
23660  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
23661  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
23662  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
23663  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
23664  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
23665 /* ==========================================================  FDR  ========================================================== */
23666  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
23667  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
23668  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
23669  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
23670 /* ==========================================================  LSR  ========================================================== */
23671  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
23672  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
23673  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
23674  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
23675  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
23676  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
23677 /* ==========================================================  CDR  ========================================================== */
23678  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
23679  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
23680 /* =========================================================  SPTR  ========================================================== */
23681  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
23682  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
23683  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
23684  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
23685  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
23686  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
23687  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
23688  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
23689  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
23690  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
23691  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
23692  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
23693  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
23694  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
23695 /* =========================================================  ACTR  ========================================================== */
23696  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
23697  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
23698  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
23699  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
23700  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
23701  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
23702  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
23703  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
23704 /* =========================================================  ESMER  ========================================================= */
23705  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
23706  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
23707 /* ==========================================================  CR0  ========================================================== */
23708  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
23709  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
23710  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
23711  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
23712  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
23713  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
23714 /* ==========================================================  CR1  ========================================================== */
23715  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
23716  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
23717  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
23718  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
23719  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
23720  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
23721  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
23722  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
23723  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
23724  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
23725 /* ==========================================================  CR2  ========================================================== */
23726  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
23727  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
23728  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
23729  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
23730  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
23731  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
23732 /* ==========================================================  CR3  ========================================================== */
23733  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
23734  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
23735 /* ==========================================================  PCR  ========================================================== */
23736  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
23737  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
23738  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
23739  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
23740  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
23741  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
23742 /* ==========================================================  ICR  ========================================================== */
23743  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
23744  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
23745  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
23746  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
23747  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
23748  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
23749  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
23750  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
23751  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
23752  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
23753  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
23754  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
23755 /* ==========================================================  STR  ========================================================== */
23756  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
23757  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
23758  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
23759  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
23760  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
23761  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
23762  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
23763  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
23764  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
23765  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
23766  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
23767  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
23768 /* =========================================================  STCR  ========================================================== */
23769  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
23770  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
23771  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
23772  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
23773  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
23774  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
23775  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
23776  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
23777  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
23778  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
23779  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
23780  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
23781 /* =========================================================  CF0DR  ========================================================= */
23782 /* =========================================================  CF0CR  ========================================================= */
23783  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
23784  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
23785  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
23786  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
23787  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
23788  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
23789  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
23790  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
23791  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
23792  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
23793  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
23794  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
23795  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
23796  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
23797  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
23798  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
23799 /* =========================================================  CF0RR  ========================================================= */
23800 /* ========================================================  PCF1DR  ========================================================= */
23801 /* ========================================================  SCF1DR  ========================================================= */
23802 /* =========================================================  CF1CR  ========================================================= */
23803  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
23804  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
23805  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
23806  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
23807  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
23808  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
23809  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
23810  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
23811  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
23812  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
23813  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
23814  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
23815  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
23816  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
23817  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
23818  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
23819 /* =========================================================  CF1RR  ========================================================= */
23820 /* ==========================================================  TCR  ========================================================== */
23821  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
23822  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
23823 /* ==========================================================  TMR  ========================================================== */
23824  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
23825  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
23826  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
23827  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
23828  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
23829  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
23830 /* =========================================================  TPRE  ========================================================== */
23831 /* =========================================================  TCNT  ========================================================== */
23832 /* =======================================================  SCIMSKEN  ======================================================== */
23833  #define R_SCI0_SCIMSKEN_MSKEN_Pos      (0UL)    /*!< MSKEN (Bit 0)                                         */
23834  #define R_SCI0_SCIMSKEN_MSKEN_Msk      (0x1UL)  /*!< MSKEN (Bitfield-Mask: 0x01)                           */
23835 /* ==========================================================  MMR  ========================================================== */
23836  #define R_SCI0_MMR_MANEN_Pos           (7UL)    /*!< MANEN (Bit 7)                                         */
23837  #define R_SCI0_MMR_MANEN_Msk           (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01)                           */
23838  #define R_SCI0_MMR_SBSEL_Pos           (6UL)    /*!< SBSEL (Bit 6)                                         */
23839  #define R_SCI0_MMR_SBSEL_Msk           (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01)                           */
23840  #define R_SCI0_MMR_SYNSEL_Pos          (5UL)    /*!< SYNSEL (Bit 5)                                        */
23841  #define R_SCI0_MMR_SYNSEL_Msk          (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01)                          */
23842  #define R_SCI0_MMR_SYNVAL_Pos          (4UL)    /*!< SYNVAL (Bit 4)                                        */
23843  #define R_SCI0_MMR_SYNVAL_Msk          (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01)                          */
23844  #define R_SCI0_MMR_ERTEN_Pos           (2UL)    /*!< ERTEN (Bit 2)                                         */
23845  #define R_SCI0_MMR_ERTEN_Msk           (0x4UL)  /*!< ERTEN (Bitfield-Mask: 0x01)                           */
23846  #define R_SCI0_MMR_TMPOL_Pos           (1UL)    /*!< TMPOL (Bit 1)                                         */
23847  #define R_SCI0_MMR_TMPOL_Msk           (0x2UL)  /*!< TMPOL (Bitfield-Mask: 0x01)                           */
23848  #define R_SCI0_MMR_RMPOL_Pos           (0UL)    /*!< RMPOL (Bit 0)                                         */
23849  #define R_SCI0_MMR_RMPOL_Msk           (0x1UL)  /*!< RMPOL (Bitfield-Mask: 0x01)                           */
23850 /* =========================================================  TMPR  ========================================================== */
23851  #define R_SCI0_TMPR_TPLEN_Pos          (0UL)    /*!< TPLEN (Bit 0)                                         */
23852  #define R_SCI0_TMPR_TPLEN_Msk          (0xfUL)  /*!< TPLEN (Bitfield-Mask: 0x0f)                           */
23853  #define R_SCI0_TMPR_TPPAT_Pos          (4UL)    /*!< TPPAT (Bit 4)                                         */
23854  #define R_SCI0_TMPR_TPPAT_Msk          (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03)                           */
23855 /* =========================================================  RMPR  ========================================================== */
23856  #define R_SCI0_RMPR_RPLEN_Pos          (0UL)    /*!< RPLEN (Bit 0)                                         */
23857  #define R_SCI0_RMPR_RPLEN_Msk          (0xfUL)  /*!< RPLEN (Bitfield-Mask: 0x0f)                           */
23858  #define R_SCI0_RMPR_RPPAT_Pos          (4UL)    /*!< RPPAT (Bit 4)                                         */
23859  #define R_SCI0_RMPR_RPPAT_Msk          (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03)                           */
23860 /* =========================================================  MESR  ========================================================== */
23861  #define R_SCI0_MESR_PFER_Pos           (0UL)    /*!< PFER (Bit 0)                                          */
23862  #define R_SCI0_MESR_PFER_Msk           (0x1UL)  /*!< PFER (Bitfield-Mask: 0x01)                            */
23863  #define R_SCI0_MESR_SYER_Pos           (1UL)    /*!< SYER (Bit 1)                                          */
23864  #define R_SCI0_MESR_SYER_Msk           (0x2UL)  /*!< SYER (Bitfield-Mask: 0x01)                            */
23865  #define R_SCI0_MESR_SBER_Pos           (2UL)    /*!< SBER (Bit 2)                                          */
23866  #define R_SCI0_MESR_SBER_Msk           (0x4UL)  /*!< SBER (Bitfield-Mask: 0x01)                            */
23867 /* =========================================================  MECR  ========================================================== */
23868  #define R_SCI0_MECR_PFEREN_Pos         (0UL)    /*!< PFEREN (Bit 0)                                        */
23869  #define R_SCI0_MECR_PFEREN_Msk         (0x1UL)  /*!< PFEREN (Bitfield-Mask: 0x01)                          */
23870  #define R_SCI0_MECR_SYEREN_Pos         (1UL)    /*!< SYEREN (Bit 1)                                        */
23871  #define R_SCI0_MECR_SYEREN_Msk         (0x2UL)  /*!< SYEREN (Bitfield-Mask: 0x01)                          */
23872  #define R_SCI0_MECR_SBEREN_Pos         (2UL)    /*!< SBEREN (Bit 2)                                        */
23873  #define R_SCI0_MECR_SBEREN_Msk         (0x4UL)  /*!< SBEREN (Bitfield-Mask: 0x01)                          */
23874 
23875 /* =========================================================================================================================== */
23876 /* ================                                          R_SLCDC                                          ================ */
23877 /* =========================================================================================================================== */
23878 
23879 /* =========================================================  LCDM0  ========================================================= */
23880  #define R_SLCDC_LCDM0_MDSET_Pos     (6UL)    /*!< MDSET (Bit 6)                                         */
23881  #define R_SLCDC_LCDM0_MDSET_Msk     (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03)                           */
23882  #define R_SLCDC_LCDM0_LWAVE_Pos     (5UL)    /*!< LWAVE (Bit 5)                                         */
23883  #define R_SLCDC_LCDM0_LWAVE_Msk     (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01)                           */
23884  #define R_SLCDC_LCDM0_LDTY_Pos      (2UL)    /*!< LDTY (Bit 2)                                          */
23885  #define R_SLCDC_LCDM0_LDTY_Msk      (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07)                            */
23886  #define R_SLCDC_LCDM0_LBAS_Pos      (0UL)    /*!< LBAS (Bit 0)                                          */
23887  #define R_SLCDC_LCDM0_LBAS_Msk      (0x3UL)  /*!< LBAS (Bitfield-Mask: 0x03)                            */
23888 /* =========================================================  LCDM1  ========================================================= */
23889  #define R_SLCDC_LCDM1_LCDON_Pos     (7UL)    /*!< LCDON (Bit 7)                                         */
23890  #define R_SLCDC_LCDM1_LCDON_Msk     (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01)                           */
23891  #define R_SLCDC_LCDM1_SCOC_Pos      (6UL)    /*!< SCOC (Bit 6)                                          */
23892  #define R_SLCDC_LCDM1_SCOC_Msk      (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01)                            */
23893  #define R_SLCDC_LCDM1_VLCON_Pos     (5UL)    /*!< VLCON (Bit 5)                                         */
23894  #define R_SLCDC_LCDM1_VLCON_Msk     (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01)                           */
23895  #define R_SLCDC_LCDM1_BLON_Pos      (4UL)    /*!< BLON (Bit 4)                                          */
23896  #define R_SLCDC_LCDM1_BLON_Msk      (0x10UL) /*!< BLON (Bitfield-Mask: 0x01)                            */
23897  #define R_SLCDC_LCDM1_LCDSEL_Pos    (3UL)    /*!< LCDSEL (Bit 3)                                        */
23898  #define R_SLCDC_LCDM1_LCDSEL_Msk    (0x8UL)  /*!< LCDSEL (Bitfield-Mask: 0x01)                          */
23899  #define R_SLCDC_LCDM1_LCDVLM_Pos    (0UL)    /*!< LCDVLM (Bit 0)                                        */
23900  #define R_SLCDC_LCDM1_LCDVLM_Msk    (0x1UL)  /*!< LCDVLM (Bitfield-Mask: 0x01)                          */
23901 /* =========================================================  LCDC0  ========================================================= */
23902  #define R_SLCDC_LCDC0_LCDC_Pos      (0UL)    /*!< LCDC (Bit 0)                                          */
23903  #define R_SLCDC_LCDC0_LCDC_Msk      (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f)                            */
23904 /* =========================================================  VLCD  ========================================================== */
23905  #define R_SLCDC_VLCD_MDSET2_Pos     (7UL)    /*!< MDSET2 (Bit 7)                                        */
23906  #define R_SLCDC_VLCD_MDSET2_Msk     (0x80UL) /*!< MDSET2 (Bitfield-Mask: 0x01)                          */
23907  #define R_SLCDC_VLCD_VLCD_Pos       (0UL)    /*!< VLCD (Bit 0)                                          */
23908  #define R_SLCDC_VLCD_VLCD_Msk       (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f)                            */
23909 /* ==========================================================  SEG  ========================================================== */
23910  #define R_SLCDC_SEG_A_Pos           (0UL)    /*!< A (Bit 0)                                             */
23911  #define R_SLCDC_SEG_A_Msk           (0xfUL)  /*!< A (Bitfield-Mask: 0x0f)                               */
23912  #define R_SLCDC_SEG_B_Pos           (4UL)    /*!< B (Bit 4)                                             */
23913  #define R_SLCDC_SEG_B_Msk           (0xf0UL) /*!< B (Bitfield-Mask: 0x0f)                               */
23914 
23915 /* =========================================================================================================================== */
23916 /* ================                                          R_SPI0                                           ================ */
23917 /* =========================================================================================================================== */
23918 
23919 /* =========================================================  SPCR  ========================================================== */
23920  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
23921  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
23922  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
23923  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
23924  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
23925  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
23926  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
23927  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
23928  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
23929  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
23930  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
23931  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
23932  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
23933  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
23934  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
23935  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
23936 /* =========================================================  SSLP  ========================================================== */
23937  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
23938  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
23939  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
23940  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
23941  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
23942  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
23943  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
23944  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
23945  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
23946  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
23947  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
23948  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
23949  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
23950  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
23951  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
23952  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
23953 /* =========================================================  SPPCR  ========================================================= */
23954  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
23955  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
23956  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
23957  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
23958  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
23959  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
23960  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
23961  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
23962 /* =========================================================  SPSR  ========================================================== */
23963  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
23964  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
23965  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
23966  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
23967  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
23968  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
23969  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
23970  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
23971  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
23972  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
23973  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
23974  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
23975  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
23976  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
23977  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
23978  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
23979 /* =========================================================  SPDR  ========================================================== */
23980 /* ========================================================  SPDR_HA  ======================================================== */
23981 /* ========================================================  SPDR_BY  ======================================================== */
23982 /* =========================================================  SPSCR  ========================================================= */
23983  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
23984  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
23985 /* =========================================================  SPBR  ========================================================== */
23986  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
23987  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
23988 /* =========================================================  SPDCR  ========================================================= */
23989  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
23990  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
23991  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
23992  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
23993  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
23994  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
23995  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
23996  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
23997  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
23998  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
23999 /* =========================================================  SPCKD  ========================================================= */
24000  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
24001  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
24002 /* =========================================================  SSLND  ========================================================= */
24003  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
24004  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
24005 /* =========================================================  SPND  ========================================================== */
24006  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
24007  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
24008 /* =========================================================  SPCR2  ========================================================= */
24009  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
24010  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
24011  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
24012  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
24013  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
24014  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
24015  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
24016  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
24017  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
24018  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
24019  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
24020  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
24021 /* =========================================================  SPCMD  ========================================================= */
24022  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
24023  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
24024  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
24025  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
24026  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
24027  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
24028  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
24029  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
24030  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
24031  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
24032  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
24033  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
24034  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
24035  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
24036  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
24037  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
24038  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
24039  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
24040  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
24041  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
24042 /* ========================================================  SPDCR2  ========================================================= */
24043  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
24044  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
24045  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
24046  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
24047 /* =========================================================  SPSSR  ========================================================= */
24048  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
24049  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
24050  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
24051  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
24052 /* =========================================================  SPCR3  ========================================================= */
24053  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
24054  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
24055  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
24056  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
24057  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
24058  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
24059 /* =========================================================  SPPR  ========================================================== */
24060  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
24061  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
24062  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
24063  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
24064  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
24065  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
24066 
24067 /* =========================================================================================================================== */
24068 /* ================                                          R_SRAM                                           ================ */
24069 /* =========================================================================================================================== */
24070 
24071 /* ========================================================  PARIOAD  ======================================================== */
24072  #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
24073  #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
24074 /* =======================================================  SRAMPRCR  ======================================================== */
24075  #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
24076  #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
24077  #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
24078  #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
24079 /* =======================================================  SRAMWTSC  ======================================================== */
24080 /* ========================================================  ECCMODE  ======================================================== */
24081  #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
24082  #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
24083 /* ========================================================  ECC2STS  ======================================================== */
24084  #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
24085  #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
24086 /* =======================================================  ECC1STSEN  ======================================================= */
24087  #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
24088  #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
24089 /* ========================================================  ECC1STS  ======================================================== */
24090  #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
24091  #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
24092 /* ========================================================  ECCPRCR  ======================================================== */
24093  #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
24094  #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
24095  #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
24096  #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
24097 /* =======================================================  ECCPRCR2  ======================================================== */
24098  #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
24099  #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
24100  #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
24101  #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
24102 /* ========================================================  ECCETST  ======================================================== */
24103  #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
24104  #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
24105 /* ========================================================  ECCOAD  ========================================================= */
24106  #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
24107  #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
24108 /* =======================================================  SRAMPRCR2  ======================================================= */
24109  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
24110  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
24111  #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
24112  #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
24113 
24114 /* =========================================================================================================================== */
24115 /* ================                                          R_SSI0                                           ================ */
24116 /* =========================================================================================================================== */
24117 
24118 /* =========================================================  SSICR  ========================================================= */
24119  #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
24120  #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
24121  #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
24122  #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
24123  #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
24124  #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
24125  #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
24126  #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
24127  #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
24128  #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
24129  #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
24130  #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
24131  #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
24132  #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
24133  #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
24134  #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
24135  #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
24136  #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
24137  #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
24138  #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
24139  #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
24140  #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
24141  #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
24142  #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
24143  #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
24144  #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
24145  #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
24146  #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
24147  #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
24148  #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
24149  #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
24150  #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
24151  #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
24152  #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
24153  #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
24154  #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
24155  #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
24156  #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
24157  #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
24158  #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
24159 /* =========================================================  SSISR  ========================================================= */
24160  #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
24161  #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
24162  #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
24163  #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
24164  #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
24165  #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
24166  #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
24167  #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
24168  #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
24169  #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
24170  #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
24171  #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
24172  #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
24173  #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
24174  #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
24175  #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
24176  #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
24177  #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
24178  #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
24179  #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
24180 /* ========================================================  SSIFCR  ========================================================= */
24181  #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
24182  #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
24183  #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
24184  #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
24185  #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
24186  #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
24187  #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
24188  #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
24189  #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
24190  #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
24191  #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
24192  #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
24193  #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
24194  #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
24195  #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
24196  #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
24197  #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
24198  #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
24199 /* ========================================================  SSIFSR  ========================================================= */
24200  #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
24201  #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
24202  #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
24203  #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
24204  #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
24205  #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
24206  #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
24207  #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
24208 /* ========================================================  SSIFTDR  ======================================================== */
24209  #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
24210  #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
24211 /* =======================================================  SSIFTDR16  ======================================================= */
24212 /* =======================================================  SSIFTDR8  ======================================================== */
24213 /* ========================================================  SSIFRDR  ======================================================== */
24214  #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
24215  #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
24216 /* =======================================================  SSIFRDR16  ======================================================= */
24217 /* =======================================================  SSIFRDR8  ======================================================== */
24218 /* ========================================================  SSIOFR  ========================================================= */
24219  #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
24220  #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
24221  #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
24222  #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
24223  #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
24224  #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
24225 /* ========================================================  SSISCR  ========================================================= */
24226  #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
24227  #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
24228  #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
24229  #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
24230 
24231 /* =========================================================================================================================== */
24232 /* ================                                         R_SYSTEM                                          ================ */
24233 /* =========================================================================================================================== */
24234 
24235 /* =========================================================  SBYCR  ========================================================= */
24236  #define R_SYSTEM_SBYCR_SSBY_Pos                 (15UL)         /*!< SSBY (Bit 15)                                         */
24237  #define R_SYSTEM_SBYCR_SSBY_Msk                 (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
24238 /* =======================================================  SCKDIVCR  ======================================================== */
24239  #define R_SYSTEM_SCKDIVCR_FCK_Pos               (28UL)         /*!< FCK (Bit 28)                                          */
24240  #define R_SYSTEM_SCKDIVCR_FCK_Msk               (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
24241  #define R_SYSTEM_SCKDIVCR_ICK_Pos               (24UL)         /*!< ICK (Bit 24)                                          */
24242  #define R_SYSTEM_SCKDIVCR_ICK_Msk               (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
24243  #define R_SYSTEM_SCKDIVCR_BCK_Pos               (16UL)         /*!< BCK (Bit 16)                                          */
24244  #define R_SYSTEM_SCKDIVCR_BCK_Msk               (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
24245  #define R_SYSTEM_SCKDIVCR_PCKA_Pos              (12UL)         /*!< PCKA (Bit 12)                                         */
24246  #define R_SYSTEM_SCKDIVCR_PCKA_Msk              (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
24247  #define R_SYSTEM_SCKDIVCR_PCKB_Pos              (8UL)          /*!< PCKB (Bit 8)                                          */
24248  #define R_SYSTEM_SCKDIVCR_PCKB_Msk              (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
24249  #define R_SYSTEM_SCKDIVCR_PCKC_Pos              (4UL)          /*!< PCKC (Bit 4)                                          */
24250  #define R_SYSTEM_SCKDIVCR_PCKC_Msk              (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
24251  #define R_SYSTEM_SCKDIVCR_PCKD_Pos              (0UL)          /*!< PCKD (Bit 0)                                          */
24252  #define R_SYSTEM_SCKDIVCR_PCKD_Msk              (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
24253 /* ========================================================  SCKSCR  ========================================================= */
24254  #define R_SYSTEM_SCKSCR_CKSEL_Pos               (0UL)          /*!< CKSEL (Bit 0)                                         */
24255  #define R_SYSTEM_SCKSCR_CKSEL_Msk               (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
24256 /* ========================================================  PLLCCR  ========================================================= */
24257  #define R_SYSTEM_PLLCCR_PLLMUL_Pos              (8UL)          /*!< PLLMUL (Bit 8)                                        */
24258  #define R_SYSTEM_PLLCCR_PLLMUL_Msk              (0x1f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
24259  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos            (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
24260  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk            (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
24261  #define R_SYSTEM_PLLCCR_PLIDIV_Pos              (0UL)          /*!< PLIDIV (Bit 0)                                        */
24262  #define R_SYSTEM_PLLCCR_PLIDIV_Msk              (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
24263 /* =========================================================  PLLCR  ========================================================= */
24264  #define R_SYSTEM_PLLCR_PLLSTP_Pos               (0UL)          /*!< PLLSTP (Bit 0)                                        */
24265  #define R_SYSTEM_PLLCR_PLLSTP_Msk               (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
24266 /* =======================================================  PLLRTCCR  ======================================================== */
24267  #define R_SYSTEM_PLLRTCCR_PLLRTCSTP_Pos         (0UL)          /*!< PLLRTCSTP (Bit 0)                                     */
24268  #define R_SYSTEM_PLLRTCCR_PLLRTCSTP_Msk         (0x1UL)        /*!< PLLRTCSTP (Bitfield-Mask: 0x01)                       */
24269 /* ========================================================  MEMWAIT  ======================================================== */
24270  #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos            (0UL)          /*!< MEMWAIT (Bit 0)                                       */
24271  #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk            (0x3UL)        /*!< MEMWAIT (Bitfield-Mask: 0x03)                         */
24272 /* ========================================================  MOSCCR  ========================================================= */
24273  #define R_SYSTEM_MOSCCR_MOSTP_Pos               (0UL)          /*!< MOSTP (Bit 0)                                         */
24274  #define R_SYSTEM_MOSCCR_MOSTP_Msk               (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
24275 /* ========================================================  HOCOCR  ========================================================= */
24276  #define R_SYSTEM_HOCOCR_HCSTP_Pos               (0UL)          /*!< HCSTP (Bit 0)                                         */
24277  #define R_SYSTEM_HOCOCR_HCSTP_Msk               (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
24278 /* ========================================================  MOCOCR  ========================================================= */
24279  #define R_SYSTEM_MOCOCR_MCSTP_Pos               (0UL)          /*!< MCSTP (Bit 0)                                         */
24280  #define R_SYSTEM_MOCOCR_MCSTP_Msk               (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
24281 /* =========================================================  OSCSF  ========================================================= */
24282  #define R_SYSTEM_OSCSF_PLLRTCSF_Pos             (7UL)          /*!< PLLRTCSF (Bit 7)                                      */
24283  #define R_SYSTEM_OSCSF_PLLRTCSF_Msk             (0x80UL)       /*!< PLLRTCSF (Bitfield-Mask: 0x01)                        */
24284  #define R_SYSTEM_OSCSF_PLLSF_Pos                (5UL)          /*!< PLLSF (Bit 5)                                         */
24285  #define R_SYSTEM_OSCSF_PLLSF_Msk                (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
24286  #define R_SYSTEM_OSCSF_MOSCSF_Pos               (3UL)          /*!< MOSCSF (Bit 3)                                        */
24287  #define R_SYSTEM_OSCSF_MOSCSF_Msk               (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
24288  #define R_SYSTEM_OSCSF_HOCOSF_Pos               (0UL)          /*!< HOCOSF (Bit 0)                                        */
24289  #define R_SYSTEM_OSCSF_HOCOSF_Msk               (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
24290 /* =========================================================  CKOCR  ========================================================= */
24291  #define R_SYSTEM_CKOCR_CKOEN_Pos                (7UL)          /*!< CKOEN (Bit 7)                                         */
24292  #define R_SYSTEM_CKOCR_CKOEN_Msk                (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
24293  #define R_SYSTEM_CKOCR_CKODIV_Pos               (4UL)          /*!< CKODIV (Bit 4)                                        */
24294  #define R_SYSTEM_CKOCR_CKODIV_Msk               (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
24295  #define R_SYSTEM_CKOCR_CKOSEL_Pos               (0UL)          /*!< CKOSEL (Bit 0)                                        */
24296  #define R_SYSTEM_CKOCR_CKOSEL_Msk               (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
24297 /* ========================================================  OSTDCR  ========================================================= */
24298  #define R_SYSTEM_OSTDCR_OSTDE_Pos               (7UL)          /*!< OSTDE (Bit 7)                                         */
24299  #define R_SYSTEM_OSTDCR_OSTDE_Msk               (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
24300  #define R_SYSTEM_OSTDCR_OSTDIE_Pos              (0UL)          /*!< OSTDIE (Bit 0)                                        */
24301  #define R_SYSTEM_OSTDCR_OSTDIE_Msk              (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
24302 /* ========================================================  OSTDSR  ========================================================= */
24303  #define R_SYSTEM_OSTDSR_OSTDF_Pos               (0UL)          /*!< OSTDF (Bit 0)                                         */
24304  #define R_SYSTEM_OSTDSR_OSTDF_Msk               (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
24305 /* ========================================================  SOSTDCR  ======================================================== */
24306  #define R_SYSTEM_SOSTDCR_SOSDCE_Pos             (15UL)         /*!< SOSDCE (Bit 15)                                       */
24307  #define R_SYSTEM_SOSTDCR_SOSDCE_Msk             (0x8000UL)     /*!< SOSDCE (Bitfield-Mask: 0x01)                          */
24308  #define R_SYSTEM_SOSTDCR_SOSDCF_Pos             (14UL)         /*!< SOSDCF (Bit 14)                                       */
24309  #define R_SYSTEM_SOSTDCR_SOSDCF_Msk             (0x4000UL)     /*!< SOSDCF (Bitfield-Mask: 0x01)                          */
24310  #define R_SYSTEM_SOSTDCR_SOSTDF_Pos             (13UL)         /*!< SOSTDF (Bit 13)                                       */
24311  #define R_SYSTEM_SOSTDCR_SOSTDF_Msk             (0x2000UL)     /*!< SOSTDF (Bitfield-Mask: 0x01)                          */
24312  #define R_SYSTEM_SOSTDCR_SOSTDIE_Pos            (12UL)         /*!< SOSTDIE (Bit 12)                                      */
24313  #define R_SYSTEM_SOSTDCR_SOSTDIE_Msk            (0x1000UL)     /*!< SOSTDIE (Bitfield-Mask: 0x01)                         */
24314  #define R_SYSTEM_SOSTDCR_SOSDCCMP_Pos           (0UL)          /*!< SOSDCCMP (Bit 0)                                      */
24315  #define R_SYSTEM_SOSTDCR_SOSDCCMP_Msk           (0xfffUL)      /*!< SOSDCCMP (Bitfield-Mask: 0xfff)                       */
24316 /* =======================================================  SLCDSCKCR  ======================================================= */
24317  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos         (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
24318  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk         (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
24319  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos        (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
24320  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk        (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
24321 /* =======================================================  MOCOUTCR  ======================================================== */
24322  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos          (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
24323  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk          (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
24324 /* =======================================================  HOCOUTCR  ======================================================== */
24325  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos          (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
24326  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk          (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
24327 /* =========================================================  SNZCR  ========================================================= */
24328  #define R_SYSTEM_SNZCR_SNZE_Pos                 (7UL)          /*!< SNZE (Bit 7)                                          */
24329  #define R_SYSTEM_SNZCR_SNZE_Msk                 (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
24330  #define R_SYSTEM_SNZCR_SNZDTCEN_Pos             (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
24331  #define R_SYSTEM_SNZCR_SNZDTCEN_Msk             (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
24332  #define R_SYSTEM_SNZCR_RXDREQEN_Pos             (0UL)          /*!< RXDREQEN (Bit 0)                                      */
24333  #define R_SYSTEM_SNZCR_RXDREQEN_Msk             (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
24334 /* ========================================================  SNZEDCR  ======================================================== */
24335  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos          (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
24336  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk          (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
24337  #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos           (4UL)          /*!< AD0UMTED (Bit 4)                                      */
24338  #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk           (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
24339  #define R_SYSTEM_SNZEDCR_AD0MATED_Pos           (3UL)          /*!< AD0MATED (Bit 3)                                      */
24340  #define R_SYSTEM_SNZEDCR_AD0MATED_Msk           (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
24341  #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos           (2UL)          /*!< DTCNZRED (Bit 2)                                      */
24342  #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk           (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
24343  #define R_SYSTEM_SNZEDCR_DTCZRED_Pos            (1UL)          /*!< DTCZRED (Bit 1)                                       */
24344  #define R_SYSTEM_SNZEDCR_DTCZRED_Msk            (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
24345  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos          (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
24346  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk          (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
24347 /* =======================================================  SNZEDCR1  ======================================================== */
24348  #define R_SYSTEM_SNZEDCR1_CTSUNAJED_Pos         (1UL)          /*!< CTSUNAJED (Bit 1)                                     */
24349  #define R_SYSTEM_SNZEDCR1_CTSUNAJED_Msk         (0x2UL)        /*!< CTSUNAJED (Bitfield-Mask: 0x01)                       */
24350 /* =======================================================  SNZREQCR  ======================================================== */
24351  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos        (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
24352  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk        (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
24353  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos        (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
24354  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk        (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
24355  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos        (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
24356  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk        (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
24357  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos        (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
24358  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk        (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
24359  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos        (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
24360  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk        (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
24361  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos        (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
24362  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk        (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
24363  #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos          (0UL)          /*!< SNZREQEN (Bit 0)                                      */
24364  #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk          (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
24365 /* =========================================================  PSMCR  ========================================================= */
24366  #define R_SYSTEM_PSMCR_PSMC_Pos                 (0UL)          /*!< PSMC (Bit 0)                                          */
24367  #define R_SYSTEM_PSMCR_PSMC_Msk                 (0x1UL)        /*!< PSMC (Bitfield-Mask: 0x01)                            */
24368 /* =========================================================  OPCCR  ========================================================= */
24369  #define R_SYSTEM_OPCCR_OPCMTSF_Pos              (4UL)          /*!< OPCMTSF (Bit 4)                                       */
24370  #define R_SYSTEM_OPCCR_OPCMTSF_Msk              (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
24371  #define R_SYSTEM_OPCCR_OPCM_Pos                 (0UL)          /*!< OPCM (Bit 0)                                          */
24372  #define R_SYSTEM_OPCCR_OPCM_Msk                 (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
24373 /* ========================================================  SOPCCR  ========================================================= */
24374  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos            (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
24375  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk            (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
24376  #define R_SYSTEM_SOPCCR_SOPCM_Pos               (0UL)          /*!< SOPCM (Bit 0)                                         */
24377  #define R_SYSTEM_SOPCCR_SOPCM_Msk               (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
24378 /* =======================================================  MOSCWTCR  ======================================================== */
24379  #define R_SYSTEM_MOSCWTCR_MSTS_Pos              (0UL)          /*!< MSTS (Bit 0)                                          */
24380  #define R_SYSTEM_MOSCWTCR_MSTS_Msk              (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
24381 /* ========================================================  SRMPSCR  ======================================================== */
24382  #define R_SYSTEM_SRMPSCR_SPSC_Pos               (0UL)          /*!< SPSC (Bit 0)                                          */
24383  #define R_SYSTEM_SRMPSCR_SPSC_Msk               (0x1UL)        /*!< SPSC (Bitfield-Mask: 0x01)                            */
24384 /* ========================================================  RSTSR1  ========================================================= */
24385  #define R_SYSTEM_RSTSR1_BUSMRF_Pos              (11UL)         /*!< BUSMRF (Bit 11)                                       */
24386  #define R_SYSTEM_RSTSR1_BUSMRF_Msk              (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
24387  #define R_SYSTEM_RSTSR1_REERF_Pos               (9UL)          /*!< REERF (Bit 9)                                         */
24388  #define R_SYSTEM_RSTSR1_REERF_Msk               (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
24389  #define R_SYSTEM_RSTSR1_RPERF_Pos               (8UL)          /*!< RPERF (Bit 8)                                         */
24390  #define R_SYSTEM_RSTSR1_RPERF_Msk               (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
24391  #define R_SYSTEM_RSTSR1_SWRF_Pos                (2UL)          /*!< SWRF (Bit 2)                                          */
24392  #define R_SYSTEM_RSTSR1_SWRF_Msk                (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
24393  #define R_SYSTEM_RSTSR1_WDTRF_Pos               (1UL)          /*!< WDTRF (Bit 1)                                         */
24394  #define R_SYSTEM_RSTSR1_WDTRF_Msk               (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
24395  #define R_SYSTEM_RSTSR1_IWDTRF_Pos              (0UL)          /*!< IWDTRF (Bit 0)                                        */
24396  #define R_SYSTEM_RSTSR1_IWDTRF_Msk              (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
24397  #define R_SYSTEM_RSTSR1_TZERF_Pos               (13UL)         /*!< TZERF (Bit 13)                                        */
24398  #define R_SYSTEM_RSTSR1_TZERF_Msk               (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
24399  #define R_SYSTEM_RSTSR1_CPERF_Pos               (15UL)         /*!< CPERF (Bit 15)                                        */
24400  #define R_SYSTEM_RSTSR1_CPERF_Msk               (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
24401 /* =========================================================  LDOCR  ========================================================= */
24402  #define R_SYSTEM_LDOCR_CHG0_Pos                 (0UL)          /*!< CHG0 (Bit 0)                                          */
24403  #define R_SYSTEM_LDOCR_CHG0_Msk                 (0x1UL)        /*!< CHG0 (Bitfield-Mask: 0x01)                            */
24404 /* ========================================================  LVD1CR1  ======================================================== */
24405  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
24406  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
24407  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
24408  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
24409 /* ========================================================  LVD2CR1  ======================================================== */
24410  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
24411  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
24412  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
24413  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
24414 /* ======================================================  USBCKCR_ALT  ====================================================== */
24415  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos      (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
24416  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk      (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
24417 /* ========================================================  LVD1SR  ========================================================= */
24418  #define R_SYSTEM_LVD1SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
24419  #define R_SYSTEM_LVD1SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
24420  #define R_SYSTEM_LVD1SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
24421  #define R_SYSTEM_LVD1SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
24422 /* ========================================================  LVD2SR  ========================================================= */
24423  #define R_SYSTEM_LVD2SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
24424  #define R_SYSTEM_LVD2SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
24425  #define R_SYSTEM_LVD2SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
24426  #define R_SYSTEM_LVD2SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
24427 /* =========================================================  PRCR  ========================================================== */
24428  #define R_SYSTEM_PRCR_PRKEY_Pos                 (8UL)          /*!< PRKEY (Bit 8)                                         */
24429  #define R_SYSTEM_PRCR_PRKEY_Msk                 (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
24430  #define R_SYSTEM_PRCR_PRC3_Pos                  (3UL)          /*!< PRC3 (Bit 3)                                          */
24431  #define R_SYSTEM_PRCR_PRC3_Msk                  (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
24432  #define R_SYSTEM_PRCR_PRC1_Pos                  (1UL)          /*!< PRC1 (Bit 1)                                          */
24433  #define R_SYSTEM_PRCR_PRC1_Msk                  (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
24434  #define R_SYSTEM_PRCR_PRC0_Pos                  (0UL)          /*!< PRC0 (Bit 0)                                          */
24435  #define R_SYSTEM_PRCR_PRC0_Msk                  (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
24436  #define R_SYSTEM_PRCR_PRC4_Pos                  (4UL)          /*!< PRC4 (Bit 4)                                          */
24437  #define R_SYSTEM_PRCR_PRC4_Msk                  (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
24438 /* ========================================================  SYOCDCR  ======================================================== */
24439  #define R_SYSTEM_SYOCDCR_DBGEN_Pos              (7UL)          /*!< DBGEN (Bit 7)                                         */
24440  #define R_SYSTEM_SYOCDCR_DBGEN_Msk              (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
24441 /* =========================================================  MOMCR  ========================================================= */
24442  #define R_SYSTEM_MOMCR_MOSEL_Pos                (6UL)          /*!< MOSEL (Bit 6)                                         */
24443  #define R_SYSTEM_MOMCR_MOSEL_Msk                (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
24444  #define R_SYSTEM_MOMCR_MODRV1_Pos               (3UL)          /*!< MODRV1 (Bit 3)                                        */
24445  #define R_SYSTEM_MOMCR_MODRV1_Msk               (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
24446 /* ========================================================  RSTSR0  ========================================================= */
24447  #define R_SYSTEM_RSTSR0_LVD2RF_Pos              (3UL)          /*!< LVD2RF (Bit 3)                                        */
24448  #define R_SYSTEM_RSTSR0_LVD2RF_Msk              (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
24449  #define R_SYSTEM_RSTSR0_LVD1RF_Pos              (2UL)          /*!< LVD1RF (Bit 2)                                        */
24450  #define R_SYSTEM_RSTSR0_LVD1RF_Msk              (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
24451  #define R_SYSTEM_RSTSR0_LVD0RF_Pos              (1UL)          /*!< LVD0RF (Bit 1)                                        */
24452  #define R_SYSTEM_RSTSR0_LVD0RF_Msk              (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
24453  #define R_SYSTEM_RSTSR0_PORF_Pos                (0UL)          /*!< PORF (Bit 0)                                          */
24454  #define R_SYSTEM_RSTSR0_PORF_Msk                (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
24455 /* ========================================================  RSTSR2  ========================================================= */
24456  #define R_SYSTEM_RSTSR2_CWSF_Pos                (0UL)          /*!< CWSF (Bit 0)                                          */
24457  #define R_SYSTEM_RSTSR2_CWSF_Msk                (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
24458 /* ========================================================  LVCMPCR  ======================================================== */
24459  #define R_SYSTEM_LVCMPCR_LVD2E_Pos              (6UL)          /*!< LVD2E (Bit 6)                                         */
24460  #define R_SYSTEM_LVCMPCR_LVD2E_Msk              (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
24461  #define R_SYSTEM_LVCMPCR_LVD1E_Pos              (5UL)          /*!< LVD1E (Bit 5)                                         */
24462  #define R_SYSTEM_LVCMPCR_LVD1E_Msk              (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
24463 /* =======================================================  LVD1CMPCR  ======================================================= */
24464  #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos           (0UL)          /*!< LVDLVL (Bit 0)                                        */
24465  #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk           (0xfUL)        /*!< LVDLVL (Bitfield-Mask: 0x0f)                          */
24466  #define R_SYSTEM_LVD1CMPCR_LVDE_Pos             (7UL)          /*!< LVDE (Bit 7)                                          */
24467  #define R_SYSTEM_LVD1CMPCR_LVDE_Msk             (0x80UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
24468 /* =======================================================  LVD2CMPCR  ======================================================= */
24469  #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos           (0UL)          /*!< LVDLVL (Bit 0)                                        */
24470  #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk           (0x7UL)        /*!< LVDLVL (Bitfield-Mask: 0x07)                          */
24471  #define R_SYSTEM_LVD2CMPCR_EXVCCINP2_Pos        (6UL)          /*!< EXVCCINP2 (Bit 6)                                     */
24472  #define R_SYSTEM_LVD2CMPCR_EXVCCINP2_Msk        (0x40UL)       /*!< EXVCCINP2 (Bitfield-Mask: 0x01)                       */
24473  #define R_SYSTEM_LVD2CMPCR_LVDE_Pos             (7UL)          /*!< LVDE (Bit 7)                                          */
24474  #define R_SYSTEM_LVD2CMPCR_LVDE_Msk             (0x80UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
24475 /* ========================================================  LVD1CR0  ======================================================== */
24476  #define R_SYSTEM_LVD1CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
24477  #define R_SYSTEM_LVD1CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
24478  #define R_SYSTEM_LVD1CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
24479  #define R_SYSTEM_LVD1CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
24480  #define R_SYSTEM_LVD1CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
24481  #define R_SYSTEM_LVD1CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
24482  #define R_SYSTEM_LVD1CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
24483  #define R_SYSTEM_LVD1CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
24484 /* ========================================================  LVD2CR0  ======================================================== */
24485  #define R_SYSTEM_LVD2CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
24486  #define R_SYSTEM_LVD2CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
24487  #define R_SYSTEM_LVD2CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
24488  #define R_SYSTEM_LVD2CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
24489  #define R_SYSTEM_LVD2CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
24490  #define R_SYSTEM_LVD2CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
24491  #define R_SYSTEM_LVD2CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
24492  #define R_SYSTEM_LVD2CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
24493 /* ========================================================  SOSCCR  ========================================================= */
24494  #define R_SYSTEM_SOSCCR_SOSTP_Pos               (0UL)          /*!< SOSTP (Bit 0)                                         */
24495  #define R_SYSTEM_SOSCCR_SOSTP_Msk               (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
24496 /* =========================================================  SOMCR  ========================================================= */
24497  #define R_SYSTEM_SOMCR_SODRV_Pos                (0UL)          /*!< SODRV (Bit 0)                                         */
24498  #define R_SYSTEM_SOMCR_SODRV_Msk                (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
24499  #define R_SYSTEM_SOMCR_EXCLKS_Pos               (4UL)          /*!< EXCLKS (Bit 4)                                        */
24500  #define R_SYSTEM_SOMCR_EXCLKS_Msk               (0x10UL)       /*!< EXCLKS (Bitfield-Mask: 0x01)                          */
24501 /* =========================================================  SOMRG  ========================================================= */
24502  #define R_SYSTEM_SOMRG_SOSCMRG_Pos              (0UL)          /*!< SOSCMRG (Bit 0)                                       */
24503  #define R_SYSTEM_SOMRG_SOSCMRG_Msk              (0x3UL)        /*!< SOSCMRG (Bitfield-Mask: 0x03)                         */
24504 /* ========================================================  LOCOCR  ========================================================= */
24505  #define R_SYSTEM_LOCOCR_LCSTP_Pos               (0UL)          /*!< LCSTP (Bit 0)                                         */
24506  #define R_SYSTEM_LOCOCR_LCSTP_Msk               (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
24507 /* =======================================================  LOCOUTCR  ======================================================== */
24508  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos          (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
24509  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk          (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
24510 /* ========================================================  PLL2CR  ========================================================= */
24511  #define R_SYSTEM_PLL2CR_PLL2STP_Pos             (0UL)          /*!< PLL2STP (Bit 0)                                       */
24512  #define R_SYSTEM_PLL2CR_PLL2STP_Msk             (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
24513 /* =====================================================  CANFDCKDIVCR  ====================================================== */
24514  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos    (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
24515  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk    (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
24516 /* ======================================================  I3CCKDIVCR  ======================================================= */
24517  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos        (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
24518  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk        (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
24519 /* ========================================================  USBCKCR  ======================================================== */
24520  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos           (0UL)          /*!< USBCKSEL (Bit 0)                                      */
24521  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk           (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
24522  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos          (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
24523  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk          (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
24524  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos          (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
24525  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk          (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
24526 /* =======================================================  CANFDCKCR  ======================================================= */
24527  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos       (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
24528  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk       (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
24529  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos      (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
24530  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk      (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
24531  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos      (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
24532  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk      (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
24533 /* ========================================================  I3CCKCR  ======================================================== */
24534  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos           (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
24535  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk           (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
24536  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos          (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
24537  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk          (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
24538  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos          (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
24539  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk          (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
24540 /* ========================================================  CGFSAR  ========================================================= */
24541  #define R_SYSTEM_CGFSAR_NONSEC00_Pos            (0UL)          /*!< NONSEC00 (Bit 0)                                      */
24542  #define R_SYSTEM_CGFSAR_NONSEC00_Msk            (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
24543  #define R_SYSTEM_CGFSAR_NONSEC02_Pos            (2UL)          /*!< NONSEC02 (Bit 2)                                      */
24544  #define R_SYSTEM_CGFSAR_NONSEC02_Msk            (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
24545  #define R_SYSTEM_CGFSAR_NONSEC03_Pos            (3UL)          /*!< NONSEC03 (Bit 3)                                      */
24546  #define R_SYSTEM_CGFSAR_NONSEC03_Msk            (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
24547  #define R_SYSTEM_CGFSAR_NONSEC04_Pos            (4UL)          /*!< NONSEC04 (Bit 4)                                      */
24548  #define R_SYSTEM_CGFSAR_NONSEC04_Msk            (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
24549  #define R_SYSTEM_CGFSAR_NONSEC05_Pos            (5UL)          /*!< NONSEC05 (Bit 5)                                      */
24550  #define R_SYSTEM_CGFSAR_NONSEC05_Msk            (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
24551  #define R_SYSTEM_CGFSAR_NONSEC06_Pos            (6UL)          /*!< NONSEC06 (Bit 6)                                      */
24552  #define R_SYSTEM_CGFSAR_NONSEC06_Msk            (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
24553  #define R_SYSTEM_CGFSAR_NONSEC07_Pos            (7UL)          /*!< NONSEC07 (Bit 7)                                      */
24554  #define R_SYSTEM_CGFSAR_NONSEC07_Msk            (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
24555  #define R_SYSTEM_CGFSAR_NONSEC08_Pos            (8UL)          /*!< NONSEC08 (Bit 8)                                      */
24556  #define R_SYSTEM_CGFSAR_NONSEC08_Msk            (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
24557  #define R_SYSTEM_CGFSAR_NONSEC11_Pos            (11UL)         /*!< NONSEC11 (Bit 11)                                     */
24558  #define R_SYSTEM_CGFSAR_NONSEC11_Msk            (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
24559  #define R_SYSTEM_CGFSAR_NONSEC16_Pos            (16UL)         /*!< NONSEC16 (Bit 16)                                     */
24560  #define R_SYSTEM_CGFSAR_NONSEC16_Msk            (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
24561  #define R_SYSTEM_CGFSAR_NONSEC18_Pos            (18UL)         /*!< NONSEC18 (Bit 18)                                     */
24562  #define R_SYSTEM_CGFSAR_NONSEC18_Msk            (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
24563  #define R_SYSTEM_CGFSAR_NONSEC20_Pos            (20UL)         /*!< NONSEC20 (Bit 20)                                     */
24564  #define R_SYSTEM_CGFSAR_NONSEC20_Msk            (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
24565  #define R_SYSTEM_CGFSAR_NONSEC26_Pos            (26UL)         /*!< NONSEC26 (Bit 26)                                     */
24566  #define R_SYSTEM_CGFSAR_NONSEC26_Msk            (0x4000000UL)  /*!< NONSEC26 (Bitfield-Mask: 0x01)                        */
24567  #define R_SYSTEM_CGFSAR_NONSEC27_Pos            (27UL)         /*!< NONSEC27 (Bit 27)                                     */
24568  #define R_SYSTEM_CGFSAR_NONSEC27_Msk            (0x8000000UL)  /*!< NONSEC27 (Bitfield-Mask: 0x01)                        */
24569 /* ========================================================  LPMSAR  ========================================================= */
24570  #define R_SYSTEM_LPMSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
24571  #define R_SYSTEM_LPMSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
24572  #define R_SYSTEM_LPMSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
24573  #define R_SYSTEM_LPMSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
24574  #define R_SYSTEM_LPMSAR_NONSEC4_Pos             (4UL)          /*!< NONSEC4 (Bit 4)                                       */
24575  #define R_SYSTEM_LPMSAR_NONSEC4_Msk             (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
24576 /* ========================================================  LVDSAR  ========================================================= */
24577  #define R_SYSTEM_LVDSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
24578  #define R_SYSTEM_LVDSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
24579  #define R_SYSTEM_LVDSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
24580  #define R_SYSTEM_LVDSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
24581  #define R_SYSTEM_LVDSAR_NONSEC8_Pos             (8UL)          /*!< NONSEC8 (Bit 8)                                       */
24582  #define R_SYSTEM_LVDSAR_NONSEC8_Msk             (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
24583  #define R_SYSTEM_LVDSAR_NONSEC9_Pos             (9UL)          /*!< NONSEC9 (Bit 9)                                       */
24584  #define R_SYSTEM_LVDSAR_NONSEC9_Msk             (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
24585  #define R_SYSTEM_LVDSAR_NONSEC10_Pos            (10UL)         /*!< NONSEC10 (Bit 10)                                     */
24586  #define R_SYSTEM_LVDSAR_NONSEC10_Msk            (0x400UL)      /*!< NONSEC10 (Bitfield-Mask: 0x01)                        */
24587 /* ========================================================  RSTSAR  ========================================================= */
24588  #define R_SYSTEM_RSTSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
24589  #define R_SYSTEM_RSTSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
24590  #define R_SYSTEM_RSTSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
24591  #define R_SYSTEM_RSTSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
24592  #define R_SYSTEM_RSTSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
24593  #define R_SYSTEM_RSTSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
24594 /* =======================================================  VBTLVDCR  ======================================================== */
24595  #define R_SYSTEM_VBTLVDCR_LVDE_Pos              (4UL)          /*!< LVDE (Bit 4)                                          */
24596  #define R_SYSTEM_VBTLVDCR_LVDE_Msk              (0x10UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
24597  #define R_SYSTEM_VBTLVDCR_LVL_Pos               (5UL)          /*!< LVL (Bit 5)                                           */
24598  #define R_SYSTEM_VBTLVDCR_LVL_Msk               (0xe0UL)       /*!< LVL (Bitfield-Mask: 0x07)                             */
24599 /* =======================================================  VBTLVDSR  ======================================================== */
24600  #define R_SYSTEM_VBTLVDSR_DET_Pos               (1UL)          /*!< DET (Bit 1)                                           */
24601  #define R_SYSTEM_VBTLVDSR_DET_Msk               (0x2UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
24602  #define R_SYSTEM_VBTLVDSR_MON_Pos               (5UL)          /*!< MON (Bit 5)                                           */
24603  #define R_SYSTEM_VBTLVDSR_MON_Msk               (0x20UL)       /*!< MON (Bitfield-Mask: 0x01)                             */
24604 /* =======================================================  VBTCMPCR  ======================================================== */
24605  #define R_SYSTEM_VBTCMPCR_CMPE_Pos              (0UL)          /*!< CMPE (Bit 0)                                          */
24606  #define R_SYSTEM_VBTCMPCR_CMPE_Msk              (0x1UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
24607 /* =======================================================  VBTLVDICR  ======================================================= */
24608  #define R_SYSTEM_VBTLVDICR_IE_Pos               (0UL)          /*!< IE (Bit 0)                                            */
24609  #define R_SYSTEM_VBTLVDICR_IE_Msk               (0x1UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
24610  #define R_SYSTEM_VBTLVDICR_IDTSEL_Pos           (4UL)          /*!< IDTSEL (Bit 4)                                        */
24611  #define R_SYSTEM_VBTLVDICR_IDTSEL_Msk           (0x30UL)       /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
24612 /* =======================================================  VRTLVDCR  ======================================================== */
24613  #define R_SYSTEM_VRTLVDCR_LVDE_Pos              (4UL)          /*!< LVDE (Bit 4)                                          */
24614  #define R_SYSTEM_VRTLVDCR_LVDE_Msk              (0x10UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
24615  #define R_SYSTEM_VRTLVDCR_LVL_Pos               (5UL)          /*!< LVL (Bit 5)                                           */
24616  #define R_SYSTEM_VRTLVDCR_LVL_Msk               (0xe0UL)       /*!< LVL (Bitfield-Mask: 0x07)                             */
24617 /* =========================================================  VRTSR  ========================================================= */
24618  #define R_SYSTEM_VRTSR_PORDET_Pos               (0UL)          /*!< PORDET (Bit 0)                                        */
24619  #define R_SYSTEM_VRTSR_PORDET_Msk               (0x1UL)        /*!< PORDET (Bitfield-Mask: 0x01)                          */
24620  #define R_SYSTEM_VRTSR_DET_Pos                  (1UL)          /*!< DET (Bit 1)                                           */
24621  #define R_SYSTEM_VRTSR_DET_Msk                  (0x2UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
24622  #define R_SYSTEM_VRTSR_VRTVLD_Pos               (4UL)          /*!< VRTVLD (Bit 4)                                        */
24623  #define R_SYSTEM_VRTSR_VRTVLD_Msk               (0x10UL)       /*!< VRTVLD (Bitfield-Mask: 0x01)                          */
24624  #define R_SYSTEM_VRTSR_MON_Pos                  (5UL)          /*!< MON (Bit 5)                                           */
24625  #define R_SYSTEM_VRTSR_MON_Msk                  (0x20UL)       /*!< MON (Bitfield-Mask: 0x01)                             */
24626 /* =======================================================  VRTCMPCR  ======================================================== */
24627  #define R_SYSTEM_VRTCMPCR_CMPE_Pos              (0UL)          /*!< CMPE (Bit 0)                                          */
24628  #define R_SYSTEM_VRTCMPCR_CMPE_Msk              (0x1UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
24629 /* =======================================================  VRTLVDICR  ======================================================= */
24630  #define R_SYSTEM_VRTLVDICR_IE_Pos               (0UL)          /*!< IE (Bit 0)                                            */
24631  #define R_SYSTEM_VRTLVDICR_IE_Msk               (0x1UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
24632  #define R_SYSTEM_VRTLVDICR_IDTSEL_Pos           (4UL)          /*!< IDTSEL (Bit 4)                                        */
24633  #define R_SYSTEM_VRTLVDICR_IDTSEL_Msk           (0x30UL)       /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
24634 /* ========================================================  EXLVDCR  ======================================================== */
24635  #define R_SYSTEM_EXLVDCR_LVDE_Pos               (4UL)          /*!< LVDE (Bit 4)                                          */
24636  #define R_SYSTEM_EXLVDCR_LVDE_Msk               (0x10UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
24637 /* ========================================================  EXLVDSR  ======================================================== */
24638  #define R_SYSTEM_EXLVDSR_DET_Pos                (1UL)          /*!< DET (Bit 1)                                           */
24639  #define R_SYSTEM_EXLVDSR_DET_Msk                (0x2UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
24640  #define R_SYSTEM_EXLVDSR_MON_Pos                (5UL)          /*!< MON (Bit 5)                                           */
24641  #define R_SYSTEM_EXLVDSR_MON_Msk                (0x20UL)       /*!< MON (Bitfield-Mask: 0x01)                             */
24642 /* ======================================================  EXLVDCMPCR  ======================================================= */
24643  #define R_SYSTEM_EXLVDCMPCR_CMPE_Pos            (0UL)          /*!< CMPE (Bit 0)                                          */
24644  #define R_SYSTEM_EXLVDCMPCR_CMPE_Msk            (0x1UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
24645 /* =======================================================  EXLVDICR  ======================================================== */
24646  #define R_SYSTEM_EXLVDICR_IE_Pos                (0UL)          /*!< IE (Bit 0)                                            */
24647  #define R_SYSTEM_EXLVDICR_IE_Msk                (0x1UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
24648  #define R_SYSTEM_EXLVDICR_IDTSEL_Pos            (4UL)          /*!< IDTSEL (Bit 4)                                        */
24649  #define R_SYSTEM_EXLVDICR_IDTSEL_Msk            (0x30UL)       /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
24650 
24651 /* =========================================================================================================================== */
24652 /* ================                                           R_TSN                                           ================ */
24653 /* =========================================================================================================================== */
24654 
24655 /* =========================================================  TSCDR  ========================================================= */
24656 /* ========================================================  TSCDRH  ========================================================= */
24657  #define R_TSN_TSCDRH_TSCDRH_Pos    (0UL)    /*!< TSCDRH (Bit 0)                                        */
24658  #define R_TSN_TSCDRH_TSCDRH_Msk    (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff)                          */
24659 /* ========================================================  TSCDRL  ========================================================= */
24660  #define R_TSN_TSCDRL_TSCDRL_Pos    (0UL)    /*!< TSCDRL (Bit 0)                                        */
24661  #define R_TSN_TSCDRL_TSCDRL_Msk    (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff)                          */
24662 /* ========================================================  TSCDRR  ========================================================= */
24663 
24664 /* =========================================================================================================================== */
24665 /* ================                                         R_USB_FS0                                         ================ */
24666 /* =========================================================================================================================== */
24667 
24668 /* ========================================================  SYSCFG  ========================================================= */
24669  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
24670  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
24671  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
24672  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
24673  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
24674  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
24675  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
24676  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
24677  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
24678  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
24679  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
24680  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
24681  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
24682  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
24683 /* ========================================================  BUSWAIT  ======================================================== */
24684  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
24685  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
24686 /* ========================================================  SYSSTS0  ======================================================== */
24687  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
24688  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
24689  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
24690  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
24691  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
24692  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
24693  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
24694  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
24695  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
24696  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
24697 /* ========================================================  PLLSTA  ========================================================= */
24698  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
24699  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
24700 /* =======================================================  DVSTCTR0  ======================================================== */
24701  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
24702  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
24703  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
24704  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
24705  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
24706  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
24707  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
24708  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
24709  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
24710  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
24711  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
24712  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
24713  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
24714  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
24715  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
24716  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
24717  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
24718  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
24719 /* =======================================================  TESTMODE  ======================================================== */
24720  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
24721  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
24722 /* ========================================================  CFIFOL  ========================================================= */
24723 /* ========================================================  CFIFOLL  ======================================================== */
24724 /* =========================================================  CFIFO  ========================================================= */
24725 /* ========================================================  CFIFOH  ========================================================= */
24726 /* ========================================================  CFIFOHH  ======================================================== */
24727 /* ========================================================  D0FIFOL  ======================================================== */
24728 /* =======================================================  D0FIFOLL  ======================================================== */
24729 /* ========================================================  D0FIFO  ========================================================= */
24730 /* ========================================================  D0FIFOH  ======================================================== */
24731 /* =======================================================  D0FIFOHH  ======================================================== */
24732 /* ========================================================  D1FIFOL  ======================================================== */
24733 /* =======================================================  D1FIFOLL  ======================================================== */
24734 /* ========================================================  D1FIFO  ========================================================= */
24735 /* ========================================================  D1FIFOH  ======================================================== */
24736 /* =======================================================  D1FIFOHH  ======================================================== */
24737 /* =======================================================  CFIFOSEL  ======================================================== */
24738  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
24739  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
24740  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
24741  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
24742  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
24743  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
24744  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
24745  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
24746  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
24747  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
24748  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
24749  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
24750 /* =======================================================  CFIFOCTR  ======================================================== */
24751  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
24752  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
24753  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
24754  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
24755  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
24756  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
24757  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
24758  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
24759 /* =======================================================  D0FIFOSEL  ======================================================= */
24760  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
24761  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
24762  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
24763  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
24764  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
24765  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
24766  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
24767  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
24768  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
24769  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
24770  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
24771  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
24772  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
24773  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
24774 /* =======================================================  D0FIFOCTR  ======================================================= */
24775  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
24776  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
24777  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
24778  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
24779  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
24780  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
24781  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
24782  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
24783 /* =======================================================  D1FIFOSEL  ======================================================= */
24784  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
24785  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
24786  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
24787  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
24788  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
24789  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
24790  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
24791  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
24792  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
24793  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
24794  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
24795  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
24796  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
24797  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
24798 /* =======================================================  D1FIFOCTR  ======================================================= */
24799  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
24800  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
24801  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
24802  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
24803  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
24804  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
24805  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
24806  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
24807 /* ========================================================  INTENB0  ======================================================== */
24808  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
24809  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
24810  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
24811  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
24812  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
24813  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
24814  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
24815  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
24816  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
24817  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
24818  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
24819  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
24820  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
24821  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
24822  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
24823  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
24824 /* ========================================================  INTENB1  ======================================================== */
24825  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
24826  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
24827  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
24828  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
24829  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
24830  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
24831  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
24832  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
24833  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
24834  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
24835  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
24836  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
24837  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
24838  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
24839  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
24840  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
24841 /* ========================================================  BRDYENB  ======================================================== */
24842  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
24843  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
24844 /* ========================================================  NRDYENB  ======================================================== */
24845  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
24846  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
24847 /* ========================================================  BEMPENB  ======================================================== */
24848  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
24849  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
24850 /* ========================================================  SOFCFG  ========================================================= */
24851  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
24852  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
24853  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
24854  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
24855  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
24856  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
24857  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
24858  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
24859 /* ========================================================  PHYSET  ========================================================= */
24860  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
24861  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
24862  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
24863  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
24864  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
24865  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
24866  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
24867  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
24868  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
24869  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
24870  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
24871  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
24872  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
24873  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
24874 /* ========================================================  INTSTS0  ======================================================== */
24875  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
24876  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
24877  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
24878  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
24879  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
24880  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
24881  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
24882  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
24883  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
24884  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
24885  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
24886  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
24887  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
24888  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
24889  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
24890  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
24891  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
24892  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
24893  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
24894  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
24895  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
24896  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
24897  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
24898  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
24899 /* ========================================================  INTSTS1  ======================================================== */
24900  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
24901  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
24902  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
24903  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
24904  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
24905  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
24906  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
24907  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
24908  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
24909  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
24910  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
24911  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
24912  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
24913  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
24914  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
24915  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
24916  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
24917  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
24918  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
24919  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
24920 /* ========================================================  BRDYSTS  ======================================================== */
24921  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
24922  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
24923 /* ========================================================  NRDYSTS  ======================================================== */
24924  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
24925  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
24926 /* ========================================================  BEMPSTS  ======================================================== */
24927  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
24928  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
24929 /* ========================================================  FRMNUM  ========================================================= */
24930  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
24931  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
24932  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
24933  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
24934  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
24935  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
24936 /* ========================================================  DVCHGR  ========================================================= */
24937  #define R_USB_FS0_DVCHGR_DVCHG_Pos             (15UL)       /*!< DVCHG (Bit 15)                                        */
24938  #define R_USB_FS0_DVCHGR_DVCHG_Msk             (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
24939 /* ========================================================  USBADDR  ======================================================== */
24940  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
24941  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0xf00UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x0f)                       */
24942  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
24943  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
24944 /* ========================================================  USBREQ  ========================================================= */
24945  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
24946  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
24947  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
24948  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
24949 /* ========================================================  USBVAL  ========================================================= */
24950  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
24951  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
24952 /* ========================================================  USBINDX  ======================================================== */
24953  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
24954  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
24955 /* ========================================================  USBLENG  ======================================================== */
24956  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
24957  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
24958 /* ========================================================  DCPCFG  ========================================================= */
24959  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
24960  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
24961  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
24962  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
24963  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
24964  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
24965 /* ========================================================  DCPMAXP  ======================================================== */
24966  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
24967  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
24968  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
24969  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
24970 /* ========================================================  DCPCTR  ========================================================= */
24971  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
24972  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
24973  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
24974  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
24975  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
24976  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
24977  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
24978  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
24979  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
24980  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
24981  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
24982  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
24983  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
24984  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
24985  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
24986  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
24987  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
24988  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
24989 /* ========================================================  PIPESEL  ======================================================== */
24990  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
24991  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
24992 /* ========================================================  PIPECFG  ======================================================== */
24993  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
24994  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
24995  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
24996  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
24997  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
24998  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
24999  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
25000  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
25001  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
25002  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
25003  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
25004  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
25005 /* =======================================================  PIPEMAXP  ======================================================== */
25006  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
25007  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
25008  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
25009  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
25010 /* =======================================================  PIPEPERI  ======================================================== */
25011  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
25012  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
25013  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
25014  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
25015 /* =======================================================  PIPE_CTR  ======================================================== */
25016  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
25017  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
25018  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
25019  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
25020  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
25021  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
25022  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
25023  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
25024  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
25025  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
25026  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
25027  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
25028  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
25029  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
25030  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
25031  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
25032  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
25033  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
25034  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
25035  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
25036  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
25037  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
25038 /* ========================================================  DEVADD  ========================================================= */
25039  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
25040  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
25041  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
25042  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
25043  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
25044  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
25045 /* ======================================================  USBBCCTRL0  ======================================================= */
25046  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
25047  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
25048  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
25049  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
25050  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
25051  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
25052  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
25053  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
25054  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
25055  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
25056  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
25057  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
25058  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
25059  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
25060  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
25061  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
25062  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
25063  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
25064 /* ========================================================  UCKSEL  ========================================================= */
25065  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
25066  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
25067 /* =========================================================  USBMC  ========================================================= */
25068  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
25069  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
25070  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
25071  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
25072 /* ========================================================  PHYSLEW  ======================================================== */
25073  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
25074  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
25075  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
25076  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
25077  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
25078  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
25079  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
25080  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
25081 /* ========================================================  LPCTRL  ========================================================= */
25082  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
25083  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
25084 /* =========================================================  LPSTS  ========================================================= */
25085  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
25086  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
25087 /* ========================================================  BCCTRL  ========================================================= */
25088  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
25089  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
25090  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
25091  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
25092  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
25093  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
25094  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
25095  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
25096  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
25097  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
25098  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
25099  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
25100  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
25101  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
25102  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
25103  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
25104 /* =======================================================  PL1CTRL1  ======================================================== */
25105  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
25106  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
25107  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
25108  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
25109  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
25110  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
25111  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
25112  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
25113  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
25114  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
25115  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
25116  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
25117 /* =======================================================  PL1CTRL2  ======================================================== */
25118  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
25119  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
25120  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
25121  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
25122 /* =======================================================  HL1CTRL1  ======================================================== */
25123  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
25124  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
25125  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
25126  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
25127 /* =======================================================  HL1CTRL2  ======================================================== */
25128  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
25129  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
25130  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
25131  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
25132  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
25133  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
25134  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
25135  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
25136 /* ========================================================  DPUSR0R  ======================================================== */
25137  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
25138  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
25139  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
25140  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
25141  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
25142  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
25143 /* ========================================================  DPUSR1R  ======================================================== */
25144  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
25145  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
25146  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
25147  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
25148  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
25149  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
25150  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
25151  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
25152  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
25153  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
25154  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
25155  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
25156 /* ========================================================  DPUSR2R  ======================================================== */
25157  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
25158  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
25159  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
25160  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
25161  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
25162  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
25163  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
25164  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
25165  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
25166  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
25167  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
25168  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
25169 /* ========================================================  DPUSRCR  ======================================================== */
25170  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
25171  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
25172  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
25173  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
25174 /* ======================================================  DPUSR0R_FS  ======================================================= */
25175  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
25176  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
25177  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
25178  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
25179  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
25180  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
25181  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
25182  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
25183  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
25184  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
25185  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
25186  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
25187  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
25188  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
25189  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
25190  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
25191  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
25192  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
25193 /* ======================================================  DPUSR1R_FS  ======================================================= */
25194  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
25195  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
25196  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
25197  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
25198  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
25199  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
25200  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
25201  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
25202  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
25203  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
25204  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
25205  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
25206  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
25207  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
25208  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
25209  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
25210  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
25211  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
25212  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
25213  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
25214 
25215 /* =========================================================================================================================== */
25216 /* ================                                         R_UARTA0                                          ================ */
25217 /* =========================================================================================================================== */
25218 
25219 /* =========================================================  TXBAn  ========================================================= */
25220 /* =========================================================  RXBAn  ========================================================= */
25221 /* ========================================================  ASIMAn0  ======================================================== */
25222  #define R_UARTA0_ASIMAn0_ISRMA_Pos    (0UL)    /*!< ISRMA (Bit 0)                                         */
25223  #define R_UARTA0_ASIMAn0_ISRMA_Msk    (0x1UL)  /*!< ISRMA (Bitfield-Mask: 0x01)                           */
25224  #define R_UARTA0_ASIMAn0_ISSMA_Pos    (1UL)    /*!< ISSMA (Bit 1)                                         */
25225  #define R_UARTA0_ASIMAn0_ISSMA_Msk    (0x2UL)  /*!< ISSMA (Bitfield-Mask: 0x01)                           */
25226  #define R_UARTA0_ASIMAn0_RXEA_Pos     (5UL)    /*!< RXEA (Bit 5)                                          */
25227  #define R_UARTA0_ASIMAn0_RXEA_Msk     (0x20UL) /*!< RXEA (Bitfield-Mask: 0x01)                            */
25228  #define R_UARTA0_ASIMAn0_TXEA_Pos     (6UL)    /*!< TXEA (Bit 6)                                          */
25229  #define R_UARTA0_ASIMAn0_TXEA_Msk     (0x40UL) /*!< TXEA (Bitfield-Mask: 0x01)                            */
25230  #define R_UARTA0_ASIMAn0_EN_Pos       (7UL)    /*!< EN (Bit 7)                                            */
25231  #define R_UARTA0_ASIMAn0_EN_Msk       (0x80UL) /*!< EN (Bitfield-Mask: 0x01)                              */
25232 /* ========================================================  ASIMAn1  ======================================================== */
25233  #define R_UARTA0_ASIMAn1_ALV_Pos      (0UL)    /*!< ALV (Bit 0)                                           */
25234  #define R_UARTA0_ASIMAn1_ALV_Msk      (0x1UL)  /*!< ALV (Bitfield-Mask: 0x01)                             */
25235  #define R_UARTA0_ASIMAn1_DIR_Pos      (1UL)    /*!< DIR (Bit 1)                                           */
25236  #define R_UARTA0_ASIMAn1_DIR_Msk      (0x2UL)  /*!< DIR (Bitfield-Mask: 0x01)                             */
25237  #define R_UARTA0_ASIMAn1_SL_Pos       (2UL)    /*!< SL (Bit 2)                                            */
25238  #define R_UARTA0_ASIMAn1_SL_Msk       (0x4UL)  /*!< SL (Bitfield-Mask: 0x01)                              */
25239  #define R_UARTA0_ASIMAn1_CL_Pos       (3UL)    /*!< CL (Bit 3)                                            */
25240  #define R_UARTA0_ASIMAn1_CL_Msk       (0x18UL) /*!< CL (Bitfield-Mask: 0x03)                              */
25241  #define R_UARTA0_ASIMAn1_PS_Pos       (5UL)    /*!< PS (Bit 5)                                            */
25242  #define R_UARTA0_ASIMAn1_PS_Msk       (0x60UL) /*!< PS (Bitfield-Mask: 0x03)                              */
25243 /* ========================================================  BRGCAn  ========================================================= */
25244 /* ========================================================  ASISAn  ========================================================= */
25245  #define R_UARTA0_ASISAn_OVEA_Pos      (0UL)    /*!< OVEA (Bit 0)                                          */
25246  #define R_UARTA0_ASISAn_OVEA_Msk      (0x1UL)  /*!< OVEA (Bitfield-Mask: 0x01)                            */
25247  #define R_UARTA0_ASISAn_FEA_Pos       (1UL)    /*!< FEA (Bit 1)                                           */
25248  #define R_UARTA0_ASISAn_FEA_Msk       (0x2UL)  /*!< FEA (Bitfield-Mask: 0x01)                             */
25249  #define R_UARTA0_ASISAn_PEA_Pos       (2UL)    /*!< PEA (Bit 2)                                           */
25250  #define R_UARTA0_ASISAn_PEA_Msk       (0x4UL)  /*!< PEA (Bitfield-Mask: 0x01)                             */
25251  #define R_UARTA0_ASISAn_TXSFA_Pos     (4UL)    /*!< TXSFA (Bit 4)                                         */
25252  #define R_UARTA0_ASISAn_TXSFA_Msk     (0x10UL) /*!< TXSFA (Bitfield-Mask: 0x01)                           */
25253  #define R_UARTA0_ASISAn_TXBFA_Pos     (5UL)    /*!< TXBFA (Bit 5)                                         */
25254  #define R_UARTA0_ASISAn_TXBFA_Msk     (0x20UL) /*!< TXBFA (Bitfield-Mask: 0x01)                           */
25255 /* ========================================================  ASCTAn  ========================================================= */
25256  #define R_UARTA0_ASCTAn_OVECTA_Pos    (0UL)    /*!< OVECTA (Bit 0)                                        */
25257  #define R_UARTA0_ASCTAn_OVECTA_Msk    (0x1UL)  /*!< OVECTA (Bitfield-Mask: 0x01)                          */
25258  #define R_UARTA0_ASCTAn_FECTA_Pos     (1UL)    /*!< FECTA (Bit 1)                                         */
25259  #define R_UARTA0_ASCTAn_FECTA_Msk     (0x2UL)  /*!< FECTA (Bitfield-Mask: 0x01)                           */
25260  #define R_UARTA0_ASCTAn_PECTA_Pos     (2UL)    /*!< PECTA (Bit 2)                                         */
25261  #define R_UARTA0_ASCTAn_PECTA_Msk     (0x4UL)  /*!< PECTA (Bitfield-Mask: 0x01)                           */
25262 
25263 /* =========================================================================================================================== */
25264 /* ================                                        R_UARTA_CK                                         ================ */
25265 /* =========================================================================================================================== */
25266 
25267 /* ========================================================  UTAnCK  ========================================================= */
25268  #define R_UARTA_CK_UTAnCK_CK_Pos     (0UL)    /*!< CK (Bit 0)                                            */
25269  #define R_UARTA_CK_UTAnCK_CK_Msk     (0xfUL)  /*!< CK (Bitfield-Mask: 0x0f)                              */
25270  #define R_UARTA_CK_UTAnCK_SEL_Pos    (4UL)    /*!< SEL (Bit 4)                                           */
25271  #define R_UARTA_CK_UTAnCK_SEL_Msk    (0x30UL) /*!< SEL (Bitfield-Mask: 0x03)                             */
25272  #define R_UARTA_CK_UTAnCK_EN_Pos     (7UL)    /*!< EN (Bit 7)                                            */
25273  #define R_UARTA_CK_UTAnCK_EN_Msk     (0x80UL) /*!< EN (Bitfield-Mask: 0x01)                              */
25274 
25275 /* =========================================================================================================================== */
25276 /* ================                                           R_WDT                                           ================ */
25277 /* =========================================================================================================================== */
25278 
25279 /* =========================================================  WDTRR  ========================================================= */
25280  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
25281  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
25282 /* =========================================================  WDTCR  ========================================================= */
25283  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
25284  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
25285  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
25286  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
25287  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
25288  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
25289  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
25290  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
25291 /* =========================================================  WDTSR  ========================================================= */
25292  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
25293  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
25294  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
25295  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
25296  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
25297  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
25298 /* ========================================================  WDTRCR  ========================================================= */
25299  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
25300  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
25301 /* =======================================================  WDTCSTPR  ======================================================== */
25302  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
25303  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
25304 
25305 /* =========================================================================================================================== */
25306 /* ================                                           R_TZF                                           ================ */
25307 /* =========================================================================================================================== */
25308 
25309 /* ========================================================  TZFOAD  ========================================================= */
25310  #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
25311  #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
25312  #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
25313  #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25314 /* =========================================================  TZFPT  ========================================================= */
25315  #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
25316  #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
25317  #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
25318  #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
25319 
25320 /* =========================================================================================================================== */
25321 /* ================                                          R_CACHE                                          ================ */
25322 /* =========================================================================================================================== */
25323 
25324 /* ========================================================  CCACTL  ========================================================= */
25325  #define R_CACHE_CCACTL_ENC_Pos     (0UL)    /*!< ENC (Bit 0)                                           */
25326  #define R_CACHE_CCACTL_ENC_Msk     (0x1UL)  /*!< ENC (Bitfield-Mask: 0x01)                             */
25327 /* ========================================================  CCAFCT  ========================================================= */
25328  #define R_CACHE_CCAFCT_FC_Pos      (0UL)    /*!< FC (Bit 0)                                            */
25329  #define R_CACHE_CCAFCT_FC_Msk      (0x1UL)  /*!< FC (Bitfield-Mask: 0x01)                              */
25330 /* ========================================================  CCALCF  ========================================================= */
25331  #define R_CACHE_CCALCF_CC_Pos      (0UL)    /*!< CC (Bit 0)                                            */
25332  #define R_CACHE_CCALCF_CC_Msk      (0x3UL)  /*!< CC (Bitfield-Mask: 0x03)                              */
25333 /* ========================================================  SCACTL  ========================================================= */
25334  #define R_CACHE_SCACTL_ENS_Pos     (0UL)    /*!< ENS (Bit 0)                                           */
25335  #define R_CACHE_SCACTL_ENS_Msk     (0x1UL)  /*!< ENS (Bitfield-Mask: 0x01)                             */
25336 /* ========================================================  SCAFCT  ========================================================= */
25337  #define R_CACHE_SCAFCT_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
25338  #define R_CACHE_SCAFCT_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
25339 /* ========================================================  SCALCF  ========================================================= */
25340  #define R_CACHE_SCALCF_CS_Pos      (0UL)    /*!< CS (Bit 0)                                            */
25341  #define R_CACHE_SCALCF_CS_Msk      (0x3UL)  /*!< CS (Bitfield-Mask: 0x03)                              */
25342 /* ========================================================  CAPOAD  ========================================================= */
25343  #define R_CACHE_CAPOAD_OAD_Pos     (0UL)    /*!< OAD (Bit 0)                                           */
25344  #define R_CACHE_CAPOAD_OAD_Msk     (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
25345 /* ========================================================  CAPRCR  ========================================================= */
25346  #define R_CACHE_CAPRCR_PRCR_Pos    (0UL)    /*!< PRCR (Bit 0)                                          */
25347  #define R_CACHE_CAPRCR_PRCR_Msk    (0x1UL)  /*!< PRCR (Bitfield-Mask: 0x01)                            */
25348  #define R_CACHE_CAPRCR_KW_Pos      (1UL)    /*!< KW (Bit 1)                                            */
25349  #define R_CACHE_CAPRCR_KW_Msk      (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
25350 
25351 /* =========================================================================================================================== */
25352 /* ================                                          R_CPSCU                                          ================ */
25353 /* =========================================================================================================================== */
25354 
25355 /* =========================================================  CSAR  ========================================================== */
25356  #define R_CPSCU_CSAR_CACHESA_Pos              (0UL)          /*!< CACHESA (Bit 0)                                       */
25357  #define R_CPSCU_CSAR_CACHESA_Msk              (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
25358  #define R_CPSCU_CSAR_CACHELSA_Pos             (1UL)          /*!< CACHELSA (Bit 1)                                      */
25359  #define R_CPSCU_CSAR_CACHELSA_Msk             (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
25360  #define R_CPSCU_CSAR_CACHEESA_Pos             (2UL)          /*!< CACHEESA (Bit 2)                                      */
25361  #define R_CPSCU_CSAR_CACHEESA_Msk             (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
25362 /* ========================================================  SRAMSAR  ======================================================== */
25363  #define R_CPSCU_SRAMSAR_SRAMSA0_Pos           (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
25364  #define R_CPSCU_SRAMSAR_SRAMSA0_Msk           (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
25365  #define R_CPSCU_SRAMSAR_SRAMSA1_Pos           (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
25366  #define R_CPSCU_SRAMSAR_SRAMSA1_Msk           (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
25367  #define R_CPSCU_SRAMSAR_SRAMSA2_Pos           (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
25368  #define R_CPSCU_SRAMSAR_SRAMSA2_Msk           (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
25369 /* =======================================================  STBRAMSAR  ======================================================= */
25370  #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos         (0UL)          /*!< NSBSTBR (Bit 0)                                       */
25371  #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk         (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
25372 /* ========================================================  DTCSAR  ========================================================= */
25373  #define R_CPSCU_DTCSAR_DTCSTSA_Pos            (0UL)          /*!< DTCSTSA (Bit 0)                                       */
25374  #define R_CPSCU_DTCSAR_DTCSTSA_Msk            (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
25375 /* ========================================================  DMACSAR  ======================================================== */
25376  #define R_CPSCU_DMACSAR_DMASTSA_Pos           (0UL)          /*!< DMASTSA (Bit 0)                                       */
25377  #define R_CPSCU_DMACSAR_DMASTSA_Msk           (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
25378 /* ========================================================  ICUSARA  ======================================================== */
25379  #define R_CPSCU_ICUSARA_SAIRQCRn_Pos          (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
25380  #define R_CPSCU_ICUSARA_SAIRQCRn_Msk          (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
25381 /* ========================================================  ICUSARB  ======================================================== */
25382  #define R_CPSCU_ICUSARB_SANMI_Pos             (0UL)          /*!< SANMI (Bit 0)                                         */
25383  #define R_CPSCU_ICUSARB_SANMI_Msk             (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
25384 /* ========================================================  ICUSARC  ======================================================== */
25385  #define R_CPSCU_ICUSARC_SADMACn_Pos           (0UL)          /*!< SADMACn (Bit 0)                                       */
25386  #define R_CPSCU_ICUSARC_SADMACn_Msk           (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
25387 /* ========================================================  ICUSARD  ======================================================== */
25388  #define R_CPSCU_ICUSARD_SASELSR0_Pos          (0UL)          /*!< SASELSR0 (Bit 0)                                      */
25389  #define R_CPSCU_ICUSARD_SASELSR0_Msk          (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
25390 /* ========================================================  ICUSARE  ======================================================== */
25391  #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos         (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
25392  #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk         (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
25393  #define R_CPSCU_ICUSARE_SALVD1WUP_Pos         (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
25394  #define R_CPSCU_ICUSARE_SALVD1WUP_Msk         (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
25395  #define R_CPSCU_ICUSARE_SALVD2WUP_Pos         (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
25396  #define R_CPSCU_ICUSARE_SALVD2WUP_Msk         (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
25397  #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos        (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
25398  #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk        (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
25399  #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos      (23UL)         /*!< SAACMPLP0WUP (Bit 23)                                 */
25400  #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk      (0x800000UL)   /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01)                    */
25401  #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos       (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
25402  #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk       (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
25403  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos       (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
25404  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk       (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
25405  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos       (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
25406  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk       (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
25407  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos       (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
25408  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk       (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
25409  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos       (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
25410  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk       (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
25411  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos       (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
25412  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk       (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
25413  #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos         (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
25414  #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk         (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
25415 /* ========================================================  ICUSARF  ======================================================== */
25416  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos       (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
25417  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk       (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
25418  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos       (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
25419  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk       (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
25420  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos       (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
25421  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk       (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
25422  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos      (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
25423  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk      (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
25424  #define R_CPSCU_ICUSARF_SASOSCWUP_Pos         (7UL)          /*!< SASOSCWUP (Bit 7)                                     */
25425  #define R_CPSCU_ICUSARF_SASOSCWUP_Msk         (0x80UL)       /*!< SASOSCWUP (Bitfield-Mask: 0x01)                       */
25426  #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos        (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
25427  #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk        (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
25428  #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos        (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
25429  #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk        (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
25430  #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos        (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
25431  #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk        (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
25432  #define R_CPSCU_ICUSARF_SAI3CWUP_Pos          (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
25433  #define R_CPSCU_ICUSARF_SAI3CWUP_Msk          (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
25434  #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos        (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
25435  #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk        (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
25436  #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos        (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
25437  #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk        (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
25438  #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos        (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
25439  #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk        (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
25440 /* ========================================================  ICUSARG  ======================================================== */
25441  #define R_CPSCU_ICUSARG_SAIELSRn_Pos          (0UL)          /*!< SAIELSRn (Bit 0)                                      */
25442  #define R_CPSCU_ICUSARG_SAIELSRn_Msk          (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
25443 /* ========================================================  ICUSARH  ======================================================== */
25444  #define R_CPSCU_ICUSARH_SAIELSRn_Pos          (0UL)          /*!< SAIELSRn (Bit 0)                                      */
25445  #define R_CPSCU_ICUSARH_SAIELSRn_Msk          (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
25446 /* ========================================================  ICUSARI  ======================================================== */
25447  #define R_CPSCU_ICUSARI_SAIELSRn_Pos          (0UL)          /*!< SAIELSRn (Bit 0)                                      */
25448  #define R_CPSCU_ICUSARI_SAIELSRn_Msk          (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
25449 /* ========================================================  ICUSARM  ======================================================== */
25450  #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos       (0UL)          /*!< SAINTUR0WUP (Bit 0)                                   */
25451  #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk       (0x1UL)        /*!< SAINTUR0WUP (Bitfield-Mask: 0x01)                     */
25452  #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos      (1UL)          /*!< SAINTURE0WUP (Bit 1)                                  */
25453  #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk      (0x2UL)        /*!< SAINTURE0WUP (Bitfield-Mask: 0x01)                    */
25454  #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos       (2UL)          /*!< SAINTUR1WUP (Bit 2)                                   */
25455  #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk       (0x4UL)        /*!< SAINTUR1WUP (Bitfield-Mask: 0x01)                     */
25456  #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos      (3UL)          /*!< SAINTURE1WUP (Bit 3)                                  */
25457  #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk      (0x8UL)        /*!< SAINTURE1WUP (Bitfield-Mask: 0x01)                    */
25458  #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos    (4UL)          /*!< SAEXLVDVBATWUP (Bit 4)                                */
25459  #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk    (0x10UL)       /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01)                  */
25460  #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos      (5UL)          /*!< SALVDVRTCWUP (Bit 5)                                  */
25461  #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk      (0x20UL)       /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01)                    */
25462  #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos        (6UL)          /*!< SAEXLVDWUP (Bit 6)                                    */
25463  #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk        (0x40UL)       /*!< SAEXLVDWUP (Bitfield-Mask: 0x01)                      */
25464 /* ========================================================  BUSSARA  ======================================================== */
25465  #define R_CPSCU_BUSSARA_BUSSA0_Pos            (0UL)          /*!< BUSSA0 (Bit 0)                                        */
25466  #define R_CPSCU_BUSSARA_BUSSA0_Msk            (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
25467 /* ========================================================  BUSSARB  ======================================================== */
25468  #define R_CPSCU_BUSSARB_BUSSB0_Pos            (0UL)          /*!< BUSSB0 (Bit 0)                                        */
25469  #define R_CPSCU_BUSSARB_BUSSB0_Msk            (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
25470 /* ========================================================  BUSSARC  ======================================================== */
25471  #define R_CPSCU_BUSSARC_BUSSC0_Pos            (0UL)          /*!< BUSSC0 (Bit 0)                                        */
25472  #define R_CPSCU_BUSSARC_BUSSC0_Msk            (0x1UL)        /*!< BUSSC0 (Bitfield-Mask: 0x01)                          */
25473 /* ========================================================  BUSPARC  ======================================================== */
25474  #define R_CPSCU_BUSPARC_BUSPA0_Pos            (0UL)          /*!< BUSPA0 (Bit 0)                                        */
25475  #define R_CPSCU_BUSPARC_BUSPA0_Msk            (0x1UL)        /*!< BUSPA0 (Bitfield-Mask: 0x01)                          */
25476 /* =======================================================  MMPUSARA  ======================================================== */
25477  #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos         (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
25478  #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk         (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
25479 /* =======================================================  MMPUSARB  ======================================================== */
25480  #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos         (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
25481  #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk         (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
25482 /* ========================================================  TZFSAR  ========================================================= */
25483  #define R_CPSCU_TZFSAR_TZFSA0_Pos             (0UL)          /*!< TZFSA0 (Bit 0)                                        */
25484  #define R_CPSCU_TZFSAR_TZFSA0_Msk             (0x1UL)        /*!< TZFSA0 (Bitfield-Mask: 0x01)                          */
25485 /* =======================================================  DEBUGSAR  ======================================================== */
25486  #define R_CPSCU_DEBUGSAR_DBGSA0_Pos           (0UL)          /*!< DBGSA0 (Bit 0)                                        */
25487  #define R_CPSCU_DEBUGSAR_DBGSA0_Msk           (0x1UL)        /*!< DBGSA0 (Bitfield-Mask: 0x01)                          */
25488 /* =======================================================  DMACCHSAR  ======================================================= */
25489  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos      (0UL)          /*!< DMACCHSARn (Bit 0)                                    */
25490  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk      (0xffUL)       /*!< DMACCHSARn (Bitfield-Mask: 0xff)                      */
25491 /* ========================================================  CPUDSAR  ======================================================== */
25492  #define R_CPSCU_CPUDSAR_CPUDSA0_Pos           (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
25493  #define R_CPSCU_CPUDSAR_CPUDSA0_Msk           (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
25494 /* ======================================================  SRAMSABAR0  ======================================================= */
25495  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos      (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
25496  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk      (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
25497 /* ======================================================  SRAMSABAR1  ======================================================= */
25498  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos      (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
25499  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk      (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
25500 /* ========================================================  TEVTRCR  ======================================================== */
25501  #define R_CPSCU_TEVTRCR_TEVTE_Pos             (0UL)          /*!< TEVTE (Bit 0)                                         */
25502  #define R_CPSCU_TEVTRCR_TEVTE_Msk             (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
25503 
25504 /* =========================================================================================================================== */
25505 /* ================                                          R_DOC_B                                          ================ */
25506 /* =========================================================================================================================== */
25507 
25508 /* =========================================================  DOCR  ========================================================== */
25509  #define R_DOC_B_DOCR_OMS_Pos         (0UL)    /*!< OMS (Bit 0)                                           */
25510  #define R_DOC_B_DOCR_OMS_Msk         (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
25511  #define R_DOC_B_DOCR_DOBW_Pos        (3UL)    /*!< DOBW (Bit 3)                                          */
25512  #define R_DOC_B_DOCR_DOBW_Msk        (0x8UL)  /*!< DOBW (Bitfield-Mask: 0x01)                            */
25513  #define R_DOC_B_DOCR_DCSEL_Pos       (4UL)    /*!< DCSEL (Bit 4)                                         */
25514  #define R_DOC_B_DOCR_DCSEL_Msk       (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07)                           */
25515 /* =========================================================  DOSR  ========================================================== */
25516  #define R_DOC_B_DOSR_DOPCF_Pos       (0UL)    /*!< DOPCF (Bit 0)                                         */
25517  #define R_DOC_B_DOSR_DOPCF_Msk       (0x1UL)  /*!< DOPCF (Bitfield-Mask: 0x01)                           */
25518 /* =========================================================  DOSCR  ========================================================= */
25519  #define R_DOC_B_DOSCR_DOPCFCL_Pos    (0UL)    /*!< DOPCFCL (Bit 0)                                       */
25520  #define R_DOC_B_DOSCR_DOPCFCL_Msk    (0x1UL)  /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
25521 /* =========================================================  DODIR  ========================================================= */
25522 /* ========================================================  DODSR0  ========================================================= */
25523 /* ========================================================  DODSR1  ========================================================= */
25524 
25525 /* =========================================================================================================================== */
25526 /* ================                                          R_AGTX0                                          ================ */
25527 /* =========================================================================================================================== */
25528 
25529 /** @} */ /* End of group PosMask_peripherals */
25530 
25531  #ifdef __cplusplus
25532 }
25533  #endif
25534 
25535 #endif                                 /* R7FA4L1BD_H */
25536 
25537 /** @} */ /* End of group R7FA4L1BD */
25538 
25539 /** @} */ /* End of group Renesas Electronics Corporation */
25540